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Thu, 13 Jan 2022 13:31:05 +0000 From: Akhil R To: , , , , , , , , , CC: Subject: [PATCH 2/6] dt-bindings: i2c: tegra: Add Tegra234 details Date: Thu, 13 Jan 2022 19:00:19 +0530 Message-ID: <1642080623-15980-3-git-send-email-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1642080623-15980-1-git-send-email-akhilrajeev@nvidia.com> References: <1642080623-15980-1-git-send-email-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f7697f11-3533-4b90-bedb-08d9d698f65c X-MS-TrafficTypeDiagnostic: DM5PR12MB1851:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4303; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9YilOuxW8MdGEZb+SHCZf6unoEbHN7kdlt4/abOK+afg8Taklb5ZqmhifCf6URiDF13QIu5Ua0APXQ9W6BSJ2pzpcuZmKKCmrwcD9+KOe5Yuy6VMCF3FqRqTNFE4i5OJMtns9+crupQTiksnmHTBw0YkYHmNdFmmlz0zaPL06tRRTqh3kgm7WxCB6AlAMJIL4idF1jkz2sF1U/vJWRBnolZryE5eu9sKraCKLHDl5/XGrsINNv7OYYPqgfCwWvSYRuthJ2FLhTeur2/53nWoArCvJsx/jnDaB2YQOC96NGgVc/NyCfTBVaS/YRoR+pLhHiKMDTMm+6clryWm/+BhewhMEgp1GUqt6J/uB8Wf2RhFjKclacHo2Q4PFYC+g0Fx/oq3odjAJRlAU+iZHmW0eAXjP/aq/ekdrvnlB7Sl8Tjbb7n5zG/WNmyDkLJrPghXX/ghEViOsu1BQPf5Pk2wld3a7+Vh4UyFpg1OwAksP9tsFxdbXhc6b97Fuy9jGiA8xx7+nDjZcbEBqQWQKUBcoPAg7UioQW95aydWwlRlYlJLRWrWDcXdpwEHZaPmfLVcyS3Gm2wu4IDmJ5LYMmkm1dA1wLsHChExv7OTEBGS/gn3oeheSips7SpI4UanBYBYyvBIRHBqAQN8aKJICmPhmrwP2AZDiRUWJIU+H89AmI79Jj5UhLFzptLaNTrNCDx3IBFMWwS8yern4vx1x3efw2qb4H5OELBaYo4vK7OKun/lGaWzNJv7rcRE/2U7MPqJ8w6YWGyLA0OBDaYRAlfN24xAhi8a05P5nqeY0gO1zRIR91TfWMpm48H/LK6JcSI7 X-Forefront-Antispam-Report: CIP:12.22.5.238; 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Signed-off-by: Akhil R --- Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml index 424a4fc..c58e256 100644 --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml @@ -80,6 +80,11 @@ properties: support for 64 KiB transactions whereas earlier chips supported no more than 4 KiB per transactions. const: nvidia,tegra194-i2c + - description: | + Tegra234 has 8 generic I2C controllers, two of which are in the AON + (always-on) partition of the SoC. All of these controllers are + similar to those found on Tegra194. + const: nvidia,tegra234-i2c reg: maxItems: 1 From patchwork Thu Jan 13 13:30:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil R X-Patchwork-Id: 531842 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FDF7C433FE for ; Thu, 13 Jan 2022 13:31:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235219AbiAMNbY (ORCPT ); Thu, 13 Jan 2022 08:31:24 -0500 Received: from mail-mw2nam10on2050.outbound.protection.outlook.com ([40.107.94.50]:40545 "EHLO NAM10-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S235203AbiAMNbY (ORCPT ); Thu, 13 Jan 2022 08:31:24 -0500 ARC-Seal: i=1; a=rsa-sha256; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(36840700001)(40470700002)(46966006)(81166007)(921005)(6666004)(508600001)(36756003)(82310400004)(83380400001)(5660300002)(110136005)(7696005)(356005)(316002)(40460700001)(8936002)(186003)(86362001)(107886003)(4326008)(2616005)(70586007)(8676002)(426003)(70206006)(2906002)(26005)(47076005)(36860700001)(336012)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2022 13:31:22.1664 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 60c67bfa-9a0a-483f-2e91-08d9d698fd55 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1563 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add device tree nodes for Tegra234 I2C controllers Signed-off-by: Akhil R --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 121 +++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 6b6f1580..51aff7d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -144,6 +144,96 @@ status = "disabled"; }; + gen1_i2c: i2c@3160000 { + compatible = "nvidia,tegra234-i2c"; + reg = <0x3160000 0x100>; + status = "disabled"; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C1 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C1>; + reset-names = "i2c"; + }; + + cam_i2c: i2c@3180000 { + compatible = "nvidia,tegra234-i2c"; + reg = <0x3180000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C3 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C3>; + reset-names = "i2c"; + }; + + dp_aux_ch1_i2c: i2c@3190000 { + compatible = "nvidia,tegra234-i2c"; + reg = <0x3190000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C4 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C4>; + reset-names = "i2c"; + }; + + dp_aux_ch0_i2c: i2c@31b0000 { + compatible = "nvidia,tegra234-i2c"; + reg = <0x31b0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C6 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C6>; + reset-names = "i2c"; + }; + + dp_aux_ch2_i2c: i2c@31c0000 { + compatible = "nvidia,tegra234-i2c"; + reg = <0x31c0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C7 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C7>; + reset-names = "i2c"; + }; + + dp_aux_ch3_i2c: i2c@31e0000 { + compatible = "nvidia,tegra234-i2c"; + reg = <0x31e0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C9 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C9>; + reset-names = "i2c"; + }; + mmc@3460000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x20000>; @@ -212,6 +302,37 @@ #mbox-cells = <2>; }; + gen2_i2c: i2c@c240000 { + compatible = "nvidia,tegra234-i2c"; + reg = <0xc240000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C2 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_I2C2>; + reset-names = "i2c"; + }; + + gen8_i2c: i2c@c250000 { + compatible = "nvidia,tegra234-i2c"; + reg = <0xc250000 0x100>; + nvidia,hw-instance-id = <0x7>; + interrupts = ; + status = "disabled"; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C8 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_I2C8>; + reset-names = "i2c"; + }; + rtc@c2a0000 { compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; reg = <0x0c2a0000 0x10000>; From patchwork Thu Jan 13 13:30:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil R X-Patchwork-Id: 531841 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63E95C433FE for ; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(40470700002)(46966006)(36840700001)(47076005)(426003)(186003)(81166007)(356005)(83380400001)(921005)(2616005)(508600001)(8676002)(7696005)(5660300002)(26005)(70586007)(70206006)(316002)(110136005)(8936002)(336012)(36756003)(36860700001)(40460700001)(82310400004)(2906002)(107886003)(86362001)(4326008)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2022 13:31:28.6112 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 580043cd-26b2-4672-f4ee-08d9d699012e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3263 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add dt-bindings header files for PWM of Tegra234 Signed-off-by: Akhil R --- include/dt-bindings/clock/tegra234-clock.h | 17 +++++++++++++++++ include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++ 2 files changed, 25 insertions(+) diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 5d05c19..9d17309 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -50,4 +50,21 @@ /** @brief PLLP clk output */ #define TEGRA234_CLK_PLLP_OUT0 102U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ +#define TEGRA234_CLK_PWM1 105U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ +#define TEGRA234_CLK_PWM2 106U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ +#define TEGRA234_CLK_PWM3 107U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ +#define TEGRA234_CLK_PWM4 108U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ +#define TEGRA234_CLK_PWM5 109U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ +#define TEGRA234_CLK_PWM6 110U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ +#define TEGRA234_CLK_PWM7 111U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ +#define TEGRA234_CLK_PWM8 112U + #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index e07e898..288524f 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -20,6 +20,14 @@ #define TEGRA234_RESET_I2C7 33U #define TEGRA234_RESET_I2C8 34U #define TEGRA234_RESET_I2C9 35U +#define TEGRA234_RESET_PWM1 68U +#define TEGRA234_RESET_PWM2 69U +#define TEGRA234_RESET_PWM3 70U +#define TEGRA234_RESET_PWM4 71U +#define TEGRA234_RESET_PWM5 72U +#define TEGRA234_RESET_PWM6 73U +#define TEGRA234_RESET_PWM7 74U +#define TEGRA234_RESET_PWM8 75U /** @} */