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Mon, 10 Jan 2022 19:37:02 +0000 From: Robert Hancock To: linux-usb@vger.kernel.org Cc: Thinh.Nguyen@synopsys.com, robh+dt@kernel.org, devicetree@vger.kernel.org, michal.simek@xilinx.com, balbi@kernel.org, gregkh@linuxfoundation.org, mounika.grace.akula@xilinx.com, manish.narani@xilinx.com, Robert Hancock Subject: [PATCH v2 1/5] usb: dwc3: xilinx: Fix PIPE clock selection for USB2.0 mode Date: Mon, 10 Jan 2022 13:36:37 -0600 Message-Id: <20220110193641.1368350-2-robert.hancock@calian.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220110193641.1368350-1-robert.hancock@calian.com> References: <20220110193641.1368350-1-robert.hancock@calian.com> X-ClientProxiedBy: MWHPR12CA0025.namprd12.prod.outlook.com (2603:10b6:301:2::11) To YT2PR01MB6270.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:4d::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 38e06f63-c275-4bbb-1a31-08d9d4709318 X-MS-TrafficTypeDiagnostic: YTOPR0101MB2236:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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Fix to set the correct value depending on whether a USB3 PHY is present. Fixes: 84770f028fab ("usb: dwc3: Add driver for Xilinx platforms") Signed-off-by: Robert Hancock --- drivers/usb/dwc3/dwc3-xilinx.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c index 9cc3ad701a29..3bc035376394 100644 --- a/drivers/usb/dwc3/dwc3-xilinx.c +++ b/drivers/usb/dwc3/dwc3-xilinx.c @@ -167,8 +167,11 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data) /* Set PIPE Power Present signal in FPD Power Present Register*/ writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSNT); - /* Set the PIPE Clock Select bit in FPD PIPE Clock register */ - writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK); + /* Set the PIPE Clock Select bit in FPD PIPE Clock register if a USB3 + * PHY is in use, deselect otherwise + */ + writel(usb3_phy ? PIPE_CLK_SELECT : PIPE_CLK_DESELECT, + priv_data->regs + XLNX_USB_FPD_PIPE_CLK); ret = reset_control_deassert(crst); if (ret < 0) { From patchwork Mon Jan 10 19:36:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hancock X-Patchwork-Id: 531081 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E05A2C433EF for ; Mon, 10 Jan 2022 19:37:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243603AbiAJThQ (ORCPT ); Mon, 10 Jan 2022 14:37:16 -0500 Received: from mx0d-0054df01.pphosted.com ([67.231.150.19]:44601 "EHLO mx0d-0054df01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241122AbiAJThP (ORCPT ); Mon, 10 Jan 2022 14:37:15 -0500 Received: from pps.filterd (m0209000.ppops.net [127.0.0.1]) by mx0c-0054df01.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20AI5sEQ001635; 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Signed-off-by: Robert Hancock --- Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml index 25ac2c93dc6c..88d8d831e04a 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml @@ -260,6 +260,18 @@ properties: minimum: 1 maximum: 0x3ff + snps,ref-clock-fladj: + description: + Value for GFLADJ_REFCLK_FLADJ field of GFLADJ register for the + fractional portion of the reference clock period in nanoseconds, + when the hardware set default does not match the actual + clock. Calculated via + ((125000/ref_clk_period_integer)-(125000/ref_clk_period)) * ref_clk_period + where ref_clk_period_integer is the period specified in GUCTL_REFCLKPER and + ref_clk_period is the period including fractional value. + minimum: 0 + maximum: 124999 + snps,rx-thr-num-pkt-prd: description: Periodic ESS RX packet threshold count (host mode only). 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Mon, 10 Jan 2022 19:37:06 +0000 From: Robert Hancock To: linux-usb@vger.kernel.org Cc: Thinh.Nguyen@synopsys.com, robh+dt@kernel.org, devicetree@vger.kernel.org, michal.simek@xilinx.com, balbi@kernel.org, gregkh@linuxfoundation.org, mounika.grace.akula@xilinx.com, manish.narani@xilinx.com, Robert Hancock Subject: [PATCH v2 4/5] usb: dwc3: add reference clock FLADJ configuration Date: Mon, 10 Jan 2022 13:36:40 -0600 Message-Id: <20220110193641.1368350-5-robert.hancock@calian.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220110193641.1368350-1-robert.hancock@calian.com> References: <20220110193641.1368350-1-robert.hancock@calian.com> X-ClientProxiedBy: MWHPR12CA0025.namprd12.prod.outlook.com (2603:10b6:301:2::11) To YT2PR01MB6270.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:4d::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e6d9e98d-97cb-430f-5b5a-08d9d47095d5 X-MS-TrafficTypeDiagnostic: YTOPR0101MB2236:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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However, there is another register field, GFLADJ_REFCLK_FLADJ, which reflects the fractional nanosecond portion of the reference clock period. Add a snps,ref-clock-fladj property to allow configuring this as well. On the Xilinx ZynqMP platform, the reference clock appears to always be 20 MHz, giving a clock period of 50 ns. However, the default value of GFLADJ_REFCLK_FLADJ was 1008 rather than 0 as it should have been, which prevented many USB devices from functioning properly. The psu_init code run by the Xilinx first-stage boot loader sets this value to 0, however when the controller is reset by the dwc3-xilinx layer, the incorrect default value is restored. This configuration property allows ensuring that the correct value is always used. Signed-off-by: Robert Hancock --- drivers/usb/dwc3/core.c | 35 +++++++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 3 +++ 2 files changed, 38 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index f4c09951b517..ea11fd1e3b42 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -359,6 +359,37 @@ static void dwc3_ref_clk_period(struct dwc3 *dwc) } +/** + * dwc3_ref_clk_fladj - Reference clock period adjustment configuration + * GFLADJ_REFCLK_FLADJ should be set based on the fractional portion of the + * reference clock period, where the integer portion is set in GUCTL_REFCLKPER. + * Calculated as: ((125000/ref_clk_period_integer)-(125000/ref_clk_period)) * ref_clk_period + * where ref_clk_period_integer is the period specified in GUCTL_REFCLKPER and + * ref_clk_period is the period including fractional value. + * This value can be specified in the device tree if the default value is incorrect. + * Note that 0 is a valid value. + * + * @dwc3: Pointer to our controller context structure + */ +static void dwc3_ref_clk_fladj(struct dwc3 *dwc) +{ + u32 reg; + u32 reg_new; + + if (DWC3_VER_IS_PRIOR(DWC3, 250A)) + return; + + if (!dwc->ref_clk_fladj_set) + return; + + reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); + reg_new = reg & ~DWC3_GFLADJ_REFCLK_FLADJ_MASK; + reg_new |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, dwc->ref_clk_fladj); + if (reg_new != reg) + dwc3_writel(dwc->regs, DWC3_GFLADJ, reg_new); +} + + /** * dwc3_free_one_event_buffer - Frees one event buffer * @dwc: Pointer to our controller context structure @@ -1033,6 +1064,7 @@ static int dwc3_core_init(struct dwc3 *dwc) /* Adjust Reference Clock Period */ dwc3_ref_clk_period(dwc); + dwc3_ref_clk_fladj(dwc); dwc3_set_incr_burst_type(dwc); @@ -1418,6 +1450,9 @@ static void dwc3_get_properties(struct dwc3 *dwc) &dwc->fladj); device_property_read_u32(dev, "snps,ref-clock-period-ns", &dwc->ref_clk_per); + if (!device_property_read_u32(dev, "snps,ref-clock-fladj", + &dwc->ref_clk_fladj)) + dwc->ref_clk_fladj_set = true; dwc->dis_metastability_quirk = device_property_read_bool(dev, "snps,dis_metastability_quirk"); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index e1cc3f7398fb..650d4c2e7a67 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -388,6 +388,7 @@ /* Global Frame Length Adjustment Register */ #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7) #define DWC3_GFLADJ_30MHZ_MASK 0x3f +#define DWC3_GFLADJ_REFCLK_FLADJ_MASK 0x3fff00 /* Global User Control Register*/ #define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000 @@ -1166,6 +1167,8 @@ struct dwc3 { u32 fladj; u32 ref_clk_per; + bool ref_clk_fladj_set; + u32 ref_clk_fladj; u32 irq_gadget; u32 otg_irq; u32 current_otg_role;