From patchwork Sun Jan 9 14:54:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 530865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31639C43217 for ; Sun, 9 Jan 2022 14:55:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235828AbiAIOzA (ORCPT ); Sun, 9 Jan 2022 09:55:00 -0500 Received: from polaris.svanheule.net ([84.16.241.116]:58410 "EHLO polaris.svanheule.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235812AbiAIOyt (ORCPT ); Sun, 9 Jan 2022 09:54:49 -0500 Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:eafe:c901:f20a:f473:2021:45ec]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 2560428EE25; Sun, 9 Jan 2022 15:54:48 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1641740088; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RffKHmKHsI7Q9f2s/yP75xd+8RX8KcPe5WgjwZP779I=; b=aKgdGywvdtYQ6FBsFA4JvMJvNVApTc4rSA2eBojxZ2pcV7+6nAwHVHADx4BHn8DzlhlE4x ixARic/881aM4Cv9fxrP0at6s9USJwwDL17VFFgoW5Bqh0MD2H2/JWp3OM9m2NuQ4jM31J WVpIc5HZftR7ipi+mVpcPTsEQCydhviQzH9QXPy3fJGpB6Q3AcgzcGQLnCWoF8dye8raqh OVj6arnw2a0+XDe80LZZsIIa/tSPV2bWbkUI0NmrrQxx9aeY0dEGZg5T+y10hmUPrHa8eb AmPBz+Mzj4HFWQOqtMcL0jseXCIMu8S5su9kZ18IB+kwh1B4gxVLVQGHeuii4A== From: Sander Vanheule To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Thomas Gleixner , Marc Zyngier , Rob Herring , Birger Koblitz , Bert Vermeulen , John Crispin , Sander Vanheule Subject: [PATCH v3 2/6] irqchip/realtek-rtl: fix off-by-one in routing Date: Sun, 9 Jan 2022 15:54:33 +0100 Message-Id: <177b920aa8d8610615692d0e657e509f363c85ca.1641739718.git.sander@svanheule.net> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There is an offset between routing values (1..6) and the connected MIPS CPU interrupts (2..7), but no distinction was made between these two values. This issue was previously hidden during testing, because an interrupt mapping was used where for each required interrupt another (unused) routing was configured, with an offset of +1. Offset the CPU IRQ numbers by -1 to retrieve the correct routing value. Fixes: 9f3a0f34b84a ("irqchip: Add support for Realtek RTL838x/RTL839x interrupt controller") Signed-off-by: Sander Vanheule --- drivers/irqchip/irq-realtek-rtl.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-realtek-rtl.c b/drivers/irqchip/irq-realtek-rtl.c index d6788dd93c7b..568614edd88f 100644 --- a/drivers/irqchip/irq-realtek-rtl.c +++ b/drivers/irqchip/irq-realtek-rtl.c @@ -95,7 +95,8 @@ static void realtek_irq_dispatch(struct irq_desc *desc) * SoC interrupts are cascaded to MIPS CPU interrupts according to the * interrupt-map in the device tree. Each SoC interrupt gets 4 bits for * the CPU interrupt in an Interrupt Routing Register. Max 32 SoC interrupts - * thus go into 4 IRRs. + * thus go into 4 IRRs. A routing value of '0' means the interrupt is left + * disconnected. Routing values {1..15} connect to output lines {0..14}. */ static int __init map_interrupts(struct device_node *node, struct irq_domain *domain) { @@ -134,7 +135,7 @@ static int __init map_interrupts(struct device_node *node, struct irq_domain *do of_node_put(cpu_ictl); cpu_int = be32_to_cpup(imap + 2); - if (cpu_int > 7) + if (cpu_int > 7 || cpu_int < 2) return -EINVAL; if (!(mips_irqs_set & BIT(cpu_int))) { @@ -143,7 +144,8 @@ static int __init map_interrupts(struct device_node *node, struct irq_domain *do mips_irqs_set |= BIT(cpu_int); } - regs[(soc_int * 4) / 32] |= cpu_int << (soc_int * 4) % 32; + /* Use routing values (1..6) for CPU interrupts (2..7) */ + regs[(soc_int * 4) / 32] |= (cpu_int - 1) << (soc_int * 4) % 32; imap += 3; } From patchwork Sun Jan 9 14:54:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 530863 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FFCBC433F5 for ; Sun, 9 Jan 2022 14:56:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231409AbiAIO4h (ORCPT ); Sun, 9 Jan 2022 09:56:37 -0500 Received: from polaris.svanheule.net ([84.16.241.116]:58452 "EHLO polaris.svanheule.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235826AbiAIOyw (ORCPT ); Sun, 9 Jan 2022 09:54:52 -0500 Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:eafe:c901:f20a:f473:2021:45ec]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 9228D28EE27; Sun, 9 Jan 2022 15:54:50 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1641740090; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=beZnfvFxhflj3F7p8ZPExQMiCmn9XP8LYTsb7UPPuYY=; b=9oi5iDvP9y4yoaaAFVqtN9IaqAU5QqaJIx4rmg4fvLLafSFvWb6xw8U33tiKSuS1/3zvtu +whVWDidFWCFRyeNkWaUY5fjAQ94eG6QZu2XSbO+vazb3AOrceCllgp/ZFVMd0ap1kfKhG 9oDZVjsUZoJv8SNrKLYDSI6pRUp4e4PXAylrBgXaqqTSAQ5hSvs6LbHDHU6X/p0tqrIhyy SFNS6st/+/+dtlu3xompXdqC2p1yCxg4AP66G1/VLU5z/8VCHe/TGFSqlVf7cR3XELFdr/ lcvp6TYBgNEtHyUGPS/Rw1ncig3YNINBYt3SaQxW0sSHc0u2mjdtuYOKX9Cxlg== From: Sander Vanheule To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Thomas Gleixner , Marc Zyngier , Rob Herring , Birger Koblitz , Bert Vermeulen , John Crispin , Sander Vanheule Subject: [PATCH v3 4/6] dt-bindings: interrupt-controller: realtek,rtl-intc: require parents Date: Sun, 9 Jan 2022 15:54:35 +0100 Message-Id: X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The interrupt router has 32 inputs and up to 15 outputs, and the way these are mapped to each other is runtime configurable. The outputs of this interrupt router on the other hand, are connected to a fixed set of parent interrupts. This means that "interrupt-map" is inappropriate, and rather a list of parent interrupts should be specified. Two-part compatibles are introduced to be able to require "interrupts" for new devicetrees. The relevant descriptions are extended or added to more clearly describe the inputs and outputs of this router. The old compatible, "interrupt-map" and "#address-cells", is deprecated. Interrupt specifiers for new compatibles will require two cells, to indicate the output selection. To prevent spurious changes when more SoCs are added, "allOf" is used with one "if", and the compatible enum only has one item. The example is updated to provide a correct example for RTL8380 SoCs. Signed-off-by: Sander Vanheule --- .../realtek,rtl-intc.yaml | 78 ++++++++++++++----- 1 file changed, 58 insertions(+), 20 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml index 9e76fff20323..aab8d44010af 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml @@ -6,6 +6,10 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Realtek RTL SoC interrupt controller devicetree bindings +description: + Interrupt router for Realtek MIPS SoCs, allowing each SoC interrupt to be + routed to one parent interrupt, or left disconnected. + maintainers: - Birger Koblitz - Bert Vermeulen @@ -13,45 +17,79 @@ maintainers: properties: compatible: - const: realtek,rtl-intc + oneOf: + - items: + - enum: + - realtek,rtl8380-intc + - const: realtek,rtl-intc + - const: realtek,rtl-intc + deprecated: true - "#interrupt-cells": - const: 1 + "#interrupt-cells": true reg: maxItems: 1 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 15 + description: + List of parent interrupts, in the order that they are connected to this + interrupt router's outputs. interrupt-controller: true - "#address-cells": - const: 0 - - interrupt-map: - description: Describes mapping from SoC interrupts to CPU interrupts - required: - compatible - reg - "#interrupt-cells" - interrupt-controller - - "#address-cells" - - interrupt-map + +allOf: + - if: + properties: + compatible: + const: realtek,rtl-intc + then: + properties: + "#interrupt-cells": + const: 1 + + "#address-cells": + const: 0 + + interrupt-map: true + required: + - "#address-cells" + - interrupt-map + else: + properties: + "#interrupt-cells": + description: + Two cells to specify which line to connect to, and which output it should + be routed to. Both cells use a zero-based index. + const: 2 + required: + - interrupts additionalProperties: false examples: - | intc: interrupt-controller@3000 { - compatible = "realtek,rtl-intc"; - #interrupt-cells = <1>; + compatible = "realtek,rtl8380-intc", "realtek,rtl-intc"; + #interrupt-cells = <2>; interrupt-controller; - reg = <0x3000 0x20>; - #address-cells = <0>; - interrupt-map = - <31 &cpuintc 2>, - <30 &cpuintc 1>, - <29 &cpuintc 5>; + reg = <0x3000 0x18>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>, <3>, <4>, <5>, <6>; + }; + + irq-consumer@0 { + reg = <0 4>; + interrupt-parent = <&intc>; + interrupts = + <19 3>, /* IRQ 19, routed to output 3 (cpuintc 5) */ + <18 4>; /* IRQ 18, routed to output 4 (cpuintc 6) */ }; From patchwork Sun Jan 9 14:54:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 530864 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B483C4321E for ; Sun, 9 Jan 2022 14:55:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235917AbiAIOzE (ORCPT ); Sun, 9 Jan 2022 09:55:04 -0500 Received: from polaris.svanheule.net ([84.16.241.116]:58434 "EHLO polaris.svanheule.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235831AbiAIOyx (ORCPT ); Sun, 9 Jan 2022 09:54:53 -0500 Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:eafe:c901:f20a:f473:2021:45ec]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id B105028EE28; Sun, 9 Jan 2022 15:54:51 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1641740092; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WrbaX59ca9lhL9V4ZRttEMkg2AaMlgPLErcXwM3dPG8=; b=Eb6T0NM0UbivXLPQKUrq8VtxmpwfZYGAOCcpS3A7GbG2ubvQ5UoGosJuioiNIkjS/lBALR /KK1qmhspNDVbnu+kyIN6LGl2TRQnJ6Ew3aIWRXEsOSOHFK4+YRsMCwAgA7UOXFlEldDgY 6E3qyxu4hACK7j+Ku7V9wQIFfh5URTm44qy3hkOGUKgnjAfBc7zHLCxHhdR/sRMmPKawaY yLQEznEkBwIjbuLChy45KdXvb4dTeW3TCq15pxfqp6qpqoIe7uorxnTm6nW0fAtvqA8/QI ZIho79SQhyWDbHAoQFyROA6QK4KXtPnvEVDzUuYWNhIsiQxzU/r90FvL8Ix7yw== From: Sander Vanheule To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Thomas Gleixner , Marc Zyngier , Rob Herring , Birger Koblitz , Bert Vermeulen , John Crispin , Sander Vanheule Subject: [PATCH v3 5/6] irqchip/realtek-rtl: use parent interrupts Date: Sun, 9 Jan 2022 15:54:36 +0100 Message-Id: <57edb463b37de4a1d63e83ca9ef9beef81e0c72a.1641739718.git.sander@svanheule.net> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The interrupt-map property for "realtek,rtl-intc" has been deprecated in favor of a list of parent interrupts. Drop the open-coded parser for interrupt-map, and use the first parent interrupt instead. If no parent was provided, the driver will assume that this is the first hardware interrupt of the SoC's MIPS CPU. All SoC interrupts were treated equally, independent of which output they were actually routed to. This means the driver might as well route all interrupts to the first output, and achieve the same behaviour. Without the interrupt-map property, interrupt routing information is no longer available at initialisation. Routing setup will now happen later, when a hardware interrupt is mapped by the subsystem. Signed-off-by: Sander Vanheule --- drivers/irqchip/irq-realtek-rtl.c | 133 ++++++++++++++---------------- 1 file changed, 61 insertions(+), 72 deletions(-) diff --git a/drivers/irqchip/irq-realtek-rtl.c b/drivers/irqchip/irq-realtek-rtl.c index 50a56820c99b..388f4a7bfb80 100644 --- a/drivers/irqchip/irq-realtek-rtl.c +++ b/drivers/irqchip/irq-realtek-rtl.c @@ -21,11 +21,33 @@ #define RTL_ICTL_IRR2 0x10 #define RTL_ICTL_IRR3 0x14 +#define RTL_ICTL_NUM_INPUTS 32 + #define REG(x) (realtek_ictl_base + x) static DEFINE_RAW_SPINLOCK(irq_lock); static void __iomem *realtek_ictl_base; +/* + * IRR0-IRR3 store 4 bits per interrupt, but Realtek uses inverted numbering, + * placing IRQ 31 in the first four bits. A routing value of '0' means the + * interrupt is left disconnected. Routing values {1..15} connect to output + * lines {0..14}. + */ +#define IRR_OFFSET(idx) (4 * (3 - (idx * 4) / 32)) +#define IRR_SHIFT(idx) ((idx * 4) % 32) + +static inline void write_irr(void __iomem *irr0, int idx, u32 value) +{ + unsigned int offset = IRR_OFFSET(idx); + unsigned int shift = IRR_SHIFT(idx); + u32 irr; + + irr = readl(irr0 + offset) & ~(0xf << shift); + irr |= (value & 0xf) << shift; + writel(irr, irr0 + offset); +} + static void realtek_ictl_unmask_irq(struct irq_data *i) { unsigned long flags; @@ -62,8 +84,14 @@ static struct irq_chip realtek_ictl_irq = { static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) { + unsigned long flags; + irq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq); + raw_spin_lock_irqsave(&irq_lock, flags); + write_irr(REG(RTL_ICTL_IRR0), hw, 1); + raw_spin_unlock_irqrestore(&irq_lock, flags); + return 0; } @@ -95,90 +123,51 @@ static void realtek_irq_dispatch(struct irq_desc *desc) chained_irq_exit(chip, desc); } -/* - * SoC interrupts are cascaded to MIPS CPU interrupts according to the - * interrupt-map in the device tree. Each SoC interrupt gets 4 bits for - * the CPU interrupt in an Interrupt Routing Register. Max 32 SoC interrupts - * thus go into 4 IRRs. A routing value of '0' means the interrupt is left - * disconnected. Routing values {1..15} connect to output lines {0..14}. - */ -static int __init map_interrupts(struct device_node *node, struct irq_domain *domain) -{ - struct device_node *cpu_ictl; - const __be32 *imap; - u32 imaplen, soc_int, cpu_int, tmp, regs[4]; - int ret, i, irr_regs[] = { - RTL_ICTL_IRR3, - RTL_ICTL_IRR2, - RTL_ICTL_IRR1, - RTL_ICTL_IRR0, - }; - u8 mips_irqs_set; - - ret = of_property_read_u32(node, "#address-cells", &tmp); - if (ret || tmp) - return -EINVAL; - - imap = of_get_property(node, "interrupt-map", &imaplen); - if (!imap || imaplen % 3) - return -EINVAL; - - mips_irqs_set = 0; - memset(regs, 0, sizeof(regs)); - for (i = 0; i < imaplen; i += 3 * sizeof(u32)) { - soc_int = be32_to_cpup(imap); - if (soc_int > 31) - return -EINVAL; - - cpu_ictl = of_find_node_by_phandle(be32_to_cpup(imap + 1)); - if (!cpu_ictl) - return -EINVAL; - ret = of_property_read_u32(cpu_ictl, "#interrupt-cells", &tmp); - if (ret || tmp != 1) - return -EINVAL; - of_node_put(cpu_ictl); - - cpu_int = be32_to_cpup(imap + 2); - if (cpu_int > 7 || cpu_int < 2) - return -EINVAL; - - if (!(mips_irqs_set & BIT(cpu_int))) { - irq_set_chained_handler_and_data(cpu_int, realtek_irq_dispatch, - domain); - mips_irqs_set |= BIT(cpu_int); - } - - /* Use routing values (1..6) for CPU interrupts (2..7) */ - regs[(soc_int * 4) / 32] |= (cpu_int - 1) << (soc_int * 4) % 32; - imap += 3; - } - - for (i = 0; i < 4; i++) - writel(regs[i], REG(irr_regs[i])); - - return 0; -} - static int __init realtek_rtl_of_init(struct device_node *node, struct device_node *parent) { + struct of_phandle_args oirq; struct irq_domain *domain; - int ret; + unsigned int soc_irq; + int parent_irq; realtek_ictl_base = of_iomap(node, 0); if (!realtek_ictl_base) return -ENXIO; - /* Disable all cascaded interrupts */ + /* Disable all cascaded interrupts and clear routing */ writel(0, REG(RTL_ICTL_GIMR)); + for (soc_irq = 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++) + write_irr(REG(RTL_ICTL_IRR0), soc_irq, 0); + + if (WARN_ON(!of_irq_count(node))) { + /* + * If DT contains no parent interrupts, assume MIPS CPU IRQ 2 + * (HW0) is connected to the first output. This is the case for + * all known hardware anyway. "interrupt-map" is deprecated, so + * don't bother trying to parse that. + */ + oirq.np = of_find_compatible_node(NULL, NULL, "mti,cpu-interrupt-controller"); + oirq.args_count = 1; + oirq.args[0] = 2; + + parent_irq = irq_create_of_mapping(&oirq); + + of_node_put(oirq.np); + } else { + parent_irq = of_irq_get(node, 0); + } + + if (parent_irq < 0) + return parent_irq; + else if (!parent_irq) + return -ENODEV; - domain = irq_domain_add_simple(node, 32, 0, + domain = irq_domain_add_simple(node, RTL_ICTL_NUM_INPUTS, 0, &irq_domain_ops, NULL); + if (!domain) + return -ENOMEM; - ret = map_interrupts(node, domain); - if (ret) { - pr_err("invalid interrupt map\n"); - return ret; - } + irq_set_chained_handler_and_data(parent_irq, realtek_irq_dispatch, domain); return 0; }