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[209.51.188.17]) by mx.google.com with ESMTPS id s2si14822321ybu.534.2022.01.03.10.56.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Jan 2022 10:56:21 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=NUixM5Uk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from localhost ([::1]:42722 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4SVI-0003dE-JE for patch@linaro.org; Mon, 03 Jan 2022 13:56:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36502) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n4SSq-0007G2-OG; Mon, 03 Jan 2022 13:53:48 -0500 Received: from [2607:f8b0:4864:20::831] (port=46688 helo=mail-qt1-x831.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n4SSn-0006GD-So; Mon, 03 Jan 2022 13:53:47 -0500 Received: by mail-qt1-x831.google.com with SMTP id m25so31284726qtq.13; Mon, 03 Jan 2022 10:53:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ONhwFubTJrewF85Qam/ZsiMfJoEJAy9vmUnumANzWDc=; b=NUixM5UkM4pWDVnXQa1AceSRgeTQSqXQJwRbkMMvhYknnsluPDF/hxhZfbmP2uRQZ2 Xb+b9DxZudPwBLPce/JsSqqgiDop5FLQOjzT9hXcu4gIPVJQPcoi27cK/6XyCPg4Ykt+ htWCO5lMRqkL8d2tl9fAAj/Mt/P71o9kMB/iO5ABOU9wF+dA1Vjm8R4WCg63IPwBCwjP piN2ZL2GYfQObJXa8WsYLmFMPdjVF5rWcbCgP31fHut6cGzQnCJzGaKNiyMnWjPs7zlo Q2ySlCvDobQ/9znweAyI/k7VuY+aZbyrZkGDz6bme9ltgC0ApZtqBf6oBCHK/goeoXeu OviA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ONhwFubTJrewF85Qam/ZsiMfJoEJAy9vmUnumANzWDc=; b=8E0hPnZyt7xqm8WbSwLHhbAlEc0qvKCyUqdJFyD2/Gxl/6P1yLs2+Pur8iZXloZ0Oy cogRqmn5nqumQcU4NjMsZ6ruqf+koheBIugNSwXtXI6gtYDRC63bwWilEgj99pX5gxnk 3fdZpXl53Iex7R77U9Mku47vLQNF/+bhcUEg9kx2zMwGrlWGUDhurgvfvA2Aia4WXEvx c7vm3VsItTZKsPnTV3DIPh6mgdWTyLzMM23WSOb/NXW7lvOgQ3BSrsnypR/YAdcqhufU gbzr6u6blBWqMgChQ8GnsP7/bg/Ctimurzo0vSKViHalJ+FLX3c5342RljqHhDVP+VvG p//Q== X-Gm-Message-State: AOAM532ZFz2bRri1tE3RE/gaDFBLrARCAeoM+WM+V4g71Zus0YzCWiXM CkQBEnXMikf+KKWSUqwdNU0d/8+xWhw= X-Received: by 2002:ac8:5842:: with SMTP id h2mr41138732qth.244.1641236024807; Mon, 03 Jan 2022 10:53:44 -0800 (PST) Received: from rekt.ibmuc.com ([2804:431:c7c7:f4d8:aa07:335f:99e0:a6e7]) by smtp.gmail.com with ESMTPSA id w9sm29002867qko.71.2022.01.03.10.53.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jan 2022 10:53:44 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v2 1/5] target/ppc: Cache per-pmc insn and cycle count settings Date: Mon, 3 Jan 2022 15:53:28 -0300 Message-Id: <20220103185332.117878-2-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220103185332.117878-1-danielhb413@gmail.com> References: <20220103185332.117878-1-danielhb413@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::831 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::831; envelope-from=danielhb413@gmail.com; helo=mail-qt1-x831.google.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This is the combination of frozen bit and counter type, on a per counter basis. So far this is only used by HFLAGS_INSN_CNT, but will be used more later. Signed-off-by: Richard Henderson [danielhb: fixed PMC4 cyc_cnt shift and insn run latch code] Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 3 +++ target/ppc/cpu_init.c | 1 + target/ppc/helper_regs.c | 2 +- target/ppc/machine.c | 2 ++ target/ppc/power8-pmu.c | 53 +++++++++++++++++++++++++++++++--------- target/ppc/power8-pmu.h | 14 +++++------ 6 files changed, 54 insertions(+), 21 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index fc66c3561d..a297a52168 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1144,6 +1144,9 @@ struct CPUPPCState { /* Other registers */ target_ulong spr[1024]; /* special purpose registers */ ppc_spr_t spr_cb[1024]; + /* Composite status for PMC[1-5] enabled and counting insns or cycles. */ + uint8_t pmc_ins_cnt; + uint8_t pmc_cyc_cnt; /* Vector status and control register, minus VSCR_SAT */ uint32_t vscr; /* VSX registers (including FP and AVR) */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 06ef15cd9e..63f9babfee 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -8313,6 +8313,7 @@ static void ppc_cpu_reset(DeviceState *dev) #endif /* CONFIG_TCG */ #endif + pmu_update_summaries(env); hreg_compute_hflags(env); env->reserve_addr = (target_ulong)-1ULL; /* Be sure no exception or interrupt is pending */ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index b847928842..8671b7bb69 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -123,7 +123,7 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env) } #if defined(TARGET_PPC64) - if (pmu_insn_cnt_enabled(env)) { + if (env->pmc_ins_cnt) { hflags |= 1 << HFLAGS_INSN_CNT; } #endif diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 93972df58e..756d8de5d8 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -8,6 +8,7 @@ #include "qapi/error.h" #include "qemu/main-loop.h" #include "kvm_ppc.h" +#include "power8-pmu.h" static void post_load_update_msr(CPUPPCState *env) { @@ -19,6 +20,7 @@ static void post_load_update_msr(CPUPPCState *env) */ env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); + pmu_update_summaries(env); } static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 08d1902cd5..4fce6e8de8 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -11,8 +11,6 @@ */ #include "qemu/osdep.h" - -#include "power8-pmu.h" #include "cpu.h" #include "helper_regs.h" #include "exec/exec-all.h" @@ -20,6 +18,7 @@ #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "hw/ppc/ppc.h" +#include "power8-pmu.h" #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) @@ -121,18 +120,47 @@ static PMUEventType pmc_get_event(CPUPPCState *env, int sprn) return evt_type; } -bool pmu_insn_cnt_enabled(CPUPPCState *env) +void pmu_update_summaries(CPUPPCState *env) { - int sprn; - - for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) { - if (pmc_get_event(env, sprn) == PMU_EVENT_INSTRUCTIONS || - pmc_get_event(env, sprn) == PMU_EVENT_INSN_RUN_LATCH) { - return true; + target_ulong mmcr0 = env->spr[SPR_POWER_MMCR0]; + target_ulong mmcr1 = env->spr[SPR_POWER_MMCR1]; + int ins_cnt = 0; + int cyc_cnt = 0; + + if (!(mmcr0 & MMCR0_FC14) && mmcr1 != 0) { + target_ulong sel; + + sel = extract64(mmcr1, MMCR1_PMC1EVT_EXTR, MMCR1_EVT_SIZE); + switch (sel) { + case 0x02: + case 0xfe: + ins_cnt |= 1 << 1; + break; + case 0x1e: + case 0xf0: + cyc_cnt |= 1 << 1; + break; } + + sel = extract64(mmcr1, MMCR1_PMC2EVT_EXTR, MMCR1_EVT_SIZE); + ins_cnt |= (sel == 0x02) << 2; + cyc_cnt |= (sel == 0x1e) << 2; + + sel = extract64(mmcr1, MMCR1_PMC3EVT_EXTR, MMCR1_EVT_SIZE); + ins_cnt |= (sel == 0x02) << 3; + cyc_cnt |= (sel == 0x1e) << 3; + + sel = extract64(mmcr1, MMCR1_PMC4EVT_EXTR, MMCR1_EVT_SIZE); + ins_cnt |= ((sel == 0xfa) || (sel == 0x2)) << 4; + cyc_cnt |= (sel == 0x1e) << 4; } - return false; + ins_cnt |= !(mmcr0 & MMCR0_FC56) << 5; + cyc_cnt |= !(mmcr0 & MMCR0_FC56) << 6; + + env->pmc_ins_cnt = ins_cnt; + env->pmc_cyc_cnt = cyc_cnt; + env->hflags = deposit32(env->hflags, HFLAGS_INSN_CNT, 1, ins_cnt != 0); } static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns) @@ -264,8 +292,9 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value) env->spr[SPR_POWER_MMCR0] = value; - /* MMCR0 writes can change HFLAGS_PMCCCLEAR and HFLAGS_INSN_CNT */ + /* MMCR0 writes can change HFLAGS_PMCC[01] and HFLAGS_INSN_CNT */ hreg_compute_hflags(env); + pmu_update_summaries(env); /* Update cycle overflow timers with the current MMCR0 state */ pmu_update_overflow_timers(env); @@ -278,7 +307,7 @@ void helper_store_mmcr1(CPUPPCState *env, uint64_t value) env->spr[SPR_POWER_MMCR1] = value; /* MMCR1 writes can change HFLAGS_INSN_CNT */ - hreg_compute_hflags(env); + pmu_update_summaries(env); } target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn) diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h index 3ee4b4cda5..a839199561 100644 --- a/target/ppc/power8-pmu.h +++ b/target/ppc/power8-pmu.h @@ -13,14 +13,12 @@ #ifndef POWER8_PMU #define POWER8_PMU -#include "qemu/osdep.h" -#include "cpu.h" -#include "exec/exec-all.h" -#include "exec/helper-proto.h" -#include "qemu/error-report.h" -#include "qemu/main-loop.h" - void cpu_ppc_pmu_init(CPUPPCState *env); -bool pmu_insn_cnt_enabled(CPUPPCState *env); + +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +void pmu_update_summaries(CPUPPCState *env); +#else +static inline void pmu_update_summaries(CPUPPCState *env) { } +#endif #endif From patchwork Mon Jan 3 18:53:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 529639 Delivered-To: patch@linaro.org Received: by 2002:ac0:9f5c:0:0:0:0:0 with SMTP id l28csp1061798imf; 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[209.51.188.17]) by mx.google.com with ESMTPS id v1si5520561ybu.81.2022.01.03.10.54.29 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Jan 2022 10:54:29 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=hLmfG5nW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from localhost ([::1]:35644 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4STU-0007Kn-VX for patch@linaro.org; Mon, 03 Jan 2022 13:54:28 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36516) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n4SSt-0007HP-11; Mon, 03 Jan 2022 13:53:51 -0500 Received: from [2607:f8b0:4864:20::831] (port=34518 helo=mail-qt1-x831.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n4SSr-0006Gd-9H; Mon, 03 Jan 2022 13:53:50 -0500 Received: by mail-qt1-x831.google.com with SMTP id o17so31362354qtk.1; Mon, 03 Jan 2022 10:53:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L0OeVrJS6kMoBDCVPLb8crS8ryqPaT8r+Qs7TZGVG+E=; b=hLmfG5nWYwLuD93aip9YqwZMZvfB0u+7SZ7WbCST5GodFejdzKtt3bMEQhwST3f8TY YKuFs1CXmiSc8Tjjqg6cnc3XmtepACq4KOqc0ICesJCZZEa9bSOiy3dUTnml0t3GkVNd sCyB6O5K9YlgwMtlIgJUo7YQmnhqkN7V3jGLc1b9cz9tXd1WEv0X2ItTkwzUm/2t7blT LNogk9piBfl1Nh66rpuXJ0/Nxfc9DttiO1sydkm326VLQZbBvi5liZxLENbmztySRc2J NXnIT/7UnXuqhd6jr2V7xJNNTqqu7nW8nu2hjihyhJMUtmtXzJG57fWnftkZXBzxaSaF AYow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L0OeVrJS6kMoBDCVPLb8crS8ryqPaT8r+Qs7TZGVG+E=; b=mR1g7eeBBP3drIFU3x5xxXBOAKP9AaXaRL1my10mhZV1TLcnfcoqmu8egftSRjZkIO gxUWu1r0QpSEbcCvcd4LXnkqkpifDkdnxi/GAd6C7COPW3VtmGdVIexSwukCRUpwNmty iDeKfqSrqHx8LXB6dSKu2KbO2kEcha3cIYQ28j9ChApP4oGm4bdfpOdIogfnizaXtowz tQ+KDzoDKW+8//pWUOnRD3Q4OLAyFk0r7eG4dRVfa32nQD1riV0uWdRHWJ3+8B/t0amp Brc7uYjP62FT3lul3es9hUIQR9gw7k/M6v07LNZ2Hv3Ae8kYZLTCA2cMph9DhxGSp1mu Mr4w== X-Gm-Message-State: AOAM533+6dONeuz8efwq4zuiEX08tZk4hjikFIuITR6IBsX1cCiiuJzo GHUAAswmv4eQ7QWj9GwdCGY8WjypoRE= X-Received: by 2002:ac8:7f8b:: with SMTP id z11mr41026718qtj.513.1641236027006; Mon, 03 Jan 2022 10:53:47 -0800 (PST) Received: from rekt.ibmuc.com ([2804:431:c7c7:f4d8:aa07:335f:99e0:a6e7]) by smtp.gmail.com with ESMTPSA id w9sm29002867qko.71.2022.01.03.10.53.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jan 2022 10:53:46 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v2 2/5] target/ppc: Rewrite pmu_increment_insns Date: Mon, 3 Jan 2022 15:53:29 -0300 Message-Id: <20220103185332.117878-3-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220103185332.117878-1-danielhb413@gmail.com> References: <20220103185332.117878-1-danielhb413@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::831 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::831; envelope-from=danielhb413@gmail.com; helo=mail-qt1-x831.google.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Use the cached pmc_ins_cnt value. Unroll the loop over the different PMC counters. Treat the PMC4 run-latch specially. Signed-off-by: Richard Henderson --- target/ppc/power8-pmu.c | 78 ++++++++++++++++++++++++++--------------- 1 file changed, 49 insertions(+), 29 deletions(-) diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 4fce6e8de8..8f01934c15 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -165,45 +165,65 @@ void pmu_update_summaries(CPUPPCState *env) static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns) { + target_ulong mmcr0 = env->spr[SPR_POWER_MMCR0]; + unsigned ins_cnt = env->pmc_ins_cnt; bool overflow_triggered = false; - int sprn; - - /* PMC6 never counts instructions */ - for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) { - PMUEventType evt_type = pmc_get_event(env, sprn); - bool insn_event = evt_type == PMU_EVENT_INSTRUCTIONS || - evt_type == PMU_EVENT_INSN_RUN_LATCH; - - if (pmc_is_inactive(env, sprn) || !insn_event) { - continue; + target_ulong tmp; + + if (unlikely(ins_cnt & 0x1e)) { + if (ins_cnt & (1 << 1)) { + tmp = env->spr[SPR_POWER_PMC1]; + tmp += num_insns; + if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMC1CE)) { + tmp = PMC_COUNTER_NEGATIVE_VAL; + overflow_triggered = true; + } + env->spr[SPR_POWER_PMC1] = tmp; } - if (evt_type == PMU_EVENT_INSTRUCTIONS) { - env->spr[sprn] += num_insns; + if (ins_cnt & (1 << 2)) { + tmp = env->spr[SPR_POWER_PMC2]; + tmp += num_insns; + if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) { + tmp = PMC_COUNTER_NEGATIVE_VAL; + overflow_triggered = true; + } + env->spr[SPR_POWER_PMC2] = tmp; } - if (evt_type == PMU_EVENT_INSN_RUN_LATCH && - env->spr[SPR_CTRL] & CTRL_RUN) { - env->spr[sprn] += num_insns; + if (ins_cnt & (1 << 3)) { + tmp = env->spr[SPR_POWER_PMC3]; + tmp += num_insns; + if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) { + tmp = PMC_COUNTER_NEGATIVE_VAL; + overflow_triggered = true; + } + env->spr[SPR_POWER_PMC3] = tmp; } - if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL && - pmc_has_overflow_enabled(env, sprn)) { + if (ins_cnt & (1 << 4)) { + target_ulong mmcr1 = env->spr[SPR_POWER_MMCR1]; + int sel = extract64(mmcr1, MMCR1_PMC4EVT_EXTR, MMCR1_EVT_SIZE); + if (sel == 0x02 || (env->spr[SPR_CTRL] & CTRL_RUN)) { + tmp = env->spr[SPR_POWER_PMC4]; + tmp += num_insns; + if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) { + tmp = PMC_COUNTER_NEGATIVE_VAL; + overflow_triggered = true; + } + env->spr[SPR_POWER_PMC4] = tmp; + } + } + } + if (ins_cnt & (1 << 5)) { + tmp = env->spr[SPR_POWER_PMC5]; + tmp += num_insns; + if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) { + tmp = PMC_COUNTER_NEGATIVE_VAL; overflow_triggered = true; - - /* - * The real PMU will always trigger a counter overflow with - * PMC_COUNTER_NEGATIVE_VAL. We don't have an easy way to - * do that since we're counting block of instructions at - * the end of each translation block, and we're probably - * passing this value at this point. - * - * Let's write PMC_COUNTER_NEGATIVE_VAL to the overflowed - * counter to simulate what the real hardware would do. - */ - env->spr[sprn] = PMC_COUNTER_NEGATIVE_VAL; } + env->spr[SPR_POWER_PMC5] = tmp; } return overflow_triggered; From patchwork Mon Jan 3 18:53:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 529640 Delivered-To: patch@linaro.org Received: by 2002:ac0:9f5c:0:0:0:0:0 with SMTP id l28csp1061911imf; Mon, 3 Jan 2022 10:54:39 -0800 (PST) X-Google-Smtp-Source: ABdhPJx0WZxY+RPiCGP3S3S1F7he8uJ9rqshyv23e6WPd8b0tJzcaVWFNqZahVCHjrKZpiHZseCP X-Received: by 2002:a5b:f0e:: with SMTP id x14mr58724796ybr.671.1641236078918; Mon, 03 Jan 2022 10:54:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1641236078; cv=none; d=google.com; s=arc-20160816; b=XFYHCtm8FBl8Vju1nB1sXKixJo2K41GrlhmjDbPLuFV/0Vo6nRxhG6IdH75TytZEJH /TXSoBcC/bGu90WS74lBEkPNDSGC6Eo+oikeFK/T/hfI+OEPAAEN+Q0RPRDiddtosqpt pTOlVkth+DAQJpcNMN/UgK0seOy+Ue9dL2GPFwdNHfEXePSUx2XHwpL92Zi70atl7xK5 u0DGy4AeKJY5aubhjQvF8gqvh9owLjmQTkJEF8h3x9+tR62hR5PelvY6ShTPJQ4XOHjQ kWu5jATy6NaR+WPGX5OAWtzysmBKXaFi0LcUKngSrr/QaKUf+a26CJLSF9/FV3H4B2pV bUTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dahHqnMxceDbQ74I84xFv3w02NM0JbWTAXBZEs59W+g=; b=0aqZE7Pm33H8AYZnY/UmsgsjlDCwnmGxIb9QqyPg3GnAXbQBj6K2QjXxV91SjElI70 cFis/Pba9KebfpuyqvlIwEtyDoJtw17/IMLgKd2d9T4OxTgtuLzOLd98fStmxSbrk7QM 8miEWzSsod1NHFr8mh6r0a0oN1qgEteFfhA6o0ck2cRPk7OqvhVNJkxGA7dLVAYG+xhG hpg+IbJsgWE/fA88UYGmlAwJ65l3ETbc/hfYG9wykHQRhist51CW4zv5HRxzJqSy5LAo CqM8Yz3FcpCBqoBcg7FXOkp4J8nIBgOnK8BWQzQeKxO5XZfmkZ9kh2J0Xw4gyynN7x/j uE+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=HwygmsqK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o11si18638801ybk.791.2022.01.03.10.54.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Jan 2022 10:54:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=HwygmsqK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from localhost ([::1]:36400 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4STe-0007rN-D7 for patch@linaro.org; Mon, 03 Jan 2022 13:54:38 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36530) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n4SSu-0007KG-SF; Mon, 03 Jan 2022 13:53:53 -0500 Received: from [2607:f8b0:4864:20::82a] (port=38909 helo=mail-qt1-x82a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n4SSt-0006Gw-6U; Mon, 03 Jan 2022 13:53:52 -0500 Received: by mail-qt1-x82a.google.com with SMTP id 8so31334100qtx.5; Mon, 03 Jan 2022 10:53:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dahHqnMxceDbQ74I84xFv3w02NM0JbWTAXBZEs59W+g=; b=HwygmsqKagS4/1u/wmwDtqnIopi548KVsdvuWfE28cvHuaYGRqk+4a71OKuznCqvED kJ9uYLE00WQoa4gmdmyk2pP7iaiaAqg1DS2/sJlHzspAM2LyLhX17CsuJzVS6Z/a+1+s 4lOS/YRivRuWLS9o+vtH6+sC34aanZtuFC+eRpEOlFoMQHKAqMvZFm6HhIgPJVv5QCiJ Rhi4gt3yMu2Y7tgI8s3Qy5PX5DZEAT1FeDrik4+V8pWWYZCo4Wrsop74FKfv7otXAKBV syku2I7adfL+jIyaDv6cUERXFN3/aqHX7wM2tuFOAq1NxoM+z7DxvBweG2DmQPam5gP0 4qHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dahHqnMxceDbQ74I84xFv3w02NM0JbWTAXBZEs59W+g=; b=mNhOwmeKtgPZcK1XgVNA7EjrGBECdDNn4IhW3ZSvMuofwRhFTJz41CcUvE7q7Otirm pA5xy+B4mX1Rv3g7G+wOpnmVKdJMVVlVZOem0wIYktN5OMnuNfXPztKTqhvcd+BePvyc I/4eNMVaxcQfoTMvhmHrc8Y4158Vmje6J374JXfevdVpRDv/sJt9QW525+k2ZFCBuK0O fguaLQNWHa/KrDzSf8fEZZ91pNh4tTmoOxkb2dpC+EwTn1XSqCZTlpyzTOiMyTuiinWO DzRlDp3DHP5T8TSALwEa7ZiDiO3TBearQo5jeWvn5oxH0bQyZbt+LmFUkfqJYVWNHwyp l8cA== X-Gm-Message-State: AOAM5338e89ycK3a5/7XvtpXFdPgeH0NgnKCGvr4CPT6cXNx+NfTeHVN jeKSBPxSVw6gBpQp9rk7cjUnmuv9RoA= X-Received: by 2002:a05:622a:1114:: with SMTP id e20mr41750945qty.279.1641236030059; Mon, 03 Jan 2022 10:53:50 -0800 (PST) Received: from rekt.ibmuc.com ([2804:431:c7c7:f4d8:aa07:335f:99e0:a6e7]) by smtp.gmail.com with ESMTPSA id w9sm29002867qko.71.2022.01.03.10.53.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jan 2022 10:53:49 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v2 3/5] target/ppc: Use env->pnc_cyc_cnt Date: Mon, 3 Jan 2022 15:53:30 -0300 Message-Id: <20220103185332.117878-4-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220103185332.117878-1-danielhb413@gmail.com> References: <20220103185332.117878-1-danielhb413@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::82a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::82a; envelope-from=danielhb413@gmail.com; helo=mail-qt1-x82a.google.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Use the cached pmc_cyc_cnt value in pmu_update_cycles and pmc_update_overflow_timer. This leaves pmc_get_event and pmc_is_inactive unused, so remove them. Signed-off-by: Richard Henderson --- target/ppc/power8-pmu.c | 107 ++++------------------------------------ 1 file changed, 9 insertions(+), 98 deletions(-) diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 8f01934c15..7fc7d91109 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -24,19 +24,6 @@ #define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL -static bool pmc_is_inactive(CPUPPCState *env, int sprn) -{ - if (env->spr[SPR_POWER_MMCR0] & MMCR0_FC) { - return true; - } - - if (sprn < SPR_POWER_PMC5) { - return env->spr[SPR_POWER_MMCR0] & MMCR0_FC14; - } - - return env->spr[SPR_POWER_MMCR0] & MMCR0_FC56; -} - static bool pmc_has_overflow_enabled(CPUPPCState *env, int sprn) { if (sprn == SPR_POWER_PMC1) { @@ -46,80 +33,6 @@ static bool pmc_has_overflow_enabled(CPUPPCState *env, int sprn) return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE; } -/* - * For PMCs 1-4, IBM POWER chips has support for an implementation - * dependent event, 0x1E, that enables cycle counting. The Linux kernel - * makes extensive use of 0x1E, so let's also support it. - * - * Likewise, event 0x2 is an implementation-dependent event that IBM - * POWER chips implement (at least since POWER8) that is equivalent to - * PM_INST_CMPL. Let's support this event on PMCs 1-4 as well. - */ -static PMUEventType pmc_get_event(CPUPPCState *env, int sprn) -{ - uint8_t mmcr1_evt_extr[] = { MMCR1_PMC1EVT_EXTR, MMCR1_PMC2EVT_EXTR, - MMCR1_PMC3EVT_EXTR, MMCR1_PMC4EVT_EXTR }; - PMUEventType evt_type = PMU_EVENT_INVALID; - uint8_t pmcsel; - int i; - - if (pmc_is_inactive(env, sprn)) { - return PMU_EVENT_INACTIVE; - } - - if (sprn == SPR_POWER_PMC5) { - return PMU_EVENT_INSTRUCTIONS; - } - - if (sprn == SPR_POWER_PMC6) { - return PMU_EVENT_CYCLES; - } - - i = sprn - SPR_POWER_PMC1; - pmcsel = extract64(env->spr[SPR_POWER_MMCR1], mmcr1_evt_extr[i], - MMCR1_EVT_SIZE); - - switch (pmcsel) { - case 0x2: - evt_type = PMU_EVENT_INSTRUCTIONS; - break; - case 0x1E: - evt_type = PMU_EVENT_CYCLES; - break; - case 0xF0: - /* - * PMC1SEL = 0xF0 is the architected PowerISA v3.1 - * event that counts cycles using PMC1. - */ - if (sprn == SPR_POWER_PMC1) { - evt_type = PMU_EVENT_CYCLES; - } - break; - case 0xFA: - /* - * PMC4SEL = 0xFA is the "instructions completed - * with run latch set" event. - */ - if (sprn == SPR_POWER_PMC4) { - evt_type = PMU_EVENT_INSN_RUN_LATCH; - } - break; - case 0xFE: - /* - * PMC1SEL = 0xFE is the architected PowerISA v3.1 - * event to sample instructions using PMC1. - */ - if (sprn == SPR_POWER_PMC1) { - evt_type = PMU_EVENT_INSTRUCTIONS; - } - break; - default: - break; - } - - return evt_type; -} - void pmu_update_summaries(CPUPPCState *env) { target_ulong mmcr0 = env->spr[SPR_POWER_MMCR0]; @@ -233,18 +146,16 @@ static void pmu_update_cycles(CPUPPCState *env) { uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); uint64_t time_delta = now - env->pmu_base_time; - int sprn; + int sprn, cyc_cnt = env->pmc_cyc_cnt; for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) { - if (pmc_get_event(env, sprn) != PMU_EVENT_CYCLES) { - continue; + if (cyc_cnt & (1 << (sprn - SPR_POWER_PMC1 + 1))) { + /* + * The pseries and powernv clock runs at 1Ghz, meaning + * that 1 nanosec equals 1 cycle. + */ + env->spr[sprn] += time_delta; } - - /* - * The pseries and powernv clock runs at 1Ghz, meaning - * that 1 nanosec equals 1 cycle. - */ - env->spr[sprn] += time_delta; } /* Update base_time for future calculations */ @@ -273,7 +184,7 @@ static void pmc_update_overflow_timer(CPUPPCState *env, int sprn) return; } - if (pmc_get_event(env, sprn) != PMU_EVENT_CYCLES || + if (!(env->pmc_cyc_cnt & (1 << (sprn - SPR_POWER_PMC1 + 1))) || !pmc_has_overflow_enabled(env, sprn)) { /* Overflow timer is not needed for this counter */ timer_del(pmc_overflow_timer); @@ -281,7 +192,7 @@ static void pmc_update_overflow_timer(CPUPPCState *env, int sprn) } if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL) { - timeout = 0; + timeout = 0; } else { timeout = PMC_COUNTER_NEGATIVE_VAL - env->spr[sprn]; }