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[89.77.68.124]) by smtp.gmail.com with ESMTPSA id v9sm2454505lja.109.2021.12.30.11.53.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Dec 2021 11:53:34 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Marek Szyprowski , Jaehoon Chung , Chanho Park , Sam Protsenko , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Sylwester Nawrocki , stable@vger.kernel.org Subject: [RFT][PATCH 1/3] ARM: dts: exynos: fix UART3 pins configuration in Exynos5250 Date: Thu, 30 Dec 2021 20:53:23 +0100 Message-Id: <20211230195325.328220-1-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org The gpa1-4 pin was put twice in UART3 pin configuration of Exynos5250, instead of proper pin gpa1-5. Fixes: f8bfe2b050f3 ("ARM: dts: add pin state information in client nodes for Exynos5 platforms") Cc: Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Tested-by: Marek Szyprowski --- arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index d31a68672bfa..d7d756614edd 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -260,7 +260,7 @@ i2c3_hs_bus: i2c3-hs-bus { }; uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-4"; + samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; From patchwork Thu Dec 30 19:53:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 529622 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16274C433EF for ; Thu, 30 Dec 2021 19:53:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242030AbhL3Txj (ORCPT ); Thu, 30 Dec 2021 14:53:39 -0500 Received: from smtp-relay-internal-1.canonical.com ([185.125.188.123]:33638 "EHLO smtp-relay-internal-1.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241937AbhL3Txi (ORCPT ); Thu, 30 Dec 2021 14:53:38 -0500 Received: from mail-lj1-f197.google.com (mail-lj1-f197.google.com [209.85.208.197]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id 5B6563F1A4 for ; Thu, 30 Dec 2021 19:53:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1640894017; bh=QNADCpp7Mlh0tiTM/IZxnSD9jEJmVsO7Ez+VZPkoolk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FZLpCDxlQfhIZFka20t/7kQ05zL58oiE1XaQ5937izdJuHuNYZuNpECW51K5MwYIG j8oowMzlW2h6U0JuLxA0SeIkxq5XRylH2u/rUCFYQzkjaOvh72yE4IIG7BVSA8agF/ upIVb+ADPdFhY2HngydEb3B9s0yiAjK81W6h0lfZB/ZjNyGwDSIP0ziD4erP8yS5GU LxyLCmVHvjRmUo6RpbOgQ7zpMypVKCdHwFN+2ZIRMhOFn4wDai2uqaNqlN/+cqT4wm DPD6vyDdnLSweKH0/d3ul8rOwtXLxjHodAYb0fmmUabEl7ZZLAUyKEBxz6BIzyb6k+ miuCPeeaTd5eA== Received: by mail-lj1-f197.google.com with SMTP id o11-20020a2e90cb000000b0022dd251d30aso4901562ljg.8 for ; Thu, 30 Dec 2021 11:53:37 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QNADCpp7Mlh0tiTM/IZxnSD9jEJmVsO7Ez+VZPkoolk=; b=ZX2L1AeyRaU2c0ujxbOIEQfaNv4fsmUJty66TNa6f2RWQkSknotMQIv57HX5Dy8hua IZ5epWr6SRaj+uCwXFmPLQdv8Cmz3xNl17ryHbTSvweA3tJzXW7rxhJ2XIuRtu1Rte5Y L3UHTxWqJ7zEEARl8FMcFx/HNHGePUBesp2Fl23OANl/vrfSeIvNiEwzu2iD9EP39TsB bIqPlzO8U2VfL6+i26gPSf18qlF+0dtIMOP61bASjNpfXZqYjj1UBRkgNfvaBwLB0f9P J/kIi9Q1uSU/xktlOwReoUDFXibcEgj/7IN25Sr8HYXc4FJaC/GRHGiMCLbOUdL5EHdu k37A== X-Gm-Message-State: AOAM53260xgrU1mGUdxq7BljRpIoRhksm734Ad9BbBJkvgvmepqnMTNG bu33trgEMPzJL3vWOiKiQS8H59hMeE424o5tUfpB4NT4ZAhiCWcsGnNpAc06D2b+wXkudNuuMe/ grbDdu1++UgFRhArwIaFnlOEmj0u27suOxQ== X-Received: by 2002:ac2:4e0f:: with SMTP id e15mr28637091lfr.352.1640894016663; Thu, 30 Dec 2021 11:53:36 -0800 (PST) X-Google-Smtp-Source: ABdhPJx7O09tl2Ts7mTIWiy2LfEGqGyrflqLZ61fdbAegNO9XsZTDpgxdoRm8WI5V2+TWOtiW3DmOw== X-Received: by 2002:ac2:4e0f:: with SMTP id e15mr28637080lfr.352.1640894016500; Thu, 30 Dec 2021 11:53:36 -0800 (PST) Received: from krzk-bin.lan (89-77-68-124.dynamic.chello.pl. [89.77.68.124]) by smtp.gmail.com with ESMTPSA id v9sm2454505lja.109.2021.12.30.11.53.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Dec 2021 11:53:36 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Marek Szyprowski , Jaehoon Chung , Chanho Park , Sam Protsenko , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Sylwester Nawrocki , stable@vger.kernel.org Subject: [RFT][PATCH 2/3] arm64: dts: exynos: fix WLAN pin configuration in TM2 Date: Thu, 30 Dec 2021 20:53:24 +0100 Message-Id: <20211230195325.328220-2-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211230195325.328220-1-krzysztof.kozlowski@canonical.com> References: <20211230195325.328220-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Each pin configuration in pin controller should be a node with "samsung,pins" and other similar properties. However the macro PIN() (used for initial/sleep states) defines entire node, so PCIe WLAN pin configuration node was ignored. Fixes: 98c03b6eef3f ("arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards") Cc: Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index cbcc01a66aab..c5054c7a9c03 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -1104,8 +1104,11 @@ &pinctrl_ese { pinctrl-names = "default"; pinctrl-0 = <&initial_ese>; - pcie_wlanen: pcie-wlanen { - PIN(INPUT, gpj2-0, UP, FAST_SR4); + pcie_wlanen: pcie-wlanen-pins { + samsung,pins = "gpj2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; initial_ese: initial-state {