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[81.169.180.215]) by mx.google.com with ESMTP id v22-v6si2310048ejr.314.2018.11.14.01.03.17; Wed, 14 Nov 2018 01:03:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HkuDf68C; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id CAADEC2207E; Wed, 14 Nov 2018 09:02:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A5949C21F77; Wed, 14 Nov 2018 09:01:46 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3EE72C2205D; Wed, 14 Nov 2018 09:01:36 +0000 (UTC) Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by lists.denx.de (Postfix) with ESMTPS id BC492C2207B for ; Wed, 14 Nov 2018 09:01:32 +0000 (UTC) Received: by mail-wm1-f67.google.com with SMTP id s11so4616555wmh.1 for ; Wed, 14 Nov 2018 01:01:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iaohqzlDPM5QXVx6bqBVDkpB+/CMdsPn5m08HvfQ/Ag=; b=HkuDf68CAjv9eOdKLbYRQGjUaOSNFsYQuT16eft5HyFRmgg+NXhi8daXBu9E6UPuVj Ar46a/qasLkLL/XFMWGaANtPjaeSabLcWmYodJFQ/QDTtgcKfmtRmBPzFoRpo/hiLqzJ y5uY+GgP4QbQIZ/LcEQjXd3UG8dEH1wL/9cmo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iaohqzlDPM5QXVx6bqBVDkpB+/CMdsPn5m08HvfQ/Ag=; b=lsyxSM0EtIyXKh5Lq0WW7amfl/NnbtMqUgthDGQohKUFXhH1HS7M0NlIv48DAxGJsk sUWZbeatIrIchZ4vO9T2KbyfABWqncTuTziVGK5RrvH7Fi50bL/9FgcOQe7uwXCmXH8n PPNjoJzsut7TosBQ8pg9o+KICDOZE+NiAjELzNbzFZ9ynL5OweuxBEJ6ez91NopJLVPN /fyL8h5Ox/HXXA2Q1oobkPNsIxqQNAUno9W+iUznWiOm5mt30eg3WFYvIeI9OWFxcwks JU1R+9s4ScYGdn9jg/S/xaZleT9j13GrF3+EMjjGCpB/iyO3ntR2LQW2LNiY1GLWNt7V YhEA== X-Gm-Message-State: AGRZ1gL9a2bFtmfOL+qDqpw+diqgZEQMn7dplG5GsF+nfK+CO0O3FPCD 059HfpmQ4kYZOrBNqI26eScc2Q== X-Received: by 2002:a1c:98d5:: with SMTP id a204-v6mr1059876wme.73.1542186092031; Wed, 14 Nov 2018 01:01:32 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1088:2b4c:4d39:8b22:d570:822a]) by smtp.gmail.com with ESMTPSA id j125-v6sm14474871wmb.12.2018.11.14.01.01.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Nov 2018 01:01:31 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: patrick.delaunay@st.com, albert.u.boot@aribaud.net, sjg@chromium.org, christophe.kerello@st.com, patrice.chotard@st.com Date: Wed, 14 Nov 2018 10:01:11 +0100 Message-Id: <20181114090114.7727-2-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181114090114.7727-1-benjamin.gaignard@st.com> References: <20181114090114.7727-1-benjamin.gaignard@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 1/4] dm: Add Hardware Spinlock class X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Benjamin Gaignard This is uclass for Hardware Spinlocks. It implements two mandatory operations: lock and unlock and one optional relax operation. Signed-off-by: Benjamin Gaignard Reviewed-by: Simon Glass Reviewed-by: Patrice Chotard --- version 2: - use -ETIMEDOUT and -ENOSYS for errors cases - do not test if ops is valid arch/sandbox/dts/test.dts | 4 + arch/sandbox/include/asm/state.h | 1 + configs/sandbox_defconfig | 2 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/hwspinlock/Kconfig | 16 ++++ drivers/hwspinlock/Makefile | 6 ++ drivers/hwspinlock/hwspinlock-uclass.c | 143 ++++++++++++++++++++++++++++++++ drivers/hwspinlock/sandbox_hwspinlock.c | 56 +++++++++++++ include/dm/uclass-id.h | 1 + include/hwspinlock.h | 140 +++++++++++++++++++++++++++++++ test/dm/Makefile | 1 + test/dm/hwspinlock.c | 40 +++++++++ 13 files changed, 413 insertions(+) create mode 100644 drivers/hwspinlock/Kconfig create mode 100644 drivers/hwspinlock/Makefile create mode 100644 drivers/hwspinlock/hwspinlock-uclass.c create mode 100644 drivers/hwspinlock/sandbox_hwspinlock.c create mode 100644 include/hwspinlock.h create mode 100644 test/dm/hwspinlock.c diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 57e0dd7663..50cd2f89e0 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -712,6 +712,10 @@ sandbox_tee { compatible = "sandbox,tee"; }; + + hwspinlock@0 { + compatible = "sandbox,hwspinlock"; + }; }; #include "sandbox_pmic.dtsi" diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index dcb6d5f568..a5d7c6aaf3 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -99,6 +99,7 @@ struct sandbox_state { ulong next_tag; /* Next address tag to allocate */ struct list_head mapmem_head; /* struct sandbox_mapmem_entry */ + bool hwspinlock; /* Hardware Spinlock status */ }; /* Minimum space we guarantee in the state FDT when calling read/write*/ diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 2ce336fc81..36b67be2df 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -97,6 +97,8 @@ CONFIG_BOARD=y CONFIG_BOARD_SANDBOX=y CONFIG_PM8916_GPIO=y CONFIG_SANDBOX_GPIO=y +CONFIG_DM_HWSPINLOCK=y +CONFIG_HWSPINLOCK_SANDBOX=y CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_CROS_EC_LDO=y diff --git a/drivers/Kconfig b/drivers/Kconfig index 927a2b87f6..7e6ca7cd3e 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -40,6 +40,8 @@ source "drivers/fpga/Kconfig" source "drivers/gpio/Kconfig" +source "drivers/hwspinlock/Kconfig" + source "drivers/i2c/Kconfig" source "drivers/input/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index fb38b67541..0ef56fb416 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -111,4 +111,5 @@ obj-$(CONFIG_W1) += w1/ obj-$(CONFIG_W1_EEPROM) += w1-eeprom/ obj-$(CONFIG_MACH_PIC32) += ddr/microchip/ +obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock/ endif diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig new file mode 100644 index 0000000000..de367fd2a9 --- /dev/null +++ b/drivers/hwspinlock/Kconfig @@ -0,0 +1,16 @@ +menu "Hardware Spinlock Support" + +config DM_HWSPINLOCK + bool "Enable U-Boot hardware spinlock support" + help + This option enables U-Boot hardware spinlock support + +config HWSPINLOCK_SANDBOX + bool "Enable Hardware Spinlock support for Sandbox" + depends on SANDBOX && DM_HWSPINLOCK + help + Enable hardware spinlock support in Sandbox. This is a dummy device that + can be probed and support all the methods of HWSPINLOCK, but does not + really do anything. + +endmenu diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile new file mode 100644 index 0000000000..2704d6814f --- /dev/null +++ b/drivers/hwspinlock/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved + +obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock-uclass.o +obj-$(CONFIG_HWSPINLOCK_SANDBOX) += sandbox_hwspinlock.o diff --git a/drivers/hwspinlock/hwspinlock-uclass.c b/drivers/hwspinlock/hwspinlock-uclass.c new file mode 100644 index 0000000000..353bd77154 --- /dev/null +++ b/drivers/hwspinlock/hwspinlock-uclass.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include + +static inline const struct hwspinlock_ops * +hwspinlock_dev_ops(struct udevice *dev) +{ + return (const struct hwspinlock_ops *)dev->driver->ops; +} + +static int hwspinlock_of_xlate_default(struct hwspinlock *hws, + struct ofnode_phandle_args *args) +{ + if (args->args_count > 1) { + debug("Invaild args_count: %d\n", args->args_count); + return -EINVAL; + } + + if (args->args_count) + hws->id = args->args[0]; + else + hws->id = 0; + + return 0; +} + +int hwspinlock_get_by_index(struct udevice *dev, int index, + struct hwspinlock *hws) +{ + int ret; + struct ofnode_phandle_args args; + struct udevice *dev_hws; + const struct hwspinlock_ops *ops; + + assert(hws); + hws->dev = NULL; + + ret = dev_read_phandle_with_args(dev, "hwlocks", "#hwlock-cells", 1, + index, &args); + if (ret) { + dev_dbg(dev, "%s: dev_read_phandle_with_args: err=%d\n", + __func__, ret); + return ret; + } + + ret = uclass_get_device_by_ofnode(UCLASS_HWSPINLOCK, + args.node, &dev_hws); + if (ret) { + dev_dbg(dev, + "%s: uclass_get_device_by_of_offset failed: err=%d\n", + __func__, ret); + return ret; + } + + hws->dev = dev_hws; + + ops = hwspinlock_dev_ops(dev_hws); + + if (ops->of_xlate) + ret = ops->of_xlate(hws, &args); + else + ret = hwspinlock_of_xlate_default(hws, &args); + if (ret) + dev_dbg(dev, "of_xlate() failed: %d\n", ret); + + return ret; +} + +int hwspinlock_lock_timeout(struct hwspinlock *hws, unsigned int timeout) +{ + const struct hwspinlock_ops *ops; + ulong start; + int ret; + + assert(hws); + + if (!hws->dev) + return -EINVAL; + + ops = hwspinlock_dev_ops(hws->dev); + if (!ops->lock) + return -ENOSYS; + + for (start = get_timer(0); get_timer(start) < timeout;) { + ret = ops->lock(hws->dev, hws->id); + if (!ret) + return ret; + + if (ops->relax) + ops->relax(hws->dev); + } + + return -ETIMEDOUT; +} + +int hwspinlock_unlock(struct hwspinlock *hws) +{ + const struct hwspinlock_ops *ops; + + assert(hws); + + if (!hws->dev) + return -EINVAL; + + ops = hwspinlock_dev_ops(hws->dev); + if (!ops->unlock) + return -ENOSYS; + + return ops->unlock(hws->dev, hws->id); +} + +static int hwspinlock_post_bind(struct udevice *dev) +{ +#if defined(CONFIG_NEEDS_MANUAL_RELOC) + struct hwspinlock_ops *ops = device_get_ops(dev); + static int reloc_done; + + if (!reloc_done) { + if (ops->lock) + ops->lock += gd->reloc_off; + if (ops->unlock) + ops->unlock += gd->reloc_off; + if (ops->relax) + ops->relax += gd->reloc_off; + + reloc_done++; + } +#endif + return 0; +} + +UCLASS_DRIVER(hwspinlock) = { + .id = UCLASS_HWSPINLOCK, + .name = "hwspinlock", + .post_bind = hwspinlock_post_bind, +}; diff --git a/drivers/hwspinlock/sandbox_hwspinlock.c b/drivers/hwspinlock/sandbox_hwspinlock.c new file mode 100644 index 0000000000..be920f5f99 --- /dev/null +++ b/drivers/hwspinlock/sandbox_hwspinlock.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include + +static int sandbox_lock(struct udevice *dev, int index) +{ + struct sandbox_state *state = state_get_current(); + + if (index != 0) + return -1; + + if (state->hwspinlock) + return -1; + + state->hwspinlock = true; + + return 0; +} + +static int sandbox_unlock(struct udevice *dev, int index) +{ + struct sandbox_state *state = state_get_current(); + + if (index != 0) + return -1; + + if (!state->hwspinlock) + return -1; + + state->hwspinlock = false; + + return 0; +} + +static const struct hwspinlock_ops sandbox_hwspinlock_ops = { + .lock = sandbox_lock, + .unlock = sandbox_unlock, +}; + +static const struct udevice_id sandbox_hwspinlock_ids[] = { + { .compatible = "sandbox,hwspinlock" }, + {} +}; + +U_BOOT_DRIVER(hwspinlock_sandbox) = { + .name = "hwspinlock_sandbox", + .id = UCLASS_HWSPINLOCK, + .of_match = sandbox_hwspinlock_ids, + .ops = &sandbox_hwspinlock_ops, +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 269a2c6e72..6193017432 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -40,6 +40,7 @@ enum uclass_id { UCLASS_ETH, /* Ethernet device */ UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ + UCLASS_HWSPINLOCK, /* Hardware semaphores */ UCLASS_FIRMWARE, /* Firmware */ UCLASS_I2C, /* I2C bus */ UCLASS_I2C_EEPROM, /* I2C EEPROM device */ diff --git a/include/hwspinlock.h b/include/hwspinlock.h new file mode 100644 index 0000000000..99389c13c2 --- /dev/null +++ b/include/hwspinlock.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#ifndef _HWSPINLOCK_H_ +#define _HWSPINLOCK_H_ + +/** + * Implement a hwspinlock uclass. + * Hardware spinlocks are used to perform hardware protection of + * critical sections and synchronisation between multiprocessors. + */ + +struct udevice; + +/** + * struct hwspinlock - A handle to (allowing control of) a single hardware + * spinlock. + * + * @dev: The device which implements the hardware spinlock. + * @id: The hardware spinlock ID within the provider. + */ +struct hwspinlock { + struct udevice *dev; + unsigned long id; +}; + +#if CONFIG_IS_ENABLED(DM_HWSPINLOCK) + +/** + * hwspinlock_get_by_index - Get a hardware spinlock by integer index + * + * This looks up and request a hardware spinlock. The index is relative to the + * client device; each device is assumed to have n hardware spinlock associated + * with it somehow, and this function finds and requests one of them. + * + * @dev: The client device. + * @index: The index of the hardware spinlock to request, within the + * client's list of hardware spinlock. + * @hws: A pointer to a hardware spinlock struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int hwspinlock_get_by_index(struct udevice *dev, + int index, struct hwspinlock *hws); + +/** + * Lock the hardware spinlock + * + * @hws: A hardware spinlock struct that previously requested by + * hwspinlock_get_by_index + * @timeout: Timeout value in msecs + * @return: 0 if OK, -ETIMEDOUT if timeout, -ve on other errors + */ +int hwspinlock_lock_timeout(struct hwspinlock *hws, unsigned int timeout); + +/** + * Unlock the hardware spinlock + * + * @hws: A hardware spinlock struct that previously requested by + * hwspinlock_get_by_index + * @return: 0 if OK, -ve on error + */ +int hwspinlock_unlock(struct hwspinlock *hws); + +#else + +static inline int hwspinlock_get_by_index(struct udevice *dev, + int index, + struct hwspinlock *hws) +{ + return -ENOSYS; +} + +static inline int hwspinlock_lock_timeout(struct hwspinlock *hws, + int timeout) +{ + return -ENOSYS; +} + +static inline int hwspinlock_unlock(struct hwspinlock *hws) +{ + return -ENOSYS; +} + +#endif /* CONFIG_DM_HWSPINLOCK */ + +struct ofnode_phandle_args; + +/** + * struct hwspinlock_ops - Driver model hwspinlock operations + * + * The uclass interface is implemented by all hwspinlock devices which use + * driver model. + */ +struct hwspinlock_ops { + /** + * of_xlate - Translate a client's device-tree (OF) hardware specifier. + * + * The hardware core calls this function as the first step in + * implementing a client's hwspinlock_get_by_*() call. + * + * @hws: The hardware spinlock struct to hold the translation + * result. + * @args: The hardware spinlock specifier values from device tree. + * @return 0 if OK, or a negative error code. + */ + int (*of_xlate)(struct hwspinlock *hws, + struct ofnode_phandle_args *args); + + /** + * Lock the hardware spinlock + * + * @dev: hwspinlock Device + * @index: index of the lock to be used + * @return 0 if OK, -ve on error + */ + int (*lock)(struct udevice *dev, int index); + + /** + * Unlock the hardware spinlock + * + * @dev: hwspinlock Device + * @index: index of the lock to be unlocked + * @return 0 if OK, -ve on error + */ + int (*unlock)(struct udevice *dev, int index); + + /** + * Relax - optional + * Platform-specific relax method, called by hwspinlock core + * while spinning on a lock, between two successive call to + * lock + * + * @dev: hwspinlock Device + */ + void (*relax)(struct udevice *dev); +}; + +#endif /* _HWSPINLOCK_H_ */ diff --git a/test/dm/Makefile b/test/dm/Makefile index b490cf2862..9b3b0bf202 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_CLK) += clk.o obj-$(CONFIG_DM_ETH) += eth.o obj-$(CONFIG_FIRMWARE) += firmware.o obj-$(CONFIG_DM_GPIO) += gpio.o +obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock.o obj-$(CONFIG_DM_I2C) += i2c.o obj-$(CONFIG_LED) += led.o obj-$(CONFIG_DM_MAILBOX) += mailbox.o diff --git a/test/dm/hwspinlock.c b/test/dm/hwspinlock.c new file mode 100644 index 0000000000..09ec38b4f3 --- /dev/null +++ b/test/dm/hwspinlock.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Test that hwspinlock driver functions are called */ +static int dm_test_hwspinlock_base(struct unit_test_state *uts) +{ + struct sandbox_state *state = state_get_current(); + struct hwspinlock hws; + + ut_assertok(uclass_get_device(UCLASS_HWSPINLOCK, 0, &hws.dev)); + ut_assertnonnull(hws.dev); + ut_asserteq(false, state->hwspinlock); + + hws.id = 0; + ut_assertok(hwspinlock_lock_timeout(&hws, 1)); + ut_asserteq(true, state->hwspinlock); + + ut_assertok(hwspinlock_unlock(&hws)); + ut_asserteq(false, state->hwspinlock); + + ut_assertok(hwspinlock_lock_timeout(&hws, 1)); + ut_assertok(!hwspinlock_lock_timeout(&hws, 1)); + + ut_assertok(hwspinlock_unlock(&hws)); + ut_assertok(!hwspinlock_unlock(&hws)); + + return 0; +} + +DM_TEST(dm_test_hwspinlock_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); From patchwork Wed Nov 14 09:01:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 151050 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp5437700ljp; Wed, 14 Nov 2018 01:03:45 -0800 (PST) X-Google-Smtp-Source: AJdET5eeS6Rw95uwi8tQPcH9GI1xncqbItYnXjb9lCdzL5eX7Fw4JQ6dx8TE3s1Nb/QvKbcucOjZ X-Received: by 2002:a17:906:f14e:: with SMTP id gw14-v6mr1202977ejb.231.1542186225521; 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[81.169.180.215]) by mx.google.com with ESMTP id y18-v6si2167870ejg.151.2018.11.14.01.03.45; Wed, 14 Nov 2018 01:03:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=XsVWRdQX; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id D6321C22081; Wed, 14 Nov 2018 09:02:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A5A52C22079; Wed, 14 Nov 2018 09:01:51 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E2AB6C2207C; Wed, 14 Nov 2018 09:01:37 +0000 (UTC) Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by lists.denx.de (Postfix) with ESMTPS id 17B95C22075 for ; Wed, 14 Nov 2018 09:01:34 +0000 (UTC) Received: by mail-wm1-f66.google.com with SMTP id i73-v6so9316583wmd.5 for ; Wed, 14 Nov 2018 01:01:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/CmlmCmViZQAz4cyHIO2o3IkVmiv6Tq2TnwqaDNM8mQ=; b=XsVWRdQXse8rG6tQ1ve/MVw6TCb9UrQg74DPILYORHJtzNFBaD3sAM1AjbgMeAHX92 93EvoCJEN79615QkZpYx/CQaWDcCnASPzySR4GAMY4uosKH0HxaER78KmEFfonEhPs1V Bo5/GQ9FIzkvwTg7s72Pc52pne/w246RzvKiA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/CmlmCmViZQAz4cyHIO2o3IkVmiv6Tq2TnwqaDNM8mQ=; b=mezoUuUFDjpffF9VfOgJoNapPcu8rloE1/Knf6EN8FB+SuYe3ZOz2xUJbxIBVt4ti2 TR8rUujzlznf/e+cI8deRFeHj8X+8o0uoYKjywgmlH5CwDVjsUi1vzVUihVtY5D2xDIS vhfiItkGdYG+Q7wwZ0yeXdFV8tNr8wx6SGRolVRmU6JIiBrWcrc6fXqdICSvd8pwItbs n9S6uNhticKEjao6NgplZQJhDu9ddjdyezc6ht+eC/KUwMV0SG5h08P0NvvoT+3YQjWR PEAwMbslGkpu7iOUuTTRKva4H2Ou5UV9iKy6PXRDiNX51QEEyMYGf1HNYde26JU1cipS mQ1g== X-Gm-Message-State: AGRZ1gI3fLh5L1AAIZAfXbRJXyplQSOwEzC3Ifs3ZPdG/5BFQDtUTw5M pCm739O6jhD4aUN1dkkm9rkJhg== X-Received: by 2002:a1c:8314:: with SMTP id f20-v6mr1145113wmd.120.1542186093705; Wed, 14 Nov 2018 01:01:33 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1088:2b4c:4d39:8b22:d570:822a]) by smtp.gmail.com with ESMTPSA id j125-v6sm14474871wmb.12.2018.11.14.01.01.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Nov 2018 01:01:33 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: patrick.delaunay@st.com, albert.u.boot@aribaud.net, sjg@chromium.org, christophe.kerello@st.com, patrice.chotard@st.com Date: Wed, 14 Nov 2018 10:01:12 +0100 Message-Id: <20181114090114.7727-3-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181114090114.7727-1-benjamin.gaignard@st.com> References: <20181114090114.7727-1-benjamin.gaignard@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 2/4] clk: stm32: add hardware spinlock clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Benjamin Gaignard Add hardware spinlock in the list of the clocks. Signed-off-by: Benjamin Gaignard Reviewed-by: Simon Glass Reviewed-by: Patrice Chotard --- drivers/clk/clk_stm32mp1.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 6a8c7b754f..b7c5d34fe0 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -104,6 +104,7 @@ #define RCC_MP_APB2ENSETR 0XA08 #define RCC_MP_APB3ENSETR 0xA10 #define RCC_MP_AHB2ENSETR 0xA18 +#define RCC_MP_AHB3ENSETR 0xA20 #define RCC_MP_AHB4ENSETR 0xA28 /* used for most of SELR register */ @@ -534,6 +535,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), From patchwork Wed Nov 14 09:01:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 151048 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp5436148ljp; Wed, 14 Nov 2018 01:02:10 -0800 (PST) X-Google-Smtp-Source: AJdET5ftUOtpoyYI9LmnuoFG7+jFxWSmjvUtylcI5Xv9Mm8Dhln3QxTMYBIQL0TeOf+ozYhW0z/i X-Received: by 2002:a17:906:5053:: with SMTP id e19-v6mr1214690ejk.223.1542186130384; Wed, 14 Nov 2018 01:02:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542186130; cv=none; d=google.com; s=arc-20160816; b=WYaiw8ZT3UZXHACxyAhU06r3a8+GApyOYNf/1TineK/XBlmZcpMhwvLtoagV+m8Ob7 y9CW06A4B7D6IoHUphMRvI+9M0YcWCaGYF4n/C8KTw1f58Qm65iNgDcwxa6gDMKHrCiM b30s+XnNxms63C3Xa0UOWgX0Sr77nxLFCHZgxpjm1I56cIBIVqXrHPkV7gpnHm0j697/ fpLa6qsfpFkQrQznjko2rYeJcZSqXNeNkZe+nic6c+F9RynE3AKqNqrvj4dxuBNy91ZX Ku/QXSGZDP7eKH21c+9ajYtXNJaPTQIbuHjXMOnbhyuXimkynhHPoTWcOrWUxosfc1dM vKhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature; bh=dk3a5ZMLVo7f1FggWXNrCxYhZ3LVF3ctNnlZAxDHfz0=; b=vQCXm06dvR+agaETfO+b6kX2+BVBpq/YcSmQatawARg+xe4zVQAVTpEdY232ANob+H N3UUwhjruf38IAFAH6E8M0uPnGA0TjTQt+lr6JEWE5P+a1kuLUABmo55jdkbytvTeVh6 E0+E/2diH/Q9UvrdplboCxsBIbr+e0iM0CHGT5u4OSAb9ywQn/NKGz8p1cDZe1acxp5d sX4hpv3DQ5U25/ReWlzUJCorDjytzhppsvX5i6EH1ODYmLMZSXFcjBYFsDa8Se9mUOUq wIwaBqJoZRNT2RojPB2jhM1Bq4g5ETIGfASRvHIAeOcJQSCcBQu3/EfFLwoczIr4uXhh vdaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=YRsZIdPb; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id q24si755059edc.335.2018.11.14.01.02.09; Wed, 14 Nov 2018 01:02:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=YRsZIdPb; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id BD5B2C224B6; Wed, 14 Nov 2018 09:01:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A582CC2206C; Wed, 14 Nov 2018 09:01:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2B6C0C224B5; Wed, 14 Nov 2018 09:01:39 +0000 (UTC) Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by lists.denx.de (Postfix) with ESMTPS id 58A3BC2207D for ; Wed, 14 Nov 2018 09:01:36 +0000 (UTC) Received: by mail-wm1-f68.google.com with SMTP id q26so3919735wmf.5 for ; Wed, 14 Nov 2018 01:01:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7G1T/qn3Ds1FMKan4FxdEZTvvsyHqR+Fcp5F18FSOL0=; b=YRsZIdPbERK8lQiT2++ZoHvCV1NAsijQyEkuc/E/f1sXOpnnuj1zVKwRuX5MVleB+O 8A7nGlaBRrIhb/bUoOODDV/FZBCc5Z8TAXgmLvm179eDldcT755QyL2w59JhgGPnqUS8 TlnsxCFeF+MhDB4xbcK+AwkG/SIUjCflzGirE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7G1T/qn3Ds1FMKan4FxdEZTvvsyHqR+Fcp5F18FSOL0=; b=nnAmQ2SuATdgj2lDJgUry7xscR0SMaP1l5noeBt4aGPxGxKQp6DZigpKShlBY+g2ar 7ZwOdD+0rFrkThs8CLRNNPSe3btylWvmXr9aeUu07m3Efv2JmNkqLJhl1PzAe9CM9of3 Zkj/+GojSiIUd8sP/U7q1dDCBDhO+f1iuZdt0g7qdGWpl/V12POt89Z7LHIVuJya3XAo S3Kofj5WMZt3u5vwZ4T+jQp7oXh9ZJLTKaqwso5tBnuzTIEJxt1mXQ1P3ziKJw+U9o/P qUu9J4vfqPIZkkgAjQ0KZ0dIVgClTcbpqtt5IujI94Uaqrk+cFZyCbGRVZCfhekenBwf sgSg== X-Gm-Message-State: AGRZ1gJeZxEoV4jQsWjDeECP7PvjIO8qrL3EAprLn5dxfYnCB+8IJBTu AmNyreF4QXX/Uhcy9j8O92yhOQ== X-Received: by 2002:a1c:8604:: with SMTP id i4-v6mr1129463wmd.23.1542186095922; Wed, 14 Nov 2018 01:01:35 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1088:2b4c:4d39:8b22:d570:822a]) by smtp.gmail.com with ESMTPSA id j125-v6sm14474871wmb.12.2018.11.14.01.01.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Nov 2018 01:01:35 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: patrick.delaunay@st.com, albert.u.boot@aribaud.net, sjg@chromium.org, christophe.kerello@st.com, patrice.chotard@st.com Date: Wed, 14 Nov 2018 10:01:13 +0100 Message-Id: <20181114090114.7727-4-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181114090114.7727-1-benjamin.gaignard@st.com> References: <20181114090114.7727-1-benjamin.gaignard@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de, Benjamin Gaignard Subject: [U-Boot] [PATCH v2 3/4] hwspinlock: add stm32 hardware spinlock support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Implement hardware spinlock support for STM32MP1. Signed-off-by: Benjamin Gaignard Reviewed-by: Simon Glass Reviewed-by: Patrice Chotard --- version 2: - remove useless include - add a private structure to store base address - be more verbose in configuration flag description arch/arm/dts/stm32mp157c-ed1.dts | 4 ++ arch/arm/dts/stm32mp157c.dtsi | 9 ++++ configs/stm32mp15_basic_defconfig | 2 + drivers/hwspinlock/Kconfig | 8 +++ drivers/hwspinlock/Makefile | 1 + drivers/hwspinlock/stm32_hwspinlock.c | 92 +++++++++++++++++++++++++++++++++++ 6 files changed, 116 insertions(+) create mode 100644 drivers/hwspinlock/stm32_hwspinlock.c diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index f8b7701167..fc277dd7d2 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -365,6 +365,10 @@ usb33d-supply = <&usb33>; }; +&hwspinlock { + status = "okay"; +}; + &usbphyc_port0 { phy-supply = <&vdd_usb>; vdda1v1-supply = <®11>; diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi index 33c5981869..37cadfa30c 100644 --- a/arch/arm/dts/stm32mp157c.dtsi +++ b/arch/arm/dts/stm32mp157c.dtsi @@ -690,6 +690,15 @@ status = "disabled"; }; + hwspinlock: hwspinlock@4c000000 { + compatible = "st,stm32-hwspinlock"; + #hwlock-cells = <1>; + reg = <0x4c000000 0x400>; + clocks = <&rcc HSEM>; + clock-names = "hwspinlock"; + status = "disabled"; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 3bf7538089..c8409fd04e 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -32,6 +32,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" CONFIG_STM32_ADC=y +CONFIG_DM_HWSPINLOCK=y +CONFIG_HWSPINLOCK_STM32=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig index de367fd2a9..96d4f5d6ca 100644 --- a/drivers/hwspinlock/Kconfig +++ b/drivers/hwspinlock/Kconfig @@ -13,4 +13,12 @@ config HWSPINLOCK_SANDBOX can be probed and support all the methods of HWSPINLOCK, but does not really do anything. +config HWSPINLOCK_STM32 + bool "Enable Hardware Spinlock support for STM32" + depends on ARCH_STM32MP && DM_HWSPINLOCK + help + Enable hardware spinlock support in STM32MP. Hardware spinlocks are + hardware mutex which provide a synchronisation mechanism for the + various processors on the SoC. + endmenu diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile index 2704d6814f..289b12a256 100644 --- a/drivers/hwspinlock/Makefile +++ b/drivers/hwspinlock/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock-uclass.o obj-$(CONFIG_HWSPINLOCK_SANDBOX) += sandbox_hwspinlock.o +obj-$(CONFIG_HWSPINLOCK_STM32) += stm32_hwspinlock.o diff --git a/drivers/hwspinlock/stm32_hwspinlock.c b/drivers/hwspinlock/stm32_hwspinlock.c new file mode 100644 index 0000000000..a32bde4906 --- /dev/null +++ b/drivers/hwspinlock/stm32_hwspinlock.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include + +#define STM32_MUTEX_COREID BIT(8) +#define STM32_MUTEX_LOCK_BIT BIT(31) +#define STM32_MUTEX_NUM_LOCKS 32 + +struct stm32mp1_hws_priv { + fdt_addr_t base; +}; + +static int stm32mp1_lock(struct udevice *dev, int index) +{ + struct stm32mp1_hws_priv *priv = dev_get_priv(dev); + u32 status; + + if (index >= STM32_MUTEX_NUM_LOCKS) + return -EINVAL; + + status = readl(priv->base + index * sizeof(u32)); + if (status == (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID)) + return -EBUSY; + + writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID, + priv->base + index * sizeof(u32)); + + status = readl(priv->base + index * sizeof(u32)); + if (status != (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID)) + return -EINVAL; + + return 0; +} + +static int stm32mp1_unlock(struct udevice *dev, int index) +{ + struct stm32mp1_hws_priv *priv = dev_get_priv(dev); + + if (index >= STM32_MUTEX_NUM_LOCKS) + return -EINVAL; + + writel(STM32_MUTEX_COREID, priv->base + index * sizeof(u32)); + + return 0; +} + +static int stm32mp1_hwspinlock_probe(struct udevice *dev) +{ + struct stm32mp1_hws_priv *priv = dev_get_priv(dev); + struct clk clk; + int ret; + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + clk_free(&clk); + + return ret; +} + +static const struct hwspinlock_ops stm32mp1_hwspinlock_ops = { + .lock = stm32mp1_lock, + .unlock = stm32mp1_unlock, +}; + +static const struct udevice_id stm32mp1_hwspinlock_ids[] = { + { .compatible = "st,stm32-hwspinlock" }, + {} +}; + +U_BOOT_DRIVER(hwspinlock_stm32mp1) = { + .name = "hwspinlock_stm32mp1", + .id = UCLASS_HWSPINLOCK, + .of_match = stm32mp1_hwspinlock_ids, + .ops = &stm32mp1_hwspinlock_ops, + .probe = stm32mp1_hwspinlock_probe, + .priv_auto_alloc_size = sizeof(struct stm32mp1_hws_priv), +}; From patchwork Wed Nov 14 09:01:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 151051 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp5438132ljp; Wed, 14 Nov 2018 01:04:10 -0800 (PST) X-Google-Smtp-Source: AJdET5cqemJ+DgdjFC4Mrp55USIvsxS1UkdRzgIIggOyXaxK2aWS+fQwTV4VvWvHpZpyIkl4elQp X-Received: by 2002:a50:8907:: with SMTP id e7mr1372120ede.252.1542186250231; Wed, 14 Nov 2018 01:04:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542186250; cv=none; d=google.com; s=arc-20160816; b=L4dGOhvsWnm1VUn+NU7v+7qZQekM9m7m2D4wJqKANljlpfl4pb2YHcEFukUhOEJP/N IDhVRJD6Yr18d2iNHkx/UC8kunR7agga+aMPcbek0GZ8qYNxkeEYgAVBt5Lhrj6NI1fM Dzz96J+pdI9fk7FNHsia2J5PTUTfj8MKibrZ71ABU15+YD0LvE0czmde1Bt68X7sKzvf 5L8ql0cZ7rsHFMpoFQa4Nze/R7yzASInja7qKAvnASRQ1hDV0PcfDvY9UmpMaDjiuVaN 7yWRjtesH8IwmvNz1ePp8ayfmyo+WlCkQj8i1ctlZ9sVCMCrNMlWxzSozcMr5kp5yc8E 1Efg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature; bh=DGnFd3DTS5dUofryqUAeXJDYp//9tcNMnBXMmjdZ2pE=; b=0ttP8GoCcXy1hxf096608yBhyJSGpNohvUU9AAjdI47zdRMQbZRC4uYm4Yd8j7Y4TS Xw3WTYdBg/DiooT+LUBCAq43NppUh35AbfddYBZyobbm+hNV08L2//kasqT/cloZrSlH 0EwauuUaHyAMLY1JUtm13nZdvVlzSzXNpcanOW+QS6wxL5lZwICxuP9hCm4gzuh3iuQB ooN7MPAjKPIWcSb0wT1AB7NedKSlIGeaVsQdJf3Lzx94x+Ecqjd/WDiMwc9bEEysYQ6z bfZcJ2SfzUZcy2uFgWsNY5lWdOwK3mCcyhAGONJdtWsd/+bdFTwlqRUht0d55hsfkNkB iW4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=EMDkDec0; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id i88-v6si778978edd.399.2018.11.14.01.04.09; Wed, 14 Nov 2018 01:04:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=EMDkDec0; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id A3A7CC2206D; Wed, 14 Nov 2018 09:03:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8EEC8C224C4; Wed, 14 Nov 2018 09:01:53 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E5482C2205D; Wed, 14 Nov 2018 09:01:41 +0000 (UTC) Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by lists.denx.de (Postfix) with ESMTPS id 1ACB9C224AA for ; Wed, 14 Nov 2018 09:01:38 +0000 (UTC) Received: by mail-wm1-f65.google.com with SMTP id i73-v6so9316804wmd.5 for ; Wed, 14 Nov 2018 01:01:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LvD5klWzDZi5nk7m6fiOYmn5U+0L2TkxOuVMffXfW2A=; b=EMDkDec02d28iVexeHdvQu9RYRCXXzZMvdvimyaWKySiwwI2VgaXc4B9tS9gofy+ql g8ZLsQsfXXz6zTDSCLbp5x9AZCdTZ2rU23OY5snZNpSAAnrbb9pALmWBbfAt7hQdAF4C VFh66+nSe3RWn9VNtmoF3BsNNM0yhqzM9z3LM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LvD5klWzDZi5nk7m6fiOYmn5U+0L2TkxOuVMffXfW2A=; b=q+IPkWb2xBKwlLnj5vPA6FMoCYoCbTCDE9EnuGOT+BBZRLDAuVpz/EKPrKrqkGTiCe jJilFxSnoth02odoHMzr8uh6eqtd8QdpOo4h4UgHRpG6+vVkM1WrV7rUwNiWtxf+JrO/ 6Sz7uSMss6Ymd1jQI1h5DndaWrz8MXg5Dz1dvogi1iKb7VDhZ82L97ORaGcmN4Tc9FTd B1JPNXnxoC6ofWeXwvu0CCxY/9STp794BxxxqvTv8sKMW900kUrsedLxAkao+PruuxbV GT0qHO6QjBgLCiJMG706Cqtpu1qbwvjG2lOm5HDd0neACT8D2dM/JsWzvOWU/jyN5MaZ PxTw== X-Gm-Message-State: AGRZ1gK49oqinklkWAOMixTfxoOZie7GYOcMU9ZB746vctjOGuWQYFSS zKjzWkhthDZeFsKPWgi/gq78kQ== X-Received: by 2002:a1c:ce8d:: with SMTP id e135-v6mr1041424wmg.3.1542186097707; Wed, 14 Nov 2018 01:01:37 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1088:2b4c:4d39:8b22:d570:822a]) by smtp.gmail.com with ESMTPSA id j125-v6sm14474871wmb.12.2018.11.14.01.01.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Nov 2018 01:01:37 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: patrick.delaunay@st.com, albert.u.boot@aribaud.net, sjg@chromium.org, christophe.kerello@st.com, patrice.chotard@st.com Date: Wed, 14 Nov 2018 10:01:14 +0100 Message-Id: <20181114090114.7727-5-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181114090114.7727-1-benjamin.gaignard@st.com> References: <20181114090114.7727-1-benjamin.gaignard@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 4/4] pinctrl: stm32: make pinctrl use hwspinlock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Benjamin Gaignard Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard Reviewed-by: Simon Glass Reviewed-by: Patrice Chotard --- version 2: - be more verbose in commit message - log the error after hwspinlock_get_by_index() arch/arm/dts/stm32mp157c-ed1.dts | 4 ++++ drivers/pinctrl/pinctrl_stm32.c | 27 +++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index fc277dd7d2..7a9b742d36 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -369,6 +369,10 @@ status = "okay"; }; +&pinctrl { + hwlocks = <&hwspinlock 0>; +}; + &usbphyc_port0 { phy-supply = <&vdd_usb>; vdda1v1-supply = <®11>; diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 31285cdd57..5b63a2de15 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -1,6 +1,7 @@ #include #include #include +#include #include #include #include @@ -19,12 +20,20 @@ static int stm32_gpio_config(struct gpio_desc *desc, { struct stm32_gpio_priv *priv = dev_get_priv(desc->dev); struct stm32_gpio_regs *regs = priv->regs; + struct hwspinlock *hws = dev_get_priv(desc->dev->parent); u32 index; + int ret; if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 || ctl->pupd > 2 || ctl->speed > 3) return -EINVAL; + ret = hwspinlock_lock_timeout(hws, 1); + if (ret == -ETIME) { + dev_err(desc->dev, "HWSpinlock timeout\n"); + return ret; + } + index = (desc->offset & 0x07) * 4; clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index, ctl->af << index); @@ -39,6 +48,8 @@ static int stm32_gpio_config(struct gpio_desc *desc, index = desc->offset; clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index); + hwspinlock_unlock(hws); + return 0; } @@ -176,6 +187,20 @@ static int stm32_pinctrl_set_state_simple(struct udevice *dev, } #endif /* PINCTRL_FULL */ +static int stm32_pinctrl_probe(struct udevice *dev) +{ + struct hwspinlock *hws = dev_get_priv(dev); + int err; + + /* hwspinlock property is optional, just log the error */ + err = hwspinlock_get_by_index(dev, 0, hws); + if (err) + debug("%s: hwspinlock_get_by_index may have failed (%d)\n", + __func__, err); + + return 0; +} + static struct pinctrl_ops stm32_pinctrl_ops = { #if CONFIG_IS_ENABLED(PINCTRL_FULL) .set_state = stm32_pinctrl_set_state, @@ -200,4 +225,6 @@ U_BOOT_DRIVER(pinctrl_stm32) = { .of_match = stm32_pinctrl_ids, .ops = &stm32_pinctrl_ops, .bind = dm_scan_fdt_dev, + .probe = stm32_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct hwspinlock), };