From patchwork Tue Dec 21 17:39:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 527261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FC4AC433F5 for ; Tue, 21 Dec 2021 18:09:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240946AbhLUSJQ (ORCPT ); Tue, 21 Dec 2021 13:09:16 -0500 Received: from mga18.intel.com ([134.134.136.126]:63849 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240940AbhLUSJN (ORCPT ); Tue, 21 Dec 2021 13:09:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1640110153; x=1671646153; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=4k4x29Qb+0v8l+0y3SmwpANCykxqEpDNAkQhk4vCpjE=; b=kLsrcbriaaN2AA9LlhV6P98QGP2cSy/I+p96H6S6gvwboR6MHAqsJ+AJ Sj+9Miwp14gUs1SC+n3w4pStmICY7tP9yepqEeUiW6KGmg97/A4kMBz5f kogTQszBwQhhAlty3sPwHxUeGBtVUk6s3PFoGvnrWJrkyUKmUix/Rk0dS NpWJT/CcApRQbiGU4gwe71ASmHDvX0nuvm2xUbNXKnhuN1Z7UL1Nekxm1 U1S59rsFwgNPSQraGmmW7VSZ54f/IF7vYf42V5rJkURsCye6jmFXYaLlA CjWa8tnNWOxHRMaCX6DBvRBF/PqfzF41TCekAc6oUcQd5OYIjhw0u0cur w==; X-IronPort-AV: E=McAfee;i="6200,9189,10205"; a="227306802" X-IronPort-AV: E=Sophos;i="5.88,224,1635231600"; d="scan'208";a="227306802" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2021 09:41:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,224,1635231600"; d="scan'208";a="521338928" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga008.jf.intel.com with ESMTP; 21 Dec 2021 09:41:01 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 872F8190; Tue, 21 Dec 2021 19:41:09 +0200 (EET) From: Andy Shevchenko To: Wolfram Sang , Jean Delvare , Heiner Kallweit , Lee Jones , Andy Shevchenko , Tan Jui Nee , Bjorn Helgaas , Mika Westerberg , Hans de Goede , Kate Hsuan , Jonathan Yong , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: Jean Delvare , Peter Tyser , Andy Shevchenko , Linus Walleij , Mark Gross Subject: [PATCH v2 1/8] PCI: Introduce pci_bus_*() printing macros when device is not available Date: Tue, 21 Dec 2021 19:39:38 +0200 Message-Id: <20211221173945.53674-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org In some cases PCI device structure is not available and we want to print information based on the bus and devfn parameters. For this cases introduce pci_bus_*() printing macros and replace in existing users. Signed-off-by: Andy Shevchenko Reviewed-by: Jean Delvare --- drivers/pci/probe.c | 12 +++--------- include/linux/pci.h | 8 ++++++++ 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 78962652f5bf..82014b248f4d 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2333,16 +2333,12 @@ static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, */ while (pci_bus_crs_vendor_id(*l)) { if (delay > timeout) { - pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", - pci_domain_nr(bus), bus->number, - PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); + pci_bus_warn(bus, devfn, "not ready after %dms; giving up\n", delay - 1); return false; } if (delay >= 1000) - pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", - pci_domain_nr(bus), bus->number, - PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); + pci_bus_info(bus, devfn, "not ready after %dms; waiting\n", delay - 1); msleep(delay); delay *= 2; @@ -2352,9 +2348,7 @@ static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, } if (delay >= 1000) - pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", - pci_domain_nr(bus), bus->number, - PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); + pci_bus_info(bus, devfn, "ready after %dms\n", delay - 1); return true; } diff --git a/include/linux/pci.h b/include/linux/pci.h index d4308f847e58..e3c9edd103df 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2484,4 +2484,12 @@ void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); WARN_ONCE(condition, "%s %s: " fmt, \ dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) +#define pci_bus_printk(level, bus, devfn, fmt, arg...) \ + printk(level "pci %04x:%02x:%02x.%d: " fmt, \ + pci_domain_nr(bus), (bus)->number, PCI_SLOT(devfn), PCI_FUNC(devfn), ##arg) + +#define pci_bus_err(bus, devfn, fmt, arg...) pci_bus_printk(KERN_ERR, (bus), devfn, fmt, ##arg) +#define pci_bus_warn(bus, devfn, fmt, arg...) pci_bus_printk(KERN_WARNING, (bus), devfn, fmt, ##arg) +#define pci_bus_info(bus, devfn, fmt, arg...) pci_bus_printk(KERN_INFO, (bus), devfn, fmt, ##arg) + #endif /* LINUX_PCI_H */ From patchwork Tue Dec 21 17:39:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 526698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2939C433FE for ; Tue, 21 Dec 2021 18:09:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240972AbhLUSJN (ORCPT ); Tue, 21 Dec 2021 13:09:13 -0500 Received: from mga18.intel.com ([134.134.136.126]:63849 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240941AbhLUSJH (ORCPT ); Tue, 21 Dec 2021 13:09:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1640110147; x=1671646147; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BM+GedXU52ed9LruLT4278kSKAXmeTbOHJsmjmUCNNk=; b=MK0G9pI2/7pMkY7ONyZpTFDdqOahoWmPiwQHBPpKptxX/EAjdJWkd+IV vA9Dwa48Wykrp1kZS+3Vv1ZdKTy37dLHH51xLaVc8z8TX5MUR+hvLT0mr G4kuj08I/LyuYtQ45BIN3NJufYoSyUm4L4o2ZqMtUyhtWguK0ceeT9UZE js7laX0YvTDMTKw6j5HM1WnLjsu2V0GIe+0cwz7DO/hFDQJ1iImlBjwWW n/rHosryQQUriHc06iRdfDyvQTRzBBMHd5hX7mKosp16mfbLVnjPFR16C 4advah1GhAhsjtKxmTwcnR13nSeu8/foB+3nhbwgeSegfvXMUGLJmdRdb Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10205"; a="227306806" X-IronPort-AV: E=Sophos;i="5.88,224,1635231600"; d="scan'208";a="227306806" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2021 09:41:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,224,1635231600"; d="scan'208";a="521338929" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga008.jf.intel.com with ESMTP; 21 Dec 2021 09:41:01 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 950A1144; Tue, 21 Dec 2021 19:41:09 +0200 (EET) From: Andy Shevchenko To: Wolfram Sang , Jean Delvare , Heiner Kallweit , Lee Jones , Andy Shevchenko , Tan Jui Nee , Bjorn Helgaas , Mika Westerberg , Hans de Goede , Kate Hsuan , Jonathan Yong , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: Jean Delvare , Peter Tyser , Andy Shevchenko , Linus Walleij , Mark Gross Subject: [PATCH v2 2/8] PCI: Convert __pci_read_base() to __pci_bus_read_base() Date: Tue, 21 Dec 2021 19:39:39 +0200 Message-Id: <20211221173945.53674-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211221173945.53674-1-andriy.shevchenko@linux.intel.com> References: <20211221173945.53674-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Some drivers would like to read PCI BAR of the devices which has been not or can't be enumerated. In particular such mechanism is required to read PCI BAR of hidden devices behind Primary to Sideband (P2SB) bridge. Refactor __pci_read_base() to provide __pci_bus_read_base() and represent the former one as static inline helper. Signed-off-by: Andy Shevchenko --- drivers/pci/pci.h | 16 +++++++++-- drivers/pci/probe.c | 69 +++++++++++++++++++++++---------------------- 2 files changed, 50 insertions(+), 35 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 3d60cabde1a1..a03fd2da89b6 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -233,8 +233,20 @@ bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); int pci_setup_device(struct pci_dev *dev); -int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, - struct resource *res, unsigned int reg); + +int __pci_bus_read_base(struct pci_bus *bus, unsigned int devfn, + enum pci_bar_type type, + struct resource *res, unsigned int reg, + bool mmio_always_on); +static inline int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, + struct resource *res, unsigned int reg) +{ + res->name = pci_name(dev); + + return __pci_bus_read_base(dev->bus, dev->devfn, type, res, reg, + dev->mmio_always_on); +} + void pci_configure_ari(struct pci_dev *dev); void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head); diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 82014b248f4d..a5b28073822f 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -130,7 +130,7 @@ static u64 pci_size(u64 base, u64 maxbase, u64 mask) return size; } -static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) +static inline unsigned long decode_bar(u32 bar) { u32 mem_type; unsigned long flags; @@ -166,16 +166,21 @@ static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) /** - * __pci_read_base - Read a PCI BAR - * @dev: the PCI device + * __pci_bus_read_base - Read a PCI BAR + * @bus: the PCI bus + * @devfn: the PCI device and function * @type: type of the BAR * @res: resource buffer to be filled in * @pos: BAR position in the config space + * @mmio_always_on: disallow turning off IO/MEM decoding during BAR sizing * * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. + * In case of error resulting @res->flags is 0. */ -int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, - struct resource *res, unsigned int pos) +int __pci_bus_read_base(struct pci_bus *bus, unsigned int devfn, + enum pci_bar_type type, + struct resource *res, unsigned int pos, + bool mmio_always_on) { u32 l = 0, sz = 0, mask; u64 l64, sz64, mask64; @@ -185,20 +190,18 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, mask = type ? PCI_ROM_ADDRESS_MASK : ~0; /* No printks while decoding is disabled! */ - if (!dev->mmio_always_on) { - pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); + if (!mmio_always_on) { + pci_bus_read_config_word(bus, devfn, PCI_COMMAND, &orig_cmd); if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { - pci_write_config_word(dev, PCI_COMMAND, + pci_bus_write_config_word(bus, devfn, PCI_COMMAND, orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); } } - res->name = pci_name(dev); - - pci_read_config_dword(dev, pos, &l); - pci_write_config_dword(dev, pos, l | mask); - pci_read_config_dword(dev, pos, &sz); - pci_write_config_dword(dev, pos, l); + pci_bus_read_config_dword(bus, devfn, pos, &l); + pci_bus_write_config_dword(bus, devfn, pos, l | mask); + pci_bus_read_config_dword(bus, devfn, pos, &sz); + pci_bus_write_config_dword(bus, devfn, pos, l); /* * All bits set in sz means the device isn't working properly. @@ -217,7 +220,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, l = 0; if (type == pci_bar_unknown) { - res->flags = decode_bar(dev, l); + res->flags = decode_bar(l); res->flags |= IORESOURCE_SIZEALIGN; if (res->flags & IORESOURCE_IO) { l64 = l & PCI_BASE_ADDRESS_IO_MASK; @@ -237,26 +240,25 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, } if (res->flags & IORESOURCE_MEM_64) { - pci_read_config_dword(dev, pos + 4, &l); - pci_write_config_dword(dev, pos + 4, ~0); - pci_read_config_dword(dev, pos + 4, &sz); - pci_write_config_dword(dev, pos + 4, l); + pci_bus_read_config_dword(bus, devfn, pos + 4, &l); + pci_bus_write_config_dword(bus, devfn, pos + 4, ~0); + pci_bus_read_config_dword(bus, devfn, pos + 4, &sz); + pci_bus_write_config_dword(bus, devfn, pos + 4, l); l64 |= ((u64)l << 32); sz64 |= ((u64)sz << 32); mask64 |= ((u64)~0 << 32); } - if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) - pci_write_config_word(dev, PCI_COMMAND, orig_cmd); + if (!mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) + pci_bus_write_config_word(bus, devfn, PCI_COMMAND, orig_cmd); if (!sz64) goto fail; sz64 = pci_size(l64, sz64, mask64); if (!sz64) { - pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", - pos); + pci_bus_info(bus, devfn, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", pos); goto fail; } @@ -266,8 +268,9 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; res->start = 0; res->end = 0; - pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", - pos, (unsigned long long)sz64); + pci_bus_err(bus, devfn, + "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", + pos, (unsigned long long)sz64); goto out; } @@ -276,8 +279,9 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, res->flags |= IORESOURCE_UNSET; res->start = 0; res->end = sz64 - 1; - pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", - pos, (unsigned long long)l64); + pci_bus_info(bus, devfn, + "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", + pos, (unsigned long long)l64); goto out; } } @@ -285,8 +289,8 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, region.start = l64; region.end = l64 + sz64 - 1; - pcibios_bus_to_resource(dev->bus, res, ®ion); - pcibios_resource_to_bus(dev->bus, &inverted_region, res); + pcibios_bus_to_resource(bus, res, ®ion); + pcibios_resource_to_bus(bus, &inverted_region, res); /* * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is @@ -303,18 +307,17 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, res->flags |= IORESOURCE_UNSET; res->start = 0; res->end = region.end - region.start; - pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n", - pos, (unsigned long long)region.start); + pci_bus_info(bus, devfn, "reg 0x%x: initial BAR value %#010llx invalid\n", + pos, (unsigned long long)region.start); } goto out; - fail: res->flags = 0; out: if (res->flags) - pci_info(dev, "reg 0x%x: %pR\n", pos, res); + pci_bus_info(bus, devfn, "reg 0x%x: %pR\n", pos, res); return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; } From patchwork Tue Dec 21 17:39:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 527262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03413C4321E for ; Tue, 21 Dec 2021 18:07:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240910AbhLUSHj (ORCPT ); Tue, 21 Dec 2021 13:07:39 -0500 Received: from mga17.intel.com ([192.55.52.151]:27067 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240895AbhLUSHh (ORCPT ); Tue, 21 Dec 2021 13:07:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1640110056; x=1671646056; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2weH9YLl+uiZq5NoxK5gXa8HMVS6Pv2FeoIswyTQXwQ=; b=nnx/pxmlAJ1GjIKlVN8B2wKkqWv6nqnHLwjez6N9Lxb5GeLj5bC+wwcE w9i4vuO63/pHeayCu25d98J87w3O/TJr03pWC6vg2LntIR6AT8kIF6ofg 14iq2/UAI/7uqHkvC3uked3LtTls2XQObTHA8OS0T8wYpB29HSO+ZbcuU 1Yxd+plOsj6fPHpADTxNwlVNEKLLMuY9df9jhpE7YAUO7N9YQirH8j9hV XSPOPQDieuCFM2DtL9JkojVij0a7KsyVOMGX5buPAFOrh2jB1dr634B9b UwtQv8IbCWTLIs2IzCJi6rtW0blhVftc55ZM3Rpxn7ubkBpEIeb6A0AKX g==; X-IronPort-AV: E=McAfee;i="6200,9189,10205"; a="221132965" X-IronPort-AV: E=Sophos;i="5.88,224,1635231600"; d="scan'208";a="221132965" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2021 09:41:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,224,1635231600"; d="scan'208";a="684739667" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga005.jf.intel.com with ESMTP; 21 Dec 2021 09:41:01 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id AAD1B2D2; Tue, 21 Dec 2021 19:41:09 +0200 (EET) From: Andy Shevchenko To: Wolfram Sang , Jean Delvare , Heiner Kallweit , Lee Jones , Andy Shevchenko , Tan Jui Nee , Bjorn Helgaas , Mika Westerberg , Hans de Goede , Kate Hsuan , Jonathan Yong , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: Jean Delvare , Peter Tyser , Andy Shevchenko , Linus Walleij , Mark Gross Subject: [PATCH v2 3/8] platform/x86/intel: Add Primary to Sideband (P2SB) bridge support Date: Tue, 21 Dec 2021 19:39:40 +0200 Message-Id: <20211221173945.53674-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211221173945.53674-1-andriy.shevchenko@linux.intel.com> References: <20211221173945.53674-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Jonathan Yong There are already two and at least one more user is coming which require an access to Primary to Sideband (P2SB) bridge in order to get IO or MMIO BAR hidden by BIOS. Create a library to access P2SB for x86 devices. Background information ====================== Note, the term "bridge" is used in the documentation and it has nothing to do with a PCI (host) bridge as per the PCI specifications. The P2SB is an interesting device by it's nature and hardware design. First of all, it has several devices in the hardware behind it. These devices may or may not be represented as ACPI devices by a firmware. It also has a hardwired (to 0s) the least significant part of the address space which is represented by the only 64-bit BAR0. It means that OS mustn't reallocate the BAR. On top of that in some cases P2SB is represented by function 0 on PCI slot (in terms of B:D.F) and according to the PCI specification any other function can't be seen until function 0 is present and visible. In the PCI configuration space of P2SB device the full 32-bit register is allocated for the only purpose of hiding the entire P2SB device. 3.1.39 P2SB Control (P2SBC)—Offset E0h Hide Device (HIDE): When this bit is set, the P2SB will return 1s on any PCI Configuration Read on IOSF-P. All other transactions including PCI Configuration Writes on IOSF-P are unaffected by this. This does not affect reads performed on the IOSF-SB interface. This doesn't prevent MMIO accesses though. In order to prevent OS from the assignment to these addresses, the firmware on the affected platforms marks the region as unusable (by cutting it off from the PCI host bridge resources) as depicted in the Apollo Lake example below: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [io 0x0070-0x0077] pci_bus 0000:00: root bus resource [io 0x0000-0x006f window] pci_bus 0000:00: root bus resource [io 0x0078-0x0cf7 window] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] pci_bus 0000:00: root bus resource [mem 0x7c000001-0x7fffffff window] pci_bus 0000:00: root bus resource [mem 0x7b800001-0x7bffffff window] pci_bus 0000:00: root bus resource [mem 0x80000000-0xcfffffff window] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xefffffff window] pci_bus 0000:00: root bus resource [bus 00-ff] The P2SB 16MB BAR is located at 0xd0000000-0xd0ffffff memory window. The generic solution ==================== The generic solution for all cases when we need to access to the information behind P2SB device is a library code where users ask for necessary resources by demand and hence those users take care of not being run on the systems where this access is not required. The library provides the p2sb_bar() API to retrieve the MMIO of the BAR0 of the device from P2SB device slot. P2SB unconditional unhiding awareness ===================================== Technically it's possible to unhinde the P2SB device and devices on the same PCI slot and access them at any time as needed. But there are several potential issues with that: - the systems were never tested against such configuration and hence nobody knows what kind of bugs it may bring, especially when we talk about SPI NOR case which contains IFWI code (including BIOS) and already known to be problematic in the past for end users - the PCI by it's nature is a hotpluggable bus and in case somebody attaches a driver to the functions of a P2SB slot device(s) the end user experience and system behaviour can be unpredictable - the kernel code would need some ugly hacks (or code looking as an ugly hack) under arch/x86/pci in order to enable these devices on only selected platforms (which may include CPU ID table followed by a potentially growing number of DMI strings The future improvements ======================= The future improvements with this code may go in order to gain some kind of cache, if it's possible at all, to prevent unhiding and hiding to many times to take static information that may be saved once per boot. Links ===== [1]: https://lab.whitequark.org/notes/2017-11-08/accessing-intel-ich-pch-gpios/ [2]: https://lab.whitequark.org/files/gpioke/Intel-332690-004EN.pdf [3]: https://lab.whitequark.org/files/gpioke/Intel-332691-002EN.pdf [4]: https://medium.com/@jacksonchen_43335/bios-gpio-p2sb-70e9b829b403 Signed-off-by: Jonathan Yong Co-developed-by: Andy Shevchenko Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel/Kconfig | 12 ++++ drivers/platform/x86/intel/Makefile | 2 + drivers/platform/x86/intel/p2sb.c | 93 ++++++++++++++++++++++++++ include/linux/platform_data/x86/p2sb.h | 27 ++++++++ 4 files changed, 134 insertions(+) create mode 100644 drivers/platform/x86/intel/p2sb.c create mode 100644 include/linux/platform_data/x86/p2sb.h diff --git a/drivers/platform/x86/intel/Kconfig b/drivers/platform/x86/intel/Kconfig index 38ce3e344589..e0cc64dcf72c 100644 --- a/drivers/platform/x86/intel/Kconfig +++ b/drivers/platform/x86/intel/Kconfig @@ -81,6 +81,18 @@ config INTEL_OAKTRAIL enable/disable the Camera, WiFi, BT etc. devices. If in doubt, say Y here; it will only load on supported platforms. +config P2SB + bool "Primary to Sideband (P2SB) bridge access support" + depends on PCI + help + The Primary to Sideband (P2SB) bridge is an interface to some + PCI devices connected through it. In particular, SPI NOR controller + in Intel Apollo Lake SoC is one of such devices. + + The main purpose of this library is to unhide P2SB device in case + firmware kept it hidden on some platforms in order to access devices + behind it. + config INTEL_BXTWC_PMIC_TMU tristate "Intel Broxton Whiskey Cove TMU Driver" depends on INTEL_SOC_PMIC_BXTWC diff --git a/drivers/platform/x86/intel/Makefile b/drivers/platform/x86/intel/Makefile index 7c24be2423d8..b1f74b3f9c29 100644 --- a/drivers/platform/x86/intel/Makefile +++ b/drivers/platform/x86/intel/Makefile @@ -26,6 +26,8 @@ intel_int0002_vgpio-y := int0002_vgpio.o obj-$(CONFIG_INTEL_INT0002_VGPIO) += intel_int0002_vgpio.o intel_oaktrail-y := oaktrail.o obj-$(CONFIG_INTEL_OAKTRAIL) += intel_oaktrail.o +intel_p2sb-y := p2sb.o +obj-$(CONFIG_P2SB) += intel_p2sb.o # Intel PMIC / PMC / P-Unit drivers intel_bxtwc_tmu-y := bxtwc_tmu.o diff --git a/drivers/platform/x86/intel/p2sb.c b/drivers/platform/x86/intel/p2sb.c new file mode 100644 index 000000000000..b47517572310 --- /dev/null +++ b/drivers/platform/x86/intel/p2sb.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Primary to Sideband (P2SB) bridge access support + * + * Copyright (c) 2017, 2021 Intel Corporation. + * + * Authors: Andy Shevchenko + * Jonathan Yong + */ + +#include +#include +#include +#include + +/* For __pci_bus_read_base(), which is available for the PCI subsystem */ +#include <../../../pci/pci.h> + +#include +#include + +#define P2SBC_HIDE_BYTE 0xe1 +#define P2SBC_HIDE_BIT BIT(0) + +static const struct x86_cpu_id p2sb_cpu_ids[] = { + X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, PCI_DEVFN(13, 0)), + {} +}; + +static int p2sb_get_devfn(unsigned int *devfn) +{ + const struct x86_cpu_id *id; + + id = x86_match_cpu(p2sb_cpu_ids); + if (!id) + return -ENODEV; + + *devfn = (unsigned int)id->driver_data; + return 0; +} + +/** + * p2sb_bar - Get Primary to Sideband (P2SB) bridge device BAR + * @bus: PCI bus to communicate with + * @devfn: PCI slot and function to communicate with + * @mem: memory resource to be filled in + * + * The BIOS prevents the P2SB device from being enumerated by the PCI + * subsystem, so we need to unhide and hide it back to lookup the BAR. + * + * if @bus is NULL, the bus 0 in domain 0 will be in use. + * If @devfn is 0, it will be replaced by devfn of the P2SB device. + * + * Caller must provide a valid pointer to @mem. + * + * Locking is handled by pci_rescan_remove_lock mutex. + * + * Return: + * 0 on success or appropriate errno value on error. + */ +int p2sb_bar(struct pci_bus *bus, unsigned int devfn, struct resource *mem) +{ + unsigned int devfn_p2sb; + int ret; + + /* Get devfn for P2SB device itself */ + ret = p2sb_get_devfn(&devfn_p2sb); + if (ret) + return ret; + + /* if @pdev is NULL, use bus 0 in domain 0 */ + bus = bus ?: pci_find_bus(0, 0); + + /* If @devfn is 0, replace it with devfn of P2SB device itself */ + devfn = devfn ?: devfn_p2sb; + + pci_lock_rescan_remove(); + + /* Unhide the P2SB device */ + pci_bus_write_config_byte(bus, devfn_p2sb, P2SBC_HIDE_BYTE, 0); + + /* Read the first BAR of the device in question */ + __pci_bus_read_base(bus, devfn, pci_bar_unknown, mem, PCI_BASE_ADDRESS_0, true); + + /* Hide the P2SB device */ + pci_bus_write_config_byte(bus, devfn_p2sb, P2SBC_HIDE_BYTE, P2SBC_HIDE_BIT); + + pci_unlock_rescan_remove(); + + pci_bus_info(bus, devfn, "BAR: %pR\n", mem); + return 0; +} +EXPORT_SYMBOL_GPL(p2sb_bar); diff --git a/include/linux/platform_data/x86/p2sb.h b/include/linux/platform_data/x86/p2sb.h new file mode 100644 index 000000000000..2f71de65aee4 --- /dev/null +++ b/include/linux/platform_data/x86/p2sb.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Primary to Sideband (P2SB) bridge access support + */ + +#ifndef _PLATFORM_DATA_X86_P2SB_H +#define _PLATFORM_DATA_X86_P2SB_H + +#include + +struct pci_bus; +struct resource; + +#if IS_BUILTIN(CONFIG_P2SB) + +int p2sb_bar(struct pci_bus *bus, unsigned int devfn, struct resource *mem); + +#else /* CONFIG_P2SB */ + +static inline int p2sb_bar(struct pci_bus *bus, unsigned int devfn, struct resource *mem) +{ + return -ENODEV; +} + +#endif /* CONFIG_P2SB is not set */ + +#endif /* _PLATFORM_DATA_X86_P2SB_H */ From patchwork Tue Dec 21 17:39:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 527264 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A43EBC433EF for ; Tue, 21 Dec 2021 18:07:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240860AbhLUSH2 (ORCPT ); Tue, 21 Dec 2021 13:07:28 -0500 Received: from mga02.intel.com ([134.134.136.20]:28871 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236894AbhLUSH2 (ORCPT ); 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d="scan'208";a="521805190" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga007.fm.intel.com with ESMTP; 21 Dec 2021 09:41:01 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id B5A8F331; Tue, 21 Dec 2021 19:41:09 +0200 (EET) From: Andy Shevchenko To: Wolfram Sang , Jean Delvare , Heiner Kallweit , Lee Jones , Andy Shevchenko , Tan Jui Nee , Bjorn Helgaas , Mika Westerberg , Hans de Goede , Kate Hsuan , Jonathan Yong , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: Jean Delvare , Peter Tyser , Andy Shevchenko , Linus Walleij , Mark Gross , Henning Schild Subject: [PATCH v2 4/8] pinctrl: intel: Check against matching data instead of ACPI companion Date: Tue, 21 Dec 2021 19:39:41 +0200 Message-Id: <20211221173945.53674-4-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211221173945.53674-1-andriy.shevchenko@linux.intel.com> References: <20211221173945.53674-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org In some cases we may get a platform device that has ACPI companion which is different to the pin control described in the ACPI tables. This is primarily happens when device is instantiated by board file. In order to allow this device being enumerated, refactor intel_pinctrl_get_soc_data() to check the matching data instead of ACPI companion. Reported-by: Henning Schild Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-intel.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 85750974d182..7d8a7e7b0aef 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1598,16 +1598,14 @@ EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid); const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev) { + const struct intel_pinctrl_soc_data * const *table; const struct intel_pinctrl_soc_data *data = NULL; - const struct intel_pinctrl_soc_data **table; - struct acpi_device *adev; - unsigned int i; - adev = ACPI_COMPANION(&pdev->dev); - if (adev) { - const void *match = device_get_match_data(&pdev->dev); + table = device_get_match_data(&pdev->dev); + if (table) { + struct acpi_device *adev = ACPI_COMPANION(&pdev->dev); + unsigned int i; - table = (const struct intel_pinctrl_soc_data **)match; for (i = 0; table[i]; i++) { if (!strcmp(adev->pnp.unique_id, table[i]->uid)) { data = table[i]; @@ -1621,7 +1619,7 @@ const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_ if (!id) return ERR_PTR(-ENODEV); - table = (const struct intel_pinctrl_soc_data **)id->driver_data; + table = (const struct intel_pinctrl_soc_data * const *)id->driver_data; data = table[pdev->id]; } From patchwork Tue Dec 21 17:39:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 526699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72DF2C433F5 for ; Tue, 21 Dec 2021 18:07:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240928AbhLUSHh (ORCPT ); Tue, 21 Dec 2021 13:07:37 -0500 Received: from mga17.intel.com ([192.55.52.151]:27067 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236894AbhLUSHf (ORCPT ); Tue, 21 Dec 2021 13:07:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1640110055; x=1671646055; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=odfpjb40813bEsnO4F0m5yfmvDKHC6/Q8vBwdpPGyIo=; b=kzFTjdSqBtg8sLNxp/IjrwmtHSXz4EiVI32lOgZed1UXKQOv/RTBB3dV nCeENK2U7cYdYJEIdU05jEk+yyDfMvG5Uryjtw6ppfBqmXtA3ddjOvv+9 Wp3Jgf3djXoMtk0KKBNC+mrjmQQe7/doayhMwyIPdvP22w1wGUlZh2iih gj/t5vpbUtEDAubOqSLwbP9TmSQy6gGlIBi9D/LG61FDAv4d6FkaVcgFG vt1P9QsfIzqwOcaKOCEsFP9qhEm2iafBw46NQ7aMIQh/od4ElamnAMgA6 RZ3rk7ZxfWeaHADYyN5ak62ZstLzmWrJvgbNCpub8bwQ+BL2p1QcUXf3h w==; X-IronPort-AV: E=McAfee;i="6200,9189,10205"; a="221132966" X-IronPort-AV: E=Sophos;i="5.88,224,1635231600"; d="scan'208";a="221132966" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2021 09:41:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,224,1635231600"; d="scan'208";a="684739674" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga005.jf.intel.com with ESMTP; 21 Dec 2021 09:41:01 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id BF6E136F; Tue, 21 Dec 2021 19:41:09 +0200 (EET) From: Andy Shevchenko To: Wolfram Sang , Jean Delvare , Heiner Kallweit , Lee Jones , Andy Shevchenko , Tan Jui Nee , Bjorn Helgaas , Mika Westerberg , Hans de Goede , Kate Hsuan , Jonathan Yong , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: Jean Delvare , Peter Tyser , Andy Shevchenko , Linus Walleij , Mark Gross Subject: [PATCH v2 5/8] mfd: lpc_ich: Factor out lpc_ich_enable_spi_write() Date: Tue, 21 Dec 2021 19:39:42 +0200 Message-Id: <20211221173945.53674-5-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211221173945.53674-1-andriy.shevchenko@linux.intel.com> References: <20211221173945.53674-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Factor out duplicate code to lpc_ich_enable_spi_write() helper function. Signed-off-by: Andy Shevchenko Acked-for-MFD-by: Lee Jones --- drivers/mfd/lpc_ich.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index f10e53187f67..13d8c64318e6 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -1084,12 +1084,21 @@ static int lpc_ich_init_wdt(struct pci_dev *dev) return ret; } +static void lpc_ich_test_spi_write(struct pci_dev *dev, unsigned int devfn, + struct intel_spi_boardinfo *info) +{ + u32 bcr; + + pci_bus_read_config_dword(dev->bus, devfn, BCR, &bcr); + info->writeable = !!(bcr & BCR_WPD); +} + static int lpc_ich_init_spi(struct pci_dev *dev) { struct lpc_ich_priv *priv = pci_get_drvdata(dev); struct resource *res = &intel_spi_res[0]; struct intel_spi_boardinfo *info; - u32 spi_base, rcba, bcr; + u32 spi_base, rcba; info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL); if (!info) @@ -1113,8 +1122,7 @@ static int lpc_ich_init_spi(struct pci_dev *dev) res->start = spi_base + SPIBASE_LPT; res->end = res->start + SPIBASE_LPT_SZ - 1; - pci_read_config_dword(dev, BCR, &bcr); - info->writeable = !!(bcr & BCR_WPD); + lpc_ich_test_spi_write(dev, dev->devfn, info); } break; @@ -1135,8 +1143,7 @@ static int lpc_ich_init_spi(struct pci_dev *dev) res->start = spi_base & 0xfffffff0; res->end = res->start + SPIBASE_APL_SZ - 1; - pci_bus_read_config_dword(bus, spi, BCR, &bcr); - info->writeable = !!(bcr & BCR_WPD); + lpc_ich_test_spi_write(dev, spi, info); } pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1); From patchwork Tue Dec 21 17:39:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 527263 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76F60C433EF for ; Tue, 21 Dec 2021 18:07:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240866AbhLUSHc (ORCPT ); Tue, 21 Dec 2021 13:07:32 -0500 Received: from mga02.intel.com ([134.134.136.20]:28875 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240877AbhLUSHa (ORCPT ); Tue, 21 Dec 2021 13:07:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1640110050; x=1671646050; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E6FZu5u6JQthoClqs6ziOuXmSYlsUAO7E2O5fDyqdsk=; b=DV+HJERzMB3YOq+BqoQOIEq/OUUou2HHy5bqdnuyqj/QGUFJo7zBp8J5 6bLbg20lATL+/q64oqwyjlseBqURx4fUzX4TliW3fWIWVK06HZjkRI6A7 oXy1VWiMlP4tPX2dn3TwynkgYf7oH+M5QusZ4vaNN7sNOSYD3KFvcySK+ hfc24+PrxhMSxe06ETdVxrNRPpT0mwc9Jp2Wc0D/C6W2CyL1R5Knx15mi s0WQ4RjWOl1qnaVGcOZvzXRHAsl4VyuFqBCVd7tzCImZHf8LEMOt+MLjr oyYByUeJvVy7mZ6XXOyilbgkH+SKLME8PQcAEPxJ8n3ccyA/fcB/BjII6 A==; X-IronPort-AV: E=McAfee;i="6200,9189,10205"; a="227751346" X-IronPort-AV: E=Sophos;i="5.88,224,1635231600"; d="scan'208";a="227751346" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2021 09:41:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,224,1635231600"; d="scan'208";a="755891855" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga006.fm.intel.com with ESMTP; 21 Dec 2021 09:41:07 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id C9AD8379; Tue, 21 Dec 2021 19:41:09 +0200 (EET) From: Andy Shevchenko To: Wolfram Sang , Jean Delvare , Heiner Kallweit , Lee Jones , Andy Shevchenko , Tan Jui Nee , Bjorn Helgaas , Mika Westerberg , Hans de Goede , Kate Hsuan , Jonathan Yong , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: Jean Delvare , Peter Tyser , Andy Shevchenko , Linus Walleij , Mark Gross Subject: [PATCH v2 6/8] mfd: lpc_ich: Switch to generic p2sb_bar() Date: Tue, 21 Dec 2021 19:39:43 +0200 Message-Id: <20211221173945.53674-6-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211221173945.53674-1-andriy.shevchenko@linux.intel.com> References: <20211221173945.53674-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Instead of open coding p2sb_bar() functionality we are going to use generic library. There is one more user en route. This is more than just a clean-up. It also fixes a potential issue seen when SPI BAR is 64-bit. The current code works if and only if the PCI BAR of the hidden device is inside 4G address space. In case when firmware decides to go above 4G, we will get a wrong address. Signed-off-by: Andy Shevchenko Acked-for-MFD-by: Lee Jones --- drivers/mfd/Kconfig | 1 + drivers/mfd/lpc_ich.c | 20 ++++++-------------- 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index a21cbdf89477..be3616fe78b8 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -572,6 +572,7 @@ config LPC_ICH tristate "Intel ICH LPC" depends on PCI select MFD_CORE + select P2SB if X86 help The LPC bridge function of the Intel ICH provides support for many functional units. This driver provides needed support for diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index 13d8c64318e6..95dca5434917 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -45,6 +45,7 @@ #include #include #include +#include #define ACPIBASE 0x40 #define ACPIBASE_GPE_OFF 0x28 @@ -69,8 +70,6 @@ #define BCR 0xdc #define BCR_WPD BIT(0) -#define SPIBASE_APL_SZ 4096 - #define GPIOBASE_ICH0 0x58 #define GPIOCTRL_ICH0 0x5C #define GPIOBASE_ICH6 0x48 @@ -1127,26 +1126,19 @@ static int lpc_ich_init_spi(struct pci_dev *dev) break; case INTEL_SPI_BXT: { - unsigned int p2sb = PCI_DEVFN(13, 0); unsigned int spi = PCI_DEVFN(13, 2); - struct pci_bus *bus = dev->bus; + int ret; /* * The P2SB is hidden by BIOS and we need to unhide it in * order to read BAR of the SPI flash device. Once that is * done we hide it again. */ - pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0); - pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0, - &spi_base); - if (spi_base != ~0) { - res->start = spi_base & 0xfffffff0; - res->end = res->start + SPIBASE_APL_SZ - 1; - - lpc_ich_test_spi_write(dev, spi, info); - } + ret = p2sb_bar(dev->bus, spi, res); + if (ret) + return ret; - pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1); + lpc_ich_test_spi_write(dev, spi, info); break; } From patchwork Tue Dec 21 17:39:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 526697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAD6FC433EF for ; Tue, 21 Dec 2021 18:10:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237069AbhLUSKF (ORCPT ); Tue, 21 Dec 2021 13:10:05 -0500 Received: from mga03.intel.com ([134.134.136.65]:42956 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233550AbhLUSKE (ORCPT ); Tue, 21 Dec 2021 13:10:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1640110204; x=1671646204; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3DqlyHFNaDBMcquaHNTfzmoeBsD/R1tWDi1GcZhi78c=; b=ZTX1G14j3pY4pYkoUpW8OlkcDyP2hen0METSR2efVKDTRw5QRUFJ9udC ctTRwexVsvebjdJdgbb6FnkRc/HjVzTEBa3H9PEQP2GeAEbQzMXKLQFSC Q0LtuMLHyeQeSUJsjdxXH/jk5PhPOLeeO1cm9qEqGOFxTlSkOR/a6kZX0 3JRx3CSkGM0tJkFHEptgwV11wrVqJG2CDEEx6pPFIBE4US+K9dniJ36Sw ZVIhMGRmchBZig79FER9xWa3nh0q7ykvRarAZLsK4maiTLNVpUk9Q154f zKTU6bvwCo0xNFLgRA6jiGl7K5DZ5CS6mEWsc+lQjOb3PW23MVELa1TSO w==; X-IronPort-AV: E=McAfee;i="6200,9189,10205"; a="240410807" X-IronPort-AV: E=Sophos;i="5.88,224,1635231600"; d="scan'208";a="240410807" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2021 09:41:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,224,1635231600"; d="scan'208";a="466370835" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga003.jf.intel.com with ESMTP; 21 Dec 2021 09:41:07 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id D43533AE; Tue, 21 Dec 2021 19:41:09 +0200 (EET) From: Andy Shevchenko To: Wolfram Sang , Jean Delvare , Heiner Kallweit , Lee Jones , Andy Shevchenko , Tan Jui Nee , Bjorn Helgaas , Mika Westerberg , Hans de Goede , Kate Hsuan , Jonathan Yong , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: Jean Delvare , Peter Tyser , Andy Shevchenko , Linus Walleij , Mark Gross Subject: [PATCH v2 7/8] mfd: lpc_ich: Add support for pinctrl in non-ACPI system Date: Tue, 21 Dec 2021 19:39:44 +0200 Message-Id: <20211221173945.53674-7-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211221173945.53674-1-andriy.shevchenko@linux.intel.com> References: <20211221173945.53674-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Tan Jui Nee Add support for non-ACPI systems, such as system that uses Advanced Boot Loader (ABL) whereby a platform device has to be created in order to bind with pin control and GPIO. At the moment, Intel Apollo Lake In-Vehicle Infotainment (IVI) system requires a driver to hide and unhide P2SB to lookup P2SB BAR and pass the PCI BAR address to GPIO. Signed-off-by: Tan Jui Nee Co-developed-by: Andy Shevchenko Signed-off-by: Andy Shevchenko --- drivers/mfd/lpc_ich.c | 101 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 100 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index 95dca5434917..563e4ed251fd 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -8,7 +8,8 @@ * Configuration Registers. * * This driver is derived from lpc_sch. - + * + * Copyright (c) 2017, 2021 Intel Corporation * Copyright (c) 2011 Extreme Engineering Solution, Inc. * Author: Aaron Sierra * @@ -42,6 +43,7 @@ #include #include #include +#include #include #include #include @@ -140,6 +142,70 @@ static struct mfd_cell lpc_ich_gpio_cell = { .ignore_resource_conflicts = true, }; +#define APL_GPIO_NORTH 0 +#define APL_GPIO_NORTHWEST 1 +#define APL_GPIO_WEST 2 +#define APL_GPIO_SOUTHWEST 3 +#define APL_GPIO_NR_DEVICES 4 + +/* Offset data for Apollo Lake GPIO controllers */ +#define APL_GPIO_NORTH_OFFSET 0xc50000 +#define APL_GPIO_NORTHWEST_OFFSET 0xc40000 +#define APL_GPIO_WEST_OFFSET 0xc70000 +#define APL_GPIO_SOUTHWEST_OFFSET 0xc00000 + +#define APL_GPIO_IRQ 14 + +static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = { + [APL_GPIO_NORTH] = { + DEFINE_RES_MEM(APL_GPIO_NORTH_OFFSET, 0x1000), + DEFINE_RES_IRQ(APL_GPIO_IRQ), + }, + [APL_GPIO_NORTHWEST] = { + DEFINE_RES_MEM(APL_GPIO_NORTHWEST_OFFSET, 0x1000), + DEFINE_RES_IRQ(APL_GPIO_IRQ), + }, + [APL_GPIO_WEST] = { + DEFINE_RES_MEM(APL_GPIO_WEST_OFFSET, 0x1000), + DEFINE_RES_IRQ(APL_GPIO_IRQ), + }, + [APL_GPIO_SOUTHWEST] = { + DEFINE_RES_MEM(APL_GPIO_SOUTHWEST_OFFSET, 0x1000), + DEFINE_RES_IRQ(APL_GPIO_IRQ), + }, +}; + +/* The order must be in sync with apl_pinctrl_soc_data */ +static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = { + [APL_GPIO_NORTH] = { + .name = "apollolake-pinctrl", + .id = APL_GPIO_NORTH, + .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTH]), + .resources = apl_gpio_resources[APL_GPIO_NORTH], + .ignore_resource_conflicts = true, + }, + [APL_GPIO_NORTHWEST] = { + .name = "apollolake-pinctrl", + .id = APL_GPIO_NORTHWEST, + .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTHWEST]), + .resources = apl_gpio_resources[APL_GPIO_NORTHWEST], + .ignore_resource_conflicts = true, + }, + [APL_GPIO_WEST] = { + .name = "apollolake-pinctrl", + .id = APL_GPIO_WEST, + .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_WEST]), + .resources = apl_gpio_resources[APL_GPIO_WEST], + .ignore_resource_conflicts = true, + }, + [APL_GPIO_SOUTHWEST] = { + .name = "apollolake-pinctrl", + .id = APL_GPIO_SOUTHWEST, + .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_SOUTHWEST]), + .resources = apl_gpio_resources[APL_GPIO_SOUTHWEST], + .ignore_resource_conflicts = true, + }, +}; static struct mfd_cell lpc_ich_spi_cell = { .name = "intel-spi", @@ -1083,6 +1149,33 @@ static int lpc_ich_init_wdt(struct pci_dev *dev) return ret; } +static int lpc_ich_init_pinctrl(struct pci_dev *dev) +{ + struct resource base; + unsigned int i; + int ret; + + /* Check, if GPIO has been exported as an ACPI device */ + if (acpi_dev_present("INT3452", NULL, -1)) + return -EEXIST; + + ret = p2sb_bar(dev->bus, 0, &base); + if (ret) + return ret; + + for (i = 0; i < ARRAY_SIZE(apl_gpio_devices); i++) { + struct resource *mem = &apl_gpio_resources[i][0]; + + /* Fill MEM resource */ + mem->start += base.start; + mem->end += base.start; + mem->flags = base.flags; + } + + return mfd_add_devices(&dev->dev, 0, apl_gpio_devices, + ARRAY_SIZE(apl_gpio_devices), NULL, 0, NULL); +} + static void lpc_ich_test_spi_write(struct pci_dev *dev, unsigned int devfn, struct intel_spi_boardinfo *info) { @@ -1199,6 +1292,12 @@ static int lpc_ich_probe(struct pci_dev *dev, cell_added = true; } + if (priv->chipset == LPC_APL) { + ret = lpc_ich_init_pinctrl(dev); + if (!ret) + cell_added = true; + } + if (lpc_chipset_info[priv->chipset].spi_type) { ret = lpc_ich_init_spi(dev); if (!ret) From patchwork Tue Dec 21 17:39:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 526700 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE168C4321E for ; Tue, 21 Dec 2021 18:07:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240881AbhLUSHb (ORCPT ); Tue, 21 Dec 2021 13:07:31 -0500 Received: from mga02.intel.com ([134.134.136.20]:28871 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240866AbhLUSH3 (ORCPT ); Tue, 21 Dec 2021 13:07:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; 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21 Dec 2021 09:41:07 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id E01C740C; Tue, 21 Dec 2021 19:41:09 +0200 (EET) From: Andy Shevchenko To: Wolfram Sang , Jean Delvare , Heiner Kallweit , Lee Jones , Andy Shevchenko , Tan Jui Nee , Bjorn Helgaas , Mika Westerberg , Hans de Goede , Kate Hsuan , Jonathan Yong , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: Jean Delvare , Peter Tyser , Andy Shevchenko , Linus Walleij , Mark Gross Subject: [PATCH v2 8/8] i2c: i801: convert to use common P2SB accessor Date: Tue, 21 Dec 2021 19:39:45 +0200 Message-Id: <20211221173945.53674-8-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211221173945.53674-1-andriy.shevchenko@linux.intel.com> References: <20211221173945.53674-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Since we have a common P2SB accessor in tree we may use it instead of open coded variants. Replace custom code by pci_p2sb_bar() call. Signed-off-by: Andy Shevchenko --- drivers/i2c/busses/Kconfig | 1 + drivers/i2c/busses/i2c-i801.c | 39 +++++++------------------------ drivers/platform/x86/intel/p2sb.c | 6 +++++ 3 files changed, 16 insertions(+), 30 deletions(-) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 42da31c1ab70..286f3b14712b 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -101,6 +101,7 @@ config I2C_HIX5HD2 config I2C_I801 tristate "Intel 82801 (ICH/PCH)" depends on PCI + select P2SB if X86 select CHECK_SIGNATURE if X86 && DMI select I2C_SMBUS help diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c index 7428cc6af5cc..950a9b444adf 100644 --- a/drivers/i2c/busses/i2c-i801.c +++ b/drivers/i2c/busses/i2c-i801.c @@ -110,6 +110,7 @@ #include #include #include +#include #include #include @@ -139,7 +140,6 @@ #define TCOBASE 0x050 #define TCOCTL 0x054 -#define SBREG_BAR 0x10 #define SBREG_SMBCTRL 0xc6000c #define SBREG_SMBCTRL_DNV 0xcf000c @@ -1474,45 +1474,24 @@ i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev, .version = 4, }; struct resource *res; - unsigned int devfn; - u64 base64_addr; - u32 base_addr; - u8 hidden; + int ret; /* * We must access the NO_REBOOT bit over the Primary to Sideband - * bridge (P2SB). The BIOS prevents the P2SB device from being - * enumerated by the PCI subsystem, so we need to unhide/hide it - * to lookup the P2SB BAR. + * (P2SB) bridge. */ - pci_lock_rescan_remove(); - - devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); - - /* Unhide the P2SB device, if it is hidden */ - pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); - if (hidden) - pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); - - pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); - base64_addr = base_addr & 0xfffffff0; - - pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); - base64_addr |= (u64)base_addr << 32; - - /* Hide the P2SB device, if it was hidden before */ - if (hidden) - pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); - pci_unlock_rescan_remove(); res = &tco_res[1]; + ret = p2sb_bar(pci_dev->bus, 0, res); + if (ret) + return ERR_PTR(ret); + if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) - res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV; + res->start += SBREG_SMBCTRL_DNV; else - res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; + res->start += SBREG_SMBCTRL; res->end = res->start + 3; - res->flags = IORESOURCE_MEM; return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, tco_res, 2, &pldata, sizeof(pldata)); diff --git a/drivers/platform/x86/intel/p2sb.c b/drivers/platform/x86/intel/p2sb.c index b47517572310..916318a7310b 100644 --- a/drivers/platform/x86/intel/p2sb.c +++ b/drivers/platform/x86/intel/p2sb.c @@ -24,6 +24,12 @@ static const struct x86_cpu_id p2sb_cpu_ids[] = { X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, PCI_DEVFN(13, 0)), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, PCI_DEVFN(31, 1)), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D, PCI_DEVFN(31, 1)), + X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, PCI_DEVFN(31, 1)), + X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, PCI_DEVFN(31, 1)), + X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, PCI_DEVFN(31, 1)), + X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, PCI_DEVFN(31, 1)), {} };