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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(40470700001)(70586007)(36756003)(4326008)(356005)(34020700004)(40460700001)(47076005)(26005)(508600001)(186003)(70206006)(82310400004)(7696005)(81166007)(336012)(316002)(36860700001)(2616005)(83380400001)(2906002)(8676002)(426003)(6666004)(5660300002)(7416002)(8936002)(110136005)(54906003)(86362001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2021 17:30:37.4845 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e008a5a2-0118-4c3f-46cb-08d9c3de6fdd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4961 Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Sameer Pujar , linux-kernel@vger.kernel.org, stable@vger.kernel.org, jonathanh@nvidia.com, linux-tegra@vger.kernel.org, digetx@gmail.com, mkumard@nvidia.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" HDA regression is recently reported on Tegra194 based platforms. This happens because "hda2codec_2x" reset does not really exist in Tegra194 and it causes probe failure. All the HDA based audio tests fail at the moment. This underlying issue is exposed by commit c045ceb5a145 ("reset: tegra-bpmp: Handle errors in BPMP response") which now checks return code of BPMP command response. Fix this issue by skipping unavailable reset on Tegra194. Signed-off-by: Sameer Pujar Cc: stable@vger.kernel.org Depends-on: 87f0e46e7559 ("ALSA: hda/tegra: Reset hardware") --- sound/pci/hda/hda_tegra.c | 96 ++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 86 insertions(+), 10 deletions(-) diff --git a/sound/pci/hda/hda_tegra.c b/sound/pci/hda/hda_tegra.c index ea700395..be010cd 100644 --- a/sound/pci/hda/hda_tegra.c +++ b/sound/pci/hda/hda_tegra.c @@ -68,14 +68,21 @@ */ #define TEGRA194_NUM_SDO_LINES 4 +struct hda_tegra_soc { + bool has_hda2codec_2x_reset; +}; + struct hda_tegra { struct azx chip; struct device *dev; - struct reset_control *reset; + struct reset_control *reset_hda; + struct reset_control *reset_hda2hdmi; + struct reset_control *reset_hda2codec_2x; struct clk_bulk_data clocks[3]; unsigned int nclocks; void __iomem *regs; struct work_struct probe_work; + const struct hda_tegra_soc *data; }; #ifdef CONFIG_PM @@ -170,9 +177,26 @@ static int __maybe_unused hda_tegra_runtime_resume(struct device *dev) int rc; if (!chip->running) { - rc = reset_control_assert(hda->reset); - if (rc) + rc = reset_control_assert(hda->reset_hda); + if (rc) { + dev_err(dev, "hda reset assert failed, err: %d\n", rc); + return rc; + } + + rc = reset_control_assert(hda->reset_hda2hdmi); + if (rc) { + dev_err(dev, "hda2hdmi reset assert failed, err: %d\n", + rc); + return rc; + } + + rc = reset_control_assert(hda->reset_hda2codec_2x); + if (rc) { + dev_err(dev, + "hda2codec_2x reset assert failed, err: %d\n", + rc); return rc; + } } rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks); @@ -187,9 +211,27 @@ static int __maybe_unused hda_tegra_runtime_resume(struct device *dev) } else { usleep_range(10, 100); - rc = reset_control_deassert(hda->reset); - if (rc) + rc = reset_control_deassert(hda->reset_hda); + if (rc) { + dev_err(dev, "hda reset deassert failed, err: %d\n", + rc); return rc; + } + + rc = reset_control_deassert(hda->reset_hda2hdmi); + if (rc) { + dev_err(dev, "hda2hdmi reset deassert failed, err: %d\n", + rc); + return rc; + } + + rc = reset_control_deassert(hda->reset_hda2codec_2x); + if (rc) { + dev_err(dev, + "hda2codec_2x reset deassert failed, err: %d\n", + rc); + return rc; + } } return 0; @@ -427,9 +469,17 @@ static int hda_tegra_create(struct snd_card *card, return 0; } +static const struct hda_tegra_soc tegra30_data = { + .has_hda2codec_2x_reset = true, +}; + +static const struct hda_tegra_soc tegra194_data = { + .has_hda2codec_2x_reset = false, +}; + static const struct of_device_id hda_tegra_match[] = { - { .compatible = "nvidia,tegra30-hda" }, - { .compatible = "nvidia,tegra194-hda" }, + { .compatible = "nvidia,tegra30-hda", .data = &tegra30_data }, + { .compatible = "nvidia,tegra194-hda", .data = &tegra194_data }, {}, }; MODULE_DEVICE_TABLE(of, hda_tegra_match); @@ -449,6 +499,10 @@ static int hda_tegra_probe(struct platform_device *pdev) hda->dev = &pdev->dev; chip = &hda->chip; + hda->data = of_device_get_match_data(&pdev->dev); + if (!hda->data) + return -EINVAL; + err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, THIS_MODULE, 0, &card); if (err < 0) { @@ -456,12 +510,34 @@ static int hda_tegra_probe(struct platform_device *pdev) return err; } - hda->reset = devm_reset_control_array_get_exclusive(&pdev->dev); - if (IS_ERR(hda->reset)) { - err = PTR_ERR(hda->reset); + hda->reset_hda = devm_reset_control_get_exclusive(&pdev->dev, "hda"); + if (IS_ERR(hda->reset_hda)) { + err = PTR_ERR(hda->reset_hda); goto out_free; } + hda->reset_hda2hdmi = devm_reset_control_get_exclusive(&pdev->dev, + "hda2hdmi"); + if (IS_ERR(hda->reset_hda2hdmi)) { + err = PTR_ERR(hda->reset_hda2hdmi); + goto out_free; + } + + /* + * "hda2codec_2x" reset is not present on Tegra194. Though DT would + * be updated to reflect this, but to have backward compatibility + * below is necessary. + */ + if (hda->data->has_hda2codec_2x_reset) { + hda->reset_hda2codec_2x = + devm_reset_control_get_exclusive(&pdev->dev, + "hda2codec_2x"); + if (IS_ERR(hda->reset_hda2codec_2x)) { + err = PTR_ERR(hda->reset_hda2codec_2x); + goto out_free; + } + } + hda->clocks[hda->nclocks++].id = "hda"; hda->clocks[hda->nclocks++].id = "hda2hdmi"; hda->clocks[hda->nclocks++].id = "hda2codec_2x"; From patchwork Mon Dec 20 17:30:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sameer Pujar X-Patchwork-Id: 526101 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1D59DC433F5 for ; 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Mon, 20 Dec 2021 17:30:36 +0000 From: Sameer Pujar To: , , , , , Subject: [PATCH v2 2/3] dt-bindings: sound: tegra: Update HDA resets Date: Mon, 20 Dec 2021 23:00:07 +0530 Message-ID: <1640021408-12824-3-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1640021408-12824-1-git-send-email-spujar@nvidia.com> References: <1640021408-12824-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f41f6cf2-f591-4c45-0f1a-08d9c3de8662 X-MS-TrafficTypeDiagnostic: MWHPR12MB1280:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:949; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vqx6VRYP/w96l05bwbgts7mTw2JLEIVExiPGNvmc760dqknFt6+/RcI1PQ42qvYU63CAwISAcoEEWz85J58SxdmVMfcrVPG1XmolgWL7m0/AlQyjugsbc5pG6qZDGWILFWE8G/3oNhK9vmU/akNiW2KUirP2iStpirXiistHUhGxUvF2eoPFGpllIfiZEoUWr5p5YW6eAHpk22dgUUCSrmodU3SO04l+2ZKuglhWIVviU/ZA28w6KGL7LW2IVnbZsGBNJSr/rHwQnPIWqe+4G4wHh5QIYGQcJWy4GHgqj1j3tb9rx4iUtRkIBWVjD0yTFHdK0BuF4ry9zO3xxq0YWyIa41jCZsKBOOsKg+aIbVv75VBDuwQVtCz/fgjgYPKJvJ1MLIVkSIrmH5cXShTEB5DEfqshcxuJn7ORXXooFR2i9R38Zy9XXcOdJBFREE0TLg9W3LSg7D9nJUNgGdvZ3ADeejmpqAWetkch2nmxibZLvbZARDG3sNzWFcWjTGpPyvhoTWtGlhoH2+cV9jkSeyYWGS7cq/AqVy0DMKDk8sFHRMFVv0jyAYmIDSSSdASNj8TMzau5sHHoBGd0h9SFJ0GAChmjh6UF4Qe7yNE5LSqnxf7nD+ef7NTaTOQ2fD1gsTcnYlbnpdzzT0zDu9hgH13DTTmcVCuT07cGJsP4urS35mZ1EdPG0Uqxr25aiadCWaQCNs8dMfe6V+yxSvfk5k48ISMHYuEvG21zryZ+5PFaGkYn+vpNEU3F7h909aVeBYTil1peSJ/FWYD3K200Er9epxQI/lOk9z5++z6y9KYpjgm2KnzZRSci7xpY4O/RYyN9pRiV66K/YfpsXwbnEw== X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(40470700001)(426003)(508600001)(81166007)(7696005)(4744005)(107886003)(5660300002)(7416002)(34020700004)(40460700001)(36756003)(82310400004)(336012)(47076005)(15650500001)(2906002)(316002)(54906003)(4326008)(110136005)(186003)(26005)(6666004)(70206006)(70586007)(36860700001)(356005)(8936002)(83380400001)(2616005)(8676002)(86362001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2021 17:31:15.2646 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f41f6cf2-f591-4c45-0f1a-08d9c3de8662 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1280 Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Sameer Pujar , linux-kernel@vger.kernel.org, jonathanh@nvidia.com, linux-tegra@vger.kernel.org, digetx@gmail.com, mkumard@nvidia.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Tegra194 HDA has only two resets unlike the previous generations of Tegra SoCs. Hence update the reset list accordingly. Signed-off-by: Sameer Pujar Acked-by: Thierry Reding --- .../devicetree/bindings/sound/nvidia,tegra30-hda.yaml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml index b55775e..70dbdff5 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml @@ -50,13 +50,18 @@ properties: - const: hda2codec_2x resets: + minItems: 2 maxItems: 3 reset-names: - items: - - const: hda - - const: hda2hdmi - - const: hda2codec_2x + oneOf: + - items: + - const: hda + - const: hda2hdmi + - const: hda2codec_2x + - items: + - const: hda + - const: hda2hdmi power-domains: maxItems: 1 From patchwork Mon Dec 20 17:30:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sameer Pujar X-Patchwork-Id: 526635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27519C433FE for ; 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Mon, 20 Dec 2021 17:30:40 +0000 From: Sameer Pujar To: , , , , , Subject: [PATCH v2 3/3] arm64: tegra: Remove non existent Tegra194 reset Date: Mon, 20 Dec 2021 23:00:08 +0530 Message-ID: <1640021408-12824-4-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1640021408-12824-1-git-send-email-spujar@nvidia.com> References: <1640021408-12824-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5bfaff71-5cf1-4660-b29b-08d9c3de8875 X-MS-TrafficTypeDiagnostic: BN6PR12MB1457:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:935; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sYrs9g+jP+SykKrX6IMIvrZwc8aQ4NFgJB7ZN8uOXzvJ7sm039b6lcxtip2NXCZFazICgVWqvZfFwVny3B5BgVWxKEv4R10BrvhYY+kwAlxc12cp0gKZ4zT6yG3m8KxqUxDUqZJY1xiNju3jrqfhxtpmuvhdssLBPdHGLQYB4Mn4tXdPiDxluxn0ebjzqmsKt0CUMLrJ553vn43RX6ZWsw9R58sDl5Fzd9re+OrNZq64ID7RcS6RoQp9jeVVr0b//1fdvo83MQ6/sxEMBZQNvWy/gyM6pjTq7vBEWAhnbypEEJwMZe8Kdzc+QIw5KzVaclhRuPtJQiUc1USCRxiBAm6GGSFng1VrrzaFGP7alq6E0V5kd+jI/n556IJFY9EUBj3fUJvGnyTv1BFGPmglhVV8l9MDmo5n3aXPA2PHiTE08hke+Y/Goweh0IPwyhQmywveU/WcI7cC4IjaOsvWcW6AOncIm7Ma4uhXhxliy5zoh/Cq3WbsKz9FbWxSH1X8rodeu9rqzKuFy7CAycnEmX7HfmwkZCvd5cHUWa3k8Czjiy9JlwRtjUUoqonVcNKJky1+I/v1dqxs2/PPL9VVLQKsmMMqvZTyqSdOPsqggne1vebevB96Sk7J5PKMdoGBsrnM9Y9aHguu5ilAclaRadevzFx5swmlul/Ee/P8jeB/qJXOkF1w0IF0itvF9RazjkUvXe5w0a6ytRTvvtmSGkdx9JlaWG7JoPQqce1vqpkqDWZ3DHvpIO/4hvh5BVvB9Z2BgCtUXjmzhKkewtS3uyuYrdkmMnniQVPMyeKNNXDD2bpJdGGlOutP2MZoVdPyp3OkOHmCLFiPhbv8HBM6Kg== X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(40470700001)(356005)(81166007)(83380400001)(7696005)(7416002)(5660300002)(186003)(508600001)(36756003)(86362001)(8676002)(82310400004)(54906003)(316002)(26005)(2906002)(40460700001)(8936002)(110136005)(426003)(6666004)(2616005)(70206006)(336012)(70586007)(4326008)(107886003)(36860700001)(47076005)(34020700004)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2021 17:31:18.7331 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5bfaff71-5cf1-4660-b29b-08d9c3de8875 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1457 Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Sameer Pujar , linux-kernel@vger.kernel.org, jonathanh@nvidia.com, linux-tegra@vger.kernel.org, digetx@gmail.com, mkumard@nvidia.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Tegra194 does not really have "hda2codec_2x" related reset. Hence drop this entry to reflect actual HW. Fixes: 4878cc0c9fab ("arm64: tegra: Add HDA controller on Tegra194") Signed-off-by: Sameer Pujar --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 8d29b7f..6a1d896 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -976,9 +976,8 @@ <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; clock-names = "hda", "hda2hdmi", "hda2codec_2x"; resets = <&bpmp TEGRA194_RESET_HDA>, - <&bpmp TEGRA194_RESET_HDA2HDMICODEC>, - <&bpmp TEGRA194_RESET_HDA2CODEC_2X>; - reset-names = "hda", "hda2hdmi", "hda2codec_2x"; + <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; + reset-names = "hda", "hda2hdmi"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;