From patchwork Mon May 29 09:15:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 100646 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp246657qge; Mon, 29 May 2017 02:17:24 -0700 (PDT) X-Received: by 10.99.128.72 with SMTP id j69mr17601811pgd.28.1496049444017; Mon, 29 May 2017 02:17:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496049444; cv=none; d=google.com; s=arc-20160816; b=I3HX1U4gZ0A4C+AjyHvN/8z/AxMnSCeWC4CHQY+DVPiWSOuNVJzLGyvCm/0SfriSyN 4De1xh0cHP1WrZeBz7pNoeI4UhP8wfIaXoxc2+rdB5NDTSBRDUAqa/tryOlvl7Rwv2vg H//Wp2/vxOVPnQVOjpyZvrJ6ZN+D0Wr8BEQWAdN5euAPCMManEviiWJRFmVgUiHhggsi 97TZxe8SXia5qQLRExcDaClCLsiL6T4jTkkyPpAzY5TV0fo7mOw4yhpVinYfqFiSsimu yRRlMTQ4tmkSKNhhM4Qq+05/BqASbTjzicLBNXoB34hsHITIQw9967VcejJCJ2i70Wt3 rz3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=v1+czuUTH8gGDOSyzgtY2FUYLXo61LcEjnTyKyMXq38=; b=sJdyGyu4pmqqlb4eLpyCDbURF0YOzAA4ofzRM8glB/e0wHPHM8vVQuLxq7ZDSr3NFN NPcG0kiqaFAcuEY/+/5/TU11TpaKyL+/rgGGGJLDHN3Ag70+VCWrzp/dtUma4KBjepM+ xs2mCAnADKIoOZEVr4nzofHYGgrXhifOsO+NImX/U2AEFaQfjQPDyMyRVK+C/tnxzVLF kqQc1VpV6SeoNlQNxSWG9WFdrLJ1juGHGXggknvF6pcZ8J013b7cZwBBQ7aCsqjALqkM Qw6EoHTvpWtIHr5rKcHlSL4m28wsOyGFXyXN+gg5s02rL640ceEqe0ZRPMEwBj6OxdNR 45ew== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o33si40454254pld.317.2017.05.29.02.17.23; Mon, 29 May 2017 02:17:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751423AbdE2JRJ (ORCPT + 25 others); Mon, 29 May 2017 05:17:09 -0400 Received: from mx.socionext.com ([202.248.49.38]:16071 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751408AbdE2JRG (ORCPT ); Mon, 29 May 2017 05:17:06 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 29 May 2017 18:16:59 +0900 Received: from mail.mfilter.local (unknown [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 2E559180B47; Mon, 29 May 2017 18:16:59 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Mon, 29 May 2017 18:16:59 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 9C1301A0E7B; Mon, 29 May 2017 18:16:58 +0900 (JST) From: Kunihiko Hayashi To: rui.zhang@intel.com, edubezval@gmail.com Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, yamada.masahiro@socionext.com, masami.hiramatsu@linaro.org, jaswinder.singh@linaro.org, Kunihiko Hayashi Subject: [PATCH 1/4] thermal: uniphier: add UniPhier thermal driver Date: Mon, 29 May 2017 18:15:42 +0900 Message-Id: <1496049345-14649-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496049345-14649-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1496049345-14649-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a thermal driver for on-chip PVT (Process, Voltage and Temperature) monitoring unit implemented on UniPhier SoCs. This driver supports temperature monitoring and alert function. Signed-off-by: Kunihiko Hayashi --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/uniphier_thermal.c | 390 +++++++++++++++++++++++++++++++++++++ 3 files changed, 399 insertions(+) create mode 100644 drivers/thermal/uniphier_thermal.c -- 2.7.4 diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 776b343..93ccf25 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -453,4 +453,12 @@ config ZX2967_THERMAL the primitive temperature sensor embedded in zx2967 SoCs. This sensor generates the real time die temperature. +config UNIPHIER_THERMAL + tristate "Socionext UniPhier thermal driver" + depends on ARCH_UNIPHIER || COMPILE_TEST + help + Enable this to support thermal reporting on UniPhier SoC. + This driver supports CPU thermal zone to reports the temperture + and trip points. + endif diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 7adae20..05b6e7c 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -58,3 +58,4 @@ obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o obj-$(CONFIG_ZX2967_THERMAL) += zx2967_thermal.o +obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o diff --git a/drivers/thermal/uniphier_thermal.c b/drivers/thermal/uniphier_thermal.c new file mode 100644 index 0000000..ae7e5ce --- /dev/null +++ b/drivers/thermal/uniphier_thermal.c @@ -0,0 +1,390 @@ +/** + * uniphier_thermal.c - Socionext UniPhier thermal driver + * + * Copyright 2014 Panasonic Corporation + * Copyright 2016 Socionext Inc. + * All rights reserved. + * + * Author: + * Kunihiko Hayashi + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 of + * the License as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "thermal_core.h" + +/* + * block registers + * addresses are the offset from .block_base + */ +#define PVTCTLEN 0x0000 +#define PVTCTLEN_EN BIT(0) + +#define PVTCTLMODE 0x0004 +#define PVTCTLMODE_MASK 0xf +#define PVTCTLMODE_TEMPMON 0x5 + +#define EMONREPEAT 0x0040 +#define EMONREPEAT_ENDLESS BIT(24) +#define EMONREPEAT_PERIOD 0xf +#define EMONREPEAT_PERIOD_1000000 0x9 + +/* + * common registers + * addresses are the offset from .map_base + */ +#define PVTCTLSEL 0x0900 +#define PVTCTLSEL_MASK 0x7 +#define PVTCTLSEL_MONITOR 0 + +#define SETALERT0 0x0910 +#define SETALERT1 0x0914 +#define SETALERT2 0x0918 +#define SETALERT_TEMP_OVF (0xff << 16) +#define SETALERT_TEMP_OVF_VALUE(val) (((val) & 0xff) << 16) +#define SETALERT_EN BIT(0) + +#define PMALERTINTCTL 0x0920 +#define PMALERTINTCTL_CLR(ch) BIT(4 * (ch) + 2) +#define PMALERTINTCTL_SET(ch) BIT(4 * (ch) + 1) +#define PMALERTINTCTL_EN(ch) BIT(4 * (ch) + 0) +#define PMALERTINTCTL_MASK 0x777 + +#define TMOD 0x0928 +#define TMOD_MASK 0x1ff + +#define TMODCOEF 0x0e5c + +#define TMODSETUP0_EN BIT(30) +#define TMODSETUP0_VAL(val) (((val) & 0x3fff) << 16) +#define TMODSETUP1_EN BIT(15) +#define TMODSETUP1_VAL(val) ((val) & 0x7fff) + +/* SoC critical temperature is 95 degrees Celsius */ +#define CRITICAL_TEMP_LIMIT (95 * 1000) + +/* Max # of alert channels */ +#define ALERT_CH_NUM 3 + +/* SoC specific thermal sensor data */ +struct uniphier_tm_soc_data { + u32 map_base; + u32 block_base; + u32 tmod_setup_addr; +}; + +struct uniphier_tm_dev { + struct regmap *regmap; + bool alert_en[ALERT_CH_NUM]; + u32 tmod_calib0; + u32 tmod_calib1; + struct thermal_zone_device *tz_dev; + const struct uniphier_tm_soc_data *data; +}; + +static int uniphier_tm_initialize_sensor(struct uniphier_tm_dev *tdev) +{ + struct regmap *map = tdev->regmap; + u32 val; + int ret; + + /* stop PVT */ + regmap_write_bits(map, + tdev->data->block_base + PVTCTLEN, + PVTCTLEN_EN, 0); + + /* + * set default value if missing calibrated value + * + * Since SoC has a calibrated value that was set in advance, + * TMODCOEF shows non-zero and PVT refers the value internally. + * + * However, there is the case that some SoCs might not have the + * calibrated value. In that case, TMODCOEF shows zero and the driver + * has to set default value manually. + */ + ret = regmap_read(map, tdev->data->map_base + TMODCOEF, &val); + if (ret) + return ret; + if (!val) + regmap_write(map, + tdev->data->tmod_setup_addr, + TMODSETUP0_EN | + TMODSETUP0_VAL(tdev->tmod_calib0) | + TMODSETUP1_EN | + TMODSETUP1_VAL(tdev->tmod_calib1)); + + /* select temperature mode */ + regmap_write_bits(map, + tdev->data->block_base + PVTCTLMODE, + PVTCTLMODE_MASK, + PVTCTLMODE_TEMPMON); + + /* set monitoring period */ + regmap_write_bits(map, + tdev->data->block_base + EMONREPEAT, + EMONREPEAT_ENDLESS | + EMONREPEAT_PERIOD, + EMONREPEAT_ENDLESS | + EMONREPEAT_PERIOD_1000000); + + /* set monitor mode */ + regmap_write_bits(map, + tdev->data->map_base + PVTCTLSEL, + PVTCTLSEL_MASK, PVTCTLSEL_MONITOR); + + return 0; +} + +static void uniphier_tm_set_alert(struct uniphier_tm_dev *tdev, u32 ch, + u32 temp) +{ + struct regmap *map = tdev->regmap; + + /* set alert temperature */ + regmap_write_bits(map, + tdev->data->map_base + SETALERT0 + (ch << 2), + SETALERT_EN | + SETALERT_TEMP_OVF, + SETALERT_EN | + SETALERT_TEMP_OVF_VALUE(temp / 1000)); +} + +static void uniphier_tm_enable_sensor(struct uniphier_tm_dev *tdev) +{ + struct regmap *map = tdev->regmap; + int i; + u32 bits = 0; + + for (i = 0; i < ALERT_CH_NUM; i++) + if (tdev->alert_en[i]) + bits |= PMALERTINTCTL_EN(i); + + /* enable alert interrupt */ + regmap_write_bits(map, + tdev->data->map_base + PMALERTINTCTL, + PMALERTINTCTL_MASK, bits); + + /* start PVT */ + regmap_write_bits(map, + tdev->data->block_base + PVTCTLEN, + PVTCTLEN_EN, PVTCTLEN_EN); +} + +static void uniphier_tm_disable_sensor(struct uniphier_tm_dev *tdev) +{ + struct regmap *map = tdev->regmap; + + /* disable alert interrupt */ + regmap_write_bits(map, + tdev->data->map_base + PMALERTINTCTL, + PMALERTINTCTL_MASK, 0); + + /* stop PVT */ + regmap_write_bits(map, + tdev->data->block_base + PVTCTLEN, + PVTCTLEN_EN, 0); +} + +static int uniphier_tm_get_temp(void *data, int *out_temp) +{ + struct uniphier_tm_dev *tdev = data; + struct regmap *map = tdev->regmap; + int ret; + u32 temp; + + ret = regmap_read(map, tdev->data->map_base + TMOD, &temp); + if (ret) + return ret; + + temp &= TMOD_MASK; + *out_temp = temp * 1000; /* millicelsius */ + + return 0; +} + +static const struct thermal_zone_of_device_ops uniphier_of_thermal_ops = { + .get_temp = uniphier_tm_get_temp, +}; + +static void uniphier_tm_irq_clear(struct uniphier_tm_dev *tdev) +{ + u32 mask = 0, bits = 0; + int i; + + for (i = 0; i < ALERT_CH_NUM; i++) { + mask |= (PMALERTINTCTL_CLR(i) | + PMALERTINTCTL_SET(i)); + bits |= PMALERTINTCTL_CLR(i); + } + + /* clear alert interrupt */ + regmap_write_bits(tdev->regmap, + tdev->data->map_base + PMALERTINTCTL, mask, bits); +} + +static irqreturn_t uniphier_tm_alarm_handler(int irq, void *_tdev) +{ + struct uniphier_tm_dev *tdev = _tdev; + + uniphier_tm_irq_clear(tdev); + thermal_zone_device_update(tdev->tz_dev, THERMAL_EVENT_UNSPECIFIED); + + return IRQ_HANDLED; +} + +static int uniphier_tm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct regmap *regmap; + struct device_node *parent; + struct uniphier_tm_dev *tdev; + const struct thermal_trip *trips; + const u32 *calib; + int i, ret, irq, ntrips, crit_temp = INT_MAX; + + tdev = devm_kzalloc(dev, sizeof(*tdev), GFP_KERNEL); + if (!tdev) + return -ENOMEM; + + tdev->data = of_device_get_match_data(dev); + if (WARN_ON(!tdev->data)) + return -EINVAL; + + /* get irq */ + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + /* get tmod-calibration values */ + calib = of_get_property(dev->of_node, "socionext,tmod-calibration", + NULL); + if (calib) { + tdev->tmod_calib0 = of_read_number(calib, 1); + tdev->tmod_calib1 = of_read_number(calib + 1, 1); + } + + /* get regmap from syscon node */ + parent = of_get_parent(dev->of_node); /* parent should be syscon node */ + regmap = syscon_node_to_regmap(parent); + of_node_put(parent); + if (IS_ERR(regmap)) { + dev_err(dev, "failed to get regmap (error %ld)\n", + PTR_ERR(regmap)); + return PTR_ERR(regmap); + } + tdev->regmap = regmap; + + /* register sensor */ + tdev->tz_dev = devm_thermal_zone_of_sensor_register(dev, 0, tdev, + &uniphier_of_thermal_ops); + if (IS_ERR(tdev->tz_dev)) { + dev_err(dev, "failed to register sensor device\n"); + return PTR_ERR(tdev->tz_dev); + } + + /* get trip points */ + trips = of_thermal_get_trip_points(tdev->tz_dev); + ntrips = of_thermal_get_ntrips(tdev->tz_dev); + if (ntrips > ALERT_CH_NUM) { + dev_err(dev, "thermal zone has too many trips\n"); + return -E2BIG; + } + + /* initialize sensor */ + ret = uniphier_tm_initialize_sensor(tdev); + if (ret) { + dev_err(dev, "failed to initialize sensor\n"); + return ret; + } + for (i = 0; i < ntrips; i++) { + if (trips[i].type == THERMAL_TRIP_CRITICAL && + trips[i].temperature < crit_temp) + crit_temp = trips[i].temperature; + uniphier_tm_set_alert(tdev, i, trips[i].temperature); + tdev->alert_en[i] = true; + } + if (crit_temp > CRITICAL_TEMP_LIMIT) { + dev_err(dev, "critical trip is over limit(>%d), or not set\n", + CRITICAL_TEMP_LIMIT); + return -EINVAL; + } + + ret = devm_request_irq(dev, irq, uniphier_tm_alarm_handler, + 0, "thermal", tdev); + if (ret) + return ret; + + /* enable sensor */ + uniphier_tm_enable_sensor(tdev); + + platform_set_drvdata(pdev, tdev); + + return 0; +} + +static int uniphier_tm_remove(struct platform_device *pdev) +{ + struct uniphier_tm_dev *tdev = platform_get_drvdata(pdev); + + /* disable sensor */ + uniphier_tm_disable_sensor(tdev); + + return 0; +} + +static const struct uniphier_tm_soc_data uniphier_pxs2_tm_data = { + .map_base = 0xe000, + .block_base = 0xe000, + .tmod_setup_addr = 0xe904, +}; + +static const struct uniphier_tm_soc_data uniphier_ld20_tm_data = { + .map_base = 0xe000, + .block_base = 0xe800, + .tmod_setup_addr = 0xe938, +}; + +static const struct of_device_id uniphier_tm_dt_ids[] = { + { + .compatible = "socionext,uniphier-pxs2-thermal", + .data = &uniphier_pxs2_tm_data, + }, + { + .compatible = "socionext,uniphier-ld20-thermal", + .data = &uniphier_ld20_tm_data, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, uniphier_tm_dt_ids); + +static struct platform_driver uniphier_tm_driver = { + .probe = uniphier_tm_probe, + .remove = uniphier_tm_remove, + .driver = { + .name = "uniphier-thermal", + .of_match_table = uniphier_tm_dt_ids, + }, +}; +module_platform_driver(uniphier_tm_driver); + +MODULE_AUTHOR("Kunihiko Hayashi "); +MODULE_DESCRIPTION("UniPhier thermal driver"); +MODULE_LICENSE("GPL v2"); From patchwork Mon May 29 09:15:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 100647 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp246661qge; Mon, 29 May 2017 02:17:24 -0700 (PDT) X-Received: by 10.84.143.36 with SMTP id 33mr73229778ply.45.1496049444489; Mon, 29 May 2017 02:17:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496049444; cv=none; d=google.com; s=arc-20160816; b=hOgC95xCUm/svKCwh5S0K0eiLOc5QEEbxMCGO5jAY4nGl1szs0kEGsEL5hnzU1I+ZW sd+FxtU2/FgxVtgTdu0Pc23Gav6CgJPtf1Td45ngUb0SFdrNIXQkVR/1kyLJdd0dLajs afsyU6nAfoD7us/SOV50I/agD9SLewMtf2oxrWWRwGeeZIOgA579n7EA2w/ptPSJ3WwZ IT4T8iUAbOcSnQMJaFn9xiZKcNjunZXOS2nvwFuRnF8HnMEkkCbXP/IZO0UZg2lw8uGx jiOZ+ih1uG/+6l1K5XS2DUAd2AJWdYh8rm6fPD9fSpUwoDakVSJFVYGu/LQVhGu4KhrK 88aw== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id o33si40454254pld.317.2017.05.29.02.17.24; Mon, 29 May 2017 02:17:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751436AbdE2JRP (ORCPT + 25 others); Mon, 29 May 2017 05:17:15 -0400 Received: from mx.socionext.com ([202.248.49.38]:16071 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750787AbdE2JRN (ORCPT ); Mon, 29 May 2017 05:17:13 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 29 May 2017 18:16:59 +0900 Received: from mail.mfilter.local (unknown [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id C0E6861166; Mon, 29 May 2017 18:16:59 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Mon, 29 May 2017 18:16:59 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id E85501A1208; Mon, 29 May 2017 18:16:58 +0900 (JST) From: Kunihiko Hayashi To: rui.zhang@intel.com, edubezval@gmail.com Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, yamada.masahiro@socionext.com, masami.hiramatsu@linaro.org, jaswinder.singh@linaro.org, Kunihiko Hayashi Subject: [PATCH 2/4] dt-bindings: thermal: add binding documentation for UniPhier thermal monitor Date: Mon, 29 May 2017 18:15:43 +0900 Message-Id: <1496049345-14649-3-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496049345-14649-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1496049345-14649-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add devicetree binding documentation for thermal monitor implemented on Socionext UniPhier SoCs. Signed-off-by: Kunihiko Hayashi --- .../bindings/thermal/uniphier-thermal.txt | 54 ++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/uniphier-thermal.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/thermal/uniphier-thermal.txt b/Documentation/devicetree/bindings/thermal/uniphier-thermal.txt new file mode 100644 index 0000000..72834e1 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/uniphier-thermal.txt @@ -0,0 +1,54 @@ +* UniPhier Thermal bindings + +This describes the devicetree bindings for thermal monitor supported by +PVT(Process, Voltage and Temperature) monitoring unit implemented on Socionext +UniPhier SoCs. + +Required properties: +- compatible : + - "socionext,uniphier-pxs2-thermal" : For UniPhier PXs2 SoC + - "socionext,uniphier-ld20-thermal" : For UniPhier LD20 SoC +- reg : Offset address of the thermal registers from sysctrl +- interrupts : IRQ for the temperature alarm +- #thermal-sensor-cells : Should be 0. See ./thermal.txt for details. + +Optional properties: +- socionext,tmod-calibration: A pair of calibrated values referred from PVT, + in case that the values aren't set on SoC, + like a reference board. + +Example: + + sysctrl@61840000 { + compatible = "socionext,uniphier-ld20-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + ... + pvtctl: pvtctl { + compatible = "socionext,uniphier-ld20-thermal"; + interrupts = <0 3 1>; + #thermal-sensor-cells = <0>; + }; + ... + }; + + thermal-zones { + cpu_thermal { + polling-delay-passive = <250>; /* 250ms */ + polling-delay = <1000>; /* 1000ms */ + thermal-sensors = <&pvtctl>; + + trips { + cpu_crit: cpu_crit { + temperature = <95000>; /* 95C */ + hysteresis = <2000>; + type = "critical"; + }; + cpu_alert: cpu_alert { + temperature = <85000>; /* 85C */ + hysteresis = <2000>; + type = "passive"; + }; + }; + }; + }; From patchwork Mon May 29 09:15:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 100644 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp246650qge; Mon, 29 May 2017 02:17:23 -0700 (PDT) X-Received: by 10.84.231.139 with SMTP id g11mr60659257plk.71.1496049443247; Mon, 29 May 2017 02:17:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496049443; cv=none; d=google.com; s=arc-20160816; b=Oc9H5sn3LZ7dAkrIq0Taq+R/M3CktjCghnlxmTmDxo0p3nUPQN7butRDsHBl1sT8RT dnN/rNC0HMzLcRku/17rZJuJ1M3HCHcVuMZiCFyaNgIX8VVZiFxYM2+80KkAM3RU55Bj PANCPVy1um0nJM7TAVKwbccvDp5U+YhLwAps5DEtcpV7X/Pu3TwqM5cK79ry8/K/JSEe Z1NNLJqJrT6XT2wKSUPa5KrSl5OsSy+A9T1E0q/5GbFerSJ3AB8RamR9SnbdBok2u1LF 4jxF2solL2Jtgu0u+aws8sdmzZ8I/PaCWEBc8pwZ7dZGksiApYnHG+aeD9A228SX2w32 /B0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=fXMAm4YxZqXJcQFLoAvPz1I4A7nN+ftdZfgnbtvU2oo=; b=I7mNAtJIR2WzCPyn1WPC8ePEefP6p+KM0sgsxpcKoymBcZpRVJYbFBXxyvY8hMEkjd mympEHvOhpOKa0cYvkh7KaD6v/G6oYoM3WOkCITZfQM2VTNUdgUg5ch+eeQqhocNi7FL xXqfXtGS6jC1HBMDcBF1lQa4WPhiH4xQQJ2EpB3an06RSA0uAC8OiC/zh5rUI+khhIYz ZLwbjs/4wYOLCVQjVLvsJ3+9cujb8M6ulMewPHZFTs3yFqGAvKCqVNz5qh+t8THMeN+7 6GHKUeucdweQq6619TSmMz+pv5lPcud24akweOMnGaDF+Nmkgt43v4I2rQQxiYc4HTJj djjA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o33si40454254pld.317.2017.05.29.02.17.22; Mon, 29 May 2017 02:17:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751410AbdE2JRF (ORCPT + 25 others); Mon, 29 May 2017 05:17:05 -0400 Received: from mx.socionext.com ([202.248.49.38]:16069 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751237AbdE2JRC (ORCPT ); Mon, 29 May 2017 05:17:02 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 29 May 2017 18:16:59 +0900 Received: from mail.mfilter.local (unknown [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id C2ECD180B47; Mon, 29 May 2017 18:16:59 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Mon, 29 May 2017 18:16:59 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 3F4161A0E7B; Mon, 29 May 2017 18:16:59 +0900 (JST) From: Kunihiko Hayashi To: rui.zhang@intel.com, edubezval@gmail.com Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, yamada.masahiro@socionext.com, masami.hiramatsu@linaro.org, jaswinder.singh@linaro.org, Kunihiko Hayashi Subject: [PATCH 3/4] ARM: dts: uniphier: add nodes of thermal monitor and thermal zone for PXs2 Date: Mon, 29 May 2017 18:15:44 +0900 Message-Id: <1496049345-14649-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496049345-14649-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1496049345-14649-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add nodes of thermal monitor and thermal zone for UniPhier PXs2 SoC. The thermal monitor is included in sysctrl. Signed-off-by: Kunihiko Hayashi --- arch/arm/boot/dts/uniphier-pxs2-gentil.dts | 21 +++++++++++++++++++++ arch/arm/boot/dts/uniphier-pxs2-vodka.dts | 21 +++++++++++++++++++++ arch/arm/boot/dts/uniphier-pxs2.dtsi | 6 ++++++ 3 files changed, 48 insertions(+) -- 2.7.4 diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts index 373818a..89ccb88 100644 --- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts +++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts @@ -70,6 +70,27 @@ i2c5 = &i2c5; i2c6 = &i2c6; }; + + thermal-zones { + cpu_thermal { + polling-delay-passive = <250>; /* 250ms */ + polling-delay = <1000>; /* 1000ms */ + thermal-sensors = <&pvtctl>; + + trips { + cpu_crit: cpu_crit { + temperature = <95000>; /* 95C */ + hysteresis = <2000>; + type = "critical"; + }; + cpu_alert: cpu_alert { + temperature = <85000>; /* 85C */ + hysteresis = <2000>; + type = "passive"; + }; + }; + }; + }; }; &serial2 { diff --git a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts index 51a3eac..0201584 100644 --- a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts +++ b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts @@ -68,6 +68,27 @@ i2c5 = &i2c5; i2c6 = &i2c6; }; + + thermal-zones { + cpu_thermal { + polling-delay-passive = <250>; /* 250ms */ + polling-delay = <1000>; /* 1000ms */ + thermal-sensors = <&pvtctl>; + + trips { + cpu_crit: cpu_crit { + temperature = <95000>; /* 95C */ + hysteresis = <2000>; + type = "critical"; + }; + cpu_alert: cpu_alert { + temperature = <85000>; /* 85C */ + hysteresis = <2000>; + type = "passive"; + }; + }; + }; + }; }; &serial2 { diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index e9e031d..072e3b4 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -387,6 +387,12 @@ compatible = "socionext,uniphier-pxs2-reset"; #reset-cells = <1>; }; + + pvtctl: pvtctl { + compatible = "socionext,uniphier-pxs2-thermal"; + interrupts = <0 3 1>; + #thermal-sensor-cells = <0>; + }; }; }; }; From patchwork Mon May 29 09:15:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 100648 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp246858qge; Mon, 29 May 2017 02:18:04 -0700 (PDT) X-Received: by 10.99.158.17 with SMTP id s17mr18002982pgd.219.1496049484613; Mon, 29 May 2017 02:18:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496049484; cv=none; d=google.com; s=arc-20160816; b=wpX+1U9mxu/cDFjPJBA58oUG79gqlMfQopxyFlrA9zhKAx8fQpQgVT2+fslZ+9+Pmp E3n+ovd2tNRDcyzHN5vjt8OVVrEh4dyjnh5BQG434ept/zfLkDEmZAkxs13BB8nEuTb3 dsRPARxvZfMA1Vmg3tqiblxKcYS7AeLbuePtGv0TdJfPVpxmJzrAb1zZfE+FFvqmifSj UNgWL/u9oNSdFKnGD0l6BA6l1XaG0fnCDN5gJoPgDGHfjIAYCKtrTMjHsAAg8feLvtUP BUV26cFFj9AoFlT8LDWbxl0H9aKhOfHXtjoLXPWOLbxLNEr4CS+mynlfPrsF7/RcG0kG UxUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=fcrw6PhtVGYkZeWfVd+AqcoAUiTGB4uSEJ8U9VTlOyA=; b=DZAN/8to0G1D+nLvDc5cDTwZIrqWnUEnMNXniCr++TMJPA6dZN4TB9gkhthndmmYck 3StEMgnZZMxiupBKPMBfQK7JsDV9wq5/iJMo/bHIqYwZFH78PZXSOzbkrWnyPekrQLLh UtAI1fb+Ekcf4+4Qg7jv9X/8KhZzKsoAISOXVvH3ukw6f7MHU47Iqec0BRBelbMObWbA e2Y5aRk9hQH0gjsSI0eM9ATbLkU6+SHi8bzNPyGEu5dl7z3aTdp6akcAPnPrKHOL1nYO exmsBEDPNQ520w9NtV6fCwujTNiJXdIhPCBhoEZLX8LqHb36/PenOaPaRMrFYjPBrGKs fxOA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o189si9682896pgo.173.2017.05.29.02.18.04; Mon, 29 May 2017 02:18:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751209AbdE2JR7 (ORCPT + 25 others); Mon, 29 May 2017 05:17:59 -0400 Received: from mx.socionext.com ([202.248.49.38]:16085 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751011AbdE2JRN (ORCPT ); Mon, 29 May 2017 05:17:13 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 29 May 2017 18:17:00 +0900 Received: from mail.mfilter.local (unknown [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 396C961166; Mon, 29 May 2017 18:17:00 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Mon, 29 May 2017 18:17:00 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 8BCF21A1208; Mon, 29 May 2017 18:16:59 +0900 (JST) From: Kunihiko Hayashi To: rui.zhang@intel.com, edubezval@gmail.com Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, yamada.masahiro@socionext.com, masami.hiramatsu@linaro.org, jaswinder.singh@linaro.org, Kunihiko Hayashi Subject: [PATCH 4/4] arm64: dts: uniphier: add nodes of thermal monitor and thermal zone for LD20 Date: Mon, 29 May 2017 18:15:45 +0900 Message-Id: <1496049345-14649-5-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496049345-14649-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1496049345-14649-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add nodes of thermal monitor and thermal zone for UniPhier LD20 SoC. The thermal monitor is included in sysctrl. Furthermore, since SoC installed in the reference board doesn't have a calibrated value of thermal monitor, this patch gives the default value for LD20 Reference board via device-tree property. Signed-off-by: Kunihiko Hayashi --- .../arm64/boot/dts/socionext/uniphier-ld20-ref.dts | 25 ++++++++++++++++++++++ arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 6 ++++++ 2 files changed, 31 insertions(+) -- 2.7.4 diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts index 609162a..79e1363 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts @@ -73,6 +73,27 @@ i2c4 = &i2c4; i2c5 = &i2c5; }; + + thermal-zones { + cpu_thermal { + polling-delay-passive = <250>; /* 250ms */ + polling-delay = <1000>; /* 1000ms */ + thermal-sensors = <&pvtctl>; + + trips { + cpu_crit: cpu_crit { + temperature = <95000>; /* 95C */ + hysteresis = <2000>; + type = "critical"; + }; + cpu_alert: cpu_alert { + temperature = <85000>; /* 85C */ + hysteresis = <2000>; + type = "passive"; + }; + }; + }; + }; }; ðsc { @@ -86,3 +107,7 @@ &i2c0 { status = "okay"; }; + +&pvtctl { + socionext,tmod-calibration = <0x0f22 0x68ee>; +}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index a6b3a70..effa2e3 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -417,6 +417,12 @@ compatible = "socionext,uniphier-ld20-reset"; #reset-cells = <1>; }; + + pvtctl: pvtctl { + compatible = "socionext,uniphier-ld20-thermal"; + interrupts = <0 3 1>; + #thermal-sensor-cells = <0>; + }; }; }; };