From patchwork Fri Dec 17 04:19:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 525258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80105C4332F for ; Fri, 17 Dec 2021 04:20:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232704AbhLQEUO (ORCPT ); Thu, 16 Dec 2021 23:20:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232690AbhLQEUM (ORCPT ); Thu, 16 Dec 2021 23:20:12 -0500 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6157C061574; Thu, 16 Dec 2021 20:20:12 -0800 (PST) Received: by mail-pg1-x52d.google.com with SMTP id 133so940527pgc.12; Thu, 16 Dec 2021 20:20:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t6iJOC5DPpuDKIOK7ECu/vvBO8ICNaPQRjhnRSWrI2g=; b=eh/ImVhg76S3I6ACNB7gF6t12Fi2/UhZL9hne6rMpoarNjMkiUj12v+uI0rPqCzyhU +9NvcDbul19TktjGZNW5nz3H3stj9pinILehEDljA9wWXVrOvvzXqlv8+NePLPBRrATQ rXeX74BM5pcmV06Mjr4TtqdGtSY4OFUAOfMcDjwliAtIcgn04XkLiWymlBy4+Pgzvmgp BhpMFjCl/gLqBKCxkKL6D4wJh+oPkdrV2awdV+tlyH9yscaRwkcDRF3UkxnUsuzVnM0W 6W7UeGvNqEbVPuUWmKFKdebdiM7e+XKrzvaK6PANYSQ2oNjfb13PXwHbevs5Q3gSSQK/ 9GDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t6iJOC5DPpuDKIOK7ECu/vvBO8ICNaPQRjhnRSWrI2g=; b=UDneTA5pdRvwMmBoKB65WNUvGMeK239VKKD3su8QQG9VX3sw9QjOZ9c6N3jEPNN1DY tWnrYc7u9+EPLBkTqmuW8urayprvXOcrDvn4PNpnv+LOoNSj9XF6r5Yzpdg+ZR9P+RWL 8Rv0qGKn/uJKKI7QyT1PW31z+UonHFBQsddE8JHonZFjygi+72T2O2nYSASJyJlffhl+ Lv1Gwd0wwTZ7CEgG1wBOw0cUTNcnZKK8kL4SYdY2qsMnl5wbuhfu1tfbH3K7O94wDDRL r2oMN8bBza81QzCYHO5MJgaWUoJKrA0FrunVmFM5nawZsswfLul0zzzKjEwoqsoH6jml 644w== X-Gm-Message-State: AOAM533mJQL+NuX6SDZJxE4sJjKdVK4zksNvD0cc/KwxdHU34grySpfg R1HcLHLk++FocpcRjKAVFdE5JAN9kfE= X-Google-Smtp-Source: ABdhPJw4xYAzWHY8vlcb1RcDXHF6isTLeI+gjmgauvYO12IB4YpHoHrjptTPaxNMSKDmqT1xUIn1vg== X-Received: by 2002:a62:3888:0:b0:4a9:5e0e:8b99 with SMTP id f130-20020a623888000000b004a95e0e8b99mr1248155pfa.30.1639714811708; Thu, 16 Dec 2021 20:20:11 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id mq10sm7553496pjb.3.2021.12.16.20.20.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 20:20:11 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Damien Le Moal , Rob Herring , Thomas Gleixner , Marc Zyngier , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE), Greg Kroah-Hartman , Al Cooper , Ray Jui , Scott Branden , linux-ide@vger.kernel.org (open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers)), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-usb@vger.kernel.org (open list:USB SUBSYSTEM) Subject: [PATCH v4 1/6] dt-bindings: interrupt-controller: Convert BCM7120 L2 to YAML Date: Thu, 16 Dec 2021 20:19:56 -0800 Message-Id: <20211217042001.479577-2-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211217042001.479577-1-f.fainelli@gmail.com> References: <20211217042001.479577-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Broadcom BCM7120 Level 2 interrupt controller Device Tree binding to YAML to help with validation. Signed-off-by: Florian Fainelli --- .../brcm,bcm7120-l2-intc.txt | 88 ------------- .../brcm,bcm7120-l2-intc.yaml | 124 ++++++++++++++++++ 2 files changed, 124 insertions(+), 88 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt deleted file mode 100644 index addd86b6ca2f..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt +++ /dev/null @@ -1,88 +0,0 @@ -Broadcom BCM7120-style Level 2 interrupt controller - -This interrupt controller hardware is a second level interrupt controller that -is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based -platforms. It can be found on BCM7xxx products starting with BCM7120. - -Such an interrupt controller has the following hardware design: - -- outputs multiple interrupts signals towards its interrupt controller parent - -- controls how some of the interrupts will be flowing, whether they will - directly output an interrupt signal towards the interrupt controller parent, - or if they will output an interrupt signal at this 2nd level interrupt - controller, in particular for UARTs - -- has one 32-bit enable word and one 32-bit status word - -- no atomic set/clear operations - -- not all bits within the interrupt controller actually map to an interrupt - -The typical hardware layout for this controller is represented below: - -2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC) - -0 -----[ MUX ] ------------|==========> GIC interrupt 75 - \-----------\ - | -1 -----[ MUX ] --------)---|==========> GIC interrupt 76 - \------------| - | -2 -----[ MUX ] --------)---|==========> GIC interrupt 77 - \------------| - | -3 ---------------------| -4 ---------------------| -5 ---------------------| -7 ---------------------|---|===========> GIC interrupt 66 -9 ---------------------| -10 --------------------| -11 --------------------/ - -6 ------------------------\ - |===========> GIC interrupt 64 -8 ------------------------/ - -12 ........................ X -13 ........................ X (not connected) -.. -31 ........................ X - -Required properties: - -- compatible: should be "brcm,bcm7120-l2-intc" -- reg: specifies the base physical address and size of the registers -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- interrupts: specifies the interrupt line(s) in the interrupt-parent controller - node, valid values depend on the type of parent interrupt controller -- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts - are wired to this 2nd level interrupt controller, and how they match their - respective interrupt parents. Should match exactly the number of interrupts - specified in the 'interrupts' property. - -Optional properties: - -- brcm,irq-can-wake: if present, this means the L2 controller can be used as a - wakeup source for system suspend/resume. - -- brcm,int-fwd-mask: if present, a bit mask to configure the interrupts which - have a mux gate, typically UARTs. Setting these bits will make their - respective interrupt outputs bypass this 2nd level interrupt controller - completely; it is completely transparent for the interrupt controller - parent. This should have one 32-bit word per enable/status pair. - -Example: - -irq0_intc: interrupt-controller@f0406800 { - compatible = "brcm,bcm7120-l2-intc"; - interrupt-parent = <&intc>; - #interrupt-cells = <1>; - reg = <0xf0406800 0x8>; - interrupt-controller; - interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>; - brcm,int-map-mask = <0xeb8>, <0x140>; - brcm,int-fwd-mask = <0x7>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml new file mode 100644 index 000000000000..e10c9879f3f8 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM7120-style Level 2 interrupt controller + +maintainers: + - Florian Fainelli + +description: > + This interrupt controller hardware is a second level interrupt controller that + is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based + platforms. It can be found on BCM7xxx products starting with BCM7120. + + Such an interrupt controller has the following hardware design: + + - outputs multiple interrupts signals towards its interrupt controller parent + + - controls how some of the interrupts will be flowing, whether they will + directly output an interrupt signal towards the interrupt controller parent, + or if they will output an interrupt signal at this 2nd level interrupt + controller, in particular for UARTs + + - has one 32-bit enable word and one 32-bit status word + + - no atomic set/clear operations + + - not all bits within the interrupt controller actually map to an interrupt + + The typical hardware layout for this controller is represented below: + + 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC) + + 0 -----[ MUX ] ------------|==========> GIC interrupt 75 + \-----------\ + | + 1 -----[ MUX ] --------)---|==========> GIC interrupt 76 + \------------| + | + 2 -----[ MUX ] --------)---|==========> GIC interrupt 77 + \------------| + | + 3 ---------------------| + 4 ---------------------| + 5 ---------------------| + 7 ---------------------|---|===========> GIC interrupt 66 + 9 ---------------------| + 10 --------------------| + 11 --------------------/ + + 6 ------------------------\ + |===========> GIC interrupt 64 + 8 ------------------------/ + + 12 ........................ X + 13 ........................ X (not connected) + .. + 31 ........................ X + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + const: brcm,bcm7120-l2-intc + + reg: + maxItems: 1 + description: > + Specifies the base physical address and size of the registers + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + interrupts: true + + brcm,int-map-mask: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: > + 32-bits bit mask describing how many and which interrupts are wired to + this 2nd level interrupt controller, and how they match their respective + interrupt parents. Should match exactly the number of interrupts + specified in the 'interrupts' property. + + brcm,irq-can-wake: + type: boolean + description: > + If present, this means the L2 controller can be used as a wakeup source + for system suspend/resume. + + brcm,int-fwd-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + if present, a bit mask to configure the interrupts which have a mux gate, + typically UARTs. Setting these bits will make their respective interrupt + outputs bypass this 2nd level interrupt controller completely; it is + completely transparent for the interrupt controller parent. This should + have one 32-bit word per enable/status pair. + +additionalProperties: false + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - interrupts + +examples: + - | + irq0_intc: interrupt-controller@f0406800 { + compatible = "brcm,bcm7120-l2-intc"; + interrupt-parent = <&intc>; + #interrupt-cells = <1>; + reg = <0xf0406800 0x8>; + interrupt-controller; + interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>; + brcm,int-map-mask = <0xeb8>, <0x140>; + brcm,int-fwd-mask = <0x7>; + }; From patchwork Fri Dec 17 04:19:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 525257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5428C433F5 for ; Fri, 17 Dec 2021 04:20:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232774AbhLQEUV (ORCPT ); Thu, 16 Dec 2021 23:20:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232728AbhLQEUQ (ORCPT ); Thu, 16 Dec 2021 23:20:16 -0500 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F03CC06173E; Thu, 16 Dec 2021 20:20:16 -0800 (PST) Received: by mail-pg1-x533.google.com with SMTP id 200so972437pgg.3; Thu, 16 Dec 2021 20:20:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hvQSZSJjmQDhoVNAws8o0GpYR+Fym5ONsESevW2QHHo=; b=VCLMgUs3P2HRhSbZzwxM1P5j9NYLF+tWlrBYBKuNZQV0ComR8SANLymGpQtIksO75I p/BNZf/3NNAplUfm34AXrjqvIGkh+pwNeolLwI7hnxom+j8LpEJklqNVAP71AKDW+IQr HvWF+0f1ikF3zI4+puJ9zMcA5ObqPp2Q90a1RcuaL7NEC31UrWEIorFJYyrClhbelmR/ g2/WOES0f/Hz/dA0RFpsePJKwpxOgLGnFRYjDNnGAKSienFFR21Fjx9CSaDFxwtP6khr W7lEmY+t8JqM3aPcvEXk24lpgGeUE+wt6WMmfzwQa2XOtV3r+IxPJUuOcCwJotRaace4 JxKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hvQSZSJjmQDhoVNAws8o0GpYR+Fym5ONsESevW2QHHo=; b=Mxh9bKymEPKIFXvUHBQuVWzH6871giBiDnmYulktvzbGFT5J+RTJ7kZGCka1OWCKP8 HtvYUxAt/6i5kwkefRycn9eQW1Gt3q4BXUCyek3z8EGxqT377y1KR5BCSIlH+M57djBq VU3LSZzJWp2JxRx8HNR58SsjgB6lLYIwtTswfy3M1jBOG7QDQF4qjH0tyFgFhrE5fPZo OaE1JgXAwkEewSGpHiVIjnZiNhqPFBL3v+BDt0Ium7iGEGizg8R6L15OcGgEzamCoedw HJcPfHFxsRywWng/+KdRgyYhTo2OzfnXZ/Qa7Ey3kWrbYSjJd0E88XmpbVBmwVidyjTx WjlA== X-Gm-Message-State: AOAM532dhklfIQ5+Xml9c5Qiw1PwcwT6xBLE9cC/7Wx3hWQrg/H/CoyN oIB6Jox15drI4ObQCczaEh3S2YaxaF8= X-Google-Smtp-Source: ABdhPJwkisUtzEda3tzD4bYdOMoMHn17gkOvTZhkm5bs9qxmGRaGjO45sdXG/2Elh4jamoSMvLNGcA== X-Received: by 2002:a63:8bc4:: with SMTP id j187mr1281031pge.189.1639714815537; Thu, 16 Dec 2021 20:20:15 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id mq10sm7553496pjb.3.2021.12.16.20.20.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 20:20:15 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Damien Le Moal , Rob Herring , Thomas Gleixner , Marc Zyngier , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE), Greg Kroah-Hartman , Al Cooper , Ray Jui , Scott Branden , linux-ide@vger.kernel.org (open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers)), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-usb@vger.kernel.org (open list:USB SUBSYSTEM) Subject: [PATCH v4 3/6] ARM: dts: NSP: Rename SATA unit name Date: Thu, 16 Dec 2021 20:19:58 -0800 Message-Id: <20211217042001.479577-4-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211217042001.479577-1-f.fainelli@gmail.com> References: <20211217042001.479577-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rename the SATA controller unit name from ahci to sata in preparation for adding the Broadcom SATA3 controller YAML binding which will bring validation. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 1c08daa18858..ded5a59e0679 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -534,7 +534,7 @@ sata_phy1: sata-phy@1 { }; }; - sata: ahci@41000 { + sata: sata@41000 { compatible = "brcm,bcm-nsp-ahci"; reg-names = "ahci", "top-ctrl"; reg = <0x41000 0x1000>, <0x40020 0x1c>; From patchwork Fri Dec 17 04:20:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 525256 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5AFD2C433EF for ; Fri, 17 Dec 2021 04:20:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232803AbhLQEUZ (ORCPT ); Thu, 16 Dec 2021 23:20:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232756AbhLQEUV (ORCPT ); Thu, 16 Dec 2021 23:20:21 -0500 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C774C06175B; Thu, 16 Dec 2021 20:20:20 -0800 (PST) Received: by mail-pg1-x52a.google.com with SMTP id j11so978223pgs.2; Thu, 16 Dec 2021 20:20:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iENCssM+7j9yuFOoYg1txSwEuQxBBByhieQXs6KDMvI=; b=Gd8x4qElW2XQnr3xHo3QEW8JU5/nb2Js11/VU/maEtCky+BWKcDpPdvBSRVijNuegs sILsHxgpnOKpM8IdhZci4Vk76CXQ/jMwAIQ8i9cXPHUxfGnt8M+XsxisAtH7gUBxmuu7 nPt1jQF0l6H2XBNA4g5hZYAbQhlKtgrok7Yni5iCPMuTUKlOp7VPYUTTi/ZFv9zfoGAz iFPxW+3F33VhfudaiEBVIBhfwq8JA2T3Q6sHMt3dDv1XoPlGLmSrrfU8DHFDYw1JLThg Vb8ZmsO/cVcWK1EwhfsCLqd7EVGCb2z85YTBV9/SAd05KmYbZEW90tZUvJCqWPOHdYIc Y6uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iENCssM+7j9yuFOoYg1txSwEuQxBBByhieQXs6KDMvI=; b=d512kZAAOc2FwcuUlq871zgYNpraagadWnUTFrXcYpeXOaGmnenFSDZVR+HHC4wSqX Rg0ei3HQsxbzVE0ik6+LOyzSffj4+UTWZsPPlviox+xQOxx6xC3KgqvsOB2Jd1EJYRGi DGmfN6wnjUoBpzDL4PBGztBHkSXbHUXTWKTRr52yha+fari3Lfn/LftYwijg+4AoxL+s 1xUIaYBnT7QOAWoiEe8A3VLEgraQOBmFrg9bByLzj5Rn6WQq+CINwqZQh6IWUry0SJOe ssPh0wApGr+BV05ru1QBXNhsuRK+cRUOZmm1wEILwRQfjMUYwHYMFh5A7GL3eYQ8fGsZ u2qA== X-Gm-Message-State: AOAM532BsaSM+DMFPsZ/gPhk4BZ/j17+aXmXjnuEkq/xH4rnsPPB2OTX qK/FLAfdoQjsBkc9VD4tF/G3vjFjWUA= X-Google-Smtp-Source: ABdhPJwTX2oCmkdBhcbswY9jbqXaWWpE2Z/DsL+tv39GBks/dedys7lG1EmcCubEdTamu2xcgx9vSQ== X-Received: by 2002:a63:1d15:: with SMTP id d21mr1265162pgd.541.1639714819230; Thu, 16 Dec 2021 20:20:19 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id mq10sm7553496pjb.3.2021.12.16.20.20.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 20:20:18 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Damien Le Moal , Rob Herring , Thomas Gleixner , Marc Zyngier , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE), Greg Kroah-Hartman , Al Cooper , Ray Jui , Scott Branden , linux-ide@vger.kernel.org (open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers)), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-usb@vger.kernel.org (open list:USB SUBSYSTEM) Subject: [PATCH v4 5/6] dt-bindings: bus: Convert GISB arbiter to YAML Date: Thu, 16 Dec 2021 20:20:00 -0800 Message-Id: <20211217042001.479577-6-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211217042001.479577-1-f.fainelli@gmail.com> References: <20211217042001.479577-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Broadcom STB GISB bus arbiter to YAML to help with validation. Signed-off-by: Florian Fainelli --- .../devicetree/bindings/bus/brcm,gisb-arb.txt | 34 ---------- .../bindings/bus/brcm,gisb-arb.yaml | 66 +++++++++++++++++++ 2 files changed, 66 insertions(+), 34 deletions(-) delete mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt create mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt deleted file mode 100644 index 10f6d0a8159d..000000000000 --- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt +++ /dev/null @@ -1,34 +0,0 @@ -Broadcom GISB bus Arbiter controller - -Required properties: - -- compatible: - "brcm,bcm7278-gisb-arb" for V7 28nm chips - "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips - "brcm,bcm7435-gisb-arb" for newer 40nm chips - "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips - "brcm,bcm7038-gisb-arb" for 130nm chips -- reg: specifies the base physical address and size of the registers -- interrupts: specifies the two interrupts (timeout and TEA) to be used from - the parent interrupt controller. A third optional interrupt may be specified - for breakpoints. - -Optional properties: - -- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB - masters are valid at the system level -- brcm,gisb-arb-master-names: string list of the litteral name of the GISB - masters. Should match the number of bits set in brcm,gisb-master-mask and - the order in which they appear - -Example: - -gisb-arb@f0400000 { - compatible = "brcm,gisb-arb"; - reg = <0xf0400000 0x800>; - interrupts = <0>, <2>; - interrupt-parent = <&sun_l2_intc>; - - brcm,gisb-arb-master-mask = <0x7>; - brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; -}; diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml new file mode 100644 index 000000000000..b23c3001991e --- /dev/null +++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/brcm,gisb-arb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom GISB bus Arbiter controller + +maintainers: + - Florian Fainelli + +properties: + compatible: + oneOf: + - items: + - enum: + - brcm,bcm7445-gisb-arb # for other 28nm chips + - const: brcm,gisb-arb + - items: + - enum: + - brcm,bcm7278-gisb-arb # for V7 28nm chips + - brcm,bcm7435-gisb-arb # for newer 40nm chips + - brcm,bcm7400-gisb-arb # for older 40nm chips and all 65nm chips + - brcm,bcm7038-gisb-arb # for 130nm chips + - brcm,gisb-arb # fallback compatible + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + items: + - description: timeout interrupt line + - description: target abort interrupt line + - description: breakpoint interrupt line + + brcm,gisb-arb-master-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + 32-bits wide bitmask used to specify which GISB masters are valid at the + system level + + brcm,gisb-arb-master-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: > + String list of the litteral name of the GISB masters. Should match the + number of bits set in brcm,gisb-master-mask and the order in which they + appear from MSB to LSB. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + gisb-arb@f0400000 { + compatible = "brcm,gisb-arb"; + reg = <0xf0400000 0x800>; + interrupts = <0>, <2>; + interrupt-parent = <&sun_l2_intc>; + brcm,gisb-arb-master-mask = <0x7>; + brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; + };