From patchwork Fri Dec 17 09:33:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 525250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A848BC4332F for ; Fri, 17 Dec 2021 09:32:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232753AbhLQJcF (ORCPT ); Fri, 17 Dec 2021 04:32:05 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:9358 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232743AbhLQJcF (ORCPT ); Fri, 17 Dec 2021 04:32:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1639733525; x=1671269525; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=16jgpAx4F4blz9pktkPhV+VzkFMZmKHu4glaJ+JJ1JU=; b=DH8XIJI9t3mywIn5Zpunqg2+xpp6GLot2tATAtaYI48gHQOpdcoDx8LR puzWlboex+3Ipa59HsRYPRWNxegdBk+T6ytzqmJJ7ssls1RcLg+2uk+LK VvKc+xZrWgMfcL57JHPrsFRL6fzI/lg3i5Ja4nm90bxN2usXu14OtqZT8 SNl72BDal3vJY95k/mL7D4JaDec2B/hgpoZDLhKQPHG20gRAuuZbvdNCK apEnKC//eB03sGRDQ+ldJT3P5mdXWY0+iUZ1NH3e3EcUA+XZ1kdN/wDM1 zOE5CHf9wTQqxX5qewHKFZ8Dgrmnqoa6x3SS4rsu9nr/onAv2BKG1s9JB Q==; IronPort-SDR: y7Pj9EsqDH1vKmXDTh1Ap4fPnhWsI7lzCjMYFRMIEHwMa2AeCYLhVzzGngzc86Suat2YLYWdrq Ox4EHt8IHkjHMwYqFowANjywCJ+UrXIIWnCb0yIJ+GkI9sUrFbUKBRcYqVMJ+88DJgWNrKuF1z f439KV8hJsf/yYe/Kq/WDJCb71vDNiapCOEEuOo4Qt2Y2f/BJDZDehI4dBlTZjGguvqxTjvMpr 9DL3N+DcdHXfhpfoCX5aV763w99Goi0OzjemaIfe8ZnnpjGQLhV+LP1sai7LvYPBKNEbm4Zye0 TfhAPsRqH7YHunD/+lUuT7WE X-IronPort-AV: E=Sophos;i="5.88,213,1635231600"; d="scan'208";a="142745546" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Dec 2021 02:32:03 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 17 Dec 2021 02:32:02 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 17 Dec 2021 02:31:57 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v2 02/17] dt-bindings: soc/microchip: update syscontroller compatibles Date: Fri, 17 Dec 2021 09:33:10 +0000 Message-ID: <20211217093325.30612-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211217093325.30612-1-conor.dooley@microchip.com> References: <20211217093325.30612-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley The Polarfire SoC is currently using two different compatible string prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in its system controller in order to match the compatible string used in the soc binding and device tree. Signed-off-by: Conor Dooley --- ...larfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +++--- ...s-controller.yaml => microchip,mpfs-sys-controller.yaml} | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%) rename Documentation/devicetree/bindings/soc/microchip/{microchip,polarfire-soc-sys-controller.yaml => microchip,mpfs-sys-controller.yaml} (75%) diff --git a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml similarity index 82% rename from Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml rename to Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml index bbb173ea483c..9251c2218c68 100644 --- a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/mailbox/microchip,polarfire-soc-mailbox.yaml#" +$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller @@ -11,7 +11,7 @@ maintainers: properties: compatible: - const: microchip,polarfire-soc-mailbox + const: microchip,mpfs-mailbox reg: items: @@ -38,7 +38,7 @@ examples: #address-cells = <2>; #size-cells = <2>; mbox: mailbox@37020000 { - compatible = "microchip,polarfire-soc-mailbox"; + compatible = "mpfs-mailbox"; reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>; interrupt-parent = <&L1>; interrupts = <96>; diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml similarity index 75% rename from Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml rename to Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml index 2cd3bc6bd8d6..f699772fedf3 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/soc/microchip/microchip,polarfire-soc-sys-controller.yaml#" +$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller @@ -19,7 +19,7 @@ properties: maxItems: 1 compatible: - const: microchip,polarfire-soc-sys-controller + const: microchip,mpfs-sys-controller required: - compatible @@ -30,6 +30,6 @@ additionalProperties: false examples: - | syscontroller: syscontroller { - compatible = "microchip,polarfire-soc-sys-controller"; + compatible = "microchip,mpfs-sys-controller"; mboxes = <&mbox 0>; }; From patchwork Fri Dec 17 09:33:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 525249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 673B7C433FE for ; Fri, 17 Dec 2021 09:32:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231811AbhLQJc2 (ORCPT ); Fri, 17 Dec 2021 04:32:28 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:9407 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231913AbhLQJc1 (ORCPT ); Fri, 17 Dec 2021 04:32:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1639733547; 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17 Dec 2021 02:32:25 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 17 Dec 2021 02:32:25 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 17 Dec 2021 02:32:19 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v2 04/17] mailbox: change mailbox-mpfs compatible string Date: Fri, 17 Dec 2021 09:33:12 +0000 Message-ID: <20211217093325.30612-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211217093325.30612-1-conor.dooley@microchip.com> References: <20211217093325.30612-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley The Polarfire SoC is currently using two different compatible string prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in its system controller in order to match the compatible string used in the soc binding and device tree. Signed-off-by: Conor Dooley --- drivers/mailbox/mailbox-mpfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c index 0d6e2231a2c7..4e34854d1238 100644 --- a/drivers/mailbox/mailbox-mpfs.c +++ b/drivers/mailbox/mailbox-mpfs.c @@ -232,7 +232,7 @@ static int mpfs_mbox_probe(struct platform_device *pdev) } static const struct of_device_id mpfs_mbox_of_match[] = { - {.compatible = "microchip,polarfire-soc-mailbox", }, + {.compatible = "microchip,mpfs-mailbox", }, {}, }; MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match); From patchwork Fri Dec 17 09:33:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 525248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0F5FC433FE for ; Fri, 17 Dec 2021 09:32:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232736AbhLQJcu (ORCPT ); Fri, 17 Dec 2021 04:32:50 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:16916 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232790AbhLQJct (ORCPT ); Fri, 17 Dec 2021 04:32:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1639733568; x=1671269568; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fRK83uB7UBmgy7OppXNXdK4ZxB+gBwJv/ZT1t+O9sS0=; b=F10+gqB5y2cCuZX0ukj/BHMGxzvpO2dcBz45DpmrwAC1WCBVVOWE5ojr 1apoIAgVSajvXV5jshL8PE4yNHgHuNWgmZ+f08SFfAL88n/EBmPfdrwcr JjC4T/kETrSUIKEaggV2GwjXnML2v+bozhs64Y7+57twZN8uyCaTLIvuU /vad6ix4VKUEP2pJkO5sv8wOSo/YodtaZCsjjxyqdGc6gWCfW1W0hLYAO EoMcDnnCP/Lgy+JcTqPenuDuEQtBHh4xd640RbggAAYSTFu9z2kJfPuev gEIQkRHwe+/9ah0XQDIwJ8dGX2gLLJu1sLvD1f+aC0a1PGXX28pz/uJUl Q==; IronPort-SDR: CrKd4tOB+b68mUuQA2Zc6ZHToi/KHgvehYmiy4PX3pIT90VbOVR9DHCKvNXqJwwTSbeeBF8d9b qT/hxcMZ8ru69NqKG4oYHAcbnxezkEusLPGkbJjzooonvMjQXrGRX3OBaACKbERSZt6tjFmqGT CjVEPj/2sqNN0oQfkZ5tc21Z5cP8bBfVUA6+2AU70yfSMx1cbniCpQJVdr7lUxUOYa3W7OWSJU ms4r0BOxTvuXf6ZAkbpL9sjKttMVqmBmBPnbJYKHwM8Hvi6WDoDyiIobtpHrLDYAvxPKHrvcbe LM0m7AafWCeLwB16ghkWz/qX X-IronPort-AV: E=Sophos;i="5.88,213,1635231600"; d="scan'208";a="140110734" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Dec 2021 02:32:46 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 17 Dec 2021 02:32:47 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 17 Dec 2021 02:32:41 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v2 06/17] dt-bindings: rng: add bindings for microchip mpfs rng Date: Fri, 17 Dec 2021 09:33:14 +0000 Message-ID: <20211217093325.30612-7-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211217093325.30612-1-conor.dooley@microchip.com> References: <20211217093325.30612-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add device tree bindings for the hardware rng device accessed via the system services on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- .../bindings/rng/microchip,mpfs-rng.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml new file mode 100644 index 000000000000..32cbc37c9292 --- /dev/null +++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip MPFS random number generator + +maintainers: + - Conor Dooley + +description: | + The hardware random number generator on the Polarfire SoC is + accessed via the mailbox interface provided by the system controller + +properties: + compatible: + const: microchip,mpfs-rng + +required: + - compatible + +additionalProperties: false + +examples: + - | + hwrandom: hwrandom { + compatible = "microchip,mpfs-rng"; + }; From patchwork Fri Dec 17 09:33:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 525247 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B24AC433F5 for ; Fri, 17 Dec 2021 09:33:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234223AbhLQJdI (ORCPT ); Fri, 17 Dec 2021 04:33:08 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:9472 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232819AbhLQJdF (ORCPT ); Fri, 17 Dec 2021 04:33:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1639733585; x=1671269585; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gS2HEVkFP5ZT4c04g14Ry523BXpa4eJOH4ez0d0CMYg=; b=sMANZTmBy9d42cLfdWeS6CQAb6zG6I6s+vMLxBxdz2lav3aWnZFcLlD9 WDDlRpsYkHj4+ddsWTO6ckPARX1YHo9g4FwyWNUy0vTGSp8btYpFzmqAn e3gZ/vTqHGEgDrtEryviCZ2ZuFzn2CfS7yl+M0VYKNo30L/d+puX+eUhY VO0t4YpqpePgherJrLiXjEsf+BwHFGINXheviwiX9dhvEKrp0iSl1jfkz ROCZyYMX6+SMoBQDHitXXrXQy2yiqUSTc+1tNPfTisEgRMNftCn+x4RiH QMxU6ACDrbSvZRev2QeJKBGVweMxOalyq0HeHQQabKRXnXXPUKMHzi6ds g==; IronPort-SDR: RpqDwPDYdO0XhcVYtN2cMX5kcR6mmBvXnuh+MkWOJ7snVHp8GWWgynwZ2ASVR4aMpPXVT6v6GN myhE6XlJRvSLmmTOpeKIqWHfdUzQ2RWKvgn7ahkXd8Rn0sEfPeg4lCV9/BH3tWmZlYhsclXEQU dp5EZecfYu8MOz/qF1oN7o46DtxhViDCGFZawUJJHMDMqzXRmYWaIg1fHh9TJCauoxNJQfM/34 zzIXwwvfRPqULw0uMNSVYomrNLZIsi0jJsywpJMrQFCAD7zfpD4BIgssxMmdlInzmQDNmCUSX7 KHq+Do9zN9H35WLG/ZqGA9YT X-IronPort-AV: E=Sophos;i="5.88,213,1635231600"; d="scan'208";a="142745628" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Dec 2021 02:33:03 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 17 Dec 2021 02:32:53 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 17 Dec 2021 02:32:48 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v2 07/17] dt-bindings: rtc: add bindings for microchip mpfs rtc Date: Fri, 17 Dec 2021 09:33:15 +0000 Message-ID: <20211217093325.30612-8-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211217093325.30612-1-conor.dooley@microchip.com> References: <20211217093325.30612-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add device tree bindings for the real time clock on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley Signed-off-by: Daire McNamara --- .../bindings/rtc/microchip,mfps-rtc.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml new file mode 100644 index 000000000000..d57460cbe5e3 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml# + +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings + +allOf: + - $ref: rtc.yaml# + +maintainers: + - Daire McNamara + - Lewis Hanly + +properties: + compatible: + enum: + - microchip,mpfs-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 2 + + microchip,prescaler: + description: | + The prescaler divides the input frequency to create a time-based strobe (typically 1 Hz) for + the calendar counter. The Alarm and Compare Registers, in conjunction with the calendar + counter, facilitate time-matched events. To properly operate in Calendar or Binary mode, + the 26-bit prescaler must be programmed to generate a strobe to the RTC. + maxItems: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: rtc + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + rtc@20124000 { + compatible = "microchip,mpfs-rtc"; + reg = <0x20124000 0x1000>; + clocks = <&clkcfg CLK_RTC>; + clock-names = "rtc"; + interrupts = <80>, <81>; + }; +... From patchwork Fri Dec 17 09:33:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 525246 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 684EAC433EF for ; Fri, 17 Dec 2021 09:33:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234271AbhLQJdP (ORCPT ); Fri, 17 Dec 2021 04:33:15 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:26521 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232786AbhLQJdO (ORCPT ); Fri, 17 Dec 2021 04:33:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1639733594; x=1671269594; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AZ9n/RyDSa/dhqvl7nTlTNh+a3wwb7PMc//RGFolf8w=; b=mM0x/glgcq7Do/QyCRX16aw/R+HMD1JIQmzQ+4hMKS0XpTRUCQ4SnjkW AxMgdx6hdz3hza84w9CizGKVkHDjB/eyAC/pafzT7SuKCjSRgnCg+/ELp ezvRFpotVDvbuuWxVrDtTWzUhI5WUSilmQ2fHmVHSjQvowodj+KnUB+T+ QmOIXqB8qg050SgwAcHcMJRfkEWieq8dPPTW+WU5VkHaNFB0hZ7ppHwQ+ i3TITGVcOgqkRYd/rM6/w4dXv6sISd+ZwTuuLx8Hj/arHnurOBqr2rqHf cXg+SLfV2iUpqTDNCwxYRdy8EzhrHC+wzuueJqmzDHXdtgPzBkr670Z1w g==; IronPort-SDR: URrvqfHRIKuhsX04dHO5TwmpgWvtDIMhF78YdofCTrkXAmRTVPOmQ1RmHEd5wpIimtFRad8/Me uQoAlyKxdynFMA47OHC1uo3LoJpFqPy2tcj0+afKERlsVjGnbMgXYGCexsdH3BtFKvx/DzXegY VFOuScWBc3AeJXLHNVNjmtbHfWCK0cvx/QO0twyAVRXyzGBk/datukPaSSkACKcoZNRiumuQcB /1MbgOBrWhC+NAZxuRcCP65M9mpYxhCEn3iZBI1dPSPaJyGJ5ZVOmh4wr+cb3WTa/yaxkQQQ29 58jmm0K0BLbxX/ZWbgCgcIPe X-IronPort-AV: E=Sophos;i="5.88,213,1635231600"; d="scan'208";a="147571047" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Dec 2021 02:33:09 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 17 Dec 2021 02:33:01 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 17 Dec 2021 02:32:55 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v2 08/17] dt-bindings: soc/microchip: add bindings for mpfs system services Date: Fri, 17 Dec 2021 09:33:16 +0000 Message-ID: <20211217093325.30612-9-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211217093325.30612-1-conor.dooley@microchip.com> References: <20211217093325.30612-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add device tree bindings for the services provided by the system controller directly on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- .../microchip,mpfs-generic-service.yaml | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml new file mode 100644 index 000000000000..d044525b3487 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs-generic-service.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip MPFS system services + +maintainers: + - Conor Dooley + +description: | + The PolarFire SoC system controller is communicated with via a mailbox. + This binding represents several of the functions provided by the system + controller which do not belong in a specific subsystem, such as reading + the fpga device certificate, all of which follow the same format: + - a command + optional payload sent to the sys controller + - a status + a payload returned to Linux. + +properties: + compatible: + const: microchip,mpfs-generic-service + +required: + - compatible + +additionalProperties: false + +examples: + - | + sysserv: sysserv { + compatible = "microchip,mpfs-generic-service"; + }; From patchwork Fri Dec 17 09:33:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 525245 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABB02C433FE for ; Fri, 17 Dec 2021 09:33:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234345AbhLQJdd (ORCPT ); Fri, 17 Dec 2021 04:33:33 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:26574 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234336AbhLQJda (ORCPT ); Fri, 17 Dec 2021 04:33:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1639733609; x=1671269609; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YRf+J/CveN9v/mBBSULutpk2yICowM0+G8+Um5XzvjY=; b=lqdzW8wSyLhgX0wTgZSQdqq9lsb31QjH4VYdFhm7rYa/RuAbnObuwk4F dMsdaPUSyvoYI6+IpY4RR7FmpqDh/bRefPpsdnfatv6ikS0Nu8G9tH8KR /q8Sbyya3VqjPFukxZWzskDPO6UkO+NW+6dsMnLt3BVmP4Vo/mLiNMGrp sO+HibFygu37Jtm78aohWXGs8+X9kr18CmnAv3+hW+sPDiVgt9AH6Xkde C+6FsoHHAwzOfSgwqmBcVx+mtvrETyzOUeNnmOd4XwvFKwZmM/Rsaf257 +Nst2olo+ytwF59BEu24UdBUOCsQ3z3bl1AvKCbmWPeSP3I4NNtomymFa Q==; IronPort-SDR: 5kU8ugyR6rFeYPzzwUrOvEcmXLHtPPnE5vScHarLL9KZrqGgCDT9/heNLX87vVeTWwjG371zcS vOSSzHbuR/4/dQ/tktwTyH7jtnCqoRkniyVnm1coEwHESSlFti67Qz7O+gQMQ6OHyg2yU5Xuyy MUuVLwqM3PAAQJGhViph+1IOuzChZoym27O9pJRmbr96EbBGVIOxKb9pJSLNqlye+qPBv2vrKK 2zD6YVS3VJzQZSDmKfUf+JhsvEH9aNbYXXIZ3QqQN5OJb6phHTMc1BsO1x3IB9CBDtrxkXgBQ0 yn2XTxGFFYooSAIp1RZOZRJ8 X-IronPort-AV: E=Sophos;i="5.88,213,1635231600"; d="scan'208";a="147571120" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Dec 2021 02:33:28 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 17 Dec 2021 02:33:20 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 17 Dec 2021 02:33:15 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v2 11/17] dt-bindings: usb: add bindings for microchip mpfs musb Date: Fri, 17 Dec 2021 09:33:19 +0000 Message-ID: <20211217093325.30612-12-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211217093325.30612-1-conor.dooley@microchip.com> References: <20211217093325.30612-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add device tree bindings for the usb controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- .../bindings/usb/microchip,mpfs-musb.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml diff --git a/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml b/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml new file mode 100644 index 000000000000..eec918046c73 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/microchip,mpfs-musb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MPFS USB Controller Device Tree Bindings + +maintainers: + - Conor Dooley + +properties: + compatible: + enum: + - microchip,mpfs-musb + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + maxItems: 2 + + interrupt-names: + items: + - const: dma + - const: mc + + clocks: + maxItems: 1 + + dr_mode: + enum: + - host + - otg + - peripheral + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - dr_mode + +additionalProperties: false + +examples: + - | + #include "dt-bindings/clock/microchip,mpfs-clock.h" + usb: usb@20201000 { + compatible = "microchip,mpfs-musb"; + reg = <0x20201000 0x1000>; + clocks = <&clkcfg CLK_USB>; + interrupt-parent = <&plic>; + interrupts = <86>, <87>; + interrupt-names = "dma","mc"; + dr_mode = "host"; + }; + +... From patchwork Fri Dec 17 09:33:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 525244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7FBDC433FE for ; Fri, 17 Dec 2021 09:33:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234325AbhLQJdq (ORCPT ); Fri, 17 Dec 2021 04:33:46 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:56724 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229602AbhLQJdl (ORCPT ); Fri, 17 Dec 2021 04:33:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1639733622; x=1671269622; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1Syay7nVJzS7YFXqFo8/vNemWnrn/aoxo86Y2hb6xIE=; b=ouuyqw3u1uaeCFwB22kU68GjAUaP8LDnwJ4aXI1+ZINQoRc4SImXwnA3 +TdhoTlB40gEChUoocYTqNdbCZ66ezpiNJvFMmZNRF+rKD9OatCLg5+NI m2V8xESXCnzwqOxd3EgU5xDTSyky8iQQKGw9AK67I0/0g4D4P0ENIN4r1 xcsSYSRtfvSXvjixkY/IP0mjQxZlpEKh42UgdQfNmEJLog/d4OBJT+ZX5 Yma3h4q37ULqLfFJXFm5x6mFW7YlG7Ee0qMPuY8f5MdP55CrSsuQZiA9D olPDCpkeSdcEuLf9fD+VoYd3ol1xWedahDId7tdVEQ5fsOPoe8uKi0Uuw Q==; IronPort-SDR: qdJM7Qohp+HYWRLBXNZ14SZdj52Q//VI6ThUpsgbYflggAcOfGY++z55HOmd8FK1cdFmH6UF0d xo2urusGP8pnMJChMX3eawG2pdPqD31QehCoPYkm60DQJdXgsigebP02J+4KBbXKoZ3UYYGzoW OjxFA9Mhld8YK7dfnIfMON1XogtFKC8hrylT1LKU7ZGFvfX+pUNsNZiVqLUcJtTNtmcWbh1iqc 4m0UC8iQK7YxSsY15m8/RyfTJrGhpNozD+MAqXnxZ36aVZcgjBmNBO/vJNqYQ5tGE0JnOH/Fyj wcSAI51WRb+5d9wDSWBq8USA X-IronPort-AV: E=Sophos;i="5.88,213,1635231600"; d="scan'208";a="147002753" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Dec 2021 02:33:41 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 17 Dec 2021 02:33:34 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 17 Dec 2021 02:33:28 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v2 13/17] riscv: dts: microchip: use hart and clk defines for icicle kit Date: Fri, 17 Dec 2021 09:33:21 +0000 Message-ID: <20211217093325.30612-14-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211217093325.30612-1-conor.dooley@microchip.com> References: <20211217093325.30612-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Update the Microchip Icicle kit device tree by replacing interrupt and clock related magic numbers with their defined counterparts. Signed-off-by: Conor Dooley --- .../microchip/microchip-mpfs-icicle-kit.dts | 2 +- .../boot/dts/microchip/microchip-mpfs.dtsi | 55 +++++++++++-------- 2 files changed, 34 insertions(+), 23 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index 0c748ae1b006..6d19ba196f12 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -31,7 +31,7 @@ cpus { memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; - clocks = <&clkcfg 26>; + clocks = <&clkcfg CLK_DDRC>; }; }; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index 869aaf0d5c06..ce9151edd1b6 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -2,6 +2,8 @@ /* Copyright (c) 2020 Microchip Technology Inc */ /dts-v1/; +#include "dt-bindings/clock/microchip,mpfs-clock.h" +#include "dt-bindings/interrupt-controller/riscv-hart.h" / { #address-cells = <2>; @@ -14,7 +16,6 @@ cpus { #size-cells = <0>; cpu@0 { - clock-frequency = <0>; compatible = "sifive,e51", "sifive,rocket0", "riscv"; device_type = "cpu"; i-cache-block-size = <64>; @@ -22,6 +23,7 @@ cpu@0 { i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; + clocks = <&clkcfg CLK_CPU>; status = "disabled"; cpu0_intc: interrupt-controller { @@ -32,7 +34,6 @@ cpu0_intc: interrupt-controller { }; cpu@1 { - clock-frequency = <0>; compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -48,6 +49,7 @@ cpu@1 { mmu-type = "riscv,sv39"; reg = <1>; riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; tlb-split; status = "okay"; @@ -59,7 +61,6 @@ cpu1_intc: interrupt-controller { }; cpu@2 { - clock-frequency = <0>; compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -75,6 +76,7 @@ cpu@2 { mmu-type = "riscv,sv39"; reg = <2>; riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; tlb-split; status = "okay"; @@ -86,7 +88,6 @@ cpu2_intc: interrupt-controller { }; cpu@3 { - clock-frequency = <0>; compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -102,6 +103,7 @@ cpu@3 { mmu-type = "riscv,sv39"; reg = <3>; riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; tlb-split; status = "okay"; @@ -113,7 +115,6 @@ cpu3_intc: interrupt-controller { }; cpu@4 { - clock-frequency = <0>; compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -129,6 +130,7 @@ cpu@4 { mmu-type = "riscv,sv39"; reg = <4>; riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; tlb-split; status = "okay"; cpu4_intc: interrupt-controller { @@ -165,11 +167,16 @@ cache-controller@2010000 { clint@2000000 { compatible = "sifive,fu540-c000-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0xC000>; - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, - <&cpu1_intc 3>, <&cpu1_intc 7>, - <&cpu2_intc 3>, <&cpu2_intc 7>, - <&cpu3_intc 3>, <&cpu3_intc 7>, - <&cpu4_intc 3>, <&cpu4_intc 7>; + interrupts-extended = <&cpu0_intc HART_INT_M_SOFT>, + <&cpu0_intc HART_INT_M_TIMER>, + <&cpu1_intc HART_INT_M_SOFT>, + <&cpu1_intc HART_INT_M_TIMER>, + <&cpu2_intc HART_INT_M_SOFT>, + <&cpu2_intc HART_INT_M_TIMER>, + <&cpu3_intc HART_INT_M_SOFT>, + <&cpu3_intc HART_INT_M_TIMER>, + <&cpu4_intc HART_INT_M_SOFT>, + <&cpu4_intc HART_INT_M_TIMER>; }; plic: interrupt-controller@c000000 { @@ -178,11 +185,15 @@ plic: interrupt-controller@c000000 { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; - interrupts-extended = <&cpu0_intc 11>, - <&cpu1_intc 11>, <&cpu1_intc 9>, - <&cpu2_intc 11>, <&cpu2_intc 9>, - <&cpu3_intc 11>, <&cpu3_intc 9>, - <&cpu4_intc 11>, <&cpu4_intc 9>; + interrupts-extended = <&cpu0_intc HART_INT_M_EXT>, + <&cpu1_intc HART_INT_M_EXT>, + <&cpu1_intc HART_INT_S_EXT>, + <&cpu2_intc HART_INT_M_EXT>, + <&cpu2_intc HART_INT_S_EXT>, + <&cpu3_intc HART_INT_M_EXT>, + <&cpu3_intc HART_INT_S_EXT>, + <&cpu4_intc HART_INT_M_EXT>, + <&cpu4_intc HART_INT_S_EXT>; riscv,ndev = <186>; }; @@ -210,7 +221,7 @@ serial0: serial@20000000 { interrupt-parent = <&plic>; interrupts = <90>; current-speed = <115200>; - clocks = <&clkcfg 8>; + clocks = <&clkcfg CLK_MMUART0>; status = "disabled"; }; @@ -222,7 +233,7 @@ serial1: serial@20100000 { interrupt-parent = <&plic>; interrupts = <91>; current-speed = <115200>; - clocks = <&clkcfg 9>; + clocks = <&clkcfg CLK_MMUART1>; status = "disabled"; }; @@ -234,7 +245,7 @@ serial2: serial@20102000 { interrupt-parent = <&plic>; interrupts = <92>; current-speed = <115200>; - clocks = <&clkcfg 10>; + clocks = <&clkcfg CLK_MMUART2>; status = "disabled"; }; @@ -246,7 +257,7 @@ serial3: serial@20104000 { interrupt-parent = <&plic>; interrupts = <93>; current-speed = <115200>; - clocks = <&clkcfg 11>; + clocks = <&clkcfg CLK_MMUART3>; status = "disabled"; }; @@ -256,7 +267,7 @@ mmc: mmc@20008000 { reg = <0x0 0x20008000 0x0 0x1000>; interrupt-parent = <&plic>; interrupts = <88>, <89>; - clocks = <&clkcfg 6>; + clocks = <&clkcfg CLK_MMC>; max-frequency = <200000000>; status = "disabled"; }; @@ -267,7 +278,7 @@ emac0: ethernet@20110000 { interrupt-parent = <&plic>; interrupts = <64>, <65>, <66>, <67>; local-mac-address = [00 00 00 00 00 00]; - clocks = <&clkcfg 4>, <&clkcfg 2>; + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names = "pclk", "hclk"; status = "disabled"; #address-cells = <1>; @@ -280,7 +291,7 @@ emac1: ethernet@20112000 { interrupt-parent = <&plic>; interrupts = <70>, <71>, <72>, <73>; local-mac-address = [00 00 00 00 00 00]; - clocks = <&clkcfg 5>, <&clkcfg 2>; + clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; status = "disabled"; clock-names = "pclk", "hclk"; #address-cells = <1>; From patchwork Fri Dec 17 09:33:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 525243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FE3BC433EF for ; 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IronPort-SDR: 7Kw5bP+EclTbeLT+LuDKHPnj86Ym8w8CEEHXHLa81TV3eopXkMJUWrAGNyuOv5lyV1B4jUorIG t3qkOW6lAvLBHSflkXcWf5HxnhX6uUXMxXvrai/aw8H6cU24ia550MdSt25pn+Ymssuvsbu3mL QrBo4q9vpeha8eEEbjorNMy7lKJhSPbARe9RkQDk2D3zz+Pw0WzUh5Qi2fPQCdJrAtzp+rl/Q/ sf7BqgU6SdKZqOWZ41KX3Fjozrj++NTI3xDQUOMnPa2hNr1sknnM0hFp41jnuc4TUfSW+D69An bm3x78dfr1vsHvh7CTjxl2uM X-IronPort-AV: E=Sophos;i="5.88,213,1635231600"; d="scan'208";a="147002782" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Dec 2021 02:33:55 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 17 Dec 2021 02:33:47 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 17 Dec 2021 02:33:41 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v2 15/17] riscv: dts: microchip: refactor icicle kit device tree Date: Fri, 17 Dec 2021 09:33:23 +0000 Message-ID: <20211217093325.30612-16-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211217093325.30612-1-conor.dooley@microchip.com> References: <20211217093325.30612-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Assorted minor changes to the MPFS/Icicle kit device tree: - rename serial to mmuart to match microchip documentation - enable mmuart4 instead of mmuart0 - move stdout path to serial1 to avoid collision with bootloader running on the e51 - split memory node to match updated fpga design - move phy0 inside mac1 node to match phy configuration - add labels where missing (cpus, cache controller) - add missing address cells & interrupts to MACs Signed-off-by: Conor Dooley --- .../microchip/microchip-mpfs-icicle-kit.dts | 52 ++++++++------ .../boot/dts/microchip/microchip-mpfs.dtsi | 70 ++++++++++--------- 2 files changed, 68 insertions(+), 54 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index 174f977c164b..f6542ef76046 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020 Microchip Technology Inc */ +/* Copyright (c) 2020-2021 Microchip Technology Inc */ /dts-v1/; @@ -13,25 +13,34 @@ / { compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; aliases { - ethernet0 = &emac1; - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; + ethernet0 = &mac1; + serial0 = &mmuart0; + serial1 = &mmuart1; + serial2 = &mmuart2; + serial3 = &mmuart3; + serial4 = &mmuart4; }; chosen { - stdout-path = "serial0:115200n8"; + stdout-path = "serial1:115200n8"; }; cpus { timebase-frequency = ; }; - memory@80000000 { + ddrc_cache_lo: memory@80000000 { device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; + reg = <0x0 0x80000000 0x0 0x2e000000>; clocks = <&clkcfg CLK_DDRC>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x0 0x0 0x40000000>; + clocks = <&clkcfg CLK_DDRC>; + status = "okay"; }; }; @@ -39,19 +48,19 @@ &refclk { clock-frequency = <600000000>; }; -&serial0 { +&mmuart1 { status = "okay"; }; -&serial1 { +&mmuart2 { status = "okay"; }; -&serial2 { +&mmuart3 { status = "okay"; }; -&serial3 { +&mmuart4 { status = "okay"; }; @@ -61,29 +70,32 @@ &mmc { bus-width = <4>; disable-wp; cap-sd-highspeed; + cap-mmc-highspeed; card-detect-delay = <200>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; sd-uhs-sdr104; }; -&emac0 { +&mac0 { phy-mode = "sgmii"; phy-handle = <&phy0>; - phy0: ethernet-phy@8 { - reg = <8>; - ti,fifo-depth = <0x01>; - }; }; -&emac1 { +&mac1 { status = "okay"; phy-mode = "sgmii"; phy-handle = <&phy1>; phy1: ethernet-phy@9 { reg = <9>; - ti,fifo-depth = <0x01>; + ti,fifo-depth = <0x1>; + }; + phy0: ethernet-phy@8 { + reg = <8>; + ti,fifo-depth = <0x1>; }; }; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index 808500be26c3..d311c5ea27c9 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -1,5 +1,5 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020 Microchip Technology Inc */ +/* Copyright (c) 2020-2021 Microchip Technology Inc */ /dts-v1/; #include "dt-bindings/clock/microchip,mpfs-clock.h" @@ -16,7 +16,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "sifive,e51", "sifive,rocket0", "riscv"; device_type = "cpu"; i-cache-block-size = <64>; @@ -34,7 +34,7 @@ cpu0_intc: interrupt-controller { }; }; - cpu@1 { + cpu1: cpu@1 { compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -61,7 +61,7 @@ cpu1_intc: interrupt-controller { }; }; - cpu@2 { + cpu2: cpu@2 { compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -88,7 +88,7 @@ cpu2_intc: interrupt-controller { }; }; - cpu@3 { + cpu3: cpu@3 { compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -115,7 +115,7 @@ cpu3_intc: interrupt-controller { }; }; - cpu@4 { + cpu4: cpu@4 { compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -153,8 +153,9 @@ soc { compatible = "simple-bus"; ranges; - cache-controller@2010000 { + cctrllr: cache-controller@2010000 { compatible = "sifive,fu540-c000-ccache", "cache"; + reg = <0x0 0x2010000 0x0 0x1000>; cache-block-size = <64>; cache-level = <2>; cache-sets = <1024>; @@ -162,10 +163,9 @@ cache-controller@2010000 { cache-unified; interrupt-parent = <&plic>; interrupts = <1>, <2>, <3>; - reg = <0x0 0x2010000 0x0 0x1000>; }; - clint@2000000 { + clint: clint@2000000 { compatible = "sifive,fu540-c000-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0xC000>; interrupts-extended = <&cpu0_intc HART_INT_M_SOFT>, @@ -198,15 +198,6 @@ plic: interrupt-controller@c000000 { riscv,ndev = <186>; }; - dma@3000000 { - compatible = "sifive,fu540-c000-pdma"; - reg = <0x0 0x3000000 0x0 0x8000>; - interrupt-parent = <&plic>; - interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, - <30>; - #dma-cells = <1>; - }; - clkcfg: clkcfg@20002000 { compatible = "microchip,mpfs-clkcfg"; reg = <0x0 0x20002000 0x0 0x1000>; @@ -214,7 +205,7 @@ clkcfg: clkcfg@20002000 { #clock-cells = <1>; }; - serial0: serial@20000000 { + mmuart0: serial@20000000 { compatible = "ns16550a"; reg = <0x0 0x20000000 0x0 0x400>; reg-io-width = <4>; @@ -223,10 +214,10 @@ serial0: serial@20000000 { interrupts = <90>; current-speed = <115200>; clocks = <&clkcfg CLK_MMUART0>; - status = "disabled"; + status = "disabled"; /* Reserved for the HSS */ }; - serial1: serial@20100000 { + mmuart1: serial@20100000 { compatible = "ns16550a"; reg = <0x0 0x20100000 0x0 0x400>; reg-io-width = <4>; @@ -238,7 +229,7 @@ serial1: serial@20100000 { status = "disabled"; }; - serial2: serial@20102000 { + mmuart2: serial@20102000 { compatible = "ns16550a"; reg = <0x0 0x20102000 0x0 0x400>; reg-io-width = <4>; @@ -250,7 +241,7 @@ serial2: serial@20102000 { status = "disabled"; }; - serial3: serial@20104000 { + mmuart3: serial@20104000 { compatible = "ns16550a"; reg = <0x0 0x20104000 0x0 0x400>; reg-io-width = <4>; @@ -262,42 +253,53 @@ serial3: serial@20104000 { status = "disabled"; }; + mmuart4: serial@20106000 { + compatible = "ns16550a"; + reg = <0x0 0x20106000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <94>; + clocks = <&clkcfg CLK_MMUART4>; + current-speed = <115200>; + status = "disabled"; + }; + /* Common node entry for emmc/sd */ mmc: mmc@20008000 { compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; reg = <0x0 0x20008000 0x0 0x1000>; interrupt-parent = <&plic>; - interrupts = <88>, <89>; + interrupts = <88>; clocks = <&clkcfg CLK_MMC>; max-frequency = <200000000>; status = "disabled"; }; - emac0: ethernet@20110000 { + mac0: ethernet@20110000 { compatible = "cdns,macb"; reg = <0x0 0x20110000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; interrupt-parent = <&plic>; - interrupts = <64>, <65>, <66>, <67>; + interrupts = <64>, <65>, <66>, <67>, <68>, <69>; local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names = "pclk", "hclk"; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; }; - emac1: ethernet@20112000 { + mac1: ethernet@20112000 { compatible = "cdns,macb"; reg = <0x0 0x20112000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; interrupt-parent = <&plic>; - interrupts = <70>, <71>, <72>, <73>; + interrupts = <70>, <71>, <72>, <73>, <74>, <75>; local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; - status = "disabled"; clock-names = "pclk", "hclk"; - #address-cells = <1>; - #size-cells = <0>; + status = "disabled"; }; - }; }; From patchwork Fri Dec 17 09:33:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 525242 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C65CEC4332F for ; Fri, 17 Dec 2021 09:34:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233103AbhLQJeK (ORCPT ); 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d="scan'208";a="147002811" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Dec 2021 02:34:03 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 17 Dec 2021 02:34:00 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 17 Dec 2021 02:33:54 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v2 17/17] MAINTAINERS: update riscv/microchip entry Date: Fri, 17 Dec 2021 09:33:25 +0000 Message-ID: <20211217093325.30612-18-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211217093325.30612-1-conor.dooley@microchip.com> References: <20211217093325.30612-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Update the RISC-V/Microchip entry by adding the microchip dts directory and myself as maintainer Signed-off-by: Conor Dooley --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7a2345ce8521..3b1d6be7bd56 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16348,8 +16348,10 @@ K: riscv RISC-V/MICROCHIP POLARFIRE SOC SUPPORT M: Lewis Hanly +M: Conor Dooley L: linux-riscv@lists.infradead.org S: Supported +F: arch/riscv/boot/dts/microchip/ F: drivers/mailbox/mailbox-mpfs.c F: drivers/soc/microchip/ F: include/soc/microchip/mpfs.h