From patchwork Mon Nov 12 15:23:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 150850 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3268993ljp; Mon, 12 Nov 2018 07:23:55 -0800 (PST) X-Google-Smtp-Source: AJdET5f78G1rtPsD4cLTJbg5aSANMy4TRdYHU7Ad61NrFpWgReB7o9G467QDrnNYbOvVA9P/Y8i6 X-Received: by 2002:a62:3346:: with SMTP id z67-v6mr1340260pfz.112.1542036235720; Mon, 12 Nov 2018 07:23:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542036235; cv=none; d=google.com; s=arc-20160816; b=D3lO7DniZDFu1BfHtdL6b5WV54l6xaNfCC9iDI76mFA0/7qaFZ8VgG7etrTH3M6Vcz E8HEm5TxBJ4rG9kBNBlW+cpfpx/o386ACE4HzuUMbiob3C4aned74UnG/bRIeKqGr++m pETLWxAcxsI7Eb5QO+MY5lmNAH5i0B0JcMlBP71Kfam2JKaF92jh2EKrbAylI/OCAwQD xpbacq2+PGWCKcieoKQ6rWQfk5J3k3vr5GtfL1/We/mIdhcoZBW8BUdYdQRiScr668NT V32q/GU2Z4Kv7Ym3eEvNq0ds1w7ETaXWgx7bMplVVC/XH+0x5YTjKdr9Avu1MfiF/+vK jrbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=+scvbKSgWS1sZ8YB01SJV/sDev8JcNZzuzRnAPkaFfU=; b=Nq9Xxo+eolBpSn+qbV47TzMOPbkpv4HtiXWD48lDvfhxe2wHitQiV2fZGP0JowC1iO OJ0UZixKCLmoqAibkBjBnOsSss0FdcDUT26/mzUqJecd1LHu9RjoJ+NG65zZRSmF9Hf0 Go3j/LBHzqdNxhdIeJYo2EZWH1IU3ChkbExb/Ri0WkGGDaJOvQR+Ln1wtJmtfXm4fwOf IhCvPEjnuLJyFKaVUG+uYKyAeN1cgXUIYZ+Z0CnVLiRz7I/q7SC4NCjRGSiAmRNkZ4IO 3psH5uH1RhKi86xCt4WDwndg6cmXPT8jb8+riMJ59hbwc+l5yXccEDNjdb6/3hcioQHs kHew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b6y9GgLs; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Mon, 12 Nov 2018 07:23:50 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:105e:a8d5:7c2c:2737:d373:11ee]) by smtp.gmail.com with ESMTPSA id t82-v6sm11192849wme.30.2018.11.12.07.23.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 12 Nov 2018 07:23:50 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Benjamin Gaignard Subject: [PATCH v3 1/4] dt-bindings: hwlock: Document STM32 hwspinlock bindings Date: Mon, 12 Nov 2018 16:23:39 +0100 Message-Id: <20181112152342.6561-2-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181112152342.6561-1-benjamin.gaignard@st.com> References: <20181112152342.6561-1-benjamin.gaignard@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add bindings for STM32 hardware spinlock device Signed-off-by: Benjamin Gaignard --- version 3 : - fix clock name in properties description version 2 : - change clock name from hwspinlock to hsem to be align with hardware documentation .../bindings/hwlock/st,stm32-hwspinlock.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt -- 2.15.0 diff --git a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt new file mode 100644 index 000000000000..adf4f000ea3d --- /dev/null +++ b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt @@ -0,0 +1,23 @@ +STM32 Hardware Spinlock Device Binding +------------------------------------- + +Required properties : +- compatible : should be "st,stm32-hwspinlock". +- reg : the register address of hwspinlock. +- #hwlock-cells : hwlock users only use the hwlock id to represent a specific + hwlock, so the number of cells should be <1> here. +- clock-names : Must contain "hsem". +- clocks : Must contain a phandle entry for the clock in clock-names, see the + common clock bindings. + +Please look at the generic hwlock binding for usage information for consumers, +"Documentation/devicetree/bindings/hwlock/hwlock.txt" + +Example of hwlock provider: + hwspinlock@4c000000 { + compatible = "st,stm32-hwspinlock"; + #hwlock-cells = <1>; + reg = <0x4c000000 0x400>; + clocks = <&rcc HSEM>; + clock-names = "hsem"; + }; From patchwork Mon Nov 12 15:23:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 150851 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3269112ljp; Mon, 12 Nov 2018 07:24:00 -0800 (PST) X-Google-Smtp-Source: AJdET5fAaxwPmpuDJ0c9v9pGqutX916C2g5W+Ms42Kv58+B7rPYcYqumlxXhgF28FUrhtRJ5Ax4Y X-Received: by 2002:a17:902:b20c:: with SMTP id t12-v6mr1273818plr.249.1542036240053; Mon, 12 Nov 2018 07:24:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542036240; cv=none; d=google.com; s=arc-20160816; b=Ge9nmLqd9ZUTUDkc/k7AIMDABeUZKAuqUXWVmOFw/exz0tvqm9+P9VWR4vAT12jiqF rBd5Tm18FFo8pt1LQdCxcN9PRxYh2OYTIi+R6UJZPLrj59BgsBEjBsIthkUpVkYoKzGz 0UMXbeRVsDw8UjaBPGVW2mQ2lwIYyiYEUuY03DSbNhYb//78wlkuBiGtPT5QEjA8om1T cVPoilCc64gSQYYoKmoIT+2ftNT4q76Ssr9+lCWK1eEeKCSZShuH13l141DtCpLeX+ck fwR2jBvqF5JpXV+E+9vaYliJdlza3bxiXx0xBZJGh7BuKaVNWwEcx+XzcyG5hhr8uKec lIyQ== ARC-Message-Signature: i=1; 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The hardware block provides 32 semaphores. Signed-off-by: Benjamin Gaignard --- version 3 : - use postcore_initcall() instead of module_platform_driver() version 2 : - change clock name from hwspinlock to hsem to be align with hardware documentation - remove useless licence terms from header - fix alphabetic order issues - do not abort remove function if hwspin_lock_unregister() failed drivers/hwspinlock/Kconfig | 9 ++ drivers/hwspinlock/Makefile | 1 + drivers/hwspinlock/stm32_hwspinlock.c | 156 ++++++++++++++++++++++++++++++++++ 3 files changed, 166 insertions(+) create mode 100644 drivers/hwspinlock/stm32_hwspinlock.c -- 2.15.0 diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig index e895d29500ee..7869c67e5b6b 100644 --- a/drivers/hwspinlock/Kconfig +++ b/drivers/hwspinlock/Kconfig @@ -49,6 +49,15 @@ config HWSPINLOCK_SPRD If unsure, say N. +config HWSPINLOCK_STM32 + tristate "STM32 Hardware Spinlock device" + depends on MACH_STM32MP157 + depends on HWSPINLOCK + help + Say y here to support the STM32 Hardware Spinlock device. + + If unsure, say N. + config HSEM_U8500 tristate "STE Hardware Semaphore functionality" depends on HWSPINLOCK diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile index b87c01a506a4..ed053e3f02be 100644 --- a/drivers/hwspinlock/Makefile +++ b/drivers/hwspinlock/Makefile @@ -8,4 +8,5 @@ obj-$(CONFIG_HWSPINLOCK_OMAP) += omap_hwspinlock.o obj-$(CONFIG_HWSPINLOCK_QCOM) += qcom_hwspinlock.o obj-$(CONFIG_HWSPINLOCK_SIRF) += sirf_hwspinlock.o obj-$(CONFIG_HWSPINLOCK_SPRD) += sprd_hwspinlock.o +obj-$(CONFIG_HWSPINLOCK_STM32) += stm32_hwspinlock.o obj-$(CONFIG_HSEM_U8500) += u8500_hsem.o diff --git a/drivers/hwspinlock/stm32_hwspinlock.c b/drivers/hwspinlock/stm32_hwspinlock.c new file mode 100644 index 000000000000..34a8e009dc93 --- /dev/null +++ b/drivers/hwspinlock/stm32_hwspinlock.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) STMicroelectronics SA 2018 + * Author: Benjamin Gaignard for STMicroelectronics. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hwspinlock_internal.h" + +#define STM32_MUTEX_COREID BIT(8) +#define STM32_MUTEX_LOCK_BIT BIT(31) +#define STM32_MUTEX_NUM_LOCKS 32 + +struct stm32_hwspinlock { + struct clk *clk; + struct hwspinlock_device bank; +}; + +static int stm32_hwspinlock_trylock(struct hwspinlock *lock) +{ + void __iomem *lock_addr = lock->priv; + u32 status; + + writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID, lock_addr); + status = readl(lock_addr); + + return status == (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID); +} + +static void stm32_hwspinlock_unlock(struct hwspinlock *lock) +{ + void __iomem *lock_addr = lock->priv; + + writel(STM32_MUTEX_COREID, lock_addr); +} + +static const struct hwspinlock_ops stm32_hwspinlock_ops = { + .trylock = stm32_hwspinlock_trylock, + .unlock = stm32_hwspinlock_unlock, +}; + +static int stm32_hwspinlock_probe(struct platform_device *pdev) +{ + struct stm32_hwspinlock *hw; + void __iomem *io_base; + struct resource *res; + size_t array_size; + int i, ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + io_base = devm_ioremap_resource(&pdev->dev, res); + if (!io_base) + return -ENOMEM; + + array_size = STM32_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock); + hw = devm_kzalloc(&pdev->dev, sizeof(*hw) + array_size, GFP_KERNEL); + if (!hw) + return -ENOMEM; + + hw->clk = devm_clk_get(&pdev->dev, "hsem"); + if (IS_ERR(hw->clk)) + return PTR_ERR(hw->clk); + + for (i = 0; i < STM32_MUTEX_NUM_LOCKS; i++) + hw->bank.lock[i].priv = io_base + i * sizeof(u32); + + platform_set_drvdata(pdev, hw); + pm_runtime_enable(&pdev->dev); + + ret = hwspin_lock_register(&hw->bank, &pdev->dev, &stm32_hwspinlock_ops, + 0, STM32_MUTEX_NUM_LOCKS); + + if (ret) + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static int stm32_hwspinlock_remove(struct platform_device *pdev) +{ + struct stm32_hwspinlock *hw = platform_get_drvdata(pdev); + int ret; + + ret = hwspin_lock_unregister(&hw->bank); + if (ret) + dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret); + + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static int __maybe_unused stm32_hwspinlock_runtime_suspend(struct device *dev) +{ + struct stm32_hwspinlock *hw = dev_get_drvdata(dev); + + clk_disable_unprepare(hw->clk); + + return 0; +} + +static int __maybe_unused stm32_hwspinlock_runtime_resume(struct device *dev) +{ + struct stm32_hwspinlock *hw = dev_get_drvdata(dev); + + clk_prepare_enable(hw->clk); + + return 0; +} + +static const struct dev_pm_ops stm32_hwspinlock_pm_ops = { + SET_RUNTIME_PM_OPS(stm32_hwspinlock_runtime_suspend, + stm32_hwspinlock_runtime_resume, + NULL) +}; + +static const struct of_device_id stm32_hwpinlock_ids[] = { + { .compatible = "st,stm32-hwspinlock", }, + {}, +}; +MODULE_DEVICE_TABLE(of, stm32_hwpinlock_ids); + +static struct platform_driver stm32_hwspinlock_driver = { + .probe = stm32_hwspinlock_probe, + .remove = stm32_hwspinlock_remove, + .driver = { + .name = "stm32_hwspinlock", + .of_match_table = stm32_hwpinlock_ids, + .pm = &stm32_hwspinlock_pm_ops, + }, +}; + +static int __init stm32_hwspinlock_init(void) +{ + return platform_driver_register(&stm32_hwspinlock_driver); +} +/* board init code might need to reserve hwspinlocks for predefined purposes */ +postcore_initcall(stm32_hwspinlock_init); + +static void __exit stm32_hwspinlock_exit(void) +{ + platform_driver_unregister(&stm32_hwspinlock_driver); +} +module_exit(stm32_hwspinlock_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Hardware spinlock driver for STM32 SoCs"); +MODULE_AUTHOR("Benjamin Gaignard "); From patchwork Mon Nov 12 15:23:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 150852 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3269145ljp; Mon, 12 Nov 2018 07:24:01 -0800 (PST) X-Google-Smtp-Source: AJdET5fps7fBgx2O9IwkvMH0QcwLQqTVVfw8/edUOuKMkJ+otpNUw+GTzb8cI6GPdnChZeqtzimT X-Received: by 2002:a63:ed15:: with SMTP id d21mr1160094pgi.305.1542036241516; Mon, 12 Nov 2018 07:24:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542036241; cv=none; d=google.com; s=arc-20160816; b=dvBDkoS5eIc1Hmw39g/IV8qMt6wF19p1Ad2dYyBFA5Tf/r2QhcqHrCVb0s+KIF7AZm HY0BpiSEC6DyT1ns+uFpxZUVKI65gnuxxZcmcCvxCmrORNdhERJ9+Y5ROur65vKmfXYW hxPJG7oOcMix09uLGHjysN+3HJoIrhru/glpzuA3BkkJpa4NlDSXTsG3NnvxuVpfWm6H z7yckpwXSMfoBsJWhoORAqnNU6ilHsmaWP0WdtxQR3RD8/PIEMLQVfmad7+BZZvA+96i qUD6Xzxs3rH75K52ssKYfnrP7AwA5/mqHLkARvqVbDSPYD3lHfWRJjAc1pgNNp8IZ1Bx dyYw== ARC-Message-Signature: i=1; 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Mon, 12 Nov 2018 07:23:56 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:105e:a8d5:7c2c:2737:d373:11ee]) by smtp.gmail.com with ESMTPSA id t82-v6sm11192849wme.30.2018.11.12.07.23.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 12 Nov 2018 07:23:55 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Benjamin Gaignard Subject: [PATCH v3 3/4] ARM: dts: stm32: Add hwspinlock node for stm32mp157 SoC Date: Mon, 12 Nov 2018 16:23:41 +0100 Message-Id: <20181112152342.6561-4-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181112152342.6561-1-benjamin.gaignard@st.com> References: <20181112152342.6561-1-benjamin.gaignard@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Declare hwspinlock device for stm32mp157 SoC Signed-off-by: Benjamin Gaignard --- arch/arm/boot/dts/stm32mp157c.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.15.0 diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 185541a5b69f..98f824d8b0f0 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -803,6 +803,15 @@ status = "disabled"; }; + hsem: hwspinlock@4c000000 { + compatible = "st,stm32-hwspinlock"; + #hwlock-cells = <1>; + reg = <0x4c000000 0x400>; + clocks = <&rcc HSEM>; + clock-names = "hwsem"; + status = "disabled"; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; From patchwork Mon Nov 12 15:23:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 150853 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3269180ljp; Mon, 12 Nov 2018 07:24:02 -0800 (PST) X-Google-Smtp-Source: AJdET5d2LcgBSMTJW/9eRQUG4TWWD1aiW0oKorRDGFXG6TxhiZ+M8nSIp0LbVKYi5kO+pXfitmVj X-Received: by 2002:aa7:828a:: with SMTP id s10-v6mr1275600pfm.63.1542036242624; Mon, 12 Nov 2018 07:24:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542036242; cv=none; d=google.com; s=arc-20160816; b=f6KTrPG+yep1tNznDwC6mJvfdUL2/sGsW2Jjo5Lwzg93O0fHICHYeeVIy6wdvMJuaQ APBdq8EZQEGMUsiU0ZCG5B0rjzug2kL9fCUTjZvDO56rpL3Rpv+0r3UT5k+ICxLHOgcf Evl+/cx+IBjSDMYoSxtttbA15QOd9NRhEIWL0Kn+0CevlRbBZG3QIwOqCfZHqQmtpTyT xWOVKuVQEFzElJ8ckGzJmOygpym+RWg3RYCG9HIr+5J7/hWUbHy8rzI+sGHT7NkEz8WQ ikbr1vCTBHiWVcS6HpcSchzG3owJ5qU0lpIviD4EjiwWTFUrdiEQQ2enICqGHxbzNEvz SlGw== ARC-Message-Signature: i=1; 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