From patchwork Fri Dec 17 16:15:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 525184 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C93EAC433F5 for ; Fri, 17 Dec 2021 16:15:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238938AbhLQQPz (ORCPT ); Fri, 17 Dec 2021 11:15:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235450AbhLQQPy (ORCPT ); Fri, 17 Dec 2021 11:15:54 -0500 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C8EDC06173E for ; Fri, 17 Dec 2021 08:15:54 -0800 (PST) Received: by mail-lj1-x229.google.com with SMTP id m12so4153639ljj.6 for ; Fri, 17 Dec 2021 08:15:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uYUgzkFeggr15Llsv7e4ur2WY7UgMDKixIFqjG977bw=; b=F2jtMQd6lFhjMlrZmy5glgqNLxj8Apz92pg2lAKfSb8G1i0CNoBUFiP9jX3BYPIVDD mfF7M4tzVp735bLJg/h3OQ9Shd8fRY1aYbW6hSik+O6qtKqWPHoJaoz6F68AlOsgxC8F lhCUxPVnU6lZZIVnroe6HKt7cp69kFRALfdxnKiuSbv+ayQEpNPzdxFf8Z5PxTBEfRkx a0jz6+Ofm6k3Rh5ippSmoMBPY+oV6CP3kE7NcIxGcE1WhiXU5FlApoD259firKb7AOJv E871UhUt0AwGXETud/tRgwH+wW7aAahl6wqbIUXzLVU8GlS05qXJS+prwp+bsKBG7HKn DIcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uYUgzkFeggr15Llsv7e4ur2WY7UgMDKixIFqjG977bw=; b=A2zf0FgyMESFZa4npoyvZNFDCbw4eL4MbW02M0RCAxy3SyewRzvOtcVioN8zULU1ns LnCiadnSLn9ApY6sjIBKHZnibq9mVfJWlfsSkG2b+dSC+GA3lIhiyj1CXFw0wa7zN2Ob wtxSIx/C8zxJPehETx0GaF1eUPEzPwcPsaqWTsQv4ZgXg61l/L5d4TeAvmLMf3T601X4 8oqVa6rOf6IkwxuKAOBOzcUq7CbC9D9lJdG2g0RnThjNRStZv7p52FcR2GP+n+FOiEeK idyDASxJIdl7ssDs2WTcOLx/yFxxGQl7ZSCR8i0/89RI+DAVNuWAtCMAhS6xih6D4oc2 L/Gg== X-Gm-Message-State: AOAM53311NunKzqelea43MMU2T4wvWZvkTyG7cgU3fFuH+Y0gqNNPnXr sHhqoaZL66cz0adIuRxSgJeMpg== X-Google-Smtp-Source: ABdhPJy0VR2MXAw5jDzn//v7uQ/IRIcK/YKLE/K7Gvn2bHvsL5z9YVii0mln7K2J8Er4j8Ywf3eYdA== X-Received: by 2002:a2e:870b:: with SMTP id m11mr3277105lji.20.1639757752333; Fri, 17 Dec 2021 08:15:52 -0800 (PST) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id w23sm1455089lfa.191.2021.12.17.08.15.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 08:15:51 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Linus Walleij , Daniel Palmer , Hao Fang , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 1/7] dt-bindings: clock: exynos850: Add bindings for Exynos850 sysreg clocks Date: Fri, 17 Dec 2021 18:15:43 +0200 Message-Id: <20211217161549.24836-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211217161549.24836-1-semen.protsenko@linaro.org> References: <20211217161549.24836-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org System Register is used to configure system behavior, like USI protocol, etc. SYSREG clocks should be provided to corresponding syscon nodes, to make it possible to modify SYSREG registers. While at it, add also missing PMU and GPIO clocks, which looks necessary and might be needed for corresponding Exynos850 features soon. Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring Acked-by: Chanwoo Choi Signed-off-by: Sam Protsenko --- Changes in v4: - (none) Changes in v3: - (none) Changes in v2: - Added R-b tag by Krzysztof Kozlowski - Added Ack tag by Rob Herring - Added Ack tag by Chanwoo Choi include/dt-bindings/clock/exynos850.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h index 8aa5e82af0d3..0b6a3c6a7c90 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -82,7 +82,10 @@ #define CLK_GOUT_I3C_PCLK 19 #define CLK_GOUT_I3C_SCLK 20 #define CLK_GOUT_SPEEDY_PCLK 21 -#define APM_NR_CLK 22 +#define CLK_GOUT_GPIO_ALIVE_PCLK 22 +#define CLK_GOUT_PMU_ALIVE_PCLK 23 +#define CLK_GOUT_SYSREG_APM_PCLK 24 +#define APM_NR_CLK 25 /* CMU_CMGP */ #define CLK_RCO_CMGP 1 @@ -99,7 +102,8 @@ #define CLK_GOUT_CMGP_USI0_PCLK 12 #define CLK_GOUT_CMGP_USI1_IPCLK 13 #define CLK_GOUT_CMGP_USI1_PCLK 14 -#define CMGP_NR_CLK 15 +#define CLK_GOUT_SYSREG_CMGP_PCLK 15 +#define CMGP_NR_CLK 16 /* CMU_HSI */ #define CLK_MOUT_HSI_BUS_USER 1 @@ -167,7 +171,9 @@ #define CLK_GOUT_MMC_EMBD_SDCLKIN 10 #define CLK_GOUT_SSS_ACLK 11 #define CLK_GOUT_SSS_PCLK 12 -#define CORE_NR_CLK 13 +#define CLK_GOUT_GPIO_CORE_PCLK 13 +#define CLK_GOUT_SYSREG_CORE_PCLK 14 +#define CORE_NR_CLK 15 /* CMU_DPU */ #define CLK_MOUT_DPU_USER 1 From patchwork Fri Dec 17 16:15:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 525183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABCA7C43219 for ; Fri, 17 Dec 2021 16:16:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238958AbhLQQP7 (ORCPT ); Fri, 17 Dec 2021 11:15:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238952AbhLQQP5 (ORCPT ); Fri, 17 Dec 2021 11:15:57 -0500 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 283CDC061574 for ; Fri, 17 Dec 2021 08:15:57 -0800 (PST) Received: by mail-lj1-x229.google.com with SMTP id p8so4157574ljo.5 for ; Fri, 17 Dec 2021 08:15:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=15f+Ze6FNJittgFADDHtUgTTcR8503nXs41Ek9JpvtE=; b=VbD2B0rwV8JxtTK9S3if64JlLCTU1+5bDRJEaKt2+UYbSqd1c/OxESWU/3Y9zpMOIp xORL74GWvGiHXlztq+1LW0UCfy+igFf9w1Jdu7K3HqLiFVk+l5pE5abZt8W5xNDMysQb qPfKGAXBnFTmeWw3njr5rer6bTHUcqXan0QYVjZTeHDdgGM8xHoTxbyClEO85YlrWxVL T/Q/1PNSV8AGTPboOBoUiOT+wNhZlWG3fwTttJlM1H2dHtlW5EE0XME16ajRXWYowCPq jNcnGhYz4Nb8taN4UIiBpVAlZVBLvacuRf/tQrV1Ztk4GPPl1KZvLewAFzHGNR9kqZ16 IrIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=15f+Ze6FNJittgFADDHtUgTTcR8503nXs41Ek9JpvtE=; b=guyAwuxwJoGv3OT9ULc3wJhnlqz2+9lADKafOVdpsVGCnrKbfGMkQ6IQqX16cxWG1e MvMtXpFKkndf3JwDtzMYoBIPMJiHGWWiTQaxSMbcSZOGRakYAl8hN9Nj8l7gDj1oLj2Q EaN6oRLOjDH3ty+UsZLIl6NfKFt0GtZW1PvkAHNcuHeunSpwpLEbta2J+4MunmrrwyAE cm7bRvCIWUfEq0NOOYthGB9Yiw8oWXzpSEFTOHklZCQdK/7dIy0f3Vrqh7wde8+x/qeU sf73FRwzVfBjDXZYrq1cXJzPBoa9FVggRhCDDzCHsHZCsH/v+ai+6JmU31Vrvs0BE+Ch f5+g== X-Gm-Message-State: AOAM532c8d1U03Liq/DhDnGeLurkNdNivbElU5ujF0gkR55Y5QVgyRQg e62IB2Pg/ut18CuKVMGfDEB01Q== X-Google-Smtp-Source: ABdhPJw+UbN8zwav66L+P3QZG0al+Rw25j2hqujD+XhCzFJatRciH4W39QillkSQFhbPjp34jDPPzA== X-Received: by 2002:a2e:808a:: with SMTP id i10mr3348752ljg.329.1639757755453; Fri, 17 Dec 2021 08:15:55 -0800 (PST) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id i18sm1453775lfu.67.2021.12.17.08.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 08:15:55 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Linus Walleij , Daniel Palmer , Hao Fang , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 3/7] dt-bindings: Add vendor prefix for WinLink Date: Fri, 17 Dec 2021 18:15:45 +0200 Message-Id: <20211217161549.24836-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211217161549.24836-1-semen.protsenko@linaro.org> References: <20211217161549.24836-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org WinLink Co., Ltd is a hardware design and manufacturing company based in South Korea. Official web-site: [1]. [1] http://win-link.net/ Acked-by: Rob Herring Signed-off-by: Sam Protsenko --- Changes in v4: - (none) Changes in v3: - (none) Changes in v2: - Added Ack tag by Rob Herring Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 4698213611db..25f94c723cbc 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1328,6 +1328,8 @@ patternProperties: description: Wiligear, Ltd. "^winbond,.*": description: Winbond Electronics corp. + "^winlink,.*": + description: WinLink Co., Ltd "^winstar,.*": description: Winstar Display Corp. "^wits,.*": From patchwork Fri Dec 17 16:15:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 525182 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A919AC433F5 for ; Fri, 17 Dec 2021 16:16:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239008AbhLQQQF (ORCPT ); Fri, 17 Dec 2021 11:16:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238954AbhLQQQA (ORCPT ); Fri, 17 Dec 2021 11:16:00 -0500 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 441BAC061401 for ; Fri, 17 Dec 2021 08:16:00 -0800 (PST) Received: by mail-lf1-x12c.google.com with SMTP id g11so5725566lfu.2 for ; Fri, 17 Dec 2021 08:16:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8QEZ+2WyzDr1Gicg/jJLj4X7PVW+zTh/aqldmrybsKU=; b=jde5oGiJDktLTwR1GMu3kEDrgm9gWmIyDoda+tYONGQnKX46PKpbWtYbpNDXM1JpKG eIYgFvwhcTOZVzlhD1gLLQm7W6GitRVq+nCAQELjGrlz4BdQnbz7W0hTX5U9DaROU0Co X/MCYqDFLc9Pgsn9XqN1waEpdZAtsWUlPZr1RVGWq9aoB3S5KkfftNVfGPXwUd9/NZJv tyBGFi1GhBpOlq9sNP7Ze7yegskuFoV98H50fvBBLcRi/h3bY4xEoxk7FwMcEQy2VHaM awOpBCGmBsvXSIGm3RIyEwumZlPw7NRBFmaS7JH4Bmmg3cKHo+qKKmORyZxg4C9H1Nzt pBiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8QEZ+2WyzDr1Gicg/jJLj4X7PVW+zTh/aqldmrybsKU=; b=dM6Dh15/8mO6ZRgF4tbRjSjhXnlm08HX5R458HwfR3lRvP5acKgiHGiWa7WkYkxv75 DgdiWVaWCSHnV7Cl1Ad73zmBZpyAGxpjzOsilGXiW5P4H82qkO/P4hkfYeJG7Ikbliff KUDyg/yGbeyK11sk1l7yW8wXcD788o00oGl6cTAkScqhgwCkQT/8sswVBecapsY44FdJ JT2JtXJIn67fumF35au2/TBFx1l11lSNMMU8HfY0BoLtthoN/lolBaUDKlzSF+XYgCQ1 DHw2+QeHwNnHCKMMryDBDClfNhNims9/0CkOEYHGoA9NL6h2t717ZdSUOuzxatk7949x uHXg== X-Gm-Message-State: AOAM533GKsBtAglGDUSww/g+Rpa4Dka3vPeObHz0PhTVuF9jnuVSDG+y RwJAldUAvPYht58BKLgbEFq22A== X-Google-Smtp-Source: ABdhPJxcwieciW+q+Dm535CYa+a8AniIkF2+9iWYEjr90PZnGSLPfd3zNHb+r7LM12QgFoFiwVadng== X-Received: by 2002:a05:6512:10cb:: with SMTP id k11mr3374991lfg.534.1639757758549; Fri, 17 Dec 2021 08:15:58 -0800 (PST) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id n30sm1453982lfi.194.2021.12.17.08.15.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 08:15:58 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Linus Walleij , Daniel Palmer , Hao Fang , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 5/7] dt-bindings: pinctrl: samsung: Add pin drive definitions for Exynos850 Date: Fri, 17 Dec 2021 18:15:47 +0200 Message-Id: <20211217161549.24836-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211217161549.24836-1-semen.protsenko@linaro.org> References: <20211217161549.24836-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org All Exynos850 GPIO blocks can use EXYNOS5420_PIN_DRV* definitions, except GPIO_HSI block. Add pin drive strength definitions for GPIO_HSI block correspondingly. Acked-by: Rob Herring Signed-off-by: Sam Protsenko --- Changes in v4: - (none) Changes in v3: - (none) Changes in v2: - Added Ack tag by Rob Herring include/dt-bindings/pinctrl/samsung.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/pinctrl/samsung.h b/include/dt-bindings/pinctrl/samsung.h index b1832506b923..950970634dfe 100644 --- a/include/dt-bindings/pinctrl/samsung.h +++ b/include/dt-bindings/pinctrl/samsung.h @@ -36,7 +36,10 @@ #define EXYNOS5260_PIN_DRV_LV4 2 #define EXYNOS5260_PIN_DRV_LV6 3 -/* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */ +/* + * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except + * GPIO_HSI block) + */ #define EXYNOS5420_PIN_DRV_LV1 0 #define EXYNOS5420_PIN_DRV_LV2 1 #define EXYNOS5420_PIN_DRV_LV3 2 @@ -56,6 +59,14 @@ #define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc #define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf +/* Drive strengths for Exynos850 GPIO_HSI block */ +#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */ +#define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */ +#define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */ +#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */ + #define EXYNOS_PIN_FUNC_INPUT 0 #define EXYNOS_PIN_FUNC_OUTPUT 1 #define EXYNOS_PIN_FUNC_2 2 From patchwork Fri Dec 17 16:15:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 525181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC2B3C433FE for ; Fri, 17 Dec 2021 16:16:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238945AbhLQQQI (ORCPT ); Fri, 17 Dec 2021 11:16:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238996AbhLQQQE (ORCPT ); Fri, 17 Dec 2021 11:16:04 -0500 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFF92C061759 for ; Fri, 17 Dec 2021 08:16:03 -0800 (PST) Received: by mail-lj1-x234.google.com with SMTP id a37so4095979ljq.13 for ; Fri, 17 Dec 2021 08:16:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AGJMeiOUT5EAa7p/t2no99UvrcKFkTeRZrArWF0eXgU=; b=dw12q6WLyAAnrdexTnghrgA2/fuQrQLnsq5p2hDsVX0yp9RVhiN2vlyx/34EcXevWV xs753mxfnqY+ehsf1XW34MtyCP3SRJmuuQ9bdhlORqUBbb6hyS13KjJImJQoFB88C7v8 6W/bwU6oS2LtkD+hWso6VT0Vli6yU2Amz7Q5SEjGbb3YCyc/sfpksW4T0MUNccKdL1/U 1jvSTuR5kYZzKF7n9I83i6fScHpXsOuNVmVdMWKclkN/CS6ZEpRvHeR9ULZbgRWeUF3M dHe9NqTVApmn4DBY2MgGx7zQX9QKmWp8Bp+0xMYpC3JeXlYFthvRWXDZbSHsOvmXhKWQ ERMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AGJMeiOUT5EAa7p/t2no99UvrcKFkTeRZrArWF0eXgU=; b=OKAyDT5x/U0ILMHke754ygqrwDlNStyBYg2B9+XqPSyLOJSgO+IvARivuZOcPPc0n6 eklfJvof8I8v12oOqKCeWJLfE5wW5PvUv9qpRkn6E7wj7+g5jKth9rDJjNmO4mrB2+vd x9iMTu5uahSlvgFMEuLeypujC85XvLlyXY+PGXHSc2DgMrFpFIbLwVqzpqdP0IV1qtbx RJcEtnEfHBVx44WShouyUhJaiSpUueNYxlnAk05xWTEoIwKYYnEa7l1HwXndvaKjgay/ eecJOMTGpWd3In5+Agnbr12CcUAAK32EWyM2oNqh3JW2azArk24vA1/uFWqvrDwuRe4b 3c1g== X-Gm-Message-State: AOAM5328yHFogoooxFEj5wDrwEHzCJDgUsRoWMkTrEAwWqn97j3sr/Cw N7iOCJF03q8uACbyyd+RzpS3ug== X-Google-Smtp-Source: ABdhPJw1DamsgUMvN5CEgLlSMoetBbjWx1x7A06Nf9fF6HLqisRNVLz5UnyKlspuOukgv/eWbITnIw== X-Received: by 2002:a2e:a78e:: with SMTP id c14mr3497687ljf.162.1639757761985; Fri, 17 Dec 2021 08:16:01 -0800 (PST) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id k5sm1457148lfj.112.2021.12.17.08.16.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 08:16:01 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Linus Walleij , Daniel Palmer , Hao Fang , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 7/7] arm64: dts: exynos: Add initial E850-96 board support Date: Fri, 17 Dec 2021 18:15:49 +0200 Message-Id: <20211217161549.24836-8-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211217161549.24836-1-semen.protsenko@linaro.org> References: <20211217161549.24836-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org E850-96 is a 96boards development board manufactured by WinLink. It incorporates Samsung Exynos850 SoC, and is compatible with 96boards mezzanine boards [1], as it follows 96boards standards. This patch adds minimal support for E850-96 board. Next features are enabled in board dts file and verified with minimal BusyBox rootfs: * User buttons * LEDs * Serial console * Watchdog timers * RTC * eMMC [1] https://www.96boards.org/products/mezzanine/ Signed-off-by: Sam Protsenko --- Changes in v4: - Moved "rtcclk" clock to board dts file - Specified "rtc_src" clock for rtc node in board dts file - Specified "rtcclk" clock for cmu_hsi node in board dts file - Improved comment for RAM memory node Changes in v3: - Ordered the pinctrl_alive phandle alphabetically (forgot to do so in v2) Changes in v2: - Removed board_id and board_rev properties - Removed BOARD_ID and BOARD_REV constants - Put dtb in alphabetical order in Makefile - Added "color" and "function" properties to LED nodes - Sorted all phandle overrides by phandle name - Removed 'broken-cd' property in eMMC node - Added memory node arch/arm64/boot/dts/exynos/Makefile | 1 + .../boot/dts/exynos/exynos850-e850-96.dts | 195 ++++++++++++++++++ 2 files changed, 196 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos850-e850-96.dts diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile index b41e86df0a84..be9df8e85c59 100644 --- a/arch/arm64/boot/dts/exynos/Makefile +++ b/arch/arm64/boot/dts/exynos/Makefile @@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \ exynos5433-tm2.dtb \ exynos5433-tm2e.dtb \ exynos7-espresso.dtb \ + exynos850-e850-96.dtb \ exynosautov9-sadk.dtb diff --git a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts new file mode 100644 index 000000000000..7b5a61d22cc5 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * WinLink E850-96 board device tree source + * + * Copyright (C) 2018 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Device tree source file for WinLink's E850-96 board which is based on + * Samsung Exynos850 SoC. + */ + +/dts-v1/; + +#include "exynos850.dtsi" +#include +#include +#include + +/ { + model = "WinLink E850-96 board"; + compatible = "winlink,e850-96", "samsung,exynos850"; + + chosen { + stdout-path = &serial_0; + }; + + /* + * RAM: 4 GiB (eMCP): + * - 2 GiB at 0x80000000 + * - 2 GiB at 0x880000000 + * + * 0xbab00000..0xbfffffff: secure memory (85 MiB). + */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x3ab00000>, + <0x0 0xc0000000 0x40000000>, + <0x8 0x80000000 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_voldown_pins &key_volup_pins>; + + volume-down-key { + label = "Volume Down"; + linux,code = ; + gpios = <&gpa1 0 GPIO_ACTIVE_LOW>; + }; + + volume-up-key { + label = "Volume Up"; + linux,code = ; + gpios = <&gpa0 7 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + /* HEART_BEAT_LED */ + user_led1: led-1 { + label = "yellow:user1"; + gpios = <&gpg2 2 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + }; + + /* eMMC_LED */ + user_led2: led-2 { + label = "yellow:user2"; + gpios = <&gpg2 3 GPIO_ACTIVE_HIGH>; + color = ; + linux,default-trigger = "mmc0"; + }; + + /* SD_LED */ + user_led3: led-3 { + label = "white:user3"; + gpios = <&gpg2 4 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_SD; + linux,default-trigger = "mmc2"; + }; + + /* WIFI_LED */ + wlan_active_led: led-4 { + label = "yellow:wlan"; + gpios = <&gpg2 6 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WLAN; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + /* BLUETOOTH_LED */ + bt_active_led: led-5 { + label = "blue:bt"; + gpios = <&gpg2 7 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_BLUETOOTH; + linux,default-trigger = "hci0rx"; + default-state = "off"; + }; + }; + + /* + * RTC clock (XrtcXTI); external, must be 32.768 kHz. + * + * TODO: Remove this once RTC clock is implemented properly as part of + * PMIC driver. + */ + rtcclk: clock-rtcclk { + compatible = "fixed-clock"; + clock-output-names = "rtcclk"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; +}; + +&cmu_hsi { + clocks = <&oscclk>, <&rtcclk>, + <&cmu_top CLK_DOUT_HSI_BUS>, + <&cmu_top CLK_DOUT_HSI_MMC_CARD>, + <&cmu_top CLK_DOUT_HSI_USB20DRD>; + clock-names = "oscclk", "rtcclk", "dout_hsi_bus", + "dout_hsi_mmc_card", "dout_hsi_usb20drd"; +}; + +&mmc_0 { + status = "okay"; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-highspeed; + non-removable; + mmc-hs400-enhanced-strobe; + card-detect-delay = <200>; + clock-frequency = <800000000>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <2 4>; + samsung,dw-mshc-hs400-timing = <0 2>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk_pins &sd0_cmd_pins &sd0_rdqs_pins &sd0_nreset_pins + &sd0_bus1_pins &sd0_bus4_pins &sd0_bus8_pins>; +}; + +&oscclk { + clock-frequency = <26000000>; +}; + +&pinctrl_alive { + key_voldown_pins: key-voldown-pins { + samsung,pins = "gpa1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + key_volup_pins: key-volup-pins { + samsung,pins = "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&rtc { + status = "okay"; + clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>, <&rtcclk>; + clock-names = "rtc", "rtc_src"; +}; + +&serial_0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&usi_uart { + samsung,clkreq-on; /* needed for UART mode */ + status = "okay"; +}; + +&watchdog_cl0 { + status = "okay"; +}; + +&watchdog_cl1 { + status = "okay"; +};