From patchwork Fri Dec 17 19:57:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 525158 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C144CC433EF for ; Fri, 17 Dec 2021 19:57:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240775AbhLQT5o (ORCPT ); Fri, 17 Dec 2021 14:57:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230108AbhLQT5n (ORCPT ); Fri, 17 Dec 2021 14:57:43 -0500 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06FD5C061574; Fri, 17 Dec 2021 11:57:43 -0800 (PST) Received: by mail-wr1-x432.google.com with SMTP id v11so6041612wrw.10; Fri, 17 Dec 2021 11:57:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vY0vz4OHKS9xBTPvFTuiZ+WCKN0YR03bQMvMz1cRhF4=; b=gPLlA3+3Q5vW0h81FGl1ipW5go9sYKsjbDaCKhhc7mkPhXyXgQ0USzkw3hlSMGkoCH +Khw/8AkroHdDq6ynxhoSpOs7mWuA8bmMpNdo0awlegaZjfetvoUq959Ou0j8jvb4ppF fOdnzNSL1XQNIj6jqlA6Rsd2lGZVUMVNM8Z0XJip8uzklCAAjRVjB9Z+C4ng++6prVjA Az/Cc+N1YfR9xFo+NJsUNMU4MeIJDj7YwTrMzp7TsFmOHLbcSlVxwSf1+UOsm0ghYGQd stuOzEwbUTJ2cqZGb+fX2EMpFE0H9h9XRza6TqxmArwtZCVvtOSSBRGPRqi12NOoQtp3 PMiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vY0vz4OHKS9xBTPvFTuiZ+WCKN0YR03bQMvMz1cRhF4=; b=f1ibBUm+q6V49HDOmzv5tG6QGM1uVzCCytqJO4M1qaUf9PfI3UGr6cvFiIk+gaKOvN 3/ukAsB7z7IeT6i9KMl9hLpN5K9scd5n1DDoSbVDyj9idWWlLWRe+JVuHwyjtC78EPRM gzJuQnkYwdFIg3YUUEtcDV6KdBYHYt4BEUtd7XnUZoStkScaQhrhK7xu5YsS55msquLj 61bHgq49t8Gcyjl8PIu4KSwQNi1WZBbbrOE7F9MnNKDUleH+9GYp6ifxecLsBANdqgft ySpUxyQIUgEm/6IXjDdp/Wlkq7jc3gq65idSKtB+3Rjg6mAlUwWG5XuDr10+mvvl3C8t usPg== X-Gm-Message-State: AOAM5311ZUJLaewxKjVk+PD7tatIaGOHwllk9TatlU4V2CaqWAC/sjCW xStq8mwiQa+Ara09uh6Eewbeal7NuMg= X-Google-Smtp-Source: ABdhPJziSE1jtSxEZSdWMcZFgQI+yul8bLRjuFrNT7FlAOtdEWLbrAFcRLEG9G25MFLMVAMT+V0cpQ== X-Received: by 2002:adf:f201:: with SMTP id p1mr3657136wro.243.1639771061248; Fri, 17 Dec 2021 11:57:41 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id r20sm6962666wmd.37.2021.12.17.11.57.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 11:57:40 -0800 (PST) From: Romain Perier To: Daniel Lezcano , Thomas Gleixner , Daniel Palmer , Romain Perier , Rob Herring , Russell King Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/6] clocksource: msc313e: Add support for ssd20xd-based platforms Date: Fri, 17 Dec 2021 20:57:23 +0100 Message-Id: <20211217195727.8955-3-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217195727.8955-1-romain.perier@gmail.com> References: <20211217195727.8955-1-romain.perier@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On SSD20X family SoCs the timers are connected to a 432MHz clock instead of 12MHz that all the previous chips used. There is no way to reduce or divide these clocks in the clktree yet as we do not know exactly where the 432MHz clock comes from but it is enabled at boot. The SSD20X timers have an input clock divider within the timer itself to configure the frequency. timer0 is preconfigured at power up to run at 12MHz so it is backwards compatible and doesn't need special handling right now. timer1 and timer2 run at 432Mhz at power up so are not backward compatible. This commit adds support for the input clock divider register and sets timer1 and timer2 to run at 48Mhz for clockevents. Signed-off-by: Romain Perier --- drivers/clocksource/timer-msc313e.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clocksource/timer-msc313e.c b/drivers/clocksource/timer-msc313e.c index 154e73444a0c..54c54ca7c786 100644 --- a/drivers/clocksource/timer-msc313e.c +++ b/drivers/clocksource/timer-msc313e.c @@ -33,7 +33,9 @@ #define MSC313E_REG_TIMER_MAX_HIGH 0x0c #define MSC313E_REG_COUNTER_LOW 0x10 #define MSC313E_REG_COUNTER_HIGH 0x14 +#define MSC313E_REG_TIMER_DIVIDE 0x18 +#define MSC313E_CLK_DIVIDER 9 #define TIMER_SYNC_TICKS 3 #ifdef CONFIG_ARM @@ -179,6 +181,12 @@ static int __init msc313e_clkevt_init(struct device_node *np) if (ret) return ret; + if (of_device_is_compatible(np, "sstar,ssd20xd-timer")) { + to->of_clk.rate = clk_get_rate(to->of_clk.clk) / MSC313E_CLK_DIVIDER; + to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); + writew(MSC313E_CLK_DIVIDER - 1, timer_of_base(to) + MSC313E_REG_TIMER_DIVIDE); + } + msc313e_clkevt.cpumask = cpu_possible_mask; msc313e_clkevt.irq = to->of_irq.irq; to->clkevt = msc313e_clkevt; @@ -242,3 +250,4 @@ static int __init msc313e_timer_init(struct device_node *np) } TIMER_OF_DECLARE(msc313, "mstar,msc313e-timer", msc313e_timer_init); +TIMER_OF_DECLARE(ssd20xd, "sstar,ssd20xd-timer", msc313e_timer_init); From patchwork Fri Dec 17 19:57:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 525157 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 513A3C4332F for ; Fri, 17 Dec 2021 19:57:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240721AbhLQT5r (ORCPT ); Fri, 17 Dec 2021 14:57:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240788AbhLQT5q (ORCPT ); Fri, 17 Dec 2021 14:57:46 -0500 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0AB80C061401; Fri, 17 Dec 2021 11:57:46 -0800 (PST) Received: by mail-wm1-x336.google.com with SMTP id j140-20020a1c2392000000b003399ae48f58so4783784wmj.5; Fri, 17 Dec 2021 11:57:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eU0XGPi4uBhPUtyGCEgXF/C3mA2MpO37zRIQErCawvo=; b=f9VKS4gPYA3Bst20TJUlMjQI5/yet1jmgxsDXqhLiDT1wAXa5vbUy+yT9pHpv+D9T7 RSbOMRYPqqV0KXJOstjbEa8DSH1ZHijqX+EUve2ebiEtiAUMtlr/kVvqVl/IyaUBDA4J JrTi715WFR7b5VHZTIexXlBh9aus6csf4oSHs9GV76cWI41D9wjIV3pIhsp1a+fAHFHb VFdj4Yjmf3JL+aT85WzUrqfA6wObE4SUBTJlibrbUo/mNn9qIAecOiuI+SVXnb2QK3sq iSHrjqSJ9jr6yOxrzJ3NfkW8QUJMqm57W9Wu34GO1hbTbAfTR0DIbEifUhR5i/Vp4yQB l2YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eU0XGPi4uBhPUtyGCEgXF/C3mA2MpO37zRIQErCawvo=; b=sLT94xt99HRUAVcldmQmyknVWGZEOM6kTEqHO2KuXnyv3at3Dx0mEK1xtIGDKzIB0F JSb7kQaIbqXnDLSojvRFZpMN1P0bxqiMFBV7WCJpn6t2TIurh7FkToNACpiguw4XFq/j aaRW8sav98ztshChV7pLFicm0FGtCjwxNtoeSVsrxdC1qfvCEKW2iFM2Ns8NkEpbXGZb SfXNn7lAqE37pb4+X8MEqRCwKwdKUzR6fCI88lEEEdF7OOMjO5bc4Q+2JTsU60C06YF8 xhZWHR8yRiORWtphCJGtaNSfQxuk2FS40uzVyp2+m3hJKVPkfjPnNE0Zfsur9I9z5QJR 3/zg== X-Gm-Message-State: AOAM531Kwdg5u1h7GwgkcLUgXXVPCH6BEZCBX7la0xcrCbYyRcolJEkl qoTLnxUU0DL9xCB+YaLRvApSpYJxn7ioZg== X-Google-Smtp-Source: ABdhPJxzAMjIxX2CXI+2wbGHfE/1VAILVFrQsoQogotGZM/HaypI7k2Q17zUtBJT70jYx40zjbJY/A== X-Received: by 2002:a1c:f418:: with SMTP id z24mr10925271wma.95.1639771064308; Fri, 17 Dec 2021 11:57:44 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id i17sm9340951wmq.48.2021.12.17.11.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 11:57:43 -0800 (PST) From: Romain Perier To: Daniel Lezcano , Thomas Gleixner , Daniel Palmer , Romain Perier , Rob Herring , Russell King Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/6] ARM: dts: mstar: Add timers device nodes Date: Fri, 17 Dec 2021 20:57:26 +0100 Message-Id: <20211217195727.8955-6-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217195727.8955-1-romain.perier@gmail.com> References: <20211217195727.8955-1-romain.perier@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds the definition of the timers device node. Signed-off-by: Romain Perier --- arch/arm/boot/dts/mstar-v7.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 89ebfe4f29da..7ede4cec0af9 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -123,6 +123,26 @@ watchdog@6000 { clocks = <&xtal_div2>; }; + timer@6040 { + compatible = "mstar,msc313e-timer"; + reg = <0x6040 0x40>; + clocks = <&xtal_div2>; + interrupts-extended = <&intc_fiq GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer1: timer@6080 { + compatible = "mstar,msc313e-timer"; + reg = <0x6080 0x40>; + clocks = <&xtal_div2>; + interrupts-extended = <&intc_fiq GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer2: timer@60c0 { + compatible = "mstar,msc313e-timer"; + reg = <0x60c0 0x40>; + clocks = <&xtal_div2>; + interrupts-extended = <&intc_fiq GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + }; intc_fiq: interrupt-controller@201310 { compatible = "mstar,mst-intc"; From patchwork Fri Dec 17 19:57:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 525156 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1BEEC433EF for ; Fri, 17 Dec 2021 19:57:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240784AbhLQT5w (ORCPT ); Fri, 17 Dec 2021 14:57:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230108AbhLQT5r (ORCPT ); Fri, 17 Dec 2021 14:57:47 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27B7DC061574; Fri, 17 Dec 2021 11:57:47 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id j18so6130238wrd.2; Fri, 17 Dec 2021 11:57:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pdysGXdTy+3TZBw7R9cw+LisV1Ndm6W0415d+TGMhCY=; b=pxeagsDGNrQVitn44DRzQfGy8d+GGjGuKOTiIAMdIHeOrYgHIcpNBQg4F0wK5FTdL8 3Ae6wxj6PfDehFJrQ6kzOxVYC/0PIoUeRPU8QpCUGND7FawfV7/oxPwUVHBvgnUwLn+q d3CC0s6Jmp0k0ndPYoosFWXklvQIDUeaW0T7ZPHSiTEl3Nm2ANK/+emk+yqjuHoB6kHK VBGx8bw4g+ROTudwT2OKxuQ4Iv6+wDvJSIepjlNRc9Mp9sF5pnPJ/L66ob7ZL7Cz5VP/ BsPBXD6MCQ2DBjeX/AytWi3Iu/qdijQVBZlZouMAVx0/oMdPVyXFfawugm+JJGV2wDJz YynA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pdysGXdTy+3TZBw7R9cw+LisV1Ndm6W0415d+TGMhCY=; b=NebIsSSe7a3o8oD3q6GaNvtbOtQQ4KXPUYnQZVVbtqjbaBVKq9ps/sy14X1SW0cj8I gvRzZYk4aShr+ulyXIyt/trdd411Rl+9fpTaqROG3jCAaXnsfw7VlgFVeCB2rPTA8/jG R2+V5QTYOMnMLyHQSJtO60r/KBzjL4SQ2FSsZlceKsEoYE2J0MUd2KAAdY57PEVsNe81 TtHhdSC3dGIAvtnwzf3+VM9HX05TPg9bJSyDEw3bnxjVjnPdXOwRW5vNEJvJQOq9Q5YN QlwNK0tViL4aEs5k1mXCA0rn0CqGKpJ9mZqYmegSmwjrAr2fcaKhlt2bvo1zcYa08mmF 3hMw== X-Gm-Message-State: AOAM532/ZPaVhCAE9IJIzNow/RQdV6wtpiqt7W4BlsblXIhJHA3ylYxi 9XtujZVn4uppp7dSmv9DYhCg505+yjZB2A== X-Google-Smtp-Source: ABdhPJwYyBxcJ045RgxyVdQRDDQgg/UGebYXwCxLP6/MWl/YtWWo/VehH1bzR3fhgk0gmpvCasNKUw== X-Received: by 2002:adf:efc6:: with SMTP id i6mr3689981wrp.428.1639771065406; Fri, 17 Dec 2021 11:57:45 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id y15sm11667631wry.72.2021.12.17.11.57.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 11:57:45 -0800 (PST) From: Romain Perier To: Daniel Lezcano , Thomas Gleixner , Daniel Palmer , Romain Perier , Rob Herring , Russell King Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 6/6] ARM: dts: mstar: Switch to compatible "sstar,ssd20xd-timer" on infinity2m Date: Fri, 17 Dec 2021 20:57:27 +0100 Message-Id: <20211217195727.8955-7-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217195727.8955-1-romain.perier@gmail.com> References: <20211217195727.8955-1-romain.perier@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This defines the real oscillators as input of timer1 and timer2 and switch to "sstar,ssd20xd-timer". Signed-off-by: Romain Perier --- arch/arm/boot/dts/mstar-infinity2m.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi index 6d4d1d224e96..080a18b9effb 100644 --- a/arch/arm/boot/dts/mstar-infinity2m.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -6,6 +6,14 @@ #include "mstar-infinity.dtsi" +/ { + clk_timer: timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <432000000>; + }; +}; + &cpus { cpu1: cpu@1 { device_type = "cpu"; @@ -20,3 +28,13 @@ smpctrl: smpctrl@204000 { status = "disabled"; }; }; + +&timer1 { + compatible = "sstar,ssd20xd-timer"; + clocks = <&clk_timer>; +}; + +&timer2 { + compatible = "sstar,ssd20xd-timer"; + clocks = <&clk_timer>; +};