From patchwork Thu Dec 16 13:43:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 524751 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE8E5C433F5 for ; Thu, 16 Dec 2021 13:43:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237669AbhLPNnz (ORCPT ); Thu, 16 Dec 2021 08:43:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237633AbhLPNnz (ORCPT ); Thu, 16 Dec 2021 08:43:55 -0500 Received: from michel.telenet-ops.be (michel.telenet-ops.be [IPv6:2a02:1800:110:4::f00:18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89655C06173E for ; Thu, 16 Dec 2021 05:43:54 -0800 (PST) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by michel.telenet-ops.be with bizsmtp id X1js2600G250X30061jsTx; Thu, 16 Dec 2021 14:43:53 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1mxr31-005QIH-U4; Thu, 16 Dec 2021 14:43:51 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1mxr31-009y7V-Fe; Thu, 16 Dec 2021 14:43:51 +0100 From: Geert Uytterhoeven To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Palmer Dabbelt , Paul Walmsley , Anup Patel Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Geert Uytterhoeven Subject: [PATCH v2 1/2] dt-bindings: timer: sifive,clint: Fix number of interrupts Date: Thu, 16 Dec 2021 14:43:47 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The number of interrupts lacks an upper bound, thus assuming one, causing properly grouped "interrupts-extended" properties to be flagged as an error by "make dtbs_check". Fix this by adding the missing "maxItems". As the architectural maximum is 4095 interrupts, using that as the limit would be unpractical. Hence limit it to 10 interrupts (two interrupts for a system management core, and two interrupts per core for other cores). This should be sufficient for now, and the limit can always be increased when the need arises. Signed-off-by: Geert Uytterhoeven --- v2: - Split in two patches, - Improve patch description and document limit rationale. --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 8d5f4687add9e81e..b75fd6f982b1ecb3 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -44,6 +44,7 @@ properties: interrupts-extended: minItems: 1 + maxItems: 10 additionalProperties: false From patchwork Thu Dec 16 13:43:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 524750 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B1C7C433FE for ; Thu, 16 Dec 2021 13:43:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237679AbhLPNnz (ORCPT ); Thu, 16 Dec 2021 08:43:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237668AbhLPNnz (ORCPT ); Thu, 16 Dec 2021 08:43:55 -0500 Received: from michel.telenet-ops.be (michel.telenet-ops.be [IPv6:2a02:1800:110:4::f00:18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5914C061747 for ; Thu, 16 Dec 2021 05:43:54 -0800 (PST) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by michel.telenet-ops.be with bizsmtp id X1jt26006250X30061jtUJ; Thu, 16 Dec 2021 14:43:53 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1mxr32-005QII-If; Thu, 16 Dec 2021 14:43:52 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1mxr31-009y7Z-GG; Thu, 16 Dec 2021 14:43:51 +0100 From: Geert Uytterhoeven To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Palmer Dabbelt , Paul Walmsley , Anup Patel Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Geert Uytterhoeven Subject: [PATCH v2 2/2] dt-bindings: timer: sifive,clint: Group interrupt tuples Date: Thu, 16 Dec 2021 14:43:48 +0100 Message-Id: <2859d2377f778b592c7b52597e698abc628de8dc.1639662093.git.geert@linux-m68k.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org To improve human readability and enable automatic validation, the tuples in "interrupts-extended" properties should be grouped using angle brackets. Signed-off-by: Geert Uytterhoeven Reviewed-by: Rob Herring --- v2: - Split in two patches. --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index b75fd6f982b1ecb3..3b25ec37d81159cb 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -57,10 +57,10 @@ examples: - | timer@2000000 { compatible = "sifive,fu540-c000-clint", "sifive,clint0"; - interrupts-extended = <&cpu1intc 3 &cpu1intc 7 - &cpu2intc 3 &cpu2intc 7 - &cpu3intc 3 &cpu3intc 7 - &cpu4intc 3 &cpu4intc 7>; + interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>, + <&cpu2intc 3>, <&cpu2intc 7>, + <&cpu3intc 3>, <&cpu3intc 7>, + <&cpu4intc 3>, <&cpu4intc 7>; reg = <0x2000000 0x10000>; }; ...