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[209.51.188.17]) by mx.google.com with ESMTPS id h11si851230qtk.626.2021.12.15.03.08.26 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 15 Dec 2021 03:08:26 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UmvqEaKd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:32804 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mxS92-0003Wi-PS for patch@linaro.org; Wed, 15 Dec 2021 06:08:24 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41156) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mxRiW-0006gQ-W3 for qemu-devel@nongnu.org; Wed, 15 Dec 2021 05:41:01 -0500 Received: from [2a00:1450:4864:20::42a] (port=42980 helo=mail-wr1-x42a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mxRiQ-0008PK-7G for qemu-devel@nongnu.org; Wed, 15 Dec 2021 05:41:00 -0500 Received: by mail-wr1-x42a.google.com with SMTP id c4so37352578wrd.9 for ; Wed, 15 Dec 2021 02:40:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=3N0iy2J8eRGNFowJGqdNyiNWKQh5DXE+loi7lECLI40=; b=UmvqEaKdyDTg0wll9UQi/LVi7KAST4Moggwh9aWhCv+voIiSF/CvHEfI42KmLj097t qCXdguAYaLUKbgICfggLj/zknN6HJsS3AF1O11xLpbBtM+C/csnf9ElqJDsCtwSsdk+G JitLznrjtIbXwY9MDXTm7SD1sCayBRMNJlZzOkbhheIsoGH04YjtsD+s9nJqk9G2n8Wn LTQY5BkyrOzipQy2ng8NliqpRvbOBQIawPTHiakKg4alm8qVYnHt+wgKrG6K39YVVy3u OhlXOH5dM1xK6KIGx1ENrbgZ3KyUVqjnKHAR0oJBGC5cqHj3N+c7TRGoM5Cxhbix6FlS os5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3N0iy2J8eRGNFowJGqdNyiNWKQh5DXE+loi7lECLI40=; b=v8k1N89ieJj5KQ/S/XAl2gJGSFI2qaKJysN/pyo0R//H6327EIOKJRVy7WRURExLkP HLcVnOGnXFvFgc/mjG+UOJvdwdDGiQF4x0Hzo0mQlK70Xp893xPWWzM6Pqr8PWebVBuW ccA48KA7vwEnAnyDtDd3/F+zttbbx1i8ewv6ECkgLhekjmMeoE6OH2He0I//QXBNfGXH /kU3JHbobqrgpvhyAJnaNX4sbJJ+00HugjYmDXFnHk9aycqgfx7YveNyi9mFHgu5SE5u U+q6w52tXgAGzfJRsGWMA2/fVgO/EcnZgspBhXXXRqgOFp4lhzVctuYhYUhDT6TKwSF5 W98Q== X-Gm-Message-State: AOAM532i2qUrVvO0MOuOZOGJ7EmYIyLzLgl4M7zpCalRLFoJ6N4TCjUT X8A247FkjOUcpsqeIRtU/cn9hWNvBINy8A== X-Received: by 2002:a5d:434f:: with SMTP id u15mr3999447wrr.492.1639564851839; Wed, 15 Dec 2021 02:40:51 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.40.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:40:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/33] hw/intc: clean-up error reporting for failed ITS cmd Date: Wed, 15 Dec 2021 10:40:17 +0000 Message-Id: <20211215104049.2030475-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42a (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée While trying to debug a GIC ITS failure I saw some guest errors that had poor formatting as well as leaving me confused as to what failed. As most of the checks aren't possible without a valid dte split that check apart and then check the other conditions in steps. This avoids us relying on undefined data. I still get a failure with the current kvm-unit-tests but at least I know (partially) why now: Exception return from AArch64 EL1 to AArch64 EL1 PC 0x40080588 PASS: gicv3: its-trigger: inv/invall: dev2/eventid=20 now triggers an LPI ITS: MAPD devid=2 size = 0x8 itt=0x40430000 valid=0 INT dev_id=2 event_id=20 process_its_cmd: invalid command attributes: invalid dte: 0 for 2 (MEM_TX: 0) PASS: gicv3: its-trigger: mapd valid=false: no LPI after device unmap SUMMARY: 6 tests, 1 unexpected failures Signed-off-by: Alex Bennée Reviewed-by: Peter Maydell Message-id: 20211112170454.3158925-1-alex.bennee@linaro.org Cc: Shashi Mallela Cc: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_its.c | 39 +++++++++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index c929a9cb5c3..b99e63d58f7 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -274,21 +274,36 @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t value, uint32_t offset, if (res != MEMTX_OK) { return result; } + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: " + "invalid dte: %"PRIx64" for %d (MEM_TX: %d)\n", + __func__, dte, devid, res); + return result; } - if ((devid > s->dt.maxids.max_devids) || !dte_valid || !ite_valid || - !cte_valid || (eventid > max_eventid)) { + + /* + * In this implementation, in case of guest errors we ignore the + * command and move onto the next command in the queue. + */ + if (devid > s->dt.maxids.max_devids) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid command attributes " - "devid %d or eventid %d or invalid dte %d or" - "invalid cte %d or invalid ite %d\n", - __func__, devid, eventid, dte_valid, cte_valid, - ite_valid); - /* - * in this implementation, in case of error - * we ignore this command and move onto the next - * command in the queue - */ + "%s: invalid command attributes: devid %d>%d", + __func__, devid, s->dt.maxids.max_devids); + + } else if (!dte_valid || !ite_valid || !cte_valid) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: " + "dte: %s, ite: %s, cte: %s\n", + __func__, + dte_valid ? "valid" : "invalid", + ite_valid ? "valid" : "invalid", + cte_valid ? "valid" : "invalid"); + } else if (eventid > max_eventid) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: eventid %d > %d\n", + __func__, eventid, max_eventid); } else { /* * Current implementation only supports rdbase == procnum From patchwork Wed Dec 15 10:40:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524248 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp230224imb; Wed, 15 Dec 2021 03:11:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJxs6/CPS4M88OeU1jMVXkBERypSVIvfT0L/ubVCoRMM9bfRMnJmIQuZkFDLqYNx7d+dw4sr X-Received: by 2002:a1f:a3ca:: with SMTP id m193mr2919587vke.4.1639566714864; Wed, 15 Dec 2021 03:11:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639566714; cv=none; d=google.com; s=arc-20160816; b=ZsN3iBRLrtwYNj6+cc7idD9A8HRxM0if5Cm4GfA369LBP73j/A8+n5vSzM8+jFnu8M eaUAGEVOYrPA88HGjd3Q3N6kGZD4Jdy0WysyIqQnIqeKq6E7E36DtJmaf4p4qFXnK3Ux 12WnnXinn99lZkeeYi1yuWd4VEx6sLZfOKVxDEcVLmwb0feTUR0F4gr4MP6artsorU9u Oj3VhyREt0F8s06oa6A0gp7jVVTdrL3eNsOhpfFjzuaOF92eXeZ1UehNLF7/dH/q0ieL dedmAbIczPHdWbWE6tKBUyVLg6b8UmWYXBZS3Wob/J24QVcOahsjMu5sEX9xBcnjcqHi g5OQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3biCzHE2MCm5qbLc2Z8ma5yuIbmYSUQlxcCb6aKsIYU=; b=h6JHZWOE7P/ojRIv36Cw4LDBngEuzU2SvXiqVKKs/5z8HGmxPsIuB3mVNBUE14aJ+g 3HiuJDp8n35t99GR3wZG0RxefIPAKZ4LNWFHmCHLILeVLuq7+tytXNB2N6czeV4PSnqv ASdUeDeH7Yq4xtape0dQPO2KTorUfe0+cxnLkapVPmUTWH8LYvJAlsYpYjpddPlusWOD VVtjKMFkgOYgsVeBijAAEDiPKkqr0k+BqC0nhvCYtERtHS+AsTkIHnhQK9YIPY+/zrjt /PYQPmXjmNVAkftjgy19EuikKSX3XZ3PPXPK3nkCEFcka1O8ccNB1IBK8e8QkbmtQuhR cgDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UTw907jt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.40.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:40:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/33] docs: aspeed: Add new boards Date: Wed, 15 Dec 2021 10:40:18 +0000 Message-Id: <20211215104049.2030475-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32f (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley Add X11, FP5280G2, G220A, Rainier and Fuji. Mention that Swift will be removed in v7.0. Signed-off-by: Joel Stanley Reviewed-by: Cédric Le Goater Message-id: 20211117065752.330632-2-joel@jms.id.au Signed-off-by: Peter Maydell --- docs/system/arm/aspeed.rst | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index cec87e3743d..41a9bd5608e 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -14,6 +14,7 @@ AST2400 SoC based machines : - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC - ``quanta-q71l-bmc`` OpenBMC Quanta BMC +- ``supermicrox11-bmc`` Supermicro X11 BMC AST2500 SoC based machines : @@ -21,12 +22,16 @@ AST2500 SoC based machines : - ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC - ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC - ``sonorapass-bmc`` OCP SonoraPass BMC -- ``swift-bmc`` OpenPOWER Swift BMC POWER9 +- ``swift-bmc`` OpenPOWER Swift BMC POWER9 (to be removed in v7.0) +- ``fp5280g2-bmc`` Inspur FP5280G2 BMC +- ``g220a-bmc`` Bytedance G220A BMC AST2600 SoC based machines : - ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7) - ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC +- ``rainier-bmc`` IBM Rainier POWER10 BMC +- ``fuji-bmc`` Facebook Fuji BMC Supported devices ----------------- From patchwork Wed Dec 15 10:40:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524247 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp228569imb; Wed, 15 Dec 2021 03:09:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJxnJOBM38VoPOeD+HzG43/gHXDNRsDSpdfWjn4ILRPc+dNVGYmf/IHpRVA6TaZNPLj6SYBi X-Received: by 2002:a05:622a:198c:: with SMTP id u12mr11461762qtc.416.1639566582911; Wed, 15 Dec 2021 03:09:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639566582; cv=none; d=google.com; s=arc-20160816; b=AKCzdsCvuua+LriIGktQ7eKMRO082M8kltxxxHm0srfxuqigvFKWzFu3b2iSwKvILm Pp4qPH/maq60FxIOfudF3OyDBWYb86DSXMvGod2lG5Rt52udF/dYY4+OIiQQ+mvyA5D1 3UXNT7PoXrmmecfZ9yiUJT9VMyXc7Y0k+UBnSklGmrT2Kw9nRa4C4Jz6v3sHBOLMcrUy 9FyG3ckJD7lErNE4+tG+K/b557TvSHU99/v/SU+E/iYKLMuN2VP8/KkH185Oey9FxS/V 4pwjG2vhVC82Rm0w1w4w5am/8xeVMpdg2ayJrHd91ntsnJO3Ql7OdoO0hWjD7ig2xLNh M2jw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UBBDqlYIm8PMy/t/5ZURYCoEvCyggC0aUTjUZpv2NTw=; b=ivPXRx+sOothsag4N6wyIZOKde/8DwgEwqwOoy55Wv/GAO/AsgfWBOdQ0ipIbLoTNF yZZlqa4HqWjtFzGtXfvimELnTN42Yq75IpFIxtO5SRE8Ogug1RgIHDmAv6PsFwqd4nRC cuGC4JqeIBuqR1Uj3s9dh7dxUAMxZU+aqumNoBboxQutAW6bJdHQISgPDAwR3THExWoX EZ9hlbA/0SGjWcRWN/Hu2hlLCND7Aigxp8FKIQS086NvlDmc3SYO1Aa7jVxKTt7oWM9N q0IBDq3cPEnqmXYUHga0saTWNMngUh4HnYNYdQUx+UZeeslmjgoHrREds40Vo2cyIdzH OysA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m+HatviB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.40.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:40:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/33] docs: aspeed: Update OpenBMC image URL Date: Wed, 15 Dec 2021 10:40:19 +0000 Message-Id: <20211215104049.2030475-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42d (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley This is the latest URL for the OpenBMC CI. The old URL still works, but redirects. Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley Message-id: 20211117065752.330632-3-joel@jms.id.au Signed-off-by: Peter Maydell --- docs/system/arm/aspeed.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 41a9bd5608e..b87697fcf0b 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -82,7 +82,7 @@ The Aspeed machines can be started using the ``-kernel`` option to load a Linux kernel or from a firmware. Images can be downloaded from the OpenBMC jenkins : - https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/distro=ubuntu,label=docker-builder + https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/ or directly from the OpenBMC GitHub release repository : From patchwork Wed Dec 15 10:40:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524251 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp232743imb; Wed, 15 Dec 2021 03:15:09 -0800 (PST) X-Google-Smtp-Source: ABdhPJz9soDUM1oxJf/06sNzDMwgsKGVjgC72wQDI1l/bqKwZkCtjtu5UK3d/grESiAT/ucnBdYt X-Received: by 2002:a25:8e0d:: with SMTP id p13mr5546362ybl.46.1639566909849; Wed, 15 Dec 2021 03:15:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639566909; cv=none; d=google.com; s=arc-20160816; b=uvrw9wIJulBna0xxLTAoWkwcWG+7xezeRGpc1hGCcR5qSKp7pOvI0uxN6wuE7FJQTc P15pozytAed1ejZaV+JhdnyxpHr9wn3A7HK5eACnTUC/wmATeQlkyuaRcpPPN2aD7Rbz sR+vgg7tNobeI2Iqyd1iUMD3IxgmLxkoGdjvr2LzpjDPHDbjh8C+KhK2GMsi8QJaiYHe E18dpacK+0JDnGJsTQzLdvX/bOkMJsqonxT4bESp50MtMNFp/rXKr7z8h0XhchpI2Sh3 +1OiuLaKxunTM2OohUjVyGIMpYMm/6NRjmQCTyYlcQkFR2BdBr9Iqb1yWP0ExC1g5CTk jLYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5tWc0SpCxjJ+nrESHqQyrz7We4RccBy36x+rXAWJeBE=; b=nZbpw24wLRNw2p/crSCU/yj9np0YgIHpIaDN2GYi45tPnvK7nX5hqucdycR8mDizi1 OEkUsGr8r7GPMY2ODA+D/5xk931kYj8T8JTp8Wg2A3CFa2hV7KYxupyCw96IyOt3/LBo FgWyt7BXQwVacb53YFNL/d0rNkgqQJTUj1WIGbHnXFs2ggcX7W6YZ7gjPoxs3HW9QHzC j5FgnplnAum0EeWiAYJvMLtRixkkDCRDfD90MsojiW1QfYuZv1B8PByCAGtTyM4IMxK4 LHUBK91IacFLxZte0SPwxnKm/Ya2Qem3bE8GK1Y5p2zBRydc+7RWoI/queIpTEEood1U 0YVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SqVMyirx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.40.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:40:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/33] docs: aspeed: Give an example of booting a kernel Date: Wed, 15 Dec 2021 10:40:20 +0000 Message-Id: <20211215104049.2030475-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::430 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley A common use case for the ASPEED machine is to boot a Linux kernel. Provide a full example command line. Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley Message-id: 20211117065752.330632-4-joel@jms.id.au Signed-off-by: Peter Maydell --- docs/system/arm/aspeed.rst | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index b87697fcf0b..6aafd611e9a 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -78,9 +78,9 @@ Missing devices Boot options ------------ -The Aspeed machines can be started using the ``-kernel`` option to -load a Linux kernel or from a firmware. Images can be downloaded from -the OpenBMC jenkins : +The Aspeed machines can be started using the ``-kernel`` and ``-dtb`` options +to load a Linux kernel or from a firmware. Images can be downloaded from the +OpenBMC jenkins : https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/ @@ -88,6 +88,15 @@ or directly from the OpenBMC GitHub release repository : https://github.com/openbmc/openbmc/releases +To boot a kernel directly from a Linux build tree: + +.. code-block:: bash + + $ qemu-system-arm -M ast2600-evb -nographic \ + -kernel arch/arm/boot/zImage \ + -dtb arch/arm/boot/dts/aspeed-ast2600-evb.dtb \ + -initrd rootfs.cpio + The image should be attached as an MTD drive. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.40.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:40:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/33] docs: aspeed: ADC is now modelled Date: Wed, 15 Dec 2021 10:40:21 +0000 Message-Id: <20211215104049.2030475-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::434 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley Move it to the supported list. Signed-off-by: Joel Stanley Message-id: 20211117065752.330632-5-joel@jms.id.au Signed-off-by: Peter Maydell --- docs/system/arm/aspeed.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 6aafd611e9a..d8b102fa0ad 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -56,13 +56,13 @@ Supported devices * Front LEDs (PCA9552 on I2C bus) * LPC Peripheral Controller (a subset of subdevices are supported) * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA + * ADC Missing devices --------------- * Coprocessor support - * ADC (out of tree implementation) * PWM and Fan Controller * Slave GPIO Controller * Super I/O Controller From patchwork Wed Dec 15 10:40:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524250 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp231760imb; Wed, 15 Dec 2021 03:13:49 -0800 (PST) X-Google-Smtp-Source: ABdhPJzfXosVdACF4q8aMi0xa9rZVpmL+xv6vYrN9ZSnOXSIfZ/x3696ZRYYaCrNP01NpaK4W+XA X-Received: by 2002:a05:6102:316c:: with SMTP id l12mr2614637vsm.1.1639566829372; Wed, 15 Dec 2021 03:13:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639566829; cv=none; d=google.com; s=arc-20160816; b=oD9wek7AoCifojBg5AIst+zWkTReet5NYbMNxUJ/rVmljSEZCftvj2txzcRdNKfw/U z0cjvNDxVXcWnKz1sWv+ulnyfDXI5I31BdbswdDPMUxccwLNIPfVpDpiv6dm03f+a/AW oNMDkZs2+m5Ht0RaERnwO66pex1hO2x7IBkkHD2Bth4r3yMh/E3rzYNsEYb+sFDMRC2R 2yUm1i9aJ3VzrGPBTgB1iFnErv1DEIn4886yXetGuoephY4oFdDV2g44JfIjvhFfo69B mnfLSd+XIhmS9WuC0V4kXZ+AmAj/NqKVAElF/LSLmxRzqyD9jFNgd+5baRSf7xnWxWyK hWDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=im9w3HrkyiMx/80cKplH47XGgi3jaF34akWwEvzEQuQ=; b=KwghIKQZvggiZgelrdd4IJ5fb1nasNGbZiYHurqZP2B03iK0JKdhWJIsfgJYQwS6Ti l9ha6anWiIaqO2htyrmMbB7h7ZYoIhpOBC8zzNpJ9hm/3J3D7AuBuHFFv8iuOHUAZnjv oNXRId0/+/YF2/kXz0eBpzdIrNlPyJYX1Z0nF3fYaU2QmCpa6dVNmuRlmX7WAf7/xomk efZW7kbpawd0X/RXf7tyxLeJ9XiahuneNE0s/dXEy9MZnq8POM802GWYvEu/kDgt4CRW JWU3TWdiZlqPcLVkv+YJjIffdQ2mzwuLkCpXM3pvgAAfLX8MbFSbP3IDotkJe5Wu67OE QX1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A0Y8CE+r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.40.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:40:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/33] Fix STM32F2XX USART data register readout Date: Wed, 15 Dec 2021 10:40:22 +0000 Message-Id: <20211215104049.2030475-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::436 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Olivier Hériveaux Fix issue where the data register may be overwritten by next character reception before being read and returned. Signed-off-by: Olivier Hériveaux Reviewed-by: Peter Maydell Reviewed-by: Alistair Francis Message-id: 20211128120723.4053-1-olivier.heriveaux@ledger.fr Signed-off-by: Peter Maydell --- hw/char/stm32f2xx_usart.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c index 8df0832424c..fde67f4f03f 100644 --- a/hw/char/stm32f2xx_usart.c +++ b/hw/char/stm32f2xx_usart.c @@ -103,10 +103,11 @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr, return retvalue; case USART_DR: DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr); + retvalue = s->usart_dr & 0x3FF; s->usart_sr &= ~USART_SR_RXNE; qemu_chr_fe_accept_input(&s->chr); qemu_set_irq(s->irq, 0); - return s->usart_dr & 0x3FF; + return retvalue; case USART_BRR: return s->usart_brr; case USART_CR1: From patchwork Wed Dec 15 10:40:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524255 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp235108imb; Wed, 15 Dec 2021 03:18:13 -0800 (PST) X-Google-Smtp-Source: ABdhPJz61urIBtvof2QxT85PvWbfVrznns0ZuKGpjYAlB0KLx1jQz/KYwjqBXNnKDDbKtuNob80f X-Received: by 2002:a25:ccd0:: with SMTP id l199mr5939273ybf.39.1639567092944; Wed, 15 Dec 2021 03:18:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639567092; cv=none; d=google.com; s=arc-20160816; b=TxUMysSslqmdjRusIhIHnX17Hd4dfZPR5gDP+hcaX2jxXtDqnw0ttTV4OwY96BS7fc kH7UJDpcwgdf6e2dYLeYAqQzGGrpDNMlmw24Nb4idIgOMKe01ErauVIrCOvSqka0hoF3 4zRHiN68oc5ZV0k9HGIt+VoHSueY2cQzva2XkTyvYNuzfHS00CMzKG0u2+o6Tn+QI5O3 a64Gviq1k0Q2OpFaexmcpWSv8bcetirdTLv72ykJcHZJyKl3iTty3uW8BKxkahdpulxl v+1pzT2rf8Q2QcM1CYMuIAeRa1wZMG78AGR+Wx7a1w5GRFh/NLFwdKBM+10+uVYDnwTB GQIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fqhgJq2CB3BEUpVjd/zJhy6cguqz09ikl8mo+0Dzrp4=; b=ck0Hb9rwaLSnYq8ZECfVMsSSWgLpONeMBjM0td2vzQ/dQcq3npW7aDv8rNVTqNo0PW yZrTq5k/HlblBEBxedIa8YIfNprgJOQ0jOKRTIfPF7bmv3jSYdkyRBnYhipV+xqyatSq 7L+AsW1B9oKNmI3bKp3FIcONpR+v3V8HLFYDxUVsRHyWX8Q5gGm4lh6ng2m6Fj929dkS IPGmzcz9ROjJDWSkTZTgSLLhygLJigshRWAJGQJc+uY8LMzr/kEzdDIgppqfR05njJVi PUu5Dh6212jV3WfQpP131b52b37LLNd9dgxqQUaL2NIPbW62B9FO/dfUe0ngPn4VpeG8 ns7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Fgtm/atD"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.40.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:40:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/33] hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from arm_gicv3_cpuif.c Date: Wed, 15 Dec 2021 10:40:23 +0000 Message-Id: <20211215104049.2030475-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42a (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé gicv3_set_gicv3state() is used by arm_gicv3_common.c in arm_gicv3_common_realize(). Since we want to restrict arm_gicv3_cpuif.c to TCG, extract gicv3_set_gicv3state() to a new file. Add this file to the meson 'specific' source set, since it needs access to "cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Message-id: 20211115223619.2599282-2-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 10 +--------- hw/intc/arm_gicv3_cpuif_common.c | 22 ++++++++++++++++++++++ hw/intc/meson.build | 1 + 3 files changed, 24 insertions(+), 9 deletions(-) create mode 100644 hw/intc/arm_gicv3_cpuif_common.c diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 85fc369e550..d7e03d0cab8 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1,5 +1,5 @@ /* - * ARM Generic Interrupt Controller v3 + * ARM Generic Interrupt Controller v3 (emulation) * * Copyright (c) 2016 Linaro Limited * Written by Peter Maydell @@ -21,14 +21,6 @@ #include "hw/irq.h" #include "cpu.h" -void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) -{ - ARMCPU *arm_cpu = ARM_CPU(cpu); - CPUARMState *env = &arm_cpu->env; - - env->gicv3state = (void *)s; -}; - static GICv3CPUState *icc_cs_from_env(CPUARMState *env) { return env->gicv3state; diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_common.c new file mode 100644 index 00000000000..ff1239f65db --- /dev/null +++ b/hw/intc/arm_gicv3_cpuif_common.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ARM Generic Interrupt Controller v3 + * + * Copyright (c) 2016 Linaro Limited + * Written by Peter Maydell + * + * This code is licensed under the GPL, version 2 or (at your option) + * any later version. + */ + +#include "qemu/osdep.h" +#include "gicv3_internal.h" +#include "cpu.h" + +void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + + env->gicv3state = (void *)s; +}; diff --git a/hw/intc/meson.build b/hw/intc/meson.build index c89d2ca180e..11352806db2 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -25,6 +25,7 @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c')) specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c')) +specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c')) specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c')) specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) From patchwork Wed Dec 15 10:40:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524271 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp247091imb; Wed, 15 Dec 2021 03:34:33 -0800 (PST) X-Google-Smtp-Source: ABdhPJy+Ixlgxt1IU1x0h9sgpMWixt8V+b8saesz2YkRNjsZ2q3gaKur/UCeTxB0t/xWkVVmHk9P X-Received: by 2002:a02:91c8:: with SMTP id s8mr5430392jag.662.1639568073157; Wed, 15 Dec 2021 03:34:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639568073; cv=none; d=google.com; s=arc-20160816; b=JaHutNnmVgbKVVRQGZC4XDxqBdQpKU4gzCcMwuSV45J68cF3CklXtIbj1PPNo5LOL5 wbJ8+AH88fAEJT3TDLZDEnd/jUK6reyUMFgYR4Mg55aLccYKIJ9p9FDZtb4I6ElA/rgu CI1jgLIMZUbb8B7h946JZE7suc4HZNwWMlXY/VJ3xVsTpenfB2NasnXa7Mt4jrcxyQ9G NOpZyRMPmdOaNnRdc60N1St50+X3T9ApGWlchh+MwB1x78k/llNznWB1x1V4IWMgoiDU 6hTfUGHho9U27X7RTAGJp/BVzKm1GPqCR0OQ+GEbqDHt9P4gWdmVXVVSVadwgCDcArYi 7S9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4nPJwOh5yptV6qB589WsMaQo4rGNTXm5s0QSiyJipoM=; b=CWjqo5FBKQaEsGrVV6f+efveTDi2++M/p2OvVOqI8ebEFDzw7+oPf4jMnZr//wACit V/kdCrhIcK2ajABBWSxc1meXt502W/Tw5lmqTGJ2Ptv/H48KWo/M92ffHLYB7hDGD8Wp xz+RsLUfNsdcMSloheHlVedJpyp3+F9Rv9Ot0msuTCX8PzL14GhKWBqmmvnaXQ/o9UKi dDpZSNVuCK6oedWsyT0IxZmtvxUexZ6+sAn/e/mPYGQYVuPUK5dQlY91KaDFlzzMxpwA 41sNquoSJt7iZpgckofpM7sabJjDleDhjnigLoD8YS79AarC9iRKOPXrZHVCVewz2eE1 4A6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ST3jK+Hy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.40.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:40:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/33] hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig selector Date: Wed, 15 Dec 2021 10:40:24 +0000 Message-Id: <20211215104049.2030475-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::429 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé The TYPE_ARM_GICV3 device is an emulated one. When using KVM, it is recommended to use the TYPE_KVM_ARM_GICV3 device (which uses in-kernel support). When using --with-devices-FOO, it is possible to build a binary with a specific set of devices. When this binary is restricted to KVM accelerator, the TYPE_ARM_GICV3 device is irrelevant, and it is desirable to remove it from the binary. Therefore introduce the CONFIG_ARM_GIC_TCG Kconfig selector which select the files required to have the TYPE_ARM_GICV3 device, but also allowing to de-select this device. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Message-id: 20211115223619.2599282-3-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3.c | 2 +- hw/intc/Kconfig | 5 +++++ hw/intc/meson.build | 10 ++++++---- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 9f5f815db9b..715df5421dd 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -1,5 +1,5 @@ /* - * ARM Generic Interrupt Controller v3 + * ARM Generic Interrupt Controller v3 (emulation) * * Copyright (c) 2015 Huawei. * Copyright (c) 2016 Linaro Limited diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 78aed93c454..010ded7eae0 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -25,6 +25,11 @@ config APIC select MSI_NONBROKEN select I8259 +config ARM_GIC_TCG + bool + default y + depends on ARM_GIC && TCG + config ARM_GIC_KVM bool default y diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 11352806db2..70080bc161c 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -3,12 +3,14 @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files( 'arm_gic.c', 'arm_gic_common.c', 'arm_gicv2m.c', - 'arm_gicv3.c', 'arm_gicv3_common.c', - 'arm_gicv3_dist.c', 'arm_gicv3_its_common.c', - 'arm_gicv3_redist.c', +)) +softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files( + 'arm_gicv3.c', + 'arm_gicv3_dist.c', 'arm_gicv3_its.c', + 'arm_gicv3_redist.c', )) softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c')) softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c')) @@ -26,7 +28,7 @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c')) specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c')) specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c')) -specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c')) +specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpuif.c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c')) specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) From patchwork Wed Dec 15 10:40:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524260 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp238067imb; Wed, 15 Dec 2021 03:22:12 -0800 (PST) X-Google-Smtp-Source: ABdhPJyz/OVL5YBba3QVawlM6Cwias1AfdmNNCJclNvD8C7Q+1OsTtWakiX7JMopvAbA+I9M+3th X-Received: by 2002:a25:42cb:: with SMTP id p194mr5410296yba.134.1639567332769; Wed, 15 Dec 2021 03:22:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639567332; cv=none; d=google.com; s=arc-20160816; b=PvYqiUZugc6w1gJg40M1Nb3PGCvg31QI349XX7DTHKQvbnNrKQVbW2VpNIB8lkke4F CrGy6Y19ik2FPkVbpEuhGAQY1U14lForWo9dFj7sf6D4n0q3ofHSiR7zNwRhZv9drL7i rwnPkjLQRu1fCyTleEEF1vr1s5gz/wYw3NQQ2M74da90pXRRE1cw/Jcy3AqwHxVnxpSN Bp2ryAuPPJBh/nYWKk69/oROgp10uvoIgTc1yXebLI2TXH0Pfad7OoCdjnibclzXB+Oi jTC37UYkj5TJTq4OfPXImtAIRDKPEtOMdhYtoSEe0jmPj9f6oINsnUYdNlMrf+0CFYoA dtWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dUOHsQLorVT3Jc1OzDLRWuNIwMw2lM0/Ici6Robi+sY=; b=z1F50hJ79M5TIfcrArjeRLQoVIW9QUSv6dttMtuQls49W78Hv9uNkET6I4NHnUupwt jPNfFAROXYgczlQ2s7/pIyTtOP/y67Jd0iR3ihbQU/aBBo7VOqFVPr4iyn63NDvkxP1C 2OYdsSD/2RfPRiRlSMd6P/DIOvhY/MxSYLGxX2jUd31rLFOVCGN/yQGYa6SKhvJSL7Px DBe/LrHska80/C7sNHLo+UuJmyKT2i5j1sQFE/d0/OC/uTc1iWquowmxJDOtkMVnOBGM AYLHJs48K4iYIfhnaazlzt+SAGr92WIRN2WQfwigqsz2JhtDEKzMIM9HNgNvTmNohdRB AoIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XwUf2hd9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.40.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:40:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/33] target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn Date: Wed, 15 Dec 2021 10:40:25 +0000 Message-Id: <20211215104049.2030475-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::435 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index cec672f2296..9c4258ccac2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14750,6 +14750,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *s = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; + uint64_t pc = s->base.pc_next; uint32_t insn; if (s->ss_active && !s->pstate_ss) { @@ -14769,10 +14770,10 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) return; } - s->pc_curr = s->base.pc_next; - insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b); + s->pc_curr = pc; + insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b); s->insn = insn; - s->base.pc_next += 4; + s->base.pc_next = pc + 4; s->fp_access_checked = false; s->sve_access_checked = false; From patchwork Wed Dec 15 10:40:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524259 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp237685imb; Wed, 15 Dec 2021 03:21:39 -0800 (PST) X-Google-Smtp-Source: ABdhPJzdaFMcWNRVZR+kGANlyLG3gfazvA3BP0UcBXy2T9QDykHoBeoJuzDpp0qnm61FOlmo2Kq/ X-Received: by 2002:a25:aba3:: with SMTP id v32mr5140289ybi.358.1639567299256; Wed, 15 Dec 2021 03:21:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639567299; cv=none; d=google.com; s=arc-20160816; b=ojBXuZ1SVZDaEvcnYnkmrT77g/sUfJ2KJC3w7PRiHBlQ6DYaYQXOyv6W1k4ctxDGXH xzV8Ps0IpEfabADIbQw0W0WwVjWEj/iv7xa5IztzImzU9tNvp9xG6VrBdumu1GNlVq9Q SLJRDNjlK2i7pJfsoP7Sw19Zrt4IfnKlMU7xXFqCP8IU0PT6iAv/W6E8aJtU3t//bMoe I61Jsr9anwNpZjkLRJ2zkcU6fOzT1wHGZ3uem6AOW11jkMW1KhDgEu4MWS5JvTXpD15G obbQv4bPGlMj+B10d04ilhosxVydUrMxZxxn8glFHrlVmFSQL2rC7+YfJ4jEd1/A3gZv 48mw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WnLnjL7txGvuWh5pOnws/qxampi6HwwdnoH/cJfxyxo=; b=ZmIoz8DpHbrMjx/l3Ew4XeDODK+pAlFe1zmOtgNnXd4rD+iJ1Y0cJSeBIN/Rcdv7KT pC6Atc3b4BzT+TOfKMdUnwfGXGZlr+cDzrkciczgzeRv08fW5Ud9PQZlg59Nt2yy6F/o 72/abQ3b9UtQyt+u0VoIsZDgo8TMGPaGC2wmbWpFSebwx/4h6FyEiQ662QF2P10p7YHa 7VaoXvCB8FaInlj9oYzPBVPZ5HNvYq5+/+mrAWXDApCDtBKX/QRGhiy/AFRz701Wqd68 W0avJwINrD5a1yEZHrtNZQXkNeduogdbNtLgFIQtkSlKIQ4ood2nZsPQ9IRgBubPRnND cnmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kSkQDIV7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.40.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:40:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/33] target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn Date: Wed, 15 Dec 2021 10:40:26 +0000 Message-Id: <20211215104049.2030475-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::431 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 98f59259284..c721b2ce42c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9548,17 +9548,18 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; + uint32_t pc = dc->base.pc_next; unsigned int insn; if (arm_pre_translate_insn(dc)) { - dc->base.pc_next += 4; + dc->base.pc_next = pc + 4; return; } - dc->pc_curr = dc->base.pc_next; - insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); + dc->pc_curr = pc; + insn = arm_ldl_code(env, &dc->base, pc, dc->sctlr_b); dc->insn = insn; - dc->base.pc_next += 4; + dc->base.pc_next = pc + 4; disas_arm_insn(dc, insn); arm_post_translate_insn(dc); From patchwork Wed Dec 15 10:40:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524256 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp235364imb; Wed, 15 Dec 2021 03:18:33 -0800 (PST) X-Google-Smtp-Source: ABdhPJwHTsnX1uBUB2a6tr2sR/NazfQBxlTqZXyATn9GBekgYBnTjK8QgN3h3rzRkCiHjGyUQmc2 X-Received: by 2002:a05:6902:1105:: with SMTP id o5mr5792624ybu.519.1639567112980; Wed, 15 Dec 2021 03:18:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639567112; cv=none; d=google.com; s=arc-20160816; b=G6bpQ1GVtz/pH3ibjrvi32lFAXCxDUMo2iHBl0P4fHjFDJPZAWQVSlamUoiz927ZVH K42SxC0MEgz8y4zKIFT3XRlZcItxGCj8dwPGX2Yz6RehXQ212oR4sGECmgN3tSfRK/YS RoHJAnTXUGTgBu6P9IiN/ALXsdJND9t+U3q7yTpOQNaNfYjX5Ky93tLRQ/I9TcNJXySr kz21c6bjw5yik7H95CozFZV8Dzb6eSmQXFZaVWM0ZaLgop9ffeUF8nd6yr36fsF7l1yt /gB70NnBf7vn4wMzmhL0iBnvAlbj1fVOkiJGn7+JT6uHrq4slCoB8N+SnDDnZfrtTv2A 0b7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=G182pIHkjJrICKs+H0StOPfRJTHwqdMAHlojnGkBCfQ=; b=SPGomF+P9fMbxbf8An579mTeglA39mPZrsAcpJEbClDg1ML5qMrGqTRzCnUp88B+Mf O5NAmublRrlYVtjZbcqEoxXTXE8iBN6i7r6uboMeZlP+cfvVpmBzyj4ODU4RrE8HTDfP szezTQjb0PDM2KvjiD691pdPCtqpl97aQpjfj73YxEKu1bWh2y9Eues/yD9J2ucSRgGk Y/Oxk0+dAvucMNYW0qCNZ/CHPyzY/4nVZUR9jmjRSJojBL4w2mbTBJX4XJswj9LFsyi/ jQwtyN1xQLxHnJpvt152zFBpfYZRbWNP8/HxWaXdgUZEHbrGpFxBWlfwgo5eGpMEvFOB E95g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hCiaY+5q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.40.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:40:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/33] target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn Date: Wed, 15 Dec 2021 10:40:27 +0000 Message-Id: <20211215104049.2030475-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::436 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index c721b2ce42c..1c2a7274dfc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9618,25 +9618,25 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; + uint32_t pc = dc->base.pc_next; uint32_t insn; bool is_16bit; if (arm_pre_translate_insn(dc)) { - dc->base.pc_next += 2; + dc->base.pc_next = pc + 2; return; } - dc->pc_curr = dc->base.pc_next; - insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); + dc->pc_curr = pc; + insn = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b); is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn); - dc->base.pc_next += 2; + pc += 2; if (!is_16bit) { - uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next, - dc->sctlr_b); - + uint32_t insn2 = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b); insn = insn << 16 | insn2; - dc->base.pc_next += 2; + pc += 2; } + dc->base.pc_next = pc; dc->insn = insn; if (dc->pstate_il) { From patchwork Wed Dec 15 10:40:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524246 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp228089imb; Wed, 15 Dec 2021 03:09:11 -0800 (PST) X-Google-Smtp-Source: ABdhPJxz0wBW9E3P/t6D52VvUae40eBtUZ5XNrU3sNROlB+dCFGZo0d6wrcsMRG88A34X+grTIfp X-Received: by 2002:a05:6102:32d1:: with SMTP id o17mr2597048vss.19.1639566550943; Wed, 15 Dec 2021 03:09:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639566550; cv=none; d=google.com; s=arc-20160816; b=kKdo+wRjyzIFyi5cfa0ekNjKIRCA8W5g1KhLaVVZb8eCsusjIF1M+r1pwwCam0z97k iBCyhLZjj6jpHDR1ba/CyTtiTL8fgs91CSmKGatjU34JifSpaZtkW2nxglHOB3yJV92i VKzIQABffZlOBVhy6F3HsLyfEVd4mym5d5qr2gLf61MoZzzkf741jtFX09UnBmrh95vx MR1vnryJWf8376JVuz2Nk+khtZNjhm3zkRVmDgVwG0zaWLJ60ocFTAZ+v3dKSsKFzBmU xL69TRLu2UH6VV6Ew++d8RAoejcMCG1Apqu96kK96380NjWFj/hPjdU3L0sZ0Fs8uuNV 56Cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ORTqNRlgAL3aGjFO6YwXxyL4b2oYDvxssC50fjyS/k8=; b=uD+o+/FZoWUm2h4HzTZL/nU20THqCUjcqSAmMtxhYmtyQRRm+26kmO+z23dNjwX5QE nejW7rHIQo39+JFeXVHAmbAvBkOoaTMx9qyp1nvZuZE0pdvOPYRV0oyv1kvbqIqUyyLr GTQhNwLgcQTYvHeTF/6wYKSmpMbuxnwiNBHS8c+r+B/tFn3ymspxp5UYXRr9PNzerInO PR9NPwAsEA7SrYOABKteq2rT3AJb/oajdRn9TwlqOlCgpC5K5qibX5MvDAROdkS38p2A DuA/PHM7FkZjQr+F2BGDensY3PQoSDs9Q9751Jp5BuIIrs/IiJBSYgWFYc44T11R1AeV Iokg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Fj4ccnjq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.40.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:40:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/33] target/arm: Split arm_pre_translate_insn Date: Wed, 15 Dec 2021 10:40:28 +0000 Message-Id: <20211215104049.2030475-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::432 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Create arm_check_ss_active and arm_check_kernelpage. Reverse the order of the tests. While it doesn't matter in practice, because only user-only has a kernel page and user-only never sets ss_active, ss_active has priority over execution exceptions and it is best to keep them in the proper order. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 1c2a7274dfc..0103c75a274 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9502,7 +9502,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) dc->insn_start = tcg_last_op(); } -static bool arm_pre_translate_insn(DisasContext *dc) +static bool arm_check_kernelpage(DisasContext *dc) { #ifdef CONFIG_USER_ONLY /* Intercept jump to the magic kernel page. */ @@ -9514,7 +9514,11 @@ static bool arm_pre_translate_insn(DisasContext *dc) return true; } #endif + return false; +} +static bool arm_check_ss_active(DisasContext *dc) +{ if (dc->ss_active && !dc->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either @@ -9551,7 +9555,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint32_t pc = dc->base.pc_next; unsigned int insn; - if (arm_pre_translate_insn(dc)) { + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { dc->base.pc_next = pc + 4; return; } @@ -9622,7 +9626,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint32_t insn; bool is_16bit; - if (arm_pre_translate_insn(dc)) { + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { dc->base.pc_next = pc + 2; return; } From patchwork Wed Dec 15 10:40:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524254 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp234565imb; Wed, 15 Dec 2021 03:17:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJwFToW88gUH31WJN2R6M4pyc7zZvfaVsBMdHHPPVuG6lHjcSaqim46OKtILtSG5Bt1Km+Mf X-Received: by 2002:a25:bd12:: with SMTP id f18mr6008289ybk.282.1639567051006; Wed, 15 Dec 2021 03:17:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639567051; cv=none; d=google.com; s=arc-20160816; b=BPZDzx7tpXaqQ3LO0oWfNFrdSaY26d/qtst/q3trvN0IkgEDECPzJEnAJBCMIieqzt 74ggoAkAuhdTo+JeWDnP9P5LQ4KiIcjec2Fgm+HJlCvgP7mlR+blyO2zt7FnW7xmxlm2 BkEbDKSICbKInNZadSrltS9ZJWWd8vM1heVuDOFpuHAVRVl5FkWy4EcWQrRRU5k8Wen/ aJzalexQ4H+EMoASCGvmBcZwTxFFYKWhAo1kZANYqDHeZKaJ/d0x+RnPBIzSK20vIvxS a+8uxIKGPn3PXlKLiAq/Xdr4/Ldxbj6mDLunsSOxnc5q5TdqjZM/IrJmzf3s2EBDxIjw H14g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=N0uYtzp1T/duTn386YyO+lODMSKezKpWWtt0gTXr47k=; b=metk0S/XYsOBFsa7sGilakdul+oEEQJ9UiluMrU0PYAHQM65IJGIFPMoBG7A8sVGNO OSaszxifG/6KcANpupIU+FgVDrtocfQNv3jAQHgWTJmOMIYXQHFFjc9yfVHQEztuNs8C 6N7fYcmDPwnLP3Tu2eUCxgcBWNQO64rcHSe9QAHSEHkt4ElRFkJDRB9aqZJDMfTih1sR zHKGVjfopb8b1XxU6OGsTbTk4UX5VvWidpwpXSY3TADJfb+F0E8YD6i/Ca9atn7enUen FsrsOJKMxzIx9hfGBYAsSiDvUuTKu4Kq/hB1VccGjI7aH2ImmbKZFSE74AAUfoy6NZSy itQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jVeUpTG0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.40.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:40:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/33] target/arm: Advance pc for arch single-step exception Date: Wed, 15 Dec 2021 10:40:29 +0000 Message-Id: <20211215104049.2030475-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42d (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The size of the code covered by a TranslationBlock cannot be 0; this is checked via assert in tb_gen_code. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9c4258ccac2..2986fe13935 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14767,6 +14767,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) assert(s->base.num_insns == 1); gen_swstep_exception(s, 0, 0); s->base.is_jmp = DISAS_NORETURN; + s->base.pc_next = pc + 4; return; } From patchwork Wed Dec 15 10:40:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524249 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp231280imb; Wed, 15 Dec 2021 03:13:05 -0800 (PST) X-Google-Smtp-Source: ABdhPJyc2bNMF/r34PT0lUnFEM3EG9XLi4P8PhphOZEduL1ieJfChBVN7z0veZn4+S2JoXlXS2ul X-Received: by 2002:ab0:35d2:: with SMTP id x18mr9229643uat.32.1639566785840; Wed, 15 Dec 2021 03:13:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639566785; cv=none; d=google.com; s=arc-20160816; b=hMevc/0X9MaOn5AOfmVkFzypdZc0jYJsicvj+kFGey8ASDsVJ0zLDG+ZnCGIPjBVAg ebY66W4jHrB7woJTD0RTzfaII0y8g0agQPZsdstehATOHhLNRzuHs/QE0Msd47af2tzU ID+Rv0WsaN5W2p2orwd0Mzz+yktRZ/oT+J1t8NSyZlNFh47Rk4lMSXi3UVUmtpubYHDP L+7tgoWC/PEAyq7CrSOWW19saD5Nlsa3lr3L89IGgHIjHQ/ilD8x/sJfDL1MM06rh73D ef1OtDsD10vQRw59/hj2xeZvB5Q/mggDTmkINx905K1vcdRFuY8bh4QakYsbRaw60PsI C8Uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EbvaOheGHih9OZWQqKwYHdzxPCbAj4qvSl18sxhGpuI=; b=LmM2xXvgTabximKBdGrbhNZ/FIsD49Aa1Is9SrSmG9uaExzOEVbUIuy8WH56Ugq3zS siqc/iagPqEMHCHZfShYlBcjtcQWGbM2dCZNb15EBno9xP/xceOfqMhtsVPRYWIhIBIO Q4SJD2hR9pwpRUC4Y85J5BqxfyfI7uCEdZjg9E8ZN0Gjzsap+1hKrcn2bdN4YqKFA6Tz lRIqtJ8I1etnC2Jv0UgWrST/wYJJGUacBKPqW21OYDDw0jrWUFFqxkOu3LTfGhJmiNZG Cy6z82Q38awV2Hsxa/wDmx6bFVOYPpqT4EBCd593uhg8zFi7pEljmaSTCVQhio23Wfb8 h56A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Se1jAZIV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.40.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:40:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/33] target/arm: Split compute_fsr_fsc out of arm_deliver_fault Date: Wed, 15 Dec 2021 10:40:30 +0000 Message-Id: <20211215104049.2030475-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::435 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson We will reuse this section of arm_deliver_fault for raising pc alignment faults. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tlb_helper.c | 45 +++++++++++++++++++++++++---------------- 1 file changed, 28 insertions(+), 17 deletions(-) diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 12a934e9248..4cacb9658fb 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -49,25 +49,11 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, return syn; } -static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, ARMMMUFaultInfo *fi) +static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi, + int target_el, int mmu_idx, uint32_t *ret_fsc) { - CPUARMState *env = &cpu->env; - int target_el; - bool same_el; - uint32_t syn, exc, fsr, fsc; ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); - - target_el = exception_target_el(env); - if (fi->stage2) { - target_el = 2; - env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; - if (arm_is_secure_below_el3(env) && fi->s1ns) { - env->cp15.hpfar_el2 |= HPFAR_NS; - } - } - same_el = (arm_current_el(env) == target_el); + uint32_t fsr, fsc; if (target_el == 2 || arm_el_is_aa64(env, target_el) || arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { @@ -88,6 +74,31 @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, fsc = 0x3f; } + *ret_fsc = fsc; + return fsr; +} + +static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi) +{ + CPUARMState *env = &cpu->env; + int target_el; + bool same_el; + uint32_t syn, exc, fsr, fsc; + + target_el = exception_target_el(env); + if (fi->stage2) { + target_el = 2; + env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; + if (arm_is_secure_below_el3(env) && fi->s1ns) { + env->cp15.hpfar_el2 |= HPFAR_NS; + } + } + same_el = (arm_current_el(env) == target_el); + + fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); + if (access_type == MMU_INST_FETCH) { syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); exc = EXCP_PREFETCH_ABORT; From patchwork Wed Dec 15 10:40:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524266 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp243450imb; Wed, 15 Dec 2021 03:29:46 -0800 (PST) X-Google-Smtp-Source: ABdhPJxpKTW679pddFKxBSRQVF71Geovjei9rHKCgCq191GYZbzwdmboPsgeVbVmgG24tm5U3TVZ X-Received: by 2002:a05:6638:144a:: with SMTP id l10mr5533645jad.315.1639567786123; Wed, 15 Dec 2021 03:29:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639567786; cv=none; d=google.com; s=arc-20160816; b=vXvAUdoRZAY0BXl9Sk6u9IskJwmAbXpxe0qk2nvXob49rEMou6bYKotj37p3yvgKLo Q4sD55Kz5NzIgoW9TMNnxmdWVvXKY9H62husl8lP2ZH3HamJh+dmhEodl28Z06fU3TyH j7QROpo521dj9zLoIhgENNgGX63DPApsd/NILkQuiYd2U1wG/x/NF841Nvce7vHT77+X Wd7DV1chX8zUXXzkdWIWnd/jVY8fHtSvHLYDzhM7/nXd4xnTm6acYzQrh7K2qC/3LhKd L6ybVrtI2PloNk51yZTzjDv3ZHFhTkA/9KBlQ2LjcN3vjiPEvYde24Z/i/OyGrS80yj+ +dgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6kBw302WwHhJPN2hEgYUEFv5ycm8v30JC+SADrB5jpk=; b=Hk2V9Y1vh2V12O61pTT+W7f7/U7UH6Qy6C/VdC+knZR8XthRGKCUiXTbntMJkrTMfd WnqnUHTF+AGhIAe53BMM6oqgWIQXTZktHFoxiIYS6kQaDgG3RNYLl8v7z6Of1diF16Ea bRle+ubyUdtqNkDhTNiEoL+vYYNXKct5nDIkYjRvTqmeefu4ntkRu+XpX8ap4U7mplmm WyJG6rbT2cyPwgOrg73/froD+jCfvjPbfSe/C//uEyAmBAYB8FYpC1ggKEJwnZT44GxW ZKe2IBdW3e+kHt1YRlrjC7yvYNzG66uCkWJ8914W3M8h1p5A8LlAuj3D2WbaQaxSNFxB X3Mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ch8cE4mH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.40.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:40:59 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/33] target/arm: Take an exception if PC is misaligned Date: Wed, 15 Dec 2021 10:40:31 +0000 Message-Id: <20211215104049.2030475-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::433 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson For A64, any input to an indirect branch can cause this. For A32, many indirect branch paths force the branch to be aligned, but BXWritePC does not. This includes the BX instruction but also other interworking changes to PC. Prior to v8, this case is UNDEFINED. With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an exception or force align the PC. We choose to raise an exception because we have the infrastructure, it makes the generated code for gen_bx simpler, and it has the possibility of catching more guest bugs. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.h | 1 + target/arm/syndrome.h | 5 ++++ linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++++++--------------- target/arm/tlb_helper.c | 18 ++++++++++++++ target/arm/translate-a64.c | 15 ++++++++++++ target/arm/translate.c | 22 ++++++++++++++++- 6 files changed, 87 insertions(+), 20 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 448a86edfdc..b463d9343bc 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -47,6 +47,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, DEF_HELPER_2(exception_internal, void, env, i32) DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) DEF_HELPER_2(exception_bkpt_insn, void, env, i32) +DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_1(wfe, void, env) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index f30f4130a27..8cde8e7243a 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -282,4 +282,9 @@ static inline uint32_t syn_illegalstate(void) return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; } +static inline uint32_t syn_pcalignment(void) +{ + return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + #endif /* TARGET_ARM_SYNDROME_H */ diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 97e0728b679..f9f3473288f 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -113,27 +113,35 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */ ec = syn_get_ec(env->exception.syndrome); - assert(ec == EC_DATAABORT || ec == EC_INSNABORT); - - /* Both EC have the same format for FSC, or close enough. */ - fsc = extract32(env->exception.syndrome, 0, 6); - switch (fsc) { - case 0x04 ... 0x07: /* Translation fault, level {0-3} */ - si_signo = TARGET_SIGSEGV; - si_code = TARGET_SEGV_MAPERR; + switch (ec) { + case EC_DATAABORT: + case EC_INSNABORT: + /* Both EC have the same format for FSC, or close enough. */ + fsc = extract32(env->exception.syndrome, 0, 6); + switch (fsc) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_ACCERR; + break; + case 0x11: /* Synchronous Tag Check Fault */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MTESERR; + break; + case 0x21: /* Alignment fault */ + si_signo = TARGET_SIGBUS; + si_code = TARGET_BUS_ADRALN; + break; + default: + g_assert_not_reached(); + } break; - case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ - case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ - si_signo = TARGET_SIGSEGV; - si_code = TARGET_SEGV_ACCERR; - break; - case 0x11: /* Synchronous Tag Check Fault */ - si_signo = TARGET_SIGSEGV; - si_code = TARGET_SEGV_MTESERR; - break; - case 0x21: /* Alignment fault */ + case EC_PCALIGNMENT: si_signo = TARGET_SIGBUS; si_code = TARGET_BUS_ADRALN; break; diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 4cacb9658fb..b79004e0cca 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -9,6 +9,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/helper-proto.h" static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, @@ -134,6 +135,23 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } +void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) +{ + ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; + int target_el = exception_target_el(env); + int mmu_idx = cpu_mmu_index(env, true); + uint32_t fsc; + + env->exception.vaddress = pc; + + /* + * Note that the fsc is not applicable to this exception, + * since any syndrome is pcalignment not insn_abort. + */ + env->exception.fsr = compute_fsr_fsc(env, &fi, target_el, mmu_idx, &fsc); + raise_exception(env, EXCP_PREFETCH_ABORT, syn_pcalignment(), target_el); +} + #if !defined(CONFIG_USER_ONLY) /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2986fe13935..130a9ff8d54 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14753,6 +14753,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint64_t pc = s->base.pc_next; uint32_t insn; + /* Singlestep exceptions have the highest priority. */ if (s->ss_active && !s->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either @@ -14771,6 +14772,20 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) return; } + if (pc & 3) { + /* + * PC alignment fault. This has priority over the instruction abort + * that we would receive from a translation fault via arm_ldl_code. + * This should only be possible after an indirect branch, at the + * start of the TB. + */ + assert(s->base.num_insns == 1); + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); + s->base.is_jmp = DISAS_NORETURN; + s->base.pc_next = QEMU_ALIGN_UP(pc, 4); + return; + } + s->pc_curr = pc; insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b); s->insn = insn; diff --git a/target/arm/translate.c b/target/arm/translate.c index 0103c75a274..45917c3a6d2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9555,7 +9555,27 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint32_t pc = dc->base.pc_next; unsigned int insn; - if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { + /* Singlestep exceptions have the highest priority. */ + if (arm_check_ss_active(dc)) { + dc->base.pc_next = pc + 4; + return; + } + + if (pc & 3) { + /* + * PC alignment fault. This has priority over the instruction abort + * that we would receive from a translation fault via arm_ldl_code + * (or the execution of the kernelpage entrypoint). This should only + * be possible after an indirect branch, at the start of the TB. + */ + assert(dc->base.num_insns == 1); + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); + dc->base.is_jmp = DISAS_NORETURN; + dc->base.pc_next = QEMU_ALIGN_UP(pc, 4); + return; + } + + if (arm_check_kernelpage(dc)) { dc->base.pc_next = pc + 4; return; } From patchwork Wed Dec 15 10:40:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524263 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp240030imb; Wed, 15 Dec 2021 03:25:01 -0800 (PST) X-Google-Smtp-Source: ABdhPJwXfclcZI+L4ZKPozIziyKyxztBqZP7ocUAD8Qo+ceTD446otBamSrWjAz9MQKZAKbrgASJ X-Received: by 2002:a25:2d1:: with SMTP id 200mr5367056ybc.528.1639567501589; Wed, 15 Dec 2021 03:25:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639567501; cv=none; d=google.com; s=arc-20160816; b=jM/Ge+ZwrHB3/lC+UA9iv5WKJdTb2laZSPMR++Bxi8he6ZuahxeFe/uVHFV/BtuRiP 7TTvypYEy58ZQ6TOXO/ulNstTqUwup/BhfAyU8g5O1oIJAgW6HgrOZo+Qj+bwIkseT5p Y8kJXMFw9sc3aXufjkkoD5m+gfd47v4Wzpppv/EUfFCSmpfk5wGBbrD2XfElDYUXIQfO ZfXRzp29E5lwTfbmq6WD6stpFb0v5yVV9gcwbsR+jSJUWO0lSpuvMJX08C1DqQfB093t THkv+/+lGqGynckW67SUPex2gVVhBvJHQL34A78M5pu8Jdk+JZT6ohE0EXnlbE5Grlp/ RQqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dWLzLfQlZup7XMFO5JjnyV3vJtIaJi3BRfsuFCKl1fw=; b=lESjtyase2g7dV/wPGNymTNxc3IkzxW8FL0lCN9EQxyRJ4LETU6gfDk+7k3ENv56fr wFsZ4oCTtAxQVXcnT1S1WE/BX1jM4ksBd3erEOW4KieMc7kKE7ZovB2vb+LzbQP/7Qal PSkRwU2zw9kqffhdeBvkXkSqzunbenMI5wbrnh0tQCPhsW2V4oD5xD77qr7ewlQfo8OP iadasvLWiukRg+7f+IFxgN7oAHSk4RRO33YotJukJSzWssf0kFvgxa5e9nP0VuCT+AvT rBAXGrLfJhExrc6ha06v/g5tXiQRcMdGSsx+aMsGf4l/0m1u/KxETO0VeUEtabqSl3l0 /1tQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tjcHFBy+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.40.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:40:59 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/33] target/arm: Assert thumb pc is aligned Date: Wed, 15 Dec 2021 10:40:32 +0000 Message-Id: <20211215104049.2030475-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42a (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Misaligned thumb PC is architecturally impossible. Assert is better than proceeding, in case we've missed something somewhere. Expand a comment about aligning the pc in gdbstub. Fail an incoming migrate if a thumb pc is misaligned. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/gdbstub.c | 9 +++++++-- target/arm/machine.c | 10 ++++++++++ target/arm/translate.c | 3 +++ 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 134da0d0ae3..ca1de475116 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -77,8 +77,13 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) tmp = ldl_p(mem_buf); - /* Mask out low bit of PC to workaround gdb bugs. This will probably - cause problems if we ever implement the Jazelle DBX extensions. */ + /* + * Mask out low bits of PC to workaround gdb bugs. + * This avoids an assert in thumb_tr_translate_insn, because it is + * architecturally impossible to misalign the pc. + * This will probably cause problems if we ever implement the + * Jazelle DBX extensions. + */ if (n == 15) { tmp &= ~1; } diff --git a/target/arm/machine.c b/target/arm/machine.c index c74d8c3f4b3..135d2420b5c 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -794,6 +794,16 @@ static int cpu_post_load(void *opaque, int version_id) return -1; } } + + /* + * Misaligned thumb pc is architecturally impossible. + * We have an assert in thumb_tr_translate_insn to verify this. + * Fail an incoming migrate to avoid this assert. + */ + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { + return -1; + } + if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } diff --git a/target/arm/translate.c b/target/arm/translate.c index 45917c3a6d2..0a3840d227f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9646,6 +9646,9 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint32_t insn; bool is_16bit; + /* Misaligned thumb PC is architecturally impossible. */ + assert((dc->base.pc_next & 1) == 0); + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { dc->base.pc_next = pc + 2; return; From patchwork Wed Dec 15 10:40:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524270 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp246624imb; Wed, 15 Dec 2021 03:33:53 -0800 (PST) X-Google-Smtp-Source: ABdhPJxi+zPUhptUIqnOw4MDID7wSEW9fk0i2jbIe9dsGb1hBBJCEPl3N81gMdM26jHi9OasrT4r X-Received: by 2002:a25:8609:: with SMTP id y9mr5438564ybk.50.1639568033342; Wed, 15 Dec 2021 03:33:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639568033; cv=none; d=google.com; s=arc-20160816; b=HR776WzSV6R1rcNfBUXiUhViTGeEIZ7DU24Z4ro++0uNGQuuUdJYrR/QmPNWOvYEw2 PKCCivuYp9U4q6DbEoxf3MaprcFN4EwxfBc55+QU3Fl/AeM6Zvp7PA+SoZCOb/wTujzx mmvG0IbOw7ImIQJzf5blEZ3HQbvs3gpiwHa7FDS2j+TkYHCjEmA9gxwp5PHI8XyCR6Fy 1nzc4yap1S08v5AqgbjCalTk8phht3bWbUcPp29n/gjAemiiDXXMTldak8a1cktys53t 5ck57mObxg0TvxziwqQJeiB6TOSXG86ohEx1Qt7qkvC1NolApQLtDzhOnnLhMNvcbEOC AmUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tLNa3rIPfRwl8m/eEZTAjhUMYzfnAvACuXtMQvvgIj0=; b=Zv6JLbP/vTuMyaDURM2nC6/0I0RiCNlv1nurRF7pr8Smg/22eQTipNhZF2E3+kOxqM eGDlJNcS+kiAE680hRsDegNzzYuBhh6bt4qnLCqCKP451i6WvG9glZMts1Di08LNSDK4 8U92IAIUIWP+qBkcwMNjpqVSgpFItpWuexHMWk7pNVi2oUYzRcac/6Uxbyw4I3fjWfHL PvoyIH4edVSYM6ld/srd+w3QPqO6XWKP160A4tXzsDlpJUo/oMKpplHK/x4GQE7w5XxI kzc1vAXHDG6UBF6cnefWdfIM2F12mBFqoOtlQDRQ9ZuVuEYsa9dNbJwo6T/TJZZ9Sajl xkmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ey2eAYmO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.41.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:41:00 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/33] target/arm: Suppress bp for exceptions with more priority Date: Wed, 15 Dec 2021 10:40:33 +0000 Message-Id: <20211215104049.2030475-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::435 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Both single-step and pc alignment faults have priority over breakpoint exceptions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/debug_helper.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 2983e36dd33..32f3caec238 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -220,6 +220,7 @@ bool arm_debug_check_breakpoint(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; + target_ulong pc; int n; /* @@ -231,6 +232,28 @@ bool arm_debug_check_breakpoint(CPUState *cs) return false; } + /* + * Single-step exceptions have priority over breakpoint exceptions. + * If single-step state is active-pending, suppress the bp. + */ + if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) { + return false; + } + + /* + * PC alignment faults have priority over breakpoint exceptions. + */ + pc = is_a64(env) ? env->pc : env->regs[15]; + if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) { + return false; + } + + /* + * Instruction aborts have priority over breakpoint exceptions. + * TODO: We would need to look up the page for PC and verify that + * it is present and executable. + */ + for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { if (bp_wp_matches(cpu, n, false)) { return true; From patchwork Wed Dec 15 10:40:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524273 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp248711imb; Wed, 15 Dec 2021 03:36:57 -0800 (PST) X-Google-Smtp-Source: ABdhPJzsuxCbdW7WoqbNPSafOmQocz367yxnkSgXSX63OATDPf7JZLScZD+GneC8sgIg51mM4CXs X-Received: by 2002:a25:cd47:: with SMTP id d68mr5619280ybf.537.1639568217365; Wed, 15 Dec 2021 03:36:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639568217; cv=none; d=google.com; s=arc-20160816; b=RLpNveh0Wkkcko0kq/YbJ4JeZmzeIuq7p/cOM9NKbf3C6rqcj85NrgyUYfkdQGSb0A wSjGnum8Crf/8+4qRivaLu0KW1P+nU3KyjxS2I6zji3LtFX8+VF95IXlQ5xv5Srayo4Y zPtCImPI4dR5BIZsyBSbQqswlyOrZT96Oho1zZjEsPzQDiHytZ2amMOocRpXSytm6s/M 0HyXBzpLsnSjuH6EX4k94zdgm7/OnXXfmUMJcyiSmvlOCUKqwpYYPmuMa9wiodV4d9Rq l0xJJTC0smNIC8NyEcX5sNkq++wTDFT3ORch3cDNLIDvjuEy6HtQlRgavRj0udZRYXh/ mKdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zsiqwW/bbQhFQjNkeayyIckoQIXuNagLEjNtbn8AkMM=; b=mhRciy4tVSSKASm0IfYc8LfMfTHBbovtpZjinYfAV9zv9KYHxNxag1+rrk54PsUJSE T0HW230mw27Bjeky1bAznBR/cXECEeFKFzLUj745EPDOPmQM6UkxbvljZouVK7LfAdzt e52ZTbZo1rvcM9DTSlhTho6vXHzwQI3QJ95AcSYbf7mNX414uXgCZOgHJLhuejECswd3 LIQ6K8DEVMklu/emloIXseVOZHCPrJk0zGCPkJOWsh4DP8e2w/SqpAeflOAjCFMRjtTq wU0ec8r9P3hwLBCYf5F9TKWotvicyNDwU0Et7aHkx2GX/9b9xvJ6CHtgkZdMlC15aSV7 E/eQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VCWs+ANi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.41.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:41:00 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/33] tests/tcg: Add arm and aarch64 pc alignment tests Date: Wed, 15 Dec 2021 10:40:34 +0000 Message-Id: <20211215104049.2030475-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::433 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell --- tests/tcg/aarch64/pcalign-a64.c | 37 +++++++++++++++++++++++++ tests/tcg/arm/pcalign-a32.c | 46 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 4 +-- tests/tcg/arm/Makefile.target | 4 +++ 4 files changed, 89 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/aarch64/pcalign-a64.c create mode 100644 tests/tcg/arm/pcalign-a32.c diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a64.c new file mode 100644 index 00000000000..6b9277f919f --- /dev/null +++ b/tests/tcg/aarch64/pcalign-a64.c @@ -0,0 +1,37 @@ +/* Test PC misalignment exception */ + +#include +#include +#include +#include + +static void *expected; + +static void sigbus(int sig, siginfo_t *info, void *vuc) +{ + assert(info->si_code == BUS_ADRALN); + assert(info->si_addr == expected); + exit(EXIT_SUCCESS); +} + +int main() +{ + void *tmp; + + struct sigaction sa = { + .sa_sigaction = sigbus, + .sa_flags = SA_SIGINFO + }; + + if (sigaction(SIGBUS, &sa, NULL) < 0) { + perror("sigaction"); + return EXIT_FAILURE; + } + + asm volatile("adr %0, 1f + 1\n\t" + "str %0, %1\n\t" + "br %0\n" + "1:" + : "=&r"(tmp), "=m"(expected)); + abort(); +} diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c new file mode 100644 index 00000000000..3c9c8cc97b1 --- /dev/null +++ b/tests/tcg/arm/pcalign-a32.c @@ -0,0 +1,46 @@ +/* Test PC misalignment exception */ + +#ifdef __thumb__ +#error "This test must be compiled for ARM" +#endif + +#include +#include +#include +#include + +static void *expected; + +static void sigbus(int sig, siginfo_t *info, void *vuc) +{ + assert(info->si_code == BUS_ADRALN); + assert(info->si_addr == expected); + exit(EXIT_SUCCESS); +} + +int main() +{ + void *tmp; + + struct sigaction sa = { + .sa_sigaction = sigbus, + .sa_flags = SA_SIGINFO + }; + + if (sigaction(SIGBUS, &sa, NULL) < 0) { + perror("sigaction"); + return EXIT_FAILURE; + } + + asm volatile("adr %0, 1f + 2\n\t" + "str %0, %1\n\t" + "bx %0\n" + "1:" + : "=&r"(tmp), "=m"(expected)); + + /* + * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns + * the address or not. If so, we can legitimately fall through. + */ + return EXIT_SUCCESS; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 2c05c90d170..1d967901bd2 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -8,8 +8,8 @@ VPATH += $(ARM_SRC) AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64 VPATH += $(AARCH64_SRC) -# Float-convert Tests -AARCH64_TESTS=fcvt +# Base architecture tests +AARCH64_TESTS=fcvt pcalign-a64 fcvt: LDFLAGS+=-lm diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target index 5ab59ed6ce1..f509d823d4f 100644 --- a/tests/tcg/arm/Makefile.target +++ b/tests/tcg/arm/Makefile.target @@ -29,6 +29,10 @@ run-fcvt: fcvt $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) +# PC alignment test +ARM_TESTS += pcalign-a32 +pcalign-a32: CFLAGS+=-marm + ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y) # Semihosting smoke test for linux-user From patchwork Wed Dec 15 10:40:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524253 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp233827imb; Wed, 15 Dec 2021 03:16:35 -0800 (PST) X-Google-Smtp-Source: ABdhPJwuIFo5XaL6QncqitVQgJEMCSLMJjh0qQAQyvMtiSDfiThwLnx2qUhWitG7Ggqaoa6NXiV2 X-Received: by 2002:a25:848d:: with SMTP id v13mr6148542ybk.178.1639566994902; Wed, 15 Dec 2021 03:16:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639566994; cv=none; d=google.com; s=arc-20160816; b=U+4ps5WV23Cbv3Erud0PliUj/V7nxmyF8pReJ0+AmQ1xhvbaomNSz2MX9dfCuv9408 bbbM6BcPbaEENjCrxL9VYHVvurFefG/7E4jVYISm5EI9dnqBp8Q+G0xuvPe7h8tDB3t/ Etza9dx4njc2XtJdoYWOx4zbk5AUje07BhmsYfsFW3UhtTbeDU1/OCOvX9vpO7HBr+SP 4MvnWU8QXjpz1nEmUbWBLmYM5RYUUICEc3bzfpwpilmMf7HfJCpb1Gjp3A3plQ4JPUrH A3fM9IfMutXFg9vWpEh1soGNCzNCkT9UtzkpTUYc03cHiQuTJlaHi6NsZy/xDBo9H8Bf 5nxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1LIBTaRPYIs3MFe5ZnN0Uy0Pc8j1ZIq2IU2jO2WESb4=; b=ec2qyuB7EI9MffwVnr7iurTWsh3tWH+huEBN8mMloVGJmyCUEjoW2MJZUOdh68GO7o UzmuN3Gm1BzYV1u5JIlN4R7eteXUybU8UbDqaaqlUuHFk2SM2/hZn/Z9NePlKHxp3iRx IsiIGLnTDLHzrBoSyyAPZRXq2xFLiXvN2gkLf0vs3QRMwY5iicdh5R+lBYaDYr1vPcAi MGKY+NpTASK9H3cH4QzkHblYutGH+xsWIDn+Xn9u3cdz7l3DN+DI8NGjQWvEFF90mDfs 95FsR1e52+Szr1vbpkztmjH9M4nBqnhCBjdBc3HT/JBdiOoAQg0wS5iMImWPMg8r+ZS4 VPHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I2bu0+Kx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.41.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:41:01 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/33] target/i386: Use assert() to sanity-check b1 in SSE decode Date: Wed, 15 Dec 2021 10:40:35 +0000 Message-Id: <20211215104049.2030475-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::432 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In the SSE decode function gen_sse(), we combine a byte 'b' and a value 'b1' which can be [0..3], and switch on them: b |= (b1 << 8); switch (b) { ... default: unknown_op: gen_unknown_opcode(env, s); return; } In three cases inside this switch, we were then also checking for "if (b1 >= 2) { goto unknown_op; }". However, this can never happen, because the 'case' values in each place are 0x0nn or 0x1nn and the switch will have directed the b1 == (2, 3) cases to the default already. This check was added in commit c045af25a52e9 in 2010; the added code was unnecessary then as well, and was apparently intended only to ensure that we never accidentally ended up indexing off the end of an sse_op_table with only 2 entries as a result of future bugs in the decode logic. Change the checks to assert() instead, and make sure they're always immediately before the array access they are protecting. Fixes: Coverity CID 1460207 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/i386/tcg/translate.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index e9e14515409..05f9336c9b9 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -3519,9 +3519,6 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x171: /* shift xmm, im */ case 0x172: case 0x173: - if (b1 >= 2) { - goto unknown_op; - } val = x86_ldub_code(env, s); if (is_xmm) { tcg_gen_movi_tl(s->T0, val); @@ -3540,6 +3537,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, offsetof(CPUX86State, mmx_t0.MMX_L(1))); op1_offset = offsetof(CPUX86State,mmx_t0); } + assert(b1 < 2); sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1]; if (!sse_fn_epp) { @@ -3770,10 +3768,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, rm = modrm & 7; reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; - if (b1 >= 2) { - goto unknown_op; - } + assert(b1 < 2); sse_fn_epp = sse_op_table6[b].op[b1]; if (!sse_fn_epp) { goto unknown_op; @@ -4200,10 +4196,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, rm = modrm & 7; reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; - if (b1 >= 2) { - goto unknown_op; - } + assert(b1 < 2); sse_fn_eppi = sse_op_table7[b].op[b1]; if (!sse_fn_eppi) { goto unknown_op; From patchwork Wed Dec 15 10:40:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524258 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp236084imb; Wed, 15 Dec 2021 03:19:35 -0800 (PST) X-Google-Smtp-Source: ABdhPJwuyz1oCgXL2eqJOz1V+Bgh/l7mtV3x+fO3Ol3v+YOW1lCQK4ZbEIl+jpyZn8svNaxdQMcw X-Received: by 2002:a25:c552:: with SMTP id v79mr5397880ybe.709.1639567175414; Wed, 15 Dec 2021 03:19:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639567175; cv=none; d=google.com; s=arc-20160816; b=dTMvX9AX0jfNx/Hhte/wLvKUV7N0p9DTrznaDs8aPwVt4ctUne6UIyyw0H4nefazag FuovcvN7gvdnEoPGh5J4eRLjJSZkgQtX6+gig+kD8hIRAh7J/YWovgvv8dV38wVdnU7V buUwIcEKopS6d3LtI3V6HJ78RSeAe4IwNCaBoZDCQjUKkvYGztLG959ETfHbkAZGzLvw qBALyqQ2ZoxM/iM/0ZcGcHpdYDhgxiOdi+gGyfn2cs6b0en3Q7qFHFlJCnU/DMnFLYam 83/Tw5ykJ0HMGzhUXoYgdFuJrb4J3RVln4IkCckpAbs0I47qSfskqSUbN1e7Ruhe6tF4 ERNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hhMYipSwn2eG/b+4IrljLjNjCQxUpkJwZAkhclx3/mk=; b=pSHfl8oHT8L4V3jBrkwzH+slY/cCDlQPYgFqMUSuevZ0BeCKU9kf38L7j3CpnqP7hE Xeo9Mc1xIvdgC6KxvOKmEYgPLs7wbtzK0TNL2RWozLBpRjlJgopMK5NZDzqGCnizTXGz eYWsHEDRuDw0pKXCfPEhzUfc3RWcrRq+ullKAJ0dDJUqvqOpvnQOLs+Gg1vVNea4tUJn DQN4maSJ8UMQipCweHxzSgLKOj7ZBJAD+j35zbWUhNfmPg9KTTxAK1UNpPDKkKLoD2qE FkOlMKuX0Djx1pJ/jx05zfoSemtIRagRATptu0lesUqN42H7p6/Csgrsy3LIsSQDgWke 6ztA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=z6EGwv64; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.41.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:41:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/33] include/hw/i386: Don't include qemu-common.h in .h files Date: Wed, 15 Dec 2021 10:40:36 +0000 Message-Id: <20211215104049.2030475-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::429 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The qemu-common.h header is not supposed to be included from any other header files, only from .c files (as documented in a comment at the start of it). include/hw/i386/x86.h and include/hw/i386/microvm.h break this rule. In fact, the include is not required at all, so we can just drop it from both files. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20211129200510.1233037-2-peter.maydell@linaro.org --- include/hw/i386/microvm.h | 1 - include/hw/i386/x86.h | 1 - 2 files changed, 2 deletions(-) diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h index 4d9c732d4b2..efcbd926fd4 100644 --- a/include/hw/i386/microvm.h +++ b/include/hw/i386/microvm.h @@ -18,7 +18,6 @@ #ifndef HW_I386_MICROVM_H #define HW_I386_MICROVM_H -#include "qemu-common.h" #include "exec/hwaddr.h" #include "qemu/notify.h" diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index bb1cfb88966..a145a303703 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -17,7 +17,6 @@ #ifndef HW_I386_X86_H #define HW_I386_X86_H -#include "qemu-common.h" #include "exec/hwaddr.h" #include "qemu/notify.h" From patchwork Wed Dec 15 10:40:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524264 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp241040imb; Wed, 15 Dec 2021 03:26:34 -0800 (PST) X-Google-Smtp-Source: ABdhPJwSbmTdIzmFmcZJQE0MIe+XymekYM6CVk6RV2YE5i+V1nGXWrwIXkGw3IJG2XWH1xyURAXr X-Received: by 2002:a25:c343:: with SMTP id t64mr5160321ybf.290.1639567594228; Wed, 15 Dec 2021 03:26:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639567594; cv=none; d=google.com; s=arc-20160816; b=RmwxsE+9oNxV2rhouTE9ihyRQBHDqjTMK4kC5ycVwE7mpxmAnZdBdU4/NVbxcFU/3A /4RxTpmWw+jnLNSOvaveXzoVTfz3aCldrPH3oQ4G1qK4ktzZNQkB3yn7r6MBE3I4gmnj GxwModFHkm427t4EWS907z3Yzg/BB2UE1DRn29MwXqvEdfZB4IypPRMvttgtwu7zTqC9 EBM6Z0t6DCa74mcSQfGCYq4NnrZvC70ACys4+QCCzRcu2EMGW/SrUcd3c8yOTxv6vALw cpSi++AolrJWv0EjZgVyQzGOnOpUQxT66hOF3HV2u15RY17oL77ZMxzcsfDTgi7XlYgd ByGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=V9ad1ft9XN2bt0JubTin4DNNl6fvaB1gNU6QqLOH+X4=; b=h9sV6aM53sj+VVzO2FTyQwnInfM1l+mbn8zqpk5SItCL0dqYidpU84l9Bil5xW4ugX WmW7thRGprCLPj7WJDnugST5Q9bzWk++fuMy6uxPPxF7Rtt115sDtmczTAt31Dyri3PX CYzvvFyf6IFWvWZd6/WpIA7YTqV+1hlI2WXK24qFcFakdu3Oxe3XRPq1VAcKKb3LMrV/ Zeb5V9Aw20h5hUGVzWrTldNqvot+zLbjfpdOhim9gFd9rzENl+RWgxF5Cm2P4PAmAlb0 Z6TTSmrXkjE8drvCG+D/YgRBlXiQqPMpW3TDEVJxWGLGE2/xfIjb15kL6UijkuQzSJS7 4rYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xtIBO+Jq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.41.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:41:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/33] target/hexagon/cpu.h: don't include qemu-common.h Date: Wed, 15 Dec 2021 10:40:37 +0000 Message-Id: <20211215104049.2030475-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The qemu-common.h header is not supposed to be included from any other header files, only from .c files (as documented in a comment at the start of it). Move the include to linux-user/hexagon/cpu_loop.c, which needs it for the declaration of cpu_exec_step_atomic(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Taylor Simpson Message-id: 20211129200510.1233037-3-peter.maydell@linaro.org --- target/hexagon/cpu.h | 1 - linux-user/hexagon/cpu_loop.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index de121d950f2..58a0d3870bb 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -23,7 +23,6 @@ typedef struct CPUHexagonState CPUHexagonState; #include "fpu/softfloat-types.h" -#include "qemu-common.h" #include "exec/cpu-defs.h" #include "hex_regs.h" #include "mmvec/mmvec.h" diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index 6b24cbaba93..e47f8348d56 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -19,6 +19,7 @@ */ #include "qemu/osdep.h" +#include "qemu-common.h" #include "qemu.h" #include "user-internals.h" #include "cpu_loop-common.h" From patchwork Wed Dec 15 10:40:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524262 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp238731imb; Wed, 15 Dec 2021 03:23:01 -0800 (PST) X-Google-Smtp-Source: ABdhPJz/HESBVpVUBjeaRhEsbhplixnlbzy23os9Mm42g2OC92G/EFz/lU30Lg3GYG7gmJsbvoJo X-Received: by 2002:a25:7613:: with SMTP id r19mr5409863ybc.498.1639567381400; Wed, 15 Dec 2021 03:23:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639567381; cv=none; d=google.com; s=arc-20160816; b=jN+IOMdrCgWReRPk8v2P1o07GugQpbo3pxyZ4Dw2J7zKhnjfIqjRKNueoZCGEBvLFZ XVJhNb3QJaCW7UcZ3UDJr5tkL1Yvl51L/9aAqvoSdcaHsqNUAxzMQcgVnvJERYDzeNsz ahJjwzSv1Ed6z2onJLVxnj5UEHzo2TZSIVC7LIoI89cFJVrX4eQzSwLFQCpKoM/DMOAW GrS6LFwtjme1qqodDl2QSmTy7Zcl708OnkCnufNe91iF+vGJqQRO7gewBhAyZ7Gth+vv mJkf4CYCMeJcQK39TRyQviBTEkkUKpXUK4XY9JvFtBPre8qrUjfB77O8q0L9c6RJHBSC hWfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=itrbLItJypKD95cQZggGEzOjT12l1+m/EwZ7pOTkiIQ=; b=N28t708sxK8NWwYVuUx1eg7ibyxbjo7tBXdckKnWlnZNT/V7TamK1rLl3/SrFZfr+S vo65F9+oS+gfbe8ykoWK2ZXK2NvvvSfysFLVR9s2R0uVO0Kr7iIR84p6Q5ttX2QTGQit 3HlTXfsTk43IYyyEVqywrjksUDZHBy1CsQZPCne40x/HKa04k8kzHWFx+YmscUMQNlfw /g0QQ5FyYxFvMIHdlh54iJwb46SMNNfEoGqnXTHCXEla9VLdzloMrkfft1xaeb9J+Kl7 pgdmdwIQ17NWjg4NoXsez5VJqQPEpZkB4wwyVpi6cL0WdwnZmlh5mH/aF8pD/RHTqviI POMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rol+mb1R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.41.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:41:03 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/33] target/rx/cpu.h: Don't include qemu-common.h Date: Wed, 15 Dec 2021 10:40:38 +0000 Message-Id: <20211215104049.2030475-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42f (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The qemu-common.h header is not supposed to be included from any other header files, only from .c files (as documented in a comment at the start of it). Nothing actually relies on target/rx/cpu.h including it, so we can just drop the include. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Taylor Simpson Reviewed-by: Yoshinori Sato Message-id: 20211129200510.1233037-4-peter.maydell@linaro.org --- target/rx/cpu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 4ac71aec370..657db84ef0a 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -20,7 +20,6 @@ #define RX_CPU_H #include "qemu/bitops.h" -#include "qemu-common.h" #include "hw/registerfields.h" #include "cpu-qom.h" From patchwork Wed Dec 15 10:40:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524257 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp235423imb; Wed, 15 Dec 2021 03:18:39 -0800 (PST) X-Google-Smtp-Source: ABdhPJwsRYCn8WPJpa9q22UXQT9SEjAgc2PKURi1zjZYK6Vc9ByC5r8xLTf3Bpk6NfdDpnaBsRS0 X-Received: by 2002:a25:2d3:: with SMTP id 202mr5270914ybc.111.1639567119109; Wed, 15 Dec 2021 03:18:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639567119; cv=none; d=google.com; s=arc-20160816; b=uLCqu8bKuaNQVwNxHlLvacMLZ4E3k7xK+fJazOR4sRasTUHLhzPkwTUOKxt+ynjo+9 JEgExgsrsVz3IRAZJU1slw2yxGgtTwFAglp+YEg3rF6/6NaMXVjpq0HIUvfQggSnqoZ3 DoIFD04uovBxd2PqRz+v+vRjFh9mPU6E+H88xcvzPGRom0kFVDYUkvquc/QIhbS0KV2q 6E92fzXLa587aOyisnsnGGme/C2tfJUvThlpVuhQhamHIuX6b3HB8cBosiIj9MzLxDb+ SnEK+vmFoHekjGeeNhizlPJlIf/0KPt9IB5T2hsT9u5BPsGNQ8L7akigT9h8kdraXl/0 wqYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qng/i8R7/XsaL+VWydrhabs7NyFdgykqoNa9afu5vIU=; b=f9UMT12lsYE/XMUFv3OUalkvvQZctzewAIFGhBFsoJWVJ5QfECIGshwJ941K1A36vl LdHjS64B7O0iaAMNTG/18wUzjAhMKt3V0pMHYWv4UlIvGfqydYiPnuxY+X4T9QSmbFMr 4HrGu0aaK9lCTzTRfQ2TK31lJshx88ThgoZHlXnmPt4uC0LcKfkzOINMzpzm+fXdFeAS QpvUuHtDkVRBhUA0ehypwf7AWK2YBdMXjBMrPzM9wjA2EW5Fb9QCyl2F5CB16ujQbVTd xr01YNYnyllriwv2xmNXwO7nC3TTfaY+Tt5PudixbEHI6baZt1xqEUwS0M2Zeipz+RZ+ uuew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="GLEOJA/c"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.41.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:41:03 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/33] hw/arm: Don't include qemu-common.h unnecessarily Date: Wed, 15 Dec 2021 10:40:39 +0000 Message-Id: <20211215104049.2030475-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::331 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" A lot of C files in hw/arm include qemu-common.h when they don't need anything from it. Drop the include lines. omap1.c, pxa2xx.c and strongarm.c retain the include because they use it for the prototype of qemu_get_timedate(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Taylor Simpson Reviewed-by: Yoshinori Sato Message-id: 20211129200510.1233037-5-peter.maydell@linaro.org --- hw/arm/boot.c | 1 - hw/arm/digic_boards.c | 1 - hw/arm/highbank.c | 1 - hw/arm/npcm7xx_boards.c | 1 - hw/arm/sbsa-ref.c | 1 - hw/arm/stm32f405_soc.c | 1 - hw/arm/vexpress.c | 1 - hw/arm/virt.c | 1 - 8 files changed, 8 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 74ad397b1ff..399f8e837ce 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -8,7 +8,6 @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "qemu/error-report.h" #include "qapi/error.h" diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index b771a3d8b74..4093af09cb2 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -25,7 +25,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "hw/boards.h" #include "qemu/error-report.h" diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index c3cb315dbc6..4210894d814 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -18,7 +18,6 @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "qapi/error.h" #include "hw/sysbus.h" diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index dec7d16ae51..aff8c870420 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -24,7 +24,6 @@ #include "hw/qdev-core.h" #include "hw/qdev-properties.h" #include "qapi/error.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "qemu/units.h" #include "sysemu/blockdev.h" diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 358714bd3e8..dd944553f78 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -18,7 +18,6 @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "qapi/error.h" #include "qemu/error-report.h" diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index 0019b7f4785..c07947d9f8b 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -24,7 +24,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "qemu-common.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" #include "hw/arm/stm32f405_soc.h" diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 58481c07629..3e6d63c7f96 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -23,7 +23,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "cpu.h" #include "hw/sysbus.h" diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 30da05dfe04..3e2144e31af 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -29,7 +29,6 @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/option.h" From patchwork Wed Dec 15 10:40:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524267 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp244072imb; Wed, 15 Dec 2021 03:30:26 -0800 (PST) X-Google-Smtp-Source: ABdhPJyVR9DUVTF+8R8PVsq7dsIaafdWd839esWBQWarITDv+qcmgRKPt1jiYgRGW5fm7j/6dOlL X-Received: by 2002:a25:db8e:: with SMTP id g136mr5168399ybf.301.1639567826017; Wed, 15 Dec 2021 03:30:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639567826; cv=none; d=google.com; s=arc-20160816; b=BVi1JAXYZXELbPkRjeOUqdF+6ae/W06JCBDDeY0jcJzE6oaAlN1FBZ6ApGHWBbDame h7Oq7f8L8CkOMRwCgFGiB/TstZ6XFhld68/N/147VzYt0F5ikrygBdPwD0uG31TP20B5 NYf6ePW+z7qlT0Z9/UYPM4V32VIKf34ugzW1FhU72J+rDQO5w9gu/+67hUzNCvX7wTAz P7XQX3hbupgfI9VBXJxaSWINfFynOLeQb8DjB01nmutN+BGLCm3clSuJKh0SaHNOLn7t ca3nmyqET2weT55csfJjqJyqkZ44mieUFMzsUxD5tvjF7tPxAgwahUWyht72lfTB3QFb R9lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jRMpMS/CyWONQSCDvYHRycsqwdxA5hg+1aajGuji4ZE=; b=FjW0CMrqEanr334t3/iRDJLpplmoZ09aVHOzp0CJLb0pxUnJcZfTU7ZGl/Wf3EfDKV XxAL1kKgD5Mcd8hpgHYmKgWhGMqGnac5FEnaFWTiJdks83xywr4Y5W1Vl3+sL5WjWcAe IOr1sAGFpMPfIyE1OMJLzFkL4I+PCFfypcJJQYxk5vzIUlDmDAo7ro1hG+39HIo2dzl1 wydsZ2T6jbttQC2DsQTuBUSDsuc9z0Ea5DP89vaFd6JU6UhPSUUOolN8kP0bBezdubYa GGTH0q/ysDXkeb59w3XkBOcEC8pM4+eKGaBmkPsXk2hJJIuAjJ4ccDb56P5l9AjjzOUz mo8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Dj2nkxX/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.41.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:41:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/33] target/arm: Correct calculation of tlb range invalidate length Date: Wed, 15 Dec 2021 10:40:40 +0000 Message-Id: <20211215104049.2030475-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32f (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The calculation of the length of TLB range invalidate operations in tlbi_aa64_range_get_length() is incorrect in two ways: * the NUM field is 5 bits, but we read only 4 bits * we miscalculate the page_shift value, because of an off-by-one error: TG 0b00 is invalid TG 0b01 is 4K granule size == 4096 == 2^12 TG 0b10 is 16K granule size == 16384 == 2^14 TG 0b11 is 64K granule size == 65536 == 2^16 so page_shift should be (TG - 1) * 2 + 12 Thanks to the bug report submitter Cha HyunSoo for identifying both these errors. Fixes: 84940ed82552d3c ("target/arm: Add support for FEAT_TLBIRANGE") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/734 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-id: 20211130173257.1274194-1-peter.maydell@linaro.org --- target/arm/helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9b317899a66..db837d53bd9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4519,18 +4519,18 @@ static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, uint64_t exponent; uint64_t length; - num = extract64(value, 39, 4); + num = extract64(value, 39, 5); scale = extract64(value, 44, 2); page_size_granule = extract64(value, 46, 2); - page_shift = page_size_granule * 2 + 12; - if (page_size_granule == 0) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", page_size_granule); return 0; } + page_shift = (page_size_granule - 1) * 2 + 12; + exponent = (5 * scale) + 1; length = (num + 1) << (exponent + page_shift); From patchwork Wed Dec 15 10:40:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524265 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp242253imb; Wed, 15 Dec 2021 03:28:18 -0800 (PST) X-Google-Smtp-Source: ABdhPJwU/bykxRj0/s9WMRpExgoLWFbHPYyO7TVRu00yne2EcHuFgx3OZ/Uo1ilvZVYX7y8d9pYE X-Received: by 2002:a25:80c9:: with SMTP id c9mr5897958ybm.238.1639567698607; Wed, 15 Dec 2021 03:28:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639567698; cv=none; d=google.com; s=arc-20160816; b=h1rBJhlMT3ZGadO0yTQUxuU1fnexAFsRFNCuSM0B6g42wxLAbP2HVKFOUFyhAXG7lB Y73GZvDvaoC/j2pF/Q//s4p+VT32aEgzuxIUDmpuQ+ox5GC76bwuXtG3FK6QxUckClJC FbhOd89H/j0RtrjfWWV0GpSeZtuMZkWIbqDsTfHC8Hk7Mt6YOTYYl2cZTnAmryEhCz/s 3EVKBQFiucIVsXHFUNgHDac3LytUYSqJFQalt2O3cGHf6H/6PqGVpaSndIxHf8nE7I+W IDcqtfroo8OU0OyQQgRaIEoWwdZ/Im/HVFVzmplxEVoMBd28bW6nKlxvJ05C+JcB0+A9 SwAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BueFJrFQF32/n5kB0mnvMkP97sG05knzH92TC7Y/zGQ=; b=QnGXimwAmiWKFyVOEy8STQlqJEfB5bzKDi6jPxPf8SDurpeh4xmtP2g1k7Df+PvAjO bZFX6ZQc5fgDu7FIYdEkAF2XRrBskbpVyr52pzqykc5AE+3HZqYjNe0dNFs0Flnjw4RO +mhyMgR1xhaXIDZhq1EKqY3KhixFXoANQbpieP0/QYIet2ikLkNoqoFAUGh/6EqWWB2j c1Xqe2ZC55DyEaSmh+2hdddyROTvcoVBf2u0phrz2cC7Pyv1JtZqc6FKaDtFpVUgvSH+ flj0jS0gYgXOtT1OK04WqGsQBYjAJQ8lmwh9mEzMO+9SHVGir6C0gl9JBujGQM+1cLbP XS4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FtQx4a+d; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.41.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:41:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/33] hw/net: npcm7xx_emc fix missing queue_flush Date: Wed, 15 Dec 2021 10:40:41 +0000 Message-Id: <20211215104049.2030475-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::330 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Patrick Venture The rx_active boolean change to true should always trigger a try_read call that flushes the queue. Signed-off-by: Patrick Venture Reviewed-by: Philippe Mathieu-Daudé Message-id: 20211203221002.1719306-1-venture@google.com Signed-off-by: Peter Maydell --- hw/net/npcm7xx_emc.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c index 7c892f820fb..545b2b74108 100644 --- a/hw/net/npcm7xx_emc.c +++ b/hw/net/npcm7xx_emc.c @@ -284,6 +284,12 @@ static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag) emc_set_mista(emc, mista_flag); } +static void emc_enable_rx_and_flush(NPCM7xxEMCState *emc) +{ + emc->rx_active = true; + qemu_flush_queued_packets(qemu_get_queue(emc->nic)); +} + static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc, const NPCM7xxEMCTxDesc *tx_desc, uint32_t desc_addr) @@ -581,13 +587,6 @@ static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t len1) return len; } -static void emc_try_receive_next_packet(NPCM7xxEMCState *emc) -{ - if (emc_can_receive(qemu_get_queue(emc->nic))) { - qemu_flush_queued_packets(qemu_get_queue(emc->nic)); - } -} - static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned size) { NPCM7xxEMCState *emc = opaque; @@ -703,7 +702,7 @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset, emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA; } if (value & REG_MCMDR_RXON) { - emc->rx_active = true; + emc_enable_rx_and_flush(emc); } else { emc_halt_rx(emc, 0); } @@ -739,8 +738,7 @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset, break; case REG_RSDR: if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) { - emc->rx_active = true; - emc_try_receive_next_packet(emc); + emc_enable_rx_and_flush(emc); } break; case REG_MIIDA: From patchwork Wed Dec 15 10:40:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524268 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp245131imb; Wed, 15 Dec 2021 03:31:47 -0800 (PST) X-Google-Smtp-Source: ABdhPJwk4ifVInjm2E6dK9jVTQr67aigL/eFBKp1fKqTLAcNFhPIOfsAOEdS7P/m2sJ0wTMSdJbJ X-Received: by 2002:a5b:108:: with SMTP id 8mr5867876ybx.623.1639567907222; Wed, 15 Dec 2021 03:31:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639567907; cv=none; d=google.com; s=arc-20160816; b=WFVemrIkvWqERmkgd0oqmYdF3xQaMfllg09yM3pVD5CGdjb7uBxgDIILTbN9kSsVK/ sQIhsT1421Atx9boWmOOX2ZUSqm6SJG2dClRPqdxpjWay0kgboJUyfrd0h/0jAvF7ptN f3TfeU3IF9GXEry3TqMojOytW2O98Gv5d0nhjCRM6DHDFFV3sDht9X89CiW2D1T+c0DM MG9kuX0CggTxDM8v+TGzTk7sBnbYCxKFm9c6ivUE14r30pRSPhaz0WaRCh0hkhgyclD2 nxbw5kHU/98Pv8S61uMuhkbOqOGRU17v4JmI7ONF6D2e1QP5JB9IZMx3LIpoMOvqxcFQ Q9gA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LQfvPnAnSV9TH7ItFcMu9ilDeSCvJK9/sHlcO51QJJ0=; b=B95/XqoER+1vd8+Y6pMfUKMzcGAIU4csuX35F+KohjuqDw1M6pUeLYClKRyiTlwvJI CkofZvyCwpqFpoTj6VJi4e25F+F/GuDe6Iq8NNPox60Y+fsYH0tYxknwuVmccq1jQzUU +uScf4q98akygHarpEvDEf5Cyjbs98BFTMYjoYFh3SYyJftXejC9ZppYnJZqiS/0OnKi fxlUPekWZHlZ3dFP0KjDNjaT/Lx7q6rkZnGs/hrE6xWsJom9EX1k7KYMEoNzqAdihpvv NlUwWbgln6/X6uB0ZAY6rsgCNp+/JILYhQPKs3cg2KtLo5TrNbDVZnu7GueesWbIf23T 0+0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OS2HOkyd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.41.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:41:05 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/33] hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu Date: Wed, 15 Dec 2021 10:40:42 +0000 Message-Id: <20211215104049.2030475-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::435 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Jean-Philippe Brucker When a virtio-iommu is instantiated, describe it using the ACPI VIOT table. Acked-by: Igor Mammedov Reviewed-by: Eric Auger Signed-off-by: Jean-Philippe Brucker Message-id: 20211210170415.583179-2-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 7 +++++++ hw/arm/Kconfig | 1 + 2 files changed, 8 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 674f9026525..d0f4867fdfe 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -55,6 +55,7 @@ #include "kvm_arm.h" #include "migration/vmstate.h" #include "hw/acpi/ghes.h" +#include "hw/acpi/viot.h" #define ARM_SPI_BASE 32 @@ -1011,6 +1012,12 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) } #endif + if (vms->iommu == VIRT_IOMMU_VIRTIO) { + acpi_add_table(table_offsets, tables_blob); + build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf, + vms->oem_id, vms->oem_table_id); + } + /* XSDT is pointed to by RSDP */ xsdt = tables_blob->len; build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 2d37d29f02b..e6525909438 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -27,6 +27,7 @@ config ARM_VIRT select DIMM select ACPI_HW_REDUCED select ACPI_APEI + select ACPI_VIOT config CHEETAH bool From patchwork Wed Dec 15 10:40:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524269 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp246355imb; Wed, 15 Dec 2021 03:33:30 -0800 (PST) X-Google-Smtp-Source: ABdhPJysrt7E3yxQQqByppHHyAMoSIFqtO9xkPPN+41RfkEX81sw8JkNB7YGvHZ/oHJEEspRCzXu X-Received: by 2002:a25:104:: with SMTP id 4mr5712747ybb.27.1639568010511; Wed, 15 Dec 2021 03:33:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639568010; cv=none; d=google.com; s=arc-20160816; b=M6FsBEuGN5Y9LhjTyzw/Uik6VLv+IileBTVzOsz5lRyqPndIHa58CsoSsMZQOmqex1 Ys/VKLnNje7rYcW3hsMpE8dbYSpx18hxmc99FqALCq+uNeBbq1i7XNHjs9yYDumzdSXL tZjOpvVZvdCJAr51FvHsVIdX1gVNisEHy3RYytwMTtkfY0sSbrbAxMT5msw3GNp4MJ44 wiYopBR5FZRYQgdWdAYxxhRotwUWUVfxBJKFbC070MW7JWGLYsYmPhN2c1EYuRQpX3e0 aQ1MkQDS1DnSKzPasvzT564CsLkoJJfV24Aia5LICkluCHLt+r56A49X0aINnplTFF1C YnUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mp6wU/cd8wCbmBM90XIFSwoBMkk3KTjj8wwjMORUlrU=; b=CGUsjpzj6LfQLO2F95PYFri9qMCfRBAy30gJMl1U2bfvAtt0BCBUDkpxJtgtRKOabA ckWzMXFd51R7ACHYCVABMejrEXZIOazb/PJ7AeshnpylP+jbCfQg0b+W/RMhLM1JstgK QFuEsOSlFFPBa0IIIboiMDQOIhSFS6Qhv4gPtK2jfQAXiy/6cPnq84BoYhFq1dltIngU 0+/jlsluPr6AaRe3s2eqZyI2b00t3UNPSS3pP/ywYjcoIPNgaiXCa3oyJ+jbFYzI7sHL poc6Ln+OsjGgrQ9s197i3+94MuqT3+q8CQSYjvt85Rf33dE8Yk8JswKfjQjSj3iyjcI2 tA8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pTPRXn1g; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.41.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:41:05 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/33] hw/arm/virt: Remove device tree restriction for virtio-iommu Date: Wed, 15 Dec 2021 10:40:43 +0000 Message-Id: <20211215104049.2030475-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42f (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Jean-Philippe Brucker virtio-iommu is now supported with ACPI VIOT as well as device tree. Remove the restriction that prevents from instantiating a virtio-iommu device under ACPI. Acked-by: Igor Mammedov Reviewed-by: Eric Auger Signed-off-by: Jean-Philippe Brucker Message-id: 20211210170415.583179-3-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- hw/arm/virt.c | 10 ++-------- hw/virtio/virtio-iommu-pci.c | 12 ++---------- 2 files changed, 4 insertions(+), 18 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3e2144e31af..e621cada990 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2613,16 +2613,10 @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, MachineClass *mc = MACHINE_GET_CLASS(machine); if (device_is_dynamic_sysbus(mc, dev) || - (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) { + object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || + object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { return HOTPLUG_HANDLER(machine); } - if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { - VirtMachineState *vms = VIRT_MACHINE(machine); - - if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) { - return HOTPLUG_HANDLER(machine); - } - } return NULL; } diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c index a160ae6b413..6a1df7fe503 100644 --- a/hw/virtio/virtio-iommu-pci.c +++ b/hw/virtio/virtio-iommu-pci.c @@ -48,16 +48,8 @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) VirtIOIOMMU *s = VIRTIO_IOMMU(vdev); if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) { - MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); - - error_setg(errp, - "%s machine fails to create iommu-map device tree bindings", - mc->name); - error_append_hint(errp, - "Check your machine implements a hotplug handler " - "for the virtio-iommu-pci device\n"); - error_append_hint(errp, "Check the guest is booted without FW or with " - "-no-acpi\n"); + error_setg(errp, "Check your machine implements a hotplug handler " + "for the virtio-iommu-pci device"); return; } for (int i = 0; i < s->nb_reserved_regions; i++) { From patchwork Wed Dec 15 10:40:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524272 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp248642imb; Wed, 15 Dec 2021 03:36:49 -0800 (PST) X-Google-Smtp-Source: ABdhPJz3Aldn6vSBysFxsWMSQ7sqZvEkFHksyiLFfrK50UftdHRTq/ExZyp9wTmKOmfAUHf0MlPZ X-Received: by 2002:a25:fc24:: with SMTP id v36mr5536887ybd.588.1639568209391; Wed, 15 Dec 2021 03:36:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639568209; cv=none; d=google.com; s=arc-20160816; b=gLxJkF8CUd/AxOLRId214E9WkVXF7fvzE4g8TtZAFg9SPRhEee1+J20ygISxzzDEjM AU97OHBEMa1/5o7s+IotB1ie3wavy2JgrJogJDWw++AVDs1Tku/24gEYWkECWr/OpZXg fDfEvEcYR69owitZHvMYRQTj5POrNSQDGUzJ9z1RUbO35KjgjE5Ig2N0tqwKGGv39bA2 0qLzWPtqYqMvzytNCW8h0PQfD0+ZGT6MGsy0svazKS09IwEy4MgG2UaApvT1tzw75QVE HFJgyCnc8aPu3qUJGDOb9T8++/Ozp7NixnnPJ1x0IGdKyvfsFKtlRE7E15f2jA6f4U1b /TQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QlaXP6HbGtQy9VsDGePHKfrhYKYYns72bklRe3d2y+Q=; b=x2lfelta/XR/IJPx9/F7c8azt8Q4bxyxsJnYFnTNiv8Qb/4A3SRngY2aAPuBkLUGL1 +4+Q0mF8U4riXWzq6G51/epRXfyXYrQ/P3Ohzfml4kRdoGTRNvxuyqBtd/yuerlOOIG5 ulx5wj4i+wc6DJDtYRFn5aaRzEL6O4PB5LuJmN5iTKdFgqE/pfSsz3cLmHKIKHa3hE6d 3HLKVszVWJioNHvPHmfnuZrycXlcebDPQ63ZwPOcJjLcnVP8SAE38o1ndG7/JVVSuY8p /3GmkfwJOUA72v/tnGs3o9e1M52iMlipxXFxrdGpMUsdz8y9LENUVeQ85BFuvlBNR3vC SsmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="acr/bnKN"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.41.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:41:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/33] hw/arm/virt: Reject instantiation of multiple IOMMUs Date: Wed, 15 Dec 2021 10:40:44 +0000 Message-Id: <20211215104049.2030475-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::334 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Jean-Philippe Brucker We do not support instantiating multiple IOMMUs. Before adding a virtio-iommu, check that no other IOMMU is present. This will detect both "iommu=smmuv3" machine parameter and another virtio-iommu instance. Fixes: 70e89132c9 ("hw/arm/virt: Add the virtio-iommu device tree mappings") Reviewed-by: Eric Auger Reviewed-by: Igor Mammedov Signed-off-by: Jean-Philippe Brucker Message-id: 20211210170415.583179-4-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- hw/arm/virt.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index e621cada990..41c9808a3fd 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2493,6 +2493,11 @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, hwaddr db_start = 0, db_end = 0; char *resv_prop_str; + if (vms->iommu != VIRT_IOMMU_NONE) { + error_setg(errp, "virt machine does not support multiple IOMMUs"); + return; + } + switch (vms->msi_controller) { case VIRT_MSI_CTRL_NONE: return; From patchwork Wed Dec 15 10:40:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524276 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp250760imb; Wed, 15 Dec 2021 03:39:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJyuBC96VoPjDWx5KsIgwIlmgBCWHQ0GK0JdsQBqPeAeQ5Mj5HnGAVYOK6FIeGe+7qzNvdDa X-Received: by 2002:a05:6e02:1a65:: with SMTP id w5mr6073740ilv.57.1639568396718; Wed, 15 Dec 2021 03:39:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639568396; cv=none; d=google.com; s=arc-20160816; b=c9S6ZlDXTXDcuVejL0Exdao/WtHJUH0Iu6Gl/5tkEWG50UigxwZ2oXZqcKyivqLU1Q mrVIBny9RbFxXUNvSzeVawrt6XqwnFAYHPKY928VvGU6SOHEoZPUECLqdJVkVvIiNLUm kyq6EJDpogm54Dli4H3L+omToWk/AAnzn2U7tivSx6AskaURBSE+cGIaSHNGZC0tkUoL bz46KOxrQ967IQta/x8QjOa2FU5q/JRwPQ0cu1GyycDiXZS/O42aAGI0tlH+nZiS2zJW zBcjAFQppu0zbtox2wYgk25+rjHzeh17AiVh9fN3zdQ7rjLipz5bBUhu8H17T/6dBqkj lxgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=sNNQW6d9QcHylqNB7F7ihK/G2DuCR/LnfVagA5pSg9U=; b=bp1JnTGFLXHiQZXA3ooEb3MeTy+4GgsdBgqaygjU+ZrzvoFjR5G/pNhptF0srYM3Iz /HoLVL+DZduU/CZffYvcldTJuQKG8BpG2uYdP5CMl1Z95Qb4hOeRb06okQCEDSDjBQ3W sSEhRMYv+ScmHQAlxxLz7KyUAerPi2ChXTMQbUUpOU/g6JaeJL9NrbRkZBHsU00gOY/+ K/FfkHZfcnAyqEyd1fWtQM+p2icFUN1zo8w5KGrV9rbYyVwekfcxLuBH8OhbTHoJI4mF V36tHDvnwZwAiLH1H+WI6xK5ls5gSqgMfABAZL4t+KOD826WGjaEocPlgWQPQjefn0xM wNrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gkIH1z9D; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.41.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:41:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/33] hw/arm/virt: Use object_property_set instead of qdev_prop_set Date: Wed, 15 Dec 2021 10:40:45 +0000 Message-Id: <20211215104049.2030475-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42a (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Jean-Philippe Brucker To propagate errors to the caller of the pre_plug callback, use the object_poperty_set*() functions directly instead of the qdev_prop_set*() helpers. Suggested-by: Igor Mammedov Reviewed-by: Eric Auger Reviewed-by: Igor Mammedov Signed-off-by: Jean-Philippe Brucker Message-id: 20211210170415.583179-5-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- hw/arm/virt.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 41c9808a3fd..6bce595aba2 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2517,8 +2517,9 @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, db_start, db_end, VIRTIO_IOMMU_RESV_MEM_T_MSI); - qdev_prop_set_uint32(dev, "len-reserved-regions", 1); - qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str); + object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); + object_property_set_str(OBJECT(dev), "reserved-regions[0]", + resv_prop_str, errp); g_free(resv_prop_str); } } From patchwork Wed Dec 15 10:40:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524274 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp248951imb; Wed, 15 Dec 2021 03:37:20 -0800 (PST) X-Google-Smtp-Source: ABdhPJyM9vh/39yq/UHSUen1OiQ+fi4Sj9y9IVkKnlxrbQgnMc3ssGVwHnwlGZzVhMknXXQGo8Y8 X-Received: by 2002:a05:6902:100a:: with SMTP id w10mr6664565ybt.441.1639568240875; Wed, 15 Dec 2021 03:37:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639568240; cv=none; d=google.com; s=arc-20160816; b=Pw/KsHDzwk5CViVxMA0dLzrMaV3qwe4grgxH5JVOoAYGWGw5msMfA8dbAlYr5D6OoB u5+vqGNaKfKF9BqY/BoHA2bMJA2cf2o+uoH7YeDIR0OVD1JokRuZ98lwDuBPozCZwxue +OIo9ZvpjcKJOTWTVyrN7xLRAK1Yry6rv1VJM4n6UPnmty5pwmRsUppjI2jS0VcTMuJH GX2eMixje1jRInCy+dUZ+1NnjeGBsCoeaakGmZEkodHPPKbm+RtQSPFtzBonaQ1Q1Wc7 CF29RCNlnTiua+XZCBJ8tVbPoKiDxnZLQMdHKdVWbiutIFzEZ3WHB653ey6kMG/gFSFF GwPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bo0mTQjcOMMWuhko1G14Jx9iZKqWtrs0vKnktosNhhc=; b=zowVqkohXfjV0uisdzQp9rtejAQid0HiqHwPdkpWg8FLSAFz1QXKZyDFCvImocF4rs 4ChPd5sZCRuVWKX22m5ZxhQONGnrMpZoAgo6wnfJqbHvTAi2efQZsdKrFp19NGy3rUpk AwGiEirLRoFIZe9aANMNYeLfkiZfi73oy/Hgsmwdk4rYpm20/HOx672DDtvAhA2CnRKs +gSbW7vOeuiRYtWj3VZKoX/Xy82TyFK1WphWLfQsRPT02WouhsFImTn88tothvZjGsi4 7rjC0KahaotQDmoH3J2T6cdBqGxMsjuwxLxxbxOGYC952vnlDz6vAw82yfISF8lsodgF OpiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hPGL3a2F; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.41.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:41:07 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/33] tests/acpi: allow updates of VIOT expected data files Date: Wed, 15 Dec 2021 10:40:46 +0000 Message-Id: <20211215104049.2030475-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::336 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Jean-Philippe Brucker Create empty data files and allow updates for the upcoming VIOT tests. Acked-by: Igor Mammedov Reviewed-by: Eric Auger Signed-off-by: Jean-Philippe Brucker Message-id: 20211210170415.583179-6-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ tests/data/acpi/q35/DSDT.viot | 0 tests/data/acpi/q35/VIOT.viot | 0 tests/data/acpi/virt/VIOT | 0 4 files changed, 3 insertions(+) create mode 100644 tests/data/acpi/q35/DSDT.viot create mode 100644 tests/data/acpi/q35/VIOT.viot create mode 100644 tests/data/acpi/virt/VIOT diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8bf..29b5b1eabc7 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,4 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/VIOT", +"tests/data/acpi/q35/DSDT.viot", +"tests/data/acpi/q35/VIOT.viot", diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot new file mode 100644 index 00000000000..e69de29bb2d diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot new file mode 100644 index 00000000000..e69de29bb2d diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT new file mode 100644 index 00000000000..e69de29bb2d From patchwork Wed Dec 15 10:40:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524261 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp238188imb; Wed, 15 Dec 2021 03:22:21 -0800 (PST) X-Google-Smtp-Source: ABdhPJw4k6XWNWMXEdBumLQZ/OVk8njDcAqO6J2h5AadaW3Q/Xy489zi+vASHIxD9KEj6GY1HrCf X-Received: by 2002:a25:d492:: with SMTP id m140mr6132097ybf.105.1639567340920; Wed, 15 Dec 2021 03:22:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639567340; cv=none; d=google.com; s=arc-20160816; b=XuAhv/MksrGhr99Suzbgni/+HshsDC+Ray26oQ9b7jwTkaMI87wizi1GaVzvQLu/ks 695WqHq9dKV/nZxroO8zoyOrm3BC2jPbhBAncxRDBV/3ex3vr76tkZsYb28G/q2mxv5w 3KeJsPJjU2BVo5AhpzGkMFhibIQO7hGQLMbd2sQ0Wre2a01UL4E8LUs2mcG1bShcxBTL aolGpamRRgVFV8pABxDvwPX9YRBlpELyoItp0diX/MNLUJcXO6mC2Y2hn3uOQaosDp9s PjsnhtyH3Sx6DXcnnr9dJ4abjgByUB4pYsN0SqRQBXlkb3iFSQq+nfiXpmISz622VWe7 vkPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AxAfi0cSCTWP0iQobjmr0rvRXa2XPUga+L6BtFS0ls8=; b=Ctn+6WwrsXbGnBv+NDpVvqKL7ZyNo1Y2hduwnI9KeQJuwnJ0ibWYawjxp7huFmQda5 DgLsKb6MJMTgDroK0KLEWSWbnbvQT25osqkNRQebzuwcIwrYIDn4lHz9Z5EF3iFtLopI ivxgH9CkdQKCCFo0zekzFnMv18F9la9EWrbHHiT2RlG6E6HsDHgDMsTClIfCx41kqM9U GqBXgKrthPRxEsn/cOftEaDe3Hzb0YF7jAbtNMbLoTaqnFhIkB4KXmM6nZqDn5qGn4mB CqKfseD6OKU1x5ox4kDSAo+XNzbq6WYxZivxSRnxeRmgivj9l/RIomz/q402gVhIZ5tB +8Ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=asxNSw+s; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.41.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:41:07 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/33] tests/acpi: add test case for VIOT Date: Wed, 15 Dec 2021 10:40:47 +0000 Message-Id: <20211215104049.2030475-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32a (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Jean-Philippe Brucker Add two test cases for VIOT, one on the q35 machine and the other on virt. To test complex topologies the q35 test has two PCIe buses that bypass the IOMMU (and are therefore not described by VIOT), and two buses that are translated by virtio-iommu. Reviewed-by: Eric Auger Reviewed-by: Igor Mammedov Signed-off-by: Jean-Philippe Brucker Message-id: 20211210170415.583179-7-jean-philippe@linaro.org Signed-off-by: Peter Maydell Reported-by: Richard Henderson Signed-off-by: Jean-Philippe Brucker --- tests/qtest/bios-tables-test.c | 38 ++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 258874167ef..58df53b15b5 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1465,6 +1465,42 @@ static void test_acpi_virt_tcg(void) free_test_data(&data); } +static void test_acpi_q35_viot(void) +{ + test_data data = { + .machine = MACHINE_Q35, + .variant = ".viot", + }; + + /* + * To keep things interesting, two buses bypass the IOMMU. + * VIOT should only describes the other two buses. + */ + test_acpi_one("-machine default_bus_bypass_iommu=on " + "-device virtio-iommu-pci " + "-device pxb-pcie,bus_nr=0x10,id=pcie.100,bus=pcie.0 " + "-device pxb-pcie,bus_nr=0x20,id=pcie.200,bus=pcie.0,bypass_iommu=on " + "-device pxb-pcie,bus_nr=0x30,id=pcie.300,bus=pcie.0", + &data); + free_test_data(&data); +} + +static void test_acpi_virt_viot(void) +{ + test_data data = { + .machine = "virt", + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd", + .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2", + .ram_start = 0x40000000ULL, + .scan_len = 128ULL * 1024 * 1024, + }; + + test_acpi_one("-cpu cortex-a57 " + "-device virtio-iommu-pci", &data); + free_test_data(&data); +} + static void test_oem_fields(test_data *data) { int i; @@ -1639,6 +1675,7 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic); qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar); } + qtest_add_func("acpi/q35/viot", test_acpi_q35_viot); } else if (strcmp(arch, "aarch64") == 0) { if (has_tcg) { qtest_add_func("acpi/virt", test_acpi_virt_tcg); @@ -1646,6 +1683,7 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp); qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb); qtest_add_func("acpi/virt/oem-fields", test_acpi_oem_fields_virt); + qtest_add_func("acpi/virt/viot", test_acpi_virt_viot); } } ret = g_test_run(); From patchwork Wed Dec 15 10:40:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524277 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp252097imb; Wed, 15 Dec 2021 03:41:57 -0800 (PST) X-Google-Smtp-Source: ABdhPJwoun78cTI0XnVDDNG2QirYNT4IgZfmrp/NobHTJ/v2Tal/NM0O7rnRx8Jj7EYrMG2xBN4p X-Received: by 2002:a25:4213:: with SMTP id p19mr5291872yba.41.1639568516882; Wed, 15 Dec 2021 03:41:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639568516; cv=none; d=google.com; s=arc-20160816; b=TmSlXFljRvESwseEWULyEbOP+9q8p/MtZaJnn65AWyYNSUwLoqvlwm/J5nYyoah3ke NUIoeWkjvbTJIye0D2pNaJoUPZMpZDrQEkcqQ/xTDAGt+gsKuaIdFUWovEIuR/PhoKye tnkFSrr0R7OFXp1acaelXNjz7d/YrJWsaXr3CJuHNv8tYqdvenGQHkisl+YHDaRyt4+W s9R0qp8nRfyA1DNt7uGns2Y9eL6OfI+LuF1b0AtqFRecHWVsIse/XVLg50ykyCJH6/0y XW16ZkKpiC/pEsn4PfVL2Y+EvDZHQQG6VLnUz7ls4GOS/x6dltm3/6/n+6GRYzk7gNqb 5asQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gNzXUu0OrlHTO9BQfopM0W7JsU+2JwfO+ymcTMcHXMc=; b=Ou/cKvjlM06x93lxWZgL/l067sQACHhqmsOAMKHrIAWLCi8LgZVBT7WgABr/Q6xdbs rV+vIX4h56l0NKl2QOVwjClj0pHp6FzySz+Bk4q6ML+NaOrVIhXo2PAj4urhmZwrIMzJ lpPv/dOgzEvT29HGzFoULVCPNw415Tk0RCEtKPEraqrQxdlbEe91M0Hv3n8hTJzbZr4O AMrcgvrDiJFfe9XtHq2oRn0AkgJh+LiKGgxgXrr1qCSaObNy4vBLQoJzKTuxqFRV8loY sxg08ZiX27Dou100gFXnImMlOKVqekXx6B3M7BLgemX0Io/BE9TVQq7+dVwPlYtLWO/e lyHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=co4L6APL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.41.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:41:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/33] tests/acpi: add expected blobs for VIOT test on q35 machine Date: Wed, 15 Dec 2021 10:40:48 +0000 Message-Id: <20211215104049.2030475-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::334 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Jean-Philippe Brucker Add expected blobs of the VIOT and DSDT table for the VIOT test on the q35 machine. Since the test instantiates a virtio device and two PCIe expander bridges, DSDT.viot has more blocks than the base DSDT. The VIOT table generated for the q35 test is: [000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table] [004h 0004 4] Table Length : 00000070 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 3D [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 2] Node count : 0003 [026h 0038 2] Node offset : 0030 [028h 0040 8] Reserved : 0000000000000000 [030h 0048 1] Type : 03 [VirtIO-PCI IOMMU] [031h 0049 1] Reserved : 00 [032h 0050 2] Length : 0010 [034h 0052 2] PCI Segment : 0000 [036h 0054 2] PCI BDF number : 0010 [038h 0056 8] Reserved : 0000000000000000 [040h 0064 1] Type : 01 [PCI Range] [041h 0065 1] Reserved : 00 [042h 0066 2] Length : 0018 [044h 0068 4] Endpoint start : 00003000 [048h 0072 2] PCI Segment start : 0000 [04Ah 0074 2] PCI Segment end : 0000 [04Ch 0076 2] PCI BDF start : 3000 [04Eh 0078 2] PCI BDF end : 30FF [050h 0080 2] Output node : 0030 [052h 0082 6] Reserved : 000000000000 [058h 0088 1] Type : 01 [PCI Range] [059h 0089 1] Reserved : 00 [05Ah 0090 2] Length : 0018 [05Ch 0092 4] Endpoint start : 00001000 [060h 0096 2] PCI Segment start : 0000 [062h 0098 2] PCI Segment end : 0000 [064h 0100 2] PCI BDF start : 1000 [066h 0102 2] PCI BDF end : 10FF [068h 0104 2] Output node : 0030 [06Ah 0106 6] Reserved : 000000000000 And the DSDT diff is: @@ -5,13 +5,13 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT, Fri Dec 10 15:03:08 2021 + * Disassembly of /tmp/aml-H9Y5D1, Fri Dec 10 15:02:27 2021 * * Original Table Header: * Signature "DSDT" - * Length 0x00002061 (8289) + * Length 0x000024B6 (9398) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xFA + * Checksum 0xA7 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) @@ -3114,6 +3114,339 @@ } } + Scope (\_SB) + { + Device (PC30) + { + Name (_UID, 0x30) // _UID: Unique ID + Name (_BBN, 0x30) // _BBN: BIOS Bus Number + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PC30._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0030, // Range Minimum + 0x0030, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + } + } + + Scope (\_SB) + { + Device (PC20) + { + Name (_UID, 0x20) // _UID: Unique ID + Name (_BBN, 0x20) // _BBN: BIOS Bus Number + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PC20._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0020, // Range Minimum + 0x0020, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + } + } + + Scope (\_SB) + { + Device (PC10) + { + Name (_UID, 0x10) // _UID: Unique ID + Name (_BBN, 0x10) // _BBN: BIOS Bus Number + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PC10._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0010, // Range Minimum + 0x0010, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + } + } + Scope (\_SB.PCI0) { Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings @@ -3121,9 +3454,9 @@ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, // Granularity 0x0000, // Range Minimum - 0x00FF, // Range Maximum + 0x000F, // Range Maximum 0x0000, // Translation Offset - 0x0100, // Length + 0x0010, // Length ,, ) IO (Decode16, 0x0CF8, // Range Minimum @@ -3278,6 +3611,26 @@ } } + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + } + + Device (S18) + { + Name (_ADR, 0x00030000) // _ADR: Address + } + + Device (S20) + { + Name (_ADR, 0x00040000) // _ADR: Address + } + + Device (S28) + { + Name (_ADR, 0x00050000) // _ADR: Address + } + Method (PCNT, 0, NotSerialized) { } Reviewed-by: Eric Auger Signed-off-by: Jean-Philippe Brucker Message-id: 20211210170415.583179-8-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 2 -- tests/data/acpi/q35/DSDT.viot | Bin 0 -> 9398 bytes tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes 3 files changed, 2 deletions(-) diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..1c3b4da5cbe81ecab5e1ef50d383b561c5e0f55f 100644 GIT binary patch literal 9398 zcmeHNO>7&-8J*>iv|O&FB}G~Oi$yp||57BBoWHhc5OS9yDTx$CQgH$r;8Idr*-4Q_ z5(9Az1F`}niVsB-)S~D)a>NF1~WVB6^~_B#yhJ`H+JU@=6aXs`?Yv)J2h=N?drcS zeLZ*n<JRPm3~# z&ICS{+_OayRW-l=Mtk=~uaS3o8z<_udd|(wqg`&JnVPfCe>BUOO`Su3e>pff_^UW% z&JE^NO`)=Amg~iqRB1pPscP?(>#ZuY8GHCmlEvD$9g3%4Db~Dfz2SATnddvrR-Oe^ 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b/tests/qtest/bios-tables-test-allowed-diff.h index 29b5b1eabc7..8367ffe1d40 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,4 +1,2 @@ /* List of comma-separated changed AML files to ignore */ "tests/data/acpi/virt/VIOT", -"tests/data/acpi/q35/DSDT.viot", -"tests/data/acpi/q35/VIOT.viot", From patchwork Wed Dec 15 10:40:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 524275 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp250081imb; Wed, 15 Dec 2021 03:38:59 -0800 (PST) X-Google-Smtp-Source: ABdhPJza5yvyZ7AaOj1xT2LLEb0jA2ewOlwKcsSZiZR0vjRULD4rq9bxwvPqpO0lRhlsTVz77xMx X-Received: by 2002:a05:6638:101c:: with SMTP id r28mr6109038jab.674.1639568339882; Wed, 15 Dec 2021 03:38:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1639568339; cv=none; d=google.com; s=arc-20160816; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e18sm1600815wrs.48.2021.12.15.02.41.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 02:41:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/33] tests/acpi: add expected blob for VIOT test on virt machine Date: Wed, 15 Dec 2021 10:40:49 +0000 Message-Id: <20211215104049.2030475-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215104049.2030475-1-peter.maydell@linaro.org> References: <20211215104049.2030475-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::431 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Jean-Philippe Brucker The VIOT blob contains the following: [000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table] [004h 0004 4] Table Length : 00000058 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 66 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 2] Node count : 0002 [026h 0038 2] Node offset : 0030 [028h 0040 8] Reserved : 0000000000000000 [030h 0048 1] Type : 03 [VirtIO-PCI IOMMU] [031h 0049 1] Reserved : 00 [032h 0050 2] Length : 0010 [034h 0052 2] PCI Segment : 0000 [036h 0054 2] PCI BDF number : 0008 [038h 0056 8] Reserved : 0000000000000000 [040h 0064 1] Type : 01 [PCI Range] [041h 0065 1] Reserved : 00 [042h 0066 2] Length : 0018 [044h 0068 4] Endpoint start : 00000000 [048h 0072 2] PCI Segment start : 0000 [04Ah 0074 2] PCI Segment end : 0000 [04Ch 0076 2] PCI BDF start : 0000 [04Eh 0078 2] PCI BDF end : 00FF [050h 0080 2] Output node : 0030 [052h 0082 6] Reserved : 000000000000 Acked-by: Ani Sinha Reviewed-by: Eric Auger Signed-off-by: Jean-Philippe Brucker Message-id: 20211210170415.583179-9-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 1 - tests/data/acpi/virt/VIOT | Bin 0 -> 88 bytes 2 files changed, 1 deletion(-) diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..921f40d88c28ba2171a4d664e119914335309e7d 100644 GIT binary patch literal 88 zcmWIZ^bd((0D?3pe`k+i1*eDrX9XZ&1PX!JAexE60Hgv8m>C3sGzXN&z`)2L0cSHX I{D-Rq0Q5fy0RR91 literal 0 HcmV?d00001 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index 8367ffe1d40..dfb8523c8bf 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,2 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/virt/VIOT",