From patchwork Fri Nov 9 15:26:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 150663 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp80768ljp; Fri, 9 Nov 2018 07:28:15 -0800 (PST) X-Google-Smtp-Source: AJdET5fMlCIKDNQm8yLfxtmy9DpRHYqrg5DsIZHtYSkWrsrJdQb1edfxV416N9l/J8cN3an3Qm5q X-Received: by 2002:a17:906:e211:: with SMTP id gf17-v6mr2150643ejb.46.1541777295521; Fri, 09 Nov 2018 07:28:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541777295; cv=none; d=google.com; s=arc-20160816; b=xIlsax/+UM6mzIsIMA4+Hw+I2+pZTW1FcgXh8slx+rOSD5b9uc/RGmJILl+SO61K0a dGb78pdQLci3bHOJzJ/1qG4cDQOeyZn1jnMEK+1Al1sXGSL1ZX3/mg1NBEZmcyltbHZ9 D1E/HyBrvx6DzHLaPwXPsFnXoDAC3+RvfhiD+2chEWVaNDme+UHKR7UXP8mGZZTwrh+X qkAqieC5LCU9sAruiHIN6n33NKjDKk5odeessViYO6NSqKfZINszk9ncIPTeVTy46LyA Rh7FG0EVSGvvmlpnZCj9wET54pPxvt3Vueixrut7LCXWOAkyayl44CAxOshnZ/eIdINV jtjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature; bh=UPFDPj5Oght8n8cB1sgMx1UC4s+X30PVCnBW3L1nQtQ=; b=a3J7pkjEUnE2BJZfMVV8vXUyz8LxvHbsoJz30Ay/iQYC/fZ1SPAidPDQ9Ncl45BlxH ZHNrK0X+NGGEuCLd7G+EXdC0wss734YWFRNTKpICi1JoJMUtsmYIDMDKJaZTrsyXNXZ0 u4Cb2sE0IMGBlaqiJH+OHjH2PAeEl0ri+UbCG3vP+vwnvpFaRwBImeDEI/auRKEX5bw6 LbrPqLS7xoAhb8ilVfalcufkgj4pugSIKdSdLGzId+AuvRh4nbDLGl2llyBZMOCWNtVy Qgf9TlA3PEYZ4dKwmf2vtZ9C/w1v8scAyZwjnctGcl8hWWfMasGpWUFxAHnbAZ7vh2fo 7fIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=l71qEMu7; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. 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This makes sense since compiling these targets will export global symbols, such as board_init() The change rework amlogic Kconfig so only one board may be selected at a time Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- arch/arm/mach-meson/Kconfig | 51 ++++++++++++++++++--------------------------- 1 file changed, 20 insertions(+), 31 deletions(-) diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index cc94344..bc0f6a1 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -1,41 +1,32 @@ if ARCH_MESON -config MESON_GXBB - bool "Support Meson GXBaby" +config MESON64_COMMON + bool select ARM64 select CLK select DM select DM_SERIAL imply CMD_DM - help - The Amlogic Meson GXBaby (S905) is an ARM SoC with a - quad-core Cortex-A53 CPU and a Mali-450 GPU. + +config MESON_GXBB + bool + select MESON64_COMMON config MESON_GXL - bool "Support Meson GXL" - select ARM64 - select CLK - select DM - select DM_SERIAL - imply CMD_DM - help - The Amlogic Meson GXL (S905X and S905D) is an ARM SoC with a - quad-core Cortex-A53 CPU and a Mali-450 GPU. + bool + select MESON64_COMMON config MESON_GXM - bool "Support Meson GXM" - select ARM64 - select CLK - select DM - select DM_SERIAL - help - The Amlogic Meson GXM (S912) is an ARM SoC with an - octo-core Cortex-A53 CPU and a Mali-T860 GPU. + bool + select MESON64_COMMON -if MESON_GXBB +choice + prompt "Platform select" + default TARGET_ODROID_C2 config TARGET_ODROID_C2 bool "ODROID-C2" + select MESON_GXBB help ODROID-C2 is a single board computer based on Meson GXBaby with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD @@ -43,16 +34,15 @@ config TARGET_ODROID_C2 config TARGET_NANOPI_K2 bool "NANOPI_K2" + select MESON_GXBB help NANOPI_K2 is a single board computer based on Meson GXBaby with 2 GiB of RAM, Gigabit Ethernet,AP6212 Wifi, HDMI, 4 USB, micro-SD slot, eMMC, IR receiver and a 40-pin GPIO header. -endif - -if MESON_GXL config TARGET_P212 bool "P212" + select MESON_GXL help P212 is a reference dessign board based on Meson GXL S905X SoC with 2 GiB of RAM, Ethernet, HDMI, 2 USB, micro-SD slot, @@ -60,6 +50,7 @@ config TARGET_P212 config TARGET_LIBRETECH_CC bool "LIBRETECH-CC" + select MESON_GXL help LibreTech CC is a single board computer based on Meson GXL with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot, @@ -67,23 +58,21 @@ config TARGET_LIBRETECH_CC config TARGET_KHADAS_VIM bool "KHADAS-VIM" + select MESON_GXL help Khadas VIM is a single board computer based on Meson GXL with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot, eMMC, IR receiver and a 40-pin GPIO header. -endif - -if MESON_GXM - config TARGET_KHADAS_VIM2 bool "KHADAS-VIM2" + select MESON_GXM help Khadas VIM2 is a single board computer based on Meson GXM with 2/3 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot, eMMC, IR receiver and a 40-pin GPIO header. -endif +endchoice config SYS_SOC default "meson" From patchwork Fri Nov 9 15:26:41 2018 Content-Type: text/plain; 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We can easily derive it from CONFIG_DEFAULT_DEVICE_TREE instead. This will help factorize the code a bit Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- include/configs/khadas-vim.h | 2 -- include/configs/libretech-cc.h | 2 -- include/configs/meson-gx-common.h | 2 +- include/configs/nanopi-k2.h | 4 ---- include/configs/odroid-c2.h | 4 ---- include/configs/p212.h | 4 ---- 6 files changed, 1 insertion(+), 17 deletions(-) diff --git a/include/configs/khadas-vim.h b/include/configs/khadas-vim.h index 6615f77..ff87c02 100644 --- a/include/configs/khadas-vim.h +++ b/include/configs/khadas-vim.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-khadas-vim.dtb\0" - #include #endif /* __CONFIG_H */ diff --git a/include/configs/libretech-cc.h b/include/configs/libretech-cc.h index a0856f9..95e0f34 100644 --- a/include/configs/libretech-cc.h +++ b/include/configs/libretech-cc.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-libretech-cc.dtb\0" - #include #endif /* __CONFIG_H */ diff --git a/include/configs/meson-gx-common.h b/include/configs/meson-gx-common.h index c46522e..c436976 100644 --- a/include/configs/meson-gx-common.h +++ b/include/configs/meson-gx-common.h @@ -44,7 +44,7 @@ "kernel_addr_r=0x01080000\0" \ "pxefile_addr_r=0x01080000\0" \ "ramdisk_addr_r=0x13000000\0" \ - MESON_FDTFILE_SETTING \ + "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ BOOTENV #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */ diff --git a/include/configs/nanopi-k2.h b/include/configs/nanopi-k2.h index ef53f20..3fd6e8f 100644 --- a/include/configs/nanopi-k2.h +++ b/include/configs/nanopi-k2.h @@ -7,10 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* Serial setup */ - -#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxbb-nanopi-k2.dtb\0" - #include #endif /* __CONFIG_H */ diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h index d117b18..87e3ddb 100644 --- a/include/configs/odroid-c2.h +++ b/include/configs/odroid-c2.h @@ -7,10 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* Serial setup */ - -#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxbb-odroidc2.dtb\0" - #include #endif /* __CONFIG_H */ diff --git a/include/configs/p212.h b/include/configs/p212.h index 2aa9f5d..4414293 100644 --- a/include/configs/p212.h +++ b/include/configs/p212.h @@ -9,10 +9,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* Serial setup */ - -#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-p212.dtb\0" - #include #endif /* __CONFIG_H */ From patchwork Fri Nov 9 15:26:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 150668 Delivered-To: patch@linaro.org Received: by 2002:aa7:da0f:0:0:0:0:0 with SMTP id r15csp373866eds; Fri, 9 Nov 2018 07:31:52 -0800 (PST) X-Google-Smtp-Source: AJdET5eTFCiPedR3hBtuT0OmEDzBy2laTVuOO3CJ4h8BneY0PF+OX2LkNLA0fhDDerHJvq92akNo X-Received: by 2002:aa7:d48e:: with SMTP id b14-v6mr2666959edr.256.1541777512183; Fri, 09 Nov 2018 07:31:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541777512; cv=none; d=google.com; s=arc-20160816; b=ZV3WdSAG7HA5mNhLpM7ulnaMXmsubMM1Q1spPx1s4oHznBt3RPZqMigCGj1hrkvF0V f9BXtEbCF1WJ1r3+l/d/5GMaG8OcREMmF/LfQwJCsO7lL7lA36RtCJy000FBEZNRH9lc HiV+Oe2smforHbtZjKAczdRIxM/RfMJFKtx85+hvcFdAWtNSsA4qIjkG4eOPzXaA+Pz6 9+9InVOBNoaiDVFPHMHr0lGtqKe8tShvxVKTtfCnldNrqTVxY5AB7DtPuKD/7nlM9a/v wRfOOwRxQfxfK7ueIcMiyrCb9fU1ntexqY6JDVNvM/qLsesA4GmqBydTNVrgheNI6izB yqtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature; bh=eHgA7fhqcLpnWkbeBJOp2Appj39VZGmj/LUQzIHjvnQ=; b=AWbMR8kMnqGEXxBere/ieezuHfROzPIrUm7mna6dYZ8+ymEaD6J0AOvn/cYvTbqkAs J8BKXuovP1OlTrTitpkHq3yBa2gyp+xSmnw6g1+xa3PYXAg8xfg0tfk89ywy1m46YJ4A QjTvS3qoi7bPnMHeDOP8OTAGiNfVMCPe/kZ2utMcuVcbLdtkz92UeNqKK7HbOVmO5yZx UPA3JR+MKfm+zHCrEfXM3rtCfYnAu5VqwSD2noY8WywM4rhr2ixQM6BqGCo92UcCbdPx uHpV8+/Qr+OUrbnFWbWiVRtgpK/6ql1mnpx4t9lZOfGbl/6kgSATMVMUEg6XFqG9ZalG eetg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=HrAurJuZ; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. 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All the code in these board is a copy/paste from the p212, which is tedious to maintain. This change use p212 u-boot board for all these boards, while keeping a dedicated defconfig to customize the names and device tree. Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- arch/arm/mach-meson/Kconfig | 22 +------ board/amlogic/khadas-vim/Kconfig | 12 ---- board/amlogic/khadas-vim/MAINTAINERS | 6 -- board/amlogic/khadas-vim/Makefile | 6 -- board/amlogic/khadas-vim/README | 102 ----------------------------- board/amlogic/khadas-vim/khadas-vim.c | 57 ----------------- board/amlogic/libretech-cc/Kconfig | 12 ---- board/amlogic/libretech-cc/MAINTAINERS | 6 -- board/amlogic/libretech-cc/Makefile | 6 -- board/amlogic/libretech-cc/README | 102 ----------------------------- board/amlogic/libretech-cc/libretech-cc.c | 57 ----------------- board/amlogic/p212/README | 103 ------------------------------ board/amlogic/p212/README.khadas-vim | 102 +++++++++++++++++++++++++++++ board/amlogic/p212/README.libretech-cc | 102 +++++++++++++++++++++++++++++ board/amlogic/p212/README.p212 | 103 ++++++++++++++++++++++++++++++ configs/khadas-vim_defconfig | 2 +- configs/libretech-cc_defconfig | 2 +- 17 files changed, 311 insertions(+), 491 deletions(-) delete mode 100644 board/amlogic/khadas-vim/Kconfig delete mode 100644 board/amlogic/khadas-vim/MAINTAINERS delete mode 100644 board/amlogic/khadas-vim/Makefile delete mode 100644 board/amlogic/khadas-vim/README delete mode 100644 board/amlogic/khadas-vim/khadas-vim.c delete mode 100644 board/amlogic/libretech-cc/Kconfig delete mode 100644 board/amlogic/libretech-cc/MAINTAINERS delete mode 100644 board/amlogic/libretech-cc/Makefile delete mode 100644 board/amlogic/libretech-cc/README delete mode 100644 board/amlogic/libretech-cc/libretech-cc.c delete mode 100644 board/amlogic/p212/README create mode 100644 board/amlogic/p212/README.khadas-vim create mode 100644 board/amlogic/p212/README.libretech-cc create mode 100644 board/amlogic/p212/README.p212 diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index bc0f6a1..e0b2812 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -47,22 +47,8 @@ config TARGET_P212 P212 is a reference dessign board based on Meson GXL S905X SoC with 2 GiB of RAM, Ethernet, HDMI, 2 USB, micro-SD slot, eMMC, IR receiver, CVBS+Audio jack and a SDIO WiFi module. - -config TARGET_LIBRETECH_CC - bool "LIBRETECH-CC" - select MESON_GXL - help - LibreTech CC is a single board computer based on Meson GXL - with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot, - eMMC, IR receiver and a 40-pin GPIO header. - -config TARGET_KHADAS_VIM - bool "KHADAS-VIM" - select MESON_GXL - help - Khadas VIM is a single board computer based on Meson GXL - with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot, - eMMC, IR receiver and a 40-pin GPIO header. + You should also select this TARGET if you have Khadas Vim or + a libretech aml-s905x-cc config TARGET_KHADAS_VIM2 bool "KHADAS-VIM2" @@ -86,10 +72,6 @@ source "board/amlogic/nanopi-k2/Kconfig" source "board/amlogic/p212/Kconfig" -source "board/amlogic/libretech-cc/Kconfig" - -source "board/amlogic/khadas-vim/Kconfig" - source "board/amlogic/khadas-vim2/Kconfig" endif diff --git a/board/amlogic/khadas-vim/Kconfig b/board/amlogic/khadas-vim/Kconfig deleted file mode 100644 index 0fa8db9..0000000 --- a/board/amlogic/khadas-vim/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_KHADAS_VIM - -config SYS_BOARD - default "khadas-vim" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "khadas-vim" - -endif diff --git a/board/amlogic/khadas-vim/MAINTAINERS b/board/amlogic/khadas-vim/MAINTAINERS deleted file mode 100644 index 024220a..0000000 --- a/board/amlogic/khadas-vim/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -KHADAS-VIM -M: Neil Armstrong -S: Maintained -F: board/amlogic/khadas-vim/ -F: include/configs/khadas-vim.h -F: configs/khadas-vim_defconfig diff --git a/board/amlogic/khadas-vim/Makefile b/board/amlogic/khadas-vim/Makefile deleted file mode 100644 index 558c076..0000000 --- a/board/amlogic/khadas-vim/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2016 BayLibre, SAS -# Author: Neil Armstrong - -obj-y := khadas-vim.o diff --git a/board/amlogic/khadas-vim/README b/board/amlogic/khadas-vim/README deleted file mode 100644 index b194236..0000000 --- a/board/amlogic/khadas-vim/README +++ /dev/null @@ -1,102 +0,0 @@ -U-Boot for Khadas VIM -======================= - -Khadas VIM is an Open Source DIY Box manufactured by Shenzhen Wesion -Technology Co., Ltd with the following specifications: - - - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - 10/100 Ethernet - - HDMI 2.0 4K/60Hz display - - 40-pin GPIO header - - 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG - - 8GB/16GBeMMC - - microSD - - SDIO Wifi Module, Bluetooth - - Two channels IR receiver - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -U-Boot compilation -================== - - > export ARCH=arm - > export CROSS_COMPILE=aarch64-none-elf- - > make khadas-vim_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/khadas/u-boot -b Vim vim-u-boot - > cd vim-u-boot - > make kvim_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxl/bl2.bin fip/ - > cp $FIPDIR/gxl/acs.bin fip/ - > cp $FIPDIR/gxl/bl21.bin fip/ - > cp $FIPDIR/gxl/bl30.bin fip/ - > cp $FIPDIR/gxl/bl301.bin fip/ - > cp $FIPDIR/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/khadas-vim/khadas-vim.c b/board/amlogic/khadas-vim/khadas-vim.c deleted file mode 100644 index 692bf2a..0000000 --- a/board/amlogic/khadas-vim/khadas-vim.c +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 BayLibre, SAS - * Author: Neil Armstrong - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define EFUSE_SN_OFFSET 20 -#define EFUSE_SN_SIZE 16 -#define EFUSE_MAC_OFFSET 52 -#define EFUSE_MAC_SIZE 6 - -int board_init(void) -{ - return 0; -} - -int misc_init_r(void) -{ - u8 mac_addr[EFUSE_MAC_SIZE]; - char serial[EFUSE_SN_SIZE]; - ssize_t len; - - meson_gx_eth_init(PHY_INTERFACE_MODE_RMII, - MESON_GXL_USE_INTERNAL_RMII_PHY); - - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { - len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, - mac_addr, EFUSE_MAC_SIZE); - if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) - eth_env_set_enetaddr("ethaddr", mac_addr); - } - - if (!env_get("serial#")) { - len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, - EFUSE_SN_SIZE); - if (len == EFUSE_SN_SIZE) - env_set("serial#", serial); - } - - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - meson_gx_init_reserved_memory(blob); - - return 0; -} diff --git a/board/amlogic/libretech-cc/Kconfig b/board/amlogic/libretech-cc/Kconfig deleted file mode 100644 index 7a6f916..0000000 --- a/board/amlogic/libretech-cc/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_LIBRETECH_CC - -config SYS_BOARD - default "libretech-cc" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "libretech-cc" - -endif diff --git a/board/amlogic/libretech-cc/MAINTAINERS b/board/amlogic/libretech-cc/MAINTAINERS deleted file mode 100644 index 398ce57..0000000 --- a/board/amlogic/libretech-cc/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -LIBRETECH-CC -M: Neil Armstrong -S: Maintained -F: board/amlogic/libretech-cc/ -F: include/configs/libretech-cc.h -F: configs/libretech-cc_defconfig diff --git a/board/amlogic/libretech-cc/Makefile b/board/amlogic/libretech-cc/Makefile deleted file mode 100644 index 3b0adf8..0000000 --- a/board/amlogic/libretech-cc/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2016 BayLibre, SAS -# Author: Neil Armstrong - -obj-y := libretech-cc.o diff --git a/board/amlogic/libretech-cc/README b/board/amlogic/libretech-cc/README deleted file mode 100644 index d007f58..0000000 --- a/board/amlogic/libretech-cc/README +++ /dev/null @@ -1,102 +0,0 @@ -U-Boot for LibreTech CC -======================= - -LibreTech CC is a single board computer manufactured by Libre Technology -with the following specifications: - - - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - 10/100 Ethernet - - HDMI 2.0 4K/60Hz display - - 40-pin GPIO header - - 4 x USB 2.0 Host - - eMMC, microSD - - Infrared receiver - -Schematics are available on the manufacturer website. - -Currently the U-Boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -U-Boot compilation -================== - - > export ARCH=arm - > export CROSS_COMPILE=aarch64-none-elf- - > make libretech-cc_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot - > cd amlogic-u-boot - > make libretech_cc_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxl/bl2.bin fip/ - > cp $FIPDIR/gxl/acs.bin fip/ - > cp $FIPDIR/gxl/bl21.bin fip/ - > cp $FIPDIR/gxl/bl30.bin fip/ - > cp $FIPDIR/gxl/bl301.bin fip/ - > cp $FIPDIR/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/libretech-cc/libretech-cc.c b/board/amlogic/libretech-cc/libretech-cc.c deleted file mode 100644 index ccab127..0000000 --- a/board/amlogic/libretech-cc/libretech-cc.c +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 BayLibre, SAS - * Author: Neil Armstrong - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define EFUSE_SN_OFFSET 20 -#define EFUSE_SN_SIZE 16 -#define EFUSE_MAC_OFFSET 52 -#define EFUSE_MAC_SIZE 6 - -int board_init(void) -{ - return 0; -} - -int misc_init_r(void) -{ - u8 mac_addr[EFUSE_MAC_SIZE]; - char serial[EFUSE_SN_SIZE]; - ssize_t len; - - meson_gx_eth_init(PHY_INTERFACE_MODE_RMII, - MESON_GXL_USE_INTERNAL_RMII_PHY); - - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { - len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, - mac_addr, EFUSE_MAC_SIZE); - if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) - eth_env_set_enetaddr("ethaddr", mac_addr); - } - - if (!env_get("serial#")) { - len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, - EFUSE_SN_SIZE); - if (len == EFUSE_SN_SIZE) - env_set("serial#", serial); - } - - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - meson_gx_init_reserved_memory(blob); - - return 0; -} diff --git a/board/amlogic/p212/README b/board/amlogic/p212/README deleted file mode 100644 index ef5370c..0000000 --- a/board/amlogic/p212/README +++ /dev/null @@ -1,103 +0,0 @@ -U-Boot for Amlogic P212 -======================= - -P212 is a reference board manufactured by Amlogic with the following -specifications: - - - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - 10/100 Ethernet - - HDMI 2.0 4K/60Hz display - - 2 x USB 2.0 Host - - eMMC, microSD - - Infrared receiver - - SDIO WiFi Module - - CVBS+Stereo Audio Jack - -Schematics are available from Amlogic on demand. - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -u-boot compilation -================== - - > export ARCH=arm - > export CROSS_COMPILE=aarch64-none-elf- - > make p212_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot - > cd amlogic-u-boot - > make gxl_p212_v1_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxl/bl2.bin fip/ - > cp $FIPDIR/gxl/acs.bin fip/ - > cp $FIPDIR/gxl/bl21.bin fip/ - > cp $FIPDIR/gxl/bl30.bin fip/ - > cp $FIPDIR/gxl/bl301.bin fip/ - > cp $FIPDIR/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/p212/README.khadas-vim b/board/amlogic/p212/README.khadas-vim new file mode 100644 index 0000000..b194236 --- /dev/null +++ b/board/amlogic/p212/README.khadas-vim @@ -0,0 +1,102 @@ +U-Boot for Khadas VIM +======================= + +Khadas VIM is an Open Source DIY Box manufactured by Shenzhen Wesion +Technology Co., Ltd with the following specifications: + + - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - 10/100 Ethernet + - HDMI 2.0 4K/60Hz display + - 40-pin GPIO header + - 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG + - 8GB/16GBeMMC + - microSD + - SDIO Wifi Module, Bluetooth + - Two channels IR receiver + +Currently the u-boot port supports the following devices: + - serial + - eMMC, microSD + - Ethernet + - I2C + - Regulators + - Reset controller + - Clock controller + - USB Host + - ADC + +U-Boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make khadas-vim_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + > git clone https://github.com/khadas/u-boot -b Vim vim-u-boot + > cd vim-u-boot + > make kvim_defconfig + > make + > export FIPDIR=$PWD/fip + +Go back to mainline U-Boot source tree then : + > mkdir fip + + > cp $FIPDIR/gxl/bl2.bin fip/ + > cp $FIPDIR/gxl/acs.bin fip/ + > cp $FIPDIR/gxl/bl21.bin fip/ + > cp $FIPDIR/gxl/bl30.bin fip/ + > cp $FIPDIR/gxl/bl301.bin fip/ + > cp $FIPDIR/gxl/bl31.img fip/ + > cp u-boot.bin fip/bl33.bin + + > $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + > $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/p212/README.libretech-cc b/board/amlogic/p212/README.libretech-cc new file mode 100644 index 0000000..d007f58 --- /dev/null +++ b/board/amlogic/p212/README.libretech-cc @@ -0,0 +1,102 @@ +U-Boot for LibreTech CC +======================= + +LibreTech CC is a single board computer manufactured by Libre Technology +with the following specifications: + + - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - 10/100 Ethernet + - HDMI 2.0 4K/60Hz display + - 40-pin GPIO header + - 4 x USB 2.0 Host + - eMMC, microSD + - Infrared receiver + +Schematics are available on the manufacturer website. + +Currently the U-Boot port supports the following devices: + - serial + - eMMC, microSD + - Ethernet + - I2C + - Regulators + - Reset controller + - Clock controller + - USB Host + - ADC + +U-Boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make libretech-cc_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + > git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot + > cd amlogic-u-boot + > make libretech_cc_defconfig + > make + > export FIPDIR=$PWD/fip + +Go back to mainline U-Boot source tree then : + > mkdir fip + + > cp $FIPDIR/gxl/bl2.bin fip/ + > cp $FIPDIR/gxl/acs.bin fip/ + > cp $FIPDIR/gxl/bl21.bin fip/ + > cp $FIPDIR/gxl/bl30.bin fip/ + > cp $FIPDIR/gxl/bl301.bin fip/ + > cp $FIPDIR/gxl/bl31.img fip/ + > cp u-boot.bin fip/bl33.bin + + > $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + > $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/p212/README.p212 b/board/amlogic/p212/README.p212 new file mode 100644 index 0000000..ef5370c --- /dev/null +++ b/board/amlogic/p212/README.p212 @@ -0,0 +1,103 @@ +U-Boot for Amlogic P212 +======================= + +P212 is a reference board manufactured by Amlogic with the following +specifications: + + - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - 10/100 Ethernet + - HDMI 2.0 4K/60Hz display + - 2 x USB 2.0 Host + - eMMC, microSD + - Infrared receiver + - SDIO WiFi Module + - CVBS+Stereo Audio Jack + +Schematics are available from Amlogic on demand. + +Currently the u-boot port supports the following devices: + - serial + - eMMC, microSD + - Ethernet + - I2C + - Regulators + - Reset controller + - Clock controller + - USB Host + - ADC + +u-boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make p212_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot + > cd amlogic-u-boot + > make gxl_p212_v1_defconfig + > make + > export FIPDIR=$PWD/fip + +Go back to mainline U-boot source tree then : + > mkdir fip + + > cp $FIPDIR/gxl/bl2.bin fip/ + > cp $FIPDIR/gxl/acs.bin fip/ + > cp $FIPDIR/gxl/bl21.bin fip/ + > cp $FIPDIR/gxl/bl30.bin fip/ + > cp $FIPDIR/gxl/bl301.bin fip/ + > cp $FIPDIR/gxl/bl31.img fip/ + > cp u-boot.bin fip/bl33.bin + + > $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + > $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig index 0c89d9a..af30113 100644 --- a/configs/khadas-vim_defconfig +++ b/configs/khadas-vim_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_MESON_GXL=y -CONFIG_TARGET_KHADAS_VIM=y +CONFIG_TARGET_P212=y CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" khadas-vim" diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig index 36d117c..7526516 100644 --- a/configs/libretech-cc_defconfig +++ b/configs/libretech-cc_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_MESON_GXL=y -CONFIG_TARGET_LIBRETECH_CC=y +CONFIG_TARGET_P212=y CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" libretech-cc" From patchwork Fri Nov 9 15:26:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 150666 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp82544ljp; Fri, 9 Nov 2018 07:29:46 -0800 (PST) X-Google-Smtp-Source: AJdET5ffNSEJ2ePvDE721OaH9MlstdqdedMMnlR3A7jbdHIoLnhCdZQV2/yIhrx0aZ28EtL5eQhU X-Received: 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This change use odroid-c2 u-boot board for the nanopi-k2 as well. Dedicated defconfig are kept to customize the names and device tree. Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- arch/arm/mach-meson/Kconfig | 11 +--- board/amlogic/nanopi-k2/Kconfig | 12 ---- board/amlogic/nanopi-k2/MAINTAINERS | 6 -- board/amlogic/nanopi-k2/Makefile | 7 --- board/amlogic/nanopi-k2/README | 99 -------------------------------- board/amlogic/nanopi-k2/nanopi-k2.c | 55 ------------------ board/amlogic/odroid-c2/MAINTAINERS | 1 + board/amlogic/odroid-c2/README | 66 --------------------- board/amlogic/odroid-c2/README.nanopi-k2 | 99 ++++++++++++++++++++++++++++++++ board/amlogic/odroid-c2/README.odroid-c2 | 66 +++++++++++++++++++++ configs/nanopi-k2_defconfig | 2 +- 11 files changed, 168 insertions(+), 256 deletions(-) delete mode 100644 board/amlogic/nanopi-k2/Kconfig delete mode 100644 board/amlogic/nanopi-k2/MAINTAINERS delete mode 100644 board/amlogic/nanopi-k2/Makefile delete mode 100644 board/amlogic/nanopi-k2/README delete mode 100644 board/amlogic/nanopi-k2/nanopi-k2.c delete mode 100644 board/amlogic/odroid-c2/README create mode 100644 board/amlogic/odroid-c2/README.nanopi-k2 create mode 100644 board/amlogic/odroid-c2/README.odroid-c2 diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 98303db..d86b1be 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -31,14 +31,7 @@ config TARGET_ODROID_C2 ODROID-C2 is a single board computer based on Meson GXBaby with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD slot, eMMC, IR receiver and a 40-pin GPIO header. - -config TARGET_NANOPI_K2 - bool "NANOPI_K2" - select MESON_GXBB - help - NANOPI_K2 is a single board computer based on Meson GXBaby - with 2 GiB of RAM, Gigabit Ethernet,AP6212 Wifi, HDMI, 4 USB, - micro-SD slot, eMMC, IR receiver and a 40-pin GPIO header. + You should also select this TARGET if you have an nanopi-k2 config TARGET_P212 bool "P212" @@ -69,8 +62,6 @@ config SYS_MALLOC_F_LEN source "board/amlogic/odroid-c2/Kconfig" -source "board/amlogic/nanopi-k2/Kconfig" - source "board/amlogic/p212/Kconfig" source "board/amlogic/q200/Kconfig" diff --git a/board/amlogic/nanopi-k2/Kconfig b/board/amlogic/nanopi-k2/Kconfig deleted file mode 100644 index 374bda2..0000000 --- a/board/amlogic/nanopi-k2/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_NANOPI_K2 - -config SYS_BOARD - default "nanopi-k2" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "nanopi-k2" - -endif diff --git a/board/amlogic/nanopi-k2/MAINTAINERS b/board/amlogic/nanopi-k2/MAINTAINERS deleted file mode 100644 index 0452bd1..0000000 --- a/board/amlogic/nanopi-k2/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -NANOPI-K2 -M: Neil Armstrong -S: Maintained -F: board/amlogic/nanopi-k2/ -F: include/configs/nanopi-k2.h -F: configs/nanopi-k2_defconfig diff --git a/board/amlogic/nanopi-k2/Makefile b/board/amlogic/nanopi-k2/Makefile deleted file mode 100644 index 7d9b666..0000000 --- a/board/amlogic/nanopi-k2/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2018 Thomas McKahan -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := nanopi-k2.o diff --git a/board/amlogic/nanopi-k2/README b/board/amlogic/nanopi-k2/README deleted file mode 100644 index d450d3c..0000000 --- a/board/amlogic/nanopi-k2/README +++ /dev/null @@ -1,99 +0,0 @@ -U-Boot for NanoPi-K2 -==================== - -NanoPi-K2 is a single board computer manufactured by FriendlyElec -with the following specifications: - - - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - Gigabit Ethernet - - HDMI 2.0 4K/60Hz display - - 40-pin GPIO header - - 4 x USB 2.0 Host, 1 x USB OTG - - eMMC, microSD - - Infrared receiver - -Schematics are available on the manufacturer website. - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - -u-boot compilation -================== - - > export ARCH=arm - > export CROSS_COMPILE=aarch64-none-elf- - > make nanopi-k2_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot - > git clone https://github.com/friendlyarm/u-boot.git -b nanopi-k2-v2015.01 amlogic-u-boot - > cd amlogic-u-boot - > sed -i 's/aarch64-linux-gnu-/aarch64-none-elf-/' Makefile - > sed -i 's/arm-linux-/arm-none-eabi-/' arch/arm/cpu/armv8/gxb/firmware/scp_task/Makefile - > make nanopi-k2_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxb/bl2.bin fip/ - > cp $FIPDIR/gxb/acs.bin fip/ - > cp $FIPDIR/gxb/bl21.bin fip/ - > cp $FIPDIR/gxb/bl30.bin fip/ - > cp $FIPDIR/gxb/bl301.bin fip/ - > cp $FIPDIR/gxb/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > $FIPDIR/fip_create \ - --bl30 fip/bl30_new.bin \ - --bl31 fip/bl31.img \ - --bl33 fip/bl33.bin \ - fip/fip.bin - - > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin - - > $FIPDIR/gxb/aml_encrypt_gxb --bootsig \ - --input fip/boot_new.bin - --output fip/u-boot.bin - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin of=$DEV conv=fsync,notrunc bs=512 seek=1 diff --git a/board/amlogic/nanopi-k2/nanopi-k2.c b/board/amlogic/nanopi-k2/nanopi-k2.c deleted file mode 100644 index ae29dd6..0000000 --- a/board/amlogic/nanopi-k2/nanopi-k2.c +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2018 Thomas McKahan - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define EFUSE_SN_OFFSET 20 -#define EFUSE_SN_SIZE 16 -#define EFUSE_MAC_OFFSET 52 -#define EFUSE_MAC_SIZE 6 - -int board_init(void) -{ - return 0; -} - -int misc_init_r(void) -{ - u8 mac_addr[EFUSE_MAC_SIZE]; - char serial[EFUSE_SN_SIZE]; - ssize_t len; - - meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0); - - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { - len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, - mac_addr, EFUSE_MAC_SIZE); - if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) - eth_env_set_enetaddr("ethaddr", mac_addr); - } - - if (!env_get("serial#")) { - len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, - EFUSE_SN_SIZE); - if (len == EFUSE_SN_SIZE) - env_set("serial#", serial); - } - - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - meson_gx_init_reserved_memory(blob); - - return 0; -} diff --git a/board/amlogic/odroid-c2/MAINTAINERS b/board/amlogic/odroid-c2/MAINTAINERS index 699850f..fd74d53 100644 --- a/board/amlogic/odroid-c2/MAINTAINERS +++ b/board/amlogic/odroid-c2/MAINTAINERS @@ -1,5 +1,6 @@ ODROID-C2 M: Beniamino Galvani +M: Neil Armstrong S: Maintained F: board/amlogic/odroid-c2/ F: include/configs/odroid-c2.h diff --git a/board/amlogic/odroid-c2/README b/board/amlogic/odroid-c2/README deleted file mode 100644 index bed48c5..0000000 --- a/board/amlogic/odroid-c2/README +++ /dev/null @@ -1,66 +0,0 @@ -U-Boot for ODROID-C2 -==================== - -ODROID-C2 is a single board computer manufactured by Hardkernel -Co. Ltd with the following specifications: - - - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - Gigabit Ethernet - - HDMI 2.0 4K/60Hz display - - 40-pin GPIO header - - 4 x USB 2.0 Host, 1 x USB OTG - - eMMC, microSD - - Infrared receiver - -Schematics are available on the manufacturer website. - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - ADC - -u-boot compilation -================== - - > export ARCH=arm - > export CROSS_COMPILE=aarch64-none-elf- - > make odroid-c2_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > DIR=odroid-c2 - > git clone --depth 1 \ - https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \ - $DIR - > $DIR/fip/fip_create --bl30 $DIR/fip/gxb/bl30.bin \ - --bl301 $DIR/fip/gxb/bl301.bin \ - --bl31 $DIR/fip/gxb/bl31.bin \ - --bl33 u-boot.bin \ - $DIR/fip.bin - > $DIR/fip/fip_create --dump $DIR/fip.bin - > cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin - > $DIR/fip/gxb/aml_encrypt_gxb --bootsig \ - --input $DIR/boot_new.bin \ - --output $DIR/u-boot.img - > dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > BL1=$DIR/sd_fuse/bl1.bin.hardkernel - > dd if=$BL1 of=$DEV conv=fsync bs=1 count=442 - > dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1 - > dd if=$DIR/u-boot.gxbb of=$DEV conv=fsync bs=512 seek=97 diff --git a/board/amlogic/odroid-c2/README.nanopi-k2 b/board/amlogic/odroid-c2/README.nanopi-k2 new file mode 100644 index 0000000..d450d3c --- /dev/null +++ b/board/amlogic/odroid-c2/README.nanopi-k2 @@ -0,0 +1,99 @@ +U-Boot for NanoPi-K2 +==================== + +NanoPi-K2 is a single board computer manufactured by FriendlyElec +with the following specifications: + + - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - Gigabit Ethernet + - HDMI 2.0 4K/60Hz display + - 40-pin GPIO header + - 4 x USB 2.0 Host, 1 x USB OTG + - eMMC, microSD + - Infrared receiver + +Schematics are available on the manufacturer website. + +Currently the u-boot port supports the following devices: + - serial + - eMMC, microSD + - Ethernet + +u-boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make nanopi-k2_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + > git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot + > git clone https://github.com/friendlyarm/u-boot.git -b nanopi-k2-v2015.01 amlogic-u-boot + > cd amlogic-u-boot + > sed -i 's/aarch64-linux-gnu-/aarch64-none-elf-/' Makefile + > sed -i 's/arm-linux-/arm-none-eabi-/' arch/arm/cpu/armv8/gxb/firmware/scp_task/Makefile + > make nanopi-k2_defconfig + > make + > export FIPDIR=$PWD/fip + +Go back to mainline U-Boot source tree then : + > mkdir fip + + > cp $FIPDIR/gxb/bl2.bin fip/ + > cp $FIPDIR/gxb/acs.bin fip/ + > cp $FIPDIR/gxb/bl21.bin fip/ + > cp $FIPDIR/gxb/bl30.bin fip/ + > cp $FIPDIR/gxb/bl301.bin fip/ + > cp $FIPDIR/gxb/bl31.img fip/ + > cp u-boot.bin fip/bl33.bin + + > $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > $FIPDIR/fip_create \ + --bl30 fip/bl30_new.bin \ + --bl31 fip/bl31.img \ + --bl33 fip/bl33.bin \ + fip/fip.bin + + > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + > $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin + + > $FIPDIR/gxb/aml_encrypt_gxb --bootsig \ + --input fip/boot_new.bin + --output fip/u-boot.bin + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin of=$DEV conv=fsync,notrunc bs=512 seek=1 diff --git a/board/amlogic/odroid-c2/README.odroid-c2 b/board/amlogic/odroid-c2/README.odroid-c2 new file mode 100644 index 0000000..bed48c5 --- /dev/null +++ b/board/amlogic/odroid-c2/README.odroid-c2 @@ -0,0 +1,66 @@ +U-Boot for ODROID-C2 +==================== + +ODROID-C2 is a single board computer manufactured by Hardkernel +Co. Ltd with the following specifications: + + - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - Gigabit Ethernet + - HDMI 2.0 4K/60Hz display + - 40-pin GPIO header + - 4 x USB 2.0 Host, 1 x USB OTG + - eMMC, microSD + - Infrared receiver + +Schematics are available on the manufacturer website. + +Currently the u-boot port supports the following devices: + - serial + - eMMC, microSD + - Ethernet + - I2C + - Regulators + - Reset controller + - Clock controller + - ADC + +u-boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make odroid-c2_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > DIR=odroid-c2 + > git clone --depth 1 \ + https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \ + $DIR + > $DIR/fip/fip_create --bl30 $DIR/fip/gxb/bl30.bin \ + --bl301 $DIR/fip/gxb/bl301.bin \ + --bl31 $DIR/fip/gxb/bl31.bin \ + --bl33 u-boot.bin \ + $DIR/fip.bin + > $DIR/fip/fip_create --dump $DIR/fip.bin + > cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin + > $DIR/fip/gxb/aml_encrypt_gxb --bootsig \ + --input $DIR/boot_new.bin \ + --output $DIR/u-boot.img + > dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96 + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > BL1=$DIR/sd_fuse/bl1.bin.hardkernel + > dd if=$BL1 of=$DEV conv=fsync bs=1 count=442 + > dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1 + > dd if=$DIR/u-boot.gxbb of=$DEV conv=fsync bs=512 seek=97 diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig index 5c8c747..01196d6 100644 --- a/configs/nanopi-k2_defconfig +++ b/configs/nanopi-k2_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_MESON_GXBB=y -CONFIG_TARGET_NANOPI_K2=y +CONFIG_TARGET_ODROID_C2=y CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" nanopi-k2" From patchwork Fri Nov 9 15:26:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 150667 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp84222ljp; Fri, 9 Nov 2018 07:31:08 -0800 (PST) X-Google-Smtp-Source: AJdET5dhms8UXePPETJ4DDLW5NKiM6ch1yD2OwMyIdI4M0ianrqNRWMB+c3DKh8SHPVZ8eAB1EPG X-Received: by 2002:a50:9f83:: with SMTP id c3mr2179402edf.33.1541777468029; Fri, 09 Nov 2018 07:31:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541777468; cv=none; d=google.com; s=arc-20160816; b=0FXpomF7coJXX0i4DZYGkxKl7tiPhuXEDj6DpBMPd1XqIqPdM0MuJF8YUsFSah5b50 e3UtTQFT5j4M/0G77L3cMcLDBVvSTetRUeqJasLNxFmfh3DyF3L1qtEo+r2uGy8CpH/4 vt7VBwzuFkv5n83CDFVvhpUD8/AUNckB85A0UYeyMEQFU8oUmr1PWJyPWQ/IEYMw3XNu Kymyq5jk+UzHMDSchLw7jIdA5MJMsvaBFeDZk66H5bWxcCIOEx//RpvmZ2AroaC5EE9y Rc/sevmkJ24y+Qr7WOT8QsBr5R0Z5VkpXy610WyfpCGx/itTzwcyqOr/GRDqh2KZDLdj DzVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature; bh=6SsPbIoC6aJlgv+5Ap5uV4JKo2y7fI8pCmM8OzYJ68Y=; b=oSQlU+1BTIK9XMwrcOXNB7LeU9XLWXvrfzTEBgHQ+/U95vGyBAu+SkjIIMhsgPbkWr xWu/UfYOvq3I7zJFXB+HhmdzGF2Z6aYZmlCnF41iXIE4SvrguXL3uc7hZap2F6EywTNG 0kw61rstXfyHl8g7OoVzSiaLQDVDag3OllyraxKFhpCkECyUZevHI0Kl3SH+ePZC+y5J f8hlmMqthDI847FwABf40awHRc366QSfCI7AECmzkGSx432bAbD5EvKXpAy0JyhurZz4 jZJuMlK0ut4NS+6jy0W+4a3zCnIs41Xfg8uSeX5T0m3/Mp3uhbGqVE83l2twCU1qXNSy Egbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=ev3s4KJh; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id gu17-v6si3261506ejb.36.2018.11.09.07.31.07; Fri, 09 Nov 2018 07:31:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=ev3s4KJh; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 7FA26C22598; Fri, 9 Nov 2018 15:30:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CFAC0C225AF; Fri, 9 Nov 2018 15:27:21 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 526FBC2257F; Fri, 9 Nov 2018 15:27:14 +0000 (UTC) Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by lists.denx.de (Postfix) with ESMTPS id 71C66C22596 for ; Fri, 9 Nov 2018 15:27:07 +0000 (UTC) Received: by mail-wm1-f66.google.com with SMTP id t15-v6so2315758wmt.0 for ; Fri, 09 Nov 2018 07:27:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=s2K9xcxTcusoPv4GxG1EjjPgt+GGAhkSta3/nCmk+RI=; b=ev3s4KJh4WvFxABtSX8V05zJ7Twy+rsspNeEI8O81boCWFjT8ovlE7YHe95RNxdv6Z hp2KaURfLEJoSJJJO9Ljfhto6We8f/v3tCHAoz7PtRxVugMaJnYCasYizeNMNHeGGcyb yEOvkcJNP6S9JNpFJreu2+so2EWHy/Ri1D2VT5aba5xjTqF7rpKCUPyCv95TRnxJYmEQ LtqVl0FQtD7GDkOUpAf3H0cZtVxZA1TRdfKuGy2Ucvw/+lNZSUuisAd6Pt60ZY9x7dDd KtIEvoWdWrnssh+3ZTkzxl+oq4ACrLUk6YcSNonoxIGqx9SytU3DGr1ZT6OSC+I/nCeB pRNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=s2K9xcxTcusoPv4GxG1EjjPgt+GGAhkSta3/nCmk+RI=; b=R5yAGaHJj0K9kRt4LzovxUDRgmuS2dhP/mLghusXlPrk5jvFvXzdoVwJqQuVMB8ePL rpG00MAipAVvLii6SlL0NAmoePvxBhA9iVFf5CBYvdxzPHK0DoTp0ocp8mV8TNXD0nj1 ycnZvU2fuFMkeNld3TIr/gcto45NnGz1VFdPsIVbaCKJ8XctunmTblHXtGNofqLvos1b 2cDT/F+q+Vg8/Gkxie9vui/M5/AFelAhbMAVhwyGyelZBnSDLES182poyfmXrhWE1YaB jmJkBtWlDEt87FByzYgmJrUj+3PfMgmTJcC6+Sbdi6Ecv4gLS4O17cy3CGWFBDxgJrjw YWCg== X-Gm-Message-State: AGRZ1gLqeZAKJtAI2Zud4JHF+cBy17++nTHOIEyY5CZQwFmDJ2TZ+Gq9 cN+6nsYD63/1P9q2G5AT0GkPgaykMsU= X-Received: by 2002:a1c:ce0e:: with SMTP id e14-v6mr4943343wmg.45.1541777226580; Fri, 09 Nov 2018 07:27:06 -0800 (PST) Received: from bender.baylibre.local ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id a127-v6sm1748545wmh.24.2018.11.09.07.27.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Nov 2018 07:27:06 -0800 (PST) From: Neil Armstrong To: u-boot@lists.denx.de Date: Fri, 9 Nov 2018 16:26:45 +0100 Message-Id: <1541777218-472-7-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1541777218-472-1-git-send-email-narmstrong@baylibre.com> References: <1541777218-472-1-git-send-email-narmstrong@baylibre.com> Cc: linux-amlogic@lists.infradead.org, trini@konsulko.com, Jerome Brunet Subject: [U-Boot] [PATCH u-boot 06/19] ARM: rework amlogic configuration X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jerome Brunet Rework the board SYS_BOARD, SYS_VENDOR and SYS_CONFIG_NAME setup by moving the board Kconfig into the mach-meson Kconfig to make it easier to add new boards for a SoC architecture and add a custom config header or custom board handler for a platform. This drops the board CONFIGs and the duplicate boards configs headers in favor of a single meson64.h config header. Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- arch/arm/mach-meson/Kconfig | 75 +++++++++++++++++++-------------------- board/amlogic/odroid-c2/Kconfig | 12 ------- board/amlogic/p212/Kconfig | 12 ------- board/amlogic/q200/Kconfig | 12 ------- configs/khadas-vim2_defconfig | 1 - configs/khadas-vim_defconfig | 1 - configs/libretech-cc_defconfig | 1 - configs/nanopi-k2_defconfig | 2 -- configs/odroid-c2_defconfig | 1 - configs/p212_defconfig | 1 - include/configs/khadas-vim.h | 14 -------- include/configs/libretech-cc.h | 14 -------- include/configs/meson-gx-common.h | 52 --------------------------- include/configs/meson64.h | 55 ++++++++++++++++++++++++++++ include/configs/nanopi-k2.h | 12 ------- include/configs/odroid-c2.h | 12 ------- include/configs/p212.h | 14 -------- include/configs/q200.h | 18 ---------- 18 files changed, 92 insertions(+), 217 deletions(-) delete mode 100644 board/amlogic/odroid-c2/Kconfig delete mode 100644 board/amlogic/p212/Kconfig delete mode 100644 board/amlogic/q200/Kconfig delete mode 100644 include/configs/khadas-vim.h delete mode 100644 include/configs/libretech-cc.h delete mode 100644 include/configs/meson-gx-common.h create mode 100644 include/configs/meson64.h delete mode 100644 include/configs/nanopi-k2.h delete mode 100644 include/configs/odroid-c2.h delete mode 100644 include/configs/p212.h delete mode 100644 include/configs/q200.h diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index d86b1be..6f60167 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -8,49 +8,27 @@ config MESON64_COMMON select DM_SERIAL imply CMD_DM -config MESON_GXBB - bool - select MESON64_COMMON - -config MESON_GXL - bool - select MESON64_COMMON - -config MESON_GXM - bool - select MESON64_COMMON - choice prompt "Platform select" - default TARGET_ODROID_C2 + default MESON_GXBB -config TARGET_ODROID_C2 - bool "ODROID-C2" - select MESON_GXBB +config MESON_GXBB + bool "GXBB" + select MESON64_COMMON help - ODROID-C2 is a single board computer based on Meson GXBaby - with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD - slot, eMMC, IR receiver and a 40-pin GPIO header. - You should also select this TARGET if you have an nanopi-k2 + Select this if your SoC is an S905 -config TARGET_P212 - bool "P212" - select MESON_GXL +config MESON_GXL + bool "GXL" + select MESON64_COMMON help - P212 is a reference dessign board based on Meson GXL S905X SoC - with 2 GiB of RAM, Ethernet, HDMI, 2 USB, micro-SD slot, - eMMC, IR receiver, CVBS+Audio jack and a SDIO WiFi module. - You should also select this TARGET if you have Khadas Vim or - a libretech aml-s905x-cc + Select this if your SoC is an S905X/D or S805X -config TARGET_Q200 - bool "KHADAS-VIM2" - select MESON_GXM +config MESON_GXM + bool "GXM" + select MESON64_COMMON help - Q200 is a reference dessign board based on Meson GXM - with 2/3 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot, - eMMC, IR receiver. - You should also select this TARGET if you have Khadas Vim2. + Select this if your SoC is an S912 endchoice @@ -60,10 +38,31 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x1000 -source "board/amlogic/odroid-c2/Kconfig" +config SYS_VENDOR + string "Vendor name" + default "amlogic" + help + This option contains information about board name. + Based on this option board// will + be used. -source "board/amlogic/p212/Kconfig" +config SYS_BOARD + string "Board name" + default "odroid-c2" if MESON_GXBB + default "p212" if MESON_GXL + default "q200" if MESON_GXM + default "" + help + This option contains information about board name. + Based on this option board// will + be used. -source "board/amlogic/q200/Kconfig" +config SYS_CONFIG_NAME + string "Board configuration name" + default "meson64" + help + This option contains information about board configuration name. + Based on this option include/configs/.h header + will be used for board configuration. endif diff --git a/board/amlogic/odroid-c2/Kconfig b/board/amlogic/odroid-c2/Kconfig deleted file mode 100644 index 2b16889..0000000 --- a/board/amlogic/odroid-c2/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ODROID_C2 - -config SYS_BOARD - default "odroid-c2" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "odroid-c2" - -endif diff --git a/board/amlogic/p212/Kconfig b/board/amlogic/p212/Kconfig deleted file mode 100644 index 720c92b..0000000 --- a/board/amlogic/p212/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_P212 - -config SYS_BOARD - default "p212" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "p212" - -endif diff --git a/board/amlogic/q200/Kconfig b/board/amlogic/q200/Kconfig deleted file mode 100644 index cfaf379..0000000 --- a/board/amlogic/q200/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_Q200 - -config SYS_BOARD - default "q200" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "q200" - -endif diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig index 387d7da..40e7cac 100644 --- a/configs/khadas-vim2_defconfig +++ b/configs/khadas-vim2_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_MESON_GXM=y -CONFIG_TARGET_Q200=y CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" khadas-vim2" diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig index af30113..6e855dd 100644 --- a/configs/khadas-vim_defconfig +++ b/configs/khadas-vim_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_MESON_GXL=y -CONFIG_TARGET_P212=y CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" khadas-vim" diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig index 7526516..c2f985f 100644 --- a/configs/libretech-cc_defconfig +++ b/configs/libretech-cc_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_MESON_GXL=y -CONFIG_TARGET_P212=y CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" libretech-cc" diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig index 01196d6..8bbf48f 100644 --- a/configs/nanopi-k2_defconfig +++ b/configs/nanopi-k2_defconfig @@ -1,8 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x01000000 -CONFIG_MESON_GXBB=y -CONFIG_TARGET_ODROID_C2=y CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" nanopi-k2" diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig index 19196b3..68554ba 100644 --- a/configs/odroid-c2_defconfig +++ b/configs/odroid-c2_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_MESON_GXBB=y -CONFIG_TARGET_ODROID_C2=y CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" odroid-c2" diff --git a/configs/p212_defconfig b/configs/p212_defconfig index 9e3b1d6..a15064d 100644 --- a/configs/p212_defconfig +++ b/configs/p212_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_MESON_GXL=y -CONFIG_TARGET_P212=y CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" p212" diff --git a/include/configs/khadas-vim.h b/include/configs/khadas-vim.h deleted file mode 100644 index ff87c02..0000000 --- a/include/configs/khadas-vim.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Khadas VIM - * - * Copyright (C) 2017 Baylibre, SAS - * Author: Neil Armstrong - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/libretech-cc.h b/include/configs/libretech-cc.h deleted file mode 100644 index 95e0f34..0000000 --- a/include/configs/libretech-cc.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for LibreTech CC - * - * Copyright (C) 2017 Baylibre, SAS - * Author: Neil Armstrong - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/meson-gx-common.h b/include/configs/meson-gx-common.h deleted file mode 100644 index c436976..0000000 --- a/include/configs/meson-gx-common.h +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Amlogic Meson GX SoCs - * (C) Copyright 2016 Beniamino Galvani - */ - -#ifndef __MESON_GX_COMMON_CONFIG_H -#define __MESON_GX_COMMON_CONFIG_H - -#define CONFIG_CPU_ARMV8 -#define CONFIG_REMAKE_ELF -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) -#define CONFIG_SYS_CBSIZE 1024 - -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_INIT_SP_ADDR 0x20000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE - -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0xc4301000 -#define GICC_BASE 0xc4302000 - -#ifdef CONFIG_CMD_USB -#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) -#else -#define BOOT_TARGET_DEVICES_USB(func) -#endif - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 2) \ - BOOT_TARGET_DEVICES_USB(func) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_addr_r=0x01000000\0" \ - "scriptaddr=0x1f000000\0" \ - "kernel_addr_r=0x01080000\0" \ - "pxefile_addr_r=0x01080000\0" \ - "ramdisk_addr_r=0x13000000\0" \ - "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ - BOOTENV - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */ - -#endif /* __MESON_GX_COMMON_CONFIG_H */ diff --git a/include/configs/meson64.h b/include/configs/meson64.h new file mode 100644 index 0000000..1929a3e --- /dev/null +++ b/include/configs/meson64.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for Amlogic Meson 64bits SoCs + * (C) Copyright 2016 Beniamino Galvani + */ + +#ifndef __MESON64_CONFIG_H +#define __MESON64_CONFIG_H + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0xc4301000 +#define GICC_BASE 0xc4302000 + +#define CONFIG_CPU_ARMV8 +#define CONFIG_REMAKE_ELF +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 + +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_INIT_SP_ADDR 0x20000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */ + +#ifdef CONFIG_CMD_USB +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + +#ifndef BOOT_TARGET_DEVICES +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + BOOT_TARGET_DEVICES_USB(func) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) +#endif + +#ifndef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr_r=0x01000000\0" \ + "scriptaddr=0x1f000000\0" \ + "kernel_addr_r=0x01080000\0" \ + "pxefile_addr_r=0x01080000\0" \ + "ramdisk_addr_r=0x13000000\0" \ + "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + BOOTENV +#endif + +#include + +#endif /* __MESON64_CONFIG_H */ diff --git a/include/configs/nanopi-k2.h b/include/configs/nanopi-k2.h deleted file mode 100644 index 3fd6e8f..0000000 --- a/include/configs/nanopi-k2.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for NANOPI-K2 - * (C) Copyright 2018 Thomas McKahan - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h deleted file mode 100644 index 87e3ddb..0000000 --- a/include/configs/odroid-c2.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for ODROID-C2 - * (C) Copyright 2016 Beniamino Galvani - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/p212.h b/include/configs/p212.h deleted file mode 100644 index 4414293..0000000 --- a/include/configs/p212.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Amlogic P212 - * - * Copyright (C) 2017 Baylibre, SAS - * Author: Neil Armstrong - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/q200.h b/include/configs/q200.h deleted file mode 100644 index 7ef8f42..0000000 --- a/include/configs/q200.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Khadas VIM2 - * - * Copyright (C) 2017 Baylibre, SAS - * Author: Neil Armstrong - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MISC_INIT_R - -#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxm-khadas-vim2.dtb\0" - -#include - -#endif /* __CONFIG_H */ From patchwork Fri Nov 9 15:26:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 150669 Delivered-To: patch@linaro.org Received: by 2002:aa7:da0f:0:0:0:0:0 with SMTP id r15csp376517eds; Fri, 9 Nov 2018 07:34:02 -0800 (PST) X-Google-Smtp-Source: AJdET5f+7VMe29Hi70kq+u9b+SLhjth9cwm4S4hxZO2n38mi0+XYl2HYSOh2y+S86C5dbP0UmIVY X-Received: by 2002:a50:b2e1:: with SMTP id p88-v6mr2735230edd.155.1541777642456; Fri, 09 Nov 2018 07:34:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541777642; cv=none; d=google.com; s=arc-20160816; b=ogmExAIapLQHnd+7cZ1N7s5dKemiCbrhSpE9bExHIQEZ4JOxdkFAciHs1U/dxyRRWI 6RQzzAiQJdJRqcPpX4qQprSKLQAFZ+00wGuBulXmAbtwO7VHPwCK2HUfs4L7+mL6I3+9 a5dv8OrQwITtZZxNjWi8ScmsubPVH/jmpahsjQoGHLvMrOFEZwXNCdoJMUJZVEd+lVzo b+Q6pFEy+RKLlDkaWkmyiDUrTtr6ZsbF+xDj0Z0xJnCrAE4x157AB0O1E9g0GAeewEXR sE7DxJlOE79wkxE6rAef74xf4WyJVILkf6vqX2ok2kbcO0/1feXafAQ7lBschxcybUsh tMDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature; bh=3/Vk4ZYMm0XZw6UdKzbRo6JKYM1L/NWdhvbURix+WVs=; b=VUXI0zfxhCYaUWW4ZKrdtyZUTVBZOb5Lc4JPetZoZxr8gNC2TjqOV3c6CsEL+Wnh/T olYmkjUYng/yXyhRz/th4bw2nEu45gyXfjqrrN8IZJ5VWtyBVQOjl5FuPfzrh4bIVqpW maiWIX7J/jh2h0ogIDlo4iUJw670OaEewIUwFjsHC/QHaoF1/+khZQfAaXgIwD9zrDCl t5kmafcOt219WrFzwP5qmVhgi3/STsamxzewEtu/v0mXFRYBtzf0yufEMGMQLFKDRIqB FDbJXjiVyNJsQTA1MCVl5X8H4w/P80DkMP1ppWnqEQOlP9IbwqavT0/hmOKbNNkwhgt6 Eq0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=GkDMlsMY; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id r1-v6si4025136edq.38.2018.11.09.07.33.52; Fri, 09 Nov 2018 07:34:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=GkDMlsMY; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 3A6B3C2210B; Fri, 9 Nov 2018 15:32:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 882FFC225B0; Fri, 9 Nov 2018 15:27:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 77E2EC2259B; Fri, 9 Nov 2018 15:27:14 +0000 (UTC) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by lists.denx.de (Postfix) with ESMTPS id 8C742C2259E for ; Fri, 9 Nov 2018 15:27:08 +0000 (UTC) Received: by mail-wr1-f67.google.com with SMTP id u9-v6so2333524wrr.0 for ; Fri, 09 Nov 2018 07:27:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4G4jhZ4NPrqD9z35EA3JgHI7ZuEmf+o7iVAHKLkoJTg=; b=GkDMlsMYiIh/H10hgbrnKMu5kqd3F87IRsP6kIJt3GsP/2jGtZEiaSNTyxEnpG3IGK 5qq+6YFsH7q94PUs2cOn5o3IOilkbvF2iDYwDhOfXCd8p7J1Suk9V5sbQHvIxanprfwR NAVMrmaDMNwapbkObgHEZq0OkNQbJqDy2OBg5FsTHWqkNgeZFwO3H27dzcVdoEGvN2g3 IFYAsOScd47HDNIK68k8MGjBc+YP1pc8oMsaJqKMDP01ptlKvlEmecky8MuvAL4g7njr kB2QivG/6+z5vehhJHclS+PJUlaH8RP0NYc89yHsDGnVI80m6vlZdgnniTba7nRXhx2r yR+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4G4jhZ4NPrqD9z35EA3JgHI7ZuEmf+o7iVAHKLkoJTg=; b=PmjueSgJEgj5Ul3RBDRNKydCmcSs0eO9cw9PR6JBDfsgY/+sgQ9nMNX6lN0yrVqZGa aURHGLJUiUAe6TeYDTLk5fWmxMXWWCXZbdSSZ/BSyAZkSkt5DKWW4e48+dT7//9+phVA RNlTas339EsGL5hLqJywBicn5xqo+MoojE2aWYdP3JP7nmpBwqs2FId74Aq/4+9MMdge 2WqXGr/BGfyNCfgvm3/YzlIAlR9vgdCczFRPuKoLhSosw3dgO+pZ4fZQMJgq8eI40S41 A32WJ2A33620cqtyacNxxTIGLR1Q2uAj85ghxlrS7+lKgnNOO9WAcxOONEKKmv8w4ctX o8LA== X-Gm-Message-State: AGRZ1gIqMEMfic+tAMuUh9rzl+xMYOvy93HE2MZ9teMke2/xbfp26YXm XvK8Gj7XbwltzY2kYF1R5VO5MeP4ULo= X-Received: by 2002:adf:c752:: with SMTP id b18-v6mr7810283wrh.197.1541777227927; Fri, 09 Nov 2018 07:27:07 -0800 (PST) Received: from bender.baylibre.local ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id a127-v6sm1748545wmh.24.2018.11.09.07.27.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Nov 2018 07:27:07 -0800 (PST) From: Neil Armstrong To: u-boot@lists.denx.de Date: Fri, 9 Nov 2018 16:26:46 +0100 Message-Id: <1541777218-472-8-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1541777218-472-1-git-send-email-narmstrong@baylibre.com> References: <1541777218-472-1-git-send-email-narmstrong@baylibre.com> Cc: linux-amlogic@lists.infradead.org, trini@konsulko.com, Jerome Brunet Subject: [U-Boot] [PATCH u-boot 07/19] configs: meson: change default load addresses X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jerome Brunet The original chosen addresses conflict with the BL2 initialisation. So far there was no issue with them but if we preload binaries in RAM (ROMUSB boot) before running the BL2 they get corrupted by the execution of BL2 init. If we load them around 0x08000000, there is no such issue. Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- include/configs/meson64.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 1929a3e..80c883e 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -41,9 +41,9 @@ #ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_addr_r=0x01000000\0" \ - "scriptaddr=0x1f000000\0" \ - "kernel_addr_r=0x01080000\0" \ + "fdt_addr_r=0x08008000\0" \ + "scriptaddr=0x08000000\0" \ + "kernel_addr_r=0x08080000\0" \ "pxefile_addr_r=0x01080000\0" \ "ramdisk_addr_r=0x13000000\0" \ "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ From patchwork Fri Nov 9 15:26:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 150670 Delivered-To: patch@linaro.org Received: by 2002:aa7:da0f:0:0:0:0:0 with SMTP id r15csp377630eds; Fri, 9 Nov 2018 07:34:59 -0800 (PST) X-Google-Smtp-Source: AJdET5dC/Rrdc0VKO+huwsOImnjIUK70ziqrlIkahg3RTaK1NMtLjXWRM+NJGehZbeErJtAQCgrB X-Received: by 2002:a50:90a7:: with SMTP id c36-v6mr2872947eda.31.1541777699573; Fri, 09 Nov 2018 07:34:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541777699; cv=none; d=google.com; s=arc-20160816; b=yXr3GbQ88yHpFbhjewLrlPdx0ByFy39XrysPa0LcC2Ypciz6J/nQEEU2I+F+jP53bh 8dqug7M1p42O9VOjIHNZsU2qEAvh6ACeitUp1N1wJBFX9YnlSU/Gy0LLVOkr+6VPc/ar gX25LrefcwiVX4S8bYYISxdKYep/quXYT/onVl6JuR41Zv3kSw3XwoPBq1v8PwMhMYRa LYBYY9LIVxCccY/3c/Lah7c1c67h9bfk/6pbtZkVseulUc84inlkmT97aUkdMyPnQxnA qhVzKU9KEkIUBKm3k8K4gDVExu1OiUf6yB0uegVc4NX/5IIqLwvwIJE8BAB1e6u1Ozew i82w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature; bh=WL69t2sM6JFEFtrn02+Q9wzFNXHOyYASCVfmSsjDTo8=; b=v24szH4A+37lGOGR7BpQPA9GOPw7/CIiwWpyoIm3fhsIywFcLJtyRZ7eNNQO7ja9et JToqIBAq5L3fVFDYBzfLqA1qRJjcG80cTWXF5k2iGbkEv55x93FqBoAI+TPYPmmrD8i/ 9/Z3UEgUudKO6SYK3Iw2Ha2Iy6H8KaYiekHpQxAUl/BGPmi45JKe7wBNW9AjJOftznSj 5fFSIzAAPgtQFX+Wjoo34sXOIEbrdZX+7T9Af3yeRSB24E0sSku9/4dRGOBukkBwGu8v Ycvo1FMPF6JGmzCzvL83FLTEkhhruJi9Dqqr6T90CZNixBZYYUNLiZM81vvkOQlicTCf t6PQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=CdJMgtwP; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id t24-v6si3921607edc.405.2018.11.09.07.34.58; Fri, 09 Nov 2018 07:34:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=CdJMgtwP; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 94CC8C225AE; Fri, 9 Nov 2018 15:33:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A79DEC225CE; Fri, 9 Nov 2018 15:27:26 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8B25AC22594; Fri, 9 Nov 2018 15:27:15 +0000 (UTC) Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by lists.denx.de (Postfix) with ESMTPS id A9BF6C225A3 for ; Fri, 9 Nov 2018 15:27:09 +0000 (UTC) Received: by mail-wm1-f67.google.com with SMTP id r63-v6so2391337wma.4 for ; Fri, 09 Nov 2018 07:27:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1I8t3Bda3keis/UqDRluQ3IKQgF2qM4zjn8NWvfByBY=; b=CdJMgtwP3uUjawm2NxvH7Ty0Y1LdCsQ40VN8FMFdPt7fUEcXrvPKgzgIhjXOcPLREp zuS2b4NlDMFulnKESjHRaIifAjdu4GKtNi2gIHrT0qyQ10zmQ/r0nJSc+q8/N8rYuOue JnJKV0UHO7L0o8szFHshVjyeIDDw14a7lZGFXpoE2jQ9JceRHwuoEeArOsqAEO0sVwN7 uV6LwN3n+moNatd2Fj3IG+E9m6KL15L9W0hpEhYh4vkv6j1/k+89hTE3yPuNx/4j0EjB I2rem02+s2GYbrE3aV+Pt/XH1eVCv0IQgN951VcWABCiwJ/Xj2ixsIfc0GzIDSaaKDgf 3omg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1I8t3Bda3keis/UqDRluQ3IKQgF2qM4zjn8NWvfByBY=; b=GpcDjmJ38JDiD9jemEixlxBYKRO62HBJt+vqOtdIl+FOR9ZJNt+KTf6sMRU5+SOVju mjN5S9ngfOb9EIjCkFdChFHlHWrihVVXISKvAHICnTguNXTQztKg31PY4V/XdZM4IZoq HEQkELmiCNnzR/X6REG5FQPHgTSsQgD0lntUq8n5L7yVzcE2PlxdBSR46IligLXoBp/t dLn0VzqbyWuV+Xw2IMNd1pyDKI61/QV5Km6hz6uV4rmJFe7Es9fm66g4L598rgP1+oWo FJUjfEo060JTgaFW1oaqSbii+r7G7VhtT1MftopPxArRLJ57e9RvfYlfpHuLxTbIylPc fzCA== X-Gm-Message-State: AGRZ1gI0YrGPiaxPxxMCGNGINI0HeSu8EOJhb2Q/8k8GzT3WCZTgWxv1 BFzWRSD6FzNFrBLx0B4iWtR+rUZIrvI= X-Received: by 2002:a7b:c183:: with SMTP id y3-v6mr4949209wmi.150.1541777228826; Fri, 09 Nov 2018 07:27:08 -0800 (PST) Received: from bender.baylibre.local ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id a127-v6sm1748545wmh.24.2018.11.09.07.27.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Nov 2018 07:27:08 -0800 (PST) From: Neil Armstrong To: u-boot@lists.denx.de Date: Fri, 9 Nov 2018 16:26:47 +0100 Message-Id: <1541777218-472-9-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1541777218-472-1-git-send-email-narmstrong@baylibre.com> References: <1541777218-472-1-git-send-email-narmstrong@baylibre.com> Cc: linux-amlogic@lists.infradead.org, trini@konsulko.com, Jerome Brunet Subject: [U-Boot] [PATCH u-boot 08/19] pinctrl: meson: rework gx pmx function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jerome Brunet In preparation of supporting the new Amlogix AGX SoCs, we need to move the Amlogic GX pinmux functions out of the common code to be able to add a different set of SoC specific pinmux functions for AXG. Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- drivers/pinctrl/meson/Kconfig | 8 +- drivers/pinctrl/meson/Makefile | 1 + drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c | 97 ++++++++++++++++++++++++ drivers/pinctrl/meson/pinctrl-meson-gx.h | 48 ++++++++++++ drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 6 +- drivers/pinctrl/meson/pinctrl-meson-gxl.c | 6 +- drivers/pinctrl/meson/pinctrl-meson.c | 109 ++++----------------------- drivers/pinctrl/meson/pinctrl-meson.h | 37 +++++---- 8 files changed, 191 insertions(+), 121 deletions(-) create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gx.h diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index 27ba890..15a8d9c 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig @@ -4,12 +4,16 @@ config PINCTRL_MESON depends on PINCTRL_GENERIC bool +config PINCTRL_MESON_GX_PMX + select PINCTRL_MESON + bool + config PINCTRL_MESON_GXBB bool "Amlogic Meson GXBB SoC pinctrl driver" - select PINCTRL_MESON + select PINCTRL_MESON_GX_PMX config PINCTRL_MESON_GXL bool "Amlogic Meson GXL SoC pinctrl driver" - select PINCTRL_MESON + select PINCTRL_MESON_GX_PMX endif diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile index 965092c..30b6875 100644 --- a/drivers/pinctrl/meson/Makefile +++ b/drivers/pinctrl/meson/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y += pinctrl-meson.o +obj-$(CONFIG_PINCTRL_MESON_GX_PMX) += pinctrl-meson-gx-pmx.o obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o diff --git a/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c new file mode 100644 index 0000000..fc1538e --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 - Beniamino Galvani + */ + +#include +#include +#include +#include +#include +#include "pinctrl-meson-gx.h" + +static void meson_gx_pinmux_disable_other_groups(struct meson_pinctrl *priv, + unsigned int pin, + int sel_group) +{ + struct meson_pmx_group *group; + struct meson_gx_pmx_data *pmx_data; + void __iomem *addr; + int i, j; + + for (i = 0; i < priv->data->num_groups; i++) { + group = &priv->data->groups[i]; + pmx_data = (struct meson_gx_pmx_data *)group->data; + if (pmx_data->is_gpio || i == sel_group) + continue; + + for (j = 0; j < group->num_pins; j++) { + if (group->pins[j] == pin) { + /* We have found a group using the pin */ + debug("pinmux: disabling %s\n", group->name); + addr = priv->reg_mux + pmx_data->reg * 4; + writel(readl(addr) & ~BIT(pmx_data->bit), addr); + } + } + } +} + +static int meson_gx_pinmux_group_set(struct udevice *dev, + unsigned int group_selector, + unsigned int func_selector) +{ + struct meson_pinctrl *priv = dev_get_priv(dev); + const struct meson_pmx_group *group; + const struct meson_pmx_func *func; + struct meson_gx_pmx_data *pmx_data; + void __iomem *addr; + int i; + + group = &priv->data->groups[group_selector]; + pmx_data = (struct meson_gx_pmx_data *)group->data; + func = &priv->data->funcs[func_selector]; + + debug("pinmux: set group %s func %s\n", group->name, func->name); + + /* + * Disable groups using the same pins. + * The selected group is not disabled to avoid glitches. + */ + for (i = 0; i < group->num_pins; i++) { + meson_gx_pinmux_disable_other_groups(priv, + group->pins[i], + group_selector); + } + + /* Function 0 (GPIO) doesn't need any additional setting */ + if (func_selector) { + addr = priv->reg_mux + pmx_data->reg * 4; + writel(readl(addr) | BIT(pmx_data->bit), addr); + } + + return 0; +} + +const struct pinctrl_ops meson_gx_pinctrl_ops = { + .get_groups_count = meson_pinctrl_get_groups_count, + .get_group_name = meson_pinctrl_get_group_name, + .get_functions_count = meson_pinmux_get_functions_count, + .get_function_name = meson_pinmux_get_function_name, + .pinmux_group_set = meson_gx_pinmux_group_set, + .set_state = pinctrl_generic_set_state, +}; + +static const struct dm_gpio_ops meson_gx_gpio_ops = { + .set_value = meson_gpio_set, + .get_value = meson_gpio_get, + .get_function = meson_gpio_get_direction, + .direction_input = meson_gpio_direction_input, + .direction_output = meson_gpio_direction_output, +}; + +const struct driver meson_gx_gpio_driver = { + .name = "meson-gx-gpio", + .id = UCLASS_GPIO, + .probe = meson_gpio_probe, + .ops = &meson_gx_gpio_ops, +}; diff --git a/drivers/pinctrl/meson/pinctrl-meson-gx.h b/drivers/pinctrl/meson/pinctrl-meson-gx.h new file mode 100644 index 0000000..4c1aa1a --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-gx.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Beniamino Galvani + * Copyright (C) 2017 Jerome Brunet + */ + +#ifndef __PINCTRL_MESON_GX_H__ +#define __PINCTRL_MESON_GX_H__ + +#include "pinctrl-meson.h" + +struct meson_gx_pmx_data { + bool is_gpio; + unsigned int reg; + unsigned int bit; +}; + +#define PMX_DATA(r, b, g) \ + { \ + .reg = r, \ + .bit = b, \ + .is_gpio = g, \ + } + +#define GROUP(grp, r, b) \ + { \ + .name = #grp, \ + .pins = grp ## _pins, \ + .num_pins = ARRAY_SIZE(grp ## _pins), \ + .data = (const struct meson_gx_pmx_data[]){ \ + PMX_DATA(r, b, false), \ + }, \ + } + +#define GPIO_GROUP(gpio, b) \ + { \ + .name = #gpio, \ + .pins = (const unsigned int[]){ PIN(gpio, b) }, \ + .num_pins = 1, \ + .data = (const struct meson_gx_pmx_data[]){ \ + PMX_DATA(0, 0, true), \ + }, \ + } + +extern const struct pinctrl_ops meson_gx_pinctrl_ops; +extern const struct driver meson_gx_gpio_driver; + +#endif /* __PINCTRL_MESON_GX_H__ */ diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index a8e47e3..22e8b05 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -11,7 +11,7 @@ #include #include -#include "pinctrl-meson.h" +#include "pinctrl-meson-gx.h" #define EE_OFF 15 @@ -417,6 +417,7 @@ struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups), .num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions), .num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks), + .gpio_driver = &meson_gx_gpio_driver, }; struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { @@ -429,6 +430,7 @@ struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups), .num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions), .num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks), + .gpio_driver = &meson_gx_gpio_driver, }; static const struct udevice_id meson_gxbb_pinctrl_match[] = { @@ -449,5 +451,5 @@ U_BOOT_DRIVER(meson_gxbb_pinctrl) = { .of_match = of_match_ptr(meson_gxbb_pinctrl_match), .probe = meson_pinctrl_probe, .priv_auto_alloc_size = sizeof(struct meson_pinctrl), - .ops = &meson_pinctrl_ops, + .ops = &meson_gx_pinctrl_ops, }; diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c index ba6e353..1819eee 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -11,7 +11,7 @@ #include #include -#include "pinctrl-meson.h" +#include "pinctrl-meson-gx.h" #define EE_OFF 11 @@ -699,6 +699,7 @@ struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_gxl_periphs_groups), .num_funcs = ARRAY_SIZE(meson_gxl_periphs_functions), .num_banks = ARRAY_SIZE(meson_gxl_periphs_banks), + .gpio_driver = &meson_gx_gpio_driver, }; struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = { @@ -711,6 +712,7 @@ struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_gxl_aobus_groups), .num_funcs = ARRAY_SIZE(meson_gxl_aobus_functions), .num_banks = ARRAY_SIZE(meson_gxl_aobus_banks), + .gpio_driver = &meson_gx_gpio_driver, }; static const struct udevice_id meson_gxl_pinctrl_match[] = { @@ -731,5 +733,5 @@ U_BOOT_DRIVER(meson_gxl_pinctrl) = { .of_match = of_match_ptr(meson_gxl_pinctrl_match), .probe = meson_pinctrl_probe, .priv_auto_alloc_size = sizeof(struct meson_pinctrl), - .ops = &meson_pinctrl_ops, + .ops = &meson_gx_pinctrl_ops, }; diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 387c241..0bd6152 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -20,15 +20,15 @@ DECLARE_GLOBAL_DATA_PTR; static const char *meson_pinctrl_dummy_name = "_dummy"; -static int meson_pinctrl_get_groups_count(struct udevice *dev) +int meson_pinctrl_get_groups_count(struct udevice *dev) { struct meson_pinctrl *priv = dev_get_priv(dev); return priv->data->num_groups; } -static const char *meson_pinctrl_get_group_name(struct udevice *dev, - unsigned selector) +const char *meson_pinctrl_get_group_name(struct udevice *dev, + unsigned int selector) { struct meson_pinctrl *priv = dev_get_priv(dev); @@ -38,87 +38,21 @@ static const char *meson_pinctrl_get_group_name(struct udevice *dev, return priv->data->groups[selector].name; } -static int meson_pinmux_get_functions_count(struct udevice *dev) +int meson_pinmux_get_functions_count(struct udevice *dev) { struct meson_pinctrl *priv = dev_get_priv(dev); return priv->data->num_funcs; } -static const char *meson_pinmux_get_function_name(struct udevice *dev, - unsigned selector) +const char *meson_pinmux_get_function_name(struct udevice *dev, + unsigned int selector) { struct meson_pinctrl *priv = dev_get_priv(dev); return priv->data->funcs[selector].name; } -static void meson_pinmux_disable_other_groups(struct meson_pinctrl *priv, - unsigned int pin, int sel_group) -{ - struct meson_pmx_group *group; - void __iomem *addr; - int i, j; - - for (i = 0; i < priv->data->num_groups; i++) { - group = &priv->data->groups[i]; - if (group->is_gpio || i == sel_group) - continue; - - for (j = 0; j < group->num_pins; j++) { - if (group->pins[j] == pin) { - /* We have found a group using the pin */ - debug("pinmux: disabling %s\n", group->name); - addr = priv->reg_mux + group->reg * 4; - writel(readl(addr) & ~BIT(group->bit), addr); - } - } - } -} - -static int meson_pinmux_group_set(struct udevice *dev, - unsigned group_selector, - unsigned func_selector) -{ - struct meson_pinctrl *priv = dev_get_priv(dev); - const struct meson_pmx_group *group; - const struct meson_pmx_func *func; - void __iomem *addr; - int i; - - group = &priv->data->groups[group_selector]; - func = &priv->data->funcs[func_selector]; - - debug("pinmux: set group %s func %s\n", group->name, func->name); - - /* - * Disable groups using the same pins. - * The selected group is not disabled to avoid glitches. - */ - for (i = 0; i < group->num_pins; i++) { - meson_pinmux_disable_other_groups(priv, - group->pins[i], - group_selector); - } - - /* Function 0 (GPIO) doesn't need any additional setting */ - if (func_selector) { - addr = priv->reg_mux + group->reg * 4; - writel(readl(addr) | BIT(group->bit), addr); - } - - return 0; -} - -const struct pinctrl_ops meson_pinctrl_ops = { - .get_groups_count = meson_pinctrl_get_groups_count, - .get_group_name = meson_pinctrl_get_group_name, - .get_functions_count = meson_pinmux_get_functions_count, - .get_function_name = meson_pinmux_get_function_name, - .pinmux_group_set = meson_pinmux_group_set, - .set_state = pinctrl_generic_set_state, -}; - static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset, enum meson_reg_type reg_type, unsigned int *reg, unsigned int *bit) @@ -149,7 +83,7 @@ static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset, return 0; } -static int meson_gpio_get(struct udevice *dev, unsigned int offset) +int meson_gpio_get(struct udevice *dev, unsigned int offset) { struct meson_pinctrl *priv = dev_get_priv(dev->parent); unsigned int reg, bit; @@ -162,7 +96,7 @@ static int meson_gpio_get(struct udevice *dev, unsigned int offset) return !!(readl(priv->reg_gpio + reg) & BIT(bit)); } -static int meson_gpio_set(struct udevice *dev, unsigned int offset, int value) +int meson_gpio_set(struct udevice *dev, unsigned int offset, int value) { struct meson_pinctrl *priv = dev_get_priv(dev->parent); unsigned int reg, bit; @@ -177,7 +111,7 @@ static int meson_gpio_set(struct udevice *dev, unsigned int offset, int value) return 0; } -static int meson_gpio_get_direction(struct udevice *dev, unsigned int offset) +int meson_gpio_get_direction(struct udevice *dev, unsigned int offset) { struct meson_pinctrl *priv = dev_get_priv(dev->parent); unsigned int reg, bit, val; @@ -192,7 +126,7 @@ static int meson_gpio_get_direction(struct udevice *dev, unsigned int offset) return (val & BIT(bit)) ? GPIOF_INPUT : GPIOF_OUTPUT; } -static int meson_gpio_direction_input(struct udevice *dev, unsigned int offset) +int meson_gpio_direction_input(struct udevice *dev, unsigned int offset) { struct meson_pinctrl *priv = dev_get_priv(dev->parent); unsigned int reg, bit; @@ -207,8 +141,8 @@ static int meson_gpio_direction_input(struct udevice *dev, unsigned int offset) return 0; } -static int meson_gpio_direction_output(struct udevice *dev, - unsigned int offset, int value) +int meson_gpio_direction_output(struct udevice *dev, + unsigned int offset, int value) { struct meson_pinctrl *priv = dev_get_priv(dev->parent); unsigned int reg, bit; @@ -229,7 +163,7 @@ static int meson_gpio_direction_output(struct udevice *dev, return 0; } -static int meson_gpio_probe(struct udevice *dev) +int meson_gpio_probe(struct udevice *dev) { struct meson_pinctrl *priv = dev_get_priv(dev->parent); struct gpio_dev_priv *uc_priv; @@ -241,21 +175,6 @@ static int meson_gpio_probe(struct udevice *dev) return 0; } -static const struct dm_gpio_ops meson_gpio_ops = { - .set_value = meson_gpio_set, - .get_value = meson_gpio_get, - .get_function = meson_gpio_get_direction, - .direction_input = meson_gpio_direction_input, - .direction_output = meson_gpio_direction_output, -}; - -static struct driver meson_gpio_driver = { - .name = "meson-gpio", - .id = UCLASS_GPIO, - .probe = meson_gpio_probe, - .ops = &meson_gpio_ops, -}; - static fdt_addr_t parse_address(int offset, const char *name, int na, int ns) { int index, len = 0; @@ -334,7 +253,7 @@ int meson_pinctrl_probe(struct udevice *dev) sprintf(name, "meson-gpio"); /* Create child device UCLASS_GPIO and bind it */ - device_bind(dev, &meson_gpio_driver, name, NULL, gpio, &gpio_dev); + device_bind(dev, priv->data->gpio_driver, name, NULL, gpio, &gpio_dev); dev_set_of_offset(gpio_dev, gpio); return 0; diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h index 6ec89ba..bdee721 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.h +++ b/drivers/pinctrl/meson/pinctrl-meson.h @@ -12,9 +12,7 @@ struct meson_pmx_group { const char *name; const unsigned int *pins; unsigned int num_pins; - bool is_gpio; - unsigned int reg; - unsigned int bit; + const void *data; }; struct meson_pmx_func { @@ -33,6 +31,8 @@ struct meson_pinctrl_data { unsigned int num_groups; unsigned int num_funcs; unsigned int num_banks; + const struct driver *gpio_driver; + void *pmx_data; }; struct meson_pinctrl { @@ -89,23 +89,6 @@ struct meson_bank { #define PIN(x, b) (b + x) -#define GROUP(grp, r, b) \ - { \ - .name = #grp, \ - .pins = grp ## _pins, \ - .num_pins = ARRAY_SIZE(grp ## _pins), \ - .reg = r, \ - .bit = b, \ - } - -#define GPIO_GROUP(gpio, b) \ - { \ - .name = #gpio, \ - .pins = (const unsigned int[]){ PIN(gpio, b) }, \ - .num_pins = 1, \ - .is_gpio = true, \ - } - #define FUNCTION(fn) \ { \ .name = #fn, \ @@ -131,6 +114,20 @@ struct meson_bank { extern const struct pinctrl_ops meson_pinctrl_ops; +int meson_pinctrl_get_groups_count(struct udevice *dev); +const char *meson_pinctrl_get_group_name(struct udevice *dev, + unsigned int selector); +int meson_pinmux_get_functions_count(struct udevice *dev); +const char *meson_pinmux_get_function_name(struct udevice *dev, + unsigned int selector); int meson_pinctrl_probe(struct udevice *dev); +int meson_gpio_get(struct udevice *dev, unsigned int offset); +int meson_gpio_set(struct udevice *dev, unsigned int offset, int value); +int meson_gpio_get_direction(struct udevice *dev, unsigned int offset); +int meson_gpio_direction_input(struct udevice *dev, unsigned int offset); +int meson_gpio_direction_output(struct udevice *dev, unsigned int offset, + int value); +int meson_gpio_probe(struct udevice *dev); + #endif /* __PINCTRL_MESON_H__ */ From patchwork Fri Nov 9 15:26:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 150671 Delivered-To: patch@linaro.org Received: by 2002:aa7:da0f:0:0:0:0:0 with SMTP id r15csp378424eds; Fri, 9 Nov 2018 07:35:36 -0800 (PST) X-Google-Smtp-Source: AJdET5eF6eUnSvT1RKPTi9pHGBdLA/zrtmNAIuMHhB2ofYrbLIaKcd6ubTlIr9bWUYTwAC5FVNDz X-Received: by 2002:a17:906:5451:: with SMTP id d17-v6mr2180502ejp.65.1541777736305; Fri, 09 Nov 2018 07:35:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541777736; cv=none; d=google.com; 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Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- drivers/pinctrl/meson/Kconfig | 8 + drivers/pinctrl/meson/Makefile | 2 + drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c | 125 ++++ drivers/pinctrl/meson/pinctrl-meson-axg.c | 979 ++++++++++++++++++++++++++ drivers/pinctrl/meson/pinctrl-meson-axg.h | 66 ++ 5 files changed, 1180 insertions(+) create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg.c create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg.h diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index fc51b43..ee820a5 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig @@ -8,6 +8,10 @@ config PINCTRL_MESON_GX_PMX select PINCTRL_MESON bool +config PINCTRL_MESON_AXG_PMX + select PINCTRL_MESON + bool + config PINCTRL_MESON_GXBB bool "Amlogic Meson GXBB SoC pinctrl driver" select PINCTRL_MESON_GX_PMX @@ -16,4 +20,8 @@ config PINCTRL_MESON_GXL bool "Amlogic Meson GXL SoC pinctrl driver" select PINCTRL_MESON_GX_PMX +config PINCTRL_MESON_AXG + bool "Amlogic Meson AXG SoC pinctrl driver" + select PINCTRL_MESON_AXG_PMX + endif diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile index 30b6875..707287c 100644 --- a/drivers/pinctrl/meson/Makefile +++ b/drivers/pinctrl/meson/Makefile @@ -2,5 +2,7 @@ obj-y += pinctrl-meson.o obj-$(CONFIG_PINCTRL_MESON_GX_PMX) += pinctrl-meson-gx-pmx.o +obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o +obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c new file mode 100644 index 0000000..9c751ee --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Jerome Brunet + * Copyright (C) 2017 Xingyu Chen + */ + +#include +#include +#include +#include +#include +#include "pinctrl-meson-axg.h" + +static int meson_axg_pmx_get_bank(struct udevice *dev, unsigned int pin, + struct meson_pmx_bank **bank) +{ + int i; + struct meson_pinctrl *priv = dev_get_priv(dev); + struct meson_axg_pmx_data *pmx = priv->data->pmx_data; + + for (i = 0; i < pmx->num_pmx_banks; i++) + if (pin >= pmx->pmx_banks[i].first && + pin <= pmx->pmx_banks[i].last) { + *bank = &pmx->pmx_banks[i]; + return 0; + } + + return -EINVAL; +} + +static int meson_axg_pmx_calc_reg_and_offset(struct meson_pmx_bank *bank, + unsigned int pin, + unsigned int *reg, + unsigned int *offset) +{ + int shift; + + shift = pin - bank->first; + + *reg = bank->reg + (bank->offset + (shift << 2)) / 32; + *offset = (bank->offset + (shift << 2)) % 32; + + return 0; +} + +static int meson_axg_pmx_update_function(struct udevice *dev, + unsigned int pin, unsigned int func) +{ + struct meson_pinctrl *priv = dev_get_priv(dev); + struct meson_pmx_bank *bank; + unsigned int offset; + unsigned int reg; + unsigned int tmp; + int ret; + + ret = meson_axg_pmx_get_bank(dev, pin, &bank); + if (ret) + return ret; + + meson_axg_pmx_calc_reg_and_offset(bank, pin, ®, &offset); + + tmp = readl(priv->reg_mux + (reg << 2)); + tmp &= ~(0xf << offset); + tmp |= (func & 0xf) << offset; + writel(tmp, priv->reg_mux + (reg << 2)); + + return ret; +} + +static int meson_axg_pinmux_group_set(struct udevice *dev, + unsigned int group_selector, + unsigned int func_selector) +{ + struct meson_pinctrl *priv = dev_get_priv(dev); + const struct meson_pmx_group *group; + const struct meson_pmx_func *func; + struct meson_pmx_axg_data *pmx_data; + int i, ret; + + group = &priv->data->groups[group_selector]; + pmx_data = (struct meson_pmx_axg_data *)group->data; + func = &priv->data->funcs[func_selector]; + + debug("pinmux: set group %s func %s\n", group->name, func->name); + + for (i = 0; i < group->num_pins; i++) { + ret = meson_axg_pmx_update_function(dev, group->pins[i], + pmx_data->func); + if (ret) + return ret; + } + + return 0; +} + +const struct pinctrl_ops meson_axg_pinctrl_ops = { + .get_groups_count = meson_pinctrl_get_groups_count, + .get_group_name = meson_pinctrl_get_group_name, + .get_functions_count = meson_pinmux_get_functions_count, + .get_function_name = meson_pinmux_get_function_name, + .pinmux_group_set = meson_axg_pinmux_group_set, + .set_state = pinctrl_generic_set_state, +}; + +static int meson_axg_gpio_request(struct udevice *dev, + unsigned int offset, const char *label) +{ + return meson_axg_pmx_update_function(dev, offset, 0); +} + +static const struct dm_gpio_ops meson_axg_gpio_ops = { + .request = meson_axg_gpio_request, + .set_value = meson_gpio_set, + .get_value = meson_gpio_get, + .get_function = meson_gpio_get_direction, + .direction_input = meson_gpio_direction_input, + .direction_output = meson_gpio_direction_output, +}; + +const struct driver meson_axg_gpio_driver = { + .name = "meson-axg-gpio", + .id = UCLASS_GPIO, + .probe = meson_gpio_probe, + .ops = &meson_axg_gpio_ops, +}; diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c new file mode 100644 index 0000000..ab51652 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c @@ -0,0 +1,979 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright (C) 2018 Neil Armstrong + * + * Based on code from Linux kernel: + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen + */ + +#include +#include +#include +#include + +#include "pinctrl-meson-axg.h" + +#define EE_OFF 14 + +/* emmc */ +static const unsigned int emmc_nand_d0_pins[] = {BOOT_0}; +static const unsigned int emmc_nand_d1_pins[] = {BOOT_1}; +static const unsigned int emmc_nand_d2_pins[] = {BOOT_2}; +static const unsigned int emmc_nand_d3_pins[] = {BOOT_3}; +static const unsigned int emmc_nand_d4_pins[] = {BOOT_4}; +static const unsigned int emmc_nand_d5_pins[] = {BOOT_5}; +static const unsigned int emmc_nand_d6_pins[] = {BOOT_6}; +static const unsigned int emmc_nand_d7_pins[] = {BOOT_7}; + +static const unsigned int emmc_clk_pins[] = {BOOT_8}; +static const unsigned int emmc_cmd_pins[] = {BOOT_10}; +static const unsigned int emmc_ds_pins[] = {BOOT_13}; + +/* nand */ +static const unsigned int nand_ce0_pins[] = {BOOT_8}; +static const unsigned int nand_ale_pins[] = {BOOT_9}; +static const unsigned int nand_cle_pins[] = {BOOT_10}; +static const unsigned int nand_wen_clk_pins[] = {BOOT_11}; +static const unsigned int nand_ren_wr_pins[] = {BOOT_12}; +static const unsigned int nand_rb0_pins[] = {BOOT_13}; + +/* nor */ +static const unsigned int nor_hold_pins[] = {BOOT_3}; +static const unsigned int nor_d_pins[] = {BOOT_4}; +static const unsigned int nor_q_pins[] = {BOOT_5}; +static const unsigned int nor_c_pins[] = {BOOT_6}; +static const unsigned int nor_wp_pins[] = {BOOT_9}; +static const unsigned int nor_cs_pins[] = {BOOT_14}; + +/* sdio */ +static const unsigned int sdio_d0_pins[] = {GPIOX_0}; +static const unsigned int sdio_d1_pins[] = {GPIOX_1}; +static const unsigned int sdio_d2_pins[] = {GPIOX_2}; +static const unsigned int sdio_d3_pins[] = {GPIOX_3}; +static const unsigned int sdio_clk_pins[] = {GPIOX_4}; +static const unsigned int sdio_cmd_pins[] = {GPIOX_5}; + +/* spi0 */ +static const unsigned int spi0_clk_pins[] = {GPIOZ_0}; +static const unsigned int spi0_mosi_pins[] = {GPIOZ_1}; +static const unsigned int spi0_miso_pins[] = {GPIOZ_2}; +static const unsigned int spi0_ss0_pins[] = {GPIOZ_3}; +static const unsigned int spi0_ss1_pins[] = {GPIOZ_4}; +static const unsigned int spi0_ss2_pins[] = {GPIOZ_5}; + +/* spi1 */ +static const unsigned int spi1_clk_x_pins[] = {GPIOX_19}; +static const unsigned int spi1_mosi_x_pins[] = {GPIOX_17}; +static const unsigned int spi1_miso_x_pins[] = {GPIOX_18}; +static const unsigned int spi1_ss0_x_pins[] = {GPIOX_16}; + +static const unsigned int spi1_clk_a_pins[] = {GPIOA_4}; +static const unsigned int spi1_mosi_a_pins[] = {GPIOA_2}; +static const unsigned int spi1_miso_a_pins[] = {GPIOA_3}; +static const unsigned int spi1_ss0_a_pins[] = {GPIOA_5}; +static const unsigned int spi1_ss1_pins[] = {GPIOA_6}; + +/* i2c0 */ +static const unsigned int i2c0_sck_pins[] = {GPIOZ_6}; +static const unsigned int i2c0_sda_pins[] = {GPIOZ_7}; + +/* i2c1 */ +static const unsigned int i2c1_sck_z_pins[] = {GPIOZ_8}; +static const unsigned int i2c1_sda_z_pins[] = {GPIOZ_9}; + +static const unsigned int i2c1_sck_x_pins[] = {GPIOX_16}; +static const unsigned int i2c1_sda_x_pins[] = {GPIOX_17}; + +/* i2c2 */ +static const unsigned int i2c2_sck_x_pins[] = {GPIOX_18}; +static const unsigned int i2c2_sda_x_pins[] = {GPIOX_19}; + +static const unsigned int i2c2_sda_a_pins[] = {GPIOA_17}; +static const unsigned int i2c2_sck_a_pins[] = {GPIOA_18}; + +/* i2c3 */ +static const unsigned int i2c3_sda_a6_pins[] = {GPIOA_6}; +static const unsigned int i2c3_sck_a7_pins[] = {GPIOA_7}; + +static const unsigned int i2c3_sda_a12_pins[] = {GPIOA_12}; +static const unsigned int i2c3_sck_a13_pins[] = {GPIOA_13}; + +static const unsigned int i2c3_sda_a19_pins[] = {GPIOA_19}; +static const unsigned int i2c3_sck_a20_pins[] = {GPIOA_20}; + +/* uart_a */ +static const unsigned int uart_rts_a_pins[] = {GPIOX_11}; +static const unsigned int uart_cts_a_pins[] = {GPIOX_10}; +static const unsigned int uart_tx_a_pins[] = {GPIOX_8}; +static const unsigned int uart_rx_a_pins[] = {GPIOX_9}; + +/* uart_b */ +static const unsigned int uart_rts_b_z_pins[] = {GPIOZ_0}; +static const unsigned int uart_cts_b_z_pins[] = {GPIOZ_1}; +static const unsigned int uart_tx_b_z_pins[] = {GPIOZ_2}; +static const unsigned int uart_rx_b_z_pins[] = {GPIOZ_3}; + +static const unsigned int uart_rts_b_x_pins[] = {GPIOX_18}; +static const unsigned int uart_cts_b_x_pins[] = {GPIOX_19}; +static const unsigned int uart_tx_b_x_pins[] = {GPIOX_16}; +static const unsigned int uart_rx_b_x_pins[] = {GPIOX_17}; + +/* uart_ao_b */ +static const unsigned int uart_ao_tx_b_z_pins[] = {GPIOZ_8}; +static const unsigned int uart_ao_rx_b_z_pins[] = {GPIOZ_9}; +static const unsigned int uart_ao_cts_b_z_pins[] = {GPIOZ_6}; +static const unsigned int uart_ao_rts_b_z_pins[] = {GPIOZ_7}; + +/* pwm_a */ +static const unsigned int pwm_a_z_pins[] = {GPIOZ_5}; + +static const unsigned int pwm_a_x18_pins[] = {GPIOX_18}; +static const unsigned int pwm_a_x20_pins[] = {GPIOX_20}; + +static const unsigned int pwm_a_a_pins[] = {GPIOA_14}; + +/* pwm_b */ +static const unsigned int pwm_b_z_pins[] = {GPIOZ_4}; + +static const unsigned int pwm_b_x_pins[] = {GPIOX_19}; + +static const unsigned int pwm_b_a_pins[] = {GPIOA_15}; + +/* pwm_c */ +static const unsigned int pwm_c_x10_pins[] = {GPIOX_10}; +static const unsigned int pwm_c_x17_pins[] = {GPIOX_17}; + +static const unsigned int pwm_c_a_pins[] = {GPIOA_16}; + +/* pwm_d */ +static const unsigned int pwm_d_x11_pins[] = {GPIOX_11}; +static const unsigned int pwm_d_x16_pins[] = {GPIOX_16}; + +/* pwm_vs */ +static const unsigned int pwm_vs_pins[] = {GPIOA_0}; + +/* spdif_in */ +static const unsigned int spdif_in_z_pins[] = {GPIOZ_4}; + +static const unsigned int spdif_in_a1_pins[] = {GPIOA_1}; +static const unsigned int spdif_in_a7_pins[] = {GPIOA_7}; +static const unsigned int spdif_in_a19_pins[] = {GPIOA_19}; +static const unsigned int spdif_in_a20_pins[] = {GPIOA_20}; + +/* spdif_out */ +static const unsigned int spdif_out_z_pins[] = {GPIOZ_5}; + +static const unsigned int spdif_out_a1_pins[] = {GPIOA_1}; +static const unsigned int spdif_out_a11_pins[] = {GPIOA_11}; +static const unsigned int spdif_out_a19_pins[] = {GPIOA_19}; +static const unsigned int spdif_out_a20_pins[] = {GPIOA_20}; + +/* jtag_ee */ +static const unsigned int jtag_tdo_x_pins[] = {GPIOX_0}; +static const unsigned int jtag_tdi_x_pins[] = {GPIOX_1}; +static const unsigned int jtag_clk_x_pins[] = {GPIOX_4}; +static const unsigned int jtag_tms_x_pins[] = {GPIOX_5}; + +/* eth */ +static const unsigned int eth_txd0_x_pins[] = {GPIOX_8}; +static const unsigned int eth_txd1_x_pins[] = {GPIOX_9}; +static const unsigned int eth_txen_x_pins[] = {GPIOX_10}; +static const unsigned int eth_rgmii_rx_clk_x_pins[] = {GPIOX_12}; +static const unsigned int eth_rxd0_x_pins[] = {GPIOX_13}; +static const unsigned int eth_rxd1_x_pins[] = {GPIOX_14}; +static const unsigned int eth_rx_dv_x_pins[] = {GPIOX_15}; +static const unsigned int eth_mdio_x_pins[] = {GPIOX_21}; +static const unsigned int eth_mdc_x_pins[] = {GPIOX_22}; + +static const unsigned int eth_txd0_y_pins[] = {GPIOY_10}; +static const unsigned int eth_txd1_y_pins[] = {GPIOY_11}; +static const unsigned int eth_txen_y_pins[] = {GPIOY_9}; +static const unsigned int eth_rgmii_rx_clk_y_pins[] = {GPIOY_2}; +static const unsigned int eth_rxd0_y_pins[] = {GPIOY_4}; +static const unsigned int eth_rxd1_y_pins[] = {GPIOY_5}; +static const unsigned int eth_rx_dv_y_pins[] = {GPIOY_3}; +static const unsigned int eth_mdio_y_pins[] = {GPIOY_0}; +static const unsigned int eth_mdc_y_pins[] = {GPIOY_1}; + +static const unsigned int eth_rxd2_rgmii_pins[] = {GPIOY_6}; +static const unsigned int eth_rxd3_rgmii_pins[] = {GPIOY_7}; +static const unsigned int eth_rgmii_tx_clk_pins[] = {GPIOY_8}; +static const unsigned int eth_txd2_rgmii_pins[] = {GPIOY_12}; +static const unsigned int eth_txd3_rgmii_pins[] = {GPIOY_13}; + +/* pdm */ +static const unsigned int pdm_dclk_a14_pins[] = {GPIOA_14}; +static const unsigned int pdm_dclk_a19_pins[] = {GPIOA_19}; +static const unsigned int pdm_din0_pins[] = {GPIOA_15}; +static const unsigned int pdm_din1_pins[] = {GPIOA_16}; +static const unsigned int pdm_din2_pins[] = {GPIOA_17}; +static const unsigned int pdm_din3_pins[] = {GPIOA_18}; + +/* mclk */ +static const unsigned int mclk_c_pins[] = {GPIOA_0}; +static const unsigned int mclk_b_pins[] = {GPIOA_1}; + +/* tdm */ +static const unsigned int tdma_sclk_pins[] = {GPIOX_12}; +static const unsigned int tdma_sclk_slv_pins[] = {GPIOX_12}; +static const unsigned int tdma_fs_pins[] = {GPIOX_13}; +static const unsigned int tdma_fs_slv_pins[] = {GPIOX_13}; +static const unsigned int tdma_din0_pins[] = {GPIOX_14}; +static const unsigned int tdma_dout0_x14_pins[] = {GPIOX_14}; +static const unsigned int tdma_dout0_x15_pins[] = {GPIOX_15}; +static const unsigned int tdma_dout1_pins[] = {GPIOX_15}; +static const unsigned int tdma_din1_pins[] = {GPIOX_15}; + +static const unsigned int tdmc_sclk_pins[] = {GPIOA_2}; +static const unsigned int tdmc_sclk_slv_pins[] = {GPIOA_2}; +static const unsigned int tdmc_fs_pins[] = {GPIOA_3}; +static const unsigned int tdmc_fs_slv_pins[] = {GPIOA_3}; +static const unsigned int tdmc_din0_pins[] = {GPIOA_4}; +static const unsigned int tdmc_dout0_pins[] = {GPIOA_4}; +static const unsigned int tdmc_din1_pins[] = {GPIOA_5}; +static const unsigned int tdmc_dout1_pins[] = {GPIOA_5}; +static const unsigned int tdmc_din2_pins[] = {GPIOA_6}; +static const unsigned int tdmc_dout2_pins[] = {GPIOA_6}; +static const unsigned int tdmc_din3_pins[] = {GPIOA_7}; +static const unsigned int tdmc_dout3_pins[] = {GPIOA_7}; + +static const unsigned int tdmb_sclk_pins[] = {GPIOA_8}; +static const unsigned int tdmb_sclk_slv_pins[] = {GPIOA_8}; +static const unsigned int tdmb_fs_pins[] = {GPIOA_9}; +static const unsigned int tdmb_fs_slv_pins[] = {GPIOA_9}; +static const unsigned int tdmb_din0_pins[] = {GPIOA_10}; +static const unsigned int tdmb_dout0_pins[] = {GPIOA_10}; +static const unsigned int tdmb_din1_pins[] = {GPIOA_11}; +static const unsigned int tdmb_dout1_pins[] = {GPIOA_11}; +static const unsigned int tdmb_din2_pins[] = {GPIOA_12}; +static const unsigned int tdmb_dout2_pins[] = {GPIOA_12}; +static const unsigned int tdmb_din3_pins[] = {GPIOA_13}; +static const unsigned int tdmb_dout3_pins[] = {GPIOA_13}; + +static struct meson_pmx_group meson_axg_periphs_groups[] = { + GPIO_GROUP(GPIOZ_0, EE_OFF), + GPIO_GROUP(GPIOZ_1, EE_OFF), + GPIO_GROUP(GPIOZ_2, EE_OFF), + GPIO_GROUP(GPIOZ_3, EE_OFF), + GPIO_GROUP(GPIOZ_4, EE_OFF), + GPIO_GROUP(GPIOZ_5, EE_OFF), + GPIO_GROUP(GPIOZ_6, EE_OFF), + GPIO_GROUP(GPIOZ_7, EE_OFF), + GPIO_GROUP(GPIOZ_8, EE_OFF), + GPIO_GROUP(GPIOZ_9, EE_OFF), + GPIO_GROUP(GPIOZ_10, EE_OFF), + + GPIO_GROUP(BOOT_0, EE_OFF), + GPIO_GROUP(BOOT_1, EE_OFF), + GPIO_GROUP(BOOT_2, EE_OFF), + GPIO_GROUP(BOOT_3, EE_OFF), + GPIO_GROUP(BOOT_4, EE_OFF), + GPIO_GROUP(BOOT_5, EE_OFF), + GPIO_GROUP(BOOT_6, EE_OFF), + GPIO_GROUP(BOOT_7, EE_OFF), + GPIO_GROUP(BOOT_8, EE_OFF), + GPIO_GROUP(BOOT_9, EE_OFF), + GPIO_GROUP(BOOT_10, EE_OFF), + GPIO_GROUP(BOOT_11, EE_OFF), + GPIO_GROUP(BOOT_12, EE_OFF), + GPIO_GROUP(BOOT_13, EE_OFF), + GPIO_GROUP(BOOT_14, EE_OFF), + + GPIO_GROUP(GPIOA_0, EE_OFF), + GPIO_GROUP(GPIOA_1, EE_OFF), + GPIO_GROUP(GPIOA_2, EE_OFF), + GPIO_GROUP(GPIOA_3, EE_OFF), + GPIO_GROUP(GPIOA_4, EE_OFF), + GPIO_GROUP(GPIOA_5, EE_OFF), + GPIO_GROUP(GPIOA_6, EE_OFF), + GPIO_GROUP(GPIOA_7, EE_OFF), + GPIO_GROUP(GPIOA_8, EE_OFF), + GPIO_GROUP(GPIOA_9, EE_OFF), + GPIO_GROUP(GPIOA_10, EE_OFF), + GPIO_GROUP(GPIOA_11, EE_OFF), + GPIO_GROUP(GPIOA_12, EE_OFF), + GPIO_GROUP(GPIOA_13, EE_OFF), + GPIO_GROUP(GPIOA_14, EE_OFF), + GPIO_GROUP(GPIOA_15, EE_OFF), + GPIO_GROUP(GPIOA_16, EE_OFF), + GPIO_GROUP(GPIOA_17, EE_OFF), + GPIO_GROUP(GPIOA_19, EE_OFF), + GPIO_GROUP(GPIOA_20, EE_OFF), + + GPIO_GROUP(GPIOX_0, EE_OFF), + GPIO_GROUP(GPIOX_1, EE_OFF), + GPIO_GROUP(GPIOX_2, EE_OFF), + GPIO_GROUP(GPIOX_3, EE_OFF), + GPIO_GROUP(GPIOX_4, EE_OFF), + GPIO_GROUP(GPIOX_5, EE_OFF), + GPIO_GROUP(GPIOX_6, EE_OFF), + GPIO_GROUP(GPIOX_7, EE_OFF), + GPIO_GROUP(GPIOX_8, EE_OFF), + GPIO_GROUP(GPIOX_9, EE_OFF), + GPIO_GROUP(GPIOX_10, EE_OFF), + GPIO_GROUP(GPIOX_11, EE_OFF), + GPIO_GROUP(GPIOX_12, EE_OFF), + GPIO_GROUP(GPIOX_13, EE_OFF), + GPIO_GROUP(GPIOX_14, EE_OFF), + GPIO_GROUP(GPIOX_15, EE_OFF), + GPIO_GROUP(GPIOX_16, EE_OFF), + GPIO_GROUP(GPIOX_17, EE_OFF), + GPIO_GROUP(GPIOX_18, EE_OFF), + GPIO_GROUP(GPIOX_19, EE_OFF), + GPIO_GROUP(GPIOX_20, EE_OFF), + GPIO_GROUP(GPIOX_21, EE_OFF), + GPIO_GROUP(GPIOX_22, EE_OFF), + + GPIO_GROUP(GPIOY_0, EE_OFF), + GPIO_GROUP(GPIOY_1, EE_OFF), + GPIO_GROUP(GPIOY_2, EE_OFF), + GPIO_GROUP(GPIOY_3, EE_OFF), + GPIO_GROUP(GPIOY_4, EE_OFF), + GPIO_GROUP(GPIOY_5, EE_OFF), + GPIO_GROUP(GPIOY_6, EE_OFF), + GPIO_GROUP(GPIOY_7, EE_OFF), + GPIO_GROUP(GPIOY_8, EE_OFF), + GPIO_GROUP(GPIOY_9, EE_OFF), + GPIO_GROUP(GPIOY_10, EE_OFF), + GPIO_GROUP(GPIOY_11, EE_OFF), + GPIO_GROUP(GPIOY_12, EE_OFF), + GPIO_GROUP(GPIOY_13, EE_OFF), + GPIO_GROUP(GPIOY_14, EE_OFF), + GPIO_GROUP(GPIOY_15, EE_OFF), + + /* bank BOOT */ + GROUP(emmc_nand_d0, 1), + GROUP(emmc_nand_d1, 1), + GROUP(emmc_nand_d2, 1), + GROUP(emmc_nand_d3, 1), + GROUP(emmc_nand_d4, 1), + GROUP(emmc_nand_d5, 1), + GROUP(emmc_nand_d6, 1), + GROUP(emmc_nand_d7, 1), + GROUP(emmc_clk, 1), + GROUP(emmc_cmd, 1), + GROUP(emmc_ds, 1), + GROUP(nand_ce0, 2), + GROUP(nand_ale, 2), + GROUP(nand_cle, 2), + GROUP(nand_wen_clk, 2), + GROUP(nand_ren_wr, 2), + GROUP(nand_rb0, 2), + GROUP(nor_hold, 3), + GROUP(nor_d, 3), + GROUP(nor_q, 3), + GROUP(nor_c, 3), + GROUP(nor_wp, 3), + GROUP(nor_cs, 3), + + /* bank GPIOZ */ + GROUP(spi0_clk, 1), + GROUP(spi0_mosi, 1), + GROUP(spi0_miso, 1), + GROUP(spi0_ss0, 1), + GROUP(spi0_ss1, 1), + GROUP(spi0_ss2, 1), + GROUP(i2c0_sck, 1), + GROUP(i2c0_sda, 1), + GROUP(i2c1_sck_z, 1), + GROUP(i2c1_sda_z, 1), + GROUP(uart_rts_b_z, 2), + GROUP(uart_cts_b_z, 2), + GROUP(uart_tx_b_z, 2), + GROUP(uart_rx_b_z, 2), + GROUP(pwm_a_z, 2), + GROUP(pwm_b_z, 2), + GROUP(spdif_in_z, 3), + GROUP(spdif_out_z, 3), + GROUP(uart_ao_tx_b_z, 2), + GROUP(uart_ao_rx_b_z, 2), + GROUP(uart_ao_cts_b_z, 2), + GROUP(uart_ao_rts_b_z, 2), + + /* bank GPIOX */ + GROUP(sdio_d0, 1), + GROUP(sdio_d1, 1), + GROUP(sdio_d2, 1), + GROUP(sdio_d3, 1), + GROUP(sdio_clk, 1), + GROUP(sdio_cmd, 1), + GROUP(i2c1_sck_x, 1), + GROUP(i2c1_sda_x, 1), + GROUP(i2c2_sck_x, 1), + GROUP(i2c2_sda_x, 1), + GROUP(uart_rts_a, 1), + GROUP(uart_cts_a, 1), + GROUP(uart_tx_a, 1), + GROUP(uart_rx_a, 1), + GROUP(uart_rts_b_x, 2), + GROUP(uart_cts_b_x, 2), + GROUP(uart_tx_b_x, 2), + GROUP(uart_rx_b_x, 2), + GROUP(jtag_tdo_x, 2), + GROUP(jtag_tdi_x, 2), + GROUP(jtag_clk_x, 2), + GROUP(jtag_tms_x, 2), + GROUP(spi1_clk_x, 4), + GROUP(spi1_mosi_x, 4), + GROUP(spi1_miso_x, 4), + GROUP(spi1_ss0_x, 4), + GROUP(pwm_a_x18, 3), + GROUP(pwm_a_x20, 1), + GROUP(pwm_b_x, 3), + GROUP(pwm_c_x10, 3), + GROUP(pwm_c_x17, 3), + GROUP(pwm_d_x11, 3), + GROUP(pwm_d_x16, 3), + GROUP(eth_txd0_x, 4), + GROUP(eth_txd1_x, 4), + GROUP(eth_txen_x, 4), + GROUP(eth_rgmii_rx_clk_x, 4), + GROUP(eth_rxd0_x, 4), + GROUP(eth_rxd1_x, 4), + GROUP(eth_rx_dv_x, 4), + GROUP(eth_mdio_x, 4), + GROUP(eth_mdc_x, 4), + GROUP(tdma_sclk, 1), + GROUP(tdma_sclk_slv, 2), + GROUP(tdma_fs, 1), + GROUP(tdma_fs_slv, 2), + GROUP(tdma_din0, 1), + GROUP(tdma_dout0_x14, 2), + GROUP(tdma_dout0_x15, 1), + GROUP(tdma_dout1, 2), + GROUP(tdma_din1, 3), + + /* bank GPIOY */ + GROUP(eth_txd0_y, 1), + GROUP(eth_txd1_y, 1), + GROUP(eth_txen_y, 1), + GROUP(eth_rgmii_rx_clk_y, 1), + GROUP(eth_rxd0_y, 1), + GROUP(eth_rxd1_y, 1), + GROUP(eth_rx_dv_y, 1), + GROUP(eth_mdio_y, 1), + GROUP(eth_mdc_y, 1), + GROUP(eth_rxd2_rgmii, 1), + GROUP(eth_rxd3_rgmii, 1), + GROUP(eth_rgmii_tx_clk, 1), + GROUP(eth_txd2_rgmii, 1), + GROUP(eth_txd3_rgmii, 1), + + /* bank GPIOA */ + GROUP(spdif_out_a1, 4), + GROUP(spdif_out_a11, 3), + GROUP(spdif_out_a19, 2), + GROUP(spdif_out_a20, 1), + GROUP(spdif_in_a1, 3), + GROUP(spdif_in_a7, 3), + GROUP(spdif_in_a19, 1), + GROUP(spdif_in_a20, 2), + GROUP(spi1_clk_a, 3), + GROUP(spi1_mosi_a, 3), + GROUP(spi1_miso_a, 3), + GROUP(spi1_ss0_a, 3), + GROUP(spi1_ss1, 3), + GROUP(pwm_a_a, 3), + GROUP(pwm_b_a, 3), + GROUP(pwm_c_a, 3), + GROUP(pwm_vs, 2), + GROUP(i2c2_sda_a, 3), + GROUP(i2c2_sck_a, 3), + GROUP(i2c3_sda_a6, 4), + GROUP(i2c3_sck_a7, 4), + GROUP(i2c3_sda_a12, 4), + GROUP(i2c3_sck_a13, 4), + GROUP(i2c3_sda_a19, 4), + GROUP(i2c3_sck_a20, 4), + GROUP(pdm_dclk_a14, 1), + GROUP(pdm_dclk_a19, 3), + GROUP(pdm_din0, 1), + GROUP(pdm_din1, 1), + GROUP(pdm_din2, 1), + GROUP(pdm_din3, 1), + GROUP(mclk_c, 1), + GROUP(mclk_b, 1), + GROUP(tdmc_sclk, 1), + GROUP(tdmc_sclk_slv, 2), + GROUP(tdmc_fs, 1), + GROUP(tdmc_fs_slv, 2), + GROUP(tdmc_din0, 2), + GROUP(tdmc_dout0, 1), + GROUP(tdmc_din1, 2), + GROUP(tdmc_dout1, 1), + GROUP(tdmc_din2, 2), + GROUP(tdmc_dout2, 1), + GROUP(tdmc_din3, 2), + GROUP(tdmc_dout3, 1), + GROUP(tdmb_sclk, 1), + GROUP(tdmb_sclk_slv, 2), + GROUP(tdmb_fs, 1), + GROUP(tdmb_fs_slv, 2), + GROUP(tdmb_din0, 2), + GROUP(tdmb_dout0, 1), + GROUP(tdmb_din1, 2), + GROUP(tdmb_dout1, 1), + GROUP(tdmb_din2, 2), + GROUP(tdmb_dout2, 1), + GROUP(tdmb_din3, 2), + GROUP(tdmb_dout3, 1), +}; + +/* uart_ao_a */ +static const unsigned int uart_ao_tx_a_pins[] = {GPIOAO_0}; +static const unsigned int uart_ao_rx_a_pins[] = {GPIOAO_1}; +static const unsigned int uart_ao_cts_a_pins[] = {GPIOAO_2}; +static const unsigned int uart_ao_rts_a_pins[] = {GPIOAO_3}; + +/* uart_ao_b */ +static const unsigned int uart_ao_tx_b_pins[] = {GPIOAO_4}; +static const unsigned int uart_ao_rx_b_pins[] = {GPIOAO_5}; +static const unsigned int uart_ao_cts_b_pins[] = {GPIOAO_2}; +static const unsigned int uart_ao_rts_b_pins[] = {GPIOAO_3}; + +/* i2c_ao */ +static const unsigned int i2c_ao_sck_4_pins[] = {GPIOAO_4}; +static const unsigned int i2c_ao_sda_5_pins[] = {GPIOAO_5}; +static const unsigned int i2c_ao_sck_8_pins[] = {GPIOAO_8}; +static const unsigned int i2c_ao_sda_9_pins[] = {GPIOAO_9}; +static const unsigned int i2c_ao_sck_10_pins[] = {GPIOAO_10}; +static const unsigned int i2c_ao_sda_11_pins[] = {GPIOAO_11}; + +/* i2c_ao_slave */ +static const unsigned int i2c_ao_slave_sck_pins[] = {GPIOAO_10}; +static const unsigned int i2c_ao_slave_sda_pins[] = {GPIOAO_11}; + +/* ir_in */ +static const unsigned int remote_input_ao_pins[] = {GPIOAO_6}; + +/* ir_out */ +static const unsigned int remote_out_ao_pins[] = {GPIOAO_7}; + +/* pwm_ao_a */ +static const unsigned int pwm_ao_a_pins[] = {GPIOAO_3}; + +/* pwm_ao_b */ +static const unsigned int pwm_ao_b_ao2_pins[] = {GPIOAO_2}; +static const unsigned int pwm_ao_b_ao12_pins[] = {GPIOAO_12}; + +/* pwm_ao_c */ +static const unsigned int pwm_ao_c_ao8_pins[] = {GPIOAO_8}; +static const unsigned int pwm_ao_c_ao13_pins[] = {GPIOAO_13}; + +/* pwm_ao_d */ +static const unsigned int pwm_ao_d_pins[] = {GPIOAO_9}; + +/* jtag_ao */ +static const unsigned int jtag_ao_tdi_pins[] = {GPIOAO_3}; +static const unsigned int jtag_ao_tdo_pins[] = {GPIOAO_4}; +static const unsigned int jtag_ao_clk_pins[] = {GPIOAO_5}; +static const unsigned int jtag_ao_tms_pins[] = {GPIOAO_7}; + +static struct meson_pmx_group meson_axg_aobus_groups[] = { + GPIO_GROUP(GPIOAO_0, 0), + GPIO_GROUP(GPIOAO_1, 0), + GPIO_GROUP(GPIOAO_2, 0), + GPIO_GROUP(GPIOAO_3, 0), + GPIO_GROUP(GPIOAO_4, 0), + GPIO_GROUP(GPIOAO_5, 0), + GPIO_GROUP(GPIOAO_6, 0), + GPIO_GROUP(GPIOAO_7, 0), + GPIO_GROUP(GPIOAO_8, 0), + GPIO_GROUP(GPIOAO_9, 0), + GPIO_GROUP(GPIOAO_10, 0), + GPIO_GROUP(GPIOAO_11, 0), + GPIO_GROUP(GPIOAO_12, 0), + GPIO_GROUP(GPIOAO_13, 0), + GPIO_GROUP(GPIO_TEST_N, 0), + + /* bank AO */ + GROUP(uart_ao_tx_a, 1), + GROUP(uart_ao_rx_a, 1), + GROUP(uart_ao_cts_a, 2), + GROUP(uart_ao_rts_a, 2), + GROUP(uart_ao_tx_b, 1), + GROUP(uart_ao_rx_b, 1), + GROUP(uart_ao_cts_b, 1), + GROUP(uart_ao_rts_b, 1), + GROUP(i2c_ao_sck_4, 2), + GROUP(i2c_ao_sda_5, 2), + GROUP(i2c_ao_sck_8, 2), + GROUP(i2c_ao_sda_9, 2), + GROUP(i2c_ao_sck_10, 2), + GROUP(i2c_ao_sda_11, 2), + GROUP(i2c_ao_slave_sck, 1), + GROUP(i2c_ao_slave_sda, 1), + GROUP(remote_input_ao, 1), + GROUP(remote_out_ao, 1), + GROUP(pwm_ao_a, 3), + GROUP(pwm_ao_b_ao2, 3), + GROUP(pwm_ao_b_ao12, 3), + GROUP(pwm_ao_c_ao8, 3), + GROUP(pwm_ao_c_ao13, 3), + GROUP(pwm_ao_d, 3), + GROUP(jtag_ao_tdi, 4), + GROUP(jtag_ao_tdo, 4), + GROUP(jtag_ao_clk, 4), + GROUP(jtag_ao_tms, 4), +}; + +static const char * const gpio_periphs_groups[] = { + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", + "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", + "GPIOZ_10", + + "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", + "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", + "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", + + "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4", + "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9", + "GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14", + "GPIOA_15", "GPIOA_16", "GPIOA_17", "GPIOA_18", "GPIOA_19", + "GPIOA_20", + + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", + "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", + "GPIOX_20", "GPIOX_21", "GPIOX_22", + + "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4", + "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9", + "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14", + "GPIOY_15", +}; + +static const char * const emmc_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", + "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", + "emmc_nand_d6", "emmc_nand_d7", + "emmc_clk", "emmc_cmd", "emmc_ds", +}; + +static const char * const nand_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", + "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", + "emmc_nand_d6", "emmc_nand_d7", + "nand_ce0", "nand_ale", "nand_cle", + "nand_wen_clk", "nand_ren_wr", "nand_rb0", +}; + +static const char * const nor_groups[] = { + "nor_d", "nor_q", "nor_c", "nor_cs", + "nor_hold", "nor_wp", +}; + +static const char * const sdio_groups[] = { + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", + "sdio_cmd", "sdio_clk", +}; + +static const char * const spi0_groups[] = { + "spi0_clk", "spi0_mosi", "spi0_miso", "spi0_ss0", + "spi0_ss1", "spi0_ss2" +}; + +static const char * const spi1_groups[] = { + "spi1_clk_x", "spi1_mosi_x", "spi1_miso_x", "spi1_ss0_x", + "spi1_clk_a", "spi1_mosi_a", "spi1_miso_a", "spi1_ss0_a", + "spi1_ss1" +}; + +static const char * const uart_a_groups[] = { + "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a", +}; + +static const char * const uart_b_groups[] = { + "uart_tx_b_z", "uart_rx_b_z", "uart_cts_b_z", "uart_rts_b_z", + "uart_tx_b_x", "uart_rx_b_x", "uart_cts_b_x", "uart_rts_b_x", +}; + +static const char * const uart_ao_b_z_groups[] = { + "uart_ao_tx_b_z", "uart_ao_rx_b_z", + "uart_ao_cts_b_z", "uart_ao_rts_b_z", +}; + +static const char * const i2c0_groups[] = { + "i2c0_sck", "i2c0_sda", +}; + +static const char * const i2c1_groups[] = { + "i2c1_sck_z", "i2c1_sda_z", + "i2c1_sck_x", "i2c1_sda_x", +}; + +static const char * const i2c2_groups[] = { + "i2c2_sck_x", "i2c2_sda_x", + "i2c2_sda_a", "i2c2_sck_a", +}; + +static const char * const i2c3_groups[] = { + "i2c3_sda_a6", "i2c3_sck_a7", + "i2c3_sda_a12", "i2c3_sck_a13", + "i2c3_sda_a19", "i2c3_sck_a20", +}; + +static const char * const eth_groups[] = { + "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk", + "eth_txd2_rgmii", "eth_txd3_rgmii", + "eth_txd0_x", "eth_txd1_x", "eth_txen_x", "eth_rgmii_rx_clk_x", + "eth_rxd0_x", "eth_rxd1_x", "eth_rx_dv_x", "eth_mdio_x", + "eth_mdc_x", + "eth_txd0_y", "eth_txd1_y", "eth_txen_y", "eth_rgmii_rx_clk_y", + "eth_rxd0_y", "eth_rxd1_y", "eth_rx_dv_y", "eth_mdio_y", + "eth_mdc_y", +}; + +static const char * const pwm_a_groups[] = { + "pwm_a_z", "pwm_a_x18", "pwm_a_x20", "pwm_a_a", +}; + +static const char * const pwm_b_groups[] = { + "pwm_b_z", "pwm_b_x", "pwm_b_a", +}; + +static const char * const pwm_c_groups[] = { + "pwm_c_x10", "pwm_c_x17", "pwm_c_a", +}; + +static const char * const pwm_d_groups[] = { + "pwm_d_x11", "pwm_d_x16", +}; + +static const char * const pwm_vs_groups[] = { + "pwm_vs", +}; + +static const char * const spdif_out_groups[] = { + "spdif_out_z", "spdif_out_a1", "spdif_out_a11", + "spdif_out_a19", "spdif_out_a20", +}; + +static const char * const spdif_in_groups[] = { + "spdif_in_z", "spdif_in_a1", "spdif_in_a7", + "spdif_in_a19", "spdif_in_a20", +}; + +static const char * const jtag_ee_groups[] = { + "jtag_tdo_x", "jtag_tdi_x", "jtag_clk_x", + "jtag_tms_x", +}; + +static const char * const pdm_groups[] = { + "pdm_din0", "pdm_din1", "pdm_din2", "pdm_din3", + "pdm_dclk_a14", "pdm_dclk_a19", +}; + +static const char * const gpio_aobus_groups[] = { + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", + "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", + "GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13", + "GPIO_TEST_N", +}; + +static const char * const uart_ao_a_groups[] = { + "uart_ao_tx_a", "uart_ao_rx_a", "uart_ao_cts_a", "uart_ao_rts_a", +}; + +static const char * const uart_ao_b_groups[] = { + "uart_ao_tx_b", "uart_ao_rx_b", "uart_ao_cts_b", "uart_ao_rts_b", +}; + +static const char * const i2c_ao_groups[] = { + "i2c_ao_sck_4", "i2c_ao_sda_5", + "i2c_ao_sck_8", "i2c_ao_sda_9", + "i2c_ao_sck_10", "i2c_ao_sda_11", +}; + +static const char * const i2c_ao_slave_groups[] = { + "i2c_ao_slave_sck", "i2c_ao_slave_sda", +}; + +static const char * const remote_input_ao_groups[] = { + "remote_input_ao", +}; + +static const char * const remote_out_ao_groups[] = { + "remote_out_ao", +}; + +static const char * const pwm_ao_a_groups[] = { + "pwm_ao_a", +}; + +static const char * const pwm_ao_b_groups[] = { + "pwm_ao_b_ao2", "pwm_ao_b_ao12", +}; + +static const char * const pwm_ao_c_groups[] = { + "pwm_ao_c_ao8", "pwm_ao_c_ao13", +}; + +static const char * const pwm_ao_d_groups[] = { + "pwm_ao_d", +}; + +static const char * const jtag_ao_groups[] = { + "jtag_ao_tdi", "jtag_ao_tdo", "jtag_ao_clk", "jtag_ao_tms", +}; + +static const char * const mclk_c_groups[] = { + "mclk_c", +}; + +static const char * const mclk_b_groups[] = { + "mclk_b", +}; + +static const char * const tdma_groups[] = { + "tdma_sclk", "tdma_sclk_slv", "tdma_fs", "tdma_fs_slv", + "tdma_din0", "tdma_dout0_x14", "tdma_dout0_x15", "tdma_dout1", + "tdma_din1", +}; + +static const char * const tdmc_groups[] = { + "tdmc_sclk", "tdmc_sclk_slv", "tdmc_fs", "tdmc_fs_slv", + "tdmc_din0", "tdmc_dout0", "tdmc_din1", "tdmc_dout1", + "tdmc_din2", "tdmc_dout2", "tdmc_din3", "tdmc_dout3", +}; + +static const char * const tdmb_groups[] = { + "tdmb_sclk", "tdmb_sclk_slv", "tdmb_fs", "tdmb_fs_slv", + "tdmb_din0", "tdmb_dout0", "tdmb_din1", "tdmb_dout1", + "tdmb_din2", "tdmb_dout2", "tdmb_din3", "tdmb_dout3", +}; + +static struct meson_pmx_func meson_axg_periphs_functions[] = { + FUNCTION(gpio_periphs), + FUNCTION(emmc), + FUNCTION(nor), + FUNCTION(spi0), + FUNCTION(spi1), + FUNCTION(sdio), + FUNCTION(nand), + FUNCTION(uart_a), + FUNCTION(uart_b), + FUNCTION(uart_ao_b_z), + FUNCTION(i2c0), + FUNCTION(i2c1), + FUNCTION(i2c2), + FUNCTION(i2c3), + FUNCTION(eth), + FUNCTION(pwm_a), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_vs), + FUNCTION(spdif_out), + FUNCTION(spdif_in), + FUNCTION(jtag_ee), + FUNCTION(pdm), + FUNCTION(mclk_b), + FUNCTION(mclk_c), + FUNCTION(tdma), + FUNCTION(tdmb), + FUNCTION(tdmc), +}; + +static struct meson_pmx_func meson_axg_aobus_functions[] = { + FUNCTION(gpio_aobus), + FUNCTION(uart_ao_a), + FUNCTION(uart_ao_b), + FUNCTION(i2c_ao), + FUNCTION(i2c_ao_slave), + FUNCTION(remote_input_ao), + FUNCTION(remote_out_ao), + FUNCTION(pwm_ao_a), + FUNCTION(pwm_ao_b), + FUNCTION(pwm_ao_c), + FUNCTION(pwm_ao_d), + FUNCTION(jtag_ao), +}; + +static struct meson_bank meson_axg_periphs_banks[] = { + /* name first last pullen pull dir out in */ + BANK("Z", GPIOZ_0, GPIOZ_10, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), + BANK("BOOT", BOOT_0, BOOT_14, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), + BANK("A", GPIOA_0, GPIOA_20, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), + BANK("X", GPIOX_0, GPIOX_22, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), + BANK("Y", GPIOY_0, GPIOY_15, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), +}; + +static struct meson_bank meson_axg_aobus_banks[] = { + /* name first last pullen pull dir out in */ + BANK("AO", GPIOAO_0, GPIOAO_13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0), +}; + +static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = { + /* name first lask reg offset */ + BANK_PMX("Z", GPIOZ_0, GPIOZ_10, 0x2, 0), + BANK_PMX("BOOT", BOOT_0, BOOT_14, 0x0, 0), + BANK_PMX("A", GPIOA_0, GPIOA_20, 0xb, 0), + BANK_PMX("X", GPIOX_0, GPIOX_22, 0x4, 0), + BANK_PMX("Y", GPIOY_0, GPIOY_15, 0x8, 0), +}; + +static struct meson_axg_pmx_data meson_axg_periphs_pmx_banks_data = { + .pmx_banks = meson_axg_periphs_pmx_banks, + .num_pmx_banks = ARRAY_SIZE(meson_axg_periphs_pmx_banks), +}; + +static struct meson_pmx_bank meson_axg_aobus_pmx_banks[] = { + BANK_PMX("AO", GPIOAO_0, GPIOAO_13, 0x0, 0), +}; + +static struct meson_axg_pmx_data meson_axg_aobus_pmx_banks_data = { + .pmx_banks = meson_axg_aobus_pmx_banks, + .num_pmx_banks = ARRAY_SIZE(meson_axg_aobus_pmx_banks), +}; + +struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = { + .name = "periphs-banks", + .pin_base = 11, + .groups = meson_axg_periphs_groups, + .funcs = meson_axg_periphs_functions, + .banks = meson_axg_periphs_banks, + .num_pins = 100, + .num_groups = ARRAY_SIZE(meson_axg_periphs_groups), + .num_funcs = ARRAY_SIZE(meson_axg_periphs_functions), + .num_banks = ARRAY_SIZE(meson_axg_periphs_banks), + .gpio_driver = &meson_axg_gpio_driver, + .pmx_data = &meson_axg_periphs_pmx_banks_data, +}; + +struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = { + .name = "aobus-banks", + .pin_base = 0, + .groups = meson_axg_aobus_groups, + .funcs = meson_axg_aobus_functions, + .banks = meson_axg_aobus_banks, + .num_pins = 11, + .num_groups = ARRAY_SIZE(meson_axg_aobus_groups), + .num_funcs = ARRAY_SIZE(meson_axg_aobus_functions), + .num_banks = ARRAY_SIZE(meson_axg_aobus_banks), + .gpio_driver = &meson_axg_gpio_driver, + .pmx_data = &meson_axg_aobus_pmx_banks_data, +}; + +static const struct udevice_id meson_axg_pinctrl_match[] = { + { + .compatible = "amlogic,meson-axg-periphs-pinctrl", + .data = (ulong)&meson_axg_periphs_pinctrl_data, + }, + { + .compatible = "amlogic,meson-axg-aobus-pinctrl", + .data = (ulong)&meson_axg_aobus_pinctrl_data, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(meson_axg_pinctrl) = { + .name = "meson-axg-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(meson_axg_pinctrl_match), + .probe = meson_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct meson_pinctrl), + .ops = &meson_axg_pinctrl_ops, +}; diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.h b/drivers/pinctrl/meson/pinctrl-meson-axg.h new file mode 100644 index 0000000..c8d2b3a --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Jerome Brunet + * Copyright (C) 2017 Xingyu Chen + */ + +#ifndef __PINCTRL_MESON_AXG_H__ +#define __PINCTRL_MESON_AXG_H__ + +#include "pinctrl-meson.h" + +struct meson_pmx_bank { + const char *name; + unsigned int first; + unsigned int last; + unsigned int reg; + unsigned int offset; +}; + +struct meson_axg_pmx_data { + struct meson_pmx_bank *pmx_banks; + unsigned int num_pmx_banks; +}; + +#define BANK_PMX(n, f, l, r, o) \ + { \ + .name = n, \ + .first = f, \ + .last = l, \ + .reg = r, \ + .offset = o, \ + } + +struct meson_pmx_axg_data { + unsigned int func; +}; + +#define PMX_DATA(f) \ + { \ + .func = f, \ + } + +#define GROUP(grp, f) \ + { \ + .name = #grp, \ + .pins = grp ## _pins, \ + .num_pins = ARRAY_SIZE(grp ## _pins), \ + .data = (const struct meson_pmx_axg_data[]){ \ + PMX_DATA(f), \ + }, \ + } + +#define GPIO_GROUP(gpio, b) \ + { \ + .name = #gpio, \ + .pins = (const unsigned int[]){ PIN(gpio, b) }, \ + .num_pins = 1, \ + .data = (const struct meson_pmx_axg_data[]){ \ + PMX_DATA(0), \ + }, \ + } + +extern const struct pinctrl_ops meson_axg_pinctrl_ops; +extern const struct driver meson_axg_gpio_driver; + +#endif /* __PINCTRL_MESON_AXG_H__ */ From patchwork Fri Nov 9 15:26:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 150673 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3642ljp; Fri, 9 Nov 2018 07:38:56 -0800 (PST) X-Google-Smtp-Source: AJdET5f4Ofy7FmdpqYxdlmsuLL2bMmeF/aJa5UyR0cAok8TI9fXOWBefF6Tpbhd4IwZf0v9SljwB X-Received: by 2002:a17:906:3105:: with SMTP id 5-v6mr2258523ejx.122.1541777935903; Fri, 09 Nov 2018 07:38:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541777935; cv=none; d=google.com; s=arc-20160816; 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Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- drivers/clk/clk_meson.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk_meson.c b/drivers/clk/clk_meson.c index 509872b..87e959e 100644 --- a/drivers/clk/clk_meson.c +++ b/drivers/clk/clk_meson.c @@ -790,7 +790,7 @@ static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id) return -ENOENT; } - printf("clock %lu has rate %lu\n", id, rate); + debug("clock %lu has rate %lu\n", id, rate); return rate; } From patchwork Fri Nov 9 15:26:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 150674 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp5196ljp; Fri, 9 Nov 2018 07:40:25 -0800 (PST) X-Google-Smtp-Source: AJdET5fAtd0SFcVUMMlJE2OjLQE7dklWAg5OwSKbuLAkODpCg2OQ4nHm7QskTvndu6uvDwEKXJmg X-Received: by 2002:a50:b1db:: with SMTP id n27-v6mr2673815edd.128.1541778025573; Fri, 09 Nov 2018 07:40:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541778025; cv=none; d=google.com; s=arc-20160816; b=kmiVyVJLuYpFWDDI+BpGN7mkQ0C900CCsB4uejtWh7HX87T5mPJhp0RZQDP6SwmXP+ N3xdx5T9E2333bJyKn+zrIRfLXOXZ3ah9vND3Kg9FhiZ81Q0KDEWJdcBlItrdne5PwDI sqrBIT+T4uR72oIDUT6Z1e40Tbuvch9I8iFLta3KUIYLNHb3hC0nhE/sXPdTynWTx3GS ms8VNjqnxkbonSKFybcPQJWCy1Ykfo05VQpDO7NZacrYcntUXdkGiLXsKQklhagakpR0 fM3bSFWe8WPRo7IO+nH93W7CuC8R3F+GnkZHcdjB5b/pVsg89GuGfTP0h4gQQCFrL/wW IP6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature; bh=SQZ5nuzfs9HJzhOp6akSDilm5QnaKrW5Ot3Y5TK0HKA=; b=r0sBdQVFQwnww1fhkIJo5ImkhKOXUNz9zyCDdwyeNe6ZoBXf7+qOUMq+pWKRCtp7mq qOLNMxweGWQao8MzmhHccQOsXudjOho8DiyCLsofs2S1VPayRW3tl4cQ+wJcnKmDOilX mn8z6aaoKUzSIDLmj4lSLbeArk/QZv8AJFDJMckT4QHyfaGtOFp0iToFqkBL9BlghkMw EKkkxB4qxab+04pL46Yx9qMm2STIWcEP/SC7RbJ+WTWZIoTeMCWS8ZGFVoNePZ3o5ZKk mHu32ohCFfXV5412J9sscCFszuL/2tYzCnSlU9ZxRujinyYphK41349jsRoa83riTgvk E9tQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=0h6mlTSC; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. 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While very close to the Gx SoC family, we will need to handle a few thing which are different in this SoC. Rework the meson arch directory to prepare for this. Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- arch/arm/include/asm/arch-meson/clock-gx.h | 117 +++++++++++++++++++++++++ arch/arm/include/asm/arch-meson/clock.h | 117 ------------------------- arch/arm/include/asm/arch-meson/eth.h | 6 +- arch/arm/include/asm/arch-meson/mem.h | 3 +- arch/arm/mach-meson/Kconfig | 10 ++- arch/arm/mach-meson/Makefile | 3 +- arch/arm/mach-meson/board-common.c | 56 ++++++++++++ arch/arm/mach-meson/board-gx.c | 132 +++++++++++++++++++++++++++++ arch/arm/mach-meson/board.c | 130 ---------------------------- arch/arm/mach-meson/eth.c | 53 ------------ arch/arm/mach-meson/sm.c | 1 - board/amlogic/odroid-c2/odroid-c2.c | 6 +- board/amlogic/p212/p212.c | 6 +- board/amlogic/q200/q200.c | 4 +- drivers/clk/clk_meson.c | 2 +- 15 files changed, 328 insertions(+), 318 deletions(-) create mode 100644 arch/arm/include/asm/arch-meson/clock-gx.h delete mode 100644 arch/arm/include/asm/arch-meson/clock.h create mode 100644 arch/arm/mach-meson/board-common.c create mode 100644 arch/arm/mach-meson/board-gx.c delete mode 100644 arch/arm/mach-meson/board.c delete mode 100644 arch/arm/mach-meson/eth.c diff --git a/arch/arm/include/asm/arch-meson/clock-gx.h b/arch/arm/include/asm/arch-meson/clock-gx.h new file mode 100644 index 0000000..13a2e76 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/clock-gx.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - AmLogic, Inc. + * Copyright 2018 - Beniamino Galvani + */ +#ifndef _ARCH_MESON_CLOCK_GX_H_ +#define _ARCH_MESON_CLOCK_GX_H_ + +/* + * Clock controller register offsets + * + * Register offsets from the data sheet are listed in comment blocks below. + * Those offsets must be multiplied by 4 before adding them to the base address + * to get the right value + */ +#define SCR 0x2C /* 0x0b offset in data sheet */ +#define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */ + +#define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ +#define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ +#define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ +#define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */ +#define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ +#define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */ + +#define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */ +#define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */ + +#define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */ +#define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */ +#define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */ +#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ +#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ + +#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ +#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ +#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ +#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ +#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ +#define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */ +#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ +#define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */ +#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ + +#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ +#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ +#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ +#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */ +#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ +#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ +#define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ +#define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */ +#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ +#define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */ + +#define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */ +#define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */ +#define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */ +#define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */ +#define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */ +#define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */ +#define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */ + +#define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */ +#define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */ +#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */ +#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ +#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ + +#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */ +#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */ +#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */ + +#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ +#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ +#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ +#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ +#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ +#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ +#define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ +#define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ +#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ +#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ + +#define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */ +#define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */ +#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ +#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ + +#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ +#define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */ +#define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */ +#define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */ +#define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */ +#define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */ +#define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ +#define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ +#define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ +#define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ +#define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */ +#define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */ + +#define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */ +#define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */ +#define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */ +#define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */ + +#define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */ +#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */ +#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */ + +ulong meson_measure_clk_rate(unsigned int clk); + +#endif diff --git a/arch/arm/include/asm/arch-meson/clock.h b/arch/arm/include/asm/arch-meson/clock.h deleted file mode 100644 index c0ff00f..0000000 --- a/arch/arm/include/asm/arch-meson/clock.h +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 - AmLogic, Inc. - * Copyright 2018 - Beniamino Galvani - */ -#ifndef _ARCH_MESON_CLOCK_H_ -#define _ARCH_MESON_CLOCK_H_ - -/* - * Clock controller register offsets - * - * Register offsets from the data sheet are listed in comment blocks below. - * Those offsets must be multiplied by 4 before adding them to the base address - * to get the right value - */ -#define SCR 0x2C /* 0x0b offset in data sheet */ -#define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */ - -#define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ -#define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ -#define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ -#define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */ -#define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ -#define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */ - -#define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */ -#define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */ - -#define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */ -#define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */ -#define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */ -#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ -#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ - -#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ -#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ -#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ -#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ -#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ -#define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */ -#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ -#define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */ -#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ - -#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ -#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ -#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ -#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */ -#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ -#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ -#define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ -#define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */ -#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ -#define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */ - -#define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */ -#define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */ -#define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */ -#define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */ -#define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */ -#define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */ -#define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */ - -#define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */ -#define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */ -#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */ -#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ -#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ - -#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */ -#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */ -#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */ - -#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ -#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ -#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ -#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ -#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ -#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ -#define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ -#define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ -#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ -#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ - -#define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */ -#define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */ -#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ -#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ - -#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ -#define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */ -#define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */ -#define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */ -#define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */ -#define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */ -#define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */ -#define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ -#define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ -#define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ -#define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ -#define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ -#define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ -#define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */ -#define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */ - -#define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */ -#define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */ -#define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */ -#define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */ - -#define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */ -#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */ -#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */ - -ulong meson_measure_clk_rate(unsigned int clk); - -#endif diff --git a/arch/arm/include/asm/arch-meson/eth.h b/arch/arm/include/asm/arch-meson/eth.h index 1aa0872..08acc5c 100644 --- a/arch/arm/include/asm/arch-meson/eth.h +++ b/arch/arm/include/asm/arch-meson/eth.h @@ -10,13 +10,13 @@ #include enum { - /* Use GXL Internal RMII PHY */ - MESON_GXL_USE_INTERNAL_RMII_PHY = 1, + /* Use Internal RMII PHY */ + MESON_USE_INTERNAL_RMII_PHY = 1, }; /* Configure the Ethernet MAC with the requested interface mode * with some optional flags. */ -void meson_gx_eth_init(phy_interface_t mode, unsigned int flags); +void meson_eth_init(phy_interface_t mode, unsigned int flags); #endif /* __MESON_ETH_H__ */ diff --git a/arch/arm/include/asm/arch-meson/mem.h b/arch/arm/include/asm/arch-meson/mem.h index 6281833..a65100a 100644 --- a/arch/arm/include/asm/arch-meson/mem.h +++ b/arch/arm/include/asm/arch-meson/mem.h @@ -10,6 +10,7 @@ /* Configure the reserved memory zones exported by the secure registers * into EFI and DTB reserved memory entries. */ -void meson_gx_init_reserved_memory(void *fdt); +void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size); +void meson_init_reserved_memory(void *fdt); #endif /* __MESON_MEM_H__ */ diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 6f60167..6225417 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -8,25 +8,29 @@ config MESON64_COMMON select DM_SERIAL imply CMD_DM +config MESON_GX + bool + select MESON64_COMMON + choice prompt "Platform select" default MESON_GXBB config MESON_GXBB bool "GXBB" - select MESON64_COMMON + select MESON_GX help Select this if your SoC is an S905 config MESON_GXL bool "GXL" - select MESON64_COMMON + select MESON_GX help Select this if your SoC is an S905X/D or S805X config MESON_GXM bool "GXM" - select MESON64_COMMON + select MESON_GX help Select this if your SoC is an S912 diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile index 8ad9b3e..78345b4 100644 --- a/arch/arm/mach-meson/Makefile +++ b/arch/arm/mach-meson/Makefile @@ -2,4 +2,5 @@ # # Copyright (c) 2016 Beniamino Galvani -obj-y += board.o sm.o eth.o +obj-y += board-common.o sm.o +obj-$(CONFIG_MESON_GX) += board-gx.o diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c new file mode 100644 index 0000000..0446507 --- /dev/null +++ b/arch/arm/mach-meson/board-common.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Beniamino Galvani + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + const fdt64_t *val; + int offset; + int len; + + offset = fdt_path_offset(gd->fdt_blob, "/memory"); + if (offset < 0) + return -EINVAL; + + val = fdt_getprop(gd->fdt_blob, offset, "reg", &len); + if (len < sizeof(*val) * 2) + return -EINVAL; + + /* Use unaligned access since cache is still disabled */ + gd->ram_size = get_unaligned_be64(&val[1]); + + return 0; +} + +void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size) +{ + int ret; + + ret = fdt_add_mem_rsv(fdt, start, size); + if (ret) + printf("Could not reserve zone @ 0x%llx\n", start); + + if (IS_ENABLED(CONFIG_EFI_LOADER)) { + efi_add_memory_map(start, + ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT, + EFI_RESERVED_MEMORY_TYPE, false); + } +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} + diff --git a/arch/arm/mach-meson/board-gx.c b/arch/arm/mach-meson/board-gx.c new file mode 100644 index 0000000..f1397f8 --- /dev/null +++ b/arch/arm/mach-meson/board-gx.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Beniamino Galvani + * (C) Copyright 2018 Neil Armstrong + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Configure the reserved memory zones exported by the secure registers + * into EFI and DTB reserved memory entries. + */ +void meson_init_reserved_memory(void *fdt) +{ + u64 bl31_size, bl31_start; + u64 bl32_size, bl32_start; + u32 reg; + + /* + * Get ARM Trusted Firmware reserved memory zones in : + * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0 + * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL + * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL + */ + reg = readl(GX_AO_SEC_GP_CFG3); + + bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK) + >> GX_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K; + bl32_size = (reg & GX_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K; + + bl31_start = readl(GX_AO_SEC_GP_CFG5); + bl32_start = readl(GX_AO_SEC_GP_CFG4); + + /* + * Early Meson GX Firmware revisions did not provide the reserved + * memory zones in the registers, keep fixed memory zone handling. + */ + if (IS_ENABLED(CONFIG_MESON_GX) && + !reg && !bl31_start && !bl32_start) { + bl31_start = 0x10000000; + bl31_size = 0x200000; + } + + /* Add first 16MiB reserved zone */ + meson_board_add_reserved_memory(fdt, 0, GX_FIRMWARE_MEM_SIZE); + + /* Add BL31 reserved zone */ + if (bl31_start && bl31_size) + meson_board_add_reserved_memory(fdt, bl31_start, bl31_size); + + /* Add BL32 reserved zone */ + if (bl32_start && bl32_size) + meson_board_add_reserved_memory(fdt, bl32_start, bl32_size); +} + +phys_size_t get_effective_memsize(void) +{ + /* Size is reported in MiB, convert it in bytes */ + return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK) + >> GX_AO_MEM_SIZE_SHIFT) * SZ_1M; +} + +static struct mm_region gx_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0xc0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xc0000000UL, + .phys = 0xc0000000UL, + .size = 0x30000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = gx_mem_map; + +/* Configure the Ethernet MAC with the requested interface mode + * with some optional flags. + */ +void meson_eth_init(phy_interface_t mode, unsigned int flags) +{ + switch (mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set RGMII mode */ + setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF | + GX_ETH_REG_0_TX_PHASE(1) | + GX_ETH_REG_0_TX_RATIO(4) | + GX_ETH_REG_0_PHY_CLK_EN | + GX_ETH_REG_0_CLK_EN); + break; + + case PHY_INTERFACE_MODE_RMII: + /* Set RMII mode */ + out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK | + GX_ETH_REG_0_CLK_EN); + + /* Use GXL RMII Internal PHY */ + if (IS_ENABLED(CONFIG_MESON_GXL) && + (flags & MESON_USE_INTERNAL_RMII_PHY)) { + writel(0x10110181, GX_ETH_REG_2); + writel(0xe40908ff, GX_ETH_REG_3); + } + + break; + + default: + printf("Invalid Ethernet interface mode\n"); + return; + } + + /* Enable power gate */ + clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK); +} diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c deleted file mode 100644 index d6c6253..0000000 --- a/arch/arm/mach-meson/board.c +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Beniamino Galvani - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - const fdt64_t *val; - int offset; - int len; - - offset = fdt_path_offset(gd->fdt_blob, "/memory"); - if (offset < 0) - return -EINVAL; - - val = fdt_getprop(gd->fdt_blob, offset, "reg", &len); - if (len < sizeof(*val) * 2) - return -EINVAL; - - /* Use unaligned access since cache is still disabled */ - gd->ram_size = get_unaligned_be64(&val[1]); - - return 0; -} - -phys_size_t get_effective_memsize(void) -{ - /* Size is reported in MiB, convert it in bytes */ - return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK) - >> GX_AO_MEM_SIZE_SHIFT) * SZ_1M; -} - -static void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size) -{ - int ret; - - ret = fdt_add_mem_rsv(fdt, start, size); - if (ret) - printf("Could not reserve zone @ 0x%llx\n", start); - - if (IS_ENABLED(CONFIG_EFI_LOADER)) { - efi_add_memory_map(start, - ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT, - EFI_RESERVED_MEMORY_TYPE, false); - } -} - -void meson_gx_init_reserved_memory(void *fdt) -{ - u64 bl31_size, bl31_start; - u64 bl32_size, bl32_start; - u32 reg; - - /* - * Get ARM Trusted Firmware reserved memory zones in : - * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0 - * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL - * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL - */ - - reg = readl(GX_AO_SEC_GP_CFG3); - - bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK) - >> GX_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K; - bl32_size = (reg & GX_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K; - - bl31_start = readl(GX_AO_SEC_GP_CFG5); - bl32_start = readl(GX_AO_SEC_GP_CFG4); - - /* - * Early Meson GX Firmware revisions did not provide the reserved - * memory zones in the registers, keep fixed memory zone handling. - */ - if (IS_ENABLED(CONFIG_MESON_GX) && - !reg && !bl31_start && !bl32_start) { - bl31_start = 0x10000000; - bl31_size = 0x200000; - } - - /* Add first 16MiB reserved zone */ - meson_board_add_reserved_memory(fdt, 0, GX_FIRMWARE_MEM_SIZE); - - /* Add BL31 reserved zone */ - if (bl31_start && bl31_size) - meson_board_add_reserved_memory(fdt, bl31_start, bl31_size); - - /* Add BL32 reserved zone */ - if (bl32_start && bl32_size) - meson_board_add_reserved_memory(fdt, bl32_start, bl32_size); -} - -void reset_cpu(ulong addr) -{ - psci_system_reset(); -} - -static struct mm_region gx_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0xc0000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xc0000000UL, - .phys = 0xc0000000UL, - .size = 0x30000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = gx_mem_map; diff --git a/arch/arm/mach-meson/eth.c b/arch/arm/mach-meson/eth.c deleted file mode 100644 index 8b28bc8..0000000 --- a/arch/arm/mach-meson/eth.c +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 BayLibre, SAS - * Author: Neil Armstrong - */ - -#include -#include -#include -#include -#include -#include - -/* Configure the Ethernet MAC with the requested interface mode - * with some optional flags. - */ -void meson_gx_eth_init(phy_interface_t mode, unsigned int flags) -{ - switch (mode) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: - /* Set RGMII mode */ - setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF | - GX_ETH_REG_0_TX_PHASE(1) | - GX_ETH_REG_0_TX_RATIO(4) | - GX_ETH_REG_0_PHY_CLK_EN | - GX_ETH_REG_0_CLK_EN); - break; - - case PHY_INTERFACE_MODE_RMII: - /* Set RMII mode */ - out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK | - GX_ETH_REG_0_CLK_EN); - - /* Use GXL RMII Internal PHY */ - if (IS_ENABLED(CONFIG_MESON_GXL) && - (flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) { - writel(0x10110181, GX_ETH_REG_2); - writel(0xe40908ff, GX_ETH_REG_3); - } - - break; - - default: - printf("Invalid Ethernet interface mode\n"); - return; - } - - /* Enable power gate */ - clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK); -} diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c index 0bba5e4..a07b468 100644 --- a/arch/arm/mach-meson/sm.c +++ b/arch/arm/mach-meson/sm.c @@ -6,7 +6,6 @@ */ #include -#include #include #define FN_GET_SHARE_MEM_INPUT_BASE 0x82000020 diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c index 2a2755c..d784d6b 100644 --- a/board/amlogic/odroid-c2/odroid-c2.c +++ b/board/amlogic/odroid-c2/odroid-c2.c @@ -28,7 +28,7 @@ int misc_init_r(void) char serial[EFUSE_SN_SIZE]; ssize_t len; - meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0); + meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0); if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, @@ -40,7 +40,7 @@ int misc_init_r(void) if (!env_get("serial#")) { len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, EFUSE_SN_SIZE); - if (len == EFUSE_SN_SIZE) + if (len == EFUSE_SN_SIZE) env_set("serial#", serial); } @@ -49,7 +49,7 @@ int misc_init_r(void) int ft_board_setup(void *blob, bd_t *bd) { - meson_gx_init_reserved_memory(blob); + meson_init_reserved_memory(blob); return 0; } diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c index 00e07d7..33992a2 100644 --- a/board/amlogic/p212/p212.c +++ b/board/amlogic/p212/p212.c @@ -29,8 +29,8 @@ int misc_init_r(void) char serial[EFUSE_SN_SIZE]; ssize_t len; - meson_gx_eth_init(PHY_INTERFACE_MODE_RMII, - MESON_GXL_USE_INTERNAL_RMII_PHY); + meson_eth_init(PHY_INTERFACE_MODE_RMII, + MESON_USE_INTERNAL_RMII_PHY); if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, @@ -51,7 +51,7 @@ int misc_init_r(void) int ft_board_setup(void *blob, bd_t *bd) { - meson_gx_init_reserved_memory(blob); + meson_init_reserved_memory(blob); return 0; } diff --git a/board/amlogic/q200/q200.c b/board/amlogic/q200/q200.c index ff56569..b59c11b 100644 --- a/board/amlogic/q200/q200.c +++ b/board/amlogic/q200/q200.c @@ -29,7 +29,7 @@ int misc_init_r(void) char serial[EFUSE_SN_SIZE]; ssize_t len; - meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0); + meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0); /* Reset PHY on GPIOZ_14 */ clrbits_le32(GX_GPIO_EN(3), BIT(14)); @@ -56,7 +56,7 @@ int misc_init_r(void) int ft_board_setup(void *blob, bd_t *bd) { - meson_gx_init_reserved_memory(blob); + meson_init_reserved_memory(blob); return 0; } diff --git a/drivers/clk/clk_meson.c b/drivers/clk/clk_meson.c index 87e959e..978f646 100644 --- a/drivers/clk/clk_meson.c +++ b/drivers/clk/clk_meson.c @@ -6,7 +6,7 @@ */ #include -#include +#include #include #include #include From patchwork Fri Nov 9 15:26:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 150675 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp5522ljp; Fri, 9 Nov 2018 07:40:43 -0800 (PST) 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[81.169.180.215]) by mx.google.com with ESMTP id n10-v6si1447027ejh.45.2018.11.09.07.40.42; Fri, 09 Nov 2018 07:40:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b="OSh/ARh8"; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 7BFB6C225AF; Fri, 9 Nov 2018 15:39:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A62B4C225F4; Fri, 9 Nov 2018 15:27:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1BC37C225CB; Fri, 9 Nov 2018 15:27:24 +0000 (UTC) Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by lists.denx.de (Postfix) with ESMTPS id 24A1FC2257D for ; Fri, 9 Nov 2018 15:27:19 +0000 (UTC) Received: by mail-wr1-f66.google.com with SMTP id j17-v6so2289382wrq.11 for ; Fri, 09 Nov 2018 07:27:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Y+UJM3V6FGLyTbcr+bB0FiLM9q9P4woDvF4P6452wIo=; b=OSh/ARh8nW0F4uypMaJKIfXCIOCCLBkO/ahdFOxUk9RI+2oB56etNtu7wiCCc4+Blz s+VoIbwo/l+gAdjGmzmML6WwBlk8cm2oLCZcyBpzbLK7+CgMrN+0VHicv3J09jb1T3kq dGUyffknATHEL+SkoiqPFoAqvI0CfLIiiRwjYl4Kuwi57pxXY9zf4BKyBvAYdPtNeMl4 xgfSLs65WHK0ps+66TgBE6nOEhP0sw2Db8A9bm9CWsJQST08+NYIKZrWry6BP/d21QRG bHLk5/69t1h0cXq6SlqtNb9abKiolUamTBNUbsOpTaIQL34ZsoEvUhAXhD90smxX5zJ9 L4kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y+UJM3V6FGLyTbcr+bB0FiLM9q9P4woDvF4P6452wIo=; b=cMyucyBURnyr1T6vRezJDQWpdE1sjWxgh+8HYOuaUvD/j69u3iy0mn07r78ZsfNnxm EHDK9+J3nlvlsMEARVMlob8HWYzBp26grqMVtTJ4ZN+7APuVuo6QxN07HMlsUkfLMNb7 ZnwEEe4KByEnwnLXD+GSI+pPS2TWJX70NTMJoDypKw06MPs3IZQKtUZ30lzoR+x5aM4h yH6hwAYsBBWbx6E+khK6YXouq0CsUJcWj81AkgDcr1wY3OBD8IzQfdbMTUEVIsDsAd+/ prRYbP8GULQNLb3dRRYBx9u+khOXaU5szu0jVtUd1NHuMfi/bpqcQ03OfUXWM6xP/u/s jouw== X-Gm-Message-State: AGRZ1gLDWAHwG1fGOgROobsA8/7kC/OiPjwlwpji9WoWqsRbH/VFSqr0 EzKCM6Z5+fRo75xOv3ySM8sGk1qeRu8= X-Received: by 2002:adf:bc0c:: with SMTP id s12-v6mr2645032wrg.255.1541777238434; Fri, 09 Nov 2018 07:27:18 -0800 (PST) Received: from bender.baylibre.local ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id a127-v6sm1748545wmh.24.2018.11.09.07.27.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Nov 2018 07:27:17 -0800 (PST) From: Neil Armstrong To: u-boot@lists.denx.de Date: Fri, 9 Nov 2018 16:26:57 +0100 Message-Id: <1541777218-472-19-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1541777218-472-1-git-send-email-narmstrong@baylibre.com> References: <1541777218-472-1-git-send-email-narmstrong@baylibre.com> Cc: linux-amlogic@lists.infradead.org, trini@konsulko.com, Jerome Brunet Subject: [U-Boot] [PATCH u-boot 18/19] ARM: meson: factorize common code out amlogic's boards X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jerome Brunet Now we have moved all the Amlogic board support to common generic board code, we can move the identical board_init() and ft_board_setup() functions to weak functions into the board-common mach-meson file. Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- arch/arm/mach-meson/board-common.c | 17 +++++++++++++++++ board/amlogic/odroid-c2/odroid-c2.c | 12 ------------ board/amlogic/p212/p212.c | 12 ------------ board/amlogic/q200/q200.c | 12 ------------ board/amlogic/s400/s400.c | 12 ------------ 5 files changed, 17 insertions(+), 48 deletions(-) diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c index 0446507..249e0d9 100644 --- a/arch/arm/mach-meson/board-common.c +++ b/arch/arm/mach-meson/board-common.c @@ -14,6 +14,11 @@ DECLARE_GLOBAL_DATA_PTR; +__weak int board_init(void) +{ + return 0; +} + int dram_init(void) { const fdt64_t *val; @@ -34,6 +39,18 @@ int dram_init(void) return 0; } +__weak int meson_ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + meson_init_reserved_memory(blob); + + return meson_ft_board_setup(blob, bd); +} + void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size) { int ret; diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c index d784d6b..62f0f4c 100644 --- a/board/amlogic/odroid-c2/odroid-c2.c +++ b/board/amlogic/odroid-c2/odroid-c2.c @@ -17,11 +17,6 @@ #define EFUSE_MAC_OFFSET 52 #define EFUSE_MAC_SIZE 6 -int board_init(void) -{ - return 0; -} - int misc_init_r(void) { u8 mac_addr[EFUSE_MAC_SIZE]; @@ -46,10 +41,3 @@ int misc_init_r(void) return 0; } - -int ft_board_setup(void *blob, bd_t *bd) -{ - meson_init_reserved_memory(blob); - - return 0; -} diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c index 33992a2..546c4d9 100644 --- a/board/amlogic/p212/p212.c +++ b/board/amlogic/p212/p212.c @@ -18,11 +18,6 @@ #define EFUSE_MAC_OFFSET 52 #define EFUSE_MAC_SIZE 6 -int board_init(void) -{ - return 0; -} - int misc_init_r(void) { u8 mac_addr[EFUSE_MAC_SIZE]; @@ -48,10 +43,3 @@ int misc_init_r(void) return 0; } - -int ft_board_setup(void *blob, bd_t *bd) -{ - meson_init_reserved_memory(blob); - - return 0; -} diff --git a/board/amlogic/q200/q200.c b/board/amlogic/q200/q200.c index b59c11b..6db1b26 100644 --- a/board/amlogic/q200/q200.c +++ b/board/amlogic/q200/q200.c @@ -18,11 +18,6 @@ #define EFUSE_MAC_OFFSET 52 #define EFUSE_MAC_SIZE 6 -int board_init(void) -{ - return 0; -} - int misc_init_r(void) { u8 mac_addr[EFUSE_MAC_SIZE]; @@ -53,10 +48,3 @@ int misc_init_r(void) return 0; } - -int ft_board_setup(void *blob, bd_t *bd) -{ - meson_init_reserved_memory(blob); - - return 0; -} diff --git a/board/amlogic/s400/s400.c b/board/amlogic/s400/s400.c index c2b50f6..02a0e92 100644 --- a/board/amlogic/s400/s400.c +++ b/board/amlogic/s400/s400.c @@ -13,21 +13,9 @@ #include #include -int board_init(void) -{ - return 0; -} - int misc_init_r(void) { meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0); return 0; } - -int ft_board_setup(void *blob, bd_t *bd) -{ - meson_init_reserved_memory(blob); - - return 0; -}