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Thu, 9 Dec 2021 05:48:23 -0800 From: Akhil R To: , , , , , , , , , , , , , CC: Subject: [PATCH] i2c: tegra: use i2c_timings for bus clock freq Date: Thu, 9 Dec 2021 19:17:48 +0530 Message-ID: <1639057668-14377-1-git-send-email-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8cde6373-903f-402b-c6ee-08d9bb1aa077 X-MS-TrafficTypeDiagnostic: MN2PR12MB4584:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:513; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LeagAhG65+sliZ2LEnvznZxN78F3X758ZFHqL/ovQCg28EysL/ZWA4jysYhTdl04rCyEeIevxWetQZIZ/g/VZdPDwSEVd/Jemb4lBolyq6rh32yjWR6Fdasrdnq2hXHlOVrXmOHLc8GzJ3gr8xk/qv/VzVdcdBze0HNofKcS6LgbFXkGSilkTYBwgCEeUh38thpQTJB4/ZwZ9ZE5Xj13SislUIpgI0Cfpae2fU5utuS1s8o9slaBh4wzwOg4lXS3OIEibWeE914sg03gxAobDIZyPrY25Ii4hxIEH2muBJ+IO8koav4fJ4JgSxISSm+LMo4hcejs90tQ4IocBTF4c43N8P6rWST+EWXBH/01H1VQUvDKHLMNQdacOGeF1XX+FXCY8dqWUVuhaAa4vRV3jCazXseM7jpSKnqPMRk97SoBSVrcyzXl83jIDYhjgbzwMfRHJ+J6iAH9JaWIBshaf8zJpS6Cjw2J8VkWX2GoleJusQ1cQmj9gQjpUoytd0/cE5XMFl/UJmxiUaAMqs74nAmE5nZw7simzJ+VvIjNF/hEC27tPXVFUPvyAq+foxhJVyzArnePjswvDj8VXq9QS69I710gM9JBga1JtOPE/UQa/rcaJEVP0UchJGierR45i0aXMt0XA8YCcJdXJe8IEk1W8rSYt1kEg8l0HpKSB/eKlWRsJ6kIqd7tjVwksavjM7eiBDznHX3UDc310ntbaIac5AXlcDIHU6wEHKO9vd6F+Eiohj83IzqNZhYvcq7Owouso78x93BOHRTeaPsfwVAcvEBQfSpAADvf9FL917knVEpd3Wx+DnWpnAqFNR8S88BinE417KmTLiskbKvW/prvMEKD+ng40SO6kM84BIylvUThXLD5+HoVrPbiRM6YCVO5MoBFkFaGDVVAtobMOkQd7P/SNfrMawKaQFrG8DAqsPG7i7DmCUdJRZ3P9WTB X-Forefront-Antispam-Report: CIP:203.18.50.14; CTRY:HK; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:hkhybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(40470700001)(316002)(186003)(426003)(508600001)(7696005)(921005)(47076005)(70206006)(36756003)(36860700001)(34020700004)(26005)(110136005)(356005)(8676002)(83380400001)(4326008)(70586007)(2906002)(40460700001)(2616005)(5660300002)(86362001)(82310400004)(6666004)(966005)(107886003)(8936002)(7416002)(7636003)(336012)(83996005)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2021 13:48:48.0540 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8cde6373-903f-402b-c6ee-08d9bb1aa077 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[203.18.50.14]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4584 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Use i2c_timings struct and corresponding methods to get bus clock frequency Signed-off-by: Akhil R --- drivers/i2c/busses/i2c-tegra.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) The patch is in response to the discussion in a previous patch to use i2c_timings struct for bus freq. ref. https://lkml.org/lkml/2021/11/25/767 diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index a5be8f0..ffd2ad2 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -246,7 +246,7 @@ struct tegra_i2c_hw_feature { * @msg_buf: pointer to current message data * @msg_buf_remaining: size of unsent data in the message buffer * @msg_read: indicates that the transfer is a read access - * @bus_clk_rate: current I2C bus clock rate + * @timings: i2c timings information like bus frequency * @multimaster_mode: indicates that I2C controller is in multi-master mode * @tx_dma_chan: DMA transmit channel * @rx_dma_chan: DMA receive channel @@ -273,7 +273,7 @@ struct tegra_i2c_dev { unsigned int nclocks; struct clk *div_clk; - u32 bus_clk_rate; + struct i2c_timings timings; struct completion msg_complete; size_t msg_buf_remaining; @@ -642,14 +642,14 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) if (i2c_dev->is_vi) tegra_i2c_vi_init(i2c_dev); - switch (i2c_dev->bus_clk_rate) { + switch (i2c_dev->timings.bus_freq_hz) { case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: default: tlow = i2c_dev->hw->tlow_fast_fastplus_mode; thigh = i2c_dev->hw->thigh_fast_fastplus_mode; tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; - if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ) + if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; else non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; @@ -685,7 +685,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); err = clk_set_rate(i2c_dev->div_clk, - i2c_dev->bus_clk_rate * clk_multiplier); + i2c_dev->timings.bus_freq_hz * clk_multiplier); if (err) { dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err); return err; @@ -724,7 +724,7 @@ static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) * before disabling the controller so that the STOP condition has * been delivered properly. */ - udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); + udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz)); cnfg = i2c_readl(i2c_dev, I2C_CNFG); if (cnfg & I2C_CNFG_PACKET_MODE_EN) @@ -1254,7 +1254,7 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits */ xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC, - i2c_dev->bus_clk_rate); + i2c_dev->timings.bus_freq_hz); int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; tegra_i2c_unmask_irq(i2c_dev, int_mask); @@ -1633,10 +1633,7 @@ static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) bool multi_mode; int err; - err = device_property_read_u32(i2c_dev->dev, "clock-frequency", - &i2c_dev->bus_clk_rate); - if (err) - i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; + i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true); multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master"); i2c_dev->multimaster_mode = multi_mode;