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Thu, 9 Dec 2021 16:28:48 +0000 From: Akhil R To: , , , , , , , , , , , , , CC: Subject: [PATCH v2] i2c: tegra: use i2c_timings for bus clock freq Date: Thu, 9 Dec 2021 21:58:38 +0530 Message-ID: <1639067318-29014-1-git-send-email-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d8b3e4d9-cf3d-4d60-18b6-08d9bb30ff30 X-MS-TrafficTypeDiagnostic: CH0PR12MB5140:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:513; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Mn/ETjGNYkBtbcb/HJilpXXXI1zIBUX2qh5MjKCesbIZsfL2COg3tLOrLhNTB7dl1KkwAAcC2EyO+fCtX2hSgZ1bPkQ5QIN+GljoIjnFCpMGWo0IYaRhvG04QWdK/G5TnhtEgzWY9Oku6lEH9pR8NPzn2UGPEnF9pri7AtCGfKl88BH47rwJt1iNtfPQ2VFpdx4tAteF44Pp1ROl9AxKY4Qs2HuP14Q6QorC8gohvuYE/Xp+afubMSa5F+7di5aGYWvIL/9GtiFcCZuSAUIQFuUzAti4O/J2urzAYztr3ozNU5HtnYu4yPTyEQbBvYV+p7BLHRykrPjj37vxNdps90MZbTo3yruBrYYAs7UYdyUTqDPqoH8OjzEWuwyJzTTcEvisb2zahKPzSTZBWhHzwQ3SdGotDiW3tZqe0BrrJzwZTJ9o0qC82L+gE1WjQpFXfbBY9Ge3AiqOkHETR0sgfhjefbFi9mVTGW4HgTyxtybOnVgUZnyo6rtbnVCOn2wUQiJ/0cneuenJ4a+S31OKDEz8F6TKKhue5UwKii3A5ya0zsJrpUy1eOxUkPExli0VC9vNBAKniXPiNdQJrvCeNV9T87pIlTOX+r2GOZeuGJ4C+/gTzUSCaQSt6xxmOBUKRayEYBfLT2JtKCnrjG2rLLrpFi3sBQAOVo1SilpKZd/LUu/Ct0nm0QoqoSx1IhkeIB1a/sxK13UeKIr00W0Zt1RqFxI2BF1rFuDCCRkDqSHnSrT26VlqqZ6+G6PP/QS4UqkxDDrNNIY4hCcyImiOETIwABqYaa+TEYnBWgUT6JvUCOlTzfA0atKLlVkiZxtO4M1hsWVofWM3cuhvCMbnz9mdp/BzfnA9MBlI4Mu9UMM= X-Forefront-Antispam-Report: CIP:203.18.50.13; CTRY:HK; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:hkhybrid02.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(40470700001)(107886003)(316002)(7416002)(8936002)(26005)(2906002)(82310400004)(110136005)(4326008)(7696005)(36860700001)(34020700004)(83380400001)(36756003)(356005)(40460700001)(47076005)(7636003)(2616005)(5660300002)(86362001)(8676002)(921005)(508600001)(336012)(6666004)(426003)(70206006)(70586007)(186003)(2101003)(83996005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2021 16:28:56.0365 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8b3e4d9-cf3d-4d60-18b6-08d9bb30ff30 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[203.18.50.13]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5140 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Use i2c_timings struct and corresponding methods to get bus clock frequency Signed-off-by: Akhil R Suggested-by: Andy Shevchenko Reviewed-by: Andy Shevchenko --- drivers/i2c/busses/i2c-tegra.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) v1->v2: Added temp var for i2c_timings struct in function. diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index a5be8f0..4cbe89b 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -246,7 +246,7 @@ struct tegra_i2c_hw_feature { * @msg_buf: pointer to current message data * @msg_buf_remaining: size of unsent data in the message buffer * @msg_read: indicates that the transfer is a read access - * @bus_clk_rate: current I2C bus clock rate + * @timings: i2c timings information like bus frequency * @multimaster_mode: indicates that I2C controller is in multi-master mode * @tx_dma_chan: DMA transmit channel * @rx_dma_chan: DMA receive channel @@ -273,7 +273,7 @@ struct tegra_i2c_dev { unsigned int nclocks; struct clk *div_clk; - u32 bus_clk_rate; + struct i2c_timings timings; struct completion msg_complete; size_t msg_buf_remaining; @@ -610,6 +610,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) { u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; acpi_handle handle = ACPI_HANDLE(i2c_dev->dev); + struct i2c_timings *t = &i2c_dev->timings; int err; /* @@ -642,14 +643,14 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) if (i2c_dev->is_vi) tegra_i2c_vi_init(i2c_dev); - switch (i2c_dev->bus_clk_rate) { + switch (t->bus_freq_hz) { case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: default: tlow = i2c_dev->hw->tlow_fast_fastplus_mode; thigh = i2c_dev->hw->thigh_fast_fastplus_mode; tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; - if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ) + if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; else non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; @@ -685,7 +686,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); err = clk_set_rate(i2c_dev->div_clk, - i2c_dev->bus_clk_rate * clk_multiplier); + t->bus_freq_hz * clk_multiplier); if (err) { dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err); return err; @@ -724,7 +725,7 @@ static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) * before disabling the controller so that the STOP condition has * been delivered properly. */ - udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); + udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz)); cnfg = i2c_readl(i2c_dev, I2C_CNFG); if (cnfg & I2C_CNFG_PACKET_MODE_EN) @@ -1254,7 +1255,7 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits */ xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC, - i2c_dev->bus_clk_rate); + i2c_dev->timings.bus_freq_hz); int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; tegra_i2c_unmask_irq(i2c_dev, int_mask); @@ -1633,10 +1634,7 @@ static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) bool multi_mode; int err; - err = device_property_read_u32(i2c_dev->dev, "clock-frequency", - &i2c_dev->bus_clk_rate); - if (err) - i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; + i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true); multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master"); i2c_dev->multimaster_mode = multi_mode;