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Mon, 6 Dec 2021 14:05:43 +0000 From: Prathamesh Shete To: , , , , , , , CC: , , Subject: [PATCH v3] mmc: sdhci-tegra: Fix switch to HS400ES mode Date: Mon, 6 Dec 2021 19:35:41 +0530 Message-ID: <20211206140541.17148-1-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a47afdad-65a5-49b6-4d16-08d9b8c1d5b2 X-MS-TrafficTypeDiagnostic: BY5PR12MB3924:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3044; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: XDzgy/JzkvUPHMUORQnwf+r2NsuhQiJgMeQyPlEzzlubfkM+Z7MxcwAlr6n/PHzCNz29ccBi4N0qWsdJdJJiX/elVRXGa+7IRuLyNTdUt5bNxBjsxPgZ43jgh6wSQNmNsZq5fzA1dPxe5xIL+x8Cee8D/8mTFopwcHY0oEZunQOYVdhHOjcvta/+SfjdISLcUK4okUajuZyosHAC0nMU6CQexo8a1ZmicsJmVy569HVPZ8+tBI7f9rwuMMcxPOK+GYxSjGo4751lRVu/0FTbJv0S7VS9t33hnO8CZh1HiFvt3Q4vkJNO4yDxqb3itvYwJQouSCSX7jq8GepDg/R9SFjt8tTvXqinBhufrzHfx9/h6DSfHIBq9/vuN3/nhco7APtCG/EQrnNNhKYr2RnbNLke10fHu9nDvvoLjJ4WuW5c1aWC8wRGArOxHDHn6rTyyVaVRW+oPNenEUa98LuD3kZ4/9G/jpvmT4HQeKds80dkPXRsWjIs2CAwTRWlq+Ta21avG4yMXFNybQOh9pgJGPPICGALKo16c8+7Mc5qw5KhO12t4Oi8j3SWwq6KSL3NJlPpqwAHYTlww++uhNMfqQpilZop0nn3f9vrxhnU56IKEX4u1fA2FY4hzJW65LtSb+JQtYQ4EamTViR+130YPLY/KR14yuzONJU1/U6qefamvsrALpLXMMCJnQ7uEi6c4NevDyikOrfXXjbTiSgpcABqeGRd0uMiupb6ie4L01zdyl2OPQpxOrg9UoPl9/xRYNOfclbdm7DcgJ65xvX5BA== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(40470700001)(316002)(47076005)(8936002)(107886003)(508600001)(26005)(36756003)(83380400001)(5660300002)(186003)(426003)(336012)(4326008)(110136005)(2616005)(7636003)(70586007)(70206006)(2906002)(40460700001)(7696005)(1076003)(356005)(86362001)(54906003)(82310400004)(8676002)(36860700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2021 14:07:10.0438 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a47afdad-65a5-49b6-4d16-08d9b8c1d5b2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3924 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org When CMD13 is sent after switching to HS400ES mode, the bus is operating at either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR. To meet Tegra SDHCI requirement at HS400ES mode, force SDHCI interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host controller CAR clock and the interface clock are rate matched. Signed-off-by: Prathamesh Shete Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-tegra.c | 43 ++++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 387ce9cdbd7c..ddaa3d9000f6 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -354,23 +354,6 @@ static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) } } -static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, - struct mmc_ios *ios) -{ - struct sdhci_host *host = mmc_priv(mmc); - u32 val; - - val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); - - if (ios->enhanced_strobe) - val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; - else - val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; - - sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); - -} - static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -791,6 +774,32 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) } } +static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + struct sdhci_host *host = mmc_priv(mmc); + u32 val; + + val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); + + if (ios->enhanced_strobe) { + val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; + /* + * When CMD13 is sent from mmc_select_hs400es() after + * switching to HS400ES mode, the bus is operating at + * either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR. + * To meet Tegra SDHCI requirement at HS400ES mode, force SDHCI + * interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host + * controller CAR clock and the interface clock are rate matched. + */ + tegra_sdhci_set_clock(host, MMC_HS200_MAX_DTR); + } else { + val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; + } + + sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); +} + static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);