From patchwork Wed Dec 1 19:04:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 519583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24A94C43217 for ; Wed, 1 Dec 2021 19:05:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352596AbhLATIX (ORCPT ); Wed, 1 Dec 2021 14:08:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352125AbhLATIV (ORCPT ); Wed, 1 Dec 2021 14:08:21 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55C86C06174A for ; Wed, 1 Dec 2021 11:05:00 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id bi37so65441107lfb.5 for ; Wed, 01 Dec 2021 11:05:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AQDun0CJwvM7UQvnluW9dd4LbyUPdKYwbZE5uoVdvOU=; b=QOk2jhLZBSZEjsNg2ZX1HZj7ZbL+gPrU3uTZXF+74C1Ft+LZaIX1QFe6IJAx5gnOgA paxpTFYYkNdavEuXOkFJ0ZIdc5CoYLme8f6QRac/t2rnhsOatPMKm32BkvILVocK5Hk1 6RJRTCzL2qpF4gPlfwrZM3w2v1/o0iW0+WfDOF+aJ0zyj7ym8KGnFenEjcku1pTbKsXh qob0S81qBKydaiMxE9p3+SVbmd2nWI9vPBgmjIki+eDYUAYkYAG0btWmVeJ4LYINwHT/ 3dXghxZoWDQh0Jc8CF1pEvjL1g2fEiAApP2X1/6mJKD98YguTIr+EaI+6aexxCj/G0ap tZcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AQDun0CJwvM7UQvnluW9dd4LbyUPdKYwbZE5uoVdvOU=; b=FUVehHWg7ok3BL6+iZHnA+d8ctqfAcB/XjD9SppkaW+XuNbeX2QsomO/SrKYuHNBUR +RjhLYRoCWBiFG4qnNLgd14u4d9dbm76gENVQw8gkLpvlaczTCREVfNvKEpZuoL4Xyeu 3dNG6FauU6ruS+y5PbdiNY0Lx/NRt66f0SQDLQOeyXRYfanCv4ckEYZmjo9CyYf943Db WZWqPR+WQ1T5nK6xhc9nxpGo944iVI9Fpif9GFRoscx9JLWfUTHoPEcVsWwXKdrTo6NT pCUN0fsgwCPaHkd4KpsURuN5Ir34wC2wWo4uCJeSBzSEYMMgTN98aLF0/JYo11V+bHk4 ddSQ== X-Gm-Message-State: AOAM533xzvlYzQZEu1QqvtFIs1213eCXzKf52iwY8AHczFwRbtREQowZ 1PnpSuGi9fodr71KyByQGLq/Kg== X-Google-Smtp-Source: ABdhPJyinqe77utFYvpWzDgZHKPTgwSqv6ZB2SE7iZkufbtEZi8kvrFdCnQkRYOITN+HkdDtvYDHMA== X-Received: by 2002:a05:6512:36c9:: with SMTP id e9mr7617984lfs.87.1638385498478; Wed, 01 Dec 2021 11:04:58 -0800 (PST) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id m9sm72412ljg.80.2021.12.01.11.04.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Dec 2021 11:04:58 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Wolfram Sang , Arnd Bergmann , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 1/6] dt-bindings: i2c: exynos5: Convert to dtschema Date: Wed, 1 Dec 2021 21:04:50 +0200 Message-Id: <20211201190455.31646-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211201190455.31646-1-semen.protsenko@linaro.org> References: <20211201190455.31646-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Convert Samsung Exynos High Speed I2C bindings doc to DT schema format. Changes during bindings conversion: 1. Added missing required clock properties (driver fails when it's unable to get the clock) 2. Removed properties and descriptions that can be found in schemas/i2c/i2c-controller.yaml [1] 3. Fixed the example so it can be validated by dtschema [1] https://github.com/robherring/dt-schema/blob/master/schemas/i2c/i2c-controller.yaml Signed-off-by: Sam Protsenko --- .../devicetree/bindings/i2c/i2c-exynos5.txt | 53 ------------ .../devicetree/bindings/i2c/i2c-exynos5.yaml | 80 +++++++++++++++++++ 2 files changed, 80 insertions(+), 53 deletions(-) delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-exynos5.txt create mode 100644 Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt deleted file mode 100644 index 2dbc0b62daa6..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Samsung's High Speed I2C controller - -The Samsung's High Speed I2C controller is used to interface with I2C devices -at various speeds ranging from 100khz to 3.4Mhz. - -Required properties: - - compatible: value should be. - -> "samsung,exynos5-hsi2c", (DEPRECATED) - for i2c compatible with HSI2C available - on Exynos5250 and Exynos5420 SoCs. - -> "samsung,exynos5250-hsi2c", for i2c compatible with HSI2C available - on Exynos5250 and Exynos5420 SoCs. - -> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available - on Exynos5260 SoCs. - -> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available - on Exynos7 SoCs. - - - reg: physical base address of the controller and length of memory mapped - region. - - interrupts: interrupt number to the cpu. - - #address-cells: always 1 (for i2c addresses) - - #size-cells: always 0 - - - Pinctrl: - - pinctrl-0: Pin control group to be used for this controller. - - pinctrl-names: Should contain only one value - "default". - -Optional properties: - - clock-frequency: Desired operating frequency in Hz of the bus. - -> If not specified, the bus operates in fast-speed mode at - at 100khz. - -> If specified, the bus operates in high-speed mode only if the - clock-frequency is >= 1Mhz. - -Example: - -hsi2c@12ca0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12ca0000 0x100>; - interrupts = <56>; - clock-frequency = <100000>; - - pinctrl-0 = <&i2c4_bus>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - }; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml new file mode 100644 index 000000000000..53df1571eff1 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/i2c-exynos5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung's High Speed I2C controller + +maintainers: + - Krzysztof Kozlowski + +description: | + The Samsung's High Speed I2C controller is used to interface with I2C devices + at various speeds ranging from 100kHz to 3.4MHz. + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + oneOf: + - enum: + - "samsung,exynos5250-hsi2c" # Exynos5250 and Exynos5420 + - "samsung,exynos5260-hsi2c" # Exynos5260 + - "samsung,exynos7-hsi2c" # Exynos7 + - const: "samsung,exynos5-hsi2c" # Exynos5250 and Exynos5420 + deprecated: true + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-frequency: + default: 100000 + description: + Desired operating frequency in Hz of the bus. + + If not specified, the bus operates in fast-speed mode at 100kHz. + + If specified, the bus operates in high-speed mode only if the + clock-frequency is >= 1MHz. + + clocks: + maxItems: 1 + description: I2C operating clock + + clock-names: + const: hsi2c + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + hsi2c_8: i2c@12e00000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12e00000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + clocks = <&clock CLK_USI4>; + clock-names = "hsi2c"; + + pmic@66 { + /* compatible = "samsung,s2mps11-pmic"; */ + reg = <0x66>; + }; + }; From patchwork Wed Dec 1 19:04:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 520119 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7979CC4332F for ; Wed, 1 Dec 2021 19:05:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352608AbhLATIY (ORCPT ); Wed, 1 Dec 2021 14:08:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352412AbhLATIW (ORCPT ); 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Wed, 01 Dec 2021 11:04:59 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Wolfram Sang , Arnd Bergmann , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 2/6] dt-bindings: i2c: exynos5: Add exynosautov9-hsi2c compatible Date: Wed, 1 Dec 2021 21:04:51 +0200 Message-Id: <20211201190455.31646-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211201190455.31646-1-semen.protsenko@linaro.org> References: <20211201190455.31646-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Jaewon Kim This patch adds new "samsung,exynosautov9-hsi2c" compatible. It is for i2c compatible with HSI2C available on Exynos SoC with USI. Signed-off-by: Jaewon Kim Signed-off-by: Sam Protsenko --- Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml index 53df1571eff1..db20e703dea0 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml @@ -13,6 +13,11 @@ description: | The Samsung's High Speed I2C controller is used to interface with I2C devices at various speeds ranging from 100kHz to 3.4MHz. + In case the HSI2C controller is encapsulated within USI block (it's the case + e.g. for Exynos850 and Exynos Auto V9 SoCs), it might be also necessary to + define USI node in device tree file, choosing "i2c" configuration. Please see + Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml for details. + allOf: - $ref: /schemas/i2c/i2c-controller.yaml# @@ -23,6 +28,7 @@ properties: - "samsung,exynos5250-hsi2c" # Exynos5250 and Exynos5420 - "samsung,exynos5260-hsi2c" # Exynos5260 - "samsung,exynos7-hsi2c" # Exynos7 + - "samsung,exynosautov9-hsi2c" # ExynosAutoV9 - const: "samsung,exynos5-hsi2c" # Exynos5250 and Exynos5420 deprecated: true From patchwork Wed Dec 1 19:04:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 519582 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 195B9C433EF for ; Wed, 1 Dec 2021 19:05:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244979AbhLATI0 (ORCPT ); Wed, 1 Dec 2021 14:08:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352606AbhLATIY (ORCPT ); Wed, 1 Dec 2021 14:08:24 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1AC95C061756 for ; Wed, 1 Dec 2021 11:05:03 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id k37so65496129lfv.3 for ; Wed, 01 Dec 2021 11:05:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RUQx5kq3VrQOJzLJrHIG10H6hCDxVpxGzWKF98as5kk=; b=In8k5sq2384AcnFdRb15c2gEmINBS3KJi7PU5aATZmmOIwm71wY+dCo1UfvvCI8ubY JrQ/3mNIyh5OOfqFRcY9UCd8oSyhc1xh2Hpi7AMODLgBd2wdhiTIEkHae6+aks0/0TwF FYsmK/fu3LQa/TvYW3yTnL6PTiDnFX5+FGMKgA+K/G/y+7iwfx/Iu7gJ+oLFTNmwhoyz ZFdMWczP+U08BUVaO33E/meDGAYiFL22EwDK/QFaCnjmleEA10M7HnVLI/rWH+15Ob83 69+p04MC0BRa9jrE+tT0vrdcuq1CdRN4Q8nBf1UMHkGHjAf+VyPvTmYxwM3OK8CFund8 IiDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RUQx5kq3VrQOJzLJrHIG10H6hCDxVpxGzWKF98as5kk=; b=7viccbyaW6rg1Tqr3NxnTaMagRVHXj+E+F779ea8uMJmAHRTeKIMJQn3QHdfO/emrz nhR/wEuEF8G944tt78S86rehF66E2b3qDrE6tldEBQOzqwOdi3unHkSGmauNY6C0zgE9 H/z7wmnrYT2VC0egJwhg7BXQYKw0VxJgWkEvOBammJn4Q53c5ivQolL9gWD/AmK+HY4D wHBBCVmQR6SGl0IG/Cluo0EFSb9ejUs2jez+iKIXF217opQLIqmxb4Lc4zhkvV6Cc1uH FINtEPuMk+MinlEtlRimAkPMahZp6avgftVvUM3EIsPCNaPl9YhIw5+Mk6qbaBUWnRFT ej+Q== X-Gm-Message-State: AOAM532iN3+cRUVZPzI9UN0H3+iTul+I1Sp7lvwcvXV2Nvcc2ckB8SyB bY/lNm3cEsT9/dWy+gqD/WzLGg== X-Google-Smtp-Source: ABdhPJyXfA1Aj/HuZe6HAzGr6uRY6CRxqJOxRkA1rtTvcyqa/VFMR4R6HUAfwPmKzWFpso4Sn5/UEA== X-Received: by 2002:ac2:42c6:: with SMTP id n6mr7403216lfl.553.1638385501381; Wed, 01 Dec 2021 11:05:01 -0800 (PST) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id e20sm71103ljo.119.2021.12.01.11.05.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Dec 2021 11:05:00 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Wolfram Sang , Arnd Bergmann , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 3/6] dt-bindings: i2c: exynos5: Add bus clock Date: Wed, 1 Dec 2021 21:04:52 +0200 Message-Id: <20211201190455.31646-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211201190455.31646-1-semen.protsenko@linaro.org> References: <20211201190455.31646-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org In new Exynos SoCs (like Exynos850) where HSI2C is implemented as a part of USIv2 block, there are two clocks provided to HSI2C controller: - PCLK: bus clock (APB), provides access to register interface - IPCLK: operating IP-core clock; SCL is derived from this one Both clocks have to be asserted for HSI2C to be functional in that case. Modify bindings doc to allow specifying bus clock in addition to already described operating clock. Make it optional though, as older Exynos SoC variants only have one HSI2C clock. Signed-off-by: Sam Protsenko --- .../devicetree/bindings/i2c/i2c-exynos5.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml index db20e703dea0..a212c1d5e7d9 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml @@ -49,11 +49,16 @@ properties: clock-frequency is >= 1MHz. clocks: - maxItems: 1 - description: I2C operating clock + minItems: 1 + items: + - description: I2C operating clock + - description: Bus clock (APB) clock-names: - const: hsi2c + minItems: 1 + items: + - const: hsi2c + - const: hsi2c_pclk required: - compatible From patchwork Wed Dec 1 19:04:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 520117 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F315BC43217 for ; Wed, 1 Dec 2021 19:05:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352648AbhLATIr (ORCPT ); Wed, 1 Dec 2021 14:08:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352619AbhLATI0 (ORCPT ); Wed, 1 Dec 2021 14:08:26 -0500 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD52AC061757 for ; Wed, 1 Dec 2021 11:05:04 -0800 (PST) Received: by mail-lf1-x131.google.com with SMTP id bu18so65548702lfb.0 for ; Wed, 01 Dec 2021 11:05:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aAo5L8S04r7ipl+uXm9qNiK/iV6LQnGWXB0cFhZkmdM=; b=rHqvSkrjyON28Or7auVY6T++aDwISh/E4oAAgovbxJ8YKWassoYx1nH9Wc8W5t2LIK HpJh5rttDdFr4ReJ38i2CphfVYXPFEMq9biC78GRdUQjEjghLp02PoN+QxxnyTg86aoz x3oFQmBnuM2hXssgFYik2THgZO2aH6mELyKuHxUhg4/VKKWS0Lv1QA/cNVhBzFuf90I/ Hx2822kzjmdOk5XD2WFYwpBgKUd4rwVSzo9vKUPMWdohJEqv+KzCFXqOlap+2WR+VWPC pvPyBf368FB8oTBosJJYtbKCpTlu2rjQ8XG4qC2gwkRCCshNexVAI8DcQWGDEOU4vju1 70pQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aAo5L8S04r7ipl+uXm9qNiK/iV6LQnGWXB0cFhZkmdM=; b=lnEYmFWQAi9UWVcuNhtrSu+EMotpkm3qG0BF41cKSnGxUcmq/ISfd7VlE02WAUWXzk 5k9BT/xnhSLevVcy4pJZdIBPnywHGOEkr4pEh+Ay+nRz2co2I5lJSymuBbFxeod0htCx qlHWBQowlXHyrKFE0+5WTWaxDexswLwzKDVAlxDn5zYWrfWrApcadnS1zW8KzZGi5RWv GGbfugnXr3u1Aa5y9DqpMzjlNHiPmL7qFrgXH02hsnxGd8SHMFw/XauMFn/ZTAiC0Fs0 FLxFvTKxdyJkWCbWwqSVbVPYh1BkBT2bmO+AzXc72I6JEVcHmcYiyzFyRGL3blE2abKX 8Paw== X-Gm-Message-State: AOAM533maVXKHig0mfj8iPzmr8phPraIU8ziKQ/yTXFvmHkk3iWbZK+J JFwPcWP+mTgAH7Qsy4viRkgeuw== X-Google-Smtp-Source: ABdhPJyYuXcZhjzewZlCgGHfjAN9uPoQI44hRzrim9QZljFWb/IJjkjq+16q4MdxUHqa29lzRPl4qQ== X-Received: by 2002:a05:6512:11c5:: with SMTP id h5mr7501361lfr.431.1638385503089; Wed, 01 Dec 2021 11:05:03 -0800 (PST) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id p26sm72178ljj.70.2021.12.01.11.05.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Dec 2021 11:05:02 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Wolfram Sang , Arnd Bergmann , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 4/6] i2c: exynos5: Add support for ExynosAutoV9 SoC Date: Wed, 1 Dec 2021 21:04:53 +0200 Message-Id: <20211201190455.31646-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211201190455.31646-1-semen.protsenko@linaro.org> References: <20211201190455.31646-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Jaewon Kim ExynosAutoV9 functioning logic mostly follows I2C_TYPE_EXYNOS7, but timing calculation and configuration procedure is changed: e.g. only timing_s3 has to be set now. Another change of HSI2C controller in ExynosAutoV9 SoC is that it's now a part of USIv2 IP-core. No changes is needed for I2C driver though, as all USI related configuration is done in USI driver. Signed-off-by: Jaewon Kim Signed-off-by: Sam Protsenko --- drivers/i2c/busses/i2c-exynos5.c | 62 +++++++++++++++++++++++++++----- 1 file changed, 53 insertions(+), 9 deletions(-) diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c index c2e4bab11366..5198e71e8dab 100644 --- a/drivers/i2c/busses/i2c-exynos5.c +++ b/drivers/i2c/busses/i2c-exynos5.c @@ -169,6 +169,7 @@ enum i2c_type_exynos { I2C_TYPE_EXYNOS5, I2C_TYPE_EXYNOS7, + I2C_TYPE_EXYNOSAUTOV9, }; struct exynos5_i2c { @@ -230,6 +231,11 @@ static const struct exynos_hsi2c_variant exynos7_hsi2c_data = { .hw = I2C_TYPE_EXYNOS7, }; +static const struct exynos_hsi2c_variant exynosautov9_hsi2c_data = { + .fifo_depth = 64, + .hw = I2C_TYPE_EXYNOSAUTOV9, +}; + static const struct of_device_id exynos5_i2c_match[] = { { .compatible = "samsung,exynos5-hsi2c", @@ -243,6 +249,9 @@ static const struct of_device_id exynos5_i2c_match[] = { }, { .compatible = "samsung,exynos7-hsi2c", .data = &exynos7_hsi2c_data + }, { + .compatible = "samsung,exynosautov9-hsi2c", + .data = &exynosautov9_hsi2c_data }, {}, }; MODULE_DEVICE_TABLE(of, exynos5_i2c_match); @@ -281,6 +290,31 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings) i2c->op_clock; int div, clk_cycle, temp; + /* + * In case of HSI2C controllers in ExynosAutoV9: + * + * FSCL = IPCLK / ((CLK_DIV + 1) * 16) + * T_SCL_LOW = IPCLK * (CLK_DIV + 1) * (N + M) + * [N : number of 0's in the TSCL_H_HS] + * [M : number of 0's in the TSCL_L_HS] + * T_SCL_HIGH = IPCLK * (CLK_DIV + 1) * (N + M) + * [N : number of 1's in the TSCL_H_HS] + * [M : number of 1's in the TSCL_L_HS] + * + * Result of (N + M) is always 8. + * In general case, we don't need to control timing_s1 and timing_s2. + */ + if (i2c->variant->hw == I2C_TYPE_EXYNOSAUTOV9) { + div = ((clkin / (16 * i2c->op_clock)) - 1); + i2c_timing_s3 = div << 16; + if (hs_timings) + writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); + else + writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); + + return 0; + } + /* * In case of HSI2C controller in Exynos5 series * FPCLK / FI2C = @@ -422,7 +456,10 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id) writel(int_status, i2c->regs + HSI2C_INT_STATUS); /* handle interrupt related to the transfer status */ - if (i2c->variant->hw == I2C_TYPE_EXYNOS7) { + switch (i2c->variant->hw) { + case I2C_TYPE_EXYNOSAUTOV9: + fallthrough; + case I2C_TYPE_EXYNOS7: if (int_status & HSI2C_INT_TRANS_DONE) { i2c->trans_done = 1; i2c->state = 0; @@ -443,7 +480,12 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id) i2c->state = -ETIMEDOUT; goto stop; } - } else if (int_status & HSI2C_INT_I2C) { + + break; + case I2C_TYPE_EXYNOS5: + if (!(int_status & HSI2C_INT_I2C)) + break; + trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); if (trans_status & HSI2C_NO_DEV_ACK) { dev_dbg(i2c->dev, "No ACK from device\n"); @@ -465,6 +507,8 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id) i2c->trans_done = 1; i2c->state = 0; } + + break; } if ((i2c->msg->flags & I2C_M_RD) && (int_status & @@ -569,13 +613,13 @@ static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c) { unsigned long timeout; - if (i2c->variant->hw != I2C_TYPE_EXYNOS7) + if (i2c->variant->hw == I2C_TYPE_EXYNOS5) return; /* - * HSI2C_MASTER_ST_LOSE state in EXYNOS7 variant before transaction - * indicates that bus is stuck (SDA is low). In such case bus recovery - * can be performed. + * HSI2C_MASTER_ST_LOSE state (in Exynos7 and ExynosAutoV9 variants) + * before transaction indicates that bus is stuck (SDA is low). + * In such case bus recovery can be performed. */ timeout = jiffies + msecs_to_jiffies(100); for (;;) { @@ -611,10 +655,10 @@ static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop) unsigned long flags; unsigned short trig_lvl; - if (i2c->variant->hw == I2C_TYPE_EXYNOS7) - int_en |= HSI2C_INT_I2C_TRANS; - else + if (i2c->variant->hw == I2C_TYPE_EXYNOS5) int_en |= HSI2C_INT_I2C; + else + int_en |= HSI2C_INT_I2C_TRANS; i2c_ctl = readl(i2c->regs + HSI2C_CTL); i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON); From patchwork Wed Dec 1 19:04:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 519581 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2952FC43219 for ; Wed, 1 Dec 2021 19:05:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352638AbhLATIr (ORCPT ); Wed, 1 Dec 2021 14:08:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352632AbhLATI1 (ORCPT ); Wed, 1 Dec 2021 14:08:27 -0500 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44950C061756 for ; Wed, 1 Dec 2021 11:05:06 -0800 (PST) Received: by mail-lj1-x22f.google.com with SMTP id k23so50210077lje.1 for ; Wed, 01 Dec 2021 11:05:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xFxNqmuJVHm+4b6lR+Oly3cvobR2qTXZL1lEPZhFsrE=; b=RdnzaNKoUt5b+9agSRLYKRRF9nuVxJFlKMirK78Y43kiqglTOpkdctVQ1SKOm2eFRf 0xtzHaQg0RSsBmtrwxDFDaxljYRW0DBKq3YcdqJDvNC6l8Ghs81VvVpiO63Xtv5tfkXC OBie9N7C1xsNZ4MxtOhoHVtQCPHXcdbJHqRuRDoqEK+hJ4pg4aC4oDWjWiG3PDKNHOId 8sAN6So4lh2PBBJ1XM8KBXJ34ABpRQoGhR5z9Tl/z4NncAeieGYGVxnw9cBjXGLkblIo lTcHBIq0dIhFXBkgrmpj8XXl95XzDt1Hcle+tbSoVOzTe7H/1pB/f0YmmbjPdLjQE995 sbsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xFxNqmuJVHm+4b6lR+Oly3cvobR2qTXZL1lEPZhFsrE=; b=XT031E3hFSHWDTldtLsiZWIlG/UPpKifrob5RCNQrsveWOgrQZLFMzOLAlmQdCcKsQ iHzJ1kVGPDErAQlar8S7U99jTwadWxhBlrh9iKxbeffDuEm/2SMd3WcKCQZeoilC53Nf UHxEsT7GznpjhKf8k9cAoJbErczTm5I8KS8jG0mP7eozgsSNmD6a6oi3az4l7ig18UlQ D9/sdbxzO3ZgHTrjDg34k1gEcxdGM2Yor7efxhFt9LKb2bbNLUjYyZ4wu5CYSBxn+ops 7RG9N+4dgmYbp5WZCDFPgJfDAFxYjpsTKHIwN4tBvv/oGWTyGgYT8GW4Ae/T3wnaBgcO 4PmQ== X-Gm-Message-State: AOAM530qD7HDGYbDRZ+RGD+41mqRy5cVLq6TzOMSOV/NFy4gqYQOiVKQ 6kmeK3eggHTAmwxDQs/BpYgVIQ== X-Google-Smtp-Source: ABdhPJw9cTGW2HXAXJwsyWcNxIPUwF4D6YMKXKVz4KwpsKcwqB6bz/QYaDQRAoJPBAB71ZlXYeIOOg== X-Received: by 2002:a05:651c:106b:: with SMTP id y11mr7225777ljm.504.1638385504477; Wed, 01 Dec 2021 11:05:04 -0800 (PST) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id h17sm79175lfj.160.2021.12.01.11.05.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Dec 2021 11:05:04 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Wolfram Sang , Arnd Bergmann , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 5/6] i2c: exynos5: Add bus clock support Date: Wed, 1 Dec 2021 21:04:54 +0200 Message-Id: <20211201190455.31646-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211201190455.31646-1-semen.protsenko@linaro.org> References: <20211201190455.31646-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org In new Exynos SoCs (like Exynos850) where HSI2C is implemented as a part of USIv2 block, there are two clocks provided to HSI2C controller: - PCLK: bus clock (APB), provides access to register interface - IPCLK: operating IP-core clock; SCL is derived from this one Both clocks have to be asserted for HSI2C to be functional in that case. Add code to obtain and enable/disable PCLK in addition to already handled operating clock. Make it optional though, as older Exynos SoC variants only have one HSI2C clock. Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski Reviewed-by: Chanho Park --- drivers/i2c/busses/i2c-exynos5.c | 46 ++++++++++++++++++++++++++------ 1 file changed, 38 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c index 5198e71e8dab..9cde5ecb9449 100644 --- a/drivers/i2c/busses/i2c-exynos5.c +++ b/drivers/i2c/busses/i2c-exynos5.c @@ -182,7 +182,8 @@ struct exynos5_i2c { unsigned int irq; void __iomem *regs; - struct clk *clk; + struct clk *clk; /* operating clock */ + struct clk *pclk; /* bus clock */ struct device *dev; int state; @@ -757,10 +758,14 @@ static int exynos5_i2c_xfer(struct i2c_adapter *adap, struct exynos5_i2c *i2c = adap->algo_data; int i, ret; - ret = clk_enable(i2c->clk); + ret = clk_enable(i2c->pclk); if (ret) return ret; + ret = clk_enable(i2c->clk); + if (ret) + goto err_pclk; + for (i = 0; i < num; ++i) { ret = exynos5_i2c_xfer_msg(i2c, msgs + i, i + 1 == num); if (ret) @@ -768,6 +773,8 @@ static int exynos5_i2c_xfer(struct i2c_adapter *adap, } clk_disable(i2c->clk); +err_pclk: + clk_disable(i2c->pclk); return ret ?: num; } @@ -807,10 +814,18 @@ static int exynos5_i2c_probe(struct platform_device *pdev) return -ENOENT; } - ret = clk_prepare_enable(i2c->clk); + i2c->pclk = devm_clk_get(&pdev->dev, "hsi2c_pclk"); + if (IS_ERR(i2c->pclk)) + i2c->pclk = NULL; /* pclk is optional */ + + ret = clk_prepare_enable(i2c->pclk); if (ret) return ret; + ret = clk_prepare_enable(i2c->clk); + if (ret) + goto err_pclk; + i2c->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(i2c->regs)) { ret = PTR_ERR(i2c->regs); @@ -853,6 +868,7 @@ static int exynos5_i2c_probe(struct platform_device *pdev) platform_set_drvdata(pdev, i2c); clk_disable(i2c->clk); + clk_disable(i2c->pclk); dev_info(&pdev->dev, "%s: HSI2C adapter\n", dev_name(&i2c->adap.dev)); @@ -860,6 +876,9 @@ static int exynos5_i2c_probe(struct platform_device *pdev) err_clk: clk_disable_unprepare(i2c->clk); + + err_pclk: + clk_disable_unprepare(i2c->pclk); return ret; } @@ -870,6 +889,7 @@ static int exynos5_i2c_remove(struct platform_device *pdev) i2c_del_adapter(&i2c->adap); clk_unprepare(i2c->clk); + clk_unprepare(i2c->pclk); return 0; } @@ -881,6 +901,7 @@ static int exynos5_i2c_suspend_noirq(struct device *dev) i2c_mark_adapter_suspended(&i2c->adap); clk_unprepare(i2c->clk); + clk_unprepare(i2c->pclk); return 0; } @@ -890,21 +911,30 @@ static int exynos5_i2c_resume_noirq(struct device *dev) struct exynos5_i2c *i2c = dev_get_drvdata(dev); int ret = 0; - ret = clk_prepare_enable(i2c->clk); + ret = clk_prepare_enable(i2c->pclk); if (ret) return ret; + ret = clk_prepare_enable(i2c->clk); + if (ret) + goto err_pclk; + ret = exynos5_hsi2c_clock_setup(i2c); - if (ret) { - clk_disable_unprepare(i2c->clk); - return ret; - } + if (ret) + goto err_clk; exynos5_i2c_init(i2c); clk_disable(i2c->clk); + clk_disable(i2c->pclk); i2c_mark_adapter_resumed(&i2c->adap); return 0; + +err_clk: + clk_disable_unprepare(i2c->clk); +err_pclk: + clk_disable_unprepare(i2c->pclk); + return ret; } #endif From patchwork Wed Dec 1 19:04:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 520118 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52A64C433F5 for ; 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Wed, 01 Dec 2021 11:05:05 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Wolfram Sang , Arnd Bergmann , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 6/6] i2c: exynos5: Mention Exynos850 and ExynosAutoV9 in Kconfig Date: Wed, 1 Dec 2021 21:04:55 +0200 Message-Id: <20211201190455.31646-7-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211201190455.31646-1-semen.protsenko@linaro.org> References: <20211201190455.31646-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org I2C controller chosen by I2C_EXYNOS5 config option is also suitable for Exynos850 and ExynosAutoV9 SoCs. State that specifically in I2C_EXYNOS5 symbol help section. Signed-off-by: Sam Protsenko --- drivers/i2c/busses/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index df89cb809330..42da31c1ab70 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -617,7 +617,7 @@ config I2C_EXYNOS5 help High-speed I2C controller on Samsung Exynos5 and newer Samsung SoCs: Exynos5250, Exynos5260, Exynos5410, Exynos542x, Exynos5800, - Exynos5433 and Exynos7. + Exynos5433, Exynos7, Exynos850 and ExynosAutoV9. Choose Y here only if you build for such Samsung SoC. config I2C_GPIO