From patchwork Wed Dec 1 01:33:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 519494 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BAB7C433FE for ; Wed, 1 Dec 2021 01:34:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345076AbhLABhR (ORCPT ); Tue, 30 Nov 2021 20:37:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241240AbhLABhB (ORCPT ); Tue, 30 Nov 2021 20:37:01 -0500 Received: from mail-io1-xd31.google.com (mail-io1-xd31.google.com [IPv6:2607:f8b0:4864:20::d31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F077C061748; Tue, 30 Nov 2021 17:33:41 -0800 (PST) Received: by mail-io1-xd31.google.com with SMTP id z26so28638606iod.10; Tue, 30 Nov 2021 17:33:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dTtlcAd/4wi0l++svlS+iwW32G36swzSrzC7Ae74KpM=; b=Wh2vOhc3g70OZLTOyX4sGyowz0TD109nuF+VGGLuBUk37li6dFph1azPknrhemc0y2 xsJEg/S58uAT9vv1CHRcGEF9lEnSMk6b7WLxVh8G8k8Zjv1doQHfSg+iYNH0Tayz2qi7 XFuIs2vzoXC9pL2OihyXzmx9ftkXtcIcxM4FLE6rjmVIqqNsGPTr3PeqKH9MDuqkCzs7 h0vn5HhOA7JQOzZh7wdFrwa7ElFcWHOHGrKoZlIyLj7WEmgv/pYhjFTMD609yvIxrfU1 6FO764t5rcIQz+HCl5GUPFgSLrh4R8o8P4Y2JEIljJ89BJE+nRlaCemDKJXd9EK4y3Ll v2hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dTtlcAd/4wi0l++svlS+iwW32G36swzSrzC7Ae74KpM=; b=FgvWskOOX5aQmUShOocrgMYT1QrAU1rHuWaTkzaHIose+kayGAvDesjVo3b1/7Vrcu orhh33V733yYPgR+cBzHFt7Qk2Q/LMBRxRaps69K6RP0vEBKqU9x2Bbr87shBi25FQ8K EH7wuukS1/WiIj9G3NjN01KPTZldxnEzLVG+VXpRaflkSbzT766lJj8lQ194SDeJLbvG tK0BG34YABck69RKLUk0seyJfZV10t873EbEcXDVukE67UudokwncDJLUBWLb0OCPeBU Hb9h+fICj8Mr5Piq/nh4t0Mu19BsTHhHjRKJmKyB0h0/Zys7NfF2Cg8ttbmbDdvJ2d48 enRg== X-Gm-Message-State: AOAM530T2M/joOlsamK/+NHQ5pDLSdVAG+PSaxhMO2bScELnkrD/eulS yNnvWDLuzc0SVbSzQf58YZYl7UQ8EeT5MT7g X-Google-Smtp-Source: ABdhPJxmPZ5Q5jJc6Ry/3Q4A3LKB9MZwUgjNV73qNsmCkUeaK1WnrYTqmPEbT7N+rTVACgwTDKlvtg== X-Received: by 2002:a6b:7e44:: with SMTP id k4mr4570976ioq.103.1638322420361; Tue, 30 Nov 2021 17:33:40 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:b7ee:f768:f33c:c028]) by smtp.gmail.com with ESMTPSA id u24sm11856737ior.20.2021.11.30.17.33.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Nov 2021 17:33:39 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, hverkuil@xs4all.nl, tharvey@gateworks.com, nicolas@ndufresne.ca, aford@beaconembedded.com, Adam Ford , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Mauro Carvalho Chehab , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev Subject: [RFC V2 1/2] media: hantro: Add support for i.MX8M Mini Date: Tue, 30 Nov 2021 19:33:28 -0600 Message-Id: <20211201013329.15875-2-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211201013329.15875-1-aford173@gmail.com> References: <20211201013329.15875-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The i.MX8M Mini has a similar implementation of the Hantro G1 and G2 decoders, but the Mini uses the vpu-blk-ctrl for handling the VPU resets through the power domain system. As such, there are functions present in the 8MQ that are not applicable to the Mini which requires the driver to have a different compatible flags. Signed-off-by: Adam Ford diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index fb82b9297a2b..2aa1c520be50 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -592,6 +592,8 @@ static const struct of_device_id of_hantro_match[] = { { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, #endif #ifdef CONFIG_VIDEO_HANTRO_IMX8M + { .compatible = "nxp,imx8mm-vpu", .data = &imx8mm_vpu_variant, }, + { .compatible = "nxp,imx8mm-vpu-g2", .data = &imx8mm_vpu_g2_variant }, { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant }, #endif diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index 267a6d33a47b..ae7c3fff760c 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -211,6 +211,8 @@ enum hantro_enc_fmt { ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3, }; +extern const struct hantro_variant imx8mm_vpu_g2_variant; +extern const struct hantro_variant imx8mm_vpu_variant; extern const struct hantro_variant imx8mq_vpu_g2_variant; extern const struct hantro_variant imx8mq_vpu_variant; extern const struct hantro_variant px30_vpu_variant; diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c index ea919bfb9891..c68516c00c6d 100644 --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c @@ -242,6 +242,32 @@ static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = { }, }; +static const struct hantro_codec_ops imx8mm_vpu_codec_ops[] = { + [HANTRO_MODE_MPEG2_DEC] = { + .run = hantro_g1_mpeg2_dec_run, + .init = hantro_mpeg2_dec_init, + .exit = hantro_mpeg2_dec_exit, + }, + [HANTRO_MODE_VP8_DEC] = { + .run = hantro_g1_vp8_dec_run, + .init = hantro_vp8_dec_init, + .exit = hantro_vp8_dec_exit, + }, + [HANTRO_MODE_H264_DEC] = { + .run = hantro_g1_h264_dec_run, + .init = hantro_h264_dec_init, + .exit = hantro_h264_dec_exit, + }, +}; + +static const struct hantro_codec_ops imx8mm_vpu_g2_codec_ops[] = { + [HANTRO_MODE_HEVC_DEC] = { + .run = hantro_g2_hevc_dec_run, + .init = hantro_hevc_dec_init, + .exit = hantro_hevc_dec_exit, + }, +}; + /* * VPU variants. */ @@ -257,6 +283,11 @@ static const struct hantro_irq imx8mq_g2_irqs[] = { static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" }; static const char * const imx8mq_reg_names[] = { "g1", "g2", "ctrl" }; +static const char * const imx8mm_g1_clk_names[] = { "g1", "bus" }; +static const char * const imx8mm_g1_reg_names[] = { "g1" }; +static const char * const imx8mm_g2_clk_names[] = { "g2", "bus" }; +static const char * const imx8mm_g2_reg_names[] = { "g2" }; + const struct hantro_variant imx8mq_vpu_variant = { .dec_fmts = imx8m_vpu_dec_fmts, .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts), @@ -289,3 +320,29 @@ const struct hantro_variant imx8mq_vpu_g2_variant = { .clk_names = imx8mq_clk_names, .num_clocks = ARRAY_SIZE(imx8mq_clk_names), }; + +const struct hantro_variant imx8mm_vpu_variant = { + .dec_fmts = imx8m_vpu_dec_fmts, + .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts), + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | + HANTRO_H264_DECODER, + .codec_ops = imx8mm_vpu_codec_ops, + .irqs = imx8mq_irqs, + .num_irqs = ARRAY_SIZE(imx8mq_irqs), + .clk_names = imx8mm_g1_clk_names, + .num_clocks = ARRAY_SIZE(imx8mm_g1_clk_names), + .reg_names = imx8mm_g1_reg_names, + .num_regs = ARRAY_SIZE(imx8mm_g1_reg_names) +}; + +const struct hantro_variant imx8mm_vpu_g2_variant = { + .dec_offset = 0x0, + .dec_fmts = imx8m_vpu_g2_dec_fmts, + .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_g2_dec_fmts), + .codec = HANTRO_HEVC_DECODER, + .codec_ops = imx8mm_vpu_g2_codec_ops, + .irqs = imx8mq_g2_irqs, + .num_irqs = ARRAY_SIZE(imx8mq_g2_irqs), + .clk_names = imx8mm_g2_clk_names, + .num_clocks = ARRAY_SIZE(imx8mm_g2_reg_names), +}; From patchwork Wed Dec 1 01:33:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 520043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B141CC433EF for ; Wed, 1 Dec 2021 01:34:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240869AbhLABhP (ORCPT ); Tue, 30 Nov 2021 20:37:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241264AbhLABhH (ORCPT ); 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Tue, 30 Nov 2021 17:33:41 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, hverkuil@xs4all.nl, tharvey@gateworks.com, nicolas@ndufresne.ca, aford@beaconembedded.com, Adam Ford , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Mauro Carvalho Chehab , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev Subject: [RFC V2 2/2] arm64: dts: imx8mm: Enable VPU-G1 and VPU-G2 Date: Tue, 30 Nov 2021 19:33:29 -0600 Message-Id: <20211201013329.15875-3-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211201013329.15875-1-aford173@gmail.com> References: <20211201013329.15875-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Enable two hardware Hantro decoders called G1 and G2. Signed-off-by: Adam Ford diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index c2f3f118f82e..eb9dcd9d1a31 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1197,6 +1197,47 @@ gpu_2d: gpu@38008000 { power-domains = <&pgc_gpu>; }; + vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mm-vpu"; + reg = <0x38300000 0x10000>; + reg-names = "g1"; + interrupts = ; + interrupt-names = "g1"; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, + <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "g1", "bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, + <&clk IMX8MM_CLK_VPU_BUS>, + <&clk IMX8MM_VPU_PLL_BYPASS>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, + <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_VPU_PLL>; + assigned-clock-rates = <600000000>, + <800000000>, + <0>; + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>; + }; + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mm-vpu-g2"; + reg = <0x38310000 0x10000>; + interrupts = ; + interrupt-names = "g2"; + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>, + <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "g2", "bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G2>, + <&clk IMX8MM_CLK_VPU_BUS>, + <&clk IMX8MM_VPU_PLL_BYPASS>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, + <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_VPU_PLL>; + assigned-clock-rates = <600000000>, + <800000000>, + <0>; + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>; + }; + vpu_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>;