From patchwork Tue Nov 16 07:41:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 517638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 529BDC433EF for ; Tue, 16 Nov 2021 07:42:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3EE2F6323A for ; Tue, 16 Nov 2021 07:42:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231394AbhKPHpp (ORCPT ); Tue, 16 Nov 2021 02:45:45 -0500 Received: from relmlor2.renesas.com ([210.160.252.172]:3759 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231272AbhKPHpf (ORCPT ); Tue, 16 Nov 2021 02:45:35 -0500 X-IronPort-AV: E=Sophos;i="5.87,238,1631545200"; d="scan'208";a="100767130" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 16 Nov 2021 16:42:37 +0900 Received: from localhost.localdomain (unknown [10.166.14.185]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 484E04007536; Tue, 16 Nov 2021 16:42:37 +0900 (JST) From: Yoshihiro Shimoda To: geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH 01/16] dt-bindings: arm: renesas: Document R-Car S4-8 SoC DT bindings Date: Tue, 16 Nov 2021 16:41:15 +0900 Message-Id: <20211116074130.107554-2-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116074130.107554-1-yoshihiro.shimoda.uh@renesas.com> References: <20211116074130.107554-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add device tree bindings documentation for Renesas R-Car S4-8 (r8a779f0). Signed-off-by: Yoshihiro Shimoda --- Documentation/devicetree/bindings/arm/renesas.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 517206507801..36197f53b310 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -315,6 +315,10 @@ properties: - const: renesas,falcon-cpu - const: renesas,r8a779a0 + - description: R-Car S4-8 (R8A779F0) + items: + - const: renesas,r8a779f0 + - description: R-Car H3e (R8A779M0) items: - enum: From patchwork Tue Nov 16 07:41:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 517637 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E530C4167D for ; Tue, 16 Nov 2021 07:42:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 68E77615E3 for ; Tue, 16 Nov 2021 07:42:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231444AbhKPHps (ORCPT ); Tue, 16 Nov 2021 02:45:48 -0500 Received: from relmlor2.renesas.com ([210.160.252.172]:6142 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231279AbhKPHpf (ORCPT ); Tue, 16 Nov 2021 02:45:35 -0500 X-IronPort-AV: E=Sophos;i="5.87,238,1631545200"; d="scan'208";a="100767133" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 16 Nov 2021 16:42:37 +0900 Received: from localhost.localdomain (unknown [10.166.14.185]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 8518C400C4FD; Tue, 16 Nov 2021 16:42:37 +0900 (JST) From: Yoshihiro Shimoda To: geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH 03/16] dt-bindings: reset: renesas,rst: Document r8a779f0 reset module Date: Tue, 16 Nov 2021 16:41:17 +0900 Message-Id: <20211116074130.107554-4-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116074130.107554-1-yoshihiro.shimoda.uh@renesas.com> References: <20211116074130.107554-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Document bindings for the R-Car S4-8 (R8A779F0) reset module. Signed-off-by: Yoshihiro Shimoda --- Documentation/devicetree/bindings/reset/renesas,rst.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.yaml b/Documentation/devicetree/bindings/reset/renesas,rst.yaml index 620cd0538bbe..bbe313bf1796 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rst.yaml +++ b/Documentation/devicetree/bindings/reset/renesas,rst.yaml @@ -48,6 +48,7 @@ properties: - renesas,r8a77990-rst # R-Car E3 - renesas,r8a77995-rst # R-Car D3 - renesas,r8a779a0-rst # R-Car V3U + - renesas,r8a779f0-rst # R-Car S4-8 reg: maxItems: 1 From patchwork Tue Nov 16 07:41:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 517636 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1223C433EF for ; Tue, 16 Nov 2021 07:42:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CBB31619EC for ; Tue, 16 Nov 2021 07:42:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231255AbhKPHpt (ORCPT ); Tue, 16 Nov 2021 02:45:49 -0500 Received: from relmlor2.renesas.com ([210.160.252.172]:62354 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231368AbhKPHpo (ORCPT ); Tue, 16 Nov 2021 02:45:44 -0500 X-IronPort-AV: E=Sophos;i="5.87,238,1631545200"; d="scan'208";a="100767139" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 16 Nov 2021 16:42:38 +0900 Received: from localhost.localdomain (unknown [10.166.14.185]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id E1064400C4FD; Tue, 16 Nov 2021 16:42:37 +0900 (JST) From: Yoshihiro Shimoda To: geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH 06/16] dt-bindings: clock: renesas, cpg-mssr: Document r8a779f0 Date: Tue, 16 Nov 2021 16:41:20 +0900 Message-Id: <20211116074130.107554-7-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116074130.107554-1-yoshihiro.shimoda.uh@renesas.com> References: <20211116074130.107554-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add binding documentation for the R-Car S4-8 (R8A779F0) Clock Pulse Generator. Signed-off-by: Yoshihiro Shimoda --- Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml index 9b414fbde6d7..e0b86214f0f5 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml @@ -48,6 +48,7 @@ properties: - renesas,r8a77990-cpg-mssr # R-Car E3 - renesas,r8a77995-cpg-mssr # R-Car D3 - renesas,r8a779a0-cpg-mssr # R-Car V3U + - renesas,r8a779f0-cpg-mssr # R-Car S4-8 reg: maxItems: 1 From patchwork Tue Nov 16 07:41:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 517634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D2B1C43217 for ; Tue, 16 Nov 2021 07:43:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4B7DB619EC for ; Tue, 16 Nov 2021 07:43:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231504AbhKPHp7 (ORCPT ); Tue, 16 Nov 2021 02:45:59 -0500 Received: from relmlor2.renesas.com ([210.160.252.172]:6142 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231274AbhKPHpq (ORCPT ); Tue, 16 Nov 2021 02:45:46 -0500 X-IronPort-AV: E=Sophos;i="5.87,238,1631545200"; d="scan'208";a="100767142" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 16 Nov 2021 16:42:38 +0900 Received: from localhost.localdomain (unknown [10.166.14.185]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 1EB4A40083D3; Tue, 16 Nov 2021 16:42:38 +0900 (JST) From: Yoshihiro Shimoda To: geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH 08/16] dt-bindings: serial: renesas,scif: Document r8a779f0 bindings Date: Tue, 16 Nov 2021 16:41:22 +0900 Message-Id: <20211116074130.107554-9-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116074130.107554-1-yoshihiro.shimoda.uh@renesas.com> References: <20211116074130.107554-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org R-Car S4-8 (R8A779F0) SoC has the R-Car Gen4 compatible SCIF ports, so document the SoC specific bindings. Signed-off-by: Yoshihiro Shimoda --- Documentation/devicetree/bindings/serial/renesas,scif.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index 6b8731f7f2fb..14602b720cc0 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -64,6 +64,12 @@ properties: - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2 - const: renesas,scif # generic SCIF compatible UART + - items: + - enum: + - renesas,scif-r8a779f0 # R-Car S4-8 + - const: renesas,rcar-gen4-scif # R-Car Gen4 + - const: renesas,scif # generic SCIF compatible UART + - items: - enum: - renesas,scif-r9a07g044 # RZ/G2{L,LC} From patchwork Tue Nov 16 07:41:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 517635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 321F8C433EF for ; Tue, 16 Nov 2021 07:43:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1E785615E3 for ; Tue, 16 Nov 2021 07:43:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231491AbhKPHpy (ORCPT ); Tue, 16 Nov 2021 02:45:54 -0500 Received: from relmlor1.renesas.com ([210.160.252.171]:39793 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231389AbhKPHpq (ORCPT ); Tue, 16 Nov 2021 02:45:46 -0500 X-IronPort-AV: E=Sophos;i="5.87,238,1631545200"; d="scan'208";a="100433343" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 16 Nov 2021 16:42:38 +0900 Received: from localhost.localdomain (unknown [10.166.14.185]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 68EBF40083D3; Tue, 16 Nov 2021 16:42:38 +0900 (JST) From: Yoshihiro Shimoda To: geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH 11/16] soc: renesas: rcar-rst: Add support for R-Car S4-8 Date: Tue, 16 Nov 2021 16:41:25 +0900 Message-Id: <20211116074130.107554-12-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116074130.107554-1-yoshihiro.shimoda.uh@renesas.com> References: <20211116074130.107554-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add support for R-Car S4-8 (R8A779F0) to the R-Car RST driver. The register map of R-Car S4-8 is the same as R-Car V3U so that renames "V3U" and "r8a779a0" with "Gen4". Signed-off-by: Yoshihiro Shimoda --- drivers/soc/renesas/rcar-rst.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c index 24c7466de9f2..c9f2232a1b42 100644 --- a/drivers/soc/renesas/rcar-rst.c +++ b/drivers/soc/renesas/rcar-rst.c @@ -12,7 +12,7 @@ #define WDTRSTCR_RESET 0xA55A0002 #define WDTRSTCR 0x0054 -#define V3U_WDTRSTCR 0x0010 +#define GEN4_WDTRSTCR 0x0010 #define CR7BAR 0x0070 #define CR7BAREN BIT(4) @@ -28,9 +28,9 @@ static int rcar_rst_enable_wdt_reset(void __iomem *base) return 0; } -static int v3u_rst_enable_wdt_reset(void __iomem *base) +static int rcar_rst_gen4_enable_wdt_reset(void __iomem *base) { - iowrite32(WDTRSTCR_RESET, base + V3U_WDTRSTCR); + iowrite32(WDTRSTCR_RESET, base + GEN4_WDTRSTCR); return 0; } @@ -73,9 +73,9 @@ static const struct rst_config rcar_rst_gen3 __initconst = { .set_rproc_boot_addr = rcar_rst_set_gen3_rproc_boot_addr, }; -static const struct rst_config rcar_rst_r8a779a0 __initconst = { +static const struct rst_config rcar_rst_gen4 __initconst = { .modemr = 0x00, /* MODEMR0 and it has CPG related bits */ - .configure = v3u_rst_enable_wdt_reset, + .configure = rcar_rst_gen4_enable_wdt_reset, }; static const struct of_device_id rcar_rst_matches[] __initconst = { @@ -109,7 +109,9 @@ static const struct of_device_id rcar_rst_matches[] __initconst = { { .compatible = "renesas,r8a77990-rst", .data = &rcar_rst_gen3 }, { .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 }, /* R-Car V3U */ - { .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_r8a779a0 }, + { .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_gen4 }, + /* R-Car Gen4 */ + { .compatible = "renesas,r8a779f0-rst", .data = &rcar_rst_gen4 }, { /* sentinel */ } }; From patchwork Tue Nov 16 07:41:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 517631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAC0BC433F5 for ; Tue, 16 Nov 2021 07:43:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8C75D615E3 for ; Tue, 16 Nov 2021 07:43:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230429AbhKPHqa (ORCPT ); Tue, 16 Nov 2021 02:46:30 -0500 Received: from relmlor2.renesas.com ([210.160.252.172]:6142 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231426AbhKPHpt (ORCPT ); Tue, 16 Nov 2021 02:45:49 -0500 X-IronPort-AV: E=Sophos;i="5.87,238,1631545200"; d="scan'208";a="100767153" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 16 Nov 2021 16:42:38 +0900 Received: from localhost.localdomain (unknown [10.166.14.185]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 7DE9140083D3; Tue, 16 Nov 2021 16:42:38 +0900 (JST) From: Yoshihiro Shimoda To: geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH 12/16] clk: renesas: cpg-mssr: Add support for R-Car S4-8 Date: Tue, 16 Nov 2021 16:41:26 +0900 Message-Id: <20211116074130.107554-13-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116074130.107554-1-yoshihiro.shimoda.uh@renesas.com> References: <20211116074130.107554-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Initial support for R-Car S4-8 (r8a779f0), including core, module clocks, resets, and register access, because register specification differs from R-Car Gen2/3. The register layout of V3U is a similar with R-Car S4-8 so that renames CLK_REG_LAYOUT_RCAR_V3U as CLK_REG_LAYOUT_RCAR_GEN4. However, PLL names differ between V3U and S4-8. Inspired by patches in the BSP by LUU HOAI. Signed-off-by: Yoshihiro Shimoda --- drivers/clk/renesas/Kconfig | 10 ++ drivers/clk/renesas/Makefile | 2 + drivers/clk/renesas/r8a779a0-cpg-mssr.c | 2 +- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 188 ++++++++++++++++++++++++ drivers/clk/renesas/rcar-gen4-cpg.c | 141 ++++++++++++++++++ drivers/clk/renesas/rcar-gen4-cpg.h | 76 ++++++++++ drivers/clk/renesas/renesas-cpg-mssr.c | 42 ++++-- drivers/clk/renesas/renesas-cpg-mssr.h | 3 +- 8 files changed, 448 insertions(+), 16 deletions(-) create mode 100644 drivers/clk/renesas/r8a779f0-cpg-mssr.c create mode 100644 drivers/clk/renesas/rcar-gen4-cpg.c create mode 100644 drivers/clk/renesas/rcar-gen4-cpg.h diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 6d0280751bb1..0927fa963ca6 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -31,6 +31,7 @@ config CLK_RENESAS select CLK_R8A77990 if ARCH_R8A77990 select CLK_R8A77995 if ARCH_R8A77995 select CLK_R8A779A0 if ARCH_R8A779A0 + select CLK_R8A779F0 if ARCH_R8A779F0 select CLK_R9A06G032 if ARCH_R9A06G032 select CLK_R9A07G044 if ARCH_R9A07G044 select CLK_SH73A0 if ARCH_SH73A0 @@ -152,6 +153,10 @@ config CLK_R8A779A0 select CLK_RCAR_CPG_LIB select CLK_RENESAS_CPG_MSSR +config CLK_R8A779F0 + bool "R-Car S4-8 clock support" if COMPILE_TEST + select CLK_RCAR_GEN4_CPG + config CLK_R9A06G032 bool "RZ/N1D clock support" if COMPILE_TEST @@ -178,6 +183,11 @@ config CLK_RCAR_GEN3_CPG select CLK_RCAR_CPG_LIB select CLK_RENESAS_CPG_MSSR +config CLK_RCAR_GEN4_CPG + bool "R-Car Gen4 clock support" if COMPILE_TEST + select CLK_RCAR_CPG_LIB + select CLK_RENESAS_CPG_MSSR + config CLK_RCAR_USB2_CLOCK_SEL bool "Renesas R-Car USB2 clock selector support" depends on ARCH_RENESAS || COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 7d018700d08b..1cd461b8fa7b 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o +obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o @@ -36,6 +37,7 @@ obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o +obj-$(CONFIG_CLK_RCAR_GEN4_CPG) += rcar-gen4-cpg.o obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index fbd7454f2beb..8aab3957c23d 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -583,5 +583,5 @@ const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = { .init = r8a779a0_cpg_mssr_init, .cpg_clk_register = rcar_r8a779a0_cpg_clk_register, - .reg_layout = CLK_REG_LAYOUT_RCAR_V3U, + .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4, }; diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c new file mode 100644 index 000000000000..ebec32008bc6 --- /dev/null +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * r8a779f0 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2021 Renesas Electronics Corp. + * + * Based on r8a779a0-cpg-mssr.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "renesas-cpg-mssr.h" +#include "rcar-gen4-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A779F0_CLK_R, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL1, + CLK_PLL2, + CLK_PLL3, + CLK_PLL5, + CLK_PLL6, + CLK_PLL1_DIV2, + CLK_PLL2_DIV2, + CLK_PLL3_DIV2, + CLK_PLL5_DIV2, + CLK_PLL5_DIV4, + CLK_PLL6_DIV2, + CLK_S0, + CLK_SDSRC, + CLK_RPCSRC, + CLK_OCO, + + /* Module Clocks */ + MOD_CLK_BASE +}; + +static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("extalr", CLK_EXTALR), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), + DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN), + DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), + + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), + DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), + DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), + DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1), + DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV2, 2, 1), + DEF_RATE(".oco", CLK_OCO, 32768), + + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), + DEF_BASE(".rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC), + + /* Core Clock Outputs */ + DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1), + DEF_FIXED("s0d3", R8A779F0_CLK_S0D3, CLK_S0, 3, 1), + DEF_FIXED("s0d4", R8A779F0_CLK_S0D4, CLK_S0, 4, 1), + DEF_FIXED("cl16m", R8A779F0_CLK_CL16M, CLK_S0, 48, 1), + DEF_FIXED("s0d2_mm", R8A779F0_CLK_S0D2_MM, CLK_S0, 2, 1), + DEF_FIXED("s0d3_mm", R8A779F0_CLK_S0D3_MM, CLK_S0, 3, 1), + DEF_FIXED("s0d4_mm", R8A779F0_CLK_S0D4_MM, CLK_S0, 4, 1), + DEF_FIXED("cl16m_mm", R8A779F0_CLK_CL16M_MM, CLK_S0, 48, 1), + DEF_FIXED("s0d2_rt", R8A779F0_CLK_S0D2_RT, CLK_S0, 2, 1), + DEF_FIXED("s0d3_rt", R8A779F0_CLK_S0D3_RT, CLK_S0, 3, 1), + DEF_FIXED("s0d4_rt", R8A779F0_CLK_S0D4_RT, CLK_S0, 4, 1), + DEF_FIXED("s0d6_rt", R8A779F0_CLK_S0D6_RT, CLK_S0, 6, 1), + DEF_FIXED("cl16m_rt", R8A779F0_CLK_CL16M_RT, CLK_S0, 48, 1), + DEF_FIXED("s0d3_per", R8A779F0_CLK_S0D3_PER, CLK_S0, 3, 1), + DEF_FIXED("s0d6_per", R8A779F0_CLK_S0D6_PER, CLK_S0, 6, 1), + DEF_FIXED("s0d12_per", R8A779F0_CLK_S0D12_PER, CLK_S0, 12, 1), + DEF_FIXED("s0d24_per", R8A779F0_CLK_S0D24_PER, CLK_S0, 24, 1), + DEF_FIXED("cl16m_per", R8A779F0_CLK_CL16M_PER, CLK_S0, 48, 1), + DEF_FIXED("s0d2_hsc", R8A779F0_CLK_S0D2_HSC, CLK_S0, 2, 1), + DEF_FIXED("s0d3_hsc", R8A779F0_CLK_S0D3_HSC, CLK_S0, 3, 1), + DEF_FIXED("s0d4_hsc", R8A779F0_CLK_S0D4_HSC, CLK_S0, 4, 1), + DEF_FIXED("s0d6_hsc", R8A779F0_CLK_S0D6_HSC, CLK_S0, 6, 1), + DEF_FIXED("s0d12_hsc", R8A779F0_CLK_S0D12_HSC, CLK_S0, 12, 1), + DEF_FIXED("cl16m_hsc", R8A779F0_CLK_CL16M_HSC, CLK_S0, 48, 1), + DEF_FIXED("s0d2_cc", R8A779F0_CLK_S0D2_CC, CLK_S0, 2, 1), + DEF_FIXED("rsw", R8A779F0_CLK_RSW2, CLK_PLL5, 2, 1), + DEF_FIXED("cbfusa", R8A779F0_CLK_CBFUSA, CLK_EXTAL, 2, 1), + DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1), + + DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, CLK_SDSRC, 0x870), + DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x087C), + + DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8), + DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), +}; + +static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { + DEF_MOD("scif0", 702, R8A779F0_CLK_S0D12_PER), + DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER), + DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER), + DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER), +}; + +/* + * CPG Clock Data + */ +/* + * MD EXTAL PLL1 PLL2 PLL3 PLL5 PLL6 OSC + * 14 13 (MHz) + * ---------------------------------------------------------------- + * 0 0 16.66 / 1 x200 x150 x200 x200 x134 /15 + * 0 1 20 / 1 x160 x120 x160 x160 x106 /19 + * 1 0 Prohibited setting + * 1 1 40 / 2 x160 x120 x160 x160 x106 /38 + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ + (((md) & BIT(13)) >> 13)) + +static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = { + /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ + { 1, 200, 1, 150, 1, 200, 1, 200, 1, 134, 1, 16, }, + { 1, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 19, }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + { 2, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 38, }, +}; + +static int __init r8a779f0_cpg_mssr_init(struct device *dev) +{ + const struct rcar_gen4_cpg_pll_config *cpg_pll_config; + u32 cpg_mode; + int error; + + error = rcar_rst_read_mode_pins(&cpg_mode); + if (error) + return error; + + cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; + if (!cpg_pll_config->extal_div) { + dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); + return -EINVAL; + } + + return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); +} + +const struct cpg_mssr_info r8a779f0_cpg_mssr_info __initconst = { + /* Core Clocks */ + .core_clks = r8a779f0_core_clks, + .num_core_clks = ARRAY_SIZE(r8a779f0_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Module Clocks */ + .mod_clks = r8a779f0_mod_clks, + .num_mod_clks = ARRAY_SIZE(r8a779f0_mod_clks), + .num_hw_mod_clks = 28 * 32, + + /* Callbacks */ + .init = r8a779f0_cpg_mssr_init, + .cpg_clk_register = rcar_gen4_cpg_clk_register, + + .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4, +}; diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c new file mode 100644 index 000000000000..930ac767c1d5 --- /dev/null +++ b/drivers/clk/renesas/rcar-gen4-cpg.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R-Car Gen4 Clock Pulse Generator + * + * Copyright (C) 2021 Renesas Electronics Corp. + * + * Based on rcar-gen3-cpg.c + * + * Copyright (C) 2015-2018 Glider bvba + * Copyright (C) 2019 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "renesas-cpg-mssr.h" +#include "rcar-gen4-cpg.h" +#include "rcar-cpg-lib.h" + +static const struct clk_div_table cpg_rpcsrc_div_table[] = { + { 2, 5 }, { 3, 6 }, { 0, 0 }, +}; + +static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initconst; +static unsigned int cpg_clk_extalr __initdata; +static u32 cpg_mode __initdata; + +struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev, + const struct cpg_core_clk *core, const struct cpg_mssr_info *info, + struct clk **clks, void __iomem *base, + struct raw_notifier_head *notifiers) +{ + const struct clk *parent; + unsigned int mult = 1; + unsigned int div = 1; + + parent = clks[core->parent & 0xffff]; /* some types use high bits */ + if (IS_ERR(parent)) + return ERR_CAST(parent); + + switch (core->type) { + case CLK_TYPE_GEN4_MAIN: + div = cpg_pll_config->extal_div; + break; + + case CLK_TYPE_GEN4_PLL1: + mult = cpg_pll_config->pll1_mult; + div = cpg_pll_config->pll1_div; + break; + + case CLK_TYPE_GEN4_PLL2: + mult = cpg_pll_config->pll2_mult; + div = cpg_pll_config->pll2_div; + break; + + case CLK_TYPE_GEN4_PLL3: + mult = cpg_pll_config->pll3_mult; + div = cpg_pll_config->pll3_div; + break; + + case CLK_TYPE_GEN4_PLL5: + mult = cpg_pll_config->pll5_mult; + div = cpg_pll_config->pll5_div; + break; + + case CLK_TYPE_GEN4_PLL6: + mult = cpg_pll_config->pll6_mult; + div = cpg_pll_config->pll6_div; + break; + + case CLK_TYPE_GEN4_MDSEL: + /* + * Clock selectable between two parents and two fixed dividers + * using a mode pin + */ + if (cpg_mode & BIT(core->offset)) { + div = core->div & 0xffff; + } else { + parent = clks[core->parent >> 16]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + div = core->div >> 16; + } + mult = 1; + break; + + case CLK_TYPE_GEN4_OSC: + /* + * Clock combining OSC EXTAL predivider and a fixed divider + */ + div = cpg_pll_config->osc_prediv * core->div; + break; + + case CLK_TYPE_GEN4_RPCSRC: + return clk_register_divider_table(NULL, core->name, + __clk_get_name(parent), 0, + base + CPG_RPCCKCR, 3, 2, 0, + cpg_rpcsrc_div_table, + &cpg_lock); + + case CLK_TYPE_GEN4_RPC: + return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR, + __clk_get_name(parent), notifiers); + + case CLK_TYPE_GEN4_RPCD2: + return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR, + __clk_get_name(parent)); + + case CLK_TYPE_GEN4_SD: + return cpg_sd_clk_register(core->name, base, core->offset, + __clk_get_name(parent), notifiers, + 0); + + default: + return ERR_PTR(-EINVAL); + } + + return clk_register_fixed_factor(NULL, core->name, + __clk_get_name(parent), 0, mult, div); +} + +int __init rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config, + unsigned int clk_extalr, u32 mode) +{ + cpg_pll_config = config; + cpg_clk_extalr = clk_extalr; + cpg_mode = mode; + + spin_lock_init(&cpg_lock); + + return 0; +} diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h new file mode 100644 index 000000000000..d6e40b51743b --- /dev/null +++ b/drivers/clk/renesas/rcar-gen4-cpg.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * R-Car Gen4 Clock Pulse Generator + * + * Copyright (C) 2021 Renesas Electronics Corp. + * + */ + +#ifndef __CLK_RENESAS_RCAR_GEN4_CPG_H__ +#define __CLK_RENESAS_RCAR_GEN4_CPG_H__ + +enum rcar_gen4_clk_types { + CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM, + CLK_TYPE_GEN4_PLL1, + CLK_TYPE_GEN4_PLL2, + CLK_TYPE_GEN4_PLL3, + CLK_TYPE_GEN4_PLL5, + CLK_TYPE_GEN4_PLL6, + CLK_TYPE_GEN4_SD, + CLK_TYPE_GEN4_R, + CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */ + CLK_TYPE_GEN4_Z, + CLK_TYPE_GEN4_ZG, + CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */ + CLK_TYPE_GEN4_RPCSRC, + CLK_TYPE_GEN4_RPC, + CLK_TYPE_GEN4_RPCD2, + + /* SoC specific definitions start here */ + CLK_TYPE_GEN4_SOC_BASE, +}; + +#define DEF_GEN4_SD(_name, _id, _parent, _offset) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset) + +#define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \ + (_parent0) << 16 | (_parent1), \ + .div = (_div0) << 16 | (_div1), .offset = _md) + +#define DEF_GEN4_PE(_name, _id, _parent_clean, _div_clean, _parent_sscg, \ + _div_sscg) \ + DEF_GEN4_MDSEL(_name, _id, 12, _parent_clean, _div_clean, \ + _parent_sscg, _div_sscg) + +#define DEF_GEN4_OSC(_name, _id, _parent, _div) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div) + +#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \ + DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) + +struct rcar_gen4_cpg_pll_config { + u8 extal_div; + u8 pll1_mult; + u8 pll1_div; + u8 pll2_mult; + u8 pll2_div; + u8 pll3_mult; + u8 pll3_div; + u8 pll5_mult; + u8 pll5_div; + u8 pll6_mult; + u8 pll6_div; + u8 osc_prediv; +}; + +#define CPG_RPCCKCR 0x874 + +struct clk *rcar_gen4_cpg_clk_register(struct device *dev, + const struct cpg_core_clk *core, const struct cpg_mssr_info *info, + struct clk **clks, void __iomem *base, + struct raw_notifier_head *notifiers); +int rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config, + unsigned int clk_extalr, u32 mode); + +#endif diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 21f762aa2131..ccde338b9fed 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -57,9 +57,11 @@ static const u16 mstpsr[] = { 0x9A0, 0x9A4, 0x9A8, 0x9AC, }; -static const u16 mstpsr_for_v3u[] = { +static const u16 mstpsr_for_gen4[] = { 0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C, - 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, + 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C, + 0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C, + 0x2E60, 0x2E64, 0x2E68, 0x2E6C, }; /* @@ -71,9 +73,11 @@ static const u16 smstpcr[] = { 0x990, 0x994, 0x998, 0x99C, }; -static const u16 mstpcr_for_v3u[] = { +static const u16 mstpcr_for_gen4[] = { 0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C, - 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, + 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C, + 0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C, + 0x2D60, 0x2D64, 0x2D68, 0x2D6C, }; /* @@ -95,9 +99,11 @@ static const u16 srcr[] = { 0x920, 0x924, 0x928, 0x92C, }; -static const u16 srcr_for_v3u[] = { +static const u16 srcr_for_gen4[] = { 0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C, - 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, + 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C, + 0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C, + 0x2C60, 0x2C64, 0x2C68, 0x2C6C, }; /* @@ -109,9 +115,11 @@ static const u16 srstclr[] = { 0x960, 0x964, 0x968, 0x96C, }; -static const u16 srstclr_for_v3u[] = { +static const u16 srstclr_for_gen4[] = { 0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C, - 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, + 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC, + 0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC, + 0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC, }; /** @@ -158,7 +166,7 @@ struct cpg_mssr_priv { struct { u32 mask; u32 val; - } smstpcr_saved[ARRAY_SIZE(mstpsr_for_v3u)]; + } smstpcr_saved[ARRAY_SIZE(mstpsr_for_gen4)]; struct clk *clks[]; }; @@ -827,6 +835,12 @@ static const struct of_device_id cpg_mssr_match[] = { .compatible = "renesas,r8a779a0-cpg-mssr", .data = &r8a779a0_cpg_mssr_info, }, +#endif +#ifdef CONFIG_CLK_R8A779F0 + { + .compatible = "renesas,r8a779f0-cpg-mssr", + .data = &r8a779f0_cpg_mssr_info, + }, #endif { /* sentinel */ } }; @@ -970,11 +984,11 @@ static int __init cpg_mssr_common_init(struct device *dev, priv->reset_clear_regs = srstclr; } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { priv->control_regs = stbcr; - } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) { - priv->status_regs = mstpsr_for_v3u; - priv->control_regs = mstpcr_for_v3u; - priv->reset_regs = srcr_for_v3u; - priv->reset_clear_regs = srstclr_for_v3u; + } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) { + priv->status_regs = mstpsr_for_gen4; + priv->control_regs = mstpcr_for_gen4; + priv->reset_regs = srcr_for_gen4; + priv->reset_clear_regs = srstclr_for_gen4; } else { error = -EINVAL; goto out_err; diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 6b2a0ade482e..16810dd4e6ac 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -88,7 +88,7 @@ struct device_node; enum clk_reg_layout { CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0, CLK_REG_LAYOUT_RZ_A, - CLK_REG_LAYOUT_RCAR_V3U, + CLK_REG_LAYOUT_RCAR_GEN4, }; /** @@ -178,6 +178,7 @@ extern const struct cpg_mssr_info r8a77980_cpg_mssr_info; extern const struct cpg_mssr_info r8a77990_cpg_mssr_info; extern const struct cpg_mssr_info r8a77995_cpg_mssr_info; extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info; +extern const struct cpg_mssr_info r8a779f0_cpg_mssr_info; void __init cpg_mssr_early_init(struct device_node *np, const struct cpg_mssr_info *info); From patchwork Tue Nov 16 07:41:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 517633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23482C433FE for ; Tue, 16 Nov 2021 07:43:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 110336322C for ; Tue, 16 Nov 2021 07:43:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231303AbhKPHqC (ORCPT ); Tue, 16 Nov 2021 02:46:02 -0500 Received: from relmlor1.renesas.com ([210.160.252.171]:48885 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231270AbhKPHpr (ORCPT ); Tue, 16 Nov 2021 02:45:47 -0500 X-IronPort-AV: E=Sophos;i="5.87,238,1631545200"; d="scan'208";a="100433346" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 16 Nov 2021 16:42:38 +0900 Received: from localhost.localdomain (unknown [10.166.14.185]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 944F34007536; Tue, 16 Nov 2021 16:42:38 +0900 (JST) From: Yoshihiro Shimoda To: geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH 13/16] tty: serial: sh-sci: Add support for R-Car Gen4 Date: Tue, 16 Nov 2021 16:41:27 +0900 Message-Id: <20211116074130.107554-14-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116074130.107554-1-yoshihiro.shimoda.uh@renesas.com> References: <20211116074130.107554-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add serial support for R-Car Gen4 SoC. Signed-off-by: Yoshihiro Shimoda --- drivers/tty/serial/sh-sci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 89ee43061d3a..55f5b96663b9 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3180,6 +3180,9 @@ static const struct of_device_id of_sci_match[] = { }, { .compatible = "renesas,rcar-gen3-scif", .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), + }, { + .compatible = "renesas,rcar-gen4-scif", + .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), }, /* Generic types */ { From patchwork Tue Nov 16 07:41:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 517632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EFB5C433F5 for ; Tue, 16 Nov 2021 07:43:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 28B6D6323D for ; Tue, 16 Nov 2021 07:43:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231516AbhKPHqM (ORCPT ); Tue, 16 Nov 2021 02:46:12 -0500 Received: from relmlor1.renesas.com ([210.160.252.171]:39793 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231245AbhKPHps (ORCPT ); Tue, 16 Nov 2021 02:45:48 -0500 X-IronPort-AV: E=Sophos;i="5.87,238,1631545200"; d="scan'208";a="100433352" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 16 Nov 2021 16:42:39 +0900 Received: from localhost.localdomain (unknown [10.166.14.185]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id DC36F40083D3; Tue, 16 Nov 2021 16:42:38 +0900 (JST) From: Yoshihiro Shimoda To: geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH 16/16] arm64: defconfig: Enable R-Car S4-8 Date: Tue, 16 Nov 2021 16:41:30 +0900 Message-Id: <20211116074130.107554-17-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116074130.107554-1-yoshihiro.shimoda.uh@renesas.com> References: <20211116074130.107554-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Enable the Renesas R-Car S4-8 (R8A779F0) SoC in the ARM64 defconfig. Signed-off-by: Yoshihiro Shimoda --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index f2e2b9bdd702..04db99bfbf9d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1069,6 +1069,7 @@ CONFIG_ARCH_R8A77980=y CONFIG_ARCH_R8A77990=y CONFIG_ARCH_R8A77995=y CONFIG_ARCH_R8A779A0=y +CONFIG_ARCH_R8A779F0=y CONFIG_ARCH_R9A07G044=y CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ARCH_TEGRA_132_SOC=y