From patchwork Sat Nov 27 22:32:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 517536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98E59C4332F for ; Sat, 27 Nov 2021 22:38:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356446AbhK0Wla (ORCPT ); Sat, 27 Nov 2021 17:41:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356380AbhK0Wja (ORCPT ); Sat, 27 Nov 2021 17:39:30 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC8D2C0613E0 for ; Sat, 27 Nov 2021 14:32:59 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id l16so27257519wrp.11 for ; Sat, 27 Nov 2021 14:32:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6M4A/tb5uMp/41DxndVqEzSE2hGblNz4wYiEfFPyfnc=; b=hwCAOxXXwF6ism7IqxUqUx5YEWM699I2gzxWPjLbsuhqAxeANw0tyg2ZkoEsmxQhBM 0b9iSdg7x66rGyWrLH6auVrWWQH3b6wJHVYutnVJGMcpWtEWhVcKQ1KljEf74zibFqOA puBg08DDqOC3z87KQ50CkrfgL9gPq+6CAqIoKygr48PdbKBFJNjqnbNo9WATYhpe3bE6 lrMKH8RO+IdMTR+m3qWxiP/CFKtgNSdTXcw64hF/0TC4NwQcnOBcaPDVhH5ypKx//uqa PgaLKZK70je7WrCZ+0G55F2vKk1OFzLy2L7p1Vxi9s3gVQz9W14deADmTszNCUGxKFMJ Viow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6M4A/tb5uMp/41DxndVqEzSE2hGblNz4wYiEfFPyfnc=; b=VMr7VinB0eSX+j79ER9wp6bF7s2925XbUDsOCy2F2mpP7CwwuvPg9+D8fZb8jFqzyG 7YkD1yukF5AL41tq022AOGlztceX/qFewd6fCgu/v6Wy1FpruQTMHGyQxZg4ZS5DZCge NQ0+CHr3QPOPV6/xsVhZegl3Zxva5+RLYZy8dDtApElWiNis4+9NXc7GHFfIdey/Z12E Tr/fGgu/8M9CdFDII67dkSuXWAlR85oy/zywfvudJYhWrZ23Xke6VbKPlsR4bUmsQT57 yzhRtFJXpRoD73LHM2wtaffsiqUFSX+GAUHLNEGteEpYeJl+inx6Q1Szc1PpjtgiCz9X M6yw== X-Gm-Message-State: AOAM531rUgs4N0K5/rGX+cILobbbcMoXXJZdA6DAjKf0Yz1XLIX7hV6f sr6qPo06jdVwhZF67gaKBnLx6g== X-Google-Smtp-Source: ABdhPJwdbLpH8JwPS05Q7nu7RvXbREcA2Cct0x3S38Z74xtvi6I8L2Y3D4yJGspddD2iZgy5JeAMBw== X-Received: by 2002:a5d:6091:: with SMTP id w17mr23285781wrt.65.1638052378118; Sat, 27 Nov 2021 14:32:58 -0800 (PST) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id v6sm14801124wmh.8.2021.11.27.14.32.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Nov 2021 14:32:57 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Mark Brown , Greg Kroah-Hartman Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-i2c@vger.kernel.org Subject: [PATCH 2/8] dt-bindings: soc: samsung: Add Exynos USIv2 bindings doc Date: Sun, 28 Nov 2021 00:32:47 +0200 Message-Id: <20211127223253.19098-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211127223253.19098-1-semen.protsenko@linaro.org> References: <20211127223253.19098-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Document USIv2 IP-core bindings. Signed-off-by: Sam Protsenko --- .../bindings/soc/samsung/exynos-usi-v2.yaml | 124 ++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/samsung/exynos-usi-v2.yaml diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi-v2.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi-v2.yaml new file mode 100644 index 000000000000..d7466aa463dc --- /dev/null +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi-v2.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/samsung/exynos-usi-v2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung's Exynos USIv2 (Universal Serial Interface) binding + +maintainers: + - Sam Protsenko + - Krzysztof Kozlowski + +description: | + USIv2 IP-core provides selectable serial protocol (UART, SPI or High-Speed + I2C); only one can be chosen at a time. It is modeled as a node with zero or + more child nodes, each representing a serial sub-node device. The mode setting + selects which particular function will be used. + + Refer to next bindings documentation for information on protocol subnodes that + can exist under USI node: + + [1] Documentation/devicetree/bindings/serial/samsung_uart.yaml + [2] Documentation/devicetree/bindings/i2c/i2c-exynos5.txt + [3] Documentation/devicetree/bindings/spi/spi-samsung.txt + +properties: + $nodename: + pattern: "^usi@[0-9a-f]+$" + + compatible: + const: samsung,exynos-usi-v2 + + reg: + maxItems: 1 + + clocks: + items: + - description: Bus (APB) clock + - description: Operating clock for UART/SPI/I2C protocol + + clock-names: + items: + - const: pclk + - const: ipclk + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + samsung,sysreg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should be phandle/offset pair. The phandle to System Register syscon node + (for the same domain where this USIv2 controller resides) and the offset + of SW_CONF register for this USIv2 controller. + + samsung,mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects USIv2 function (which serial protocol to use). Refer to + for valid USI mode + values. + + samsung,clkreq-on: + type: boolean + description: + Enable this property if underlying protocol requires the clock to be + continuously provided without automatic gating. As suggested by SoC + manual, it should be set in case of SPI/I2C slave, UART Rx and I2C + multi-master mode. Usually this property is needed if USI mode is set + to "UART". + + This property is optional. + +patternProperties: + # All other properties should be child nodes + "^.*@[0-9a-f]+$": + type: object + description: Child node describing underlying USIv2 serial protocol + +required: + - compatible + - reg + - clocks + - clock-names + - ranges + - "#address-cells" + - "#size-cells" + - samsung,sysreg + - samsung,mode + +additionalProperties: false + +examples: + - | + #include + #include + + usi_uart: usi@138200c0 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x138200c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1010>; + samsung,mode = ; + samsung,clkreq-on; /* needed for UART mode */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri 32>, <&cmu_peri 31>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_0: serial@13820000 { + compatible = "samsung,exynos850-uart"; + reg = <0x13820000 0xc0>; + interrupts = ; + clocks = <&cmu_peri 32>, <&cmu_peri 31>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + }; From patchwork Sat Nov 27 22:32:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 517535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F643C4321E for ; Sat, 27 Nov 2021 22:38:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356498AbhK0WmM (ORCPT ); Sat, 27 Nov 2021 17:42:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241192AbhK0WkL (ORCPT ); Sat, 27 Nov 2021 17:40:11 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44ED0C0613F3 for ; Sat, 27 Nov 2021 14:33:01 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id d9so6386352wrw.4 for ; Sat, 27 Nov 2021 14:33:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=C2fYlu8o+hwcxca3MmfB8F34BJEFc2MVtDi8Tro0yVw=; b=g/kFSwDIdL1FGgt1BJxzECWQhS0/gPGYvTY6e8feqhelTX/YQoFIHwFaYiLU0UVNQN ZjPNdIpjKptq9BX3NIrhh+GggTZujZOcfu6xOveqin1mzGw4+fOUuVtwBsd/pnMSMXp8 k9avuikBejMseB+a8Wx1CUuxq5FGgvLH0OcZZUJPYSKgY7Ko8WeMxbP0/qUi09tN12NS NH01kdZBq48WRdQXd/GLIaKeMfa3UBCz193RF1u0jgCgtLBqAO+YMNIB5wY/wayMfTM1 vn+MdY+dJlZO9INbS48E1bhSz7y1AVYDlAPObUcrFZig1nKsRc2NWA2CQjyBLLnsOKgf feFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=C2fYlu8o+hwcxca3MmfB8F34BJEFc2MVtDi8Tro0yVw=; b=QEsPiHHY4kkSYLlGLDSdlVH7HkoVTYFN2DBhGLed+xStOTBtdFrZT25AnPNNGaxtrh CQ/MDH+xKPZd27W/FN76hYYgL0eiwgJ3GGZAw916H6Xgf4dmLgLaLZ8HfELZTwggEIbT cCbfJ8ag2HB93KT338aspV5o0U3ECmPwJrJ+xEmTKWES45CP+wHQ3nn1lEJN6+RsvYh0 /zk7Im/ZojxOQHFx/JMhFRZtIFd6MMBp3dogCUAtDcPmnuIb5U4AfF0RJ8MctMur06Jb 23rqpk2/wWWxmz57BptXuRByJsG+PZVSMme7rBkPzqUKrgKCIWvkQAgj9+7Q/AVVttG0 Tx6w== X-Gm-Message-State: AOAM530oTLeFM4eygDdpLRvuyBXe51cwCAAtMqPKpbdRQqJ4mNFXVTta sfHQBe3G4z/MgtkWGjKyoWPl+Q== X-Google-Smtp-Source: ABdhPJx7eV8hM34GzyVKeh1ASY8Ddgr8Crg8v9waCtcv3gEYGBOYuXiNVN1OMn2OWc/XXLNQSJc8Jg== X-Received: by 2002:adf:f907:: with SMTP id b7mr23385258wrr.5.1638052379807; Sat, 27 Nov 2021 14:32:59 -0800 (PST) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id h2sm9169578wrz.23.2021.11.27.14.32.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Nov 2021 14:32:59 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Mark Brown , Greg Kroah-Hartman Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-i2c@vger.kernel.org Subject: [PATCH 3/8] soc: samsung: Add USIv2 driver Date: Sun, 28 Nov 2021 00:32:48 +0200 Message-Id: <20211127223253.19098-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211127223253.19098-1-semen.protsenko@linaro.org> References: <20211127223253.19098-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and provides selectable serial protocol (one of: UART, SPI, I2C). USIv2 registers usually reside in the same register map as a particular underlying protocol it implements, but have some particular offset. E.g. on Exynos850 the USI_UART has 0x13820000 base address, where UART registers have 0x00..0x40 offsets, and USI registers have 0xc0..0xdc offsets. Desired protocol can be chosen via SW_CONF register from System Register block of the same domain as USI. Before starting to use a particular protocol, USIv2 must be configured properly: 1. Select protocol to be used via System Register 2. Clear "reset" flag in USI_CON 3. Configure HWACG behavior (e.g. for UART Rx the HWACG must be disabled, so that the IP clock is not gated automatically); this is done using USI_OPTION register 4. Keep both USI clocks (PCLK and IPCLK) running during USI registers modification This driver implements above behavior. Of course, USIv2 driver should be probed before UART/I2C/SPI drivers. It can be achived by embedding UART/I2C/SPI nodes inside of USI node (in Device Tree); driver then walks underlying nodes and instantiates those. Driver also handles USI configuration on PM resume, as register contents can be lost during CPU suspend. Signed-off-by: Sam Protsenko --- drivers/soc/samsung/Kconfig | 14 ++ drivers/soc/samsung/Makefile | 2 + drivers/soc/samsung/exynos-usi-v2.c | 242 ++++++++++++++++++++++++++++ 3 files changed, 258 insertions(+) create mode 100644 drivers/soc/samsung/exynos-usi-v2.c diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig index e2cedef1e8d1..b168973c887f 100644 --- a/drivers/soc/samsung/Kconfig +++ b/drivers/soc/samsung/Kconfig @@ -23,6 +23,20 @@ config EXYNOS_CHIPID Support for Samsung Exynos SoC ChipID and Adaptive Supply Voltage. This driver can also be built as module (exynos_chipid). +config EXYNOS_USI_V2 + tristate "Exynos USIv2 (Universal Serial Interface) driver" + default ARCH_EXYNOS && ARM64 + depends on ARCH_EXYNOS || COMPILE_TEST + select MFD_SYSCON + help + Enable support for USIv2 block. USI (Universal Serial Interface) is an + IP-core found in modern Samsung Exynos SoCs, like Exynos850 and + ExynosAutoV0. USI block can be configured to provide one of the + following serial protocols: UART, SPI or High Speed I2C. + + This driver allows one to configure USI for desired protocol, which + is usually done in USI node in Device Tree. + config EXYNOS_PMU bool "Exynos PMU controller driver" if COMPILE_TEST depends on ARCH_EXYNOS || ((ARM || ARM64) && COMPILE_TEST) diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile index 2ae4bea804cf..0b746b2fd78f 100644 --- a/drivers/soc/samsung/Makefile +++ b/drivers/soc/samsung/Makefile @@ -4,6 +4,8 @@ obj-$(CONFIG_EXYNOS_ASV_ARM) += exynos5422-asv.o obj-$(CONFIG_EXYNOS_CHIPID) += exynos_chipid.o exynos_chipid-y += exynos-chipid.o exynos-asv.o +obj-$(CONFIG_EXYNOS_USI_V2) += exynos-usi-v2.o + obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS) += exynos3250-pmu.o exynos4-pmu.o \ diff --git a/drivers/soc/samsung/exynos-usi-v2.c b/drivers/soc/samsung/exynos-usi-v2.c new file mode 100644 index 000000000000..5a315890e4ec --- /dev/null +++ b/drivers/soc/samsung/exynos-usi-v2.c @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Linaro Ltd. + * Author: Sam Protsenko + * + * Samsung Exynos USI v2 driver (Universal Serial Interface). + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +/* System Register: SW_CONF register bits */ +#define SW_CONF_UART BIT(0) +#define SW_CONF_SPI BIT(1) +#define SW_CONF_I2C BIT(2) +#define SW_CONF_MASK (SW_CONF_UART | SW_CONF_SPI | SW_CONF_I2C) + +/* USI register offsets */ +#define USI_CON 0x04 +#define USI_OPTION 0x08 + +/* USI register bits */ +#define USI_CON_RESET BIT(0) +#define USI_OPTION_CLKREQ_ON BIT(1) +#define USI_OPTION_CLKSTOP_ON BIT(2) + +struct usi_v2_mode { + const char *name; /* mode name */ + unsigned int val; /* mode register value */ +}; + +struct usi_v2 { + struct device *dev; + void __iomem *regs; /* USI register map */ + struct clk *pclk; /* USI bus clock */ + struct clk *ipclk; /* USI operating clock */ + + size_t mode; /* current USI SW_CONF mode index */ + bool clkreq_on; /* always provide clock to IP */ + + /* System Register */ + struct regmap *sysreg; /* System Register map */ + unsigned int sw_conf; /* SW_CONF register offset in sysreg */ +}; + +static const struct usi_v2_mode usi_v2_modes[] = { + [USI_V2_UART] = { .name = "uart", .val = SW_CONF_UART }, + [USI_V2_SPI] = { .name = "spi", .val = SW_CONF_SPI }, + [USI_V2_I2C] = { .name = "i2c", .val = SW_CONF_I2C }, +}; + +/** + * usi_v2_set_sw_conf - Set USI block configuration mode + * @usi: USI driver object + * @mode: Mode index + * + * Select underlying serial protocol (UART/SPI/I2C) in USI IP-core. + * + * Return: 0 on success, or negative error code on failure. + */ +static int usi_v2_set_sw_conf(struct usi_v2 *usi, size_t mode) +{ + unsigned int val; + int ret; + + if (mode >= ARRAY_SIZE(usi_v2_modes)) + return -EINVAL; + + val = usi_v2_modes[mode].val; + ret = regmap_update_bits(usi->sysreg, usi->sw_conf, SW_CONF_MASK, val); + if (ret) + return ret; + + usi->mode = mode; + dev_dbg(usi->dev, "USIv2 protocol: %s\n", usi_v2_modes[usi->mode].name); + + return 0; +} + +/** + * usi_v2_enable - Initialize USI block + * @usi: USI driver object + * + * USI IP-core start state is "reset" (on startup and after CPU resume). This + * routine enables USI block by clearing the reset flag. It also configures + * HWACG behavior (needed e.g. for UART Rx). It should be performed before + * underlying protocol becomes functional. + * + * Both 'pclk' and 'ipclk' clocks should be enabled when running this function. + */ +static void usi_v2_enable(const struct usi_v2 *usi) +{ + u32 val; + + /* Enable USI block */ + val = readl(usi->regs + USI_CON); + val &= ~USI_CON_RESET; + writel(val, usi->regs + USI_CON); + udelay(1); + + /* Continuously provide the clock to USI IP w/o gating */ + if (usi->clkreq_on) { + val = readl(usi->regs + USI_OPTION); + val &= ~USI_OPTION_CLKSTOP_ON; + val |= USI_OPTION_CLKREQ_ON; + writel(val, usi->regs + USI_OPTION); + } +} + +static int usi_v2_configure(struct usi_v2 *usi) +{ + int ret; + + ret = clk_prepare_enable(usi->pclk); + if (ret) + return ret; + + ret = clk_prepare_enable(usi->ipclk); + if (ret) + goto err_pclk; + + ret = usi_v2_set_sw_conf(usi, usi->mode); + if (ret) + goto err_ipclk; + + usi_v2_enable(usi); + +err_ipclk: + clk_disable_unprepare(usi->ipclk); +err_pclk: + clk_disable_unprepare(usi->pclk); + return ret; +} + +static int usi_v2_parse_dt(struct device_node *np, struct usi_v2 *usi) +{ + int ret; + u32 mode; + + ret = of_property_read_u32(np, "samsung,mode", &mode); + if (ret) + return ret; + usi->mode = mode; + + usi->clkreq_on = of_property_read_bool(np, "samsung,clkreq-on"); + + usi->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg"); + if (IS_ERR(usi->sysreg)) + return PTR_ERR(usi->sysreg); + + return of_property_read_u32_index(np, "samsung,sysreg", 1, + &usi->sw_conf); +} + +static int usi_v2_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct usi_v2 *usi; + int ret; + + usi = devm_kzalloc(dev, sizeof(*usi), GFP_KERNEL); + if (!usi) + return -ENOMEM; + + usi->dev = dev; + platform_set_drvdata(pdev, usi); + + usi->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(usi->regs)) + return PTR_ERR(usi->regs); + + ret = usi_v2_parse_dt(np, usi); + if (ret) + return ret; + + usi->pclk = devm_clk_get(dev, "pclk"); + if (IS_ERR(usi->pclk)) + return PTR_ERR(usi->pclk); + + usi->ipclk = devm_clk_get(dev, "ipclk"); + if (IS_ERR(usi->ipclk)) + return PTR_ERR(usi->ipclk); + + ret = usi_v2_configure(usi); + if (ret) + return ret; + + /* Make it possible to embed protocol nodes into USI np */ + return of_platform_populate(np, NULL, NULL, dev); +} + +#ifdef CONFIG_PM_SLEEP +static int usi_v2_resume_noirq(struct device *dev) +{ + struct usi_v2 *usi = dev_get_drvdata(dev); + + return usi_v2_configure(usi); +} +#endif + +static const struct dev_pm_ops usi_v2_pm = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, usi_v2_resume_noirq) +}; + +static const struct of_device_id usi_v2_dt_match[] = { + { .compatible = "samsung,exynos-usi-v2", }, + { }, +}; +MODULE_DEVICE_TABLE(of, usi_v2_dt_match); + +static struct platform_driver usi_v2_driver = { + .driver = { + .name = "exynos-usi-v2", + .pm = &usi_v2_pm, + .of_match_table = usi_v2_dt_match, + }, + .probe = usi_v2_probe, +}; + +static int __init usi_v2_init(void) +{ + return platform_driver_register(&usi_v2_driver); +} +arch_initcall(usi_v2_init); + +static void __exit usi_v2_exit(void) +{ + platform_driver_unregister(&usi_v2_driver); +} +module_exit(usi_v2_exit); + +MODULE_DESCRIPTION("Samsung USI v2 driver"); +MODULE_AUTHOR("Sam Protsenko "); +MODULE_LICENSE("GPL"); From patchwork Sat Nov 27 22:32:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 517534 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D334C43219 for ; Sat, 27 Nov 2021 22:40:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356636AbhK0Wnb (ORCPT ); Sat, 27 Nov 2021 17:43:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356444AbhK0Wla (ORCPT ); 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Sat, 27 Nov 2021 14:33:04 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Mark Brown , Greg Kroah-Hartman Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-i2c@vger.kernel.org Subject: [PATCH 6/8] tty: serial: Make SERIAL_SAMSUNG=y impossible when EXYNOS_USI_V2=m Date: Sun, 28 Nov 2021 00:32:51 +0200 Message-Id: <20211127223253.19098-7-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211127223253.19098-1-semen.protsenko@linaro.org> References: <20211127223253.19098-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org When UART is encapsulated in USIv2 block (e.g. in Exynos850), USIv2 driver must be loaded first, as it's preparing USI hardware for particular protocol use. Make it impossible for Samsung serial driver to be built-in when USIv2 driver is built as a module, to prevent incorrect booting order for those drivers. Signed-off-by: Sam Protsenko --- drivers/tty/serial/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 0e5ccb25bdb1..47bc24e74041 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -237,6 +237,7 @@ config SERIAL_CLPS711X_CONSOLE config SERIAL_SAMSUNG tristate "Samsung SoC serial support" depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || ARCH_APPLE || COMPILE_TEST + depends on EXYNOS_USI_V2 || !EXYNOS_USI_V2 select SERIAL_CORE help Support for the on-chip UARTs on the Samsung From patchwork Sat Nov 27 22:32:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 517533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95EBAC4167E for ; Sat, 27 Nov 2021 22:41:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356666AbhK0WoM (ORCPT ); Sat, 27 Nov 2021 17:44:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356572AbhK0WmM (ORCPT ); Sat, 27 Nov 2021 17:42:12 -0500 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DDF1C061397 for ; Sat, 27 Nov 2021 14:33:09 -0800 (PST) Received: by mail-wm1-x331.google.com with SMTP id o19-20020a1c7513000000b0033a93202467so9400681wmc.2 for ; Sat, 27 Nov 2021 14:33:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LJ8LcarI7xqEtvO5iVdRS56QktsqqAOlLhc5CcWcfZQ=; b=r/qaO9nQajEHTbRAiXJq5PBzELxh5SYcoGDHjkN5FwgvsS/VnF/bAOJx+7tp53JVEF i/t/XIzQCEyV+pEoUklfZrciszvg94BS/pQNz2A3MeVo01sPBNRVRbaCye70p75cV+t9 2oGmdCE46DQUSKfznDj4vh4OXQcT07HJryqQcYO4iYmdkQ/1tVg3+0Bz7ZKCVenrVQZg vIfZzm/thV8mBebncIzTNzu9qDfvmdD2lo9EjUEneA0fuKw8zj2ExbnSqJ6jRQaStZoS yKcNUcq0cYJ4y0FKW61tt2FFcZ/imS6ZDC8X4XwoOYa1SAb+cLLcZsFVTzXL0GcdSW3g Y7JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LJ8LcarI7xqEtvO5iVdRS56QktsqqAOlLhc5CcWcfZQ=; b=t/q4ga7LxkwXJnmJDxDrxtpcbhl+2da51CQDyDEdylz+LeQqGCaporajwSqbw0kXlu pLyRz5wQROfGceUZJuC14batMHYWVjKrnnq7lUk/W1SUbCgu8YpGKv8udd5jl2eMj5bg Py3jn0nHqw4reOvhgCWpasKUDk1uMAf8YYU9nkderOu4OekJ+m0L02nLgPgtHbheQbQ8 +C5OeulCGqEBXeYLPFMaZ4MsvR/U4vUJm3IB8jthNOP7tO47oFZ5B+x0Hmla2lGh8k7e ekJqvy+vytnIdv2786QFsj+m2MzEtNpHy3QGKXGGc86J5FJPsutz0DEOVhqgd7jvKOgQ 8+Wg== X-Gm-Message-State: AOAM533e/PcPgnKqCe7Cap2C65iLCVqOaQ7Eg0Rr/9aiqiKeTsFiY0BR 4It2sfMJCfI8Vsr5x48BB2W4ng== X-Google-Smtp-Source: ABdhPJybLPuiYuY26o40e1ovZYC7Flhu8vSAfHRGwdZ9hn+tl2NYlm7OSVmgTPh6Mb5T6RqHSb/bIA== X-Received: by 2002:a1c:770e:: with SMTP id t14mr24560888wmi.173.1638052388201; Sat, 27 Nov 2021 14:33:08 -0800 (PST) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id g13sm13152129wrd.57.2021.11.27.14.33.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Nov 2021 14:33:07 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Mark Brown , Greg Kroah-Hartman Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-i2c@vger.kernel.org Subject: [PATCH 8/8] spi: Make SPI_S3C64XX=y impossible when EXYNOS_USI_V2=m Date: Sun, 28 Nov 2021 00:32:53 +0200 Message-Id: <20211127223253.19098-9-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211127223253.19098-1-semen.protsenko@linaro.org> References: <20211127223253.19098-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org When S3C64XX SPI is encapsulated in USIv2 block (e.g. in Exynos850), USIv2 driver must be loaded first, as it's preparing USI hardware for particular protocol use. Make it impossible for spi-s3c64xx driver to be built-in when USIv2 driver is built as a module, to prevent incorrect booting order for those drivers. Signed-off-by: Sam Protsenko --- drivers/spi/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index b2a8821971e1..fbdf901248be 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -761,6 +761,7 @@ config SPI_S3C24XX_FIQ config SPI_S3C64XX tristate "Samsung S3C64XX/Exynos SoC series type SPI" depends on (PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST) + depends on EXYNOS_USI_V2 || !EXYNOS_USI_V2 help SPI driver for Samsung S3C64XX, S5Pv210 and Exynos SoCs. Choose Y/M here only if you build for such Samsung SoC.