From patchwork Thu Nov 11 08:43:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaewon Kim X-Patchwork-Id: 518615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DD11C433EF for ; Thu, 11 Nov 2021 08:48:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6394E61260 for ; Thu, 11 Nov 2021 08:48:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230300AbhKKIu5 (ORCPT ); Thu, 11 Nov 2021 03:50:57 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:25078 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231951AbhKKIuw (ORCPT ); Thu, 11 Nov 2021 03:50:52 -0500 Received: from epcas2p4.samsung.com (unknown [182.195.41.56]) by mailout3.samsung.com (KnoxPortal) with ESMTP id 20211111084802epoutp03e783c0bd72e9003bba6dc490b4a33ac0~2cah0jb180336403364epoutp03r for ; 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Thu, 11 Nov 2021 17:47:49 +0900 (KST) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas2p2.samsung.com (KnoxPortal) with ESMTPA id 20211111084749epcas2p291a982cce677c58febcf00d5d900c4a5~2caVKASJe1278512785epcas2p2S; Thu, 11 Nov 2021 08:47:49 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20211111084749epsmtrp23311afb969b2f8b21ec38324aa69b979~2caVJT4u72737827378epsmtrp2u; Thu, 11 Nov 2021 08:47:49 +0000 (GMT) X-AuditID: b6c32a45-447ff7000000ca37-06-618cd8b5b203 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 52.E0.29871.5B8DC816; Thu, 11 Nov 2021 17:47:49 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20211111084749epsmtip2bd31a5f334f8492140a5a3d8280a8baa~2caU-m5OA1143211432epsmtip2d; Thu, 11 Nov 2021 08:47:49 +0000 (GMT) From: Jaewon Kim To: Krzysztof Kozlowski , Wolfram Sang , Rob Herring Cc: linux-samsung-soc@vger.kernel.org, linux-i2c@vger.kernel.org, chanho61.park@samsung.com, Sam Protsenko , Jaewon Kim Subject: [PATCH 1/2] dt-bindings: i2c: exynos5: add exynosautov9-hsi2c compatible Date: Thu, 11 Nov 2021 17:43:26 +0900 Message-Id: <20211111084327.106696-2-jaewon02.kim@samsung.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211111084327.106696-1-jaewon02.kim@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplk+LIzCtJLcpLzFFi42LZdljTQnfrjZ5Eg21LlSwu79e22NFwhNVi 49sfTBYdf78wWsw4v4/JonXvEXaL531A1t39cxkdODxmNfSyeWxa1cnmcefaHjaPvi2rGD0+ b5ILYI3KtslITUxJLVJIzUvOT8nMS7dV8g6Od443NTMw1DW0tDBXUshLzE21VXLxCdB1y8wB OkVJoSwxpxQoFJBYXKykb2dTlF9akqqQkV9cYquUWpCSU2BeoFecmFtcmpeul5daYmVoYGBk ClSYkJ3Rd/wIe8Ef7oqbve/ZGhhvcHYxcnJICJhIfOpdwNrFyMUhJLCDUWL2+cvMEM4nRom+ b7dZIJxvjBKz1m8FcjjAWq5/04WI72WUeLCjgR3C+cgo8WbbESaQuWwC2hLf1y9mBbFFBOok une1MoIUMQtsYpS4+GE2G8gkYYFgial3bUBqWARUJbp2PGQFCfMK2Em8vGoIcZ68xMQJ99hB bE4Be4l3E2aD2bwCghInZz5hAbGZgWqat84Gu1pC4CO7xPy9LcwQh7pInP1aADFHWOLV8S3s ELaUxOd3e9kgSuolvt5wgGjtYZRY0/WLCaLGXuLX9C1g5zALaEqs36UPUa4sceQW1FY+iY7D f9khwrwSHW1CEI1qEvennmODsGUkJh1ZCTXQQ+LfruvQgJrEKLF30hLGCYwKs5A8MwvJM7MQ Fi9gZF7FKJZaUJybnlpsVGAIj97k/NxNjOB0qeW6g3Hy2w96hxiZOBgPMUpwMCuJ8H6/1JMo xJuSWFmVWpQfX1Sak1p8iNEUGNITmaVEk/OBCTuvJN7QxNLAxMzM0NzI1MBcSZzXUjQ7UUgg PbEkNTs1tSC1CKaPiYNTqoHpwnNDK/dn9vPi20u4I9al9nxhOv3ScrPxISY1U943Aps/rG+q U43pOXLuuKSpxlyXU/NfnJWZzPa7xvnvl/NPLFi+z/UtvMHEefNgY6/D073sdzQYZ2+bck6g 3TbOXElZ5kj5PruA0pLEiskGSyPPO01ZoCSz6N2RK+5r5k3V1vfLvbrk1ylpUcNIhb8rFv9d l/PARvn29YMv1I+/jOwRVnaMcUp6YdlS5sm1Onlr+DW1fX//3vz/vKDuZfK/mJ0N7densh5Y uso0yDIwLeZ/0EoT5XD98I36Cyp2CyRLLRUR29+RbC9077nKqdotDL8mGcf1ePf//VV1deJj r5ubfjaWPBZcMSXP4P1P913sSizFGYmGWsxFxYkA8XJrWiAEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrJLMWRmVeSWpSXmKPExsWy7bCSvO7WGz2JBofW8ltc3q9tsaPhCKvF xrc/mCw6/n5htJhxfh+TReveI+wWz/uArLv75zI6cHjMauhl89i0qpPN4861PWwefVtWMXp8 3iQXwBrFZZOSmpNZllqkb5fAldF3/Ah7wR/uipu979kaGG9wdjFycEgImEhc/6bbxcjFISSw m1Hi5Iv9zF2MnEBxGYnlz/rYIGxhifstR1ghit4zSmx50swKkmAT0Jb4vn4xWEJEoIFR4u23 RUwgCWaBbYwSTQ3lIBuEBQIlrhzwAwmzCKhKdO14yAoS5hWwk3h51RBivrzExAn32EFsTgF7 iXcTZoPZQkAlC1c/B7uHV0BQ4uTMJywQ0+UlmrfOZp7AKDALSWoWktQCRqZVjJKpBcW56bnF hgWGeanlesWJucWleel6yfm5mxjBoa2luYNx+6oPeocYmTgYDzFKcDArifB+v9STKMSbklhZ lVqUH19UmpNafIhRmoNFSZz3QtfJeCGB9MSS1OzU1ILUIpgsEwenVAOTcoB98ykDB/98i5CC /vj6Zu42/icep2ZwrrGJVVr6Icl9geR1o9SaiQvV3mX79WesVPb2WtUzPSfZ+/Dz50evZKlF /ti94eiy2qvr7QMnqtSfu1uyZ+9uH8GKkF9S5c+13pzjW66saeUTWb/z46q8lct+zBGTYDvS m6kz7Vs7z3+rNdP/sJSJlk+p9y5zippWsmTLzsBs15TFuSnRnq6839bwNAa82GH3zIX/4DoG yV0qDldlnAIfc7evEFohre4t93G7vUBzQtGVhsef2l8Udmal3Jhe80La9VynT0Tpke7p5yo+ LFnJuHy7xfvwpU8ZBaqtC3fq3bp3v/R70iue5fyv3krItT27IS6gLqDEUpyRaKjFXFScCABJ ESI/3AIAAA== X-CMS-MailID: 20211111084749epcas2p291a982cce677c58febcf00d5d900c4a5 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20211111084749epcas2p291a982cce677c58febcf00d5d900c4a5 References: <20211111084327.106696-1-jaewon02.kim@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This patch adds new "samsung,exynosautov9-hsi2c" compatible. It is for i2c compatible with HSI2C available on Exynos SoC with USI. Signed-off-by: Jaewon Kim --- Documentation/devicetree/bindings/i2c/i2c-exynos5.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt index 2dbc0b62daa6..39f4067d9d1f 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt @@ -14,6 +14,8 @@ Required properties: on Exynos5260 SoCs. -> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available on Exynos7 SoCs. + -> "samsung,exynosautov9-hsi2c", for i2c compatible with HSI2C available + on ExynosAutov9 SoCs. - reg: physical base address of the controller and length of memory mapped region. @@ -31,6 +33,11 @@ Optional properties: at 100khz. -> If specified, the bus operates in high-speed mode only if the clock-frequency is >= 1Mhz. + - samsung,sysreg : system registers controller phandle to control USI. + -> If I2C integrated to USI(Universal Serial Interface), this property + is required. When using Exynos USI block, it needs to select which type + of Serial IPs(UART, SPI, I2C) to use with system register. So, it + requires samsung,sysreg phandle and offset value of system register. Example: From patchwork Thu Nov 11 08:43:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaewon Kim X-Patchwork-Id: 517486 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC1CEC433F5 for ; Thu, 11 Nov 2021 08:48:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C08A261208 for ; Thu, 11 Nov 2021 08:48:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232256AbhKKIuz (ORCPT ); Thu, 11 Nov 2021 03:50:55 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:25042 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229649AbhKKIuw (ORCPT ); Thu, 11 Nov 2021 03:50:52 -0500 Received: from epcas2p4.samsung.com (unknown [182.195.41.56]) by mailout3.samsung.com (KnoxPortal) with ESMTP id 20211111084801epoutp036aec85c25c71d62290cc67c59d68d902~2cagJfukr0336403364epoutp03q for ; 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Thu, 11 Nov 2021 17:47:49 +0900 (KST) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas2p1.samsung.com (KnoxPortal) with ESMTPA id 20211111084749epcas2p1e80b3f3657310498bfdae65c425b3278~2caVMuCo20752207522epcas2p1_; Thu, 11 Nov 2021 08:47:49 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20211111084749epsmtrp1e5a3985c46446422d9b4062680b4b868~2caVMBTyl2177521775epsmtrp1Y; Thu, 11 Nov 2021 08:47:49 +0000 (GMT) X-AuditID: b6c32a45-c69bba800000ca37-07-618cd8b5441f Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id B9.C8.08738.5B8DC816; Thu, 11 Nov 2021 17:47:49 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20211111084749epsmtip2ca99504cac0149ce945a00c71ce6451a~2caVClHu41450214502epsmtip2j; Thu, 11 Nov 2021 08:47:49 +0000 (GMT) From: Jaewon Kim To: Krzysztof Kozlowski , Wolfram Sang , Rob Herring Cc: linux-samsung-soc@vger.kernel.org, linux-i2c@vger.kernel.org, chanho61.park@samsung.com, Sam Protsenko , Jaewon Kim Subject: [PATCH 2/2] i2c: exynos5: add support for ExynosAutov9 SoC Date: Thu, 11 Nov 2021 17:43:27 +0900 Message-Id: <20211111084327.106696-3-jaewon02.kim@samsung.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211111084327.106696-1-jaewon02.kim@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnk+LIzCtJLcpLzFFi42LZdljTTHfrjZ5Egyu/1Cwu79e22NFwhNVi 49sfTBYdf78wWsw4v4/JonXvEXaL531A1t39cxkdODxmNfSyeWxa1cnmcefaHjaPvi2rGD0+ b5ILYI3KtslITUxJLVJIzUvOT8nMS7dV8g6Od443NTMw1DW0tDBXUshLzE21VXLxCdB1y8wB OkVJoSwxpxQoFJBYXKykb2dTlF9akqqQkV9cYquUWpCSU2BeoFecmFtcmpeul5daYmVoYGBk ClSYkJ3x7+hOpoJPdhVrL5Y1ME416mLk5JAQMJFYOHU9axcjF4eQwA5GiR1f97JAOJ8YJTo3 dbBBOJ8ZJea1b2GDaZly5Rk7RGIXo8TJb8cZIZyPjBLtL7aDVbEJaEt8X7+YFcQWEaiT6N7V ClbELLCJUeLih9lgRcICzhK7bq5l7mLk4GARUJU4sEMUJMwrYCex8vkEJoht8hITJ9xjB7E5 Bewl3k2YzQ5RIyhxcuYTFhCbGaimeetsZpD5EgIv2SX271zKCtHsIjHr2gUWCFtY4tXxLewQ tpTEy/42dpC9EgL1El9vOED09jBKrOn6BbXYXuLX9C2sIDXMApoS63fpQ5QrSxy5BbWWT6Lj 8F+oKbwSHW1CEI1qEvennoOGlYzEpCMroQZ6SLT93wwN6kmMEqd3vmGZwKgwC8k3s5B8Mwth 8QJG5lWMYqkFxbnpqcVGBYbwCE7Oz93ECE6ZWq47GCe//aB3iJGJg/EQowQHs5II7/dLPYlC vCmJlVWpRfnxRaU5qcWHGE2BQT2RWUo0OR+YtPNK4g1NLA1MzMwMzY1MDcyVxHktRbMThQTS E0tSs1NTC1KLYPqYODilGphWLrhu5fkowdS74c/hVTHH9nW379Te9njRtoO9s/4wzwsv7FJe o/f2ULe2S1rO/LJb2auW7HedxuEtEDe5cffxa1OeV0yv6P0zKUFtenp17q8SvxSx78ePMmlw eFVnfYo5d6n80NGlAe+WeUa798a4hbZUPH0nPLPh/oJfjT8YdM2Clv6PvfVQsK7hX9CCUN/d P2r5Ge7MvV+v0Vh/xX3ztGOX05ZsyT3MGZSYGtYhYXX3nEtJ6PPZ9+30FqvfCDhwdYrSmm28 KoZzLQ9PTcvz0vcRZIjmnVHeqztx983YD/+1TyaEXb3JNPOf+3ImHtVJV2Ysusso+sVCRWSj 9fJbH7ZeFnjTKVekodj/R6lTiaU4I9FQi7moOBEAKa9xISIEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFLMWRmVeSWpSXmKPExsWy7bCSvO7WGz2JBteXC1lc3q9tsaPhCKvF xrc/mCw6/n5htJhxfh+TReveI+wWz/uArLv75zI6cHjMauhl89i0qpPN4861PWwefVtWMXp8 3iQXwBrFZZOSmpNZllqkb5fAlfHv6E6mgk92FWsvljUwTjXqYuTkkBAwkZhy5Rl7FyMXh5DA DkaJznPfWSESMhLLn/WxQdjCEvdbjrBCFL1nlHi+dQ87SIJNQFvi+/rFYAkRgQZGibffFjGB JJgFtjFKNDWUg9jCAs4Su26uZe5i5OBgEVCVOLBDFCTMK2AnsfL5BCaIBfISEyfcA5vJKWAv 8W7CbDBbCKhm4ernzBD1ghInZz5hgRgvL9G8dTbzBEaBWUhSs5CkFjAyrWKUTC0ozk3PLTYs MMpLLdcrTswtLs1L10vOz93ECA5uLa0djHtWfdA7xMjEwXiIUYKDWUmE9/ulnkQh3pTEyqrU ovz4otKc1OJDjNIcLErivBe6TsYLCaQnlqRmp6YWpBbBZJk4OKUamLzn9zXWrWBKX/O5rTWI JfHIQf6C5K1Bqy85dCz+HGbyKmWm7s+Nnr57Y1tcFJK1kroW5rLfZZU5qFV8oVonfn/apyAn rbKXOQzeRpNmse6riNuxs6X2rfnb/reRLSV6Mz5etM6rkGSu2clw93T9pJSeY/vZu149PvIx vsM/pd5maoUpv3gNp86amX5NW4p2nEuqLNaczR/y2HJeA7v8qpLkYGkFXbaD82W8cl+cjJkT NIc1I8snr28T16rq0rfZ0asDY30/LVM7t3ItQ87G3pyqhrhohkCXD3GTbnEF3ToVVcTdm8G2 TyHKgnn9y3eXq1YHsRyLqpuRWB0UXd/GZS/8r2tyYHJsZmy6hxJLcUaioRZzUXEiAK0giO/d AgAA X-CMS-MailID: 20211111084749epcas2p1e80b3f3657310498bfdae65c425b3278 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20211111084749epcas2p1e80b3f3657310498bfdae65c425b3278 References: <20211111084327.106696-1-jaewon02.kim@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Serial IPs(UART, I2C, SPI) are integrated into New IP-Core called USI(Universal Serial Interface). As it is integrated into USI, there are additinal HW changes. Registers to control USI and sysreg to set serial IPs have been added. Also, some timing registres have been changed. Signed-off-by: Jaewon Kim --- drivers/i2c/busses/i2c-exynos5.c | 133 ++++++++++++++++++++++++++++--- 1 file changed, 123 insertions(+), 10 deletions(-) diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c index 97d4f3ac0abd..6a05af550aa5 100644 --- a/drivers/i2c/busses/i2c-exynos5.c +++ b/drivers/i2c/busses/i2c-exynos5.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include /* * HSI2C controller from Samsung supports 2 modes of operation @@ -166,9 +168,21 @@ #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(100)) +/* USI(Universal Serial Interface) Register map */ +#define USI_CON 0xc4 +#define USI_OPTION 0xc8 + +/* USI(Universal Serial Interface) Register bits */ +#define USI_CON_RESET BIT(0) + +/* SYSREG Register bit */ +#define SYSREG_USI_SW_CONF_MASK (0x7 << 0) +#define SYSREG_I2C_SW_CONF BIT(2) + enum i2c_type_exynos { I2C_TYPE_EXYNOS5, I2C_TYPE_EXYNOS7, + I2C_TYPE_EXYNOSAUTOV9, }; struct exynos5_i2c { @@ -199,6 +213,10 @@ struct exynos5_i2c { /* Version of HS-I2C Hardware */ const struct exynos_hsi2c_variant *variant; + + /* USI sysreg info */ + struct regmap *usi_sysreg; + unsigned int usi_offset; }; /** @@ -212,24 +230,34 @@ struct exynos5_i2c { */ struct exynos_hsi2c_variant { unsigned int fifo_depth; + unsigned int has_usi; enum i2c_type_exynos hw; }; static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = { .fifo_depth = 64, + .has_usi = 0, .hw = I2C_TYPE_EXYNOS5, }; static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = { .fifo_depth = 16, + .has_usi = 0, .hw = I2C_TYPE_EXYNOS5, }; static const struct exynos_hsi2c_variant exynos7_hsi2c_data = { .fifo_depth = 16, + .has_usi = 0, .hw = I2C_TYPE_EXYNOS7, }; +static const struct exynos_hsi2c_variant exynosautov9_hsi2c_data = { + .fifo_depth = 64, + .has_usi = 1, + .hw = I2C_TYPE_EXYNOSAUTOV9, +}; + static const struct of_device_id exynos5_i2c_match[] = { { .compatible = "samsung,exynos5-hsi2c", @@ -243,6 +271,9 @@ static const struct of_device_id exynos5_i2c_match[] = { }, { .compatible = "samsung,exynos7-hsi2c", .data = &exynos7_hsi2c_data + }, { + .compatible = "samsung,exynosautov9-hsi2c", + .data = &exynosautov9_hsi2c_data }, {}, }; MODULE_DEVICE_TABLE(of, exynos5_i2c_match); @@ -281,6 +312,31 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings) i2c->op_clock; int div, clk_cycle, temp; + /* In case of HSI2C controllers in EXYNOSAUTOV9 + * timing control formula changed. + * + * FSCL = IPCLK / ((CLK_DIV + 1) * 16) + * T_SCL_LOW = IPCLK * (CLK_DIV + 1) * (N + M) + * [N : number of 0's in the TSCL_H_HS] + * [M : number of 0's in the TSCL_L_HS] + * T_SCL_HIGH = IPCLK * (CLK_DIV + 1) * (N + M) + * [N : number of 1's in the TSCL_H_HS] + * [M : number of 1's in the TSCL_L_HS] + * + * result of (N + M) is always 8. + * In general use case, we don't need to control timing_s1, timing_s2. + */ + if (i2c->variant->hw == I2C_TYPE_EXYNOSAUTOV9) { + div = ((clkin / (16 * i2c->op_clock)) - 1); + i2c_timing_s3 = div << 16; + if (hs_timings) + writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); + else + writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); + + return 0; + } + /* * In case of HSI2C controller in Exynos5 series * FPCLK / FI2C = @@ -355,6 +411,20 @@ static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c) return exynos5_i2c_set_timing(i2c, true); } +static void exynos_usi_reset(struct exynos5_i2c *i2c) +{ + u32 val; + + val = readl(i2c->regs + USI_CON); + val |= USI_CON_RESET; + writel(val, i2c->regs + USI_CON); + udelay(1); + + val = readl(i2c->regs + USI_CON); + val &= ~USI_CON_RESET; + writel(val, i2c->regs + USI_CON); +} + /* * exynos5_i2c_init: configures the controller for I2C functionality * Programs I2C controller for Master mode operation @@ -385,6 +455,9 @@ static void exynos5_i2c_reset(struct exynos5_i2c *i2c) { u32 i2c_ctl; + if (i2c->variant->hw == I2C_TYPE_EXYNOSAUTOV9) + exynos_usi_reset(i2c); + /* Set and clear the bit for reset */ i2c_ctl = readl(i2c->regs + HSI2C_CTL); i2c_ctl |= HSI2C_SW_RST; @@ -422,7 +495,8 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id) writel(int_status, i2c->regs + HSI2C_INT_STATUS); /* handle interrupt related to the transfer status */ - if (i2c->variant->hw == I2C_TYPE_EXYNOS7) { + if (i2c->variant->hw == I2C_TYPE_EXYNOS7 || + i2c->variant->hw == I2C_TYPE_EXYNOSAUTOV9) { if (int_status & HSI2C_INT_TRANS_DONE) { i2c->trans_done = 1; i2c->state = 0; @@ -569,13 +643,13 @@ static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c) { unsigned long timeout; - if (i2c->variant->hw != I2C_TYPE_EXYNOS7) + if (i2c->variant->hw == I2C_TYPE_EXYNOS5) return; /* - * HSI2C_MASTER_ST_LOSE state in EXYNOS7 variant before transaction - * indicates that bus is stuck (SDA is low). In such case bus recovery - * can be performed. + * HSI2C_MASTER_ST_LOSE state in EXYNOS7 or EXYNOSAUTOV9 variant before + * transaction indicates that bus is stuck (SDA is low). + * In such case bus recovery can be performed. */ timeout = jiffies + msecs_to_jiffies(100); for (;;) { @@ -611,10 +685,10 @@ static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop) unsigned long flags; unsigned short trig_lvl; - if (i2c->variant->hw == I2C_TYPE_EXYNOS7) - int_en |= HSI2C_INT_I2C_TRANS; - else + if (i2c->variant->hw == I2C_TYPE_EXYNOS5) int_en |= HSI2C_INT_I2C; + else + int_en |= HSI2C_INT_I2C_TRANS; i2c_ctl = readl(i2c->regs + HSI2C_CTL); i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON); @@ -738,6 +812,41 @@ static const struct i2c_algorithm exynos5_i2c_algorithm = { .functionality = exynos5_i2c_func, }; +static int exynos_usi_init(struct exynos5_i2c *i2c) +{ + struct device *dev = i2c->dev; + int ret; + + if (!i2c->variant->has_usi) + return 0; + + /* System Register has a field that can select the serial IP + * provided by USI. We need to set it to I2C to use I2C. + */ + i2c->usi_sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, + "samsung,sysreg"); + if (IS_ERR(i2c->usi_sysreg)) { + dev_err(dev, "Cannot find sysreg\n"); + return PTR_ERR(i2c->usi_sysreg); + } + + ret = of_property_read_u32_index(dev->of_node, "samsung,sysreg", + 1, &i2c->usi_offset); + if (ret) { + dev_err(dev, "sysreg offset is not specified\n"); + return ret; + } + + ret = regmap_update_bits(i2c->usi_sysreg, i2c->usi_offset, + SYSREG_USI_SW_CONF_MASK, SYSREG_I2C_SW_CONF); + if (ret < 0) + return ret; + + exynos_usi_reset(i2c); + + return 0; +} + static int exynos5_i2c_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -777,6 +886,12 @@ static int exynos5_i2c_probe(struct platform_device *pdev) i2c->adap.algo_data = i2c; i2c->adap.dev.parent = &pdev->dev; + i2c->variant = of_device_get_match_data(&pdev->dev); + + ret = exynos_usi_init(i2c); + if (ret) + return ret; + /* Clear pending interrupts from u-boot or misc causes */ exynos5_i2c_clr_pend_irq(i2c); @@ -794,8 +909,6 @@ static int exynos5_i2c_probe(struct platform_device *pdev) goto err_clk; } - i2c->variant = of_device_get_match_data(&pdev->dev); - ret = exynos5_hsi2c_clock_setup(i2c); if (ret) goto err_clk;