From patchwork Thu Nov 25 22:46:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 517251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D073BC433EF for ; Thu, 25 Nov 2021 22:57:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348464AbhKYXBF (ORCPT ); Thu, 25 Nov 2021 18:01:05 -0500 Received: from smtp-16.italiaonline.it ([213.209.10.16]:35207 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1345426AbhKYW7F (ORCPT ); Thu, 25 Nov 2021 17:59:05 -0500 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([95.244.92.113]) by smtp-16.iol.local with ESMTPA id qNWimq44e7VizqNWommHba; Thu, 25 Nov 2021 23:47:42 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1637880462; bh=hjJJ1fZhVpUryCS9ibJFEx4dC0BCjRfmiHs1Thqyd/Q=; h=From; b=Q/Nd6NNdkDKg/qUlKlxBz3gz644CmxFdR/wfOCCXCiqdWNCPQO+qwSVewsDIHZyS1 dxalD7JjKZEcrXtbwRkJ4AzeCH2mjCVLNc6bMRpxZajMHz3zK/7fZqu0c1JNGmzIXo EzC4s6/fVmS5VXtENJTpembCV8IsdigFwftuE95diNM0Ut+UXbzQy+LHXuzegLkhPJ re/aGbfABZlqlOuIBE6pSLL7XwKRA49jTmQtrC7G+ZXm14itwERGysV4wEB1g9gkSE lwbd5Oe0x56Sz3t65qSZ98+pDzjsP9HFA5RSSNsp2MwVcj5Cmf10jYLU8SdsxOjSQy XVPbTpmYsr/Kw== X-CNFS-Analysis: v=2.4 cv=ftYZ2H0f c=1 sm=1 tr=0 ts=61a0128e cx=a_exe a=GpwmefRDj0jp2XoEX/Ct1w==:117 a=GpwmefRDj0jp2XoEX/Ct1w==:17 a=Lf7JvCFZlXs7EqoJDM0A:9 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Sebastian Andrzej Siewior , linux-input@vger.kernel.org, Felipe Balbi , Zubair Lutfullah , Grygorii Strashko , Dmitry Torokhov , Dave Gerlach , "Andrew F . Davis" , Vignesh R , Lee Jones , Wolfram Sang , Brad Griffis , Jeff Lance , Rachna Patil , Dario Binacchi Subject: [PATCH v2 1/4] input: ti_am335x_tsc: set ADCREFM for X configuration Date: Thu, 25 Nov 2021 23:46:39 +0100 Message-Id: <20211125224642.21011-2-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211125224642.21011-1-dariobin@libero.it> References: <20211125224642.21011-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfIjIJBF/EBkAIXJbRbYZN5XV7GEYgt8vdiL520FiRRjFv9tibxNSGzUqCbp9gzfblihuHK9iHi7gARfzHRA78fj+agUcNzdp16aYOBzZ1iXOdVMIbN3N 3zRe+Opp+HIwlO0FlCToRgmTBg8Iy7EUylpoob6V/F1M6kAuKZ5eUnY9zR4/8epmH+O4jHU9wnj/yF2l8gqNtl4F+T6Yo9Ok3D1VyrjT3wycmfQ+NtksjKuA 4oAzhJ1nuiJHMig0/ZzpALkKI/TiE+sjEW7JMZdVnnbZ3VJGAUBzR3tla7fLZd17YSBkGLoxj7vT7zMUloWrhH5G8EPdBZhonAhk3j2y2E55TYY87pThYRmZ Mu2vWKhzsOaLDHDtpFOMtQksgSGK07HNHWv8sGQlgnYOI3hiyd6R7vvNioY7kydUwqf7SI/mWmgf3jcJklSeLW9tHR+4cKQfgK5ErXzg6fXcsW6DR+SxOqw4 JwV5XGsDiTR6OnVPPkJsPZRQueA3PF/jAgPbQljiFCXu8UEzgs13els2hBk/ovkXwM6FlvyrFuAn6yazXQBfPjH14+d0NChh4MNjm/ZCnMLXiZ/uMteJpotO HurRszGCRUB6X7dIdliwX+OtxFFpj6E4Lbcd6pg9V9RrVIT2xUQiMHkULJgf1ddXtH5HJicwh5l8UWh5u4jjijT24gKhEfiVs5yzGHi3KjS80A== Precedence: bulk List-ID: X-Mailing-List: linux-input@vger.kernel.org As reported by the STEPCONFIG[1-16] registered field descriptions of the TI reference manual, for the ADC "in single ended, SEL_INM_SWC_3_0 must be 1xxx". Unlike the Y and Z coordinates, this bit has not been set for the step configuration registers used to sample the X coordinate. Fixes: 1b8be32e691 ("Input: add support for TI Touchscreen controller") Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/input/touchscreen/ti_am335x_tsc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/input/touchscreen/ti_am335x_tsc.c b/drivers/input/touchscreen/ti_am335x_tsc.c index 83e685557a19..fd3ffdd23470 100644 --- a/drivers/input/touchscreen/ti_am335x_tsc.c +++ b/drivers/input/touchscreen/ti_am335x_tsc.c @@ -131,7 +131,8 @@ static void titsc_step_config(struct titsc *ts_dev) u32 stepenable; config = STEPCONFIG_MODE_HWSYNC | - STEPCONFIG_AVG_16 | ts_dev->bit_xp; + STEPCONFIG_AVG_16 | ts_dev->bit_xp | + STEPCONFIG_INM_ADCREFM; switch (ts_dev->wires) { case 4: config |= STEPCONFIG_INP(ts_dev->inp_yp) | ts_dev->bit_xn; From patchwork Thu Nov 25 22:46:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 517249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44218C433F5 for ; Thu, 25 Nov 2021 23:02:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235233AbhKYXGK (ORCPT ); Thu, 25 Nov 2021 18:06:10 -0500 Received: from smtp-16.italiaonline.it ([213.209.10.16]:59014 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S236157AbhKYXEK (ORCPT ); Thu, 25 Nov 2021 18:04:10 -0500 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([95.244.92.113]) by smtp-16.iol.local with ESMTPA id qNWimq44e7VizqNWpmmHco; Thu, 25 Nov 2021 23:47:44 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1637880464; bh=I9nLUTq/N/FwQwyX4ZdYepYccPs/T7kCUn7G3ZT1WTI=; h=From; b=XEfLFo2XD0ciWZgau0NXhJBGI2Dc9yzdobxclUFpzZYYQ+ULTdtLT5T8Jvmd0QOJJ kTl9Nn7eCLpUL6729ZDcv/UDjLNNwKjLuZxjRDQ8qz+ZI8kkc2HiDUaOVQ6gsijBSV L+08tYbzW0pnEs/ySqaZYiBvZ7/mu6r65DfNDNNu1xZfuqIi3qjehZD0dKGNUYn+le rA1LrmAWkYnfX/NOhLQArF2E3QSba+WIog7HfCGaYrdLQSI9KxeR47aqZNmQ+aIl1w Nzji3lN4EqOgWAy0nlDf++jEfzF7mMOGz1umZap62oE9L9SHJQaB5+jaOpGtbsOBGc YCrEALU3IwKdA== X-CNFS-Analysis: v=2.4 cv=ftYZ2H0f c=1 sm=1 tr=0 ts=61a01290 cx=a_exe a=GpwmefRDj0jp2XoEX/Ct1w==:117 a=GpwmefRDj0jp2XoEX/Ct1w==:17 a=HJ_RBZq0nG6KkHQLv6MA:9 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Sebastian Andrzej Siewior , linux-input@vger.kernel.org, Felipe Balbi , Zubair Lutfullah , Grygorii Strashko , Dmitry Torokhov , Dave Gerlach , "Andrew F . Davis" , Vignesh R , Lee Jones , Wolfram Sang , Brad Griffis , Jeff Lance , Rachna Patil , Dario Binacchi Subject: [PATCH v2 4/4] mfd: ti_am335x_tscadc: drop the CNTRLREG_TSC_8WIRE macro Date: Thu, 25 Nov 2021 23:46:42 +0100 Message-Id: <20211125224642.21011-5-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211125224642.21011-1-dariobin@libero.it> References: <20211125224642.21011-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfGVLr6ntdTCgx6VsGugYMeHKd/kIF2rMD544U4L/6quwm911CIAwT/kRVuu7QxCSClksUcQo6y7PWNCwAW6Xx8GVqxiQ+joMWzbp/hdip0vCApJUBWQE VobOKE/72HsMs5u/LJ7x25+dxRkv7sx+kkTy65sWITlGPLjxjqhN55oOUHIsY72aHHnOF+iKXSD/mibWOGN+jNwEfT7GG6Y24k51GJY7cuYAYznAj8NerB+9 5UQqtycd/8EBSX1jUvyxT1Vb+y7Bkwu6vhGjGX3EGXqxPXvjL99K0kQ4DKuSfx+SaNWK8ajRsYynqHClKbZD7mxaxLgZRaDdubXljN4B2TEpXX+yJCsDNbiS pAS3XA1IdbH/VjwwW7tSSW+WtKucVRNWasJUbpQW2zhR8tCsYPMTe5H6DFMyw5uHDgHnmjXcbITPJuLMhi9gfYgWuJ1A0aUaiAeqENt0dT2obkPt60E9yex3 kPErwH5OpjC68PWNXvQRlWNNVuJmJZ3ybs/6lbH6CBrreW94YvE3hZn3oZydSiry+DDsRQmOwILd+TjseD4Q+FfoK2pVR0YrUgtdrn8sU0tTrZkGM6gNiYCr pFo0FfTw5D8DjsrtZQUIFn/sDvRSP1yWySbJxteEf1VBYGgSjKs1+52wAqC/uMIDOG4bedPMqR4hEPvdJFqUGqXns83DwZYIaw9o4mL/eCvpbg== Precedence: bulk List-ID: X-Mailing-List: linux-input@vger.kernel.org In TI's reference manual description for the `AFE_Pen_Ctrl' bit-field of the TSC's CTRL register, there is no mention of 8-wire touchscreens. Even commit f0933a60d190 ("mfd: ti_am335x_tscadc: Update logic in CTRL register for 5-wire TS") says that the value of this bit-field must be the same for 4-wire and 8-wire touchscreens. So let's remove the CNTRLREG_TSC_8WIRE macro to avoid misunderstandings. Signed-off-by: Dario Binacchi --- Changes in v2: - Replace CNTRLREG_8WIRE with CNTRLREG_TSC_8WIRE. In the meantime, the file ti_am335x_tscadc.h has been modified, so the patch must be updated. include/linux/mfd/ti_am335x_tscadc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h index ba13e043d910..4063b0614d90 100644 --- a/include/linux/mfd/ti_am335x_tscadc.h +++ b/include/linux/mfd/ti_am335x_tscadc.h @@ -103,7 +103,6 @@ #define CNTRLREG_TSC_AFE_CTRL(val) FIELD_PREP(GENMASK(6, 5), (val)) #define CNTRLREG_TSC_4WIRE CNTRLREG_TSC_AFE_CTRL(1) #define CNTRLREG_TSC_5WIRE CNTRLREG_TSC_AFE_CTRL(2) -#define CNTRLREG_TSC_8WIRE CNTRLREG_TSC_AFE_CTRL(3) #define CNTRLREG_TSC_ENB BIT(7) /*Control registers bitfields for MAGADC IP */