From patchwork Thu Nov 18 13:21:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= X-Patchwork-Id: 517145 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF910C433F5 for ; Thu, 18 Nov 2021 13:22:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9A46561B29 for ; Thu, 18 Nov 2021 13:22:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230356AbhKRNZN (ORCPT ); Thu, 18 Nov 2021 08:25:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229786AbhKRNZM (ORCPT ); Thu, 18 Nov 2021 08:25:12 -0500 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E154C061570; Thu, 18 Nov 2021 05:22:12 -0800 (PST) Received: by mail-lf1-x12c.google.com with SMTP id t26so25871711lfk.9; Thu, 18 Nov 2021 05:22:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1L/0A+EuKJ6gwcEMDegZLhyHztp3BPqMAMC2myjRsJM=; b=DFcM0FNX12scIGyvbPCM2H5y28UU0wv+aI2RqgNj0OtQKMyNnCcHryqHnVOa1tBer6 W746hN0xeGdBuFwrCubyeX7hET9JE4diWo0Pu/foQHrUDW3fnBA+QvatOs9aZfK3pw6Y j5IVzLTYgvn0aOYg9L7lJzhMOebjCUZa09SWbs06FfNm90poA4NmINFfmp2VrK6WWlwl rPB5p/oMM6F3H3LYq/R5Em+P4m0i2GM1CZy1199LDuQu8TR88OcKRcLahwRmXOxuHyoL vJ7USf2M/lJ81zKhyrGKuodSpeJfWanJI8V5lQaDwdfg0YlJvdE2hUJoVy53rVFuBJwe M+9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1L/0A+EuKJ6gwcEMDegZLhyHztp3BPqMAMC2myjRsJM=; b=LH/GdJxUbU10JlskWb/369hrI7f82AiPLgKQIAmtrjE6tIwU+DgP0gaXc6akque7PC CYeropsnzKMuD1a4kDJsww8QZDmASvVh3A+85m18hSnnXvuhf/GfKcVR4CB4Kc+wKSOB XWh7bz+2lmX6tTfR97nuS+/Au7pJrFEDg/BnpetkunMp019kkvis+ZaopGyHW9CZ2mlj GLipQkbn1XJCpZiUukVdHnstFkjqpqTvurfxCTQyZKpfaAgd6sjNiJ1OG0OyUX70+OYx MDabjCfTqNGh96E4EvBxfzTOhq3Yy/WtpLQpuEHVMMwaChRx9ewO1JnIPDyw1v9teqXB rCfw== X-Gm-Message-State: AOAM530D2cdE+ytTrY8Sr5jEIN48bz8JyHhp2AAOBk/bxuiNX54CDEWN oWNoZm8ACHLw25DKUFqT78ZaZseXCFk= X-Google-Smtp-Source: ABdhPJxatszYdUlQDFHsrWqVZvd2OcxvxsKkd5VxJMlO3v0Oc4JF2ibpfqSmY9htcaCbpg56QWFbTg== X-Received: by 2002:a2e:a305:: with SMTP id l5mr16881369lje.73.1637241730772; Thu, 18 Nov 2021 05:22:10 -0800 (PST) Received: from localhost.lan (ip-194-187-74-233.konfederacka.maverick.com.pl. [194.187.74.233]) by smtp.gmail.com with ESMTPSA id bp36sm356550lfb.0.2021.11.18.05.22.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Nov 2021 05:22:10 -0800 (PST) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Linus Walleij , Rob Herring Cc: Tony Lindgren , Andy Shevchenko , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= Subject: [PATCH 1/5] dt-bindings: pinctrl: support specifying pins, groups & functions Date: Thu, 18 Nov 2021 14:21:48 +0100 Message-Id: <20211118132152.15722-2-zajec5@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211118132152.15722-1-zajec5@gmail.com> References: <20211118132152.15722-1-zajec5@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Rafał Miłecki This binding change is meant to introduce a generic way of describing pinctrl blocks details. Every pinmux block is expected to have: 1. Named pins 2. Named groups containing one or more pins 3. Named functions referencing one or more groups It doesn't describe how hw should be programmed. That is still binding specific. This commit describes syntax for "pins", "groups" & "functions" nodes in a standard pinctrl binding. Every above node allows specifying its entries and it's done using subnodes because: 1. It's required with reg = ("pins") 2. It's generic & extendable (hw specific properties can be added) Pins are number based so they use reg = . It's also required as binding needs to allow gaps. It's to avoid hacks like: pins = <"foo" "-ENODEV" "-ENODEV" "-ENODEV" "bar">; (for hw with pins 0 and 4 present). Subnodes also allow storing hw specific pin/group/function configuration. While it would be possible to have: groups { foo-pins = <0 1>; bar-pins = <2 3>; }; that doesn't allow hw specific quirks. Introduced design allows e.g.: groups { foo { pins = <0 1>; vendor,magic = <0xbeaf>; }; }; Signed-off-by: Rafał Miłecki --- .../devicetree/bindings/pinctrl/pinctrl.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml index d471563119a9..1a99920e94ef 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml @@ -42,4 +42,54 @@ properties: This property can be set either globally for the pin controller or in child nodes for individual pin group control. + pins: + type: object + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + patternProperties: + "^pin@[0-9a-z]+$": + type: object + + properties: + reg: + description: Pin number + + label: + description: Pin name + $ref: /schemas/types.yaml#/definitions/string + + additionalProperties: false + + groups: + type: object + + patternProperties: + "^.*$": + type: object + description: Group identified by node name + + properties: + pins: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Array of pins belonging to this group + + functions: + type: object + + patternProperties: + "^.*$": + type: object + description: Function identified by node name + + properties: + groups: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: Array of pins groups used by this function + additionalProperties: true From patchwork Thu Nov 18 13:21:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= X-Patchwork-Id: 517144 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE8FAC433EF for ; Thu, 18 Nov 2021 13:22:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D990861BB6 for ; Thu, 18 Nov 2021 13:22:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230368AbhKRNZQ (ORCPT ); Thu, 18 Nov 2021 08:25:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229786AbhKRNZP (ORCPT ); Thu, 18 Nov 2021 08:25:15 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9139BC061570; Thu, 18 Nov 2021 05:22:15 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id bi37so25939074lfb.5; Thu, 18 Nov 2021 05:22:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W1ozSFTzW6iBlqeGsm7xnlG661/HZOcRaphE0Mn8yuQ=; b=WSn1/wog/OwyjfdshRgjE58acBoLdQrXIxGyAsMo4nxV8MNHwFCqkpgLgdnR76rwqa Nn7dsAacuOuRP8yfs1zcIgm8XtNpzSnl02LbuHNGktmHxFodApoY++CuqY5zDtMKZ21v F0KrZn6XFxC+Zt1IfaJbUZcxI+/oMFhCr6wKGxV/FbY25UWySE4YoS1wCwWCiLgyye7d TESFHk3zwvpCdTQ/T44OQNvzp0gGaKB800oIWbWCVbS6yQL9woZKMvd5vBdtfSWnO7Z7 YxYdPf85AnHhHv4AnZHU4ODsw60AA/GCXw/n6euTP833uLcEXd3GFwv71MHcotFiFzUA mc5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W1ozSFTzW6iBlqeGsm7xnlG661/HZOcRaphE0Mn8yuQ=; b=a9ApqY5MqM7hh0m2rvpyJW/dQ2SkgAiY/Z3opLKWXHcKuVdEQm3y79o/QoIn4akp7e 1MJGbhsf51AKxnKyHDQNL4zWL7M1e3CUIXg2bOHTjOl5KJPXghE7s4NW62v2gxuoG1sl s9RLDCvz4Ieu+sPXd8bzYDP7IdAY65ElIBRH8dQWwQPaplrIl4+arvB+x4dfQzcgkNMm VqEtKK1TNF26MX9Eo8HQzUcXL+PZCer2EM6xaT2Yi5MN5uAT8vynrKg+rcbV55XDD5b7 2727dESqZPUxs56EsIyk60ddTGMs4Ey7+ELE36glRB/eTePoTQhE3FGz9AAgcfIeazqw t/bQ== X-Gm-Message-State: AOAM532jICN/aKrFUq+GW1UPNW5fPqSe2agffpbvz3b8uDGOTjitOtWn U0oOthQaTOSPiqRldIQ/EwSF2CxseT0= X-Google-Smtp-Source: ABdhPJzhPd3NwZM5kPJNaUrl8UlVEtayxqeTmnQVBr71WveoL1dTgaUVbSqEMK4nQaAyG4q2PA8DgA== X-Received: by 2002:a2e:9e94:: with SMTP id f20mr8987115ljk.401.1637241733983; Thu, 18 Nov 2021 05:22:13 -0800 (PST) Received: from localhost.lan (ip-194-187-74-233.konfederacka.maverick.com.pl. [194.187.74.233]) by smtp.gmail.com with ESMTPSA id bp36sm356550lfb.0.2021.11.18.05.22.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Nov 2021 05:22:13 -0800 (PST) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Linus Walleij , Rob Herring Cc: Tony Lindgren , Andy Shevchenko , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= Subject: [PATCH 3/5] pinctrl: add helpers reading pins, groups & functions from DT Date: Thu, 18 Nov 2021 14:21:50 +0100 Message-Id: <20211118132152.15722-4-zajec5@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211118132152.15722-1-zajec5@gmail.com> References: <20211118132152.15722-1-zajec5@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Rafał Miłecki DT binding allows specifying pins, groups & functions now. That allows storing them in DT instead of hardcoding in drivers. Introduce helpers based on CONFIG_GENERIC_PINCONF, CONFIG_GENERIC_PINCTRL_GROUPS and CONFIG_GENERIC_PINMUX_FUNCTIONS for parsing that info into pinctrl generic structures. Signed-off-by: Rafał Miłecki --- drivers/pinctrl/core.c | 89 ++++++++++++++++++++++++++++++++++++++++ drivers/pinctrl/core.h | 5 +++ drivers/pinctrl/pinmux.c | 43 +++++++++++++++++++ drivers/pinctrl/pinmux.h | 2 + 4 files changed, 139 insertions(+) diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index ffe39336fcac..8f6ed8488313 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -515,8 +515,97 @@ void pinctrl_remove_gpio_range(struct pinctrl_dev *pctldev, } EXPORT_SYMBOL_GPL(pinctrl_remove_gpio_range); +int pinctrl_generic_get_dt_pins(struct pinctrl_desc *pctldesc, + struct device *dev) +{ + struct pinctrl_pin_desc *descs; + struct device_node *pins; + struct device_node *np; + int err = 0; + int i = 0; + + pins = of_get_child_by_name(dev->of_node, "pins"); + if (!pins) { + dev_err(dev, "failed to find \"pins\" DT node\n"); + err = -ENOENT; + goto err_out; + } + + pctldesc->npins = of_get_available_child_count(pins); + + descs = devm_kcalloc(dev, pctldesc->npins, sizeof(*descs), GFP_KERNEL); + if (!descs) { + err = -ENOMEM; + goto err_put_node; + } + + for_each_available_child_of_node(pins, np) { + if (of_property_read_u32(np, "reg", &descs[i].number)) { + dev_err(dev, "missing \"reg\" property in %pOF\n", np); + err = -ENOENT; + goto err_put_node; + } + + if (of_property_read_string(np, "label", &descs[i].name)) { + dev_err(dev, "missing \"label\" property in %pOF\n", np); + err = -ENOENT; + goto err_put_node; + } + + i++; + } + + pctldesc->pins = descs; + +err_put_node: + of_node_put(pins); +err_out: + return err; +} +EXPORT_SYMBOL_GPL(pinctrl_generic_get_dt_pins); + #ifdef CONFIG_GENERIC_PINCTRL_GROUPS +int pinctrl_generic_get_dt_groups(struct pinctrl_dev *pctldev) +{ + struct device *dev = pctldev->dev; + struct device_node *groups; + struct device_node *np; + int err = 0; + + groups = of_get_child_by_name(dev->of_node, "groups"); + if (!groups) { + dev_err(dev, "failed to find \"groups\" DT node\n"); + err = -ENOENT; + goto err_out; + } + + for_each_available_child_of_node(groups, np) { + int num_pins; + u32 *pins; + + num_pins = of_property_count_u32_elems(np, "pins"); + pins = devm_kmalloc_array(dev, num_pins, sizeof(*pins), GFP_KERNEL); + if (!pins) { + err = -ENOMEM; + goto err_put_node; + } + + if (of_property_read_u32_array(np, "pins", pins, num_pins)) { + err = -EIO; + goto err_put_node; + } + + pinctrl_generic_add_group(pctldev, np->name, pins, num_pins, np); + } + +err_put_node: + of_node_put(groups); +err_out: + return err; +} +EXPORT_SYMBOL_GPL(pinctrl_generic_get_dt_groups); + /** * pinctrl_generic_get_group_count() - returns the number of pin groups * @pctldev: pin controller device diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h index 840103c40c14..59661d4d4cc7 100644 --- a/drivers/pinctrl/core.h +++ b/drivers/pinctrl/core.h @@ -182,6 +182,9 @@ struct pinctrl_maps { unsigned num_maps; }; +int pinctrl_generic_get_dt_pins(struct pinctrl_desc *pctldesc, + struct device *dev); + #ifdef CONFIG_GENERIC_PINCTRL_GROUPS /** @@ -198,6 +201,8 @@ struct group_desc { void *data; }; +int pinctrl_generic_get_dt_groups(struct pinctrl_dev *pctldev); + int pinctrl_generic_get_group_count(struct pinctrl_dev *pctldev); const char *pinctrl_generic_get_group_name(struct pinctrl_dev *pctldev, diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 6cdbd9ccf2f0..5e34bd3135f5 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include "core.h" @@ -788,6 +789,48 @@ void pinmux_init_device_debugfs(struct dentry *devroot, #ifdef CONFIG_GENERIC_PINMUX_FUNCTIONS +int pinmux_generic_get_dt_functions(struct pinctrl_dev *pctldev) +{ + struct device *dev = pctldev->dev; + struct device_node *functions; + struct device_node *np; + int err = 0; + + functions = of_get_child_by_name(dev->of_node, "functions"); + if (!functions) { + dev_err(dev, "failed to find \"functions\" DT node\n"); + err = -ENOENT; + goto err_out; + } + + for_each_available_child_of_node(functions, np) { + int num_groups = of_count_phandle_with_args(np, "groups", NULL); + struct of_phandle_iterator it; + const char **groups; + int ret; + int i; + + groups = devm_kmalloc_array(dev, num_groups, sizeof(*groups), GFP_KERNEL); + if (!groups) { + err = -ENOMEM; + goto err_put_node; + } + + i = 0; + of_for_each_phandle(&it, ret, np, "groups", NULL, 0) { + groups[i++] = it.node->name; + } + + pinmux_generic_add_function(pctldev, np->name, groups, num_groups, np); + } + +err_put_node: + of_node_put(functions); +err_out: + return err; +} +EXPORT_SYMBOL_GPL(pinmux_generic_get_dt_functions); + /** * pinmux_generic_get_function_count() - returns number of functions * @pctldev: pin controller device diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h index 78c3a31be882..ca69025fce46 100644 --- a/drivers/pinctrl/pinmux.h +++ b/drivers/pinctrl/pinmux.h @@ -134,6 +134,8 @@ struct function_desc { void *data; }; +int pinmux_generic_get_dt_functions(struct pinctrl_dev *pctldev); + int pinmux_generic_get_function_count(struct pinctrl_dev *pctldev); const char * From patchwork Thu Nov 18 13:21:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= X-Patchwork-Id: 517143 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59260C433F5 for ; Thu, 18 Nov 2021 13:22:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3C28E61B29 for ; Thu, 18 Nov 2021 13:22:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229786AbhKRNZW (ORCPT ); Thu, 18 Nov 2021 08:25:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230411AbhKRNZT (ORCPT ); Thu, 18 Nov 2021 08:25:19 -0500 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2111FC061767; Thu, 18 Nov 2021 05:22:19 -0800 (PST) Received: by mail-lf1-x135.google.com with SMTP id c32so26014986lfv.4; Thu, 18 Nov 2021 05:22:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ULF68UwhVDlRTvRbeXuUFDMpZQ8miFxqyGy0nvwt3uk=; b=pGo1wzg0o2Q8EeSlsXb/UhoMwD2LzHiKdnm68v0zPZs3YW98qOdHxiEmBM40i+ORjP s1oDysRZIqf3oucuL7AI0b2/oz6ayhrSUZkmYhZpDQEybzfzHyosNhfKn7f57xZ/T/ri 2i8Fa+ZFz/zwxJQEkevTM46eNqVDUOgfzKYy0yX/09v3u8rP5nhLTUdGh3Yfs2tSZv7q wZVyHSMPKSyJ42OH5kga6Vk016etBoO9QIsr+g3nmfXWtIaCq4vmpRZp5CHQ/6frxBUM KTBGFHh6iPUJoINT7O+WqDGD6lCDL+APf/O1k6Rrn8Oq3k1/IUlTgdY47MeWzPb/TIJB iCYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ULF68UwhVDlRTvRbeXuUFDMpZQ8miFxqyGy0nvwt3uk=; b=XOy8Y7VdDTx4gvFmSakKkgLEWhDzI9XtFx0WDwPqsOTnumLjuiFb4dCOtlO6ig64V3 aKutEc17KvPmVKTE1YdDeqJsKXRSbngFuZBJuFphiCiEtXLMjM+b8KYbz4B5ltD/J++7 sX7hNGgrjuHVUWKCocgrMzy5v+AHu3ffsXAJq0awQui0I6/9Rf98cvs0BlbleAoJau9e QtVDl4f3YdNxYyo/RX2FuEV+qIkaS/A6sHcnmwqWenCyBH2GeLpA6gV7P+PZj/PhLHvL p74XTXxZT5shUJDm+hg+TaL0+4aVYUKzPDQBcsfOxduVyBN8aZAnYJeCrRx9jF6vTthj FIEw== X-Gm-Message-State: AOAM532VfkrK+YrGqNc8slIHberN1ZvFmUd2WeIJsHK09EAf78Y4MWKF iosidDTFzqlpILUEBhU1Ep4= X-Google-Smtp-Source: ABdhPJwHCfXME+dCe7HSwWboePM3jMjp/q/TB3ludt+Evadz5tV+XX3KLaFub0RTmqqDLK0TBApfPA== X-Received: by 2002:a2e:9641:: with SMTP id z1mr18419557ljh.66.1637241737452; Thu, 18 Nov 2021 05:22:17 -0800 (PST) Received: from localhost.lan (ip-194-187-74-233.konfederacka.maverick.com.pl. [194.187.74.233]) by smtp.gmail.com with ESMTPSA id bp36sm356550lfb.0.2021.11.18.05.22.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Nov 2021 05:22:17 -0800 (PST) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Linus Walleij , Rob Herring Cc: Tony Lindgren , Andy Shevchenko , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= Subject: [PATCH 5/5] ARM: dts: BCM5301X: add pinctrl pins, groups & functions Date: Thu, 18 Nov 2021 14:21:52 +0100 Message-Id: <20211118132152.15722-6-zajec5@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211118132152.15722-1-zajec5@gmail.com> References: <20211118132152.15722-1-zajec5@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Rafał Miłecki They can now be described in DT so do that. Signed-off-by: Rafał Miłecki --- arch/arm/boot/dts/bcm4709.dtsi | 74 +++++++++++++++++++ arch/arm/boot/dts/bcm47094.dtsi | 11 +-- arch/arm/boot/dts/bcm5301x.dtsi | 123 ++++++++++++++++++++++++++++++++ 3 files changed, 198 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/bcm4709.dtsi b/arch/arm/boot/dts/bcm4709.dtsi index cba3d910bed8..ba4700a85772 100644 --- a/arch/arm/boot/dts/bcm4709.dtsi +++ b/arch/arm/boot/dts/bcm4709.dtsi @@ -10,6 +10,80 @@ &uart0 { status = "okay"; }; +&pinctrl { + compatible = "brcm,bcm4709-pinmux"; + + pins { + reg@6 { + reg = <6>; + label = "mdc"; + }; + + reg@7 { + reg = <7>; + label = "mdio"; + }; + + reg@10 { + reg = <16>; + label = "uart2_rx"; + }; + + reg@11 { + reg = <17>; + label = "uart2_tx"; + }; + + /* TODO + * reg@ { + * label = "xtal_out"; + * }; + */ + + reg@16 { + reg = <22>; + label = "sdio_pwr"; + }; + + reg@17 { + reg = <23>; + label = "sdio_en_1p8v"; + }; + }; + + groups { + mdio_grp: mdio_grp { + pins = <6 7>; + }; + + uart2_grp: uart2_grp { + pins = <16 17>; + }; + + sdio_pwr_grp: sdio_pwr_grp { + pins = <22>; + }; + + sdio_1p8v_grp: sdio_1p8v_grp { + pins = <23>; + }; + }; + + functions { + mdio { + groups = <&mdio_grp>; + }; + + uart2 { + groups = <&uart2_grp>; + }; + + sdio { + groups = <&sdio_pwr_grp &sdio_1p8v_grp>; + }; + }; +}; + &srab { compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; }; diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi index 6282363313e1..239c1c1b0268 100644 --- a/arch/arm/boot/dts/bcm47094.dtsi +++ b/arch/arm/boot/dts/bcm47094.dtsi @@ -3,14 +3,12 @@ * Copyright (C) 2016 Rafał Miłecki */ -#include "bcm4708.dtsi" +#include "bcm4709.dtsi" / { }; &pinctrl { - compatible = "brcm,bcm4709-pinmux"; - pinmux_mdio: mdio-pins { groups = "mdio_grp"; function = "mdio"; @@ -21,11 +19,4 @@ &usb3_phy { compatible = "brcm,ns-bx-usb3-phy"; }; -&uart0 { - clock-frequency = <125000000>; - status = "okay"; -}; -&srab { - compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; -}; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index d4f355015e3c..31c6a3dbba30 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -473,6 +473,129 @@ pinmux_uart1: uart1-pins { groups = "uart1_grp"; function = "uart1"; }; + + pins { + #address-cells = <1>; + #size-cells = <0>; + + pin@0 { + reg = <0>; + label = "spi_clk"; + }; + + pin@1 { + reg = <1>; + label = "spi_ss"; + }; + + pin@2 { + reg = <2>; + label = "spi_mosi"; + }; + + pin@3 { + reg = <3>; + label = "spi_miso"; + }; + + pin@4 { + reg = <4>; + label = "i2c_scl"; + }; + + pin@5 { + reg = <5>; + label = "i2c_sda"; + }; + + pin@8 { + reg = <8>; + label = "pwm0"; + }; + + pin@9 { + reg = <9>; + label = "pwm1"; + }; + + pin@a { + reg = <10>; + label = "pwm2"; + }; + + pin@b { + reg = <11>; + label = "pwm3"; + }; + + pin@c { + reg = <12>; + label = "uart1_rx"; + }; + + pin@d { + reg = <13>; + label = "uart1_tx"; + }; + + pin@e { + reg = <14>; + label = "uart1_cts"; + }; + + pin@f { + reg = <15>; + label = "uart1_rts"; + }; + }; + + groups { + spi_grp: spi_grp { + pins = <0 1 2 3>; + }; + + i2c_grp: i2c_grp { + pins = <4 5>; + }; + + pwm0_grp: pwm0_grp { + pins = <8>; + }; + + pwm1_grp: pwm1_grp { + pins = <9>; + }; + + pwm2_grp: pwm2_grp { + pins = <10>; + }; + + pwm3_grp: pwm3_grp { + pins = <11>; + }; + + uart1_grp: uart1_grp { + pins = <12 13 14 15>; + }; + }; + + functions { + spi { + groups = <&spi_grp>; + }; + + i2c { + groups = <&i2c_grp>; + }; + + pwm { + groups = <&pwm0_grp &pwm1_grp &pwm2_grp &pwm3_grp>; + }; + + uart1 { + groups = <&uart1_grp>; + }; + }; }; thermal: thermal@2c0 {