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[209.132.180.67]) by mx.google.com with ESMTP id f8si30219256pln.39.2017.05.26.00.39.00; Fri, 26 May 2017 00:39:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1035380AbdEZHin (ORCPT + 25 others); Fri, 26 May 2017 03:38:43 -0400 Received: from mail-pf0-f182.google.com ([209.85.192.182]:33346 "EHLO mail-pf0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1035346AbdEZHif (ORCPT ); Fri, 26 May 2017 03:38:35 -0400 Received: by mail-pf0-f182.google.com with SMTP id e193so4189336pfh.0 for ; Fri, 26 May 2017 00:38:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eF1NCHRdgYeSwUw/BUsdYReuItV1TCgRBZS89MNcBOk=; b=gu9iI7YU5CrMF4dgiWeaDtHgsXgzr070I6r24/w/hqLQagZom0UMvmSTMUL7ZFHX7U 00ypER0KYZIdYareGF5qyf7KL2B3JqOZxY2M22jtUe3lIyvHKLk/D3GMVnYwXswctOLs 81aIlk3qqOKltBc3pZuHQgyxXBOlj1FpphPJQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eF1NCHRdgYeSwUw/BUsdYReuItV1TCgRBZS89MNcBOk=; b=GhePxemG4/SQk49C9CvJcGfu8knOjo4SMqIoZTde3VpzNJ35Pxs7Ye1CmYgcgoUwIC LJU854d5TP+NJfPf6/xhe/8lYWQOOqDXuhAMHE9E99PQpAcQS4rjNz0HNpgf5N4oQLRa hl9OnP7rPTLG0dRsLzmhcznbEodC0mT0ve/g+iKZ4vijHlL2Glk71Po4krOx9g8xCiXt UvJ2SFtN9FlrJg5m3tBbDNvgyd6Lb/Pb4ye3b8EjCR//FkfqCF8G4pCgVVDHBDB9vm+E lErINcTPNaKyHGJp990ZRuK5x/h/2Tms1PvaffdGiTWmRkr4q19XkL/BDbjdxvYpkFcS pepg== X-Gm-Message-State: AODbwcDkqEog4JbsFlkk8qKMeBKbcUO6TNk2zVTSqtKBdghb1C3GOyqf kuW0GYHoelLJtFUn X-Received: by 10.98.0.8 with SMTP id 8mr709135pfa.127.1495784314904; Fri, 26 May 2017 00:38:34 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.222]) by smtp.gmail.com with ESMTPSA id t3sm19106334pfl.60.2017.05.26.00.38.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 May 2017 00:38:34 -0700 (PDT) From: Guodong Xu To: mturquette@baylibre.com, sboyd@codeaurora.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: chenjun14@huawei.com, zhongkaihua@huawei.com, zhangfei.gao@linaro.org, leo.yan@linaro.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, John Stultz , Guodong Xu Subject: [PATCH v2 1/3] clk: hi3660: fix wrong parent name of clk_mux_sysbus Date: Fri, 26 May 2017 15:38:19 +0800 Message-Id: <20170526073821.25971-2-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170526073821.25971-1-guodong.xu@linaro.org> References: <20170526073821.25971-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chen Jun Parent name of clk_mux_sysbus is not correct. This patch fixes it. Signed-off-by: Chen Jun Signed-off-by: John Stultz Signed-off-by: Guodong Xu --- drivers/clk/hisilicon/clk-hi3660.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.10.2 diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index 96a9697..143ce0c 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -206,6 +206,8 @@ static const struct hisi_gate_clock hi3660_crgctrl_gate_clks[] = { }; static const char *const +clk_mux_sysbus_p[] = {"clk_ppll1", "clk_ppll0"}; +static const char *const clk_mux_sdio_sys_p[] = {"clk_factor_mmc", "clk_div_sdio",}; static const char *const clk_mux_sd_sys_p[] = {"clk_factor_mmc", "clk_div_sd",}; @@ -239,8 +241,8 @@ static const char *const clk_mux_i2c_p[] = {"clkin_sys", "clk_div_i2c",}; static const struct hisi_mux_clock hi3660_crgctrl_mux_clks[] = { - { HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sdio_sys_p, - ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT, 0xac, 0, 1, + { HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sysbus_p, + ARRAY_SIZE(clk_mux_sysbus_p), CLK_SET_RATE_PARENT, 0xac, 0, 1, CLK_MUX_HIWORD_MASK, }, { HI3660_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p, ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT, 0xac, 2, 1, From patchwork Fri May 26 07:38:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 100558 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp130276qge; Fri, 26 May 2017 00:38:49 -0700 (PDT) X-Received: by 10.84.130.99 with SMTP id 90mr30447222plc.165.1495784329713; Fri, 26 May 2017 00:38:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495784329; cv=none; d=google.com; s=arc-20160816; b=N1hz1LlfEnVUBILUvoKUWWJuvfxlbYskhr1Q5O/KxXDrPh0NG5y5yAyHLC5zy1wNCg gdOONJXF8GTkEeP7C8S4J5XKnT+7aS56r4HuKy6MUCdUnEo1aUWIRZrI+6uHWcUKF7sJ YFHeYSJPqT0rPmDqnvOxV/PKxTTrmnxLywQ86SWfjkW8Fglw3NJtEUIztMYDs1Nkwy+e gx0Y9XHMTngJ3hzZgubaAuIyM8caN8/53ehicRKC0Tv2qOSDc4WW/cgpwyXDxLtMns8f LJN4QxsfqelCp+1C/6WI8Mn3mHgJ9VqpzouLczOfsUuyQ9cM4sSkZcpqBMQA2n09+2P6 22BQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=SADOZ5JB7jBAZGwKL2FFhZ8uPpq+sVRmPXvRRi7UQtc=; b=Gws4mzpUe/uRLgvRg59xDF6t3slx5Ide/mXU394R/IHVKoA2gc6w852Sb5LaPX9hwi +czqW07/A+eeUTUhJ7DDWajUqc/je9ArpvLsJ9x+8ovOzVKRtEsXUEwxZ5Rx85o4JbHJ OYJs2UVAqhRGD2e74HsO9yWQRxxaqsVC+ByxjfSBCqnhAY2MbiKMww8sIxKg8NPQ96V0 /DfuCJkedpc3oJE28cc0QnDI4tNAXdYw4wZwOJs8k+Q+k9V4HYuMEwUu1DWD6kCfaWRq e/XMD0weJEPz9Z6QQQ61YvOs3LXJWz6FzKUXoMO8GsXDCm5XVxsEFoC5eYoTaRWGfYjm JPXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Fri, 26 May 2017 00:38:39 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.222]) by smtp.gmail.com with ESMTPSA id t3sm19106334pfl.60.2017.05.26.00.38.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 May 2017 00:38:39 -0700 (PDT) From: Guodong Xu To: mturquette@baylibre.com, sboyd@codeaurora.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: chenjun14@huawei.com, zhongkaihua@huawei.com, zhangfei.gao@linaro.org, leo.yan@linaro.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Guodong Xu Subject: [PATCH v2 2/3] clk: hi3660: add clocks for video encoder, decoder and ISP Date: Fri, 26 May 2017 15:38:20 +0800 Message-Id: <20170526073821.25971-3-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170526073821.25971-1-guodong.xu@linaro.org> References: <20170526073821.25971-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chen Jun This patch adds more clocks for hi3660, including: - video encoder and decoder - ISP (Image Signal Processing) Signed-off-by: Chen Jun Signed-off-by: Zhong Kaihua Signed-off-by: Guodong Xu Reviewed-by: Zhangfei Gao --- drivers/clk/hisilicon/clk-hi3660.c | 40 ++++++++++++++++++++++++++++++++ include/dt-bindings/clock/hi3660-clock.h | 17 ++++++++++++++ 2 files changed, 57 insertions(+) -- 2.10.2 diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index 143ce0c..67c4d44 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -47,9 +47,14 @@ static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = { { HI3660_CLK_GATE_SPI2, "clk_gate_spi2", "clk_ppll0", 1, 8, 0, }, { HI3660_PCIEPHY_REF, "clk_pciephy_ref", "clk_div_pciephy", 1, 1, 0, }, { HI3660_CLK_ABB_USB, "clk_abb_usb", "clk_gate_usb_tcxo_en", 1, 1, 0 }, + { HI3660_VENC_VOLT_HOLD, "venc_volt_hold", "peri_volt_hold", 1, 1, 0, }, + { HI3660_CLK_FAC_ISP_SNCLK, "clk_isp_snclk_fac", "clk_isp_snclk_angt", + 1, 10, 0, }, }; static const struct hisi_gate_clock hi3660_crgctrl_gate_sep_clks[] = { + { HI3660_PERI_VOLT_HOLD, "peri_volt_hold", "clkin_sys", + CLK_SET_RATE_PARENT, 0x0, 0, 0, }, { HI3660_HCLK_GATE_SDIO0, "hclk_gate_sdio0", "clk_div_sysbus", CLK_SET_RATE_PARENT, 0x0, 21, 0, }, { HI3660_HCLK_GATE_SD, "hclk_gate_sd", "clk_div_sysbus", @@ -120,6 +125,10 @@ static const struct hisi_gate_clock hi3660_crgctrl_gate_sep_clks[] = { CLK_SET_RATE_PARENT, 0x20, 27, 0, }, { HI3660_CLK_GATE_DMAC, "clk_gate_dmac", "clk_div_sysbus", CLK_SET_RATE_PARENT, 0x30, 1, 0, }, + { HI3660_CLK_GATE_VENC, "clk_gate_venc", "clk_div_venc", + CLK_SET_RATE_PARENT, 0x30, 10, 0, }, + { HI3660_CLK_GATE_VDEC, "clk_gate_vdec", "clk_div_vdec", + CLK_SET_RATE_PARENT, 0x30, 11, 0, }, { HI3660_PCLK_GATE_DSS, "pclk_gate_dss", "clk_div_cfgbus", CLK_SET_RATE_PARENT, 0x30, 12, 0, }, { HI3660_ACLK_GATE_DSS, "aclk_gate_dss", "clk_gate_vivobus", @@ -148,6 +157,12 @@ static const struct hisi_gate_clock hi3660_crgctrl_gate_sep_clks[] = { CLK_SET_RATE_PARENT, 0x40, 17, 0, }, { HI3660_CLK_GATE_SDIO0, "clk_gate_sdio0", "clk_mux_sdio_sys", CLK_SET_RATE_PARENT, 0x40, 19, 0, }, + { HI3660_CLK_GATE_ISP_SNCLK0, "clk_gate_isp_snclk0", + "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 16, 0, }, + { HI3660_CLK_GATE_ISP_SNCLK1, "clk_gate_isp_snclk1", + "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 17, 0, }, + { HI3660_CLK_GATE_ISP_SNCLK2, "clk_gate_isp_snclk2", + "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 18, 0, }, { HI3660_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_sysbus", CLK_SET_RATE_PARENT, 0x50, 21, 0, }, { HI3660_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus", @@ -171,6 +186,10 @@ static const struct hisi_gate_clock hi3660_crgctrl_gate_clks[] = { CLK_SET_RATE_PARENT, 0xf0, 7, CLK_GATE_HIWORD_MASK, }, { HI3660_CLK_ANDGT_EDC0, "clk_andgt_edc0", "clk_mux_edc0", CLK_SET_RATE_PARENT, 0xf0, 8, CLK_GATE_HIWORD_MASK, }, + { HI3660_CLK_ANDGT_VDEC, "clk_andgt_vdec", "clk_mux_vdec", + CLK_SET_RATE_PARENT, 0xf0, 15, CLK_GATE_HIWORD_MASK, }, + { HI3660_CLK_ANDGT_VENC, "clk_andgt_venc", "clk_mux_venc", + CLK_SET_RATE_PARENT, 0xf4, 0, CLK_GATE_HIWORD_MASK, }, { HI3660_CLK_GATE_UFSPHY_GT, "clk_gate_ufsphy_gt", "clk_div_ufsperi", CLK_SET_RATE_PARENT, 0xf4, 1, CLK_GATE_HIWORD_MASK, }, { HI3660_CLK_ANDGT_MMC, "clk_andgt_mmc", "clk_mux_mmc_pll", @@ -195,6 +214,8 @@ static const struct hisi_gate_clock hi3660_crgctrl_gate_clks[] = { CLK_SET_RATE_PARENT, 0xf8, 3, CLK_GATE_HIWORD_MASK, }, { HI3660_CLK_320M_PLL_GT, "clk_320m_pll_gt", "clk_mux_320m", CLK_SET_RATE_PARENT, 0xf8, 10, 0, }, + { HI3660_CLK_ANGT_ISP_SNCLK, "clk_isp_snclk_angt", "clk_div_a53hpm", + CLK_SET_RATE_PARENT, 0x108, 2, CLK_GATE_HIWORD_MASK, }, { HI3660_AUTODIV_EMMC0BUS, "autodiv_emmc0bus", "autodiv_sysbus", CLK_SET_RATE_PARENT, 0x404, 1, CLK_GATE_HIWORD_MASK, }, { HI3660_AUTODIV_SYSBUS, "autodiv_sysbus", "clk_div_sysbus", @@ -239,6 +260,10 @@ static const char *const clk_mux_spi_p[] = {"clkin_sys", "clk_div_spi",}; static const char *const clk_mux_i2c_p[] = {"clkin_sys", "clk_div_i2c",}; +static const char *const +clk_mux_venc_p[] = {"clk_ppll0", "clk_ppll1", "clk_ppll3", "clk_ppll3",}; +static const char *const +clk_mux_isp_snclk_p[] = {"clkin_sys", "clk_isp_snclk_div"}; static const struct hisi_mux_clock hi3660_crgctrl_mux_clks[] = { { HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sysbus_p, @@ -283,6 +308,12 @@ static const struct hisi_mux_clock hi3660_crgctrl_mux_clks[] = { { HI3660_CLK_MUX_SDIO_PLL, "clk_mux_sdio_pll", clk_mux_pll_p, ARRAY_SIZE(clk_mux_pll_p), CLK_SET_RATE_PARENT, 0xc0, 4, 2, CLK_MUX_HIWORD_MASK, }, + { HI3660_CLK_MUX_VENC, "clk_mux_venc", clk_mux_venc_p, + ARRAY_SIZE(clk_mux_venc_p), CLK_SET_RATE_PARENT, 0xc8, 11, 2, + CLK_MUX_HIWORD_MASK, }, + { HI3660_CLK_MUX_VDEC, "clk_mux_vdec", clk_mux_pll0123_p, + ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xcc, 5, 2, + CLK_MUX_HIWORD_MASK, }, { HI3660_CLK_MUX_VIVOBUS, "clk_mux_vivobus", clk_mux_pll0123_p, ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xd0, 12, 2, CLK_MUX_HIWORD_MASK, }, @@ -292,6 +323,9 @@ static const struct hisi_mux_clock hi3660_crgctrl_mux_clks[] = { { HI3660_CLK_MUX_320M, "clk_mux_320m", clk_mux_pll02p, ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0x100, 0, 1, CLK_MUX_HIWORD_MASK, }, + { HI3660_CLK_MUX_ISP_SNCLK, "clk_isp_snclk_mux", clk_mux_isp_snclk_p, + ARRAY_SIZE(clk_mux_isp_snclk_p), CLK_SET_RATE_PARENT, 0x108, 3, 1, + CLK_MUX_HIWORD_MASK, }, { HI3660_CLK_MUX_IOPERI, "clk_mux_ioperi", clk_mux_ioperi_p, ARRAY_SIZE(clk_mux_ioperi_p), CLK_SET_RATE_PARENT, 0x108, 10, 1, CLK_MUX_HIWORD_MASK, }, @@ -318,6 +352,10 @@ static const struct hisi_divider_clock hi3660_crgctrl_divider_clks[] = { CLK_SET_RATE_PARENT, 0xc0, 8, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, { HI3660_CLK_DIV_SPI, "clk_div_spi", "clk_andgt_spi", CLK_SET_RATE_PARENT, 0xc4, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3660_CLK_DIV_VENC, "clk_div_venc", "clk_andgt_venc", + CLK_SET_RATE_PARENT, 0xc8, 6, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3660_CLK_DIV_VDEC, "clk_div_vdec", "clk_andgt_vdec", + CLK_SET_RATE_PARENT, 0xcc, 0, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, { HI3660_CLK_DIV_VIVOBUS, "clk_div_vivobus", "clk_vivobus_andgt", CLK_SET_RATE_PARENT, 0xd0, 7, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, { HI3660_CLK_DIV_I2C, "clk_div_i2c", "clk_div_320m", @@ -334,6 +372,8 @@ static const struct hisi_divider_clock hi3660_crgctrl_divider_clks[] = { CLK_SET_RATE_PARENT, 0xec, 14, 1, CLK_DIVIDER_HIWORD_MASK, 0, }, { HI3660_CLK_DIV_AOMM, "clk_div_aomm", "clk_aomm_andgt", CLK_SET_RATE_PARENT, 0x100, 7, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3660_CLK_DIV_ISP_SNCLK, "clk_isp_snclk_div", "clk_isp_snclk_fac", + CLK_SET_RATE_PARENT, 0x108, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, }, { HI3660_CLK_DIV_IOPERI, "clk_div_ioperi", "clk_mux_ioperi", CLK_SET_RATE_PARENT, 0x108, 11, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, }; diff --git a/include/dt-bindings/clock/hi3660-clock.h b/include/dt-bindings/clock/hi3660-clock.h index 1c00b7f..adb768d 100644 --- a/include/dt-bindings/clock/hi3660-clock.h +++ b/include/dt-bindings/clock/hi3660-clock.h @@ -154,6 +154,23 @@ #define HI3660_CLK_DIV_UFSPERI 137 #define HI3660_CLK_DIV_AOMM 138 #define HI3660_CLK_DIV_IOPERI 139 +#define HI3660_VENC_VOLT_HOLD 140 +#define HI3660_PERI_VOLT_HOLD 141 +#define HI3660_CLK_GATE_VENC 142 +#define HI3660_CLK_GATE_VDEC 143 +#define HI3660_CLK_ANDGT_VENC 144 +#define HI3660_CLK_ANDGT_VDEC 145 +#define HI3660_CLK_MUX_VENC 146 +#define HI3660_CLK_MUX_VDEC 147 +#define HI3660_CLK_DIV_VENC 148 +#define HI3660_CLK_DIV_VDEC 149 +#define HI3660_CLK_FAC_ISP_SNCLK 150 +#define HI3660_CLK_GATE_ISP_SNCLK0 151 +#define HI3660_CLK_GATE_ISP_SNCLK1 152 +#define HI3660_CLK_GATE_ISP_SNCLK2 153 +#define HI3660_CLK_ANGT_ISP_SNCLK 154 +#define HI3660_CLK_MUX_ISP_SNCLK 155 +#define HI3660_CLK_DIV_ISP_SNCLK 156 /* clk in pmuctrl */ #define HI3660_GATE_ABB_192 0