From patchwork Wed Nov 3 15:09:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilias Apalodimas X-Patchwork-Id: 516765 Delivered-To: patch@linaro.org Received: by 2002:adf:eccd:0:0:0:0:0 with SMTP id s13csp712554wro; Wed, 3 Nov 2021 08:10:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzi/uuqoD7vySIEhU1IQW8/fUURngagjpMjpj132Eil9bT3vg4kzw8TpucdSyGda+CjsO2w X-Received: by 2002:a17:906:cd03:: with SMTP id oz3mr2230161ejb.252.1635952207817; Wed, 03 Nov 2021 08:10:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635952207; cv=none; d=google.com; s=arc-20160816; b=sRn4viSzp02V8yYIVtQNQZ1+RY7lz1NlOQbJ4Way54qm4B2H0XgqcGBRdZOuiRFDN/ UL7XLp3fi2sNDtcYSX/iAEGzyEnISDIH0OkPtA6ccQfpL0F1+hCkGdb0cN001bcMRELP HL6C8wKYgks7TeK9nGXVMC5awHngLMY3KTTS4VzZNj1hsvt+h7/WOAx0sENZYzWFNnLX iGkmy34XrmfM4kB+HksaWmC4CPNvCQ98EOSVEMDL0S5tQ0uM8AAqIjTYTG/fdcNs4OfN 6rxLtf/TJZxmrRq8xud3mZz+2autatiqrWgQJc1knrz7+VjjmOvyYJhKcU+sRDNM6Ffv NVKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5OO6zwv0y/q6z0Y9YCXc0EPdyo0FfjXb8oNVYz562Ak=; b=U1y9lANpwNmwjgKxoIrZlFodUbeRYopRtmNq8H34Ct+QowecDtSWn0ShSF6DAmxKoc WRIQIcgpFjYzGxfZ8p0AKSR1bp1brjgA8IojTfFB1flGvDFYDrGJ4kIs++c8TTFyQwf4 mVSTjuIHCilFBRt3BMspVpgchYWNi0TXVyoXe4GcE/px5fVe4+Vh8+cK1cnbmmA2huMc VgL21PFNtIQAd8VWH0OU1dATt/vUn+BzyUfDydKhILq3Ty9p9BIBTJvFSCIOaYI7HMYT pokl4bG7Aiioy2VHk2hYV9nq750sLuF7C/IVLFi+kxk6KQT955Xvz2yXqMACebw0Kpue 8nXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tvxDB1uz; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id sb15si4294989ejc.427.2021.11.03.08.09.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 08:10:07 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tvxDB1uz; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 49ED083116; Wed, 3 Nov 2021 16:09:42 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="tvxDB1uz"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1F4EB8362F; Wed, 3 Nov 2021 16:09:39 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C7B0D8342C for ; Wed, 3 Nov 2021 16:09:33 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ilias.apalodimas@linaro.org Received: by mail-wm1-x330.google.com with SMTP id o4-20020a1c7504000000b0032cab7473caso3584818wmc.1 for ; Wed, 03 Nov 2021 08:09:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5OO6zwv0y/q6z0Y9YCXc0EPdyo0FfjXb8oNVYz562Ak=; b=tvxDB1uzJgSl+jMuFYibSkFjVQPr6AZkj9j+xhTZO5rr6/s4tTerKg3fI8x/3IH8H3 bvO7MDF8nYkqFn6teAwx5ySXiQcjiSgojNCWMADhtFeyXdCTrsYjamisqtXOS+ajYPAA QL3qVi0uGPUAIqCZANFeIspebDBYgj7rNKHVGDYmEbWougX2u1R+Lkrbypn5xOHrKgSj /MADNX5Z9LjNpLaEOlHcv4FG/hrKvbTu5STt7DouAuAtQJSOH5eHrWf9jUpEE5E0BK3U taK9STNN88A6whWDENspVd2kB2YqQBlB/GeNzgVuG4cch5/Ew1Wg/KmYo4B0uLkQcoEj FylQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5OO6zwv0y/q6z0Y9YCXc0EPdyo0FfjXb8oNVYz562Ak=; b=oeRTrxhpAO60FtC4vJDS/Q+IhecAI3norP6emvY00o4Pep0/OSjiHj4Uy/SinNGTch OuuPpcl55jm7/yZdZsRNgFT/KfDwbeJD+JY7WTuJhS2SDwbaeH7u/e7NF1QfvJqsOFJl jUXxzbB9GDLL66X0++Mm6wDnMKrbpH8oEsLswDsIdBQ572KjVuiMmW6RXZlgY3ymoS+u qL4khh4PO9fIOs+/a82j3qIYX+pJclYxDW7HHNbn9LwoFYGS/At2vzar4oy+uWxp0XDK Xvmk50d+Iz7Otby/K855Zw2g1SMgqeRfZnalSsd/BNlf+hRPeK9axv1kyupiUTYjvJGK vpWQ== X-Gm-Message-State: AOAM5338bMP/HfJivhVAJ30SGYj0VqSQSHO19+eomp5oE+6jjThPclqm tH+9eSQPwiq0ZDKy9ANCPqicA/p/6EQr3g== X-Received: by 2002:a05:600c:358e:: with SMTP id p14mr4350354wmq.76.1635952173260; Wed, 03 Nov 2021 08:09:33 -0700 (PDT) Received: from apalos.home ([2a02:587:4682:26e0:2e56:dcff:fe9a:8f06]) by smtp.gmail.com with ESMTPSA id f19sm2094947wmq.34.2021.11.03.08.09.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 08:09:32 -0700 (PDT) From: Ilias Apalodimas To: u-boot@lists.denx.de Cc: trini@konsulko.com, Ilias Apalodimas , Rick Chen , Sean Anderson , Simon Glass , Heinrich Schuchardt , Masahisa Kojima Subject: [PATCH 1/6 v4] tpm2: Introduce TIS tpm core Date: Wed, 3 Nov 2021 17:09:04 +0200 Message-Id: <20211103150910.69732-2-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211103150910.69732-1-ilias.apalodimas@linaro.org> References: <20211103150910.69732-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean There's a lot of code duplication in U-Boot right now. All the TPM TIS compatible drivers we have at the moment have their own copy of a TIS implementation. So let's create a common layer which implements the core TIS functions. Any driver added from now own, which is compatible with the TIS spec, will only have to provide the underlying bus communication mechanisms. Signed-off-by: Ilias Apalodimas --- drivers/tpm/tpm2_tis_core.c | 523 ++++++++++++++++++++++++++++++++++++ drivers/tpm/tpm_tis.h | 39 +++ include/tpm-v2.h | 1 + 3 files changed, 563 insertions(+) create mode 100644 drivers/tpm/tpm2_tis_core.c -- 2.33.1 diff --git a/drivers/tpm/tpm2_tis_core.c b/drivers/tpm/tpm2_tis_core.c new file mode 100644 index 000000000000..7d7050151622 --- /dev/null +++ b/drivers/tpm/tpm2_tis_core.c @@ -0,0 +1,523 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020, Linaro Limited + * + * Based on the Linux TIS core interface and U-Boot original SPI TPM driver + */ + +#include +#include +#include +#include +#include +#include "tpm_tis.h" + +/** + * tpm_tis_get_desc - Get the TPM description + * + * @udev: udevice + * @buf: buffer to fill data + * @size: buffer size + * + * @Return: Number of characters written (or would have been written) in buffer + */ +int tpm_tis_get_desc(struct udevice *udev, char *buf, int size) +{ + struct tpm_chip *chip = dev_get_priv(udev); + + if (size < 80) + return -ENOSPC; + + return snprintf(buf, size, + "%s v2.0: VendorID 0x%04x, DeviceID 0x%04x, RevisionID 0x%02x [%s]", + udev->name, chip->vend_dev & 0xFFFF, + chip->vend_dev >> 16, chip->rid, + (chip->is_open ? "open" : "closed")); +} + +/** + * tpm_tis_check_locality - Check the current TPM locality + * + * @udev: udevice + * @loc: locality + * + * Return: True if the tested locality matches + */ +static bool tpm_tis_check_locality(struct udevice *udev, int loc) +{ + struct tpm_chip *chip = dev_get_priv(udev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + u8 locality; + + phy_ops->read_bytes(udev, TPM_ACCESS(loc), 1, &locality); + if ((locality & (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID | + TPM_ACCESS_REQUEST_USE)) == + (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) { + chip->locality = loc; + return true; + } + + return false; +} + +/** + * tpm_tis_request_locality - Request a locality from the TPM + * + * @udev: udev + * @loc: requested locality + * + * Return: 0 on success -1 on failure + */ +int tpm_tis_request_locality(struct udevice *udev, int loc) +{ + struct tpm_chip *chip = dev_get_priv(udev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + u8 buf = TPM_ACCESS_REQUEST_USE; + unsigned long start, stop; + + if (tpm_tis_check_locality(udev, loc)) + return 0; + + phy_ops->write_bytes(udev, TPM_ACCESS(loc), 1, &buf); + start = get_timer(0); + stop = chip->timeout_a; + do { + if (tpm_tis_check_locality(udev, loc)) + return 0; + mdelay(TPM_TIMEOUT_MS); + } while (get_timer(start) < stop); + + return -1; +} + +/** + * tpm_tis_status - Check the current device status + * + * @udev: udevice + * @status: return value of status + * + * Return: 0 on success, negative on failure + */ +static int tpm_tis_status(struct udevice *udev, u8 *status) +{ + struct tpm_chip *chip = dev_get_priv(udev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + + if (chip->locality < 0) + return -EINVAL; + + phy_ops->read_bytes(udev, TPM_STS(chip->locality), 1, status); + + if ((*status & TPM_STS_READ_ZERO)) { + log_err("TPM returned invalid status\n"); + return -EINVAL; + } + + return 0; +} + +/** + * tpm_tis_release_locality - Release the requested locality + * + * @udev: udevice + * @loc: requested locality + * + * Return: 0 on success, negative on failure + */ +int tpm_tis_release_locality(struct udevice *udev, int loc) +{ + struct tpm_chip *chip = dev_get_priv(udev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + u8 buf = TPM_ACCESS_ACTIVE_LOCALITY; + int ret; + + if (chip->locality < 0) + return 0; + + ret = phy_ops->write_bytes(udev, TPM_ACCESS(loc), 1, &buf); + chip->locality = -1; + + return ret; +} + +/** + * tpm_tis_wait_for_stat - Wait for TPM to become ready + * + * @udev: udev + * @mask: mask to match + * @timeout: timeout for retries + * @status: current status + * + * Return: 0 on success, negative on failure + */ +static int tpm_tis_wait_for_stat(struct udevice *udev, u8 mask, + unsigned long timeout, u8 *status) +{ + unsigned long start = get_timer(0); + unsigned long stop = timeout; + int ret; + + do { + mdelay(TPM_TIMEOUT_MS); + ret = tpm_tis_status(udev, status); + if (ret) + return ret; + + if ((*status & mask) == mask) + return 0; + } while (get_timer(start) < stop); + + return -ETIMEDOUT; +} + +/** + * tpm_tis_get_burstcount - Get the burstcount for the data FIFO + * + * @udev: udevice + * @burstcount: current burstcount + * + * Return: 0 on success, negative on failure + */ +static int tpm_tis_get_burstcount(struct udevice *udev, size_t *burstcount) +{ + struct tpm_chip *chip = dev_get_priv(udev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + unsigned long start, stop; + u32 burst; + + if (chip->locality < 0) + return -EINVAL; + + /* wait for burstcount */ + start = get_timer(0); + /* + * This is the TPMv2 defined timeout. Change this in case you want to + * make the driver compatile to TPMv1 + */ + stop = chip->timeout_a; + do { + phy_ops->read32(udev, TPM_STS(chip->locality), &burst); + *burstcount = (burst >> 8) & 0xFFFF; + if (*burstcount) + return 0; + + mdelay(TPM_TIMEOUT_MS); + } while (get_timer(start) < stop); + + return -ETIMEDOUT; +} + +/** + * tpm_tis_ready - Cancel pending comands and get the device on a ready state + * + * @udev: udevcie + * + * Return: 0 on success, negative on failure + */ +static int tpm_tis_ready(struct udevice *udev) +{ + struct tpm_chip *chip = dev_get_priv(udev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + u8 data = TPM_STS_COMMAND_READY; + + /* This will cancel any pending commands */ + return phy_ops->write_bytes(udev, TPM_STS(chip->locality), 1, &data); +} + +/** + * tpm_tis_send - send data to the device + * + * @udev: udevice + * @buf: buffer to send + * @len: size of the buffer + * + * Return: number of bytes sent or negative on failure + */ +int tpm_tis_send(struct udevice *udev, const u8 *buf, size_t len) +{ + struct tpm_chip *chip = dev_get_priv(udev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + size_t burstcnt, wr_size, sent = 0; + u8 data = TPM_STS_GO; + u8 status; + int ret; + + if (!chip) + return -ENODEV; + + ret = tpm_tis_request_locality(udev, 0); + if (ret < 0) + return -EBUSY; + + ret = tpm_tis_status(udev, &status); + if (ret) + goto release_locality; + + if (!(status & TPM_STS_COMMAND_READY)) { + ret = tpm_tis_ready(udev); + if (ret) { + log_err("Can't cancel previous TPM operation\n"); + goto release_locality; + } + ret = tpm_tis_wait_for_stat(udev, TPM_STS_COMMAND_READY, + chip->timeout_b, &status); + if (ret) { + log_err("TPM not ready\n"); + goto release_locality; + } + } + + while (len > 0) { + ret = tpm_tis_get_burstcount(udev, &burstcnt); + if (ret) + goto release_locality; + + wr_size = min(len, burstcnt); + ret = phy_ops->write_bytes(udev, TPM_DATA_FIFO(chip->locality), + wr_size, buf + sent); + if (ret < 0) + goto release_locality; + + ret = tpm_tis_wait_for_stat(udev, TPM_STS_VALID, + chip->timeout_c, &status); + if (ret) + goto release_locality; + + sent += wr_size; + len -= wr_size; + /* make sure the TPM expects more data */ + if (len && !(status & TPM_STS_DATA_EXPECT)) { + ret = -EIO; + goto release_locality; + } + } + + /* + * Make a final check ensuring everything is ok and the TPM expects no + * more data + */ + ret = tpm_tis_wait_for_stat(udev, TPM_STS_VALID, chip->timeout_c, + &status); + if (ret) + goto release_locality; + + if (status & TPM_STS_DATA_EXPECT) { + ret = -EIO; + goto release_locality; + } + + ret = phy_ops->write_bytes(udev, TPM_STS(chip->locality), 1, &data); + if (ret) + goto release_locality; + + return sent; + +release_locality: + tpm_tis_ready(udev); + tpm_tis_release_locality(udev, chip->locality); + + return ret; +} + +/** + * tpm_tis_recv_data - Receive data from a device. Wrapper for tpm_tis_recv + * + * @udev: udevice + * @buf: buffer to copy data + * @size: buffer size + * + * Return: bytes read or negative on failure + */ +static int tpm_tis_recv_data(struct udevice *udev, u8 *buf, size_t count) +{ + struct tpm_chip *chip = dev_get_priv(udev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + int size = 0, len, ret; + size_t burstcnt; + u8 status; + + while (size < count && + tpm_tis_wait_for_stat(udev, TPM_STS_DATA_AVAIL | TPM_STS_VALID, + chip->timeout_c, &status) == 0) { + ret = tpm_tis_get_burstcount(udev, &burstcnt); + if (ret) + return ret; + + len = min_t(int, burstcnt, count - size); + ret = phy_ops->read_bytes(udev, TPM_DATA_FIFO(chip->locality), + len, buf + size); + if (ret < 0) + return ret; + + size += len; + } + + return size; +} + +/** + * tpm_tis_recv - Receive data from a device + * + * @udev: udevice + * @buf: buffer to copy data + * @size: buffer size + * + * Return: bytes read or negative on failure + */ +int tpm_tis_recv(struct udevice *udev, u8 *buf, size_t count) +{ + struct tpm_chip *chip = dev_get_priv(udev); + int size, expected; + + if (count < TPM_HEADER_SIZE) + return -E2BIG; + + size = tpm_tis_recv_data(udev, buf, TPM_HEADER_SIZE); + if (size < TPM_HEADER_SIZE) { + log_err("TPM error, unable to read header\n"); + goto out; + } + + expected = get_unaligned_be32(buf + TPM_CMD_COUNT_OFFSET); + if (expected > count) { + size = -EIO; + log_warning("Too much data: %d > %zu\n", expected, count); + goto out; + } + + size += tpm_tis_recv_data(udev, &buf[TPM_HEADER_SIZE], + expected - TPM_HEADER_SIZE); + if (size < expected) { + log(LOGC_NONE, LOGL_ERR, + "TPM error, unable to read remaining bytes of result\n"); + size = -EIO; + goto out; + } + +out: + tpm_tis_ready(udev); + /* acquired in tpm_tis_send */ + tpm_tis_release_locality(udev, chip->locality); + + return size; +} + +/** tpm_tis_cleanup - Get the device in ready state and release locality + * + * @udev: udevice + * + * Return: always 0 + */ +int tpm_tis_cleanup(struct udevice *udev) +{ + struct tpm_chip *chip = dev_get_priv(udev); + + tpm_tis_ready(udev); + tpm_tis_release_locality(udev, chip->locality); + + return 0; +} + +/** + * tpm_tis_open - Open the device and request locality 0 + * + * @udev: udevice + * + * Return: 0 on success, negative on failure + */ +int tpm_tis_open(struct udevice *udev) +{ + struct tpm_chip *chip = dev_get_priv(udev); + int ret; + + if (chip->is_open) + return -EBUSY; + + ret = tpm_tis_request_locality(udev, 0); + if (!ret) + chip->is_open = 1; + + return ret; +} + +/** + * tpm_tis_ops_register - register the PHY ops for the device + * + * @udev: udevice + * @ops: bus ops for the device + */ +void tpm_tis_ops_register(struct udevice *udev, struct tpm_tis_phy_ops *ops) +{ + struct tpm_chip *chip = dev_get_priv(udev); + + chip->phy_ops = ops; +} + +static bool tis_check_ops(struct tpm_tis_phy_ops *phy_ops) +{ + if (!phy_ops || !phy_ops->read_bytes || !phy_ops->write_bytes || + !phy_ops->read32 || !phy_ops->write32) + return false; + + return true; +} + +/** + * tpm_tis_init - inititalize the device + * + * @udev: udevice + * + * Return: 0 on success, negative on failure + */ +int tpm_tis_init(struct udevice *udev) +{ + struct tpm_chip *chip = dev_get_priv(udev); + struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; + int ret; + u32 tmp; + + if (!tis_check_ops(phy_ops)) { + log_err("Driver bug. No bus ops defined\n"); + return -1; + } + ret = tpm_tis_request_locality(udev, 0); + if (ret) + return ret; + + chip->timeout_a = TIS_SHORT_TIMEOUT_MS; + chip->timeout_b = TIS_LONG_TIMEOUT_MS; + chip->timeout_c = TIS_SHORT_TIMEOUT_MS; + chip->timeout_d = TIS_SHORT_TIMEOUT_MS; + + /* Disable interrupts */ + phy_ops->read32(udev, TPM_INT_ENABLE(chip->locality), &tmp); + tmp |= TPM_INTF_CMD_READY_INT | TPM_INTF_LOCALITY_CHANGE_INT | + TPM_INTF_DATA_AVAIL_INT | TPM_INTF_STS_VALID_INT; + tmp &= ~TPM_GLOBAL_INT_ENABLE; + phy_ops->write32(udev, TPM_INT_ENABLE(chip->locality), tmp); + + phy_ops->read_bytes(udev, TPM_RID(chip->locality), 1, &chip->rid); + phy_ops->read32(udev, TPM_DID_VID(chip->locality), &chip->vend_dev); + + return tpm_tis_release_locality(udev, chip->locality); +} + +/** + * tpm_tis_close - Close the device and release locality + * + * @udev: udevice + * + * Return: 0 on success, negative on failure + */ +int tpm_tis_close(struct udevice *udev) +{ + struct tpm_chip *chip = dev_get_priv(udev); + int ret = 0; + + if (chip->is_open) { + ret = tpm_tis_release_locality(udev, chip->locality); + chip->is_open = 0; + } + + return ret; +} diff --git a/drivers/tpm/tpm_tis.h b/drivers/tpm/tpm_tis.h index 2a160fe05c9a..28dd7f200329 100644 --- a/drivers/tpm/tpm_tis.h +++ b/drivers/tpm/tpm_tis.h @@ -21,6 +21,36 @@ #include #include +struct tpm_tis_phy_ops { + int (*read_bytes)(struct udevice *udev, u32 addr, u16 len, + u8 *result); + int (*write_bytes)(struct udevice *udev, u32 addr, u16 len, + const u8 *value); + int (*read32)(struct udevice *udev, u32 addr, u32 *result); + int (*write32)(struct udevice *udev, u32 addr, u32 src); +}; + +enum tis_int_flags { + TPM_GLOBAL_INT_ENABLE = 0x80000000, + TPM_INTF_BURST_COUNT_STATIC = 0x100, + TPM_INTF_CMD_READY_INT = 0x080, + TPM_INTF_INT_EDGE_FALLING = 0x040, + TPM_INTF_INT_EDGE_RISING = 0x020, + TPM_INTF_INT_LEVEL_LOW = 0x010, + TPM_INTF_INT_LEVEL_HIGH = 0x008, + TPM_INTF_LOCALITY_CHANGE_INT = 0x004, + TPM_INTF_STS_VALID_INT = 0x002, + TPM_INTF_DATA_AVAIL_INT = 0x001, +}; + +#define TPM_ACCESS(l) (0x0000 | ((l) << 12)) +#define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12)) +#define TPM_STS(l) (0x0018 | ((l) << 12)) +#define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12)) +#define TPM_DID_VID(l) (0x0F00 | ((l) << 12)) +#define TPM_RID(l) (0x0F04 | ((l) << 12)) +#define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12)) + enum tpm_timeout { TPM_TIMEOUT_MS = 5, TIS_SHORT_TIMEOUT_MS = 750, @@ -43,6 +73,7 @@ struct tpm_chip { u8 rid; unsigned long timeout_a, timeout_b, timeout_c, timeout_d; /* msec */ ulong chip_type; + struct tpm_tis_phy_ops *phy_ops; }; struct tpm_input_header { @@ -130,4 +161,12 @@ enum tis_status { }; #endif +int tpm_tis_open(struct udevice *udev); +int tpm_tis_close(struct udevice *udev); +int tpm_tis_cleanup(struct udevice *udev); +int tpm_tis_send(struct udevice *udev, const u8 *buf, size_t len); +int tpm_tis_recv(struct udevice *udev, u8 *buf, size_t count); +int tpm_tis_get_desc(struct udevice *udev, char *buf, int size); +int tpm_tis_init(struct udevice *udev); +void tpm_tis_ops_register(struct udevice *udev, struct tpm_tis_phy_ops *ops); #endif diff --git a/include/tpm-v2.h b/include/tpm-v2.h index 13b3db67c60f..e6b68769f3ff 100644 --- a/include/tpm-v2.h +++ b/include/tpm-v2.h @@ -396,6 +396,7 @@ enum { TPM_STS_DATA_EXPECT = 1 << 3, TPM_STS_SELF_TEST_DONE = 1 << 2, TPM_STS_RESPONSE_RETRY = 1 << 1, + TPM_STS_READ_ZERO = 0x23 }; enum { From patchwork Wed Nov 3 15:09:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilias Apalodimas X-Patchwork-Id: 516764 Delivered-To: patch@linaro.org Received: by 2002:adf:eccd:0:0:0:0:0 with SMTP id s13csp712477wro; Wed, 3 Nov 2021 08:10:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJznaGolA6m9+ngpoXTJqQXAXYjyOKBlHcjPpSc1nDdIj1GuRaFnAeZugDRiQgR0CMJq+p91 X-Received: by 2002:a5d:5151:: with SMTP id u17mr28134395wrt.126.1635952203295; Wed, 03 Nov 2021 08:10:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635952203; cv=none; d=google.com; s=arc-20160816; b=pdmZSLvDDNRKhySTXoWsptKUN/diOfM10Np9GpyjM9HUx2H2KkeuXf30+UXhEN693e t8yk4J5KJOKlUXqdbxTShgh1xPIIGczHbqB0+MErh/q9QUccYIAOM7yNPxyUoUgcpcWL FoIBL6fa59yG/d25+Ihoq1xV8I+otOTGLLg8qpD4+E7sZd7msqxGn30HM+OI3emTMWkZ cYcFuJtDwBhtbERU/tyiuG/QIDHY2VKa+fuIu6MesWLEAnxNS6hZgV1DNfGBVFb2wPhn AQ0rh9WPXN6zRWM8NvyUb5wAb8fPvGaAY2k6o2KW++aO6EdFaJ3aHtuZ5q9mOTAUl80i PrsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9MqBSGEpFGRQirYA73Kf7VVfUQBLvF7x46M5u73GGJ4=; b=vH/zGmW14dOlgIZ4lnJ5BD8IzHflgAf5aQN+xCH1CncpE17OTGQ4KZO46/JnOS+BTN jBXFHnPMe+uLOpUMqdFNm8fLlOe73f5a2K4sdSQ5W61eqkK5cvLb0V2UvV1TXU3rArOK KH2uE8HBcCqJgOAsb74xv23CJ1qxWMIhoc1Ut25u8Z92r468UflGKoWQXrdoORT/m8T0 glQFyVo18opTFDjnrn555s39KldockMrUN7RD15EoJt9YqdSK4egzgkmP4mCRy6yo1IC R2rk1Yn10jtiiSBdN0+Co+F/lKvrzn2GxRugrMNCz7wXJz9hnVZqrxHPo7vbgwSgusgX TFuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ocWgLiCB; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id a5si3619441ejf.478.2021.11.03.08.10.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 08:10:03 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ocWgLiCB; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 829B883633; Wed, 3 Nov 2021 16:09:46 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="ocWgLiCB"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id C5DA38342C; Wed, 3 Nov 2021 16:09:40 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id F335E82DB4 for ; Wed, 3 Nov 2021 16:09:35 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ilias.apalodimas@linaro.org Received: by mail-wr1-x432.google.com with SMTP id t30so4046299wra.10 for ; Wed, 03 Nov 2021 08:09:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9MqBSGEpFGRQirYA73Kf7VVfUQBLvF7x46M5u73GGJ4=; b=ocWgLiCB3gt8pm5+L5b2CYW7qM1Zy47xkq2dsWQMX4YQeb8LhbqLGkuZwzF2xYJsE8 7eF6BW5XwTNsmxrqwCpZPcDhoTO/Ul5IBM322kL8RJizo8PQZUK3ql9Yv71APxcEDJOh dzYfoTzICq6sgMU8bkUF4qKXJpLwZeNsgz0grInREfKVZVO7R0AOyb+qS6sn92W21Rzv /aoYF7iJ61ZHj7R5swgNk0yjmGT7gpKV1QVu4314FpzkDprgNVAt1sdxKl2eGRq/DXvN 1acP8oruh/uuFtnZe+hOLxJIm9AZdvxa4XWu+IdlBp8mAGmGbOlgeQzLAT8iA3gO8ijP PKnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9MqBSGEpFGRQirYA73Kf7VVfUQBLvF7x46M5u73GGJ4=; b=6UjnLAQlX+nvW7tDPzIgjoS9ETVMxuHRXgNlrboX34WirisSbMWpL1+8m5LgN6+sfI wHyAP7YN09F4k7HpDHejIP2FW++offHjIIXeRdVjkcMM7YhvITM3xofFT78pCxDRMCRr 4/0k9ArR8Mtj+mnoUpZUql4i6Z4RgnF1tEWlXsxiNiwsjyLVcg4+mQFsYY+Qy1yckN9B BeJeWjoSMASIDt+Sitd38Zt2Mzsb+6QYXmYytmhlT33u4B40+LbiSLWuBE8bCzqVjJUN UFJlJmwo+yzBxxT9GcvIHrUmK5qSTBb/g/Fp+UU0HotCWqQ+WDjcCuYoLu2kprbe9dHE sIyg== X-Gm-Message-State: AOAM530tWG01ypl5LIq+R2s044P5krU6Trz2hezXZeGvjCGD49F5nsh2 1ZGc7b2rDWNlJ5gb3MJaPvuX9IG4IlldVA== X-Received: by 2002:adf:e109:: with SMTP id t9mr24074672wrz.387.1635952175470; Wed, 03 Nov 2021 08:09:35 -0700 (PDT) Received: from apalos.home ([2a02:587:4682:26e0:2e56:dcff:fe9a:8f06]) by smtp.gmail.com with ESMTPSA id f19sm2094947wmq.34.2021.11.03.08.09.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 08:09:34 -0700 (PDT) From: Ilias Apalodimas To: u-boot@lists.denx.de Cc: trini@konsulko.com, Ilias Apalodimas , Rick Chen , Sean Anderson , Simon Glass , Heinrich Schuchardt , Masahisa Kojima Subject: [PATCH 2/6 v4] tpm2: Add a TPMv2 MMIO TIS driver Date: Wed, 3 Nov 2021 17:09:05 +0200 Message-Id: <20211103150910.69732-3-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211103150910.69732-1-ilias.apalodimas@linaro.org> References: <20211103150910.69732-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add support for devices that expose a TPMv2 though MMIO. Apart from those devices, we can use the driver in our QEMU setups and test TPM related code which is difficult to achieve using the sandbox driver (e.g test the EFI TCG2 protocol). It's worth noting that a previous patch added TPMv2 TIS core functions, which the current driver is consuming. Signed-off-by: Ilias Apalodimas --- drivers/tpm/Kconfig | 9 +++ drivers/tpm/Makefile | 1 + drivers/tpm/tpm2_tis_mmio.c | 152 ++++++++++++++++++++++++++++++++++++ 3 files changed, 162 insertions(+) create mode 100644 drivers/tpm/tpm2_tis_mmio.c -- 2.33.1 diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig index 9eebab5cfd90..406ee8716e1e 100644 --- a/drivers/tpm/Kconfig +++ b/drivers/tpm/Kconfig @@ -161,6 +161,15 @@ config TPM2_FTPM_TEE help This driver supports firmware TPM running in TEE. +config TPM2_MMIO + bool "MMIO based TPM2 Interface" + depends on TPM_V2 + help + This driver supports firmware TPM2.0 MMIO interface. + The usual TPM operations and the 'tpm' command can be used to talk + to the device using the standard TPM Interface Specification (TIS) + protocol. + endif # TPM_V2 endmenu diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile index c65be5267002..494aa5a46d30 100644 --- a/drivers/tpm/Makefile +++ b/drivers/tpm/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_$(SPL_TPL_)TPM2_CR50_I2C) += cr50_i2c.o obj-$(CONFIG_TPM2_TIS_SANDBOX) += tpm2_tis_sandbox.o sandbox_common.o obj-$(CONFIG_TPM2_TIS_SPI) += tpm2_tis_spi.o obj-$(CONFIG_TPM2_FTPM_TEE) += tpm2_ftpm_tee.o +obj-$(CONFIG_TPM2_MMIO) += tpm2_tis_core.o tpm2_tis_mmio.o diff --git a/drivers/tpm/tpm2_tis_mmio.c b/drivers/tpm/tpm2_tis_mmio.c new file mode 100644 index 000000000000..3bd0b0871a83 --- /dev/null +++ b/drivers/tpm/tpm2_tis_mmio.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * driver for mmio TCG/TIS TPM (trusted platform module). + * + * Specifications at www.trustedcomputinggroup.org + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "tpm_tis.h" +#include "tpm_internal.h" + +/** + * struct tpm_tis_chip_data - Information about an MMIO TPM + * @pcr_count: Number of PCR per bank + * @pcr_select_min: Minimum size in bytes of the pcrSelect array + * @iobase: Base address + */ +struct tpm_tis_chip_data { + unsigned int pcr_count; + unsigned int pcr_select_min; + void __iomem *iobase; +}; + +static int mmio_read_bytes(struct udevice *udev, u32 addr, u16 len, + u8 *result) +{ + struct tpm_tis_chip_data *drv_data = (void *)dev_get_driver_data(udev); + + while (len--) + *result++ = ioread8(drv_data->iobase + addr); + return 0; +} + +static int mmio_write_bytes(struct udevice *udev, u32 addr, u16 len, + const u8 *value) +{ + struct tpm_tis_chip_data *drv_data = (void *)dev_get_driver_data(udev); + + while (len--) + iowrite8(*value++, drv_data->iobase + addr); + return 0; +} + +static int mmio_read32(struct udevice *udev, u32 addr, u32 *result) +{ + struct tpm_tis_chip_data *drv_data = (void *)dev_get_driver_data(udev); + + *result = ioread32(drv_data->iobase + addr); + return 0; +} + +static int mmio_write32(struct udevice *udev, u32 addr, u32 value) +{ + struct tpm_tis_chip_data *drv_data = (void *)dev_get_driver_data(udev); + + iowrite32(value, drv_data->iobase + addr); + return 0; +} + +static struct tpm_tis_phy_ops phy_ops = { + .read_bytes = mmio_read_bytes, + .write_bytes = mmio_write_bytes, + .read32 = mmio_read32, + .write32 = mmio_write32, +}; + +static int tpm_tis_probe(struct udevice *udev) +{ + struct tpm_tis_chip_data *drv_data = (void *)dev_get_driver_data(udev); + struct tpm_chip_priv *priv = dev_get_uclass_priv(udev); + int ret = 0; + fdt_addr_t ioaddr; + u64 sz; + + ioaddr = dev_read_addr(udev); + if (ioaddr == FDT_ADDR_T_NONE) + return log_msg_ret("ioaddr", -EINVAL); + + ret = dev_read_u64(udev, "reg", &sz); + if (ret) + return -EINVAL; + + drv_data->iobase = ioremap(ioaddr, sz); + log_debug("Remapped TPM2 base: 0x%llx size: 0x%llx\n", ioaddr, sz); + tpm_tis_ops_register(udev, &phy_ops); + ret = tpm_tis_init(udev); + if (ret) + goto iounmap; + + priv->pcr_count = drv_data->pcr_count; + priv->pcr_select_min = drv_data->pcr_select_min; + /* + * Although the driver probably works with a TPMv1 our Kconfig + * limits the driver to TPMv2 only + */ + priv->version = TPM_V2; + + return ret; +iounmap: + iounmap(drv_data->iobase); + return -EINVAL; +} + +static int tpm_tis_remove(struct udevice *udev) +{ + struct tpm_tis_chip_data *drv_data = (void *)dev_get_driver_data(udev); + + iounmap(drv_data->iobase); + return tpm_tis_cleanup(udev); +} + +static const struct tpm_ops tpm_tis_ops = { + .open = tpm_tis_open, + .close = tpm_tis_close, + .get_desc = tpm_tis_get_desc, + .send = tpm_tis_send, + .recv = tpm_tis_recv, + .cleanup = tpm_tis_cleanup, +}; + +static const struct tpm_tis_chip_data tpm_tis_std_chip_data = { + .pcr_count = 24, + .pcr_select_min = 3, +}; + +static const struct udevice_id tpm_tis_ids[] = { + { + .compatible = "tcg,tpm-tis-mmio", + .data = (ulong)&tpm_tis_std_chip_data, + }, + { } +}; + +U_BOOT_DRIVER(tpm_tis_mmio) = { + .name = "tpm_tis_mmio", + .id = UCLASS_TPM, + .of_match = tpm_tis_ids, + .ops = &tpm_tis_ops, + .probe = tpm_tis_probe, + .remove = tpm_tis_remove, + .priv_auto = sizeof(struct tpm_chip), +}; From patchwork Wed Nov 3 15:09:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilias Apalodimas X-Patchwork-Id: 516766 Delivered-To: patch@linaro.org Received: by 2002:adf:eccd:0:0:0:0:0 with SMTP id s13csp713090wro; Wed, 3 Nov 2021 08:10:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzokIxWcsRopDUFFJtYYVKjpRaSbEK9pvgjxxUGVCBGKoo1/ouFsDq+4/Fq8OnX7WFJM/ZA X-Received: by 2002:a17:907:8688:: with SMTP id qa8mr23628421ejc.40.1635952235907; Wed, 03 Nov 2021 08:10:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635952235; cv=none; d=google.com; s=arc-20160816; b=0xsM9sqA/R60P5WcZhyWZV8eiIFdzhpNXiAkNdheo7oi3iCbXJIJ170d9nHSkFYhxu s/J9vO1DgOjoBSMkZq9r3dPkE5UwG9D7ZGxWnLpclfYxRL3cFGrt6M08LbqwaaOzTVAU vxDjsCMTTePDnUhusHlSWwBobidCKdS9gKBm6c8r7G/npeOLM8wpnjk0ZmGFzee43ln5 AgEBRa0HXbEmeGTFH9ziYdP/glO+qOFi2yqPu70qh8z8ch0y+MxaauFvTKQtJgCv81xL 48mv4w3e0Xisx8teNpjBIZfSgekk2P/XofwMFXz9EkwXEaC+rbIr1WrQ81PrSxDWxt+L 8aoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ng8V3YqUxVvU1yxHf4yDuLuvsjuzyO+P8CqwJ6Vzuws=; b=sXhkf+az272hM1eyvyBgwrLv/udwehEaH5eM3Bcb5yzhSY0xHEucy/uqph1igo5oMy XZi0787mBaoKxR8JTdV98YqQ+LhAyH6uUuRuhEYvLI0npy5q7UU1l08ZGA4c1EIaPdVh PQbOz5cPSCvy0/09Bn4yir9/Swwn73HbbHV/b+LrH5Oh9q556uZK9QhZNrjcmXJiN7pb Jj/0OlBvNXyBoC1vhhgQjDYRL8iEYPs9Q3bQY3rcHNXl/rou5HX+r3/kYUSjGrCqkBkt CZoBWjOXIZ6vLPIWfiovPxdQG+hbY8daiG8rHchupnxNPP+fFbuLp6oBYkQyhfb61JzI l0mg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mFl5APBD; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id nc36si431219ejc.735.2021.11.03.08.10.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 08:10:35 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mFl5APBD; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 022ED83651; Wed, 3 Nov 2021 16:09:50 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="mFl5APBD"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 42FB083642; Wed, 3 Nov 2021 16:09:45 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3B41C83630 for ; Wed, 3 Nov 2021 16:09:38 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ilias.apalodimas@linaro.org Received: by mail-wr1-x42f.google.com with SMTP id d5so4101561wrc.1 for ; Wed, 03 Nov 2021 08:09:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ng8V3YqUxVvU1yxHf4yDuLuvsjuzyO+P8CqwJ6Vzuws=; b=mFl5APBD8uzJqhWPrGbKvB2/18cx4o/p+pZx/B4NPUAeQdO73CNCdZoySsk/Ib7lap es6nK8KIxo0o5VJKKu+rHLmF17ISRvPTr72CphTOefhopmfxwGXhql2jeiGXPjX8WYEk 3uM7/o7XPBN4t1oAVuW0x2Hk+RHmK59x46VNtt6dNB0S3jledPw4z8uVmRJFQ/yOq/GS fttyWFg2noKmAO7aJ0Tpe7qgz5psY4Oy/FMeosdGg86AlKJg4JPuaDn90UfUNdOwFC7M LBrNIWv31YDql0ru+rpjR4RhcEd5AFckKnHYtyiTr39dpnXisjU53GvVWvQC/t8/l/ZF tb9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ng8V3YqUxVvU1yxHf4yDuLuvsjuzyO+P8CqwJ6Vzuws=; b=Q42SKw7HDKp1+3Ha1e+UTJmGK01XqxANPeJUz98+g887g3+MNint+YDn4tH5Jd9ZgI Ar7XkdA8PMO0aglR9NFEuk4Ul1Eb0DJM4d+o7TXYkkxDG5Vvxyfp1Af7K6AzTzEB0PHc sO2qNvZLLqMOOcjYMzc67vSZGeRctOD9SVhrUisCOl37zg2yDafWOjgkSTJMduff7qRt btqCrsNJuuW5f0xatyT6a98BFL/cC6wcLvf6KO+0AQE406U54sf3hdA7wH+a0YlsrRRU Py9xt/Sh2gxub0l2a6VD8v6K8W/tjKWz30uLMjkdK4tcNb7GBBW1t7cFU3QfRBdXEVTQ 6Z5A== X-Gm-Message-State: AOAM531p99DTyUBBJy0itCH0FoV3bb95RiK4PMmeIijd9ia0f9/zR8r+ 3j6FkA2nUtzW9nKit4lyfK0iYBDfN+Asqw== X-Received: by 2002:adf:fc88:: with SMTP id g8mr27119157wrr.334.1635952177623; Wed, 03 Nov 2021 08:09:37 -0700 (PDT) Received: from apalos.home ([2a02:587:4682:26e0:2e56:dcff:fe9a:8f06]) by smtp.gmail.com with ESMTPSA id f19sm2094947wmq.34.2021.11.03.08.09.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 08:09:37 -0700 (PDT) From: Ilias Apalodimas To: u-boot@lists.denx.de Cc: trini@konsulko.com, Ilias Apalodimas , Rick Chen , Sean Anderson , Simon Glass , Heinrich Schuchardt , Masahisa Kojima Subject: [PATCH 3/6 v4] tpm: Use the new API on tpm2 spi driver Date: Wed, 3 Nov 2021 17:09:06 +0200 Message-Id: <20211103150910.69732-4-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211103150910.69732-1-ilias.apalodimas@linaro.org> References: <20211103150910.69732-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Convert our SPI TPM driver and use the newly added API Signed-off-by: Ilias Apalodimas --- drivers/tpm/Makefile | 2 +- drivers/tpm/tpm2_tis_spi.c | 440 +++---------------------------------- 2 files changed, 32 insertions(+), 410 deletions(-) -- 2.33.1 Reviewed-by: Simon Glass diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile index 494aa5a46d30..51725230c780 100644 --- a/drivers/tpm/Makefile +++ b/drivers/tpm/Makefile @@ -12,6 +12,6 @@ obj-$(CONFIG_TPM_ST33ZP24_SPI) += tpm_tis_st33zp24_spi.o obj-$(CONFIG_$(SPL_TPL_)TPM2_CR50_I2C) += cr50_i2c.o obj-$(CONFIG_TPM2_TIS_SANDBOX) += tpm2_tis_sandbox.o sandbox_common.o -obj-$(CONFIG_TPM2_TIS_SPI) += tpm2_tis_spi.o +obj-$(CONFIG_TPM2_TIS_SPI) += tpm2_tis_core.o tpm2_tis_spi.o obj-$(CONFIG_TPM2_FTPM_TEE) += tpm2_ftpm_tee.o obj-$(CONFIG_TPM2_MMIO) += tpm2_tis_core.o tpm2_tis_mmio.o diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c index 1d24d32d867e..547d163200ea 100644 --- a/drivers/tpm/tpm2_tis_spi.c +++ b/drivers/tpm/tpm2_tis_spi.c @@ -165,7 +165,7 @@ release_bus: return ret; } -static int tpm_tis_spi_read(struct udevice *dev, u16 addr, u8 *in, u16 len) +static int tpm_tis_spi_read(struct udevice *dev, u32 addr, u16 len, u8 *in) { return tpm_tis_spi_xfer(dev, addr, NULL, in, len); } @@ -175,382 +175,24 @@ static int tpm_tis_spi_read32(struct udevice *dev, u32 addr, u32 *result) __le32 result_le; int ret; - ret = tpm_tis_spi_read(dev, addr, (u8 *)&result_le, sizeof(u32)); + ret = tpm_tis_spi_read(dev, addr, sizeof(u32), (u8 *)&result_le); if (!ret) *result = le32_to_cpu(result_le); return ret; } -static int tpm_tis_spi_write(struct udevice *dev, u16 addr, const u8 *out, - u16 len) -{ - return tpm_tis_spi_xfer(dev, addr, out, NULL, len); -} - -static int tpm_tis_spi_check_locality(struct udevice *dev, int loc) -{ - const u8 mask = TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID; - struct tpm_chip *chip = dev_get_priv(dev); - u8 buf; - int ret; - - ret = tpm_tis_spi_read(dev, TPM_ACCESS(loc), &buf, 1); - if (ret) - return ret; - - if ((buf & mask) == mask) { - chip->locality = loc; - return 0; - } - - return -ENOENT; -} - -static void tpm_tis_spi_release_locality(struct udevice *dev, int loc, - bool force) -{ - const u8 mask = TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID; - u8 buf; - - if (tpm_tis_spi_read(dev, TPM_ACCESS(loc), &buf, 1) < 0) - return; - - if (force || (buf & mask) == mask) { - buf = TPM_ACCESS_ACTIVE_LOCALITY; - tpm_tis_spi_write(dev, TPM_ACCESS(loc), &buf, 1); - } -} - -static int tpm_tis_spi_request_locality(struct udevice *dev, int loc) -{ - struct tpm_chip *chip = dev_get_priv(dev); - unsigned long start, stop; - u8 buf = TPM_ACCESS_REQUEST_USE; - int ret; - - ret = tpm_tis_spi_check_locality(dev, loc); - if (!ret) - return 0; - - if (ret != -ENOENT) { - log(LOGC_NONE, LOGL_ERR, "%s: Failed to get locality: %d\n", - __func__, ret); - return ret; - } - - ret = tpm_tis_spi_write(dev, TPM_ACCESS(loc), &buf, 1); - if (ret) { - log(LOGC_NONE, LOGL_ERR, "%s: Failed to write to TPM: %d\n", - __func__, ret); - return ret; - } - - start = get_timer(0); - stop = chip->timeout_a; - do { - ret = tpm_tis_spi_check_locality(dev, loc); - if (!ret) - return 0; - - if (ret != -ENOENT) { - log(LOGC_NONE, LOGL_ERR, - "%s: Failed to get locality: %d\n", __func__, ret); - return ret; - } - - mdelay(TPM_TIMEOUT_MS); - } while (get_timer(start) < stop); - - log(LOGC_NONE, LOGL_ERR, "%s: Timeout getting locality: %d\n", __func__, - ret); - - return ret; -} - -static u8 tpm_tis_spi_status(struct udevice *dev, u8 *status) -{ - struct tpm_chip *chip = dev_get_priv(dev); - - return tpm_tis_spi_read(dev, TPM_STS(chip->locality), status, 1); -} - -static int tpm_tis_spi_wait_for_stat(struct udevice *dev, u8 mask, - unsigned long timeout, u8 *status) -{ - unsigned long start = get_timer(0); - unsigned long stop = timeout; - int ret; - - do { - mdelay(TPM_TIMEOUT_MS); - ret = tpm_tis_spi_status(dev, status); - if (ret) - return ret; - - if ((*status & mask) == mask) - return 0; - } while (get_timer(start) < stop); - - return -ETIMEDOUT; -} - -static u8 tpm_tis_spi_valid_status(struct udevice *dev, u8 *status) -{ - struct tpm_chip *chip = dev_get_priv(dev); - - return tpm_tis_spi_wait_for_stat(dev, TPM_STS_VALID, - chip->timeout_c, status); -} - -static int tpm_tis_spi_get_burstcount(struct udevice *dev) -{ - struct tpm_chip *chip = dev_get_priv(dev); - unsigned long start, stop; - u32 burstcount, ret; - - /* wait for burstcount */ - start = get_timer(0); - stop = chip->timeout_d; - do { - ret = tpm_tis_spi_read32(dev, TPM_STS(chip->locality), - &burstcount); - if (ret) - return -EBUSY; - - burstcount = (burstcount >> 8) & 0xFFFF; - if (burstcount) - return burstcount; - - mdelay(TPM_TIMEOUT_MS); - } while (get_timer(start) < stop); - - return -EBUSY; -} - -static int tpm_tis_spi_cancel(struct udevice *dev) -{ - struct tpm_chip *chip = dev_get_priv(dev); - u8 data = TPM_STS_COMMAND_READY; - - return tpm_tis_spi_write(dev, TPM_STS(chip->locality), &data, 1); -} - -static int tpm_tis_spi_recv_data(struct udevice *dev, u8 *buf, size_t count) -{ - struct tpm_chip *chip = dev_get_priv(dev); - int size = 0, burstcnt, len, ret; - u8 status; - - while (size < count && - tpm_tis_spi_wait_for_stat(dev, - TPM_STS_DATA_AVAIL | TPM_STS_VALID, - chip->timeout_c, &status) == 0) { - burstcnt = tpm_tis_spi_get_burstcount(dev); - if (burstcnt < 0) - return burstcnt; - - len = min_t(int, burstcnt, count - size); - ret = tpm_tis_spi_read(dev, TPM_DATA_FIFO(chip->locality), - buf + size, len); - if (ret < 0) - return ret; - - size += len; - } - - return size; -} - -static int tpm_tis_spi_recv(struct udevice *dev, u8 *buf, size_t count) -{ - struct tpm_chip *chip = dev_get_priv(dev); - int size, expected; - if (!chip) - return -ENODEV; - - if (count < TPM_HEADER_SIZE) { - size = -EIO; - goto out; - } - - size = tpm_tis_spi_recv_data(dev, buf, TPM_HEADER_SIZE); - if (size < TPM_HEADER_SIZE) { - log(LOGC_NONE, LOGL_ERR, "TPM error, unable to read header\n"); - goto out; - } - - expected = get_unaligned_be32(buf + 2); - if (expected > count) { - size = -EIO; - goto out; - } - - size += tpm_tis_spi_recv_data(dev, &buf[TPM_HEADER_SIZE], - expected - TPM_HEADER_SIZE); - if (size < expected) { - log(LOGC_NONE, LOGL_ERR, - "TPM error, unable to read remaining bytes of result\n"); - size = -EIO; - goto out; - } - -out: - tpm_tis_spi_cancel(dev); - tpm_tis_spi_release_locality(dev, chip->locality, false); - - return size; -} - -static int tpm_tis_spi_send(struct udevice *dev, const u8 *buf, size_t len) -{ - struct tpm_chip *chip = dev_get_priv(dev); - u32 i, size; - u8 status; - int burstcnt, ret; - u8 data; - - if (!chip) - return -ENODEV; - - if (len > TPM_DEV_BUFSIZE) - return -E2BIG; /* Command is too long for our tpm, sorry */ - - ret = tpm_tis_spi_request_locality(dev, 0); - if (ret < 0) - return -EBUSY; - - /* - * Check if the TPM is ready. If not, if not, cancel the pending command - * and poll on the status to be finally ready. - */ - ret = tpm_tis_spi_status(dev, &status); - if (ret) - return ret; - - if (!(status & TPM_STS_COMMAND_READY)) { - /* Force the transition, usually this will be done at startup */ - ret = tpm_tis_spi_cancel(dev); - if (ret) { - log(LOGC_NONE, LOGL_ERR, - "%s: Could not cancel previous operation\n", - __func__); - goto out_err; - } - - ret = tpm_tis_spi_wait_for_stat(dev, TPM_STS_COMMAND_READY, - chip->timeout_b, &status); - if (ret < 0 || !(status & TPM_STS_COMMAND_READY)) { - log(LOGC_NONE, LOGL_ERR, - "status %d after wait for stat returned %d\n", - status, ret); - goto out_err; - } - } - - for (i = 0; i < len - 1;) { - burstcnt = tpm_tis_spi_get_burstcount(dev); - if (burstcnt < 0) - return burstcnt; - - size = min_t(int, len - i - 1, burstcnt); - ret = tpm_tis_spi_write(dev, TPM_DATA_FIFO(chip->locality), - buf + i, size); - if (ret < 0) - goto out_err; - - i += size; - } - - ret = tpm_tis_spi_valid_status(dev, &status); - if (ret) - goto out_err; - - if ((status & TPM_STS_DATA_EXPECT) == 0) { - ret = -EIO; - goto out_err; - } - - ret = tpm_tis_spi_write(dev, TPM_DATA_FIFO(chip->locality), - buf + len - 1, 1); - if (ret) - goto out_err; - - ret = tpm_tis_spi_valid_status(dev, &status); - if (ret) - goto out_err; - - if ((status & TPM_STS_DATA_EXPECT) != 0) { - ret = -EIO; - goto out_err; - } - - data = TPM_STS_GO; - ret = tpm_tis_spi_write(dev, TPM_STS(chip->locality), &data, 1); - if (ret) - goto out_err; - - return len; - -out_err: - tpm_tis_spi_cancel(dev); - tpm_tis_spi_release_locality(dev, chip->locality, false); - - return ret; -} - -static int tpm_tis_spi_cleanup(struct udevice *dev) +static int tpm_tis_spi_write(struct udevice *dev, u32 addr, u16 len, const u8 *out) { - struct tpm_chip *chip = dev_get_priv(dev); - - tpm_tis_spi_cancel(dev); - /* - * The TPM needs some time to clean up here, - * so we sleep rather than keeping the bus busy - */ - mdelay(2); - tpm_tis_spi_release_locality(dev, chip->locality, false); - - return 0; -} - -static int tpm_tis_spi_open(struct udevice *dev) -{ - struct tpm_chip *chip = dev_get_priv(dev); - - if (chip->is_open) - return -EBUSY; - - chip->is_open = 1; - - return 0; -} - -static int tpm_tis_spi_close(struct udevice *dev) -{ - struct tpm_chip *chip = dev_get_priv(dev); - - if (chip->is_open) { - tpm_tis_spi_release_locality(dev, chip->locality, true); - chip->is_open = 0; - } - - return 0; + return tpm_tis_spi_xfer(dev, addr, out, NULL, len); } -static int tpm_tis_get_desc(struct udevice *dev, char *buf, int size) +static int tpm_tis_spi_write32(struct udevice *dev, u32 addr, u32 value) { - struct tpm_chip *chip = dev_get_priv(dev); - - if (size < 80) - return -ENOSPC; + __le32 value_le = cpu_to_le32(value); - return snprintf(buf, size, - "%s v2.0: VendorID 0x%04x, DeviceID 0x%04x, RevisionID 0x%02x [%s]", - dev->name, chip->vend_dev & 0xFFFF, - chip->vend_dev >> 16, chip->rid, - (chip->is_open ? "open" : "closed")); + return tpm_tis_spi_write(dev, addr, sizeof(value), (u8 *)&value_le); } static int tpm_tis_wait_init(struct udevice *dev, int loc) @@ -565,7 +207,7 @@ static int tpm_tis_wait_init(struct udevice *dev, int loc) do { mdelay(TPM_TIMEOUT_MS); - ret = tpm_tis_spi_read(dev, TPM_ACCESS(loc), &status, 1); + ret = tpm_tis_spi_read(dev, TPM_ACCESS(loc), 1, &status); if (ret) break; @@ -576,6 +218,13 @@ static int tpm_tis_wait_init(struct udevice *dev, int loc) return -EIO; } +static struct tpm_tis_phy_ops phy_ops = { + .read_bytes = tpm_tis_spi_read, + .write_bytes = tpm_tis_spi_write, + .read32 = tpm_tis_spi_read32, + .write32 = tpm_tis_spi_write32, +}; + static int tpm_tis_spi_probe(struct udevice *dev) { struct tpm_tis_chip_data *drv_data = (void *)dev_get_driver_data(dev); @@ -611,65 +260,38 @@ init: /* Ensure a minimum amount of time elapsed since reset of the TPM */ mdelay(drv_data->time_before_first_cmd_ms); - chip->locality = 0; - chip->timeout_a = TIS_SHORT_TIMEOUT_MS; - chip->timeout_b = TIS_LONG_TIMEOUT_MS; - chip->timeout_c = TIS_SHORT_TIMEOUT_MS; - chip->timeout_d = TIS_SHORT_TIMEOUT_MS; - priv->pcr_count = drv_data->pcr_count; - priv->pcr_select_min = drv_data->pcr_select_min; - ret = tpm_tis_wait_init(dev, chip->locality); if (ret) { log(LOGC_DM, LOGL_ERR, "%s: no device found\n", __func__); return ret; } - ret = tpm_tis_spi_request_locality(dev, chip->locality); - if (ret) { - log(LOGC_NONE, LOGL_ERR, "%s: could not request locality %d\n", - __func__, chip->locality); - return ret; - } - - ret = tpm_tis_spi_read32(dev, TPM_DID_VID(chip->locality), - &chip->vend_dev); - if (ret) { - log(LOGC_NONE, LOGL_ERR, - "%s: could not retrieve VendorID/DeviceID\n", __func__); - return ret; - } - - ret = tpm_tis_spi_read(dev, TPM_RID(chip->locality), &chip->rid, 1); - if (ret) { - log(LOGC_NONE, LOGL_ERR, "%s: could not retrieve RevisionID\n", - __func__); - return ret; - } + tpm_tis_ops_register(dev, &phy_ops); + ret = tpm_tis_init(dev); + if (ret) + goto err; - log(LOGC_NONE, LOGL_ERR, - "SPI TPMv2.0 found (vid:%04x, did:%04x, rid:%02x)\n", - chip->vend_dev & 0xFFFF, chip->vend_dev >> 16, chip->rid); + priv->pcr_count = drv_data->pcr_count; + priv->pcr_select_min = drv_data->pcr_select_min; + priv->version = TPM_V2; return 0; +err: + return -EINVAL; } -static int tpm_tis_spi_remove(struct udevice *dev) +static int tpm_tis_spi_remove(struct udevice *udev) { - struct tpm_chip *chip = dev_get_priv(dev); - - tpm_tis_spi_release_locality(dev, chip->locality, true); - - return 0; + return tpm_tis_cleanup(udev); } static const struct tpm_ops tpm_tis_spi_ops = { - .open = tpm_tis_spi_open, - .close = tpm_tis_spi_close, + .open = tpm_tis_open, + .close = tpm_tis_close, .get_desc = tpm_tis_get_desc, - .send = tpm_tis_spi_send, - .recv = tpm_tis_spi_recv, - .cleanup = tpm_tis_spi_cleanup, + .send = tpm_tis_send, + .recv = tpm_tis_recv, + .cleanup = tpm_tis_cleanup, }; static const struct tpm_tis_chip_data tpm_tis_std_chip_data = { From patchwork Wed Nov 3 15:09:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilias Apalodimas X-Patchwork-Id: 516769 Delivered-To: patch@linaro.org Received: by 2002:adf:eccd:0:0:0:0:0 with SMTP id s13csp713387wro; Wed, 3 Nov 2021 08:10:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy2hmb62bVTdxwuSSZMOIQAYfHiFYozYu1dqib+t+Mf2u6Wl3dsqKOuaxJSf+tfhLyEUhx+ X-Received: by 2002:a05:6402:4401:: with SMTP id y1mr21846926eda.225.1635952250470; Wed, 03 Nov 2021 08:10:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635952250; cv=none; d=google.com; s=arc-20160816; b=XM8msTM31GPbBSuzCpoln6ZCvDMMq/ZZMc5tbqopgvBJsth5LXjhtisKIRtq8nUb5K hBphNOffGH8JikM6Rgnba8C08NFZhHGu6LG/o2iGwornkSI07wSCm1W67/cKQSyonZpo +3AQaOC60FQ9CQ/geaMUl0DODmfuePilholCexHjL3ZV1xN9zIXuBodmJTVs5yQUw+ur 1Y3V3Q7ZFlG8lcyXGrG8sF7uin0VGzma5zWCerMU0YWiza47PQNorZgUNSO2U5Hnp2WX ZV1mM13BEBi1lGuWa8B4ZX4UHGEhA4nr/Uw1LLM3plvLu+7fnn9jnBX1CkGOcxdfgIG8 G/4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZffdLTNpokGR3G2SGMvSVO3n8FhG/gBVQM6GGuROlqQ=; b=gKnTGN0gE25PVKs8nzMbzNjc6ouv9TEHLN8J/+sTi90LjGky7ipRV6YiqxhTnSF9cQ V9uSp0dlTHmopmUqVINyCwxyrfhDByS5cnVYYet/T8eTPrHlqWtScZ6pt8XTrCf/XfMz 91ECjmhkZnq6pWhVVKO1ZX75jyd1FKJ28+2VyANkqhczGZJaagz9uaAx+U0i7yM+KHve cuhopWbZx9lO4CTSq6+IMbq+jPveYIigznKdE8JMiYsHOaFFDd93lXVScu8/TKWzex4U 2/gMR3kTgEB4i1ranRoioonvFSigS8uKUV++H7eyQLGHQKaBRS/C9sADCE5C7z2VUzLO 7VsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ANGXGfPu; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id b15si4452806ede.50.2021.11.03.08.10.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 08:10:50 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ANGXGfPu; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 49A2A8363C; Wed, 3 Nov 2021 16:09:55 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="ANGXGfPu"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 2158283630; Wed, 3 Nov 2021 16:09:46 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1C4348347E for ; Wed, 3 Nov 2021 16:09:40 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ilias.apalodimas@linaro.org Received: by mail-wr1-x433.google.com with SMTP id d24so4146641wra.0 for ; Wed, 03 Nov 2021 08:09:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZffdLTNpokGR3G2SGMvSVO3n8FhG/gBVQM6GGuROlqQ=; b=ANGXGfPun0ah1wYkAc8BJ041Pkm3RyxGVOHiiRGfRW9VmSlNQjhSw3jAIskoherr5k VBW/0u+VK8iXpiOhUnana8eOX7o1+mCfFaUwsQ/Nmz4JIgWbuHvW+ZewQfa+7zQj/10j Y4BvHdc/XGBwkg9jmMEYEKs+4SCidSiIL71JPT1s+a/04pWEiQkDZWRcQZtfOOvMVBdP 8z+LAn0o1SKhNYxEjDAH0br7n8Hksm6+wMmTGFXM+QXgYXMdnFMT2t6MUjwbqkCMQi4q qmMvoPwLL4S98wBgkg/jvviHk3fXeHZVVXQyhBgqXkzoLsmVy3WlmVTBJjU0YHHWHPxX 6JXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZffdLTNpokGR3G2SGMvSVO3n8FhG/gBVQM6GGuROlqQ=; b=F5oWTES9dEqGzXF3+wyLSnsEOVyepAGrEtJYli1XVp3BvtezVo95+ljkpEelMn0bsj b13ASaC30sBQaNGT/PHghG4VKtIDvekDgbXaUzyyuW1QGNW0ZU9DjrxN1ZBDlJktYOWf wEJ2aACwCRq54n+aRTnxt3o3kl1Y+30wMHGMliIOpkc7uNuDEeqGzD30ulbiOt8lQRAi M9qoaX2qT+RXdjiTH++LrO6mzKPvfVJ/WsZD31f07sqHQE24TZphXoemSqNWtYP5I2o5 crYoNkAT/6/Zt5ZmLGwUwGbZUF63gksVogsnHYGgYh2K4q1ULHYkBl0IHn4zZKNyXlkx /lAw== X-Gm-Message-State: AOAM5326y6LKweFfvPtugaDCVmf+7hy3WsxAxk/cVy/yegbLGNbUGGh7 P8YoOaTQzJCEdnKVl42P7kYZ6FUn02rvYQ== X-Received: by 2002:a5d:6488:: with SMTP id o8mr1879697wri.348.1635952179699; Wed, 03 Nov 2021 08:09:39 -0700 (PDT) Received: from apalos.home ([2a02:587:4682:26e0:2e56:dcff:fe9a:8f06]) by smtp.gmail.com with ESMTPSA id f19sm2094947wmq.34.2021.11.03.08.09.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 08:09:39 -0700 (PDT) From: Ilias Apalodimas To: u-boot@lists.denx.de Cc: trini@konsulko.com, Ilias Apalodimas , Rick Chen , Sean Anderson , Simon Glass , Heinrich Schuchardt , Masahisa Kojima Subject: [PATCH 4/6 v4] configs: Enable tpmv2 mmio on qemu for arm/arm64 Date: Wed, 3 Nov 2021 17:09:07 +0200 Message-Id: <20211103150910.69732-5-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211103150910.69732-1-ilias.apalodimas@linaro.org> References: <20211103150910.69732-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean A previous commit is adding an MMIO TPMv2 driver. Include in the default qemu arm configs, since we plan on using them on EFI testing Signed-off-by: Ilias Apalodimas --- configs/qemu_arm64_defconfig | 2 ++ configs/qemu_arm_defconfig | 2 ++ 2 files changed, 4 insertions(+) -- 2.33.1 Reviewed-by: Simon Glass diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 003717efde28..83d7ae54de4d 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -49,6 +49,8 @@ CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_PSCI=y +CONFIG_TPM2_MMIO=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y +CONFIG_TPM=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index 27b0e49f6f89..ab5574847e89 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -51,6 +51,8 @@ CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_PSCI=y +CONFIG_TPM2_MMIO=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y +CONFIG_TPM=y From patchwork Wed Nov 3 15:09:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilias Apalodimas X-Patchwork-Id: 516768 Delivered-To: patch@linaro.org Received: by 2002:adf:eccd:0:0:0:0:0 with SMTP id s13csp713320wro; Wed, 3 Nov 2021 08:10:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyx2obkY2y3DgivD7MkNUbb1TmU432I9HfDW+Br4P+8rfBayIMIz0SOa/PLDWUjadlp+bc0 X-Received: by 2002:a17:907:d08:: with SMTP id gn8mr54058345ejc.395.1635952246548; Wed, 03 Nov 2021 08:10:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635952246; cv=none; d=google.com; s=arc-20160816; b=gsWvp98sxfrnJMConMxeThE92bxIY+0ivfV2IUZYw0pnKHiOEIjpU4QeqGoBn6VnaS v+5364O4ud5pQkITE8emLgfcfnjrkkGTI8rXRJNIkfHdaIUzNuV4Yyljujga7vJFq1jR BLetPmdwnFxwqwk4jt5HZHryPF4ci4VGraQjN0DfIlZz60TOoW+bAbtdRN906VJzX09t C/jCrrcrb7CpMrGluMtZ2pJfiS16wdIqrDeozlSZw3nuwL+G0v6zEI+7FyDWD9woINez KB+L7tVl/1dHmwl8mZpQaWiGtx7K4+KUVRNdHPCqSFcXamSidY3xFhFcyo41F/fmujOZ D/nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WCxbIowzUa629S/FdYL7gevtrOF6/TDQkQgdWB6a8R4=; b=S+BrnNT8HE4UOFleBgKP6+wBAb0goPGDJ/JEbBFm1Ki6odj4s/n2WyZ3ZVJBec2K8U f76AwaCYt1U0PQLqgyJaeZFAV48UDNrU96uHDCnbi8SghAFMBnQN7bPE8F+j/Znwa+24 tPAHbg5dJLQU72YUEGCllGXDMSr0ycF5PXH9mgognoEIIEINrQAXxVfeiExL2uNMZ/cG 03FqxuupSKox9pT3J43hFxFwiS94/d4/o3kJOC7ZccPr8GwasAM0/7aFaTS1kL/b0Bpm FqcelMRXq1PTKoJm97U5WkML90rHrmBoew3W6ikgMlOeaXwL3dxWlawKjgo/vuhEPRQg KkFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UarXavVR; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id di15si4513583ejc.585.2021.11.03.08.10.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 08:10:46 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UarXavVR; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7D0DD83658; Wed, 3 Nov 2021 16:09:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="UarXavVR"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3C7ED8347E; Wed, 3 Nov 2021 16:09:47 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5EACC8363C for ; Wed, 3 Nov 2021 16:09:42 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ilias.apalodimas@linaro.org Received: by mail-wr1-x431.google.com with SMTP id d13so4045724wrf.11 for ; Wed, 03 Nov 2021 08:09:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WCxbIowzUa629S/FdYL7gevtrOF6/TDQkQgdWB6a8R4=; b=UarXavVRYaI5n3LHTbWeOruE83ix3Gl1lTs4II1eHsVZE2kZ8BdgGUTdenqK1DMmgh 2pTDBhu0xYWn50E7HgoojR4QBGNRp2yzJMEtno22tTrGhu6s8UswiJmk7NULkmcjbTpF qGBUqBNGxmwkn+4r4n2cvmrViRzIK0T1NQXW891f6wveBz1FZCIyxPVK118TN97WVI2j u5a3uJBt/g+3tPxoHMQLdVhsTh/LfG05R+PY8CQNR86WZLnpcv/Xjow5sSauaJLL4kT3 o5qI48reJfg+f2OR2gUJMkRS7q2Zf8BC0Zw0TXLJVo9XdrtST1BjacNGS2XTT42P9Lg4 z6Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WCxbIowzUa629S/FdYL7gevtrOF6/TDQkQgdWB6a8R4=; b=YZ9FH0SHjIn5d6pGP7qvXzcjRIWDn2KHuwhnG/5XutMfn9R55FtKRELhmKrmFYJXj/ MDPr+FHdqsgHqkB9iBgGX2Vjk0Sz68gzf9GGKzkEabdqU7nwqQsCXC5rd4ZTwBgmstr7 5X0TnPUxzJktqCRHO0AxP7vD3ZO4HW3TocBctBbnq6ykDmLSZ7e5NB1w026/2LKdkKBo jZy77FspZ+qTDbmEebrAlklYRGjU6eYtCPeDl8+VaJF4FND9aaGEpbjBDiQ931oLpGBV wkSUliCUGSj8TQ7TRrUvy3/Ppl46winZZoIHIm7lwazxi/XUJuUu0u9wSURjULqzhHwH +hdA== X-Gm-Message-State: AOAM531Yv/UQbZdKdW7X3oZV64M+DZtYiyJq0D1uNjYr5T0WgP9f+u63 zD2kJI9Fj/0U08Gvl5ssx0E4BnqngxrAPw== X-Received: by 2002:a5d:6d07:: with SMTP id e7mr22161501wrq.311.1635952181911; Wed, 03 Nov 2021 08:09:41 -0700 (PDT) Received: from apalos.home ([2a02:587:4682:26e0:2e56:dcff:fe9a:8f06]) by smtp.gmail.com with ESMTPSA id f19sm2094947wmq.34.2021.11.03.08.09.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 08:09:41 -0700 (PDT) From: Ilias Apalodimas To: u-boot@lists.denx.de Cc: trini@konsulko.com, Ilias Apalodimas , Rick Chen , Sean Anderson , Simon Glass , Heinrich Schuchardt , Masahisa Kojima Subject: [PATCH 5/6 v4] doc: qemu: Add instructions for swtpm usage Date: Wed, 3 Nov 2021 17:09:08 +0200 Message-Id: <20211103150910.69732-6-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211103150910.69732-1-ilias.apalodimas@linaro.org> References: <20211103150910.69732-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean A previous patch added support for an mmio based TPM. Add an example in QEMU on it's usage Signed-off-by: Ilias Apalodimas --- doc/board/emulation/qemu-arm.rst | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) -- 2.33.1 Reviewed-by: Simon Glass diff --git a/doc/board/emulation/qemu-arm.rst b/doc/board/emulation/qemu-arm.rst index 8d7fda10f15e..584ef0a7e150 100644 --- a/doc/board/emulation/qemu-arm.rst +++ b/doc/board/emulation/qemu-arm.rst @@ -81,6 +81,31 @@ can be enabled with the following command line parameters: These have been tested in QEMU 2.9.0 but should work in at least 2.5.0 as well. +Enabling TPMv2 support +---------------------- + +To emulate a TPM the swtpm package may be used. It can be built from the +following repositories: + + https://github.com/stefanberger/swtpm.git + +Swtpm provides a socket for the TPM emulation which can be consumed by QEMU. + +In a first console invoke swtpm with:: + + swtpm socket --tpmstate dir=/tmp/mytpm1 \ + --ctrl type=unixio,path=/tmp/mytpm1/swtpm-sock --log level=20 + +In a second console invoke qemu-system-aarch64 with:: + + -chardev socket,id=chrtpm,path=/tmp/mytpm1/swtpm-sock \ + -tpmdev emulator,id=tpm0,chardev=chrtpm \ + -device tpm-tis-device,tpmdev=tpm0 + +Enable the TPM on U-Boot's command line with:: + + tpm2 startup TPM2_SU_CLEAR + Debug UART ---------- From patchwork Wed Nov 3 15:09:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilias Apalodimas X-Patchwork-Id: 516767 Delivered-To: patch@linaro.org Received: by 2002:adf:eccd:0:0:0:0:0 with SMTP id s13csp713289wro; Wed, 3 Nov 2021 08:10:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz5+78VmfCshcrqD7hjrmeanVn9CH58sXLLxPaDlhrm6wKSfBHXoUIsAq0W6lCWQFNWl4Bu X-Received: by 2002:a50:f08b:: with SMTP id v11mr56223405edl.96.1635952244524; Wed, 03 Nov 2021 08:10:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635952244; cv=none; d=google.com; s=arc-20160816; b=lbXDIjIPJ1BLXW4PlmnCOkPggBAG6gfz54Z5UAby4n6WkLAFyJPvSNya1L26RBeGOu qmpW9WrVHOc0lTUY6OxyCIa06R80/z+fap7/HgmaZgWhFczGf4imfprAowPsaqhq698F vdOq1U7nZmE3fV8/Jnxa4CAhNZbb9XnSFVukHymAKmG57kweXnMSb5gNrEUNf9gZL0qi xp7xwSkebetWVCly7W5qhtJrXLvEWqh5nqnN2y2ZCIduXjWnHphJrMCZirslSAfor8Nf lbskdYk/9pOEkWlqkQLCQuID5wxPASHCYGvTwsJpYv9tU5oQvw35wjSheySjd8MPc4sy 0J3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bFUlG2gk3Tf+KwjFFoRE74pt9H9+XPT886mGUjKJZrk=; b=ygdN54SWPAZcNyqssZ/YV2+azOcJaRJ91H4hHpFxcnI2zKdOC1OH7de0LgTnhqwYHW FZTCei58ApJ6bMo+PCAVbaXOXht/8MGnRaGUPPAmFeOdmOwLkmg9Arhovh6mAOJgx9GR QB/rX8lBS2nHDLYEE/nRQ6Zvi8vSdB9Nj7JZUDZ4Sj42ecLgbsua0gSrImLNBe45xpih jH8WcCJDz41wnwG2ThIsQ1mSn5ojthXuvz46qQYT3LfFxr+IF5k36csB7pmWjXQqau4y hQUHckAbn3CCo9z6GqCBy+bojTkX40mEUVCIp0PsDYqN8fS+00A0OyfaQXBzWlncWMge 0/XA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="jp254A/L"; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id v6si3082996edc.621.2021.11.03.08.10.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 08:10:44 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="jp254A/L"; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DB5998365E; Wed, 3 Nov 2021 16:09:57 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="jp254A/L"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id E36D08364F; Wed, 3 Nov 2021 16:09:50 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8DC9983647 for ; Wed, 3 Nov 2021 16:09:44 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ilias.apalodimas@linaro.org Received: by mail-wr1-x431.google.com with SMTP id c4so4045892wrd.9 for ; Wed, 03 Nov 2021 08:09:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bFUlG2gk3Tf+KwjFFoRE74pt9H9+XPT886mGUjKJZrk=; b=jp254A/LGjNx9NyrwPiLABmUl3MRHwu+iPAdQq7CZzg/gGeLl/IjAn9LdhQcW51KhZ qmS3QRR69HfzrCAsyPZz8FYIvGQ4a6W7tBAfqm4169YMZ1j2purB3D8j7TWeDMZw+J6k PXn4Opb1+Z/aflhh2zVWZgMbxtJtmtQKYIFEqgAEOxHpKjaTT6CKe1k6MA7ljqrUpMiK 83il+YIOkAK8DBzEdMdmExsYai1IgYFIC3qojZjA1JzmMj1Qzh7/5jQB9nyKWkvkTTtg k5O7zy7gW6tO4MMelm55YhjB5qre0ENuat4Ie5703kuTPPtxATcqUFh6IidDc23Me0Hl wDlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bFUlG2gk3Tf+KwjFFoRE74pt9H9+XPT886mGUjKJZrk=; b=dywcC+eeVXuZDKVEiovqTLXnOLmKxwhyr1Rr/d8XSYkJEiwnRzAzWjq+I7zSzrFT9X X2AlWvGoLq75gpUQHLuMWrbzdWcTj4yMvKaGgLHyDesDPEVzcxfb6dV1KPYqpa9Mt6gn rEYy7iMrGPz6KH51qGG0r41YDBGp/LEhfyRyJwovtojcjOBH9e47WMkcJwgMKh1oPnB0 RltHG78GCpkzyCBjXoTsuN92bIHiFVmT9QaUbXxwDCJFtKKrzGQhLJDv6q2hEgnYp65O i+RcMXJ2SHIdyJ8z03hmv1+lrTQberVj67po1F5IooCEAmq3ESwfp9zWnWJ/tB/yPvLL bh2A== X-Gm-Message-State: AOAM532srYXIMHe8fq2QbCRJYzf50pUlA2T9zH9p8oi8hEY8eEnV3P8Q 6OF1JzeOmbvENyR5xf2gLy008dQnPOksvQ== X-Received: by 2002:adf:d1cd:: with SMTP id b13mr6203157wrd.323.1635952184026; Wed, 03 Nov 2021 08:09:44 -0700 (PDT) Received: from apalos.home ([2a02:587:4682:26e0:2e56:dcff:fe9a:8f06]) by smtp.gmail.com with ESMTPSA id f19sm2094947wmq.34.2021.11.03.08.09.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 08:09:43 -0700 (PDT) From: Ilias Apalodimas To: u-boot@lists.denx.de Cc: trini@konsulko.com, Ilias Apalodimas , Heinrich Schuchardt , Simon Glass , Rick Chen , Sean Anderson , Masahisa Kojima Subject: [PATCH 6/6 v4] MAINTAINERS: Add entry for TPM drivers Date: Wed, 3 Nov 2021 17:09:09 +0200 Message-Id: <20211103150910.69732-7-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211103150910.69732-1-ilias.apalodimas@linaro.org> References: <20211103150910.69732-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean TPM drivers have currently no maintainers. Add myself since I contributed the TIS implementation. Signed-off-by: Ilias Apalodimas Reviewed-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- MAINTAINERS | 5 +++++ 1 file changed, 5 insertions(+) -- 2.33.1 diff --git a/MAINTAINERS b/MAINTAINERS index 9d8cba902800..f02901c55de5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1183,6 +1183,11 @@ F: configs/am65x_hs_evm_a53_defconfig F: configs/j721e_hs_evm_r5_defconfig F: configs/j721e_hs_evm_a72_defconfig +TPM DRIVERS +M: Ilias Apalodimas +S: Maintained +F: drivers/tpm/ + TQ GROUP #M: Martin Krause S: Orphaned (Since 2016-02)