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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 01/60] accel/tcg: Split out adjust_signal_pc Date: Tue, 2 Nov 2021 07:06:41 -0400 Message-Id: <20211102110740.215699-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2c; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out a function to adjust the raw signal pc into a value that could be passed to cpu_restore_state. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Adjust pc in place; return MMUAccessType. --- include/exec/exec-all.h | 10 ++++++++++ accel/tcg/user-exec.c | 41 +++++++++++++++++++++++++---------------- 2 files changed, 35 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 9d5987ba04..e54f8e5d65 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -663,6 +663,16 @@ static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, return addr; } +/** + * adjust_signal_pc: + * @pc: raw pc from the host signal ucontext_t. + * @is_write: host memory operation was write, or read-modify-write. + * + * Alter @pc as required for unwinding. Return the type of the + * guest memory access -- host reads may be for guest execution. + */ +MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); + /** * cpu_signal_handler * @signum: host signal number diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e6bb29b42d..c02d509ec6 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -57,18 +57,11 @@ static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu, cpu_loop_exit_noexc(cpu); } -/* 'pc' is the host PC at which the exception was raised. 'address' is - the effective address of the memory exception. 'is_write' is 1 if a - write caused the exception and otherwise 0'. 'old_set' is the - signal set which should be restored */ -static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, - int is_write, sigset_t *old_set) +/* + * Adjust the pc to pass to cpu_restore_state; return the memop type. + */ +MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write) { - CPUState *cpu = current_cpu; - CPUClass *cc; - unsigned long address = (unsigned long)info->si_addr; - MMUAccessType access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; - switch (helper_retaddr) { default: /* @@ -77,7 +70,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * pointer into the generated code that will unwind to the * correct guest pc. */ - pc = helper_retaddr; + *pc = helper_retaddr; break; case 0: @@ -97,7 +90,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * Therefore, adjust to compensate for what will be done later * by cpu_restore_state_from_tb. */ - pc += GETPC_ADJ; + *pc += GETPC_ADJ; break; case 1: @@ -113,12 +106,28 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * * Like tb_gen_code, release the memory lock before cpu_loop_exit. */ - pc = 0; - access_type = MMU_INST_FETCH; mmap_unlock(); - break; + *pc = 0; + return MMU_INST_FETCH; } + return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; +} + +/* + * 'pc' is the host PC at which the exception was raised. + * 'address' is the effective address of the memory exception. + * 'is_write' is 1 if a write caused the exception and otherwise 0. + * 'old_set' is the signal set which should be restored. + */ +static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, + int is_write, sigset_t *old_set) +{ + CPUState *cpu = current_cpu; + CPUClass *cc; + unsigned long address = (unsigned long)info->si_addr; + MMUAccessType access_type = adjust_signal_pc(&pc, is_write); + /* For synchronous signals we expect to be coming from the vCPU * thread (so current_cpu should be valid) and either from running * code or during translation which can fault as we cross pages. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 02/60] accel/tcg: Move clear_helper_retaddr to cpu loop Date: Tue, 2 Nov 2021 07:06:42 -0400 Message-Id: <20211102110740.215699-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::830; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x830.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently there are only two places that require we reset this value before exiting to the main loop, but that will change. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 3 ++- accel/tcg/user-exec.c | 2 -- 2 files changed, 2 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c9764c1325..bba4672632 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -462,6 +462,7 @@ void cpu_exec_step_atomic(CPUState *cpu) * memory. */ #ifndef CONFIG_SOFTMMU + clear_helper_retaddr(); tcg_debug_assert(!have_mmap_lock()); #endif if (qemu_mutex_iothread_locked()) { @@ -471,7 +472,6 @@ void cpu_exec_step_atomic(CPUState *cpu) qemu_plugin_disable_mem_helpers(cpu); } - /* * As we start the exclusive region before codegen we must still * be in the region if we longjump out of either the codegen or @@ -916,6 +916,7 @@ int cpu_exec(CPUState *cpu) #endif #ifndef CONFIG_SOFTMMU + clear_helper_retaddr(); tcg_debug_assert(!have_mmap_lock()); #endif if (qemu_mutex_iothread_locked()) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index c02d509ec6..3f3e793b7b 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -175,7 +175,6 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * currently executing TB was modified and must be exited * immediately. Clear helper_retaddr for next execution. */ - clear_helper_retaddr(); cpu_exit_tb_from_sighandler(cpu, old_set); /* NORETURN */ @@ -193,7 +192,6 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * an exception. Undo signal and retaddr state prior to longjmp. */ sigprocmask(SIG_SETMASK, old_set, NULL); - clear_helper_retaddr(); cc = CPU_GET_CLASS(cpu); cc->tcg_ops->tlb_fill(cpu, address, 0, access_type, From patchwork Tue Nov 2 11:06:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516634 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4403595iml; Tue, 2 Nov 2021 04:20:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyXWVum69hz46WJGdVyl3WfowTiSe4qARCXJz5JYvv2re1S+/Q3e8k0K3MSSanXakarzBFZ X-Received: by 2002:aca:3f87:: with SMTP id m129mr4433682oia.5.1635852011175; Tue, 02 Nov 2021 04:20:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852011; cv=none; d=google.com; s=arc-20160816; b=Z8lAm+Y9eNrGTrCrdOvZ6cqMu2GJcaW/Qpjx2FIUWfvS68uwH9g9+PvNpUPnDRDkEb w3BB29v4eY8N3QnPrRqTS8GsPTMRP6ipwX8v6/2W1Z3I2LjvzmmENtO3YJAh4wrJC8oM GavAPX2tyy9heAOEgf/xU0W4oBiZ9fvllw6YNGTDD52HUuyitWD0uCtwhXDfP9tXXHpr 4345SyGKDZ81ngLSEu+tAnyFkCfgtKoWc6s5dXMWhQ+WEHFsznKrNhFBS8fehdezlgoY hb6M5r1uV+M1Ky9PGPQbm1/EKOHXIu9mDebcuoFlfQDGDKp/q8c9cJqWNAfZdUtYfED8 Pj0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=shTlPwSm/VaKjDDgx3jqfEVE3VVxFJ7ui9L4q5qHESI=; b=XCbEivl3uCGPCFZwPDo0OQhq0fhVGzPa+lHqLMClsfKqgpMpsMTjY88iTnddIOK3Vu K6kI3BqwYtosrO8SCHLda4xL+EGRVlA3lSQD6qAFU/QEwGgcbsT85fbVfpT6QD8Cb1qB iyRhy6nTP9R2sltirZLcVc2BNrFNCrN2omAkSQk2JWhoRztibcqAJDrMLkWNPDjU6IyK PwyF1sq/5gj8SMLNDmkjNEouVxflpWzLHMCzYCMdcl1R4X5KGtgShh2naTlHmwwuxI8K rbVb75lK9vm9wOexFEXGhQq+cCFnDTKeE/P7UcGPRrx551YeRz53xy65kXHeIFxL8/E5 pHgw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rrOPzkRA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 03/60] accel/tcg: Split out handle_sigsegv_accerr_write Date: Tue, 2 Nov 2021 07:06:43 -0400 Message-Id: <20211102110740.215699-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the major portion of handle_cpu_signal which is specific to tcg, handling the page protections for the translations. Most of the rest will migrate to linux-user/ shortly. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Pass guest address to handle_sigsegv_accerr_write. --- include/exec/exec-all.h | 12 +++++ accel/tcg/user-exec.c | 101 ++++++++++++++++++++++++---------------- 2 files changed, 72 insertions(+), 41 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index e54f8e5d65..5f94d799aa 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -673,6 +673,18 @@ static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, */ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); +/** + * handle_sigsegv_accerr_write: + * @cpu: the cpu context + * @old_set: the sigset_t from the signal ucontext_t + * @host_pc: the host pc, adjusted for the signal + * @host_addr: the host address of the fault + * + * Return true if the write fault has been handled, and should be re-tried. + */ +bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, + uintptr_t host_pc, abi_ptr guest_addr); + /** * cpu_signal_handler * @signum: host signal number diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 3f3e793b7b..b83f8d12f4 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -114,6 +114,52 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write) return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; } +/** + * handle_sigsegv_accerr_write: + * @cpu: the cpu context + * @old_set: the sigset_t from the signal ucontext_t + * @host_pc: the host pc, adjusted for the signal + * @guest_addr: the guest address of the fault + * + * Return true if the write fault has been handled, and should be re-tried. + * + * Note that it is important that we don't call page_unprotect() unless + * this is really a "write to nonwriteable page" fault, because + * page_unprotect() assumes that if it is called for an access to + * a page that's writeable this means we had two threads racing and + * another thread got there first and already made the page writeable; + * so we will retry the access. If we were to call page_unprotect() + * for some other kind of fault that should really be passed to the + * guest, we'd end up in an infinite loop of retrying the faulting access. + */ +bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, + uintptr_t host_pc, abi_ptr guest_addr) +{ + switch (page_unprotect(guest_addr, host_pc)) { + case 0: + /* + * Fault not caused by a page marked unwritable to protect + * cached translations, must be the guest binary's problem. + */ + return false; + case 1: + /* + * Fault caused by protection of cached translation; TBs + * invalidated, so resume execution. + */ + return true; + case 2: + /* + * Fault caused by protection of cached translation, and the + * currently executing TB was modified and must be exited immediately. + */ + cpu_exit_tb_from_sighandler(cpu, old_set); + /* NORETURN */ + default: + g_assert_not_reached(); + } +} + /* * 'pc' is the host PC at which the exception was raised. * 'address' is the effective address of the memory exception. @@ -125,8 +171,9 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, { CPUState *cpu = current_cpu; CPUClass *cc; - unsigned long address = (unsigned long)info->si_addr; + unsigned long host_addr = (unsigned long)info->si_addr; MMUAccessType access_type = adjust_signal_pc(&pc, is_write); + abi_ptr guest_addr; /* For synchronous signals we expect to be coming from the vCPU * thread (so current_cpu should be valid) and either from running @@ -143,49 +190,21 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, #if defined(DEBUG_SIGNAL) printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", - pc, address, is_write, *(unsigned long *)old_set); + pc, host_addr, is_write, *(unsigned long *)old_set); #endif - /* XXX: locking issue */ - /* Note that it is important that we don't call page_unprotect() unless - * this is really a "write to nonwriteable page" fault, because - * page_unprotect() assumes that if it is called for an access to - * a page that's writeable this means we had two threads racing and - * another thread got there first and already made the page writeable; - * so we will retry the access. If we were to call page_unprotect() - * for some other kind of fault that should really be passed to the - * guest, we'd end up in an infinite loop of retrying the faulting - * access. - */ - if (is_write && info->si_signo == SIGSEGV && info->si_code == SEGV_ACCERR && - h2g_valid(address)) { - switch (page_unprotect(h2g(address), pc)) { - case 0: - /* Fault not caused by a page marked unwritable to protect - * cached translations, must be the guest binary's problem. - */ - break; - case 1: - /* Fault caused by protection of cached translation; TBs - * invalidated, so resume execution. Retain helper_retaddr - * for a possible second fault. - */ - return 1; - case 2: - /* Fault caused by protection of cached translation, and the - * currently executing TB was modified and must be exited - * immediately. Clear helper_retaddr for next execution. - */ - cpu_exit_tb_from_sighandler(cpu, old_set); - /* NORETURN */ - - default: - g_assert_not_reached(); - } - } /* Convert forcefully to guest address space, invalid addresses are still valid segv ones */ - address = h2g_nocheck(address); + guest_addr = h2g_nocheck(host_addr); + + /* XXX: locking issue */ + if (is_write && + info->si_signo == SIGSEGV && + info->si_code == SEGV_ACCERR && + h2g_valid(host_addr) && + handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) { + return 1; + } /* * There is no way the target can handle this other than raising @@ -194,7 +213,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, sigprocmask(SIG_SETMASK, old_set, NULL); cc = CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, address, 0, access_type, + cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, MMU_USER_IDX, false, pc); g_assert_not_reached(); } From patchwork Tue Nov 2 11:06:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516632 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4400243iml; Tue, 2 Nov 2021 04:16:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw59x+O6Cybx/8xHbJMdJiAg3xELdfZ1Vz8i0FvxuP/r56iJj0uBdswecj4UebetVcXJrtW X-Received: by 2002:a05:6808:3d2:: with SMTP id o18mr4243757oie.121.1635851806700; Tue, 02 Nov 2021 04:16:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635851806; cv=none; d=google.com; s=arc-20160816; b=UhqQ1agu9MnQmJMBnxmwNmVTXDKsgCk1buvfk4SWICIat1IWNH67xqP0Av66AbxGl0 DcG0vTh4gWI/Nuoco3Zb2ABgcujg6B3ocsroK2zxFAlpbtaD3v+i/KcO7a1fgkDXHAeH YUjrgJEc512MhXhmcetfhIxmftFh3PqYSbW8rOBklAzIXbG9xNlD6eV7Ss2HHVqnMwKm bwp92ztqhpwp7F3wf7VA0n8wHW/GcMRMELKbKkQ5pl/y4D+NtOysdlxpGJfxTPGHrpxk SI/FI54wnkH4XtqOUpDPjDvAXdjfg7rk09WD2V4GOVwSqh/RGCeeBgC+S64oPkHGIazI GsEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jNnLCcJOHvXqFRNx4ivHlyFLW3vo/pqpN29drgRbLjE=; b=iTDAYYGFf19x/zEsQgwldui0zSLHWXVEugnNBy6Ouhn/7wva4BVBLC08i9cebGvUYU yX6NMofbf/xIcdO0k5wOzQCtKv75myO7vZYcaA3noiXHSC1bPmS38ytTY90XR8XBEAC7 kn6IWGWM83SKdv+I57xfWJQaluTCpW1GxJ6BPIFXyCO2coYpoAng+ZX8b8BWn3PlBZSy 91a/Vu6tzy2rRjZEa63pW4kaqcC8ShsZ/vx31zdpDcX2ex03KEMoImJOaG0CekYIyZ9f QVsTvL9jszegOFj8YGD8gxYiodGsQkHC/FFcRmF8bdjJXmxTmLLYlUQoDpwq1u/AtS02 m/CA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yvYzfsni; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 04/60] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Date: Tue, 2 Nov 2021 07:06:44 -0400 Message-Id: <20211102110740.215699-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::836; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x836.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the comment about siglongjmp. We do use sigsetjmp in the main cpu loop, but we do not save the signal mask as most exits from the cpu loop do not require them. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index b83f8d12f4..b1183aa4b3 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -46,17 +46,6 @@ __thread uintptr_t helper_retaddr; //#define DEBUG_SIGNAL -/* exit the current TB from a signal handler. The host registers are - restored in a state compatible with the CPU emulator - */ -static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu, - sigset_t *old_set) -{ - /* XXX: use siglongjmp ? */ - sigprocmask(SIG_SETMASK, old_set, NULL); - cpu_loop_exit_noexc(cpu); -} - /* * Adjust the pc to pass to cpu_restore_state; return the memop type. */ @@ -153,7 +142,8 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, * Fault caused by protection of cached translation, and the * currently executing TB was modified and must be exited immediately. */ - cpu_exit_tb_from_sighandler(cpu, old_set); + sigprocmask(SIG_SETMASK, old_set, NULL); + cpu_loop_exit_noexc(cpu); /* NORETURN */ default: g_assert_not_reached(); From patchwork Tue Nov 2 11:06:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516641 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4407885iml; Tue, 2 Nov 2021 04:24:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxqmZ84y83FAD7/QiX0Nc484EctwIR3GL9CG7Ox9Q+1fqrEpfK2cdpEz0mWgsXIChvAidLd X-Received: by 2002:a9d:12c2:: with SMTP id g60mr538071otg.372.1635852287129; Tue, 02 Nov 2021 04:24:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852287; cv=none; d=google.com; s=arc-20160816; b=TmHz41U9LPWD8ev03QtgTdOj/C9Fgk+tC2EB+SQ/xeaEVXSR5rO4VTQbacfOCjSzSJ vK/9a9G8IBOr+tfPVBJxtVmpu2qYxZT9OLdunWGXnEaMdCnNp7Ya/PpTWha5aHrfJPyM B5DKFzXcXYZLz0VchDc8uVQbsCDwiTX806gd3bJKoxlCpxo2Wgq1JGjpH3SCCfENrs2r E7wDF0sCTkqz/wq+izcDVlXXJhQICzrl2fjrmfI0dZTa89jjNBq48ZsofQ6VMUR7tPMt 7TbB2YDeHvlM1uW24aNkJTRz1lolOMe0WSeTfvj7nynfJRGYDT/HYdsZmNWI+OG7nGYI UKeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dyOAbtDEe2hsdPtG2fphhVCPp8pp4Epcy5WbMT+mT+o=; b=DJTt2iQEDds3y4iAlYRRcGRDYcuTl2xNDtQM0bLADnWiJH08mb3DIOjcG96PpRM+DC RkCQtpgSPCKWF/SIQM8BZsgloAH7U70e8JxvH1gHtrGp+dFlAUeMZ598t6SbwgAGq2go mw+edK77syYq2HUXOS7yZlMfpiID7Js5p4mUz9rnrBWqUTF+GLX3HDEmGTkD4DGhAUEt FBeY+Azv5LN85zjejv87KrWec6lE3cCoig+1Y8A+mg53F0JIbPBYclRJSAZRKbwz5Mjl pNE+5rOmA/6OTScDYUC2YgSpszLvk4guX2KcGvUP5nwGwKbUONmX/X8mMwpEkRXRN31G 0CEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="ubnsuYS/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 05/60] configure: Merge riscv32 and riscv64 host architectures Date: Tue, 2 Nov 2021 07:06:45 -0400 Message-Id: <20211102110740.215699-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2a; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The existing code for safe-syscall.inc.S will compile without change for riscv32 and riscv64. We may also drop the meson.build stanza that merges them for tcg/. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- configure | 8 ++------ meson.build | 4 +--- linux-user/host/{riscv64 => riscv}/hostdep.h | 4 ++-- linux-user/host/riscv32/hostdep.h | 11 ----------- linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S | 0 5 files changed, 5 insertions(+), 22 deletions(-) rename linux-user/host/{riscv64 => riscv}/hostdep.h (94%) delete mode 100644 linux-user/host/riscv32/hostdep.h rename linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S (100%) -- 2.25.1 diff --git a/configure b/configure index 039467c04b..d57ad58342 100755 --- a/configure +++ b/configure @@ -570,11 +570,7 @@ elif check_define __s390__ ; then cpu="s390" fi elif check_define __riscv ; then - if check_define _LP64 ; then - cpu="riscv64" - else - cpu="riscv32" - fi + cpu="riscv" elif check_define __arm__ ; then cpu="arm" elif check_define __aarch64__ ; then @@ -587,7 +583,7 @@ ARCH= # Normalise host CPU name and set ARCH. # Note that this case should only have supported host CPUs, not guests. case "$cpu" in - ppc|ppc64|s390x|sparc64|x32|riscv32|riscv64) + ppc|ppc64|s390x|sparc64|x32|riscv) ;; ppc64le) ARCH="ppc64" diff --git a/meson.build b/meson.build index 2c5b53cbe2..90e3e85f20 100644 --- a/meson.build +++ b/meson.build @@ -55,7 +55,7 @@ have_block = have_system or have_tools python = import('python').find_installation() supported_oses = ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', 'sunos', 'linux'] -supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', 'x86_64', +supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64', 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] cpu = host_machine.cpu_family() @@ -351,8 +351,6 @@ if not get_option('tcg').disabled() tcg_arch = 'i386' elif config_host['ARCH'] == 'ppc64' tcg_arch = 'ppc' - elif config_host['ARCH'] in ['riscv32', 'riscv64'] - tcg_arch = 'riscv' endif add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' / tcg_arch, language: ['c', 'cpp', 'objc']) diff --git a/linux-user/host/riscv64/hostdep.h b/linux-user/host/riscv/hostdep.h similarity index 94% rename from linux-user/host/riscv64/hostdep.h rename to linux-user/host/riscv/hostdep.h index 865f0fb9ff..2ba07456ae 100644 --- a/linux-user/host/riscv64/hostdep.h +++ b/linux-user/host/riscv/hostdep.h @@ -5,8 +5,8 @@ * See the COPYING file in the top-level directory. */ -#ifndef RISCV64_HOSTDEP_H -#define RISCV64_HOSTDEP_H +#ifndef RISCV_HOSTDEP_H +#define RISCV_HOSTDEP_H /* We have a safe-syscall.inc.S */ #define HAVE_SAFE_SYSCALL diff --git a/linux-user/host/riscv32/hostdep.h b/linux-user/host/riscv32/hostdep.h deleted file mode 100644 index adf9edbf2d..0000000000 --- a/linux-user/host/riscv32/hostdep.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef RISCV32_HOSTDEP_H -#define RISCV32_HOSTDEP_H - -#endif diff --git a/linux-user/host/riscv64/safe-syscall.inc.S b/linux-user/host/riscv/safe-syscall.inc.S similarity index 100% rename from linux-user/host/riscv64/safe-syscall.inc.S rename to linux-user/host/riscv/safe-syscall.inc.S From patchwork Tue Nov 2 11:06:46 2021 Content-Type: text/plain; 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 06/60] linux-user: Reorg handling for SIGSEGV Date: Tue, 2 Nov 2021 07:06:46 -0400 Message-Id: <20211102110740.215699-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82b; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add stub host-signal.h for all linux-user hosts. Add new code replacing cpu_signal_handler. Full migration will happen one host at a time. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 1 + linux-user/host/arm/host-signal.h | 1 + linux-user/host/i386/host-signal.h | 1 + linux-user/host/mips/host-signal.h | 1 + linux-user/host/ppc/host-signal.h | 1 + linux-user/host/ppc64/host-signal.h | 1 + linux-user/host/riscv/host-signal.h | 1 + linux-user/host/s390/host-signal.h | 1 + linux-user/host/s390x/host-signal.h | 1 + linux-user/host/sparc/host-signal.h | 1 + linux-user/host/sparc64/host-signal.h | 1 + linux-user/host/x32/host-signal.h | 1 + linux-user/host/x86_64/host-signal.h | 1 + linux-user/signal.c | 109 ++++++++++++++++++++++---- 14 files changed, 106 insertions(+), 16 deletions(-) create mode 100644 linux-user/host/aarch64/host-signal.h create mode 100644 linux-user/host/arm/host-signal.h create mode 100644 linux-user/host/i386/host-signal.h create mode 100644 linux-user/host/mips/host-signal.h create mode 100644 linux-user/host/ppc/host-signal.h create mode 100644 linux-user/host/ppc64/host-signal.h create mode 100644 linux-user/host/riscv/host-signal.h create mode 100644 linux-user/host/s390/host-signal.h create mode 100644 linux-user/host/s390x/host-signal.h create mode 100644 linux-user/host/sparc/host-signal.h create mode 100644 linux-user/host/sparc64/host-signal.h create mode 100644 linux-user/host/x32/host-signal.h create mode 100644 linux-user/host/x86_64/host-signal.h -- 2.25.1 diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch64/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/aarch64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/arm/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/i386/host-signal.h b/linux-user/host/i386/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/i386/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/mips/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/ppc/host-signal.h b/linux-user/host/ppc/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/ppc/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/ppc64/host-signal.h b/linux-user/host/ppc64/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/ppc64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/riscv/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/s390/host-signal.h b/linux-user/host/s390/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/s390/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/s390x/host-signal.h b/linux-user/host/s390x/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/s390x/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/sparc/host-signal.h b/linux-user/host/sparc/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/sparc/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/sparc64/host-signal.h b/linux-user/host/sparc64/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/sparc64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/x32/host-signal.h b/linux-user/host/x32/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/x32/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/x86_64/host-signal.h b/linux-user/host/x86_64/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/x86_64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/signal.c b/linux-user/signal.c index 14d8fdfde1..6900acb122 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/bitops.h" #include "exec/gdbstub.h" +#include "hw/core/tcg-cpu-ops.h" #include #include @@ -29,6 +30,7 @@ #include "loader.h" #include "trace.h" #include "signal-common.h" +#include "host-signal.h" static struct target_sigaction sigact_table[TARGET_NSIG]; @@ -769,41 +771,116 @@ static inline void rewind_if_in_safe_syscall(void *puc) } #endif -static void host_signal_handler(int host_signum, siginfo_t *info, - void *puc) +static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) { CPUArchState *env = thread_cpu->env_ptr; CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; - - int sig; target_siginfo_t tinfo; ucontext_t *uc = puc; struct emulated_sigtable *k; + int guest_sig; +#ifdef HOST_SIGNAL_PLACEHOLDER /* the CPU emulator uses some host signals to detect exceptions, we forward to it some signals */ - if ((host_signum == SIGSEGV || host_signum == SIGBUS) + if ((host_sig == SIGSEGV || host_sig == SIGBUS) && info->si_code > 0) { - if (cpu_signal_handler(host_signum, info, puc)) + if (cpu_signal_handler(host_sig, info, puc)) { return; + } } +#else + uintptr_t pc = 0; + bool sync_sig = false; + + /* + * Non-spoofed SIGSEGV and SIGBUS are synchronous, and need special + * handling wrt signal blocking and unwinding. + */ + if ((host_sig == SIGSEGV || host_sig == SIGBUS) && info->si_code > 0) { + MMUAccessType access_type; + uintptr_t host_addr; + abi_ptr guest_addr; + bool is_write; + + host_addr = (uintptr_t)info->si_addr; + + /* + * Convert forcefully to guest address space: addresses outside + * reserved_va are still valid to report via SEGV_MAPERR. + */ + guest_addr = h2g_nocheck(host_addr); + + pc = host_signal_pc(uc); + is_write = host_signal_write(info, uc); + access_type = adjust_signal_pc(&pc, is_write); + + if (host_sig == SIGSEGV) { + const struct TCGCPUOps *tcg_ops; + + if (info->si_code == SEGV_ACCERR && h2g_valid(host_addr)) { + /* If this was a write to a TB protected page, restart. */ + if (is_write && + handle_sigsegv_accerr_write(cpu, &uc->uc_sigmask, + pc, guest_addr)) { + return; + } + + /* + * With reserved_va, the whole address space is PROT_NONE, + * which means that we may get ACCERR when we want MAPERR. + */ + if (page_get_flags(guest_addr) & PAGE_VALID) { + /* maperr = false; */ + } else { + info->si_code = SEGV_MAPERR; + } + } + + sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + + tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, + MMU_USER_IDX, false, pc); + g_assert_not_reached(); + } else { + sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + } + + sync_sig = true; + } +#endif /* get target signal number */ - sig = host_to_target_signal(host_signum); - if (sig < 1 || sig > TARGET_NSIG) + guest_sig = host_to_target_signal(host_sig); + if (guest_sig < 1 || guest_sig > TARGET_NSIG) { return; - trace_user_host_signal(env, host_signum, sig); + } + trace_user_host_signal(env, host_sig, guest_sig); + + host_to_target_siginfo_noswap(&tinfo, info); + k = &ts->sigtab[guest_sig - 1]; + k->info = tinfo; + k->pending = guest_sig; + ts->signal_pending = 1; + +#ifndef HOST_SIGNAL_PLACEHOLDER + /* + * For synchronous signals, unwind the cpu state to the faulting + * insn and then exit back to the main loop so that the signal + * is delivered immediately. + */ + if (sync_sig) { + cpu->exception_index = EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, pc); + } +#endif rewind_if_in_safe_syscall(puc); - host_to_target_siginfo_noswap(&tinfo, info); - k = &ts->sigtab[sig - 1]; - k->info = tinfo; - k->pending = sig; - ts->signal_pending = 1; - - /* Block host signals until target signal handler entered. We + /* + * Block host signals until target signal handler entered. We * can't block SIGSEGV or SIGBUS while we're executing guest * code in case the guest code provokes one in the window between * now and it getting out to the main loop. Signals will be From patchwork Tue Nov 2 11:06:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516636 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4403709iml; Tue, 2 Nov 2021 04:20:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw5801/0D+4XrEhcMliST+eIyTEHU5i8Fn9pRpB5Qt74Vlvntb/YTprpg2lm1J/qOSMbvkZ X-Received: by 2002:a9d:63c3:: with SMTP id e3mr26993686otl.220.1635852017775; Tue, 02 Nov 2021 04:20:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852017; cv=none; d=google.com; s=arc-20160816; b=ykRHq8/qk6KU7xDpiM3nweE7NUtFfgF00sjZ1yM9i5Iv1A+xmWcUmnwpUxwE+RZtcY QJgE+NUII3HJQMXT2yB3/KyHY/Uqkh4FjAfH0FQrbn2yKNxSx3hOykKf6jMjDMxucs/L r+OFsMEhzG9FEkryzbbZVAemYOZ7Pi+0VdfcdJO/YK+hAaSdjhgobYb0T5IgG+WdoQH+ 6xrbhCunwlJ+AslzU+7/v5BkSJ3Q7kvspkvD6YDG56Plpj3YF0ci+5kVmQeTd5WDTF/O 7mZrKg4w5qH9N7v+Nax6yR9PJ5Lvcq1TPfXej8rSXF35Z6sC98OohOxzcXNeSXe9YTsD s8/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RSgMMIuxwm2GRlSM3OSJ89oURZNxoJr58EWEVCgv90k=; b=OcuPgXc3ypXPy57dhJBbT3Io1zjKN0KiJgfBKxV6CygQTPSYXVikCpljIEiY8ikHRH HMdfZaupPUpPewOgVImx7LYSUh3D/ACFf/kPnUBA2bZ60kn/Z1AaY0vjRYG+t9N6P1WB ClCBVjj79DZtr6z76hU6AtOXdqmNNjgibqX4kMAT5vY9hGrmQGRBllxWjXSs9jdCHT0d r1owh7fXhkdlsvD7VDb493DJHwmhe78m7hQxzaHgsV7UlOxi7H699bI6eMLVSIEP6oaP Wft8MzUrw3irfzuTRM7fDaCyEli3tJabsU+M3GYdWrBga2S16npSo6MTZr4G31Q/X3y/ bzOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dyTIrLB+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 07/60] linux-user/host/x86: Populate host_signal.h Date: Tue, 2 Nov 2021 07:06:47 -0400 Message-Id: <20211102110740.215699-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f36; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- linux-user/host/i386/host-signal.h | 26 ++++- linux-user/host/x32/host-signal.h | 2 +- linux-user/host/x86_64/host-signal.h | 25 ++++- accel/tcg/user-exec.c | 136 +-------------------------- 4 files changed, 51 insertions(+), 138 deletions(-) -- 2.25.1 diff --git a/linux-user/host/i386/host-signal.h b/linux-user/host/i386/host-signal.h index f4b4d65031..4c8eef99ce 100644 --- a/linux-user/host/i386/host-signal.h +++ b/linux-user/host/i386/host-signal.h @@ -1 +1,25 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU LGPL, version 2.1 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef I386_HOST_SIGNAL_H +#define I386_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_EIP]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe + && (uc->uc_mcontext.gregs[REG_ERR] & 0x2); +} + +#endif diff --git a/linux-user/host/x32/host-signal.h b/linux-user/host/x32/host-signal.h index f4b4d65031..26800591d3 100644 --- a/linux-user/host/x32/host-signal.h +++ b/linux-user/host/x32/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../x86_64/host-signal.h" diff --git a/linux-user/host/x86_64/host-signal.h b/linux-user/host/x86_64/host-signal.h index f4b4d65031..883d2fcf65 100644 --- a/linux-user/host/x86_64/host-signal.h +++ b/linux-user/host/x86_64/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef X86_64_HOST_SIGNAL_H +#define X86_64_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_RIP]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe + && (uc->uc_mcontext.gregs[REG_ERR] & 0x2); +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index b1183aa4b3..b121e6c2e9 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -29,19 +29,6 @@ #include "trace/trace-root.h" #include "internal.h" -#undef EAX -#undef ECX -#undef EDX -#undef EBX -#undef ESP -#undef EBP -#undef ESI -#undef EDI -#undef EIP -#ifdef __linux__ -#include -#endif - __thread uintptr_t helper_retaddr; //#define DEBUG_SIGNAL @@ -266,123 +253,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__i386__) - -#if defined(__NetBSD__) -#include -#include - -#define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__FreeBSD__) || defined(__DragonFly__) -#include -#include - -#define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip)) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) -#define ERROR_sig(context) ((context)->uc_mcontext.mc_err) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__OpenBSD__) -#include -#define EIP_sig(context) ((context)->sc_eip) -#define TRAP_sig(context) ((context)->sc_trapno) -#define ERROR_sig(context) ((context)->sc_err) -#define MASK_sig(context) ((context)->sc_mask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#else -#define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP 0xe -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; -#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) - ucontext_t *uc = puc; -#elif defined(__OpenBSD__) - struct sigcontext *uc = puc; -#else - ucontext_t *uc = puc; -#endif - unsigned long pc; - int trapno; - -#ifndef REG_EIP -/* for glibc 2.1 */ -#define REG_EIP EIP -#define REG_ERR ERR -#define REG_TRAPNO TRAPNO -#endif - pc = EIP_sig(uc); - trapno = TRAP_sig(uc); - return handle_cpu_signal(pc, info, - trapno == PAGE_FAULT_TRAP ? - (ERROR_sig(uc) >> 1) & 1 : 0, - &MASK_sig(uc)); -} - -#elif defined(__x86_64__) - -#ifdef __NetBSD__ -#include -#define PC_sig(context) _UC_MACHINE_PC(context) -#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__OpenBSD__) -#include -#define PC_sig(context) ((context)->sc_rip) -#define TRAP_sig(context) ((context)->sc_trapno) -#define ERROR_sig(context) ((context)->sc_err) -#define MASK_sig(context) ((context)->sc_mask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__FreeBSD__) || defined(__DragonFly__) -#include -#include - -#define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip)) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) -#define ERROR_sig(context) ((context)->uc_mcontext.mc_err) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#else -#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP 0xe -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - unsigned long pc; -#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) - ucontext_t *uc = puc; -#elif defined(__OpenBSD__) - struct sigcontext *uc = puc; -#else - ucontext_t *uc = puc; -#endif - - pc = PC_sig(uc); - return handle_cpu_signal(pc, info, - TRAP_sig(uc) == PAGE_FAULT_TRAP ? - (ERROR_sig(uc) >> 1) & 1 : 0, - &MASK_sig(uc)); -} - -#elif defined(_ARCH_PPC) +#if defined(_ARCH_PPC) /*********************************************************************** * signal context platform-specific definitions @@ -893,11 +764,6 @@ int cpu_signal_handler(int host_signum, void *pinfo, return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } - -#else - -#error host CPU specific signal handler needed - #endif /* The softmmu versions of these helpers are in cputlb.c. */ From patchwork Tue Nov 2 11:06:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516639 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4407036iml; Tue, 2 Nov 2021 04:23:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyVdyo60EcZ84c2px0JhfLTX5fvrkNpbK17naFM8KMNiMuWe3TXzeWpsmZ8uwWg73d48LGi X-Received: by 2002:a05:6808:238f:: with SMTP id bp15mr4707399oib.30.1635852232848; Tue, 02 Nov 2021 04:23:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852232; cv=none; d=google.com; s=arc-20160816; b=uV2Pumys5FS1LuF+waXgaM5DknTBGUh5MM7K8pBleMFlULuIaRGjwYpDPDB9yCbekc EBaVy9pG2g8YN8YjKGPDcv2fJK53Pc+2ycV8M8YiGP90LpTjsNpT2mXTHvXh82lpY38g KbDn17x2QnlubaetAF5fFsdtKYoOPg2MSnzRh8mixCvsVdPU+H5Y6re3vnj9uGh+8p5E OKpfTKu6k4RRJyTf0RbgqTsbk0Klz1d3agOsE1RT4J0uWPzDQoqHVYIJV/JyznouZEuA ngExh4KttU0C3mKqbIAuDgrSzRcHjxA6P9Z9ZsUILeNEhVgPO1oMMcouOKz3YBJ0ng/r TgUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8/7KXVD3zq87x6TOe7PU4RK3OGzoSoejAMrm7z+tUkk=; b=C4XGIuQV2jq7MP8l3q3lKodbVBxfHbxBbs2RX96aQEQLAwrr2TeDxIm26PzdwqFsMi d0ofefGQDhx45zDDCS7nleNqKBOyOcOHbbdjeff6CJNQZ7UXM1ENKfChLxkmyA6pkmlu s06OksNVvflSV029wnAFfpiEIIhvpr1GFwjmMOMWWVtqCx+ObqkpeHZWTCP/iuZDQG+R W+IvZ8IbDP2MKQ4jR6uAMT7F11DYdUmpWrxLrJHTC1LGXADv1AuBuqhi9/IPd4Ic/jHK i8WrYRisXOg0jKSrq6bzeyPe7zmRjvN5NncN18pxu+4/TxRAOwk2fxLtoNnvPsjFLJsZ lJlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aEJ791Nd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 08/60] linux-user/host/ppc: Populate host_signal.h Date: Tue, 2 Nov 2021 07:06:48 -0400 Message-Id: <20211102110740.215699-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::736; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x736.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- linux-user/host/ppc/host-signal.h | 26 +++++++++- linux-user/host/ppc64/host-signal.h | 2 +- accel/tcg/user-exec.c | 79 +---------------------------- 3 files changed, 27 insertions(+), 80 deletions(-) -- 2.25.1 diff --git a/linux-user/host/ppc/host-signal.h b/linux-user/host/ppc/host-signal.h index f4b4d65031..a491c413dc 100644 --- a/linux-user/host/ppc/host-signal.h +++ b/linux-user/host/ppc/host-signal.h @@ -1 +1,25 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU LGPL, version 2.1 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef PPC_HOST_SIGNAL_H +#define PPC_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.regs->nip; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.regs->trap != 0x400 + && (uc->uc_mcontext.regs->dsisr & 0x02000000); +} + +#endif diff --git a/linux-user/host/ppc64/host-signal.h b/linux-user/host/ppc64/host-signal.h index f4b4d65031..a353c22a90 100644 --- a/linux-user/host/ppc64/host-signal.h +++ b/linux-user/host/ppc64/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../ppc/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index b121e6c2e9..5a0a65fa46 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -253,84 +253,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(_ARCH_PPC) - -/*********************************************************************** - * signal context platform-specific definitions - * From Wine - */ -#ifdef linux -/* All Registers access - only for local access */ -#define REG_sig(reg_name, context) \ - ((context)->uc_mcontext.regs->reg_name) -/* Gpr Registers access */ -#define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) -/* Program counter */ -#define IAR_sig(context) REG_sig(nip, context) -/* Machine State Register (Supervisor) */ -#define MSR_sig(context) REG_sig(msr, context) -/* Count register */ -#define CTR_sig(context) REG_sig(ctr, context) -/* User's integer exception register */ -#define XER_sig(context) REG_sig(xer, context) -/* Link register */ -#define LR_sig(context) REG_sig(link, context) -/* Condition register */ -#define CR_sig(context) REG_sig(ccr, context) - -/* Float Registers access */ -#define FLOAT_sig(reg_num, context) \ - (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num]) -#define FPSCR_sig(context) \ - (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4))) -/* Exception Registers access */ -#define DAR_sig(context) REG_sig(dar, context) -#define DSISR_sig(context) REG_sig(dsisr, context) -#define TRAP_sig(context) REG_sig(trap, context) -#endif /* linux */ - -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) -#include -#define IAR_sig(context) ((context)->uc_mcontext.mc_srr0) -#define MSR_sig(context) ((context)->uc_mcontext.mc_srr1) -#define CTR_sig(context) ((context)->uc_mcontext.mc_ctr) -#define XER_sig(context) ((context)->uc_mcontext.mc_xer) -#define LR_sig(context) ((context)->uc_mcontext.mc_lr) -#define CR_sig(context) ((context)->uc_mcontext.mc_cr) -/* Exception Registers access */ -#define DAR_sig(context) ((context)->uc_mcontext.mc_dar) -#define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_exc) -#endif /* __FreeBSD__|| __FreeBSD_kernel__ */ - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) - ucontext_t *uc = puc; -#else - ucontext_t *uc = puc; -#endif - unsigned long pc; - int is_write; - - pc = IAR_sig(uc); - is_write = 0; -#if 0 - /* ppc 4xx case */ - if (DSISR_sig(uc) & 0x00800000) { - is_write = 1; - } -#else - if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) { - is_write = 1; - } -#endif - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__alpha__) +#if defined(__alpha__) int cpu_signal_handler(int host_signum, void *pinfo, void *puc) From patchwork Tue Nov 2 11:06:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516647 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4411931iml; Tue, 2 Nov 2021 04:29:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxu/NeAewIIskk3rLMgo8huYtX8Ne6e+Zeh7CtSKgn2YFILUxVDfn8z4Rd6KN7ZRkMusNE1 X-Received: by 2002:aca:783:: with SMTP id 125mr4620548oih.29.1635852550311; Tue, 02 Nov 2021 04:29:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852550; cv=none; d=google.com; s=arc-20160816; b=fT026TV2XM7+JSZSmpiM5yJoaFGbUDfzYjO7V4GKheSMpK9GHKsN2uhOYBuxbnir5m XbtRvoTERJOSDOZtPVoxbWAxmsco9aFITq6pncAH9BH5ZzS1cAwW5r4ZUIOYr7uXPuJ/ rQbjL5VhAYwv0Ku3DFvAkQeZO1FjKucl+cNUqYPvsWxyVEAOdR6o3vBg+HFGdAMyV1+A xnJp6wLypMFI+9H9ZUjk+NVUyJmFNAXsCACMDxIlZcZAjm4jhaspIqXFXXlUByQI1QdJ R9VbdR/2rp48jeWOETGTjTdJ9KVWDc7qk2/058oySl1eW5rdYdTL03/ijt/3guHhqMnG JsPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Xi5Xc/by+fXO9rb16n3Qpt44Vj6KLnw5qZ8SYUB9TCU=; b=p3yGql4p/rq1zjxcTa3yi6nt5HsZPzF9v2ivVyftO21ebfQX+bNtxsusUqQ6q3ni4E cBnbtZrIzNoxUf2YAfg7ZaObrtnz84SUsSJAf0D8+6EmQfcJzOPPiodkGPMkbnEb6Gkk RLPh4gOzH/4IfjaGXfLYjv+rYMuomjhHuC5pRaEDzA6ablKT83Q+PplwW9rTUfw+AIiH L/Nrig7BYm8+WYyJ3SEVKzk9ZJjQer2X08nUAATAbPlXU/8B2Xi11cHmqLz62JMC30yC Z2+S4p5ijZ9Z9LuAUusNKlv6OYFoQn1FkLoFlOolVKSXGr1wKB7G13JO5Ju4T9Au27Om k/YA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QQrtI7EZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 09/60] linux-user/host/alpha: Populate host_signal.h Date: Tue, 2 Nov 2021 07:06:49 -0400 Message-Id: <20211102110740.215699-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82b; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/alpha/host-signal.h | 42 +++++++++++++++++++++++++++++ accel/tcg/user-exec.c | 31 +-------------------- 2 files changed, 43 insertions(+), 30 deletions(-) create mode 100644 linux-user/host/alpha/host-signal.h -- 2.25.1 diff --git a/linux-user/host/alpha/host-signal.h b/linux-user/host/alpha/host-signal.h new file mode 100644 index 0000000000..e080be412f --- /dev/null +++ b/linux-user/host/alpha/host-signal.h @@ -0,0 +1,42 @@ +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU LGPL, version 2.1 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef ALPHA_HOST_SIGNAL_H +#define ALPHA_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.sc_pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t *pc = (uint32_t *)host_signal_pc(uc); + uint32_t insn = *pc; + + /* XXX: need kernel patch to get write flag faster */ + switch (insn >> 26) { + case 0x0d: /* stw */ + case 0x0e: /* stb */ + case 0x0f: /* stq_u */ + case 0x24: /* stf */ + case 0x25: /* stg */ + case 0x26: /* sts */ + case 0x27: /* stt */ + case 0x2c: /* stl */ + case 0x2d: /* stq */ + case 0x2e: /* stl_c */ + case 0x2f: /* stq_c */ + return true; + } + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5a0a65fa46..e9b6eb696f 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -253,36 +253,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__alpha__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - uint32_t *pc = uc->uc_mcontext.sc_pc; - uint32_t insn = *pc; - int is_write = 0; - - /* XXX: need kernel patch to get write flag faster */ - switch (insn >> 26) { - case 0x0d: /* stw */ - case 0x0e: /* stb */ - case 0x0f: /* stq_u */ - case 0x24: /* stf */ - case 0x25: /* stg */ - case 0x26: /* sts */ - case 0x27: /* stt */ - case 0x2c: /* stl */ - case 0x2d: /* stq */ - case 0x2e: /* stl_c */ - case 0x2f: /* stq_c */ - is_write = 1; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#elif defined(__sparc__) +#if defined(__sparc__) int cpu_signal_handler(int host_signum, void *pinfo, void *puc) From patchwork Tue Nov 2 11:06:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516640 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4407757iml; Tue, 2 Nov 2021 04:24:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwk0AKnd8S+/FwbZdt+JlP1rb+zU+WU++6yKXlsw1zrKFlbHm2q7JHfsrMwnGF3H7NpNAAR X-Received: by 2002:a9d:34c:: with SMTP id 70mr19776018otv.89.1635852279864; Tue, 02 Nov 2021 04:24:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852279; cv=none; d=google.com; s=arc-20160816; b=DDF/khR/IFjrl76va8Vx7jg1OGQnTIR1hQP7XXoIfeSQY0WOAQaef0nJBsJ7JjtfFr 5zZSQsEStAkc9TKk2aEqEz90aemgAkkRpAAPJtLzfjlJboT12WQvXmfCJ0umHlzGDZJg J3bSRCHaeyXoqk1lf6H6PlU0IoTyOK5NBv8VqTpGnIU9cxAgiO2s1sxKW7hFgcc1Ueg6 02nLJ4nzaf9dcSVr2TsANkaU8+ikUQjsTN1y6kx31wcA51Bu+GACJBRv3SD0F+b/fsIc MbYlTrxt2ygUg7Qhajltw0xmW+Lw4UHr8ALBWGDgMoYrvo4QJgRGCnWIANsZOsKtOfU/ 3YCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=09EXkfsXIChlE/LXOeHg30UK63IRh0uoWnU1yPu4O3s=; b=s4P1OALmzZ6EZpe2zY4UDB4J4PapuU+wdGBUxuK+dvYKaoz/s3WIOXucaeGS66sh6i /PPhp4toor03UEb0YQInfcRphYetNzV/1SRjhBHXv8Uc65lwE9PSzwbntPmA2XaMfPjV 4PATYz12htynbBdacJeFE+eAWPkLU1QSmB1joKByHq3t+Lapd7SN11CdxTiJOUHFl+M0 bztlIq7LM7twXh0XZYq7eXnUlBFPN3Pgzl6Iu/CSD5MVOZx56MHgQT2946nyO7PJZbNy uxxA8B5hGRR2IE/iJPreKHm4sb3AsvinRBiRyiqspILRKuWzxWtGqkpkD/7PpPTmB3T0 qLpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yv8JHmYl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 10/60] linux-user/host/sparc: Populate host_signal.h Date: Tue, 2 Nov 2021 07:06:50 -0400 Message-Id: <20211102110740.215699-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::730; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x730.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Drop the Solaris code as completely unused. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- linux-user/host/sparc/host-signal.h | 55 +++++++++++++++++++++++- linux-user/host/sparc64/host-signal.h | 2 +- accel/tcg/user-exec.c | 62 +-------------------------- 3 files changed, 56 insertions(+), 63 deletions(-) -- 2.25.1 diff --git a/linux-user/host/sparc/host-signal.h b/linux-user/host/sparc/host-signal.h index f4b4d65031..5e71d33f8e 100644 --- a/linux-user/host/sparc/host-signal.h +++ b/linux-user/host/sparc/host-signal.h @@ -1 +1,54 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU LGPL, version 2.1 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef SPARC_HOST_SIGNAL_H +#define SPARC_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ +#ifdef __arch64__ + return uc->uc_mcontext.mc_gregs[MC_PC]; +#else + return uc->uc_mcontext.gregs[REG_PC]; +#endif +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn = *(uint32_t *)host_signal_pc(uc); + + if ((insn >> 30) == 3) { + switch ((insn >> 19) & 0x3f) { + case 0x05: /* stb */ + case 0x15: /* stba */ + case 0x06: /* sth */ + case 0x16: /* stha */ + case 0x04: /* st */ + case 0x14: /* sta */ + case 0x07: /* std */ + case 0x17: /* stda */ + case 0x0e: /* stx */ + case 0x1e: /* stxa */ + case 0x24: /* stf */ + case 0x34: /* stfa */ + case 0x27: /* stdf */ + case 0x37: /* stdfa */ + case 0x26: /* stqf */ + case 0x36: /* stqfa */ + case 0x25: /* stfsr */ + case 0x3c: /* casa */ + case 0x3e: /* casxa */ + return true; + } + } + return false; +} + +#endif diff --git a/linux-user/host/sparc64/host-signal.h b/linux-user/host/sparc64/host-signal.h index f4b4d65031..1191fe2d40 100644 --- a/linux-user/host/sparc64/host-signal.h +++ b/linux-user/host/sparc64/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../sparc/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e9b6eb696f..694eff7f04 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -253,67 +253,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__sparc__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - int is_write; - uint32_t insn; -#if !defined(__arch64__) || defined(CONFIG_SOLARIS) - uint32_t *regs = (uint32_t *)(info + 1); - void *sigmask = (regs + 20); - /* XXX: is there a standard glibc define ? */ - unsigned long pc = regs[1]; -#else -#ifdef __linux__ - struct sigcontext *sc = puc; - unsigned long pc = sc->sigc_regs.tpc; - void *sigmask = (void *)sc->sigc_mask; -#elif defined(__OpenBSD__) - struct sigcontext *uc = puc; - unsigned long pc = uc->sc_pc; - void *sigmask = (void *)(long)uc->sc_mask; -#elif defined(__NetBSD__) - ucontext_t *uc = puc; - unsigned long pc = _UC_MACHINE_PC(uc); - void *sigmask = (void *)&uc->uc_sigmask; -#endif -#endif - - /* XXX: need kernel patch to get write flag faster */ - is_write = 0; - insn = *(uint32_t *)pc; - if ((insn >> 30) == 3) { - switch ((insn >> 19) & 0x3f) { - case 0x05: /* stb */ - case 0x15: /* stba */ - case 0x06: /* sth */ - case 0x16: /* stha */ - case 0x04: /* st */ - case 0x14: /* sta */ - case 0x07: /* std */ - case 0x17: /* stda */ - case 0x0e: /* stx */ - case 0x1e: /* stxa */ - case 0x24: /* stf */ - case 0x34: /* stfa */ - case 0x27: /* stdf */ - case 0x37: /* stdfa */ - case 0x26: /* stqf */ - case 0x36: /* stqfa */ - case 0x25: /* stfsr */ - case 0x3c: /* casa */ - case 0x3e: /* casxa */ - is_write = 1; - break; - } - } - return handle_cpu_signal(pc, info, is_write, sigmask); -} - -#elif defined(__arm__) +#if defined(__arm__) #if defined(__NetBSD__) #include From patchwork Tue Nov 2 11:06:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516643 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4409683iml; Tue, 2 Nov 2021 04:26:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyasbWktLHMz0xJJKUkY8IsGBgNnspJ8lwbvxbdKLB2AXKpG8/IpW7iv2svCzp4+2131bGZ X-Received: by 2002:a9d:6e8d:: with SMTP id a13mr25988276otr.181.1635852406159; Tue, 02 Nov 2021 04:26:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852406; cv=none; d=google.com; s=arc-20160816; b=y/nJfCQq++HqgI9d+YROygoq46HCsG2eZZkKGQuWVvUbi+qWfqKviaX1AWurFYKXel wmJpziswhaR/OXwnZzEepyu/zR8Z8NicNsaRm9Vtgt5z0uHY5Pb/Sho4jl4IReuircUp z56xr4CEsFUpNskhRKGx2ytE8j4iTV9YgOH2eYxHjgBNP4PQC8I1S2uHzkyS8dTPgykj WMXJ8nc1Y/FQvcqj9gei24xVcyhx74fn9Hya2IOf2HM7sON6FYODSSZwtQQsQyWVJMIu IdBGkGAeHT3CaFObph1lMYhYCBUUPikQXm+D9dtiWAODD/JyK5oinx3vFtewe9gKmUDe Ve0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4j+5GOHH9i6aEZjBZv3rJ6b7IG39UFn9wARHFg8XAtc=; b=YohmBo0ruBDfCiPUdqEPFs89L53ggJVU8DIELGSIv7Zsmag94PNUzxYm4MMb4pkIvd ejh5DQes2EaWtFWeatSb6HeBbyjiN+B7yBSe82mX/C5RKAYdXSchVUEL9CIXhDEfr5/G KVCMwh2UAzaMjkU8zoee4rM4A8G1udq38UXCBNM0VKJKwP//+469TPM1IJt03Pk5WoQv 68BmnSJX5H4SzYrEmXJ9wzzmkxUdxA1X4K2+uOCw4B71Vys7F5sQdJ/U+px3egXdFBcs 2cGGP3385Bu+woMghML9wD9pl6Yyq4pFf64UvDJAL+qbic1iwI3stIlqLjnNTnKuUtUH uwAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=uVdB7wPN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 11/60] linux-user/host/arm: Populate host_signal.h Date: Tue, 2 Nov 2021 07:06:51 -0400 Message-Id: <20211102110740.215699-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f36; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/arm/host-signal.h | 31 ++++++++++++++++++++- accel/tcg/user-exec.c | 45 +------------------------------ 2 files changed, 31 insertions(+), 45 deletions(-) -- 2.25.1 diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-signal.h index f4b4d65031..efb165c0c5 100644 --- a/linux-user/host/arm/host-signal.h +++ b/linux-user/host/arm/host-signal.h @@ -1 +1,30 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU LGPL, version 2.1 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef ARM_HOST_SIGNAL_H +#define ARM_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.arm_pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + /* + * In the FSR, bit 11 is WnR, assuming a v6 or + * later processor. On v5 we will always report + * this as a read, which will fail later. + */ + uint32_t fsr = uc->uc_mcontext.error_code; + return extract32(fsr, 11, 1); +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 694eff7f04..fabc8855a9 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -253,50 +253,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__arm__) - -#if defined(__NetBSD__) -#include -#include -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; -#if defined(__NetBSD__) - ucontext_t *uc = puc; - siginfo_t *si = pinfo; -#else - ucontext_t *uc = puc; -#endif - unsigned long pc; - uint32_t fsr; - int is_write; - -#if defined(__NetBSD__) - pc = uc->uc_mcontext.__gregs[_REG_R15]; -#elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) - pc = uc->uc_mcontext.gregs[R15]; -#else - pc = uc->uc_mcontext.arm_pc; -#endif - -#ifdef __NetBSD__ - fsr = si->si_trap; -#else - fsr = uc->uc_mcontext.error_code; -#endif - /* - * In the FSR, bit 11 is WnR, assuming a v6 or - * later processor. On v5 we will always report - * this as a read, which will fail later. - */ - is_write = extract32(fsr, 11, 1); - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__aarch64__) +#if defined(__aarch64__) #if defined(__NetBSD__) From patchwork Tue Nov 2 11:06:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516644 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4409934iml; Tue, 2 Nov 2021 04:26:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzn0KCuuJDcFCTuxuDT4DUPK4H+h8ug4ralD2MZOkBQBVf4Og8a869rztBZazcLvXmR3R/B X-Received: by 2002:a05:6830:1d8e:: with SMTP id y14mr25977113oti.26.1635852419665; Tue, 02 Nov 2021 04:26:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852419; cv=none; d=google.com; s=arc-20160816; b=jsrSdJpdwgCNuUPq7rXHsbvuMF4ha3O3xX9hNKJihwiAsKwIaYyJ7YQ6ME4oRqndPn U5rENCLGUoi4Ioi91raptjNpkbhSbiPwuCbuJKlo7SqitivL3BWCg3pSwO7dUZxxtqOk TGwy1HX3wxdAetgF/9rC0ut6PgyxQ/dfa+k7xi4XaUG6a3Q9QvS5uRvWfpjjUpM5LqfW KiTfXg+ecgZcOlvZdeD0+q/ME462r/SS/5lfFE3K91D5o4wZYZztiRAnCpvRlMm+byHA RShXVqNIcXv5FlWMOlIAukxYpAltBlrqH9U0Pn+35JGmjAdUYAcVL4xbBZ1gVr2WwbxM S6hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FKF5pmiX/o7unekmxiUMsGTx/xn7CVdGNA9mcaJJAdI=; b=Op9BboysjeKXsp7a4o/l6f4G1VUCgajqCNa5AePNCaH5lgkr0iCymp3Xut7/J66RpD lQrFcA1oL13biLSrixDSrhF4em0zHp8L3YwAajNCe4AZPT4xFg+XDJj+EyWLA9NIv5ZH qij9pu7YsUCONW03mTTLjQJfPR1S2Vl/O61BOcvXMukHOj5Eq397SAd2M7H2J3CBP292 o+PzTE5DHHmuZZFtZXxMyccxePzOdRyukqJ9WOT1sAfNHLswsykutmN4DikNvg75Ql7V d4nadLUOxNFoO07otfEFx+yaTvh26q3iwoP67g9h2OxuKXhdKqk4GEbR0jMaxV0h5Ne+ P6Bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fJYaGTfW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 12/60] linux-user/host/aarch64: Populate host_signal.h Date: Tue, 2 Nov 2021 07:06:52 -0400 Message-Id: <20211102110740.215699-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82b; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 75 ++++++++++++++++++++- accel/tcg/user-exec.c | 94 +-------------------------- 2 files changed, 75 insertions(+), 94 deletions(-) -- 2.25.1 diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch64/host-signal.h index f4b4d65031..0c0b08383a 100644 --- a/linux-user/host/aarch64/host-signal.h +++ b/linux-user/host/aarch64/host-signal.h @@ -1 +1,74 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU LGPL, version 2.1 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef AARCH64_HOST_SIGNAL_H +#define AARCH64_HOST_SIGNAL_H + +/* Pre-3.16 kernel headers don't have these, so provide fallback definitions */ +#ifndef ESR_MAGIC +#define ESR_MAGIC 0x45535201 +struct esr_context { + struct _aarch64_ctx head; + uint64_t esr; +}; +#endif + +static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) +{ + return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; +} + +static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) +{ + return (struct _aarch64_ctx *)((char *)hdr + hdr->size); +} + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + struct _aarch64_ctx *hdr; + uint32_t insn; + + /* Find the esr_context, which has the WnR bit in it */ + for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) { + if (hdr->magic == ESR_MAGIC) { + struct esr_context const *ec = (struct esr_context const *)hdr; + uint64_t esr = ec->esr; + + /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ + return extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; + } + } + + /* + * Fall back to parsing instructions; will only be needed + * for really ancient (pre-3.16) kernels. + */ + insn = *(uint32_t *)host_signal_pc(uc); + + return (insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ + || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ + || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ + || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ + || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ + || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ + || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ + /* Ignore bits 10, 11 & 21, controlling indexing. */ + || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */ + || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */ + /* Ignore bits 23 & 24, controlling indexing. */ + || (insn & 0x3a400000) == 0x28000000; /* C3.3.7,14-16 */ +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index fabc8855a9..5cdbfab35b 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -253,99 +253,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__aarch64__) - -#if defined(__NetBSD__) - -#include -#include - -int cpu_signal_handler(int host_signum, void *pinfo, void *puc) -{ - ucontext_t *uc = puc; - siginfo_t *si = pinfo; - unsigned long pc; - int is_write; - uint32_t esr; - - pc = uc->uc_mcontext.__gregs[_REG_PC]; - esr = si->si_trap; - - /* - * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC - * is 0b10010x: then bit 6 is the WnR bit - */ - is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; - return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask); -} - -#else - -#ifndef ESR_MAGIC -/* Pre-3.16 kernel headers don't have these, so provide fallback definitions */ -#define ESR_MAGIC 0x45535201 -struct esr_context { - struct _aarch64_ctx head; - uint64_t esr; -}; -#endif - -static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) -{ - return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; -} - -static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) -{ - return (struct _aarch64_ctx *)((char *)hdr + hdr->size); -} - -int cpu_signal_handler(int host_signum, void *pinfo, void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - uintptr_t pc = uc->uc_mcontext.pc; - bool is_write; - struct _aarch64_ctx *hdr; - struct esr_context const *esrctx = NULL; - - /* Find the esr_context, which has the WnR bit in it */ - for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) { - if (hdr->magic == ESR_MAGIC) { - esrctx = (struct esr_context const *)hdr; - break; - } - } - - if (esrctx) { - /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ - uint64_t esr = esrctx->esr; - is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; - } else { - /* - * Fall back to parsing instructions; will only be needed - * for really ancient (pre-3.16) kernels. - */ - uint32_t insn = *(uint32_t *)pc; - - is_write = ((insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ - || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ - || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ - || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ - || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ - || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ - || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ - /* Ignore bits 10, 11 & 21, controlling indexing. */ - || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */ - || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */ - /* Ignore bits 23 & 24, controlling indexing. */ - || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */ - } - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#endif - -#elif defined(__s390__) +#if defined(__s390__) int cpu_signal_handler(int host_signum, void *pinfo, void *puc) From patchwork Tue Nov 2 11:06:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516645 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4410165iml; Tue, 2 Nov 2021 04:27:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyA4+LP7EHuTHzkv1M8dt2AtkPHd0hcxEJcS175RQXSCDII3TfIKWac6HaLwAltFUnzpFDv X-Received: by 2002:a05:6830:923:: with SMTP id v35mr9862766ott.116.1635852435758; Tue, 02 Nov 2021 04:27:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852435; cv=none; d=google.com; s=arc-20160816; b=IFN9Ixk7QEvE4iYeCW1QGvN2FQCAkC3Dd5l5jodAs93ioJbbTfWnwYITXerxglTa14 tx7UzBcU4zD04wYQV5+q7N2RQ/aIoxtOmCv4DesyOR/qIZS+ATEq3t25rBBf0FGJlycB Y0MIfQM+BbGqAbl7DbWcqOOYggAat54RAZ9CLm/0i8pAO55qukgxd+930cXHhwkG6skc c6xAxb9dv+VooQ0SDvcZY4L7nC29AsnwLGBM61RFf+tV+5H9P742HPf5gXp9I2zaAhcB ZDr/ZEiyldQp/N23knxL9LpyCA8zU48+Q/cR+S8MRi7ARM4V9QrrDeT6MwPK9e88xzYa AsOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iCPpn5LVQcjFIXnJdO6By+zwqZwVsISAIj+ezxFmWpI=; b=DuDARy7WUX0cs5fBvT0wfluc99KlDBeX69x1bndpc8iorNoV3w46eYYL41YW3atdDN Qvby5o/huHKRu33RIJYkJJnb3/qFuZO0LFlGaWWGKgtmNa/5Fov7r1H1uG/lOhR2GTL+ S2enUTmTLITPkzbXTzFl9KfcnCYhra67pOJbLLluCwN0YpuoqMhlMQBxkbAQZjOyJ89M Bp2clv2R09RW/tX6oYyJcmJFF+VZDGumsRBMhrm0sguJOYkrX8Bmc2X/nyGTnfcRiQ9E iJKZqDFLX6A72DoNEHjToRE6epuDkebk68ytep4ereT5iNnuvSj9j/ZZxC2pnD809xTF kIUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IuNexV1b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 13/60] linux-user/host/s390: Populate host_signal.h Date: Tue, 2 Nov 2021 07:06:53 -0400 Message-Id: <20211102110740.215699-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72c; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/s390/host-signal.h | 94 ++++++++++++++++++++++++++++- linux-user/host/s390x/host-signal.h | 2 +- accel/tcg/user-exec.c | 88 +-------------------------- 3 files changed, 95 insertions(+), 89 deletions(-) -- 2.25.1 diff --git a/linux-user/host/s390/host-signal.h b/linux-user/host/s390/host-signal.h index f4b4d65031..26990e4893 100644 --- a/linux-user/host/s390/host-signal.h +++ b/linux-user/host/s390/host-signal.h @@ -1 +1,93 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU LGPL, version 2.1 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef S390_HOST_SIGNAL_H +#define S390_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.psw.addr; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint16_t *pinsn = (uint16_t *)host_signal_pc(uc); + + /* + * ??? On linux, the non-rt signal handler has 4 (!) arguments instead + * of the normal 2 arguments. The 4th argument contains the "Translation- + * Exception Identification for DAT Exceptions" from the hardware (aka + * "int_parm_long"), which does in fact contain the is_write value. + * The rt signal handler, as far as I can tell, does not give this value + * at all. Not that we could get to it from here even if it were. + * So fall back to parsing instructions. Treat read-modify-write ones as + * writes, which is not fully correct, but for tracking self-modifying code + * this is better than treating them as reads. Checking si_addr page flags + * might be a viable improvement, albeit a racy one. + */ + /* ??? This is not even close to complete. */ + switch (pinsn[0] >> 8) { + case 0x50: /* ST */ + case 0x42: /* STC */ + case 0x40: /* STH */ + case 0xba: /* CS */ + case 0xbb: /* CDS */ + return true; + case 0xc4: /* RIL format insns */ + switch (pinsn[0] & 0xf) { + case 0xf: /* STRL */ + case 0xb: /* STGRL */ + case 0x7: /* STHRL */ + return true; + } + break; + case 0xc8: /* SSF format insns */ + switch (pinsn[0] & 0xf) { + case 0x2: /* CSST */ + return true; + } + break; + case 0xe3: /* RXY format insns */ + switch (pinsn[2] & 0xff) { + case 0x50: /* STY */ + case 0x24: /* STG */ + case 0x72: /* STCY */ + case 0x70: /* STHY */ + case 0x8e: /* STPQ */ + case 0x3f: /* STRVH */ + case 0x3e: /* STRV */ + case 0x2f: /* STRVG */ + return true; + } + break; + case 0xeb: /* RSY format insns */ + switch (pinsn[2] & 0xff) { + case 0x14: /* CSY */ + case 0x30: /* CSG */ + case 0x31: /* CDSY */ + case 0x3e: /* CDSG */ + case 0xe4: /* LANG */ + case 0xe6: /* LAOG */ + case 0xe7: /* LAXG */ + case 0xe8: /* LAAG */ + case 0xea: /* LAALG */ + case 0xf4: /* LAN */ + case 0xf6: /* LAO */ + case 0xf7: /* LAX */ + case 0xfa: /* LAAL */ + case 0xf8: /* LAA */ + return true; + } + break; + } + return false; +} + +#endif diff --git a/linux-user/host/s390x/host-signal.h b/linux-user/host/s390x/host-signal.h index f4b4d65031..0e83f9358d 100644 --- a/linux-user/host/s390x/host-signal.h +++ b/linux-user/host/s390x/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../s390/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5cdbfab35b..f18f3b2a5c 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -253,93 +253,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__s390__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - unsigned long pc; - uint16_t *pinsn; - int is_write = 0; - - pc = uc->uc_mcontext.psw.addr; - - /* - * ??? On linux, the non-rt signal handler has 4 (!) arguments instead - * of the normal 2 arguments. The 4th argument contains the "Translation- - * Exception Identification for DAT Exceptions" from the hardware (aka - * "int_parm_long"), which does in fact contain the is_write value. - * The rt signal handler, as far as I can tell, does not give this value - * at all. Not that we could get to it from here even if it were. - * So fall back to parsing instructions. Treat read-modify-write ones as - * writes, which is not fully correct, but for tracking self-modifying code - * this is better than treating them as reads. Checking si_addr page flags - * might be a viable improvement, albeit a racy one. - */ - /* ??? This is not even close to complete. */ - pinsn = (uint16_t *)pc; - switch (pinsn[0] >> 8) { - case 0x50: /* ST */ - case 0x42: /* STC */ - case 0x40: /* STH */ - case 0xba: /* CS */ - case 0xbb: /* CDS */ - is_write = 1; - break; - case 0xc4: /* RIL format insns */ - switch (pinsn[0] & 0xf) { - case 0xf: /* STRL */ - case 0xb: /* STGRL */ - case 0x7: /* STHRL */ - is_write = 1; - } - break; - case 0xc8: /* SSF format insns */ - switch (pinsn[0] & 0xf) { - case 0x2: /* CSST */ - is_write = 1; - } - break; - case 0xe3: /* RXY format insns */ - switch (pinsn[2] & 0xff) { - case 0x50: /* STY */ - case 0x24: /* STG */ - case 0x72: /* STCY */ - case 0x70: /* STHY */ - case 0x8e: /* STPQ */ - case 0x3f: /* STRVH */ - case 0x3e: /* STRV */ - case 0x2f: /* STRVG */ - is_write = 1; - } - break; - case 0xeb: /* RSY format insns */ - switch (pinsn[2] & 0xff) { - case 0x14: /* CSY */ - case 0x30: /* CSG */ - case 0x31: /* CDSY */ - case 0x3e: /* CDSG */ - case 0xe4: /* LANG */ - case 0xe6: /* LAOG */ - case 0xe7: /* LAXG */ - case 0xe8: /* LAAG */ - case 0xea: /* LAALG */ - case 0xf4: /* LAN */ - case 0xf6: /* LAO */ - case 0xf7: /* LAX */ - case 0xfa: /* LAAL */ - case 0xf8: /* LAA */ - is_write = 1; - } - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__mips__) +#if defined(__mips__) #if defined(__misp16) || defined(__mips_micromips) #error "Unsupported encoding" From patchwork Tue Nov 2 11:06:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516679 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4439333iml; Tue, 2 Nov 2021 04:58:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx3AQYWeCXi+cdTakgXcDGsUQ1Ej3y5fs47ELtz+cRp+p5oo+JjHaE4WOi/45k8+8URuHVU X-Received: by 2002:aca:ba55:: with SMTP id k82mr999898oif.167.1635854298049; Tue, 02 Nov 2021 04:58:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635854298; cv=none; d=google.com; s=arc-20160816; b=Uj8G731yDF/jjbknszuRJgMcfQ2vhbIrDCnxiyKvKTkEU4pf7Jm8XEvTbA4v1nJdlK /xs3ixuPNBlfFdY5hQaMd790VEV5XJ0H52RXmPa3RP6NdXmbYfkX7nGCM0hbwYRKtphp tApD2lg/02v9l1LdaCmH+UnwSrZBYlqUqB0+OfSxU9OJe0njqUAd8US7eso24+GGlJFh CFH5qJGAxegv2YAOl1gEVhbT1BN8DJJRWDo+LSrnM/a5igXBtffhanBIhrDqZDdQfj9i KEn3PLHKYc0nd+XbAVRefwhpIZp5KsjHPjFHVu1KmE12Jds4FELVOH7yOJxSKfJgdtGS CcqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DSOjZQ0mpw8Fmix6YmRPzs+3MA5kVCOMFIAxxXd1b/Y=; b=DWjVuNXVwGheKozcglA12gbQQo5DCpOTQWlpctcRgyJColONKz4xREWeFDfE2tIrCV t1oMitkxWxix2jNttFZPfy36KTA+G8p6f+CtTDmyaTtuRMhmCBC6eK4GzhONKdQk8Nxv 7Hw9FyKLAODlYKGs775qdf/Reii5t3qcjrUBLJSVw3rH8LGTvoCcu5EFY/GL9mUDDzpY 3q3203vxNaXA6YsoClsMqEqP5Xyb4AsJ3Mzou+oXLtrnwTZTIw7YiAw9QyXI+0VvYWgz afZEFhXHXVmWWIUQhVYUbWFOEzph/zEYtnAkF5hzDj0yuius11KV+xIvL9UoZbbjdEFy wZXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=w33iOpoL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 14/60] linux-user/host/mips: Populate host_signal.h Date: Tue, 2 Nov 2021 07:06:54 -0400 Message-Id: <20211102110740.215699-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82f; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/mips/host-signal.h | 63 +++++++++++++++++++++++++++++- accel/tcg/user-exec.c | 52 +----------------------- 2 files changed, 63 insertions(+), 52 deletions(-) -- 2.25.1 diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host-signal.h index f4b4d65031..ef341f7c20 100644 --- a/linux-user/host/mips/host-signal.h +++ b/linux-user/host/mips/host-signal.h @@ -1 +1,62 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU LGPL, version 2.1 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef MIPS_HOST_SIGNAL_H +#define MIPS_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.pc; +} + +#if defined(__misp16) || defined(__mips_micromips) +#error "Unsupported encoding" +#endif + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn = *(uint32_t *)host_signal_pc(uc); + + /* Detect all store instructions at program counter. */ + switch ((insn >> 26) & 077) { + case 050: /* SB */ + case 051: /* SH */ + case 052: /* SWL */ + case 053: /* SW */ + case 054: /* SDL */ + case 055: /* SDR */ + case 056: /* SWR */ + case 070: /* SC */ + case 071: /* SWC1 */ + case 074: /* SCD */ + case 075: /* SDC1 */ + case 077: /* SD */ +#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 + case 072: /* SWC2 */ + case 076: /* SDC2 */ +#endif + return true; + case 023: /* COP1X */ + /* + * Required in all versions of MIPS64 since + * MIPS64r1 and subsequent versions of MIPS32r2. + */ + switch (insn & 077) { + case 010: /* SWXC1 */ + case 011: /* SDXC1 */ + case 015: /* SUXC1 */ + return true; + } + break; + } + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index f18f3b2a5c..44c83acba5 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -253,57 +253,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__mips__) - -#if defined(__misp16) || defined(__mips_micromips) -#error "Unsupported encoding" -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - uintptr_t pc = uc->uc_mcontext.pc; - uint32_t insn = *(uint32_t *)pc; - int is_write = 0; - - /* Detect all store instructions at program counter. */ - switch((insn >> 26) & 077) { - case 050: /* SB */ - case 051: /* SH */ - case 052: /* SWL */ - case 053: /* SW */ - case 054: /* SDL */ - case 055: /* SDR */ - case 056: /* SWR */ - case 070: /* SC */ - case 071: /* SWC1 */ - case 074: /* SCD */ - case 075: /* SDC1 */ - case 077: /* SD */ -#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 - case 072: /* SWC2 */ - case 076: /* SDC2 */ -#endif - is_write = 1; - break; - case 023: /* COP1X */ - /* Required in all versions of MIPS64 since - MIPS64r1 and subsequent versions of MIPS32r2. */ - switch (insn & 077) { - case 010: /* SWXC1 */ - case 011: /* SDXC1 */ - case 015: /* SUXC1 */ - is_write = 1; - } - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__riscv) +#if defined(__riscv) int cpu_signal_handler(int host_signum, void *pinfo, void *puc) From patchwork Tue Nov 2 11:06:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516628 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4396072iml; Tue, 2 Nov 2021 04:12:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwKUCmWNeV4M3QpZOVLJpLeV8h8osjUMYsaOApoxgxo0J/d1U9Kso+EInS4CckuI8XjFKfq X-Received: by 2002:aca:f20a:: with SMTP id q10mr4465952oih.176.1635851555269; Tue, 02 Nov 2021 04:12:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635851555; cv=none; d=google.com; s=arc-20160816; b=sEcH5AGrRmSVGR9JDb6a1ZMZJEQ81wJck/s/GfkcmECsnJs+G7XS3AtGuUscxMvw31 k7ORiARkExe4LP0DNTikCZm4PfWkIZS2sAN9IOhgmRwBsnWSsQ3Ow87FOyOACM0s0Mwl zvKmM6LQ6E9+xiIrs/LX3Z6BQl0FXQDdnpvvRwJv7DFdiM5uL3+Erl/uH37SMaR630rP PoYSpltX7gKWxOiIVZoj2HpI+U9X1aBonmiQT694QWFQyQNMQ1qdKnk78F5fnkRqVmxB e82MIfJcW3nW2fY7z3pFD46AOQpI9rRUivPx199xB1Ac0Fmd+4k8lKeXLxNhFDA3jS+s h4kQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nso+AlCV/s0wqCbT6fU5+I4rw6sZu+GDtrLSeOTW3Gg=; b=Llvki7K21To7L2Na1zr7fBHQlyaMV+/crdzVckFrGR1i4SJGfrgtE/2Sh1FuAnvw4a Pt9cR4qc4KoxVx8LIr/INLb+DBdEtDnXU2WxtLizEjR4iDUsBtstBIscAn18URKdD55H 3RWEpHa0niuv4mTz32EPVtD0/kOeE+rq2rVAYDI14KKo6tcy6IuPbS+lOTnkUIfidKLk vucO8qmTMbzLUJMK904C0fJFnFjWezu7+A91gZ3FH7LZiy7kM3EFCnQvlBzOMnllMsoM bleZdYMQ6FUdrpiWzmz8Jhj8ROFglzNPHptUTIpi+NwevsuIFfCm9iSb2cnHcAp0O2hh PZQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=l3DPIXJY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 15/60] linux-user/host/riscv: Populate host_signal.h Date: Tue, 2 Nov 2021 07:06:55 -0400 Message-Id: <20211102110740.215699-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::830; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x830.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Warner Losh Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 86 +++++++++++++++++- accel/tcg/user-exec.c | 134 ---------------------------- 2 files changed, 85 insertions(+), 135 deletions(-) -- 2.25.1 diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/host-signal.h index f4b4d65031..df145b1527 100644 --- a/linux-user/host/riscv/host-signal.h +++ b/linux-user/host/riscv/host-signal.h @@ -1 +1,85 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU LGPL, version 2.1 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef RISCV_HOST_SIGNAL_H +#define RISCV_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.__gregs[REG_PC]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn = *(uint32_t *)host_signal_pc(uc); + + /* + * Detect store by reading the instruction at the program + * counter. Note: we currently only generate 32-bit + * instructions so we thus only detect 32-bit stores + */ + switch (((insn >> 0) & 0b11)) { + case 3: + switch (((insn >> 2) & 0b11111)) { + case 8: + switch (((insn >> 12) & 0b111)) { + case 0: /* sb */ + case 1: /* sh */ + case 2: /* sw */ + case 3: /* sd */ + case 4: /* sq */ + return true; + default: + break; + } + break; + case 9: + switch (((insn >> 12) & 0b111)) { + case 2: /* fsw */ + case 3: /* fsd */ + case 4: /* fsq */ + return true; + default: + break; + } + break; + default: + break; + } + } + + /* Check for compressed instructions */ + switch (((insn >> 13) & 0b111)) { + case 7: + switch (insn & 0b11) { + case 0: /*c.sd */ + case 2: /* c.sdsp */ + return true; + default: + break; + } + break; + case 6: + switch (insn & 0b11) { + case 0: /* c.sw */ + case 3: /* c.swsp */ + return true; + default: + break; + } + break; + default: + break; + } + + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 44c83acba5..a0cba61e83 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -137,64 +137,6 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, } } -/* - * 'pc' is the host PC at which the exception was raised. - * 'address' is the effective address of the memory exception. - * 'is_write' is 1 if a write caused the exception and otherwise 0. - * 'old_set' is the signal set which should be restored. - */ -static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, - int is_write, sigset_t *old_set) -{ - CPUState *cpu = current_cpu; - CPUClass *cc; - unsigned long host_addr = (unsigned long)info->si_addr; - MMUAccessType access_type = adjust_signal_pc(&pc, is_write); - abi_ptr guest_addr; - - /* For synchronous signals we expect to be coming from the vCPU - * thread (so current_cpu should be valid) and either from running - * code or during translation which can fault as we cross pages. - * - * If neither is true then something has gone wrong and we should - * abort rather than try and restart the vCPU execution. - */ - if (!cpu || !cpu->running) { - printf("qemu:%s received signal outside vCPU context @ pc=0x%" - PRIxPTR "\n", __func__, pc); - abort(); - } - -#if defined(DEBUG_SIGNAL) - printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", - pc, host_addr, is_write, *(unsigned long *)old_set); -#endif - - /* Convert forcefully to guest address space, invalid addresses - are still valid segv ones */ - guest_addr = h2g_nocheck(host_addr); - - /* XXX: locking issue */ - if (is_write && - info->si_signo == SIGSEGV && - info->si_code == SEGV_ACCERR && - h2g_valid(host_addr) && - handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) { - return 1; - } - - /* - * There is no way the target can handle this other than raising - * an exception. Undo signal and retaddr state prior to longjmp. - */ - sigprocmask(SIG_SETMASK, old_set, NULL); - - cc = CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, - MMU_USER_IDX, false, pc); - g_assert_not_reached(); -} - static int probe_access_internal(CPUArchState *env, target_ulong addr, int fault_size, MMUAccessType access_type, bool nonfault, uintptr_t ra) @@ -253,82 +195,6 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__riscv) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - greg_t pc = uc->uc_mcontext.__gregs[REG_PC]; - uint32_t insn = *(uint32_t *)pc; - int is_write = 0; - - /* Detect store by reading the instruction at the program - counter. Note: we currently only generate 32-bit - instructions so we thus only detect 32-bit stores */ - switch (((insn >> 0) & 0b11)) { - case 3: - switch (((insn >> 2) & 0b11111)) { - case 8: - switch (((insn >> 12) & 0b111)) { - case 0: /* sb */ - case 1: /* sh */ - case 2: /* sw */ - case 3: /* sd */ - case 4: /* sq */ - is_write = 1; - break; - default: - break; - } - break; - case 9: - switch (((insn >> 12) & 0b111)) { - case 2: /* fsw */ - case 3: /* fsd */ - case 4: /* fsq */ - is_write = 1; - break; - default: - break; - } - break; - default: - break; - } - } - - /* Check for compressed instructions */ - switch (((insn >> 13) & 0b111)) { - case 7: - switch (insn & 0b11) { - case 0: /*c.sd */ - case 2: /* c.sdsp */ - is_write = 1; - break; - default: - break; - } - break; - case 6: - switch (insn & 0b11) { - case 0: /* c.sw */ - case 3: /* c.swsp */ - is_write = 1; - break; - default: - break; - } - break; - default: - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#endif - /* The softmmu versions of these helpers are in cputlb.c. */ /* From patchwork Tue Nov 2 11:06:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516653 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4414489iml; Tue, 2 Nov 2021 04:31:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxJ6qXYwXKPH/AsF70/c2VifCqXsd2XF86p9d4d3/mbNbZJMYvJAPJzGsdBjBoxY/Wm4XTa X-Received: by 2002:a9d:2923:: with SMTP id d32mr25237373otb.149.1635852696334; Tue, 02 Nov 2021 04:31:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852696; cv=none; d=google.com; s=arc-20160816; b=cSA+pv/xmKc4rZTSURK+Nwvi4kMsJgyi1tjUl0iAdxe9xpO3ASf2SfbdtGaYj4u63G E5j77qfusu+ulKabnkprwtAtCIbBU3IGVqUi8vPELy8WPc7BL2XFr7rKjY59TcsdOL3o 7U0N+KbTv1b5IkG3tmUD6gahMJlFzZhE3DENMIkBZpFEYivk1Wo8svKoVkyC1wtHIFDr dEX1YFbZk0mr3QYD6aS1QdnIESkUVfSOABF+IWnwKrMnl3WVMviUxgHzr+uovZJMZjoz 2vKEnfs2J4tk81wuFMdOKCF5OFc1lN93ghJ0GWrKrb+rpSSlvTQjA6Yg4UFSHABoxRkt rQ3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gSr02Sd1ztBN32tTKGrZscSunLegESBnCl09IIG3Qgg=; b=ID913BDHTRtc4/4NbV8EaemgBxuY55pS1inYC1wgR2bvxxRxFnJvXc2fFfCYqmlKvC NqI6WeY9WqEZmlUrzCgCPxrqcbkL+ROy4/xKehp1vlXd1vyglgoILMmhnMWgNAwkgW1P SBeSVvY/iYD3kywTs9t6ElFbDDEUBG+pVdtr0WNQnsy8IBR9p/B+q/iv8I5yoF/rZD8r 9DDbGutkeAfg9hlHACNG2f1QBA5Y9Cxffd8h4UUX+qh3W9Opv+vKXXI50wDGOubRAXjH ffYd0aOPq347Qt0u+aHTpYSsqwzlrsX2cPm/F2dWAklYN0kOtSHU7xW22eCKzRIY67us nfzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VJ2ke1kz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 16/60] target/arm: Fixup comment re handle_cpu_signal Date: Tue, 2 Nov 2021 07:06:56 -0400 Message-Id: <20211102110740.215699-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The named function no longer exists. Refer to host_signal_handler instead. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index dab5f1d1cd..07be55b7e1 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -6118,7 +6118,7 @@ DO_LDN_2(4, dd, MO_64) * linux-user/ in its get_user/put_user macros. * * TODO: Construct some helpers, written in assembly, that interact with - * handle_cpu_signal to produce memory ops which can properly report errors + * host_signal_handler to produce memory ops which can properly report errors * without racing. */ From patchwork Tue Nov 2 11:06:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516648 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4412129iml; Tue, 2 Nov 2021 04:29:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxys6Z8qdvlztyE/XkUlVi6ubKEs/XX0qOQ9dc9HybNX6PwbOx7RLFIZJDVivDiYbrh+CvA X-Received: by 2002:a4a:b34a:: with SMTP id n10mr8008383ooo.46.1635852564234; Tue, 02 Nov 2021 04:29:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852564; cv=none; d=google.com; s=arc-20160816; b=owOGbLAro/cXNCyHcqTE34Q/JG8qHogmCL4XbX8ogtpNIaOkbfYiZJ86ipuXOUUZeY zOMOzmg6cytPWk6Wb471XjEM6KlSm0EU7hrEX0qGrMdycOBSKUdXKKj3+OmWIThEoBW+ jucSUOqb/m3NHQ+5vkQqNMyl+ukj1ulmNotngs0KOdpRolzLONGvsZfGJcS8Tge81g8z /dckGEl9FKjeb58gCGcL5TkIAChhyznUzJvNu44mLWKSOI3WOlYFzouZ691W1qnoxwBm 0wbdJOpftHnidqXbVoOVCXUNDG1gM7JNsanCeayXOIN0E1M/6NoO6zF/m7RizN1UYv/S xLLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aVqSiCZ8VIDZCZNfC7lcfLdqkY20k4N+WRPXdiuKsNc=; b=xppZuoZ0gkATYY6wZByeCsf+pQH8CrWhugiR0KwrC3eKGifZwN9Xzh7D366fvJYg/q HOkk1glmNwNoi05yRw7wwGoGrziiWs8FX54qLJPhUE4q2GydK0/Mp+yLg8jn/yLVVSJa zZejgwHbqhMqFZ4CbPFBvgohimdppZ1WIINtGrpmaf2bASN1Rayf/xqkVCCzauuSPQj4 JqqtIIWnm9X2mIvFfcM1ZW4eWJZk1pclk+Z30NkisXx/xfieJqqZd5KBrdTvaFaZiUSL CCStp9xsxGOJFJiaWLuQKrW9L0Gf6GhEc7a7TQAx0W5OR3aMiZ+SBTcZ8s1esO1jNytB aZRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vwCWarHq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 17/60] linux-user/host/riscv: Improve host_signal_write Date: Tue, 2 Nov 2021 07:06:57 -0400 Message-Id: <20211102110740.215699-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::831; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x831.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not read 4 bytes before we determine the size of the insn. Simplify triple switches in favor of checking major opcodes. Include the missing cases of compact fsd and fsdsp. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 83 ++++++++++------------------- 1 file changed, 28 insertions(+), 55 deletions(-) -- 2.25.1 diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/host-signal.h index df145b1527..3b168cb58b 100644 --- a/linux-user/host/riscv/host-signal.h +++ b/linux-user/host/riscv/host-signal.h @@ -18,65 +18,38 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) { - uint32_t insn = *(uint32_t *)host_signal_pc(uc); - /* - * Detect store by reading the instruction at the program - * counter. Note: we currently only generate 32-bit - * instructions so we thus only detect 32-bit stores + * Detect store by reading the instruction at the program counter. + * Do not read more than 16 bits, because we have not yet determined + * the size of the instruction. */ - switch (((insn >> 0) & 0b11)) { - case 3: - switch (((insn >> 2) & 0b11111)) { - case 8: - switch (((insn >> 12) & 0b111)) { - case 0: /* sb */ - case 1: /* sh */ - case 2: /* sw */ - case 3: /* sd */ - case 4: /* sq */ - return true; - default: - break; - } - break; - case 9: - switch (((insn >> 12) & 0b111)) { - case 2: /* fsw */ - case 3: /* fsd */ - case 4: /* fsq */ - return true; - default: - break; - } - break; - default: - break; - } + const uint16_t *pinsn = (const uint16_t *)host_signal_pc(uc); + uint16_t insn = pinsn[0]; + + /* 16-bit instructions */ + switch (insn & 0xe003) { + case 0xa000: /* c.fsd */ + case 0xc000: /* c.sw */ + case 0xe000: /* c.sd (rv64) / c.fsw (rv32) */ + case 0xa002: /* c.fsdsp */ + case 0xc002: /* c.swsp */ + case 0xe002: /* c.sdsp (rv64) / c.fswsp (rv32) */ + return true; } - /* Check for compressed instructions */ - switch (((insn >> 13) & 0b111)) { - case 7: - switch (insn & 0b11) { - case 0: /*c.sd */ - case 2: /* c.sdsp */ - return true; - default: - break; - } - break; - case 6: - switch (insn & 0b11) { - case 0: /* c.sw */ - case 3: /* c.swsp */ - return true; - default: - break; - } - break; - default: - break; + /* 32-bit instructions, major opcodes */ + switch (insn & 0x7f) { + case 0x23: /* store */ + case 0x27: /* store-fp */ + return true; + case 0x2f: /* amo */ + /* + * The AMO function code is in bits 25-31, unread as yet. + * The AMO functions are LR (read), SC (write), and the + * rest are all read-modify-write. + */ + insn = pinsn[1]; + return (insn >> 11) != 2; /* LR */ } return false; From patchwork Tue Nov 2 11:06:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516655 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4416498iml; Tue, 2 Nov 2021 04:33:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJykPEiwGCy5dRpjUcgrNFjtmXItwCHIhAFy8CPBPNpzSdl5RgDXVN1kbunGE7c79jWuP92p X-Received: by 2002:a9d:7987:: with SMTP id h7mr27040128otm.82.1635852813435; Tue, 02 Nov 2021 04:33:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852813; cv=none; d=google.com; s=arc-20160816; b=KOY2jw64mRHfbzAP5HVRDaElchO7KIV0EyKXZrBrpeni/5n90XRa9dFJ7+jqZXb5hH lEdlDzCP8j6l+PVWWJIYSZSEQK+4ANKxjPQqxwSPZ3eU4KuvUdtIdVByWKo6xuW1FJSq IkNzm+7U0FTAc/G60gg/JpVXyufirRwz/P3bKl3EKIBx4CQXjtX5DR+McM+waG/MvfJC amfavF5SuOSeMB/XvBYxFRs4GFmlFO9GSzSeRZIGGTBnPADswlVCbPuPmUzfmQnXVRPf 69kO3dVIMG3hd80d1bEBCTIQ+avi47f8+59soqy8+NHuS12lNlHiwat5iao8kpJm4TeA C78Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BEoOYfyvrRlliP3CVpcV5+AEGq6qhapGY3bb4mVGTHg=; b=kx9aI2q7GBwW5ST+iL4LNyJCjDJYeRNq2djCaqN4JChy7bju3UZkP2XDfdf1ct1cCd cWYGVSGcjr4WP1QHgZ2mGQX6z/JmDnx0SF2bgdY+Imu+0uHpL7i+ZXdDTpbatafSzq7i 6/knBBH0zu0udx0yo54IpN0kgS+kZWzsizOwN47MLbDMINWT/B5OvDzWvMOtn5TdA4aV BSg/txfAL104tywqj18V8joUPmOYGdSUoZH8eKX//jxxGD2e9q6Xmhn5OENhpzA5ZfD9 mHyQpUNUS3V0iDAkDS0mm1KqRK3B2qBQRINgLFULkAtymnIawcT3hovVHokWuUHjofXP bw1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FFU5BWww; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 18/60] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Date: Tue, 2 Nov 2021 07:06:58 -0400 Message-Id: <20211102110740.215699-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82f; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that all of the linux-user hosts have been converted to host-signal.h, drop the compatibility code. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 12 ------------ linux-user/signal.c | 14 -------------- 2 files changed, 26 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5f94d799aa..5dd663c153 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -685,18 +685,6 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, uintptr_t host_pc, abi_ptr guest_addr); -/** - * cpu_signal_handler - * @signum: host signal number - * @pinfo: host siginfo_t - * @puc: host ucontext_t - * - * To be called from the SIGBUS and SIGSEGV signal handler to inform the - * virtual cpu of exceptions. Returns true if the signal was handled by - * the virtual CPU. - */ -int cpu_signal_handler(int signum, void *pinfo, void *puc); - #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/linux-user/signal.c b/linux-user/signal.c index 6900acb122..b816678ba5 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -780,17 +780,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) ucontext_t *uc = puc; struct emulated_sigtable *k; int guest_sig; - -#ifdef HOST_SIGNAL_PLACEHOLDER - /* the CPU emulator uses some host signals to detect exceptions, - we forward to it some signals */ - if ((host_sig == SIGSEGV || host_sig == SIGBUS) - && info->si_code > 0) { - if (cpu_signal_handler(host_sig, info, puc)) { - return; - } - } -#else uintptr_t pc = 0; bool sync_sig = false; @@ -850,7 +839,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) sync_sig = true; } -#endif /* get target signal number */ guest_sig = host_to_target_signal(host_sig); @@ -865,7 +853,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) k->pending = guest_sig; ts->signal_pending = 1; -#ifndef HOST_SIGNAL_PLACEHOLDER /* * For synchronous signals, unwind the cpu state to the faulting * insn and then exit back to the main loop so that the signal @@ -875,7 +862,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) cpu->exception_index = EXCP_INTERRUPT; cpu_loop_exit_restore(cpu, pc); } -#endif rewind_if_in_safe_syscall(puc); From patchwork Tue Nov 2 11:06:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516624 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4393296iml; Tue, 2 Nov 2021 04:09:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzIQCCardIjtZSJfMPGSA7LzMNnpgUyITiZlRb3sXtbHIrdhQ+uW2wa4koGrIIIWSUmqmhw X-Received: by 2002:a05:6820:3d1:: with SMTP id s17mr19951097ooj.38.1635851381360; Tue, 02 Nov 2021 04:09:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635851381; cv=none; d=google.com; s=arc-20160816; b=V48l0I/biI99LA1BMKvR0+/UGQCtHsyWDGf8zdUmSqxkr7msz7wobQ/BMuZCRWWlwE /bhf2l6Csty/BWfXAqHm8YojeDOC+p5wmaRSUuFwB1Qe4/fkzmpW4GFJtdXvpn6BHFWg 16eeyWgX8VOujkEXNhWtXIK2M671Wvq2p4lcaA6yweQiRQrx7qmI+XjmhzVZZsiaWuCH +77VN0KPx1MFPTN0plLvvywm+RYbjYKyHjenwU7sxgIvHSfbWRaLFrplTdgB2QXRXO/N ckYEsJN98weoog3EBEY2+wLnkW0tuNfp2pU6puRuAEctYE+iU0Vmtn5JbPb9dk0dRp8M hkJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=p8GaNWW3vnRejpH0QBiQY2hh87QfB4bhIFphc+bCE2U=; b=bnuNORwoUjDgSxkMVHIQ53lse3ImbImC7YWgU/n94fu1+Mm2ectx8lTO1lAfLOhy8A ir8OygwPzfEIOYKD4Cr8w2zxuiH4sQ1IEprNjkFyuE1Dn0citghUFiFDoD+yjPjmrC4o 65tx59xFsiSAOJWaKVCC0u/wUtPn7c5hBcXbOCev/Ie5YEbhAngoA1C/nUhJeI1IJQIN VRS7ERBLluuRDX6yJcVS18mbW2ZOuBO1fwQNZK3S2MZtkWrsn+R+jM3k7klJpAXXV+vx f3WLm011VvWVfOi81sHXgDG7Vy6Fc7R8cIbLofvDhAzW9u7jhpf5GHIguaKKQe7hkvY8 vpkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ndx+nxGa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 19/60] hw/core: Add TCGCPUOps.record_sigsegv Date: Tue, 2 Nov 2021 07:06:59 -0400 Message-Id: <20211102110740.215699-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::833; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x833.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a new user-only interface for updating cpu state before raising a signal. This will replace tlb_fill for user-only and should result in less boilerplate for each guest. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.25.1 diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 6cbe17f2e6..41718b695b 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -111,6 +111,32 @@ struct TCGCPUOps { */ bool (*io_recompile_replay_branch)(CPUState *cpu, const TranslationBlock *tb); +#else + /** + * record_sigsegv: + * @cpu: cpu context + * @addr: faulting guest address + * @access_type: access was read/write/execute + * @maperr: true for invalid page, false for permission fault + * @ra: host pc for unwinding + * + * We are about to raise SIGSEGV with si_code set for @maperr, + * and si_addr set for @addr. Record anything further needed + * for the signal ucontext_t. + * + * If the emulated kernel does not provide anything to the signal + * handler with anything besides the user context registers, and + * the siginfo_t, then this hook need do nothing and may be omitted. + * Otherwise, record the data and return; the caller will raise + * the signal, unwind the cpu state, and return to the main loop. + * + * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided + * so that a "normal" cpu exception can be raised. In this case, + * the signal must be raised by the architecture cpu_loop. + */ + void (*record_sigsegv)(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); #endif /* CONFIG_SOFTMMU */ #endif /* NEED_CPU_H */ From patchwork Tue Nov 2 11:07:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516651 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4414147iml; Tue, 2 Nov 2021 04:31:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw2WA25dZX2hjUynYHwDHmSyYfChTzmF4rGbfh6EhOGNr3egdRYKOeycIPRNsQkNshF1qWz X-Received: by 2002:a05:6808:13ce:: with SMTP id d14mr4403115oiw.159.1635852676216; Tue, 02 Nov 2021 04:31:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852676; cv=none; d=google.com; s=arc-20160816; b=Wx6RZXFMLuV/uzx6RDLAcrATc4jCY+54lTkwrA6vNLfRBO+8m0Wbm60q4IQW1WGnM0 gTjZD9wCNv01kXlpWdmLdLQdGwjwcJ7DFCdWT58s+oF17rd86me1i4SkA9VSfu6b0r0C d33RqX0OT6yr6IRZasIKUbUvbI74OghnSwddL64NJVZChumVNXtBl009KPTW0LXwnPvc 7Fh5od67HqFMmzizM6cMJydVD67Jb5up+1cOEeygnoMVZdgKWPyegaCfhJ/Brd7AOujb t49wqc1m8WNBlbD2uqF+aESXQKrPyHM1npms9HLKV2mN+aIT1F/Jnew5WqeGLQsrV/3A wb+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=h74jAt7hxYWJ8vb//ZptaTN1DfaIP6MJ1JsKHfl8Ic0=; b=uS7S5NQVtfkPjTUAE0V5wQeh9gZ/GbDY3XMWN6mEzrAcY9/l2gCpi84W2NfTQEQ0Tw 8D7vyTeSQoi6N3GqsDKZfeShlkFucmVvk6K5FP+dS7BwPG0EVwKJLVjwOIrKYEWcUGbB BzFJma1AkZvipDFHvkJcsIcFy/zjeC62m+W0ov3QIGpMnWNNBCdTXrGCY76VUFK8+V23 vjZvK5cHzULy/W/k2OUaWuwKsi5pXlTvLUsVjOLWp59MtxaEUR1COF/W8mdL9fyYUrfl RXO9hM6R0/rsbJwnR4FYLFNdBIWKhDKmcr8nopV+b/viQ5kRX8zlNy+eoYr639aOxOLH Osnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BZWt8kLB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 20/60] linux-user: Add cpu_loop_exit_sigsegv Date: Tue, 2 Nov 2021 07:07:00 -0400 Message-Id: <20211102110740.215699-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::732; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x732.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a new interface to be provided by the os emulator for raising SIGSEGV on fault. Use the new record_sigsegv target hook. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 15 +++++++++++++++ accel/tcg/user-exec.c | 33 ++++++++++++++++++--------------- linux-user/signal.c | 30 ++++++++++++++++++++++-------- 3 files changed, 55 insertions(+), 23 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5dd663c153..f74578500c 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -685,6 +685,21 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, uintptr_t host_pc, abi_ptr guest_addr); +/** + * cpu_loop_exit_sigsegv: + * @cpu: the cpu context + * @addr: the guest address of the fault + * @access_type: access was read/write/execute + * @maperr: true for invalid page, false for permission fault + * @ra: host pc for unwinding + * + * Use the TCGCPUOps hook to record cpu state, do guest operating system + * specific things to raise SIGSEGV, and jump to the main cpu loop. + */ +void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); + #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index a0cba61e83..c4f69908e9 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -141,35 +141,38 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, int fault_size, MMUAccessType access_type, bool nonfault, uintptr_t ra) { - int flags; + int acc_flag; + bool maperr; switch (access_type) { case MMU_DATA_STORE: - flags = PAGE_WRITE; + acc_flag = PAGE_WRITE_ORG; break; case MMU_DATA_LOAD: - flags = PAGE_READ; + acc_flag = PAGE_READ; break; case MMU_INST_FETCH: - flags = PAGE_EXEC; + acc_flag = PAGE_EXEC; break; default: g_assert_not_reached(); } - if (!guest_addr_valid_untagged(addr) || - page_check_range(addr, 1, flags) < 0) { - if (nonfault) { - return TLB_INVALID_MASK; - } else { - CPUState *cpu = env_cpu(env); - CPUClass *cc = CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_type, - MMU_USER_IDX, false, ra); - g_assert_not_reached(); + if (guest_addr_valid_untagged(addr)) { + int page_flags = page_get_flags(addr); + if (page_flags & acc_flag) { + return 0; /* success */ } + maperr = !(page_flags & PAGE_VALID); + } else { + maperr = true; } - return 0; + + if (nonfault) { + return TLB_INVALID_MASK; + } + + cpu_loop_exit_sigsegv(env_cpu(env), addr, access_type, maperr, ra); } int probe_access_flags(CPUArchState *env, target_ulong addr, diff --git a/linux-user/signal.c b/linux-user/signal.c index b816678ba5..135983747d 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -688,9 +688,27 @@ void force_sigsegv(int oldsig) } force_sig(TARGET_SIGSEGV); } - #endif +void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, bool maperr, uintptr_t ra) +{ + const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + + if (tcg_ops->record_sigsegv) { + tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); + } else if (tcg_ops->tlb_fill) { + tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, ra); + g_assert_not_reached(); + } + + force_sig_fault(TARGET_SIGSEGV, + maperr ? TARGET_SEGV_MAPERR : TARGET_SEGV_ACCERR, + addr); + cpu->exception_index = EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, ra); +} + /* abort execution with signal */ static void QEMU_NORETURN dump_core_and_abort(int target_sig) { @@ -806,7 +824,7 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) access_type = adjust_signal_pc(&pc, is_write); if (host_sig == SIGSEGV) { - const struct TCGCPUOps *tcg_ops; + bool maperr = true; if (info->si_code == SEGV_ACCERR && h2g_valid(host_addr)) { /* If this was a write to a TB protected page, restart. */ @@ -821,18 +839,14 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) * which means that we may get ACCERR when we want MAPERR. */ if (page_get_flags(guest_addr) & PAGE_VALID) { - /* maperr = false; */ + maperr = false; } else { info->si_code = SEGV_MAPERR; } } sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); - - tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; - tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, - MMU_USER_IDX, false, pc); - g_assert_not_reached(); + cpu_loop_exit_sigsegv(cpu, guest_addr, access_type, maperr, pc); } else { sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); } From patchwork Tue Nov 2 11:07:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516649 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4412211iml; Tue, 2 Nov 2021 04:29:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyBMPCw6YZQBG2H+Pmt+JTrjA2w3M1w7vrffrM+JkYqv5suQ6rXtj8uXrUvUSfpUsBdF1sp X-Received: by 2002:a9d:6d03:: with SMTP id o3mr27226104otp.87.1635852569214; Tue, 02 Nov 2021 04:29:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852569; cv=none; d=google.com; s=arc-20160816; b=U3qULCj98PABnW/GCy5EoGe/3Auq++h6Onb6p0Sy/X/N84oUB9g3PwzWc4O/JbTWa6 phmmypy31OXQvR+dgAytIUI0urWB2TbTbNMHcg6T7BcQm8vvJm8H7n/3X5HiMkhsG7sK Je48TGc0UyfT6mqqhaIcRXOGhbUpenY9w1nbUjiVEIqXlmkQMjadsSx96v0LQQ2mxuOu Z407R5x/Fe7inEyCKSHkgBX3xFRqUx15iWr1Orf3Pr6JTSBDiuVqkeVQ9LBtLJg91CCE dbuhwW6NNc1aPniIDtgzfQ+NuOyhQyhdpuHKzlk1sZVFeb1UzmkHQ6mOLseM99n9OtVd WACA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AEaCX227BZE+QCVidN+9WkHpAoM/8sOPsRQn51mlr6o=; b=j5xDzFnn5Tddyp4Xei7ztSoe+RtVt9FAJiRYgWictff+RNutawAQzSuYoXdGZdXV6t 4yNpWqo5fGT5P09TCYwoauqjFoSartBzwG7GhLD+SFS0NbhJQVUtEMRQYMCKn+lUnSSZ SiF3vR2hDgMIoxwcuZ7aS9pBXj3U++NSSu8fqxhVocHVayaD8rWNrulDRaVoPVrbK8Z8 ddRY8X339Q70uBjqm8HIhhVqtHxCQG+rWT9vLC/tJWFRgyNBaxn/cY743hoiyDHFRmdV dBIxwvRt2xC7FR0+HB9CW8NheWL/2isP0Km73m7vXjMjJW5JYXeOfobKn5avyYD4Bted yz/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WvXhDJWn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 21/60] target/alpha: Implement alpha_cpu_record_sigsegv Date: Tue, 2 Nov 2021 07:07:01 -0400 Message-Id: <20211102110740.215699-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::836; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x836.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Record trap_arg{0,1,2} for the linux-user signal frame. Fill in the stores to trap_arg{1,2} that were missing from the previous user-only alpha_cpu_tlb_fill function. Use maperr to simplify computation of trap_arg1. Remove the code for EXCP_MMFAULT from cpu_loop, as that part is now handled by cpu_loop_exit_sigsegv. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 13 +++++++++---- linux-user/alpha/cpu_loop.c | 8 -------- target/alpha/cpu.c | 6 ++++-- target/alpha/helper.c | 39 ++++++++++++++++++++++++++++++++----- 4 files changed, 47 insertions(+), 19 deletions(-) -- 2.25.1 diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 772828cc26..d49cc36d07 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -439,9 +439,6 @@ void alpha_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU void alpha_cpu_list(void); -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); @@ -449,7 +446,15 @@ uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env); void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val); uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg); void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val); -#ifndef CONFIG_USER_ONLY + +#ifdef CONFIG_USER_ONLY +void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr); +#else +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 1b00a81385..4cc8e0a55c 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -54,14 +54,6 @@ void cpu_loop(CPUAlphaState *env) fprintf(stderr, "External interrupt. Exit\n"); exit(EXIT_FAILURE); break; - case EXCP_MMFAULT: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID - ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); - info._sifields._sigfault._addr = env->trap_arg0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_UNALIGN: info.si_signo = TARGET_SIGBUS; info.si_errno = 0; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 93e16a2ffb..69f32c3078 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -218,9 +218,11 @@ static const struct SysemuCPUOps alpha_sysemu_ops = { static const struct TCGCPUOps alpha_tcg_ops = { .initialize = alpha_translate_init, - .tlb_fill = alpha_cpu_tlb_fill, -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv = alpha_cpu_record_sigsegv, +#else + .tlb_fill = alpha_cpu_tlb_fill, .cpu_exec_interrupt = alpha_cpu_exec_interrupt, .do_interrupt = alpha_cpu_do_interrupt, .do_transaction_failed = alpha_cpu_do_transaction_failed, diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 81550d9e2f..b7e7f73b15 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -120,15 +120,44 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val) } #if defined(CONFIG_USER_ONLY) -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { AlphaCPU *cpu = ALPHA_CPU(cs); + target_ulong mmcsr, cause; - cs->exception_index = EXCP_MMFAULT; + /* Assuming !maperr, infer the missing protection. */ + switch (access_type) { + case MMU_DATA_LOAD: + mmcsr = MM_K_FOR; + cause = 0; + break; + case MMU_DATA_STORE: + mmcsr = MM_K_FOW; + cause = 1; + break; + case MMU_INST_FETCH: + mmcsr = MM_K_FOE; + cause = -1; + break; + default: + g_assert_not_reached(); + } + if (maperr) { + if (address < BIT_ULL(TARGET_VIRT_ADDR_SPACE_BITS - 1)) { + /* Userspace address, therefore page not mapped. */ + mmcsr = MM_K_TNV; + } else { + /* Kernel or invalid address. */ + mmcsr = MM_K_ACV; + } + } + + /* Record the arguments that PALcode would give to the kernel. */ cpu->env.trap_arg0 = address; - cpu_loop_exit_restore(cs, retaddr); + cpu->env.trap_arg1 = mmcsr; + cpu->env.trap_arg2 = cause; } #else /* Returns the OSF/1 entMM failure indication, or -1 on success. */ From patchwork Tue Nov 2 11:07:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516631 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4399809iml; Tue, 2 Nov 2021 04:16:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzJMfZrLZne0ImwpVn4ybGx2TKRO7r/Ojq6CpCV4Ym1ygyvvuZQ+/t4eRlOtKg6m63ffR3L X-Received: by 2002:a9d:220c:: with SMTP id o12mr26433968ota.250.1635851779196; Tue, 02 Nov 2021 04:16:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635851779; cv=none; d=google.com; s=arc-20160816; b=XNvy6gYjhUZ/RtsfJ/7AJqtQbHz5TWGRumO3Ds8Rj6anVlOfOFhrJMxEu5I3lz9wGb wPi4pZ3qeEbOTIU6DYOMnx0byeBD813a6EonJ42GDqVgk0EzV8BIL9kIOCHJm2lwqruD ryptmHKROt6ewuGxPL8Ubs3SGGpKAT/FWgQmig8aw94OhiSESiq9uOf5w67XS33rdkeE rEgpcpAjfw13mAKL2t1xY0NZYWsCHaHtLxdu3slBqT37NONqZ6Lfn9NUKLHbUl2g9o05 zzrWc8g6bXqYcwqfzMcJtVQc/05emmOVEp9nwfk0MbcLYKBSsilnY33SpaprNzaeFNio aPGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fofFGJJJzbXM7L3Ibz3JhPAmpo8LElJ1YWB6iIwHWsU=; b=ruYjPoY1S6JfoKcRMij7ujPkBD7P4zOu7AW3zTYtye1kg8VOHr2m9oCQi/LLMGljeI AwHdfGvNuqWgkwoy3EqzEE6MifUpkxeRnUu2bP265WwtjrUF3RPcDlGgAnYVXq6PJQwj Y+kO1sqEP64uYoVlGRMpIT5xMEetNN3F5HwC2DifufF6SmaWi8NVD85xLcOf1HJC81eg Hqxo9goV1SmMTMB077wV+vtKUkBn4NdNtcIVhHyAu4NEj6AvrpZs1FrRVM6bEDkb9cTd Iru+ttu3MdTPxdTPkpf0GANFVsaXgj3u2ek7NWSI/tEahu1ybmc0hpa81Wdo4mrJAHfz gsXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="T1aQLka/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 22/60] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup Date: Tue, 2 Nov 2021 07:07:02 -0400 Message-Id: <20211102110740.215699-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::836; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x836.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the new os interface for raising the exception, rather than calling arm_cpu_tlb_fill directly. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 724175210b..e09b7e46a2 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -84,10 +84,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, uintptr_t index; if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE_ORG : PAGE_READ))) { - /* SIGSEGV */ - arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access, - ptr_mmu_idx, false, ra); - g_assert_not_reached(); + cpu_loop_exit_sigsegv(env_cpu(env), ptr, ptr_access, + !(flags & PAGE_VALID), ra); } /* Require both MAP_ANON and PROT_MTE for the page. */ From patchwork Tue Nov 2 11:07:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516652 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4414394iml; Tue, 2 Nov 2021 04:31:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzpGNEkFa97TupGRZodxdmvL1a2VEo9S1On/RoFQntRtJ8otbkTPGJTB2QqfRWMemL6KYiu X-Received: by 2002:a05:6830:14c3:: with SMTP id t3mr23436151otq.39.1635852689842; Tue, 02 Nov 2021 04:31:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852689; cv=none; d=google.com; s=arc-20160816; b=SoWQrj1Uax78xD8V4jMt8PfsDOUDCc+JnRvBF5LKKEBHQCK4PA3ZQACJNiuCoSaKiJ C9h3e/aWaO2dKXUFJyVcI/nqCl9VZCPQ5ls+9Po3K4mgsPdVK5Zk4b6kIzsWvgtczjYc 1+R/MHw9zaKMUFEPHvAmjb/QSWr7h9LyE06BMWYzcww7GHhbj/N1PMAJfXa4WEcPEBPk H/k6Pj2lYfGXiUXvKshJIFhBV9OzmsOe+Bddt4Llg9WEhsEU516vkODyAl3WCuI6PNl+ XImfaPyJYfZtUpke5bswKAEaYBCqZ/yUL41M7BQuptbK1kRsncHVKm+fLSbRmH69/YeI wjYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GxgKUblSc/AuTdeTrCoYEJS946D/KatMQ8ilg/nMD3U=; b=kiY4Utk/pKx+emEead7Zsxv1lvGg1HGkCH4EZrgyv1DV79dMRP8m13DHxOYw908Df1 O7KUlCchhsJ+ibj/kPo1/egBjjVckAOjfcVIgvS3vLS0yP1vfL0+TwhiNr/2l98ysg6N IvZ2JgIo+6NpDgKWcHntuweNFL32aEs1fSPqS/2HNqVFLgBhmrtMp0ztlWC2IoiE8wCD //31+9JeO+KS72TNIBRHddmoultUpOPyDRmVrZBdperb/dC9Pgy9R9EbvhlNUgEk03AX B4b1FFzgC6xVdbRoSHhIQpO6PbDNWwex960+NaULQurqaXxrjs3FRCl8XKGgk0H7cMbg DJjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WUrOCNn0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 23/60] target/arm: Implement arm_cpu_record_sigsegv Date: Tue, 2 Nov 2021 07:07:03 -0400 Message-Id: <20211102110740.215699-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72d; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because of the complexity of setting ESR, continue to use arm_deliver_fault. This means we cannot remove the code within cpu_loop that decodes EXCP_DATA_ABORT and EXCP_PREFETCH_ABORT. But using the new hook means that we don't have to do the page_get_flags check manually, and we'll be able to restrict the tlb_fill hook to sysemu later. Reviewed-by: Warner Losh Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 6 ++++++ target/arm/cpu.c | 6 ++++-- target/arm/cpu_tcg.c | 6 ++++-- target/arm/tlb_helper.c | 36 +++++++++++++++++++----------------- 4 files changed, 33 insertions(+), 21 deletions(-) -- 2.25.1 diff --git a/target/arm/internals.h b/target/arm/internals.h index 3612107ab2..5a7aaf0f51 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -544,9 +544,15 @@ static inline bool arm_extabort_type(MemTxResult result) return result != MEMTX_DECODE_ERROR; } +#ifdef CONFIG_USER_ONLY +void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 641a8c2d3d..7a18a58ca0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2031,10 +2031,12 @@ static const struct SysemuCPUOps arm_sysemu_ops = { static const struct TCGCPUOps arm_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, - .tlb_fill = arm_cpu_tlb_fill, .debug_excp_handler = arm_debug_excp_handler, -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv = arm_cpu_record_sigsegv, +#else + .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_cpu_exec_interrupt, .do_interrupt = arm_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0d5adccf1a..7b3bea2fbb 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -898,10 +898,12 @@ static void pxa270c5_initfn(Object *obj) static const struct TCGCPUOps arm_v7m_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, - .tlb_fill = arm_cpu_tlb_fill, .debug_excp_handler = arm_debug_excp_handler, -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv = arm_cpu_record_sigsegv, +#else + .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, .do_interrupt = arm_v7m_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 3107f9823e..dc5860180f 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -147,28 +147,12 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } -#endif /* !defined(CONFIG_USER_ONLY) */ - bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { ARMCPU *cpu = ARM_CPU(cs); ARMMMUFaultInfo fi = {}; - -#ifdef CONFIG_USER_ONLY - int flags = page_get_flags(useronly_clean_ptr(address)); - if (flags & PAGE_VALID) { - fi.type = ARMFault_Permission; - } else { - fi.type = ARMFault_Translation; - } - fi.level = 3; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); -#else hwaddr phys_addr; target_ulong page_size; int prot, ret; @@ -210,5 +194,23 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_restore_state(cs, retaddr, true); arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); } -#endif } +#else +void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra) +{ + ARMMMUFaultInfo fi = { + .type = maperr ? ARMFault_Translation : ARMFault_Permission, + .level = 3, + }; + ARMCPU *cpu = ARM_CPU(cs); + + /* + * We report both ESR and FAR to signal handlers. + * For now, it's easiest to deliver the fault normally. + */ + cpu_restore_state(cs, ra, true); + arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi); +} +#endif /* !defined(CONFIG_USER_ONLY) */ From patchwork Tue Nov 2 11:07:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516660 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4419105iml; Tue, 2 Nov 2021 04:36:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxqQwctbPsVCOFyxw7a/oi3bcCRolSRVLPm9GAdA+BdYPo7xMdO5mef1RrftGv8eIc7UwJk X-Received: by 2002:a05:6808:5c5:: with SMTP id d5mr4634318oij.173.1635852985502; Tue, 02 Nov 2021 04:36:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852985; cv=none; d=google.com; s=arc-20160816; b=NN7rgYXjbSNn+y2H3is5hOI0+oiY7YrPhnD7CoXroJWVBMarKnJwm9M8KrfKEP8Q4Z wEImeXuUZ/gnS1qFLMgE4aTPr2o6jbmVOLOKzasnBIMCwbVt0EktfWnOwRxno5XlNODA UxA7hIoG4HJvkTUZsZ727QDXpp96kNJPV9BGEPNkxmGJSDHFWeL8kIsztLhZPsQXKGTh vBc/Z4xKoJpADTl6qQcLFH6TsOg+20kCcWL0EXxYYoBphxVU0/u90r3xmXNgXqfJKf5S VAC2aBYHsnfDA/6hOpT8niJyjbD4EQQvNmvmxdQB3KpfPwoTdZ6rOKGotuxR3+RRduQt s/Qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LvK67GkX13tDj2L9Y8ql/Gd7bbn2JZgBQ3dF7lXKOxQ=; b=xJMTaWeWqHIUTHCzS4ONNyAQq5MAjP56ZiFM6iODid9k+03TOf6WCi487QEekblQPK TSVlxeGI7NvHa2Gpd+EBTTacNvo06ycOG7GXozdBdYvjL6JSjv1E9N4dc/mTrdZAOUg1 2sdh2CFMGyBpRw+EbZEKNlsYBaLtUS1tCTPedmJrAaktF9YOf4VmZRfRpNmGlfmua5tm wZRG+0PFDm/9n6tGC9tdw204lpoPyccf577Z10wBckbja4YG7oF4U51YxGYg2Q3yALel O0YW+8ibBZtqRtwAYqw9Fbj1cAbi6tGS6eCWKXhl+3xaMcbhzhNyheYwbHwbRuv3kba/ JG9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gBpQ1oV8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 24/60] target/cris: Make cris_cpu_tlb_fill sysemu only Date: Tue, 2 Nov 2021 07:07:04 -0400 Message-Id: <20211102110740.215699-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::731; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x731.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for cris linux-user. Remove the code from cpu_loop that handled the unnamed 0xaa exception. This makes all of the code in helper.c sysemu only, so remove the ifdefs and move the file to cris_softmmu_ss. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/cris/cpu.h | 8 ++++---- linux-user/cris/cpu_loop.c | 10 ---------- target/cris/cpu.c | 4 ++-- target/cris/helper.c | 18 ------------------ target/cris/meson.build | 7 +++++-- 5 files changed, 11 insertions(+), 36 deletions(-) -- 2.25.1 diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 6603565f83..b445b194ea 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -189,6 +189,10 @@ extern const VMStateDescription vmstate_cris_cpu; void cris_cpu_do_interrupt(CPUState *cpu); void crisv10_cpu_do_interrupt(CPUState *cpu); bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req); + +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #endif void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags); @@ -251,10 +255,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) return !!(env->pregs[PR_CCS] & U_FLAG); } -bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); - /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0 diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index b9085619c4..0d5d268609 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -37,16 +37,6 @@ void cpu_loop(CPUCRISState *env) process_queued_cpu_work(cs); switch (trapnr) { - case 0xaa: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->pregs[PR_EDA]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index c2e7483f5b..ed6c781342 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -205,9 +205,9 @@ static const struct SysemuCPUOps cris_sysemu_ops = { static const struct TCGCPUOps crisv10_tcg_ops = { .initialize = cris_initialize_crisv10_tcg, - .tlb_fill = cris_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = cris_cpu_tlb_fill, .cpu_exec_interrupt = cris_cpu_exec_interrupt, .do_interrupt = crisv10_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ @@ -215,9 +215,9 @@ static const struct TCGCPUOps crisv10_tcg_ops = { static const struct TCGCPUOps crisv32_tcg_ops = { .initialize = cris_initialize_tcg, - .tlb_fill = cris_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = cris_cpu_tlb_fill, .cpu_exec_interrupt = cris_cpu_exec_interrupt, .do_interrupt = cris_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/cris/helper.c b/target/cris/helper.c index 36926faf32..a0d6ecdcd3 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -39,22 +39,6 @@ #define D_LOG(...) do { } while (0) #endif -#if defined(CONFIG_USER_ONLY) - -bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - CRISCPU *cpu = CRIS_CPU(cs); - - cs->exception_index = 0xaa; - cpu->env.pregs[PR_EDA] = address; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - - static void cris_shift_ccs(CPUCRISState *env) { uint32_t ccs; @@ -304,5 +288,3 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return ret; } - -#endif /* !CONFIG_USER_ONLY */ diff --git a/target/cris/meson.build b/target/cris/meson.build index 67c3793c85..c1e326d950 100644 --- a/target/cris/meson.build +++ b/target/cris/meson.build @@ -2,13 +2,16 @@ cris_ss = ss.source_set() cris_ss.add(files( 'cpu.c', 'gdbstub.c', - 'helper.c', 'op_helper.c', 'translate.c', )) cris_softmmu_ss = ss.source_set() -cris_softmmu_ss.add(files('mmu.c', 'machine.c')) +cris_softmmu_ss.add(files( + 'helper.c', + 'machine.c', + 'mmu.c', +)) target_arch += {'cris': cris_ss} target_softmmu_arch += {'cris': cris_softmmu_ss} From patchwork Tue Nov 2 11:07:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516659 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4418850iml; 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 25/60] target/hexagon: Remove hexagon_cpu_tlb_fill Date: Tue, 2 Nov 2021 07:07:05 -0400 Message-Id: <20211102110740.215699-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72b; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Taylor Simpson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for hexagon linux-user. Remove the code from cpu_loop that raises SIGSEGV. Reviewed-by: Taylor Simpson Signed-off-by: Richard Henderson --- linux-user/hexagon/cpu_loop.c | 24 +----------------------- target/hexagon/cpu.c | 23 ----------------------- 2 files changed, 1 insertion(+), 46 deletions(-) -- 2.25.1 diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index bee2a9e4ea..6b24cbaba9 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -28,8 +28,7 @@ void cpu_loop(CPUHexagonState *env) { CPUState *cs = env_cpu(env); - int trapnr, signum, sigcode; - target_ulong sigaddr; + int trapnr; target_ulong syscallnum; target_ulong ret; @@ -39,10 +38,6 @@ void cpu_loop(CPUHexagonState *env) cpu_exec_end(cs); process_queued_cpu_work(cs); - signum = 0; - sigcode = 0; - sigaddr = 0; - switch (trapnr) { case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ @@ -65,12 +60,6 @@ void cpu_loop(CPUHexagonState *env) env->gpr[0] = ret; } break; - case HEX_EXCP_FETCH_NO_UPAGE: - case HEX_EXCP_PRIV_NO_UREAD: - case HEX_EXCP_PRIV_NO_UWRITE: - signum = TARGET_SIGSEGV; - sigcode = TARGET_SEGV_MAPERR; - break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); break; @@ -79,17 +68,6 @@ void cpu_loop(CPUHexagonState *env) trapnr); exit(EXIT_FAILURE); } - - if (signum) { - target_siginfo_t info = { - .si_signo = signum, - .si_errno = 0, - .si_code = sigcode, - ._sifields._sigfault._addr = sigaddr - }; - queue_signal(env, info.si_signo, QEMU_SI_KILL, &info); - } - process_pending_signals(env); } } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 3338365c16..160a46a3d5 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -245,34 +245,11 @@ static void hexagon_cpu_init(Object *obj) qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property); } -static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ -#ifdef CONFIG_USER_ONLY - switch (access_type) { - case MMU_INST_FETCH: - cs->exception_index = HEX_EXCP_FETCH_NO_UPAGE; - break; - case MMU_DATA_LOAD: - cs->exception_index = HEX_EXCP_PRIV_NO_UREAD; - break; - case MMU_DATA_STORE: - cs->exception_index = HEX_EXCP_PRIV_NO_UWRITE; - break; - } - cpu_loop_exit_restore(cs, retaddr); -#else -#error System mode not implemented for Hexagon -#endif -} - #include "hw/core/tcg-cpu-ops.h" static const struct TCGCPUOps hexagon_tcg_ops = { .initialize = hexagon_translate_init, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, - .tlb_fill = hexagon_tlb_fill, }; static void hexagon_cpu_class_init(ObjectClass *c, void *data) From patchwork Tue Nov 2 11:07:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516663 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4424326iml; Tue, 2 Nov 2021 04:41:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyD+PT2SOaKbPR5o38jjOCKJ2XP86XQduzyWhejOF4cx0bdca6P8W41SNDVyXBia0S8rxvb X-Received: by 2002:a4a:b48a:: with SMTP id b10mr24081861ooo.24.1635853316986; Tue, 02 Nov 2021 04:41:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635853316; cv=none; d=google.com; s=arc-20160816; b=iDh6R4yWJQi351F6ApNHrp1/alEhHxLO60QJwx5/pxUc9owfPnGDn44r68BgxQyp2O LRwnJCwkuWKPjVxd3tm/Ver4E46qV0y/T/9Hfm3J83zn8MMb+Z+bAaMxmY28OGu6YT4j iXKXo4oy/MrM0ApDGkHphuk+Oms/R1j9TWKRzqHZsFqNmbi75UMm9QO9EasZQl4zXa+P LFfAGnPcPtejhdap7QQrpYaXlLtbHWz7DPllVsOE+MzN8uYGPorzPmSTuERcDpSQGcFT FKmtGsS37ZnOHZzc55HzB8UT8Kvu7WW2Im5BZ9TQ1A4yifQVX6syFeqkZYEViQucxhKj YDtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=StWIwDrqZSFeqnqFg+3hcLpPKjUfEIhsbr06iPdg0Gc=; b=jDClp6LbY1ks29+UYV1QU6Y/Lgs1cslynVofmTHD6Z8sOJ1MUOA1j3agraWvQ/5F13 p8upLGeEGmnJjYpjCEDID4vVTxmDjgkKNFSDkxisnQuFULgqqofwG0/B56BNiBZqgh4Z 68Pnorr2XibiWrzL9IZbrepkh+HYbgRs1uZ+XkJTnXsHTEU9BWkU9h8dRMmRt8Dj8kgU NQ9nN39vYPV39KVh/qvixJt82x/SxOZc71TOnbfMKf3FqGkMZsoK3ForcUVumc7Bfesd oOwphycm3qzDfTv8y4ga05MJTVGkbW7nWCIEGDTFq2PN9/V6SomBHiuyx6SJN0M3HNwX 15rQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DlbdVeji; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 26/60] target/hppa: Make hppa_cpu_tlb_fill sysemu only Date: Tue, 2 Nov 2021 07:07:06 -0400 Message-Id: <20211102110740.215699-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82e; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for hppa linux-user. Remove the code from cpu_loop that raised SIGSEGV. This makes all of the code in mem_helper.c sysemu only, so remove the ifdefs and move the file to hppa_softmmu_ss. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 +- linux-user/hppa/cpu_loop.c | 16 ---------------- target/hppa/cpu.c | 2 +- target/hppa/mem_helper.c | 15 --------------- target/hppa/meson.build | 6 ++++-- 5 files changed, 6 insertions(+), 35 deletions(-) -- 2.25.1 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index d3cb7a279f..294fd7297f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -323,10 +323,10 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); +#ifndef CONFIG_USER_ONLY bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -#ifndef CONFIG_USER_ONLY void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 81607a9b27..e0a62deeb9 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -144,22 +144,6 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f = env->gr[31]; env->iaoq_b = env->gr[31] + 4; break; - case EXCP_ITLB_MISS: - case EXCP_DTLB_MISS: - case EXCP_NA_ITLB_MISS: - case EXCP_NA_DTLB_MISS: - case EXCP_IMP: - case EXCP_DMP: - case EXCP_DMB: - case EXCP_PAGE_REF: - case EXCP_DMAR: - case EXCP_DMPI: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr = env->cr[CR_IOR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_UNALIGN: info.si_signo = TARGET_SIGBUS; info.si_errno = 0; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 89cba9d7a2..23eb254228 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -145,9 +145,9 @@ static const struct SysemuCPUOps hppa_sysemu_ops = { static const struct TCGCPUOps hppa_tcg_ops = { .initialize = hppa_translate_init, .synchronize_from_tb = hppa_cpu_synchronize_from_tb, - .tlb_fill = hppa_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = hppa_cpu_tlb_fill, .cpu_exec_interrupt = hppa_cpu_exec_interrupt, .do_interrupt = hppa_cpu_do_interrupt, .do_unaligned_access = hppa_cpu_do_unaligned_access, diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index afc5b56c3e..bf07445cd1 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -24,20 +24,6 @@ #include "hw/core/cpu.h" #include "trace.h" -#ifdef CONFIG_USER_ONLY -bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - HPPACPU *cpu = HPPA_CPU(cs); - - /* ??? Test between data page fault and data memory protection trap, - which would affect si_code. */ - cs->exception_index = EXCP_DMP; - cpu->env.cr[CR_IOR] = address; - cpu_loop_exit_restore(cs, retaddr); -} -#else static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) { int i; @@ -392,4 +378,3 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr) hppa_tlb_entry *ent = hppa_find_tlb(env, vaddr); return ent ? ent->ar_type : -1; } -#endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/meson.build b/target/hppa/meson.build index 8a7ff82efc..021e42a2d0 100644 --- a/target/hppa/meson.build +++ b/target/hppa/meson.build @@ -7,13 +7,15 @@ hppa_ss.add(files( 'gdbstub.c', 'helper.c', 'int_helper.c', - 'mem_helper.c', 'op_helper.c', 'translate.c', )) hppa_softmmu_ss = ss.source_set() -hppa_softmmu_ss.add(files('machine.c')) +hppa_softmmu_ss.add(files( + 'machine.c', + 'mem_helper.c', +)) target_arch += {'hppa': hppa_ss} target_softmmu_arch += {'hppa': hppa_softmmu_ss} From patchwork Tue Nov 2 11:07:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516635 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4403659iml; Tue, 2 Nov 2021 04:20:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzMyTxqNpAasTs+sWHCDCLLeiS5lERA+UHMF0SWa1NlwR4JGa2xpgJ7vKLP9F1HtIvHvGyj X-Received: by 2002:aca:db8a:: with SMTP id s132mr4260918oig.119.1635852015501; Tue, 02 Nov 2021 04:20:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852015; cv=none; d=google.com; s=arc-20160816; b=RpBFjL4122rnKKKLqB0fE8bcfuem/qei5kuoN02juWgFcFHeePu0mC2MNGCrcbvCrl IHkasFzd5z0KBjbYTwXVkZw1HAWTxCTZuKbgHhvThe+vfPjKrPiZ0Ndz/Q0fh/B7HBG2 BUJQffycoib1CkZAfeBM5GgCeKF5i7tbsuWmT4ykPDZRB4fTtAlpMbcey/MguXICcnZg w7NbWHD1Rmv8FLuk57XviP4R7GICG2WQ7guXoRLs5jqDWaE3o14yyFw3ZLEX9xYqFoeG tV5BIiCayy767guLDtwOg7rvgyOqVmHpi6Qz1wfoH0TNqKx3AYX27az9/6U9mJqH2PqV cY5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Bcv7+vrfVWDaxhREKP7oW3QycojCjuZf0xWMtNuZYi8=; b=Lv0r4jV16Rgnn7x5ptBGpr2QG1sVBddUhDA/dP7hhB4sb/cvDjR5VTzgGlZcJfzilf UYiPnWsXu/2g5okMX3eaT5Lz1+r5SK9DSb+w7/uroM3daqJECFKXCaTevQUUWtaKAvsR KZHVW5BXzKhkP2vPPwM5e/RS9OWDjhatA4YmNWQyPLcttaFiGk7MIXPGPcn9Tg0kBEfw deoau2xvHWS6JlSrfAT1sbj2m8wGwgiejY1Np5IQWGfTllNU69TiqAPtbZSS3tWWFZUA 1msVpr2W/HyS24NSjv3TCThkFP5AZ19RAl2XaV2xHVEhnDzEWQeMgzsnvbxzcraW5Nqs trnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VhhMXEt1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 27/60] target/i386: Implement x86_cpu_record_sigsegv Date: Tue, 2 Nov 2021 07:07:07 -0400 Message-Id: <20211102110740.215699-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72e; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Record cr2, error_code, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. Use the maperr parameter to properly set PG_ERROR_P_MASK. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/i386/tcg/helper-tcg.h | 6 ++++++ target/i386/tcg/tcg-cpu.c | 3 ++- target/i386/tcg/user/excp_helper.c | 23 +++++++++++++++++------ 3 files changed, 25 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 60ca09e95e..0a4401e917 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -43,9 +43,15 @@ bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); #endif /* helper.c */ +#ifdef CONFIG_USER_ONLY +void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif void breakpoint_handler(CPUState *cs); diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 3ecfae34cb..6fdfdf9598 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -72,10 +72,11 @@ static const struct TCGCPUOps x86_tcg_ops = { .synchronize_from_tb = x86_cpu_synchronize_from_tb, .cpu_exec_enter = x86_cpu_exec_enter, .cpu_exec_exit = x86_cpu_exec_exit, - .tlb_fill = x86_cpu_tlb_fill, #ifdef CONFIG_USER_ONLY .fake_user_interrupt = x86_cpu_do_interrupt, + .record_sigsegv = x86_cpu_record_sigsegv, #else + .tlb_fill = x86_cpu_tlb_fill, .do_interrupt = x86_cpu_do_interrupt, .cpu_exec_interrupt = x86_cpu_exec_interrupt, .debug_excp_handler = breakpoint_handler, diff --git a/target/i386/tcg/user/excp_helper.c b/target/i386/tcg/user/excp_helper.c index a89b5228fd..cd507e2a1b 100644 --- a/target/i386/tcg/user/excp_helper.c +++ b/target/i386/tcg/user/excp_helper.c @@ -22,18 +22,29 @@ #include "exec/exec-all.h" #include "tcg/helper-tcg.h" -bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra) { X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; + /* + * The error_code that hw reports as part of the exception frame + * is copied to linux sigcontext.err. The exception_index is + * copied to linux sigcontext.trapno. Short of inventing a new + * place to store the trapno, we cannot let our caller raise the + * signal and set exception_index to EXCP_INTERRUPT. + */ env->cr[2] = addr; - env->error_code = (access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT; - env->error_code |= PG_ERROR_U_MASK; + env->error_code = ((access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT) + | (maperr ? 0 : PG_ERROR_P_MASK) + | PG_ERROR_U_MASK; cs->exception_index = EXCP0E_PAGE; + + /* Disable do_interrupt_user. */ env->exception_is_int = 0; env->exception_next_eip = -1; - cpu_loop_exit_restore(cs, retaddr); + + cpu_loop_exit_restore(cs, ra); } From patchwork Tue Nov 2 11:07:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516656 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4416817iml; Tue, 2 Nov 2021 04:33:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwxPDjKcomXjgZ4Byhg2V5+keFZYGfBnDDpkcwwFfmDvZgD92xLp1K2EY2bAu9xSPWZuM4Z X-Received: by 2002:a05:6830:1c64:: with SMTP id s4mr25254937otg.174.1635852833538; Tue, 02 Nov 2021 04:33:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852833; cv=none; d=google.com; s=arc-20160816; b=ig7UyoG8sorlNTGxaqhcrY+rjN98xBHAjsMw8MLfskZ0hgrDskqBsMvnXUvJHwFKgT SOeoi0JNssImj6jIWuu7AAtzVkSBFAgR/63qC8LOTzhF5++rKdAoZwybh29uZn/aqEeP c13LsxJy4IAvSjVJAOMOMs87FxtBRY89+f6AWtkupWryitv7BS/NKqW/ETvTlTexcCcq MuaPATMz2I2m6BMbZgSnaLyMAvSimwg2/0Mw32BE4CkHAJOet0HlmhkXquZ7nKenXN5F K/blbYSrNSJ0r1515G3JF9l0zb1XM98x99puJaGXKTqB3bfM2CLOAbIqmHFWE7oOa7MH MtLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/utnMsLyouv7LilvnHYZPxrZ8zRoC/jZ7xS1qGJE894=; b=LhVJNKvG9D+SIwOhyCODvvF4sacefMu+kNd4M4sijVB2WPBHY7HWH72k1233HPR8yi zje22KICuw5hxYDB71ctwx3Gxa6CaTkTthF7aoGCDyiW9pr8pi9o2UiTuHgSjfecKk+o aB80Od6NWEKDAazXXO2oyu78p3MHF87qfJMyhCBzuWuBmCGtsAUaSYPzK+d6Ri3yLlXf WhS5ltzsFqD0dvLUEAEIYfpKRLY60wZY8bzeVqEsZ6a7dTiQY19iJSikim53SNbi4TC8 x1NlJXqlUt57NQ6lMCq6B+MVag+L88SVWzH9h39UA4pAUsxhy/q78nFke+UjeclZ+H27 E8PQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RCZurs00; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 28/60] target/m68k: Make m68k_cpu_tlb_fill sysemu only Date: Tue, 2 Nov 2021 07:07:08 -0400 Message-Id: <20211102110740.215699-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82a; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for m68k linux-user. Remove the code from cpu_loop that handled EXCP_ACCESS. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 10 ---------- target/m68k/cpu.c | 2 +- target/m68k/helper.c | 6 +----- 3 files changed, 2 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index ebf32be78f..790bd558c3 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -90,16 +90,6 @@ void cpu_loop(CPUM68KState *env) case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; - case EXCP_ACCESS: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->mmu.ar; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_DEBUG: info.si_signo = TARGET_SIGTRAP; info.si_errno = 0; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 66d22d1189..c7aeb7da9c 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -515,9 +515,9 @@ static const struct SysemuCPUOps m68k_sysemu_ops = { static const struct TCGCPUOps m68k_tcg_ops = { .initialize = m68k_tcg_init, - .tlb_fill = m68k_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = m68k_cpu_tlb_fill, .cpu_exec_interrupt = m68k_cpu_exec_interrupt, .do_interrupt = m68k_cpu_do_interrupt, .do_transaction_failed = m68k_cpu_transaction_failed, diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 137a3e1a3d..5728e48585 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -978,16 +978,12 @@ void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector) } } -#endif - bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType qemu_access_type, int mmu_idx, bool probe, uintptr_t retaddr) { M68kCPU *cpu = M68K_CPU(cs); CPUM68KState *env = &cpu->env; - -#ifndef CONFIG_USER_ONLY hwaddr physical; int prot; int access_type; @@ -1051,12 +1047,12 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (!(access_type & ACCESS_STORE)) { env->mmu.ssw |= M68K_RW_040; } -#endif cs->exception_index = EXCP_ACCESS; env->mmu.ar = address; cpu_loop_exit_restore(cs, retaddr); } +#endif /* !CONFIG_USER_ONLY */ uint32_t HELPER(bitrev)(uint32_t x) { From patchwork Tue Nov 2 11:07:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516657 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4417009iml; Tue, 2 Nov 2021 04:34:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJynJlt/vmen2UmLrv+yYF7NxR8twxPvp+o19KfbecTFxkAEGlknWyiiCDuZTjQjukG2d6Wv X-Received: by 2002:a05:6830:3498:: with SMTP id c24mr11545700otu.263.1635852844296; Tue, 02 Nov 2021 04:34:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852844; cv=none; d=google.com; s=arc-20160816; b=Wm8DoxZvV4yC00jUaWy+6oKoOMfs8Ubf0EhkWNejGFDErCoYZDUJbKCaN+p4ykjTIW SlR7bty5u8cpxymRHGAUddB42HIYR+KEGdDqoHD0PWJijZvnU6W4/72jf1A4tNozq0vy MWk5qdiEUxW+cEBIAEiBzasPDEicHKDXBMyo7ejOxbLZULFcgVq9ObaNyQaE4GcUt2OP 2xqbMMwb/yyO7st4g5dfEw2C2mVbyam57yD0yAHMh9mrmyRpnCIGLMDbQjXWjHx+vPb3 MvyXf+yQswBnUfRAYdqW5H6Q400bjojR2FFwvANNXgv+RSehc1EkJwja2uKT/zgMm0RC Kbxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Wm8ynGMh6kJsv+mBV6l6SdFFT71ClM8AMZtK4AOJ7uE=; b=YwZ3uhxr/EQFaDR1cXlGSoH0XgEMSH/eOoKaWWJBpJVWMSWWwsvqEdVoW8eL1igaJw fUaVgPwE6vZrhbGfvkP/BDMancJ6Cz51CWaD5l+AaAx/1oZfm5dx6yfaE39swqnT3JCb Yr7Mkmv4YFb2yJnae0avSXW3FC2gYS1/zSoC/r456CKkphb/5ZK1iOCnEXASDE1/hLWt 0na/z7VX2pU4KYk1XdrjGcM6+/Yt1OSfV0zYyp1tUOguwDPbHBcHkkOKrq7bGMRHoPI2 qF++zgYmWrgyONu++H43YDFqYpA5RUVrP4xaaH3kMM65qdKiIP8OFjnXyS7avYJYZ8Sj JH3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="ucLC/rW2"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 29/60] target/microblaze: Make mb_cpu_tlb_fill sysemu only Date: Tue, 2 Nov 2021 07:07:09 -0400 Message-Id: <20211102110740.215699-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72c; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for microblaze linux-user. Remove the code from cpu_loop that handled the unnamed 0xaa exception. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 8 ++++---- linux-user/microblaze/cpu_loop.c | 10 ---------- target/microblaze/cpu.c | 2 +- target/microblaze/helper.c | 13 +------------ 4 files changed, 6 insertions(+), 27 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b7a848bbae..e9cd0b88de 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -394,10 +394,6 @@ void mb_tcg_init(void); #define MMU_USER_IDX 2 /* See NB_MMU_MODES further up the file. */ -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); - typedef CPUMBState CPUArchState; typedef MicroBlazeCPU ArchCPU; @@ -415,6 +411,10 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, } #if !defined(CONFIG_USER_ONLY) +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index 52222eb93f..a94467dd2d 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -37,16 +37,6 @@ void cpu_loop(CPUMBState *env) process_queued_cpu_work(cs); switch (trapnr) { - case 0xaa: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = 0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 15db277925..b9c888b87e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -365,9 +365,9 @@ static const struct SysemuCPUOps mb_sysemu_ops = { static const struct TCGCPUOps mb_tcg_ops = { .initialize = mb_tcg_init, .synchronize_from_tb = mb_cpu_synchronize_from_tb, - .tlb_fill = mb_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = mb_cpu_tlb_fill, .cpu_exec_interrupt = mb_cpu_exec_interrupt, .do_interrupt = mb_cpu_do_interrupt, .do_transaction_failed = mb_cpu_transaction_failed, diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index dd2aecd1d5..a607fe68e5 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -24,18 +24,7 @@ #include "qemu/host-utils.h" #include "exec/log.h" -#if defined(CONFIG_USER_ONLY) - -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - cs->exception_index = 0xaa; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - +#ifndef CONFIG_USER_ONLY static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu, MMUAccessType access_type) { From patchwork Tue Nov 2 11:07:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516666 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4430795iml; Tue, 2 Nov 2021 04:48:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyTPFeilxcIgMaqBTctmwnXxzvJCtQzzHzx6xE8iMjPTtw/4JtJRmHSPhna4AxecOUWwqSn X-Received: by 2002:a9d:4b17:: with SMTP id q23mr18971923otf.127.1635853709629; Tue, 02 Nov 2021 04:48:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635853709; cv=none; d=google.com; s=arc-20160816; b=C/WpBEJaVvXusbx7tVwAvJ+wFzc+H/5W+UvCYtivkj8iVSbIQMXpYhmMFhTR5pC28W 0d1ms726TW+km/GAseYHrLql9GX9r4Fdj0zRndnWWmNEdTlgEXLI3LZFNe7gNei8j5qc TgxN5s8R3tUdHZQ3UjNlwvKGwIy6UQvLA4hrvpgsbX07AJLGcWLBGcGoNAq/fM8Fil9a 28zO8Jh+nGSOfpt7TvR7/PcLzNFEPiemnZX98/zf4h4gWX1dA/Uec2G6anGORZP/sdGS IeyvXsLg+sSHBhQbprs3fzeif4RXJGUs9M4fdj2XPbMTS68j+mylYFkeZmAQliPqm5UN w6Tg== ARC-Message-Signature: i=1; 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 30/60] target/mips: Make mips_cpu_tlb_fill sysemu only Date: Tue, 2 Nov 2021 07:07:10 -0400 Message-Id: <20211102110740.215699-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72d; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for mips linux-user. This means we can remove tcg/user/tlb_helper.c entirely. Remove the code from cpu_loop that raised SIGSEGV. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/tcg/tcg-internal.h | 7 ++-- linux-user/mips/cpu_loop.c | 11 ------ target/mips/cpu.c | 2 +- target/mips/tcg/user/tlb_helper.c | 59 ------------------------------- target/mips/tcg/meson.build | 3 -- target/mips/tcg/user/meson.build | 3 -- 6 files changed, 5 insertions(+), 80 deletions(-) delete mode 100644 target/mips/tcg/user/tlb_helper.c delete mode 100644 target/mips/tcg/user/meson.build -- 2.25.1 diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index bad3deb611..466768aec4 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -18,9 +18,6 @@ void mips_tcg_init(void); void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; @@ -60,6 +57,10 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, MemTxResult response, uintptr_t retaddr); void cpu_mips_tlb_flush(CPUMIPSState *env); +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + #endif /* !CONFIG_USER_ONLY */ #endif diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index cb03fb066b..b735c99a24 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -158,17 +158,6 @@ done_syscall: } env->active_tc.gpr[2] = ret; break; - case EXCP_TLBL: - case EXCP_TLBS: - case EXCP_AdEL: - case EXCP_AdES: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->CP0_BadVAddr; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_CpU: case EXCP_RI: info.si_signo = TARGET_SIGILL; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 00e0c55d0e..4aae23934b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -539,9 +539,9 @@ static const struct SysemuCPUOps mips_sysemu_ops = { static const struct TCGCPUOps mips_tcg_ops = { .initialize = mips_tcg_init, .synchronize_from_tb = mips_cpu_synchronize_from_tb, - .tlb_fill = mips_cpu_tlb_fill, #if !defined(CONFIG_USER_ONLY) + .tlb_fill = mips_cpu_tlb_fill, .cpu_exec_interrupt = mips_cpu_exec_interrupt, .do_interrupt = mips_cpu_do_interrupt, .do_transaction_failed = mips_cpu_do_transaction_failed, diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_helper.c deleted file mode 100644 index 210c6d529e..0000000000 --- a/target/mips/tcg/user/tlb_helper.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * MIPS TLB (Translation lookaside buffer) helpers. - * - * Copyright (c) 2004-2005 Jocelyn Mayer - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ -#include "qemu/osdep.h" - -#include "cpu.h" -#include "exec/exec-all.h" -#include "internal.h" - -static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type) -{ - CPUState *cs = env_cpu(env); - - env->error_code = 0; - if (access_type == MMU_INST_FETCH) { - env->error_code |= EXCP_INST_NOTAVAIL; - } - - /* Reference to kernel address from user mode or supervisor mode */ - /* Reference to supervisor address from user mode */ - if (access_type == MMU_DATA_STORE) { - cs->exception_index = EXCP_AdES; - } else { - cs->exception_index = EXCP_AdEL; - } - - /* Raise exception */ - if (!(env->hflags & MIPS_HFLAG_DM)) { - env->CP0_BadVAddr = address; - } -} - -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - - /* data access */ - raise_mmu_exception(env, address, access_type); - do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr); -} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 8f6f7508b6..98003779ae 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -28,9 +28,6 @@ mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'mxu_translate.c', )) -if have_user - subdir('user') -endif if have_system subdir('sysemu') endif diff --git a/target/mips/tcg/user/meson.build b/target/mips/tcg/user/meson.build deleted file mode 100644 index 79badcd321..0000000000 --- a/target/mips/tcg/user/meson.build +++ /dev/null @@ -1,3 +0,0 @@ -mips_user_ss.add(files( - 'tlb_helper.c', -)) From patchwork Tue Nov 2 11:07:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516673 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4435745iml; Tue, 2 Nov 2021 04:53:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyAz6BZMAm9JPPtiSrQNB/fzhlN4kEvkfeiDjx2VtLageggniJ9+UBpFfts2HhomWKt1Kz9 X-Received: by 2002:a9d:67c3:: with SMTP id c3mr1483816otn.350.1635854029044; Tue, 02 Nov 2021 04:53:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635854029; cv=none; d=google.com; s=arc-20160816; b=ILf8/sgndqg7udKW+JmPFzB9tHGTcBJlworg4vO6odWQvWkzc1qvDRhJQIoEbv4cmJ OtAV1nNYr7KSjAKuSicQRPrQb6souFE6jPovbenABBvVWur8ZKaisFbmCjwTQNQZS9Oh LkF4WP0bnZdDfUe7bhl1eQ+KtUg9MpxYlHrCh+ONsb1C3GzVLk35iUFNLiLT2JrYZCnZ uVEsQWg4G+YMgvd2dhwqw/hAT3XWhdhU9uQBGaSoeDUiNL+zAISZh+9L1GtW3JRD9vgz wB9+0HO8JQz2Qcn2pLvmDPn06eMSiz/UzWYLfIuECBTxFCsClQD8vQjMtUndo6SK5R+g aPlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zhmoQq400LN3ckB+F14vIMLu76bali80G5XXiJl040k=; b=TBp5wpm46Q+Jp2CwoBRPlJE3adMaVZrXtzFJtc3AQ5IrrJ18Qqi6UovFkavJJO+qWA LjGtmw9on9J6C8f8it2uXmabDhUaTjZaTM8xI/Y+hb5DLZJAMbjDIZmYSf7hIxnFP+0v +lX+IjZkWyEqlmXgf687ggtmn2KO3UIBIgrkyjOU0Pn3gd+1RthfQI8J3u5ci4LRVINQ RVIWpTKIx5beLrLBqhMKtDvOKn0a56vQwtVx0AMoZTWkDTiXYRMpp1HROysO9fAcniEs CkcX93D0YK28euVdbxdXsT/ziXp5DTQluDlYxVba+XkAQIEbFBxej6g4cMQtFIJp46ca Dz+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s7z92tkr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.07.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:07:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 31/60] target/nios2: Implement nios2_cpu_record_sigsegv Date: Tue, 2 Nov 2021 07:07:11 -0400 Message-Id: <20211102110740.215699-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72a; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because the linux-user kuser page handling is currently implemented by detecting magic addresses in the unnamed 0xaa trap, we cannot simply remove nios2_cpu_tlb_fill and rely on the fallback code. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 6 ++++++ target/nios2/cpu.c | 6 ++++-- target/nios2/helper.c | 7 ++++--- 3 files changed, 14 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index a80587338a..1a69ed7a49 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -218,9 +218,15 @@ static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) MMU_SUPERVISOR_IDX; } +#ifdef CONFIG_USER_ONLY +void nios2_cpu_record_sigsegv(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif static inline int cpu_interrupts_enabled(CPUNios2State *env) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 58ecd27d75..4cade61e93 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -216,9 +216,11 @@ static const struct SysemuCPUOps nios2_sysemu_ops = { static const struct TCGCPUOps nios2_tcg_ops = { .initialize = nios2_tcg_init, - .tlb_fill = nios2_cpu_tlb_fill, -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv = nios2_cpu_record_sigsegv, +#else + .tlb_fill = nios2_cpu_tlb_fill, .cpu_exec_interrupt = nios2_cpu_exec_interrupt, .do_interrupt = nios2_cpu_do_interrupt, .do_unaligned_access = nios2_cpu_do_unaligned_access, diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 53be8398e9..e5c98650e1 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -38,10 +38,11 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[R_EA] = env->regs[R_PC] + 4; } -bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { + /* FIXME: Disentangle kuser page from linux-user sigsegv handling. */ cs->exception_index = 0xaa; cpu_loop_exit_restore(cs, retaddr); } From patchwork Tue Nov 2 11:07:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516676 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4437845iml; Tue, 2 Nov 2021 04:56:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw0ietfNvAQ6otg9pNKqSk8MrBmNCe35kiijv+BOYEkcGhcXmqGp/jZobjLQ4QyDKEVMkfJ X-Received: by 2002:a05:6808:130d:: with SMTP id y13mr4705611oiv.160.1635854183798; Tue, 02 Nov 2021 04:56:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635854183; cv=none; d=google.com; s=arc-20160816; b=ahvFDvXkwRfHd8HV5OwqdhNkiPhD4jdMLWKxxLyvYkDnhMazfvgFHh9yYRQ3FeeDF5 PllOEQRnKx8U9i/rSsIogA38WwxL9sHIEkojr/NIKFKf5PaE1ZTvtqtbjyvGA86+qrli dlN3+ET1UVOiMvxL9woFVbJE7zuNo8A7e0RZZ+FWYr3/PgTXclZPspCtOuOZnhYli0+Q P2Kqv0dM9Qsg0lt7oCQ1JQE6iOlhY26KY2gVV/qa6qEt1pQQhS6vYd9cUBTy2d+T4PPJ dpPeQV6WNZKNvNuHFsUtnerLHzKFAJIhAxGzqGysMzwHyVTJPq1bmW2EsCMSyLKojpU9 EevA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mXI5pLklfarH8j3WhgGW5xn4dLCOLkkDAfhYzkOpzbo=; b=KgPDn6PBidvEatoMcHiIapVyxKKrTSAhLf9rzGHbNTaMXewkIYkFn3ozTurfjvumTc tdAYc8xJpUeD5bKQwRFwcK/ob7lyTJ1njcDBAKwuqw2qXVGnujQiCYj14NpB5ixcpDLE 1SJCaXPz5LYGYqAqe9ea83DKOPjMeBi4BtuPHcUGLJT6xdeU/GRUyuULxeQ+I5QJ8pHC g5B22RK4WnxT5qKfKEVuNkfA2iVmaOnKcppD3XTwJQxrjDgfYnp77RRK28PK2lZc5MIN G33tH+QpOMxinTd+vrKei7GH3Em5B4G4kqS1jjF/Wp5eyARHzZ8/VA8tSI2defay5ysT mIUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pnWkhqvB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.08.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:08:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 32/60] linux-user/openrisc: Abort for EXCP_RANGE, EXCP_FPE Date: Tue, 2 Nov 2021 07:07:12 -0400 Message-Id: <20211102110740.215699-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::833; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x833.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" QEMU does not allow the system control bits for either exception to be enabled in linux-user, therefore both exceptions are dead code. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/openrisc/cpu_loop.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index f6360db47c..10b7147f68 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -56,7 +56,6 @@ void cpu_loop(CPUOpenRISCState *env) break; case EXCP_DPF: case EXCP_IPF: - case EXCP_RANGE: info.si_signo = TARGET_SIGSEGV; info.si_errno = 0; info.si_code = TARGET_SEGV_MAPERR; @@ -77,13 +76,6 @@ void cpu_loop(CPUOpenRISCState *env) info._sifields._sigfault._addr = env->pc; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case EXCP_FPE: - info.si_signo = TARGET_SIGFPE; - info.si_errno = 0; - info.si_code = 0; - info._sifields._sigfault._addr = env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_INTERRUPT: /* We processed the pending cpu work above. */ break; @@ -96,6 +88,15 @@ void cpu_loop(CPUOpenRISCState *env) case EXCP_ATOMIC: cpu_exec_step_atomic(cs); break; + case EXCP_RANGE: + /* Requires SR.OVE set, which linux-user won't do. */ + cpu_abort(cs, "Unexpected RANGE exception"); + case EXCP_FPE: + /* + * Requires FPSCR.FPEE set. Writes to FPSCR from usermode not + * yet enabled in kernel ABI, so linux-user does not either. + */ + cpu_abort(cs, "Unexpected FPE exception"); default: g_assert_not_reached(); } From patchwork Tue Nov 2 11:07:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516654 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4416409iml; Tue, 2 Nov 2021 04:33:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzrTn44DKtLhAsOcjC7Lvgwi/WYZxbioFQs9gi8/T/wwICDn2uOdG5VFZzMn8i+9o2baxtL X-Received: by 2002:aca:90e:: with SMTP id 14mr4611938oij.170.1635852806494; Tue, 02 Nov 2021 04:33:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852806; cv=none; d=google.com; s=arc-20160816; b=vOYbwW0ZbNeYED8sKffTMkQLpAtM1s+vTKsyGLoaNu17pJ1WXkZrmC0DNbqsrxh0tH 7PqmgNeZebAm8zvoWKd1nABW+/vyyM84tZgpVPAnyPcbzx8OCvAnc0B2+dsTSZtduQjO Jd0haLx7hhYOKIwDPh1UAhX/tdZ1n4y3NyzAeQ22IgJeGsTAeGltxt+d+2oIBU1WpH1C 7g0++1w3rrNloUGxmgxbpgckCXvOQxQ1Ac/Exrl/iqQAuP/j4vOYm9re82Ce0sSS4BAX OJmmf9dcZxaCTqCn8cPH9/rVyRWww8/KiD42jMQTvpZGND8M8eWfm6XJoZok7sOjuS8p NBqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pnbVDz2F7bl2MnMZvXAf7/LYYOvOlpdsDMsaNKSumSw=; b=NPjqCMMEiY2jk6jeUs50V8+LjCVJmyIyPrA7zPDmojvNYrTkqZnfdwzQhNm2m6lQJX jersA1YbFtpRf1z/zdIN/YwlY4Z7BseQhr1iR/REJw+gAs1yXHeZN8VZnicwnAE4FRgX U4QwGY7c897TmWBbgTpvJ23tbcxjfDHC83AfHCLiIhSRwUdB/bHa1aiCzNBBl2zBuRzi RednRNX56Qb2JpH1bMf7Ci3kfAGssZ69kNnZKW3vq50l/Ti6MdWaOhowVM1uNO+7lRUZ 8/91CQZawB5uvwlmNkBeeV3NI4zEh/vaZs0fzj8aJHq9wVeX7+Hn49HGDWAfe0XGJLS9 JGcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gzCYzORV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.08.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:08:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 33/60] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Date: Tue, 2 Nov 2021 07:07:13 -0400 Message-Id: <20211102110740.215699-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2c; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for openrisc linux-user. This makes all of the code in mmu.c sysemu only, so remove the ifdefs and move the file to openrisc_softmmu_ss. Remove the code from cpu_loop that handled EXCP_DPF. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 7 ++++--- linux-user/openrisc/cpu_loop.c | 8 -------- target/openrisc/cpu.c | 2 +- target/openrisc/mmu.c | 9 --------- target/openrisc/meson.build | 2 +- 5 files changed, 6 insertions(+), 22 deletions(-) -- 2.25.1 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 187a4a114e..ee069b080c 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -317,14 +317,15 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); -bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); int print_insn_or1k(bfd_vma addr, disassemble_info *info); #define cpu_list cpu_openrisc_list #ifndef CONFIG_USER_ONLY +bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + extern const VMStateDescription vmstate_openrisc_cpu; void openrisc_cpu_do_interrupt(CPUState *cpu); diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index 10b7147f68..3cfdbbf037 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -54,14 +54,6 @@ void cpu_loop(CPUOpenRISCState *env) cpu_set_gpr(env, 11, ret); } break; - case EXCP_DPF: - case EXCP_IPF: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_ALIGN: info.si_signo = TARGET_SIGBUS; info.si_errno = 0; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 27cb04152f..dfbafc5236 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -186,9 +186,9 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { static const struct TCGCPUOps openrisc_tcg_ops = { .initialize = openrisc_translate_init, - .tlb_fill = openrisc_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = openrisc_cpu_tlb_fill, .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, .do_interrupt = openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 94df8c7bef..e561ef245b 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -23,11 +23,8 @@ #include "exec/exec-all.h" #include "exec/gdbstub.h" #include "qemu/host-utils.h" -#ifndef CONFIG_USER_ONLY #include "hw/loader.h" -#endif -#ifndef CONFIG_USER_ONLY static inline void get_phys_nommu(hwaddr *phys_addr, int *prot, target_ulong address) { @@ -94,7 +91,6 @@ static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot, return need & PAGE_EXEC ? EXCP_ITLBMISS : EXCP_DTLBMISS; } } -#endif static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, int exception) @@ -112,8 +108,6 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, { OpenRISCCPU *cpu = OPENRISC_CPU(cs); int excp = EXCP_DPF; - -#ifndef CONFIG_USER_ONLY int prot; hwaddr phys_addr; @@ -138,13 +132,11 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, if (probe) { return false; } -#endif raise_mmu_exception(cpu, addr, excp); cpu_loop_exit_restore(cs, retaddr); } -#ifndef CONFIG_USER_ONLY hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { OpenRISCCPU *cpu = OPENRISC_CPU(cs); @@ -177,4 +169,3 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } } -#endif diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build index e445dec4a0..84322086ec 100644 --- a/target/openrisc/meson.build +++ b/target/openrisc/meson.build @@ -10,7 +10,6 @@ openrisc_ss.add(files( 'fpu_helper.c', 'gdbstub.c', 'interrupt_helper.c', - 'mmu.c', 'sys_helper.c', 'translate.c', )) @@ -19,6 +18,7 @@ openrisc_softmmu_ss = ss.source_set() openrisc_softmmu_ss.add(files( 'interrupt.c', 'machine.c', + 'mmu.c', )) target_arch += {'openrisc': openrisc_ss} From patchwork Tue Nov 2 11:07:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516650 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4413950iml; Tue, 2 Nov 2021 04:31:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwyXa56VTnQ+nvRGRlXdGwgxVgKyjK+Ki+DUVCvL8eKi20NVVTOLPeCcCPDmPUGb961Qn0v X-Received: by 2002:a05:6830:2aa5:: with SMTP id s37mr15175116otu.299.1635852666488; Tue, 02 Nov 2021 04:31:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852666; cv=none; d=google.com; s=arc-20160816; b=zxc+IbBOLwky1q6mI6BWLC/y0qZ/xgVKw34BmNde+qcKJ6OLCnnzaDKYC1h2R07c7N c/NIER8UqUVqPz8wM6+LM2HSzsjsPPeUsZyCl28D2VQ1ihG2Uz1WEdR9AGDZ+QrKdxGZ ZtvEL59Tl7OMyqIIIu29ZI8Uxu/fQlHM7rsJXnfc6NIeaFW8pKqrgD3bVb6v3GnrWJ+j pBjaIAyk183u4q8Jz7L/35l7Ysuyzf20051kmIPhwNckk0pXvQS4157/ewoiwNugM05E uMrBL+qWbU7u15/Dyta2wUhWw0MBZwnN8OlyAT+l4HioxQddxuP8qFUYhj+VW9OP31Fe VIEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=b7jpFgMMciMmW9Xl8VdlfSERFh4gLfLYDvd7byDKhQQ=; b=ziLM5A4Egq6ovmBb4xPKgOmYajg2m6JRVoR++B1dr6+MxqOPyQ67J5RVjGm9UWeNIa QQQ5WK7PFUaQNsDseZfybdQOI0yVWGUu1jH0IFgPRdMOzI9CFjOhF92vB/9dMiMtUUwK gs4Tddmg3XOgPhw2qY/h9fsUINykYW4y6MeZdMU5fF8Dmy2xrPnztFNKUlIaPHCEKqv0 7aUt7Lii89sqVB37vntBkyN7Sroqad7G+RMOkfHY1CrAs/3vJEHA2gZDqD2W4viKPNAu YD5iDGhJqQ9xlry96Py0uhFjOLcNbXb6tU9pDSwBPEoM5MbrjQ4C7U0xu/CQdwyaeD9M zDOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=w7Pm78Lu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.08.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:08:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 34/60] target/ppc: Implement ppc_cpu_record_sigsegv Date: Tue, 2 Nov 2021 07:07:14 -0400 Message-Id: <20211102110740.215699-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Record DAR, DSISR, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. This is exactly what the user-mode ppc_cpu_tlb_fill does, so simply rename it as ppc_cpu_record_sigsegv. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 3 --- target/ppc/internal.h | 9 +++++++++ target/ppc/cpu_init.c | 6 ++++-- target/ppc/user_only_helper.c | 15 +++++++++++---- 4 files changed, 24 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 0472ec9154..e946da5f3a 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1302,9 +1302,6 @@ extern const VMStateDescription vmstate_ppc_cpu; /*****************************************************************************/ void ppc_translate_init(void); -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); #if !defined(CONFIG_USER_ONLY) void ppc_store_sdr1(CPUPPCState *env, target_ulong value); diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 55284369f5..339974b7d8 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -283,5 +283,14 @@ static inline void pte_invalidate(target_ulong *pte0) #define PTE_PTEM_MASK 0x7FFFFFBF #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) +#ifdef CONFIG_USER_ONLY +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#endif #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 65545ba9ca..1c7a7b4b38 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -9014,9 +9014,11 @@ static const struct SysemuCPUOps ppc_sysemu_ops = { static const struct TCGCPUOps ppc_tcg_ops = { .initialize = ppc_translate_init, - .tlb_fill = ppc_cpu_tlb_fill, -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv = ppc_cpu_record_sigsegv, +#else + .tlb_fill = ppc_cpu_tlb_fill, .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .do_interrupt = ppc_cpu_do_interrupt, .cpu_exec_enter = ppc_cpu_exec_enter, diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index aa3f867596..7ff76f7a06 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -21,16 +21,23 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "internal.h" - -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; int exception, error_code; + /* + * Both DSISR and the "trap number" (exception vector offset, + * looked up from exception_index) are present in the linux-user + * signal frame. + * FIXME: we don't actually populate the trap number properly. + * It would be easiest to fill in an env->trap value now. + */ if (access_type == MMU_INST_FETCH) { exception = POWERPC_EXCP_ISI; error_code = 0x40000000; From patchwork Tue Nov 2 11:07:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516638 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4406972iml; Tue, 2 Nov 2021 04:23:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxscO9cbL6lIc+sqykAJgq0ceSTQZSszNq/GLrjbI0NnLIIs/OaRV7Pn0oACWmaXBqLf/6m X-Received: by 2002:a9d:7dd8:: with SMTP id k24mr2936407otn.23.1635852227844; Tue, 02 Nov 2021 04:23:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.08.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:08:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 35/60] target/riscv: Make riscv_cpu_tlb_fill sysemu only Date: Tue, 2 Nov 2021 07:07:15 -0400 Message-Id: <20211102110740.215699-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2e; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for riscv linux-user. Remove the code from cpu_loop that raised SIGSEGV. Reviewed-by: Warner Losh Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/riscv/cpu_loop.c | 7 ------- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 21 +-------------------- 3 files changed, 2 insertions(+), 28 deletions(-) -- 2.25.1 diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index e5bb6d908a..b301dac802 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -87,13 +87,6 @@ void cpu_loop(CPURISCVState *env) sigcode = TARGET_TRAP_BRKPT; sigaddr = env->pc; break; - case RISCV_EXCP_INST_PAGE_FAULT: - case RISCV_EXCP_LOAD_PAGE_FAULT: - case RISCV_EXCP_STORE_PAGE_FAULT: - signum = TARGET_SIGSEGV; - sigcode = TARGET_SEGV_MAPERR; - sigaddr = env->badaddr; - break; case RISCV_EXCP_SEMIHOST: env->gpr[xA0] = do_common_semihosting(cs); env->pc += 4; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d53125dbc..f812998123 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -694,9 +694,9 @@ static const struct SysemuCPUOps riscv_sysemu_ops = { static const struct TCGCPUOps riscv_tcg_ops = { .initialize = riscv_translate_init, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, - .tlb_fill = riscv_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = riscv_cpu_tlb_fill, .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .do_interrupt = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f30ff672f8..9eeed38c7e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -814,7 +814,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, riscv_cpu_two_stage_lookup(mmu_idx); riscv_raise_exception(env, cs->exception_index, retaddr); } -#endif /* !CONFIG_USER_ONLY */ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -822,7 +821,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; -#ifndef CONFIG_USER_ONLY vaddr im_address; hwaddr pa = 0; int prot, prot2, prot_pmp; @@ -954,25 +952,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } return true; - -#else - switch (access_type) { - case MMU_INST_FETCH: - cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; - break; - case MMU_DATA_LOAD: - cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; - break; - case MMU_DATA_STORE: - cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; - break; - default: - g_assert_not_reached(); - } - env->badaddr = address; - cpu_loop_exit_restore(cs, retaddr); -#endif } +#endif /* !CONFIG_USER_ONLY */ /* * Handle Traps From patchwork Tue Nov 2 11:07:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516642 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4409606iml; Tue, 2 Nov 2021 04:26:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxSSBM+N1d3abBjszOHbFIa7YR7WKysaHNoiGJvfUz5gg77h2rianG5pHNQej6TOO8eaR8B X-Received: by 2002:aca:5f44:: with SMTP id t65mr4377801oib.97.1635852401515; Tue, 02 Nov 2021 04:26:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852401; cv=none; d=google.com; s=arc-20160816; b=dK3BJcWVJS0DjajMmmOXWXmmKhtDI2zLqjX0JsE6Uee4MNuGQXA2HhXkIY8Zq2CIJW 2Fu8gXPh/w7Ma/OdnW5n1DpUAn+iuZfMkCs+ddlBlcvEr81RkjSAC/RtQwHV+750xyj6 e89nK/j+YzBVk82Hs6xkU15SdnP/u3CHKANLNrs8+p4LfLUeopoIu/zxca294rl/TVeE gS3ryRKOZbNatbZ/q8CJPqVf/alqjHzsil1NsWuD5q72w6hgDSP6F/CIX4XN8lmWrfXD f0YFklTz2bQTIICdtqrM9W/br3iYCv0t5MLjoCRFm2H+XDe5p9OufwRM8e1lhYcnwafv GoLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ky6yY478j1xSRIHIN9BTjrdKe+bHyugXQSySqll0teU=; b=a1eBDty5dwnX9JqrDBGeeHZQy8WWEFPq6h4bJ6SWhWRXRavojOzULA/GCbFPDa+KHE hc9fqR935hibOqenqz6lci9TFCcygytys2EmsUws90tXyTUUptayVSWX5OeN27EY58AY WUjUTO9fZIn+ij9xrcuF/Rzc4CswSQ/PiKi9MT08Maug1M49UrqpbXoNjY5WpBrmNdSz Wj+enLXKFa+JZ3QSOnYVvLbKV0c3S8pfjPloAYVIG/wuuz6IR1ELDaYDpoL42cRZzuA6 KMHZxBIoJ8SIap+NQO8Wei7p6DfrlGOcaRLB2tCZId32AzrYU8Ue2UowVp6TgxjzvMF+ Kqng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CoR6ArYs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.08.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:08:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 36/60] target/s390x: Use probe_access_flags in s390_probe_access Date: Tue, 2 Nov 2021 07:07:16 -0400 Message-Id: <20211102110740.215699-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::831; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x831.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Not sure why the user-only code wasn't rewritten to use probe_access_flags at the same time that the sysemu code was converted. For the purpose of user-only, this is an exact replacement. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 17e3f83641..362a30d99e 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -141,20 +141,12 @@ static int s390_probe_access(CPUArchState *env, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t ra) { +#if defined(CONFIG_USER_ONLY) + return probe_access_flags(env, addr, access_type, mmu_idx, + nonfault, phost, ra); +#else int flags; -#if defined(CONFIG_USER_ONLY) - flags = page_get_flags(addr); - if (!(flags & (access_type == MMU_DATA_LOAD ? PAGE_READ : PAGE_WRITE_ORG))) { - env->__excp_addr = addr; - flags = (flags & PAGE_VALID) ? PGM_PROTECTION : PGM_ADDRESSING; - if (nonfault) { - return flags; - } - tcg_s390_program_interrupt(env, flags, ra); - } - *phost = g2h(env_cpu(env), addr); -#else /* * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr==NULL * to detect if there was an exception during tlb_fill(). @@ -173,8 +165,8 @@ static int s390_probe_access(CPUArchState *env, target_ulong addr, int size, (access_type == MMU_DATA_STORE ? BP_MEM_WRITE : BP_MEM_READ), ra); } -#endif return 0; +#endif } static int access_prepare_nf(S390Access *access, CPUS390XState *env, From patchwork Tue Nov 2 11:07:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516669 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4433932iml; Tue, 2 Nov 2021 04:51:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwaJMwAa97NZQiefZ4QzixiCKLFbcMlPfXsGT8xsxJbdlCo0kmJLGvt16iVascynZL1/cDa X-Received: by 2002:a05:6830:23a6:: with SMTP id m6mr26086986ots.38.1635853905504; Tue, 02 Nov 2021 04:51:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635853905; cv=none; d=google.com; s=arc-20160816; b=bJqflLVVfHJSQ4yCKmSf4XXmklGQ0yQePlmzDaxyW6wqZsjzY8quoWAJg/376PEtmj nmF9URfTBtqCp9J0QjzePm4iGjUJ9fmSUPnJWhznY+nCO2GZgVdObZVwJBkrZRlrAZvE rNXJ+m7G8ObFEOqVLU6JoVUG+oRVTmr+CxAREux2TnyvDwWJzDASXpip21PmYxq1Wjur UJxNmgW0EwwKE74+Y2Bdj4YMBTuKSUMpgQ/+3gsKxRvQfszj1qdzFcrHCplzXx9eJkGB daTY++c2siJnex9Y8BD7oq3I7y25ixQTHu7MM3Bn4I6yQvOQb8n0uSPCWfOEabLUn9l4 u7Fg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ij1YRgU0peRo+QSVg6ezzkIr6IGfKaWXUXRkApukMz0=; b=CdRzhWPYtpbmq8e9jO/cfSD1yhpTwftTA2AcjISuRVKVNTSD0MIDmqOtV0tKpYqoMq ev9yeVb+glBzopXzL5Pc3m09fmepVcrEtuuDGaAFyBwqvl1xeH+Pul2RNLSoUoMCj2/w YqLJqnXT4ryhIdDAbzjx7ZFXWuNB0OqPN2k9lg83fgE6vy1UZAcgjinflN2hES+dtbDU wOn49hnBwidM/subfrtLhCHvFP3Zy5ggSAU7/84uvvoPm+zflCnOqIPDWTs3XlTEnXhC 80SRdtjQFzWRqe6d1jvsTCJbQj2vW9q8jAs95AdERe6KajKSBUWcHH+g3k4QwZ6ZM6LQ 5gMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mijVd7qt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.08.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:08:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 37/60] target/s390x: Implement s390_cpu_record_sigsegv Date: Tue, 2 Nov 2021 07:07:17 -0400 Message-Id: <20211102110740.215699-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x834.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the masking of the address from cpu_loop into s390_cpu_record_sigsegv -- this is governed by hw, not linux. This does mean we have to raise our own exception, rather than return to the fallback. Use maperr to choose between PGM_PROTECTION and PGM_ADDRESSING. Use the appropriate si_code for each in cpu_loop. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/s390x-internal.h | 13 ++++++++++--- linux-user/s390x/cpu_loop.c | 13 ++++++------- target/s390x/cpu.c | 6 ++++-- target/s390x/tcg/excp_helper.c | 18 +++++++++++------- 4 files changed, 31 insertions(+), 19 deletions(-) -- 2.25.1 diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 27d4a03ca1..163aa4f94a 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -270,13 +270,20 @@ ObjectClass *s390_cpu_class_by_name(const char *name); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; +#ifdef CONFIG_USER_ONLY +void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr); +#else +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#endif + /* fpu_helper.c */ uint32_t set_cc_nz_f32(float32 v); diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c index 69b69981f6..d089c8417e 100644 --- a/linux-user/s390x/cpu_loop.c +++ b/linux-user/s390x/cpu_loop.c @@ -24,8 +24,6 @@ #include "cpu_loop-common.h" #include "signal-common.h" -/* s390x masks the fault address it reports in si_addr for SIGSEGV and SIGBUS */ -#define S390X_FAIL_ADDR_MASK -4096LL static int get_pgm_data_si_code(int dxc_code) { @@ -111,12 +109,13 @@ void cpu_loop(CPUS390XState *env) n = TARGET_ILL_ILLOPC; goto do_signal_pc; case PGM_PROTECTION: + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_ACCERR, + env->__excp_addr); + break; case PGM_ADDRESSING: - sig = TARGET_SIGSEGV; - /* XXX: check env->error_code */ - n = TARGET_SEGV_MAPERR; - addr = env->__excp_addr & S390X_FAIL_ADDR_MASK; - goto do_signal; + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, + env->__excp_addr); + break; case PGM_EXECUTE: case PGM_SPECIFICATION: case PGM_SPECIAL_OP: diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7b7b05f1d3..593dda75c4 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -266,9 +266,11 @@ static void s390_cpu_reset_full(DeviceState *dev) static const struct TCGCPUOps s390_tcg_ops = { .initialize = s390x_translate_init, - .tlb_fill = s390_cpu_tlb_fill, -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv = s390_cpu_record_sigsegv, +#else + .tlb_fill = s390_cpu_tlb_fill, .cpu_exec_interrupt = s390_cpu_exec_interrupt, .do_interrupt = s390_cpu_do_interrupt, .debug_excp_handler = s390x_cpu_debug_excp_handler, diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 3d6662a53c..b923d080fc 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -89,16 +89,20 @@ void s390_cpu_do_interrupt(CPUState *cs) cs->exception_index = -1; } -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { S390CPU *cpu = S390_CPU(cs); - trigger_pgm_exception(&cpu->env, PGM_ADDRESSING); - /* On real machines this value is dropped into LowMem. Since this - is userland, simply put this someplace that cpu_loop can find it. */ - cpu->env.__excp_addr = address; + trigger_pgm_exception(&cpu->env, maperr ? PGM_ADDRESSING : PGM_PROTECTION); + /* + * On real machines this value is dropped into LowMem. Since this + * is userland, simply put this someplace that cpu_loop can find it. + * S390 only gives the page of the fault, not the exact address. + * C.f. the construction of TEC in mmu_translate(). + */ + cpu->env.__excp_addr = address & TARGET_PAGE_MASK; cpu_loop_exit_restore(cs, retaddr); } From patchwork Tue Nov 2 11:07:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516646 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4411843iml; Tue, 2 Nov 2021 04:29:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwBkSvXnF26oKcEcWs+8uTTSQV1QKigVowVDH7KDVlfTB2wPsv5DYcqTrqxSuaJ9MMPoPJE X-Received: by 2002:a05:6808:1187:: with SMTP id j7mr4484994oil.135.1635852543320; Tue, 02 Nov 2021 04:29:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852543; cv=none; d=google.com; s=arc-20160816; b=XYLYWRs1x9lVrx2aq/YhfzA7Gm1XQOsicmlump6s/kPlL938ZPh5RxwKo5t5rcozqe EXugRD3oQ5PbnOzBWbVbEY8giNijDzVsJDy3Xq9ExYD7hVVqmQo1Q9Q1J0m5JGjS7TyA MqQn4pcH3nRm4ggwuB2snXYEbvjqpDfKH5UKh4bvoIBao6tGzKqUx157IQ5RHneCS7JR HKl27cxuAtp/atElMUUOl245FdggR8i93JK/QgFigNKbYBnN1pf5YN+ax5rpEZM0M80D Fl64CUE4zV2/z2tR5akkpMMzXi+DA9gRi5uX21zCc+GFwBmyNFnRHqzMTwaIT9TUXwQe gcKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bSOPptd8n2vyIHjygFEkKtsmxu32Sh4/nm0zdx+yC2M=; b=kUZDHILfd0PCvv3rw8Dx2xUflAEXWzdRO6UYnk+d3W701U4dMm1qnJQhw12DwTftw3 sF8VmNjJmISLaGeW0hOR0Vapx7yqmrbIywxgAY7mGwlsB1aJW1OXfM3lVZ0s3/VpI7WM gW5zxDYJrvFPdYsXHHa9WNdutzdeKBKv7Ok2g3oLBvjcm9S2O0of0qluFi8Lu6i4thGk kfSrn8zfCy5ky0gXI+JeyPSjZV0gN1VmAGocTurf/ekxMeEl3s1pc4ykyq0G5mZvZRZe cEm6uVokH1xeddD88GdDBzk2mtIRbun2bz/dEV3EBmdCTZIMIZ5KCk/YQfzzOk9w7oax lipg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RWo6+dIK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.08.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:08:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 38/60] target/sh4: Make sh4_cpu_tlb_fill sysemu only Date: Tue, 2 Nov 2021 07:07:18 -0400 Message-Id: <20211102110740.215699-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::831; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x831.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for sh4 linux-user. Remove the code from cpu_loop that raised SIGSEGV. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 6 +++--- linux-user/sh4/cpu_loop.c | 8 -------- target/sh4/cpu.c | 2 +- target/sh4/helper.c | 9 +-------- 4 files changed, 5 insertions(+), 20 deletions(-) -- 2.25.1 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index dc81406646..4cfb109f56 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -213,12 +213,12 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, uintptr_t retaddr) QEMU_NORETURN; void sh4_translate_init(void); +void sh4_cpu_list(void); + +#if !defined(CONFIG_USER_ONLY) bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); - -void sh4_cpu_list(void); -#if !defined(CONFIG_USER_ONLY) void superh_cpu_do_interrupt(CPUState *cpu); bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); void cpu_sh4_invalidate_tlb(CPUSH4State *s); diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c index 65b8972e3c..ac9b01840c 100644 --- a/linux-user/sh4/cpu_loop.c +++ b/linux-user/sh4/cpu_loop.c @@ -65,14 +65,6 @@ void cpu_loop(CPUSH4State *env) info.si_code = TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case 0xa0: - case 0xc0: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->tea; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); arch_interrupt = false; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 2047742d03..06b2691dc4 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -236,9 +236,9 @@ static const struct SysemuCPUOps sh4_sysemu_ops = { static const struct TCGCPUOps superh_tcg_ops = { .initialize = sh4_translate_init, .synchronize_from_tb = superh_cpu_synchronize_from_tb, - .tlb_fill = superh_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = superh_cpu_tlb_fill, .cpu_exec_interrupt = superh_cpu_exec_interrupt, .do_interrupt = superh_cpu_do_interrupt, .do_unaligned_access = superh_cpu_do_unaligned_access, diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 53cb9c3b63..6a620e36fc 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -796,8 +796,6 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } -#endif /* !CONFIG_USER_ONLY */ - bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -806,11 +804,6 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, CPUSH4State *env = &cpu->env; int ret; -#ifdef CONFIG_USER_ONLY - ret = (access_type == MMU_DATA_STORE ? MMU_DTLB_VIOLATION_WRITE : - access_type == MMU_INST_FETCH ? MMU_ITLB_VIOLATION : - MMU_DTLB_VIOLATION_READ); -#else target_ulong physical; int prot; @@ -829,7 +822,6 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) { env->pteh = (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_MASK); } -#endif env->tea = address; switch (ret) { @@ -868,3 +860,4 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } cpu_loop_exit_restore(cs, retaddr); } +#endif /* !CONFIG_USER_ONLY */ From patchwork Tue Nov 2 11:07:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516661 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4419294iml; Tue, 2 Nov 2021 04:36:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwTv4DHIhOndkgf3EwPNAvueKN+oNsU2CBoJpUt0oRKQbP/EQRhJgPddhJx8jYy0Aoom6Lp X-Received: by 2002:a9d:de1:: with SMTP id 88mr13558269ots.286.1635852997325; Tue, 02 Nov 2021 04:36:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852997; cv=none; d=google.com; s=arc-20160816; b=HKqThp0DO0YDripGjdrBL+rUzTiNffiS8gVp8ARpPKFoCS1Kx+JftvmVj5EiwWcAQC FK0GsykpoHqfgrlxRC+klgphmObDJJF/ybt0CZLYK6kfMF0Cc6si0cEQkZUNa6ZOY1Jr CHMmYbBXt3BU1DvImzuZSgqGzDMvth+QGyPGtEVTUjRQb68eEdwAEWL/CFFvWnH6kE6u DNFQpTBpi4fOsaXMz4twK33hYaHXVRP67O/MbRGHa9CxiWnsavKpTs+dvK9utDRBFTUT RJiBYDEA/ebXETPXQzgZ7eeOamHwmBApEdc/UK4kCHD0wlVVPLxCF5fNwuth8GUl5TPl 8afw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OFBASZgYo/dnEXgBhwjQsgVMikt4qFVfoC5aZFh8E0o=; b=TLiQbTkgvlosjB9VjC1joqAv6DAPvwInnyaeWf11X0rUJzgYBydB3ixS8IXIf7TwXh oUUssWvaRF0l3RTnX5BvML2G28a22Kl4b8TAwvKcjzs9iZLdyciTOQZr6avLJ3yZ2/Yw f5ouxTrFW68Pt4wQhEojde4LbLeqOBxIkpLJo5IRWz1dbBLhc7DuT8sdF4GLkW3Yiuxo m64x0jv9jfyazHaPZrADq5rlXpDc38qNmL/21F9ZJ+83WRhLb/dym3m97mPO5g5yw4/g RHqWK7uTOKnFfr+G8LRGYGi3dpvkmuco7b5MJ4dwDozn2i0v3LIC15au92mHzmsFfI/u kQ6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RspD3Pxt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm7sm3568612qkb.86.2021.11.02.04.08.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:08:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 39/60] target/sparc: Make sparc_cpu_tlb_fill sysemu only Date: Tue, 2 Nov 2021 07:07:19 -0400 Message-Id: <20211102110740.215699-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x834.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for sparc linux-user. This makes all of the code in mmu_helper.c sysemu only, so remove the ifdefs and move the file to sparc_softmmu_ss. Remove the code from cpu_loop that handled TT_DFAULT and TT_TFAULT. Cc: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/sparc/cpu_loop.c | 25 ------------------------- target/sparc/cpu.c | 2 +- target/sparc/mmu_helper.c | 25 ------------------------- target/sparc/meson.build | 2 +- 4 files changed, 2 insertions(+), 52 deletions(-) -- 2.25.1 diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index ad29b4eb6a..0ba65e431c 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -219,17 +219,6 @@ void cpu_loop (CPUSPARCState *env) case TT_WIN_UNF: /* window underflow */ restore_window(env); break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->mmuregs[4]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; #else case TT_SPILL: /* window overflow */ save_window(env); @@ -237,20 +226,6 @@ void cpu_loop (CPUSPARCState *env) case TT_FILL: /* window underflow */ restore_window(env); break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - if (trapnr == TT_DFAULT) - info._sifields._sigfault._addr = env->dmmu.mmuregs[4]; - else - info._sifields._sigfault._addr = cpu_tsptr(env)->tpc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; #ifndef TARGET_ABI32 case 0x16e: flush_windows(env); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 21dd27796d..55268ed2a1 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -865,9 +865,9 @@ static const struct SysemuCPUOps sparc_sysemu_ops = { static const struct TCGCPUOps sparc_tcg_ops = { .initialize = sparc_tcg_init, .synchronize_from_tb = sparc_cpu_synchronize_from_tb, - .tlb_fill = sparc_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = sparc_cpu_tlb_fill, .cpu_exec_interrupt = sparc_cpu_exec_interrupt, .do_interrupt = sparc_cpu_do_interrupt, .do_transaction_failed = sparc_cpu_do_transaction_failed, diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index a44473a1c7..2ad47391d0 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -25,30 +25,6 @@ /* Sparc MMU emulation */ -#if defined(CONFIG_USER_ONLY) - -bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - - if (access_type == MMU_INST_FETCH) { - cs->exception_index = TT_TFAULT; - } else { - cs->exception_index = TT_DFAULT; -#ifdef TARGET_SPARC64 - env->dmmu.mmuregs[4] = address; -#else - env->mmuregs[4] = address; -#endif - } - cpu_loop_exit_restore(cs, retaddr); -} - -#else - #ifndef TARGET_SPARC64 /* * Sparc V8 Reference MMU (SRMMU) @@ -926,4 +902,3 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } return phys_addr; } -#endif diff --git a/target/sparc/meson.build b/target/sparc/meson.build index a3638b9503..a801802ee2 100644 --- a/target/sparc/meson.build +++ b/target/sparc/meson.build @@ -6,7 +6,6 @@ sparc_ss.add(files( 'gdbstub.c', 'helper.c', 'ldst_helper.c', - 'mmu_helper.c', 'translate.c', 'win_helper.c', )) @@ -16,6 +15,7 @@ sparc_ss.add(when: 'TARGET_SPARC64', if_true: files('int64_helper.c', 'vis_helpe sparc_softmmu_ss = ss.source_set() sparc_softmmu_ss.add(files( 'machine.c', + 'mmu_helper.c', 'monitor.c', )) From patchwork Tue Nov 2 11:07:20 2021 Content-Type: text/plain; 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 40/60] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only Date: Tue, 2 Nov 2021 07:07:20 -0400 Message-Id: <20211102110740.215699-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::732; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x732.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for xtensa linux-user. Remove the code from cpu_loop that raised SIGSEGV. Acked-by: Max Filippov Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 2 +- linux-user/xtensa/cpu_loop.c | 9 --------- target/xtensa/cpu.c | 2 +- target/xtensa/helper.c | 22 +--------------------- 4 files changed, 3 insertions(+), 32 deletions(-) -- 2.25.1 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index f9a510ca46..02143f2f77 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -563,10 +563,10 @@ struct XtensaCPU { }; +#ifndef CONFIG_USER_ONLY bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c index 622afbcd34..a83490ab35 100644 --- a/linux-user/xtensa/cpu_loop.c +++ b/linux-user/xtensa/cpu_loop.c @@ -226,15 +226,6 @@ void cpu_loop(CPUXtensaState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case LOAD_PROHIBITED_CAUSE: - case STORE_PROHIBITED_CAUSE: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr = env->sregs[EXCVADDR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - default: fprintf(stderr, "exccause = %d\n", env->sregs[EXCCAUSE]); g_assert_not_reached(); diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c1cbd03595..224f723236 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -192,10 +192,10 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = { static const struct TCGCPUOps xtensa_tcg_ops = { .initialize = xtensa_translate_init, - .tlb_fill = xtensa_cpu_tlb_fill, .debug_excp_handler = xtensa_breakpoint_handler, #ifndef CONFIG_USER_ONLY + .tlb_fill = xtensa_cpu_tlb_fill, .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, .do_interrupt = xtensa_cpu_do_interrupt, .do_transaction_failed = xtensa_cpu_do_transaction_failed, diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f18ab383fd..29d216ec1b 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -242,27 +242,7 @@ void xtensa_cpu_list(void) } } -#ifdef CONFIG_USER_ONLY - -bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; - - qemu_log_mask(CPU_LOG_INT, - "%s: rw = %d, address = 0x%08" VADDR_PRIx ", size = %d\n", - __func__, access_type, address, size); - env->sregs[EXCVADDR] = address; - env->sregs[EXCCAUSE] = (access_type == MMU_DATA_STORE ? - STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE); - cs->exception_index = EXC_USER; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - +#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) From patchwork Tue Nov 2 11:07:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516674 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4435822iml; Tue, 2 Nov 2021 04:53:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwOE1RPF+vUSh7gQc60VBG0YP2hVJEgTs74MAjU1zX8LlLGqnAGzGDpKc36nFfLhTyQumJP X-Received: by 2002:a05:6808:118c:: with SMTP id j12mr4434952oil.65.1635854035756; Tue, 02 Nov 2021 04:53:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635854035; cv=none; d=google.com; s=arc-20160816; b=U0/Gz5sBw9eCWaSEhpyo0a8N2FIGOdiXpMEs11KszrOcO19777C6zLOGMv1zN6ToPl /TvH9jb8bFT+4PlmK+zFKJBzmS5JdiTbXBHW+/a5ITWk5lvGnCuiTJglfBhUhGMiYs5S 21OYbTRhrYh9xYxe+hPTNJh4vnCVz/F+uRJqnEqxwB2iUbO10A8lg4fty+Q7hsYsTxeB nKwiUqya+4//pWnZX2+bKg8EHEsPnYTo44ahc8KK8WS1JuHrEClcA+3R7tni4HMYYWf0 /WnytFAD8oocBzj6muzZZ1G8zH0oAwqW9re53150sDhJdVcKdSb16YaGrcy85QcZKhD1 HmlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AlAKO3pHLk0w42dzpdqlCWgmBC5kkngUdLfuQLXO9ho=; b=PazXEA8E0ri0VjmXwlhQH40VB9SAubyMnBnzVtw7Aw5wW/WN4rZMdxNhfuzG/OdBj8 Cy7xXsp7YLdJ99Jt4lEcb3cubTV3akIU4wK5XYY6gxDUk5lMLfH8dtC204ZzWv/+JpaF upbAERi13ow5KnffHWyVNtW/52QWPI4y7jwjdEWwJvmMUDdJ3Ns1OeiozefQOmKIyukN nhGC2BpO8Rx8zjsLXe5ZC7KMFgao/XwIeawCwTYVYUi2ZJhfTNPDtBuJxioN0cS9ClqQ G6rULKemBYlns+6KY70RxxOop/nrKiNg0WZMLob0646G6X1yZz7uXguuCM7jdwRsSevk UHmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FxzYCT3f; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 41/60] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Date: Tue, 2 Nov 2021 07:07:21 -0400 Message-Id: <20211102110740.215699-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::829; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x829.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have replaced tlb_fill with record_sigsegv for user mode. Move the declaration to restrict it to system emulation. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 22 ++++++++++------------ linux-user/signal.c | 3 --- 2 files changed, 10 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 41718b695b..8eadd404c8 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -35,18 +35,6 @@ struct TCGCPUOps { void (*cpu_exec_enter)(CPUState *cpu); /** @cpu_exec_exit: Callback for cpu_exec cleanup */ void (*cpu_exec_exit)(CPUState *cpu); - /** - * @tlb_fill: Handle a softmmu tlb miss or user-only address fault - * - * For system mode, if the access is valid, call tlb_set_page - * and return true; if the access is invalid, and probe is - * true, return false; otherwise raise an exception and do - * not return. For user-only mode, always raise an exception - * and do not return. - */ - bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); /** @debug_excp_handler: Callback for handling debug exceptions */ void (*debug_excp_handler)(CPUState *cpu); @@ -68,6 +56,16 @@ struct TCGCPUOps { #ifdef CONFIG_SOFTMMU /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** + * @tlb_fill: Handle a softmmu tlb miss + * + * If the access is valid, call tlb_set_page and return true; + * if the access is invalid and probe is true, return false; + * otherwise raise an exception and do not return. + */ + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); /** * @do_transaction_failed: Callback for handling failed memory transactions * (ie bus faults or external aborts; not MMU faults) diff --git a/linux-user/signal.c b/linux-user/signal.c index 135983747d..9d60abc038 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -697,9 +697,6 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, if (tcg_ops->record_sigsegv) { tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); - } else if (tcg_ops->tlb_fill) { - tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, ra); - g_assert_not_reached(); } force_sig_fault(TARGET_SIGSEGV, From patchwork Tue Nov 2 11:07:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516667 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4431474iml; Tue, 2 Nov 2021 04:49:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz6WCVArmxj6KxSkfKpjwacLrzYUPb8gz7EgjGJrgO76LHAHG/HK6g+UP462DUxndxYOx/A X-Received: by 2002:a9d:5cc4:: with SMTP id r4mr9676992oti.19.1635853760003; Tue, 02 Nov 2021 04:49:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635853760; cv=none; d=google.com; s=arc-20160816; b=oACbSmSgzKCBKijh3v8J1Gf1Wu4bWCyA9eCdRg0IFk8zBJYcdu7FHCpk69nxdqgEGc BmA7Mk83aMtbQmzNtCIwI6U97FcutdSXCuBqwRGDqXtKkZUQ27n2fGxezY7bPdmCeRYS 4mES1AfGdGvcZKRzMNxILhP9dk25OCUC6EN8hLjtxdQmIQZOKuuhRb9fZg6rzF7V+gPG JhslPs1HqIGVrm+GaLcmCqNdIybnIzc8ifld1dnphae97K8jKJ6ziRscjqdij1VS0MWf 2cWvP6WsIhEsaMeuA/D/EQH3VCn+umfw2a2jcI8eQCzFan8LvXv2aD63MOmag/PjSNjv UURg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vGec2V7sqBlJXZFFOVGa4jSeCFBEP3Km3jAuCBMCplk=; b=uJTIqM5ddlVTCEW1S7d5/gR7PrluTwtMgsdRfUkz+IuRE+4IChlRGkgvnhOaJRwKj4 zzYWlNX5D9k4A6Iz9gyYvJ3k71LQX27RyjJykoJcbQpFcWvz8RffezUU6oWS6ZSBbB7X IkzFfJZspFjKD3M15mfxKbiCwSXflXh2UmTVm3+NMntzyuiyIBCJ9nzeM8hO2F6+iYHL hupMR1/0XEJSx7pjOTWSOp1f7I6rV3BiXMUNLpFmZlKb8Pe5Pze1j14g2/VEMcJzb5fa RHwvrxtZ0q50iMyZg/yuWW6m7bSkRSRxG/stq8qfOKhV6rAhk0dYKR5JHebzdflavgRl RisA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TJp+AxRI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 42/60] hw/core: Add TCGCPUOps.record_sigbus Date: Tue, 2 Nov 2021 07:07:22 -0400 Message-Id: <20211102110740.215699-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82a; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a new user-only interface for updating cpu state before raising a signal. This will take the place of do_unaligned_access for user-only and should result in less boilerplate for each guest. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) -- 2.25.1 diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 8eadd404c8..e13898553a 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -135,6 +135,29 @@ struct TCGCPUOps { void (*record_sigsegv)(CPUState *cpu, vaddr addr, MMUAccessType access_type, bool maperr, uintptr_t ra); + /** + * record_sigbus: + * @cpu: cpu context + * @addr: misaligned guest address + * @access_type: access was read/write/execute + * @ra: host pc for unwinding + * + * We are about to raise SIGBUS with si_code BUS_ADRALN, + * and si_addr set for @addr. Record anything further needed + * for the signal ucontext_t. + * + * If the emulated kernel does not provide the signal handler with + * anything besides the user context registers, and the siginfo_t, + * then this hook need do nothing and may be omitted. + * Otherwise, record the data and return; the caller will raise + * the signal, unwind the cpu state, and return to the main loop. + * + * If it is simpler to re-use the sysemu do_unaligned_access code, + * @ra is provided so that a "normal" cpu exception can be raised. + * In this case, the signal must be raised by the architecture cpu_loop. + */ + void (*record_sigbus)(CPUState *cpu, vaddr addr, + MMUAccessType access_type, uintptr_t ra); #endif /* CONFIG_SOFTMMU */ #endif /* NEED_CPU_H */ From patchwork Tue Nov 2 11:07:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516658 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4418733iml; Tue, 2 Nov 2021 04:36:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyuOzUw0gHqYD0yQNnjEmJ+GlMW9WIkAKsN43kYRqQqZZLuIhsMU+t45fOWWOletXzh6Xae X-Received: by 2002:a9d:1783:: with SMTP id j3mr26917932otj.366.1635852962391; Tue, 02 Nov 2021 04:36:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635852962; cv=none; d=google.com; s=arc-20160816; b=BXEpdvvVwP8xVzYxX4wYB8ALHl9dow+Ph7wUsoZG9afHX2/5RqjSEHY34x4Bg6MN9e lOW9MOJlYqhs2NtQ4KOsp0YMnXm+iAjSuE8wemTnONg273t0ClUph/PhFMMJeLkKQ2ZF YHk4N012JRj6ACGQd5G15jmAVTt/dJMrkjWA6Sf8BAu7+3jD1JJEmfg/tgsOR2sFc0RB orCGWoR7JwLldLBEx0OEJK8clOiiDItXgv5n6mAkMyZ4GQvGCh2JFCvqgV+n1PD701dg SOj34Y/8bkVI0s0h6dHvEwmdTP7EDStBTmMWEG39MlN1EJ2Fln8Lwh+/5BT/lmbEJjLj jtOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1Ep7pHHg1zb1sPSHGpQ1/FF+Txy5JMnbD431/U5MPag=; b=AVTO7t2WdPJ4NCUvb0FhYU0fdzKufvd93nBu1nulhg8vhHb8pQPOvArdZmD6q+umVW MeVhqOS1Lw4ArSKW7HGOxyYIGD/61qv7OiK4zFMXTdpEQWe7h1oOeARcBn87yKGauuGz xLgKTBeXA+poMSseKX+TulvhIVVORdt9plU+u9x/D4MOBH+gmWjwnNGsoMGQKcoGeRVR aLl4vGP3kUgxSOpExe4e9QUkmWWie4lst1lnEbAlSMZCz0AKQcBA96cOf2p6uoIR+cj5 +bzWWwDKPhGdYUHWwp5lhSwSP+sjojplEq33LT4jnYknxV60EcuFU1FxGXndaBQilALz yGzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MQMc9UQV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 43/60] linux-user: Add cpu_loop_exit_sigbus Date: Tue, 2 Nov 2021 07:07:23 -0400 Message-Id: <20211102110740.215699-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::731; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x731.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a new interface to be provided by the os emulator for raising SIGBUS on fault. Use the new record_sigbus target hook. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 14 ++++++++++++++ linux-user/signal.c | 14 ++++++++++++++ 2 files changed, 28 insertions(+) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f74578500c..6bb2a0f7ec 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -700,6 +700,20 @@ void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, MMUAccessType access_type, bool maperr, uintptr_t ra); +/** + * cpu_loop_exit_sigbus: + * @cpu: the cpu context + * @addr: the guest address of the alignment fault + * @access_type: access was read/write/execute + * @ra: host pc for unwinding + * + * Use the TCGCPUOps hook to record cpu state, do guest operating system + * specific things to raise SIGBUS, and jump to the main cpu loop. + */ +void QEMU_NORETURN cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, + uintptr_t ra); + #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/linux-user/signal.c b/linux-user/signal.c index 9d60abc038..df2c8678d0 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -706,6 +706,20 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, cpu_loop_exit_restore(cpu, ra); } +void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, uintptr_t ra) +{ + const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + + if (tcg_ops->record_sigbus) { + tcg_ops->record_sigbus(cpu, addr, access_type, ra); + } + + force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, addr); + cpu->exception_index = EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, ra); +} + /* abort execution with signal */ static void QEMU_NORETURN dump_core_and_abort(int target_sig) { From patchwork Tue Nov 2 11:07:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516662 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4423579iml; Tue, 2 Nov 2021 04:41:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzG9/f2fGt+PFh/BlV9YhnEemt3iPnBA0fRjKIqgNZON1IJoucTisWyHMIgFgT1uoupuvBK X-Received: by 2002:a05:6808:f0c:: with SMTP id m12mr4526416oiw.150.1635853270994; Tue, 02 Nov 2021 04:41:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635853270; cv=none; d=google.com; s=arc-20160816; b=N73+AbNknIXTrC/10oFhtOAW7r+fXjYrHVWmWvMDIZ0bvWrgvyGw91uS9Gw8itHcIV UKHiWyRJTOHCQJDSqXfH6Fy2bBVJQQ1t3Fw+Mpd9unRa2Cwvbm4Y1/V20N7eFGfLnN/7 JjPjX5lRlv0xf6PmcqyS4hEnUyqq+tNQ6JHJW4E4b1H2kmrZ7L+wTtgcSXNBhePXmPhI PGgHT0DudGhBZh3+pPw4lPKTAGUX9/tEXEEIFRd9Sg/WSpYeyiScLQx741z6xdpuIGU7 s/JMPuB9KaaD+ASs+FYsNJO9/AGfNnUS2GHlqDzrfzVCqEXvGDQuHgyDoAjvWRdvv3pL 9/Gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lCTWBHg3yAPeLZcM1I7LLlGr7M38G+m6NQblxbcjKCQ=; b=dtFCyM7WI1rJjZjTg5F9g0yF6/0tW+0HpxsHb/sAfZhHMErWgW05QsMOUJC+nWryQl qZNDW+103sX6hgQW1ZetOEyyf1WVwAWh5tC7Io4a0npeCdY91yw31BMZ0u2kOi2Ktw+e 2/H84S/yuil3NojMe1lGJMUlutVaYXbE4vlR1RWnos1vsiOIGkhVwFZ9OsbJ91uVTpUb wwO5MYJRUNnUvY1fLee6i2obgQB9kYDLdeqU2L8ZYDWje8fM92izfb2xgnqTa/NUORBb RaCUT/hFGO+2n0oaLBPRE0gMgAkNWRnVqx+ukzOMPOdxDDpKNXm1Tor1IkhKtY9CSrrA yfjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ygL+Jwzc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 44/60] target/alpha: Implement alpha_cpu_record_sigbus Date: Tue, 2 Nov 2021 07:07:24 -0400 Message-Id: <20211102110740.215699-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f30; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Record trap_arg{0,1,2} for the linux-user signal frame. Raise SIGBUS directly from cpu_loop_exit_sigbus, which means we can remove the code for EXCP_UNALIGN in cpu_loop. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 8 +++++--- linux-user/alpha/cpu_loop.c | 7 ------- target/alpha/cpu.c | 1 + target/alpha/mem_helper.c | 30 ++++++++++++++++++++++-------- 4 files changed, 28 insertions(+), 18 deletions(-) -- 2.25.1 diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index d49cc36d07..afd975c878 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -282,9 +282,6 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags); hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; #define cpu_list alpha_cpu_list @@ -451,10 +448,15 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val); void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, MMUAccessType access_type, bool maperr, uintptr_t retaddr); +void alpha_cpu_record_sigbus(CPUState *cs, vaddr address, + MMUAccessType access_type, uintptr_t retaddr); #else bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 4cc8e0a55c..4029849d5c 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -54,13 +54,6 @@ void cpu_loop(CPUAlphaState *env) fprintf(stderr, "External interrupt. Exit\n"); exit(EXIT_FAILURE); break; - case EXCP_UNALIGN: - info.si_signo = TARGET_SIGBUS; - info.si_errno = 0; - info.si_code = TARGET_BUS_ADRALN; - info._sifields._sigfault._addr = env->trap_arg0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_OPCDEC: do_sigill: info.si_signo = TARGET_SIGILL; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 69f32c3078..a8990d401b 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -221,6 +221,7 @@ static const struct TCGCPUOps alpha_tcg_ops = { #ifdef CONFIG_USER_ONLY .record_sigsegv = alpha_cpu_record_sigsegv, + .record_sigbus = alpha_cpu_record_sigbus, #else .tlb_fill = alpha_cpu_tlb_fill, .cpu_exec_interrupt = alpha_cpu_exec_interrupt, diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 75e72bc337..47283a0612 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -23,18 +23,12 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" -/* Softmmu support */ -#ifndef CONFIG_USER_ONLY -void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t retaddr) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; uint64_t pc; uint32_t insn; - cpu_restore_state(cs, retaddr, true); + cpu_restore_state(env_cpu(env), retaddr, true); pc = env->pc; insn = cpu_ldl_code(env, pc); @@ -42,6 +36,26 @@ void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, env->trap_arg0 = addr; env->trap_arg1 = insn >> 26; /* opcode */ env->trap_arg2 = (insn >> 21) & 31; /* dest regno */ +} + +#ifdef CONFIG_USER_ONLY +void alpha_cpu_record_sigbus(CPUState *cs, vaddr addr, + MMUAccessType access_type, uintptr_t retaddr) +{ + AlphaCPU *cpu = ALPHA_CPU(cs); + CPUAlphaState *env = &cpu->env; + + do_unaligned_access(env, addr, retaddr); +} +#else +void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + AlphaCPU *cpu = ALPHA_CPU(cs); + CPUAlphaState *env = &cpu->env; + + do_unaligned_access(env, addr, retaddr); cs->exception_index = EXCP_UNALIGN; env->error_code = 0; cpu_loop_exit(cs); From patchwork Tue Nov 2 11:07:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516682 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4440698iml; Tue, 2 Nov 2021 04:59:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwaNGHfFkrGJJKGEalufMzaYV4JHIq4Mly4ZbL0QS50LsXF4JiTB/N6/vRH1zgU4KiYQoCQ X-Received: by 2002:a05:6808:b31:: with SMTP id t17mr4587637oij.140.1635854399161; Tue, 02 Nov 2021 04:59:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635854399; cv=none; d=google.com; s=arc-20160816; b=nZ8ZhhGCE6V8NTNH6b0GVyCD2dnQBRdLyQwfgl/tuN2I6R0xskBoPuVSMZFcdnSefR BQNNz6FqxLeMgZt0IahspTmo5oIsaes9YlY3Ufh+mgEol1AGzfaD7QvgV2ljXwlrrUVE 1BZ9UGkr0ZQoiMvvs2WbWU8mQBEQ/lE4v9fxFiPz1wdDJvAOrsq0j+eRk0TaM4iMDokz +ATXP9XinIdLNky/+FOuRXN5w9Zi+C4vBai6RQK8A8+ddwIoAZTxpHR3NMK0ZkctPQpi OlABcdN8IR9jnn5qpl5t5Hef4bxGznItNn5tgioiQNs09Ru6i809ZjjmTkre0spR0keb MqkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6E2EHrVXu+fKkNaLcRStkdoJxkkRxYzYfXrw6rxs8+I=; b=HWR0IvBKqJJOW/RtLdCEru0wTYsLoPMTDJKi/FO1gkkPMzCvvjuI5NW3JrkJZ9vk0+ V1NpTprDuFwPeb01EX94/jFu4bPKPQZRcPkH7Pz4tnTbIqX9Kxqdl4rdOraQjxNzg3gi D60uSNB5j7CtwZ1/ecDh/7uozJn2MptTR0O2dw0EQj0FZRyLBAXzRt6x8I6bQB9HX6F0 dvtCa1yxAmyw/xXayLdikojVpe7kruG/O36fo4c44/TbmF9QMVg9CBA8BV3Mn9IB/stZ SkC7H//NEuDaSTm6r57GCWvkaG1oqP5F4tZnTfaNdC9FHlXdffnC+YXjbtk/hwUYXj6+ Smmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Q6XFHrCu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 45/60] target/arm: Implement arm_cpu_record_sigbus Date: Tue, 2 Nov 2021 07:07:25 -0400 Message-Id: <20211102110740.215699-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72a; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because of the complexity of setting ESR, re-use the existing arm_cpu_do_unaligned_access function. This means we have to handle the exception ourselves in cpu_loop, transforming it to the appropriate signal. Reviewed-by: Warner Losh Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 ++ linux-user/aarch64/cpu_loop.c | 12 +++++++++--- linux-user/arm/cpu_loop.c | 30 ++++++++++++++++++++++++++---- target/arm/cpu.c | 1 + target/arm/cpu_tcg.c | 1 + target/arm/tlb_helper.c | 6 ++++++ 6 files changed, 45 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/arm/internals.h b/target/arm/internals.h index 5a7aaf0f51..89f7610ebc 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -548,6 +548,8 @@ static inline bool arm_extabort_type(MemTxResult result) void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, MMUAccessType access_type, bool maperr, uintptr_t ra); +void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr, + MMUAccessType access_type, uintptr_t ra); #else bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 034b737435..97e0728b67 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -79,7 +79,7 @@ void cpu_loop(CPUARMState *env) { CPUState *cs = env_cpu(env); - int trapnr, ec, fsc, si_code; + int trapnr, ec, fsc, si_code, si_signo; abi_long ret; for (;;) { @@ -121,20 +121,26 @@ void cpu_loop(CPUARMState *env) fsc = extract32(env->exception.syndrome, 0, 6); switch (fsc) { case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + si_signo = TARGET_SIGSEGV; si_code = TARGET_SEGV_MAPERR; break; case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + si_signo = TARGET_SIGSEGV; si_code = TARGET_SEGV_ACCERR; break; case 0x11: /* Synchronous Tag Check Fault */ + si_signo = TARGET_SIGSEGV; si_code = TARGET_SEGV_MTESERR; break; + case 0x21: /* Alignment fault */ + si_signo = TARGET_SIGBUS; + si_code = TARGET_BUS_ADRALN; + break; default: g_assert_not_reached(); } - - force_sig_fault(TARGET_SIGSEGV, si_code, env->exception.vaddress); + force_sig_fault(si_signo, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index ae09adcb95..01cb6eb534 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -25,6 +25,7 @@ #include "cpu_loop-common.h" #include "signal-common.h" #include "semihosting/common-semi.h" +#include "target/arm/syndrome.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -280,7 +281,7 @@ static bool emulate_arm_fpa11(CPUARMState *env, uint32_t opcode) void cpu_loop(CPUARMState *env) { CPUState *cs = env_cpu(env); - int trapnr; + int trapnr, si_signo, si_code; unsigned int n, insn; abi_ulong ret; @@ -423,9 +424,30 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* XXX: check env->error_code */ - force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, - env->exception.vaddress); + /* For user-only we don't set TTBCR_EAE, so look at the FSR. */ + switch (env->exception.fsr & 0x1f) { + case 0x1: /* Alignment */ + si_signo = TARGET_SIGBUS; + si_code = TARGET_BUS_ADRALN; + break; + case 0x3: /* Access flag fault, level 1 */ + case 0x6: /* Access flag fault, level 2 */ + case 0x9: /* Domain fault, level 1 */ + case 0xb: /* Domain fault, level 2 */ + case 0xd: /* Permision fault, level 1 */ + case 0xf: /* Permision fault, level 2 */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_ACCERR; + break; + case 0x5: /* Translation fault, level 1 */ + case 0x7: /* Translation fault, level 2 */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MAPERR; + break; + default: + g_assert_not_reached(); + } + force_sig_fault(si_signo, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a18a58ca0..a211804fd3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2035,6 +2035,7 @@ static const struct TCGCPUOps arm_tcg_ops = { #ifdef CONFIG_USER_ONLY .record_sigsegv = arm_cpu_record_sigsegv, + .record_sigbus = arm_cpu_record_sigbus, #else .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_cpu_exec_interrupt, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 7b3bea2fbb..13d0e9b195 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -902,6 +902,7 @@ static const struct TCGCPUOps arm_v7m_tcg_ops = { #ifdef CONFIG_USER_ONLY .record_sigsegv = arm_cpu_record_sigsegv, + .record_sigbus = arm_cpu_record_sigbus, #else .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index dc5860180f..12a934e924 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -213,4 +213,10 @@ void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr, cpu_restore_state(cs, ra, true); arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi); } + +void arm_cpu_record_sigbus(CPUState *cs, vaddr addr, + MMUAccessType access_type, uintptr_t ra) +{ + arm_cpu_do_unaligned_access(cs, addr, access_type, MMU_USER_IDX, ra); +} #endif /* !defined(CONFIG_USER_ONLY) */ From patchwork Tue Nov 2 11:07:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516670 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4433970iml; Tue, 2 Nov 2021 04:51:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxXf1YMPuDgEgpttEqmEEMwkFtYchTXT4Un8LoQ/HABUiRbPOGV8L8mkgGW4EaFDDTIy6En X-Received: by 2002:a05:6808:128f:: with SMTP id a15mr4451756oiw.62.1635853907517; Tue, 02 Nov 2021 04:51:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635853907; cv=none; d=google.com; s=arc-20160816; b=g5ekjgNzCWDZPf8HD1TLILnAFaXZgdb/cHqDFThYj7jPLsjIMSAVYHuKhlc3Sflodz f3392waRbwf1Huhb/2zgwqGgQERQXuojNdrAJJCj6W+E0BZ6Q79oVV6G8/OXhb0SaW4b oECNqJ1QDGMLy174uRXu3e3WSlpq0aNNy56DDlTYr6nO9TScnoRhqoJ1o4mG7CjuMXw4 8IqTnMS/DXU9qvAEqu4RJejcGpFjSixVXTNTMq8m8ov7Lbe3PQLDxtUioTNDXQoQJEUt xdcQ2xKVehxaP80PRW+FOBfm6uNVTJfgC2vYXHrYv1A9udRo0BtpLKxB9F8VhVda0Xnl XocQ== ARC-Message-Signature: i=1; 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 46/60] linux-user/hppa: Remove EXCP_UNALIGN handling Date: Tue, 2 Nov 2021 07:07:26 -0400 Message-Id: <20211102110740.215699-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::732; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x732.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will raise SIGBUS directly from cpu_loop_exit_sigbus. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/hppa/cpu_loop.c | 7 ------- 1 file changed, 7 deletions(-) -- 2.25.1 diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index e0a62deeb9..375576c8f0 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -144,13 +144,6 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f = env->gr[31]; env->iaoq_b = env->gr[31] + 4; break; - case EXCP_UNALIGN: - info.si_signo = TARGET_SIGBUS; - info.si_errno = 0; - info.si_code = 0; - info._sifields._sigfault._addr = env->cr[CR_IOR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_ILL: case EXCP_PRIV_OPR: case EXCP_PRIV_REG: From patchwork Tue Nov 2 11:07:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516677 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4438017iml; Tue, 2 Nov 2021 04:56:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJydO0LMLzW4BuABnVZ0s+DtaSEXyU/qLHP7Aj81MZdJL066daDDKwvUyO+ocVc28b5OWU0F X-Received: by 2002:aca:e08b:: with SMTP id x133mr4730626oig.133.1635854196997; Tue, 02 Nov 2021 04:56:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635854196; cv=none; d=google.com; s=arc-20160816; b=Y8U4xSx91VSp4R9r6H+TadDsCbbRGjLyx7i6mT7CiJcZWYZruQaSyQO7Q9gmbDuAxK Dvmu5eGuqOCYXj9cSvbXklTTIcIeWbm1aGgiAhmfBcORR7uwz0PZ7nOJpkPhZXq+XssK o78AM0PE55pOAX3waEpLWPYtimh1YV+UzELdYEccbgKwmiL2av+wtC9PBoy9ZAQQOhyK ey8P0+MxKZJ7AgnAjSOYEGyxTSydVPW5iyT/x/SpqQcR5bVVrhueo93CeF/lpl8ZNuRK xzdyuKwSvs3Bx+ouMDlgIFbT6gU8Ku3APf4snBDZVotZLyk1MDaGwPD/0QAHLQy6ZeNZ VBSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mTKdaHiEpe60z+ThGKt8c3K8jQRQXSW+5obPKHUiPMs=; b=NFkkW5CM1qrnf36kvvUAdZNX3ZDVEZ++xOWzuEL9FwgP4e5yGnkPeh75YwlChsnVU5 5LhMfzBuzt654tz7ftgjk8m8paxOKVdR9mwRKQZIaxqKmTKyRQsvJLAwSVHJO7YqvWFd F6uXywmKbifALDREY/rM80iXN77rc9U7/OCQG7r43laUIy/OyuNlOHfeFlp8bb1amFK+ lBHC5VDCpjH/IjIX8tc8Damacr2+8dxWln+qS19OpaRpEtdikGW4a3VdbhF26tjqeaZg qzDfrmL/t52mjIeSLs97F8JntGWv6V2TZ5KSwx4RLyCoOyVS7YbJ7Y7rBxfkYwL1r9FR /y4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N8TzaLvv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 47/60] target/microblaze: Do not set MO_ALIGN for user-only Date: Tue, 2 Nov 2021 07:07:27 -0400 Message-Id: <20211102110740.215699-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72b; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The kernel will fix up unaligned accesses, so emulate that by allowing unaligned accesses to succeed. Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 437bbed6d6..2561b904b9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -722,6 +722,7 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) } #endif +#ifndef CONFIG_USER_ONLY static void record_unaligned_ess(DisasContext *dc, int rd, MemOp size, bool store) { @@ -734,6 +735,7 @@ static void record_unaligned_ess(DisasContext *dc, int rd, tcg_set_insn_start_param(dc->insn_start, 1, iflags); } +#endif static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, int mem_index, bool rev) @@ -755,12 +757,19 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } + /* + * For system mode, enforce alignment if the cpu configuration + * requires it. For user-mode, the Linux kernel will have fixed up + * any unaligned access, so emulate that by *not* setting MO_ALIGN. + */ +#ifndef CONFIG_USER_ONLY if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, rd, size, false); mop |= MO_ALIGN; } +#endif tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop); @@ -901,12 +910,19 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } + /* + * For system mode, enforce alignment if the cpu configuration + * requires it. For user-mode, the Linux kernel will have fixed up + * any unaligned access, so emulate that by *not* setting MO_ALIGN. + */ +#ifndef CONFIG_USER_ONLY if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, rd, size, true); mop |= MO_ALIGN; } +#endif tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); From patchwork Tue Nov 2 11:07:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516665 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4430352iml; Tue, 2 Nov 2021 04:47:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzSvYpJY7lDYuryhawT1PUjkyjHqexQXgMmcGFi4rBX9g5qc4rot6TyiN2/lPAoxqm37asl X-Received: by 2002:aca:6256:: with SMTP id w83mr4534676oib.19.1635853677293; Tue, 02 Nov 2021 04:47:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635853677; cv=none; d=google.com; s=arc-20160816; b=P3bNKSSkPKMjd49PpTrelJzcIzZ6i7IHxf0gXzmZIJKPPEpy1RCVIvqcCgVH43kNB6 98VjqRf8GjJn+nWLF0L+vbtsla8MchquRZwqt5kSJm1M9A0S/fc+KfcP2bBc/2IOSu9H 5EGZkRivOma2Rlh3ZE7pdXLdzocY3TqyTfrChVJoKDnvmKpJsLZDJYc8W5bNBgt5SUse raxS10WJgnCeJnxgVk0G93N1uYzMhADtcUODgV9OUziIhikDmlweHmmMjf86/mwMmz6I e6lF41j8PV5KwCyD5ruNm5KTS9LrTg5evPEDAwCZwM6NcaBDyuUP6yLybgBkSlyogmTN eV5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=54O7y5F6cil48JbVjJeuP4tBSWG4MHFPBxntrZflWpI=; b=PG4dgXI4rQzSgmHQ2GXvMiZVZ9VF0mwiBE3Lgbn4AuPENz6n1oa/F/WDtpmmA2qHsf /AYJ9HtvS3LX//CoUw2KE3BRQufsPFXFFW2NnsHJqyTF3ArKWSnXhbU1b8TcotyvGzM4 ZIeGT4dNndhdcVe9+OckdymCkg3jUCNdtb/dYmZ6AawkMljLDLFsHi4B10gQSNsCqkrw dp583aJcgiCXBfqmr/pGb/pTWw9ZWIqnbrKlLv9KCGiAQbxG9vjeRmCGZV+9U5ojJohU EaJ9BhI9/Qlx4dLf5HS7T7FUBkaf+t62u0POtWp7mDt2F0zJYjzerPXN84Tpe9pw8qeo JDrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UV1GmcKa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 48/60] target/ppc: Move SPR_DSISR setting to powerpc_excp Date: Tue, 2 Nov 2021 07:07:28 -0400 Message-Id: <20211102110740.215699-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72d; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" By doing this while sending the exception, we will have already done the unwinding, which makes the ppc_cpu_do_unaligned_access code a bit cleaner. Update the comment about the expected instruction format. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/ppc/excp_helper.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index b7d1767920..88a8de4b80 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -454,13 +454,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) break; } case POWERPC_EXCP_ALIGN: /* Alignment exception */ - /* Get rS/rD and rA from faulting opcode */ /* - * Note: the opcode fields will not be set properly for a - * direct store load/store, but nobody cares as nobody - * actually uses direct store segments. + * Get rS/rD and rA from faulting opcode. + * Note: We will only invoke ALIGN for atomic operations, + * so all instructions are X-form. */ - env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; + { + uint32_t insn = cpu_ldl_code(env, env->nip); + env->spr[SPR_DSISR] |= (insn & 0x03FF0000) >> 16; + } break; case POWERPC_EXCP_PROGRAM: /* Program exception */ switch (env->error_code & ~0xF) { @@ -1462,14 +1464,9 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int mmu_idx, uintptr_t retaddr) { CPUPPCState *env = cs->env_ptr; - uint32_t insn; - - /* Restore state and reload the insn we executed, for filling in DSISR. */ - cpu_restore_state(cs, retaddr, true); - insn = cpu_ldl_code(env, env->nip); cs->exception_index = POWERPC_EXCP_ALIGN; - env->error_code = insn & 0x03FF0000; - cpu_loop_exit(cs); + env->error_code = 0; + cpu_loop_exit_restore(cs, retaddr); } #endif From patchwork Tue Nov 2 11:07:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516671 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4434203iml; Tue, 2 Nov 2021 04:52:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyvU/tyfzOV/U/a1+2EodrVuF7pBf3O8AFkmG4JPJ769MXxrb6Dy6EARaawDO5NM2zDKw1i X-Received: by 2002:aca:2403:: with SMTP id n3mr4506995oic.123.1635853923878; Tue, 02 Nov 2021 04:52:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635853923; cv=none; d=google.com; s=arc-20160816; b=n5+q/l2elF3YoVyXOptmhlAKTAu2mkHEkah857oQYcqffeRcG7Eo6PmUoNoYvRZVW+ dNtnQ0InOC7soe0hh9Gg4PoHN/vQTM59eA9/YMj0PXEfNz27D/06k/TIfNL/OLYH3o/A VJSNd0N3ZcY5Yth237CVwTFxjzovt91DpBHasR9NdU4Qpu9wljgcUG8Lb69rkVt+dvS2 +D6KlN0HDPeDtSolFayq/SnoNMY2WN1ZnRCqV7pRh8hn6pq9IVYqvptjqinxdOlvXFU/ YyHRPDnon2nIBa/Gk5/7a1ZWmsztchjzMB10JRwPdD1dWySBLV7SYlX5KC3cxgCWx323 ONSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hDIIDmSt3XkX7dozNp8YyanBuOQiSpBj16JErrhb+ZE=; b=eFJv+7Od3fFuvah14TnlS7VcV2hoIrTgPu60SEKYUnrpjOaD6OZq2HZi4eekvDAcF6 YN1spHKpjdRfJx8oh+83d5UdYtA0GHUuhCauFJCw68aNAcyJlE22vY5S7SFdYBVCdgI+ 0ujCEW2Q5z/oN8rno3Klwp7/NjYna/gQ5mNAzIzsk6SDsr4mSntQ5Fzy4iQm6ZPktb+n mtuxVvNSlltbIvxbg8ZXkWJL1VHasUr5DfxeSllG9rIbDuWnaC5wqFdMNxswleGUry3j XxoPQbEXAeQ4Gpsxxf7UWl4FNr4pCRJ4vurErP/OGLW2p2MlqggwqR/zFAPygZOyTz6u 4A1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=szYdm483; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 49/60] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Date: Tue, 2 Nov 2021 07:07:29 -0400 Message-Id: <20211102110740.215699-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72d; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-ppc@nongnu.org, Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We ought to have been recording the virtual address for reporting to the guest trap handler. Cc: qemu-ppc@nongnu.org Reviewed-by: Warner Losh Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/ppc/excp_helper.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.25.1 diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 88a8de4b80..e568a54536 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1465,6 +1465,20 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, { CPUPPCState *env = cs->env_ptr; + switch (env->mmu_model) { + case POWERPC_MMU_SOFT_4xx: + case POWERPC_MMU_SOFT_4xx_Z: + env->spr[SPR_40x_DEAR] = vaddr; + break; + case POWERPC_MMU_BOOKE: + case POWERPC_MMU_BOOKE206: + env->spr[SPR_BOOKE_DEAR] = vaddr; + break; + default: + env->spr[SPR_DAR] = vaddr; + break; + } + cs->exception_index = POWERPC_EXCP_ALIGN; env->error_code = 0; cpu_loop_exit_restore(cs, retaddr); From patchwork Tue Nov 2 11:07:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516675 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4436260iml; Tue, 2 Nov 2021 04:54:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx0LuVITsWc773s1IJ70iVVjCJKyypcLEZMK5poXYovbMzr6VtYtsVCabQTJn+N9qTvHL/F X-Received: by 2002:a4a:d785:: with SMTP id c5mr15669201oou.2.1635854064905; Tue, 02 Nov 2021 04:54:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635854064; cv=none; d=google.com; s=arc-20160816; b=0m3kfTiYbP+fFO7oPiEdbT0UIf/WvwWVojLi/SFck4DRY1qy6+8RU0DBb15XmrhgD5 9aUaAakUXyKIW8LFV8tkz+iyIABjvVPMiaYkUgKfvPtolQjcxj3pR/8ozNCm6/lgR/9E P5nbuPY3a5PZX/eP9I6+4d0xtq2zRvwMqTaTFYyD7NxeRPALtjbct/kDVXa+1rT/XFqm kVFXs64fwkhCTxKjUHHCETzxS0mJOOR9+v/MTyzYkP37hY2uwVgGbIGoWnz8cWVzPJwf jzW+boBDjh3uNGdjwnTEnySe47SBEGgXNJTwla/lESISK373CqZxOAaYJK6AEnrXS2WL DsTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=O2Pwh8dMK2GW2V5gEng3hQsybzKfwzmJDjUzbvltEB4=; b=FDSdLRkFwqgj0sXNqmU78+lAZCsDQdBmh+pkihp1ojCkWZ/aH2F8006RTR/PetkXo+ mXAMXkPbLcY2ClcrWdnYc9d4+9WiOurvlhZeN1WIA+pmsD9NxyoAUXHbXbqn+6jZ+svI 7oDRCLGdiufmumc5UF8iVVO/IafVuMFzZNR13laq770sidEzIfaaZg2te1PV+zvxrOAt X/PgIK4h13oMfF3yIlGDB4SkVSzIvoPkhgLGe7tyi6/EmdxJCnI/olTEhCbacCoBeNwA KPeghe1RZqHB2XLT/uh8Xxoimyx5UJdc4brBwFHxTk5GE2IRK0q+GTboMfDXPuaUYCvJ JGuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KII20b0p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 50/60] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu Date: Tue, 2 Nov 2021 07:07:30 -0400 Message-Id: <20211102110740.215699-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::730; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x730.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is not used by, nor required by, user-only. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/ppc/internal.h | 8 +++----- target/ppc/excp_helper.c | 8 +++----- 2 files changed, 6 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 339974b7d8..6aa9484f34 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -211,11 +211,6 @@ void helper_compute_fprf_float16(CPUPPCState *env, float16 arg); void helper_compute_fprf_float32(CPUPPCState *env, float32 arg); void helper_compute_fprf_float128(CPUPPCState *env, float128 arg); -/* Raise a data fault alignment exception for the specified virtual address */ -void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; - /* translate.c */ int ppc_fixup_cpu(PowerPCCPU *cpu); @@ -291,6 +286,9 @@ void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr, bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; #endif #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index e568a54536..17607adbe4 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1454,11 +1454,8 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb) book3s_msgsnd_common(pir, PPC_INTERRUPT_DOORBELL); } -#endif -#endif /* CONFIG_TCG */ -#endif +#endif /* TARGET_PPC64 */ -#ifdef CONFIG_TCG void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) @@ -1483,4 +1480,5 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, env->error_code = 0; cpu_loop_exit_restore(cs, retaddr); } -#endif +#endif /* CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY */ From patchwork Tue Nov 2 11:07:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516680 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4439550iml; Tue, 2 Nov 2021 04:58:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz935Vc2ceE+9HeRspvwxMbC3twLTP+htFldcIQ63OBPbvFXpYYoxBz/sibmIw3aapQdgbW X-Received: by 2002:a9d:6653:: with SMTP id q19mr11357212otm.93.1635854310452; Tue, 02 Nov 2021 04:58:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635854310; cv=none; d=google.com; s=arc-20160816; b=Yg0/VC7AQxIqDUEXECyn/Y9AggdmQSUu9QD/+VoZ456bgQ3J7pl25FyANu7+JFXPDu +KMGMmK6wcn4HNAkcbhurUJSxlTph+pdaOd/FB12BgKs7+yietN4kL/s6TPGRpXNOjPD 5fFCBP/t//3f3iMdEGAeXRZLjXpfgy6Am6yIzLmPpdwGzhbu95lkHTUJ96ku9iBPxIGt 9+kL5wu92fdToUlK5Eyime0Vl48KDwyLre/+0/bnq8Nk9BFlgLfXBt3VmqHKUm0V3e7f UIq0PeNvXT3OVEo+m1vEF2jm1wXd2jxHqjvV5p0+PmoaZiAwn0qy13UbhHL9acl0zhcG VMfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JbVRREsh8zZn+CBQ6RQjqfCoQN/6HupmGu/vI+h3Hm8=; b=a7VIsQLiX4/NuFVyNXKp+gEWltW8XLQRbNzf8HV3OW3SirRzsHzygIzbwiSXxKj062 82wb6f5YdCLXxEZJ1xxAs+ILYB7PAe2NpKkKVNyEphbjsd3xXG6RG4ee1gmaWVuoIuYK LG1VZh9ecLuTTAXriZ6eYCUODNw8vTSJ8YYnFwvO94uCpYYv7efb3/hGZ+2552502we3 j5QMcKvXGx5i9C1q95AhP6ZjWROdjvqXATqABYkEguk9IMtnz5Lu0CcRKqi69TvSzQkh dMOEKxg/sTKbp/+qlCfe0EFQ3LB3jEVFjQPDhlOPe3o8co5x5iq1LCw7d76BNdCZbyJW pBYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vD2gFwof; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 51/60] linux-user/ppc: Remove POWERPC_EXCP_ALIGN handling Date: Tue, 2 Nov 2021 07:07:31 -0400 Message-Id: <20211102110740.215699-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::735; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x735.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SUBJ_WIPE_DEBT=1.004 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will raise SIGBUS directly from cpu_loop_exit_sigbus. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/ppc/cpu_loop.c | 8 -------- 1 file changed, 8 deletions(-) -- 2.25.1 diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index 840b23736b..483e669300 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -162,14 +162,6 @@ void cpu_loop(CPUPPCState *env) cpu_abort(cs, "External interrupt while in user mode. " "Aborting\n"); break; - case POWERPC_EXCP_ALIGN: /* Alignment exception */ - /* XXX: check this */ - info.si_signo = TARGET_SIGBUS; - info.si_errno = 0; - info.si_code = TARGET_BUS_ADRALN; - info._sifields._sigfault._addr = env->nip; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case POWERPC_EXCP_PROGRAM: /* Program exception */ case POWERPC_EXCP_HV_EMU: /* HV emulation */ /* XXX: check this */ From patchwork Tue Nov 2 11:07:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516683 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4441547iml; Tue, 2 Nov 2021 05:00:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw2wI/n9cuPQr9YGS9fUz2/KMyB0tk4cOGEbWFe8LNpokcrn/OOg4BuKPPzgue34RGmKDiV X-Received: by 2002:aca:df82:: with SMTP id w124mr989569oig.171.1635854441635; Tue, 02 Nov 2021 05:00:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635854441; cv=none; d=google.com; s=arc-20160816; b=Ww7ScJPTg+roBpQ5HL5E8vRQwVK+BDtlIeD/1ERZ11RqeJAsKf9Oob1SrHXUkdYFla 5SNCiUpQr1Z71UyrbERWvcWtfzaH00SAe7+SE/3xdyPS2izr+QWFvz6StA+J/C8iQgVL DMv6BD/bNApt4+CEkpoHFq2Fsswj7ttrLva+C9cfwtmrASE7vt1SYHA/MkQ/Tr96s4jf 1MqRSmf3Igr3bAnfPBV0Z9jfAOMq7IirmQmcCn2X8sRnyRaIpCZg3OOQ3Wvg8KVFBpjq HiGobzDfWw+rIUDCuJGsd9B98rS7PsBWZxlGpu5JT4r9tjOxlmWf+EdElQ0IgQ1GiNiq ou/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RjnbfjA/SuXJ4jF6cq76qF1xRJpDxH7O+xJW5W8IXoI=; b=EGgQCJyGlho7S3NbzOdT67xQIWWuBQ5G/rUTzkSWklVilXHHPVmQK1KDQ2xalINfAp 3lgMBXANuISv9E0PFim+2gdWEXnNGrnOO/NF9NKQ33OOVeoqT5Lxb6GlmbBxpDvQpp0w Ewbp5MFqv+Jy0S4h18m+sOg9TYdOg3yJ2HFFwLwUaP/wYwYydKt/b0Hj8Y9sU3klbyNB fdVXHp/QRD5DeGYgz2wlTZA/Anbgb/93U1bRC2W/iZD2Ur+K/0ejDqPjVzCDP9IN7wVb m40MTbBWgClQuMh4Y1kheHH+kaY4Uhvhr2P5qLeTdfayBKhkUgQD8KepLUtV1B1dD7m7 iTmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hP+qHkts; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 52/60] target/s390x: Implement s390x_cpu_record_sigbus Date: Tue, 2 Nov 2021 07:07:32 -0400 Message-Id: <20211102110740.215699-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72d; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For s390x, the only unaligned accesses that are signaled are atomic, and we don't actually want to raise SIGBUS for those, but instead raise a SPECIFICATION error, which the kernel will report as SIGILL. Split out a do_unaligned_access function to share between the user-only s390x_cpu_record_sigbus and the sysemu s390x_do_unaligned_access. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/s390x-internal.h | 8 +++++--- target/s390x/cpu.c | 1 + target/s390x/tcg/excp_helper.c | 27 ++++++++++++++++++++------- 3 files changed, 26 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 163aa4f94a..1a178aed41 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -270,18 +270,20 @@ ObjectClass *s390_cpu_class_by_name(const char *name); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); -void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; #ifdef CONFIG_USER_ONLY void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, MMUAccessType access_type, bool maperr, uintptr_t retaddr); +void s390_cpu_record_sigbus(CPUState *cs, vaddr address, + MMUAccessType access_type, uintptr_t retaddr); #else bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; #endif diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 593dda75c4..ccdbaf84d5 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -269,6 +269,7 @@ static const struct TCGCPUOps s390_tcg_ops = { #ifdef CONFIG_USER_ONLY .record_sigsegv = s390_cpu_record_sigsegv, + .record_sigbus = s390_cpu_record_sigbus, #else .tlb_fill = s390_cpu_tlb_fill, .cpu_exec_interrupt = s390_cpu_exec_interrupt, diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index b923d080fc..4e7648f301 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -82,6 +82,19 @@ void HELPER(data_exception)(CPUS390XState *env, uint32_t dxc) tcg_s390_data_exception(env, dxc, GETPC()); } +/* + * Unaligned accesses are only diagnosed with MO_ALIGN. At the moment, + * this is only for the atomic operations, for which we want to raise a + * specification exception. + */ +static void QEMU_NORETURN do_unaligned_access(CPUState *cs, uintptr_t retaddr) +{ + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + + tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr); +} + #if defined(CONFIG_USER_ONLY) void s390_cpu_do_interrupt(CPUState *cs) @@ -106,6 +119,12 @@ void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, cpu_loop_exit_restore(cs, retaddr); } +void s390_cpu_record_sigbus(CPUState *cs, vaddr address, + MMUAccessType access_type, uintptr_t retaddr) +{ + do_unaligned_access(cs, retaddr); +} + #else /* !CONFIG_USER_ONLY */ static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx) @@ -593,17 +612,11 @@ void s390x_cpu_debug_excp_handler(CPUState *cs) } } -/* Unaligned accesses are only diagnosed with MO_ALIGN. At the moment, - this is only for the atomic operations, for which we want to raise a - specification exception. */ void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; - - tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr); + do_unaligned_access(cs, retaddr); } static void QEMU_NORETURN monitor_event(CPUS390XState *env, From patchwork Tue Nov 2 11:07:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516684 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4444406iml; Tue, 2 Nov 2021 05:02:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyEi/IOCi20HNYKn17AqkzngALyBP2ymyqsSxIKfetCin9RlYln9lg8CRWf98i7koF3EIVY X-Received: by 2002:a05:6808:14d6:: with SMTP id f22mr4591103oiw.101.1635854575669; Tue, 02 Nov 2021 05:02:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635854575; cv=none; d=google.com; s=arc-20160816; b=umd0pwl1AeiwknmYCvwP3ddir7NiOW6DDhuwPAU1jIE0yJlekIXGh8cmlySiq9f/Pt K/pODaHv+0qD3xMpLUCXB+JuVezEzDix1NtHRuBHl0rfWCfQJcloMMtUsR/Az8MKky0E Hnk4L2JGVLP7ypKGy55HAZMlC1aXQ3Af4iRcGTP4sIbuKNB9qrC4jybHfUkZhRJRHBwA UjUnpaovklPEZMM8ptFVOM3Eu31p9bmplWAJkGwW9HCD0gL8bhCIW0nS8omfIZpcKPsg X94kAREvZYvP0vR2T1tl9IAGEniBQpijeQGZb6KsYi1P/Dv1OIJt6t4i8ZJjtXYixNsp lr2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3/CJUXQvBCEoPlihnnAPxMwhS0SfN83B4jFLy6O6YSI=; b=aMqvI700BqbAztkGcFIIruM6UUittvfLmtiRInv32davZwxbFfNoJIcsH0u1JFXCR8 f2bfwTOd8ec6e+f4AkrPBGBspmWXdhiroMGud98HrjikyXMYvaaRDngN6EGlpETlIcea x5D9XkTVmtu3p46hp4KjmGG85XLaI9ypNLJf71ZxZyrKRUJTd243mNeVENGoaXr22lpC oBiZTl8cAwxiLccSPXoi8h7VsnLdWxjm6dQHpzoTvQsTwJT0y9jQCCFbB0KZijWJP5eA 8xwGkqGwkmrjgAuQXUG5BFTGliktKGXlJ/yFc3iqEM+/dEXW/vw0uMHNTbUdT4fZOxvM U/+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HkmiMGny; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 53/60] target/sh4: Set fault address in superh_cpu_do_unaligned_access Date: Tue, 2 Nov 2021 07:07:33 -0400 Message-Id: <20211102110740.215699-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Yoshinori Sato Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We ought to have been recording the virtual address for reporting to the guest trap handler. Cc: Yoshinori Sato Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sh4/op_helper.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.25.1 diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index c996dce7df..752669825f 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -29,6 +29,9 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { + CPUSH4State *env = cs->env_ptr; + + env->tea = addr; switch (access_type) { case MMU_INST_FETCH: case MMU_DATA_LOAD: @@ -37,6 +40,8 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, case MMU_DATA_STORE: cs->exception_index = 0x100; break; + default: + g_assert_not_reached(); } cpu_loop_exit_restore(cs, retaddr); } From patchwork Tue Nov 2 11:07:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516668 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4433685iml; Tue, 2 Nov 2021 04:51:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz7Y5hlHJ0+lFOoYGWkuP5Yonf14UvY3K2N8q8qnkuDXywGpXVt8QwxJoXftH71p9fOOISa X-Received: by 2002:aca:674a:: with SMTP id b10mr4699659oiy.60.1635853889549; Tue, 02 Nov 2021 04:51:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635853889; cv=none; d=google.com; s=arc-20160816; b=DVfe1isGeG7rk5nELXQ7ESwnE8BRAW4DIDFSa7wepdHLWCvnKRWiuy3f1h53klpS4f IqqMgA32Kr1aVb4FMGC9HD/NSG3oSoYW3wYk9GSySiUpnv8g1hdgI/E7QcOk6stOz388 WAS3IrBWofurmdqiusaqODMDs8v3AfrUjnF3NtdtuJeFN1XJVFfEm4FuMi4BucTIzHuZ /dGheEy29ER+I5lD7exQMcjECVPftn0CIC2aCefNctG5CUwQ8Rx0ooMlA+/33iRFb6ma DE0JDNGkNKX3Vu9bsdAb3UVZ1o5UGocmqpJ90UiU24ICwUzSRybDi6kpZ8nQPNdPPSgj fEOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=P+LiSx7CkE3blKbhg5ALaxOT08dtFOhalcqlNc9ibvc=; b=fst8PPiKYis4JToQFX+5Qan5hw+M0FHWjD02ED067j0InfbFC/mu0PjU1fWF0BsY6p zoGNdyX/YME8CfRYzg+Z9BLNlRN4E07MDXpKp98/cSdPytaGwmjxoY4ZAzZ7lPpdqwfw B5LpzDCvZRuPbxM7ylXrVkOc/ljVlpwokvuv6yiLcvqnCfk1PBwD/hSdmLfuk3GOjnns B3Pk+VeQwCwoxj3RuxAcSSjJ2KxmEl6CXOBWVgkF3oTeIsjOBXPOFwWu0hXNQhi4/Fh7 KMJH6SGP+XvWUzrl55sEeVtyf8q15JNt56dFu2CDCOEQJGigRZb2bY+/xJr95wYS6iC2 zW4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Usx/HpVA"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 54/60] target/sparc: Remove DEBUG_UNALIGNED Date: Tue, 2 Nov 2021 07:07:34 -0400 Message-Id: <20211102110740.215699-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82f; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The printf should have been qemu_log_mask, the parameters themselves no longer compile, and because this is placed before unwinding the PC is actively wrong. We get better (and correct) logging on the other side of raising the exception, in sparc_cpu_do_interrupt. Reviewed-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 9 --------- 1 file changed, 9 deletions(-) -- 2.25.1 diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index bbf3601cb1..0549b6adf1 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -27,7 +27,6 @@ //#define DEBUG_MMU //#define DEBUG_MXCC -//#define DEBUG_UNALIGNED //#define DEBUG_UNASSIGNED //#define DEBUG_ASI //#define DEBUG_CACHE_CONTROL @@ -364,10 +363,6 @@ static void do_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align, uintptr_t ra) { if (addr & align) { -#ifdef DEBUG_UNALIGNED - printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx - "\n", addr, env->pc); -#endif cpu_raise_exception_ra(env, TT_UNALIGNED, ra); } } @@ -1968,10 +1963,6 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; -#ifdef DEBUG_UNALIGNED - printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx - "\n", addr, env->pc); -#endif cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } #endif From patchwork Tue Nov 2 11:07:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516686 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4447541iml; Tue, 2 Nov 2021 05:05:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy7UtJ9187zl/xPxMwN3nt2eeL8mgBdYZWKqAHZLS5yAoVDRnrD4qVTXMd6J4oHLXMk0I0o X-Received: by 2002:a54:4594:: with SMTP id z20mr4498659oib.17.1635854738273; Tue, 02 Nov 2021 05:05:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635854738; cv=none; d=google.com; s=arc-20160816; b=S6/pwvqQBk8eGEp3btdGXpruBmMWM/BnIpcSNQowr53gh/HwDNCxegUI5P8r9rge2l FkuAUazYecb5lSxFQ1Iez8mK2NEgj5B3Vpf7KNaETkMh4azOhDIhwmwcbgGySI/2eD/P lGTJEO76Qmy/DxfiUWuldWCyIrH0oUEBVuYdowSXCvAl3vi8oVSU0/xn0GxPPDzPT5vg skcuaoA3UbL9uh2O08HAAVqoPWhOPsxKcfhFcr1908TQ4H1m+dK+lqUYBT88avFeNmS9 UGffr+xVyYq1h+ydiCJnuI19qpnRlHLDnGT3zdcqFwlQQfmx6/y6hJ/7+dDM+IgiDrS5 bmAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fVhlPoABQmS8wc89+ovGDAnkicIV2MZx6WAeJyRD9lM=; b=mcGLE2O+lFPwg+BLuiAnVEnk51lKrJ/Oj6WSdQ36eKNPQaH0abJdyGB2xoP8k7592p nozsthjIH1pvkho/CifwBnrmOnDKA94RILJ0qOJ6notjUHBTu9SZG7Kam08YLWta+K/L U445pT0fl8KV31DRX5dGpykMk/6OnAbhC9uiixBIyXUzD6XYyDk+0Nw5yci2nqaLR9+d N6TFEuKaciNoTKe7KeqKmMjELB/M2mQEIyneVCmm161ChHwqwzMI0pyy8vEFpHiTAJPG vhMT87elpWzePKlZhLd4k4DzsAPYSdynIYevRoEPTOmbdq10NKKocXpvnWj8HSN/Ltd5 9LFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CTrjXneP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 55/60] target/sparc: Split out build_sfsr Date: Tue, 2 Nov 2021 07:07:35 -0400 Message-Id: <20211102110740.215699-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/mmu_helper.c | 72 +++++++++++++++++++++++++-------------- 1 file changed, 46 insertions(+), 26 deletions(-) -- 2.25.1 diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 2ad47391d0..014601e701 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -502,16 +502,60 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *tlb, return 0; } +static uint64_t build_sfsr(CPUSPARCState *env, int mmu_idx, int rw) +{ + uint64_t sfsr = SFSR_VALID_BIT; + + switch (mmu_idx) { + case MMU_PHYS_IDX: + sfsr |= SFSR_CT_NOTRANS; + break; + case MMU_USER_IDX: + case MMU_KERNEL_IDX: + sfsr |= SFSR_CT_PRIMARY; + break; + case MMU_USER_SECONDARY_IDX: + case MMU_KERNEL_SECONDARY_IDX: + sfsr |= SFSR_CT_SECONDARY; + break; + case MMU_NUCLEUS_IDX: + sfsr |= SFSR_CT_NUCLEUS; + break; + default: + g_assert_not_reached(); + } + + if (rw == 1) { + sfsr |= SFSR_WRITE_BIT; + } else if (rw == 4) { + sfsr |= SFSR_NF_BIT; + } + + if (env->pstate & PS_PRIV) { + sfsr |= SFSR_PR_BIT; + } + + if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */ + sfsr |= SFSR_OW_BIT; /* overflow (not read before another fault) */ + } + + /* FIXME: ASI field in SFSR must be set */ + + return sfsr; +} + static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, int *prot, MemTxAttrs *attrs, target_ulong address, int rw, int mmu_idx) { CPUState *cs = env_cpu(env); unsigned int i; + uint64_t sfsr; uint64_t context; - uint64_t sfsr = 0; bool is_user = false; + sfsr = build_sfsr(env, mmu_idx, rw); + switch (mmu_idx) { case MMU_PHYS_IDX: g_assert_not_reached(); @@ -520,29 +564,18 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, /* fallthru */ case MMU_KERNEL_IDX: context = env->dmmu.mmu_primary_context & 0x1fff; - sfsr |= SFSR_CT_PRIMARY; break; case MMU_USER_SECONDARY_IDX: is_user = true; /* fallthru */ case MMU_KERNEL_SECONDARY_IDX: context = env->dmmu.mmu_secondary_context & 0x1fff; - sfsr |= SFSR_CT_SECONDARY; break; - case MMU_NUCLEUS_IDX: - sfsr |= SFSR_CT_NUCLEUS; - /* FALLTHRU */ default: context = 0; break; } - if (rw == 1) { - sfsr |= SFSR_WRITE_BIT; - } else if (rw == 4) { - sfsr |= SFSR_NF_BIT; - } - for (i = 0; i < 64; i++) { /* ctx match, vaddr match, valid? */ if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) { @@ -592,22 +625,9 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, return 0; } - if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */ - sfsr |= SFSR_OW_BIT; /* overflow (not read before - another fault) */ - } - - if (env->pstate & PS_PRIV) { - sfsr |= SFSR_PR_BIT; - } - - /* FIXME: ASI field in SFSR must be set */ - env->dmmu.sfsr = sfsr | SFSR_VALID_BIT; - + env->dmmu.sfsr = sfsr; env->dmmu.sfar = address; /* Fault address register */ - env->dmmu.tag_access = (address & ~0x1fffULL) | context; - return 1; } } From patchwork Tue Nov 2 11:07:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516687 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4451383iml; Tue, 2 Nov 2021 05:08:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwW9N1nzVFgFTqw+g23AfuXBYgjt52M4Ac4PTpDRYsDe22ZDjBVaUPA7jhfiPX3z4noGL7d X-Received: by 2002:a9d:70c9:: with SMTP id w9mr25377161otj.243.1635854923670; Tue, 02 Nov 2021 05:08:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635854923; cv=none; d=google.com; s=arc-20160816; b=ex5u4uiiM+mtInT8p//2PeF1RSldk1DXW3tURcxb3eWCXz1PZdAzsvnZWjmgX1mnFd WzUiEKLm3DpkX30ygaO0y0TosdSxAuRt3U09CYRjj+Q0Yzz5OY8Jkg/UCVwrmRtBF+7+ mFmlF6ehVDERyrO1txndR9TyDaNqJuwKtGF5Y/kCylSGGpep85Pr4PcJa7aTNq1Xkp2x /AZ+jgHjraPNYEu4q9w9SvjVRBGrdku5ZEtJzXTmKmLaFGnd4BlHPTQjfv7HvMvLgPbi CF3T+rMOStFp/u8tsLlVNUkaDg/szSPaHUnEIl11tBhjgG8p2nqbWdMh9tsNvLNrkWaR go9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=muffzeHX3yZuoAcxrWs0UhKgv9u/j8rmCNk7xQHU/Hc=; b=OQLrXies6lK7gH9QCQb1svi92i0/hUSTGS0zDn1WVE7Xh8jZ/Ut2nDvpnsVu9/KgkZ xtqk1dfwXg4WGvuHblpoNBe3M5UPzvtnJ4tEpZtRkPSFlyWnl9JJSRjwPAlbQTI9AWUz mU4c9uO8QARJSgSAPOn9qkeWBhKkTpjzEOPxDjIDbLDpmPB2slz0y9bkL1dGZEAcBNR9 LB0w5Zr6DJi+bgvQIPUqRgiphqrtBMRRjjAw8p43GE0AwpwMlTy/xVtv6Ti6OkUUVTG5 ZYnT7/BwKrv0FKGv977pYLz6b8c/xtkL3CDlNTmzvw0YrqYZpOIATq0ZZbSzHOlYdfn5 wLQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lj+prjzC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 56/60] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Date: Tue, 2 Nov 2021 07:07:36 -0400 Message-Id: <20211102110740.215699-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82f; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We ought to have been recording the virtual address for reporting to the guest trap handler. Move the function to mmu_helper.c, so that we can re-use code shared with get_physical_address_data. Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 13 ------------- target/sparc/mmu_helper.c | 20 ++++++++++++++++++++ 2 files changed, 20 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 0549b6adf1..a3e1cf9b6e 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1953,16 +1953,3 @@ void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, is_asi, size, retaddr); } #endif - -#if !defined(CONFIG_USER_ONLY) -void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, - uintptr_t retaddr) -{ - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - - cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); -} -#endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 014601e701..f2668389b0 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -922,3 +922,23 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } return phys_addr; } + +#ifndef CONFIG_USER_ONLY +void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, + uintptr_t retaddr) +{ + SPARCCPU *cpu = SPARC_CPU(cs); + CPUSPARCState *env = &cpu->env; + +#ifdef TARGET_SPARC64 + env->dmmu.sfsr = build_sfsr(env, mmu_idx, access_type); + env->dmmu.sfar = addr; +#else + env->mmuregs[4] = addr; +#endif + + cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); +} +#endif /* !CONFIG_USER_ONLY */ From patchwork Tue Nov 2 11:07:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516672 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4435645iml; Tue, 2 Nov 2021 04:53:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz4GetkreMc8rIW17qgeE9PJ3YdompmvXUcnyKzlsQj71yH8ZIhcjc5lgNJkupTAZikPYI4 X-Received: by 2002:a05:6808:1524:: with SMTP id u36mr4724186oiw.13.1635854022210; Tue, 02 Nov 2021 04:53:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635854022; cv=none; d=google.com; s=arc-20160816; b=kD3UitLn8v5GzrzLToJPYAPiWLMM1kr5eRXOfEOyKhhGiRf39M2pYAa+vDOqVFsbDf pUXNEYC7o9hGyTmrYxjAN2icLrJKvS7lk3GXKdyIaOlWuOI3zMzc6Yag8aE6QzbLrFZt +OvQ0A/Y8uB4NXTKmH/toMP1t9vyFWayiPM//ym5U/F4GxtbX1kchfCYbrK6ZfpN5yuS zM+TzONYH9B5wmF0uc4aBtE0SObrgDV0NoexXk39fv8DbToGH1wvIpQymPcCsg0muhY6 muEitiRQuZbU8LYix5d8TBYFLuTSFdhE1XHNctggV2CF6us0T5mNddk1pbrzsXn2WQZ/ G1Tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=G7SBr/WksrEb3wfGw9+4/7HGKeZrYxUMshTizcIBHp0=; b=Jcxv/Mju1YYGMdfRzTmd1rEnYG/24KNunaHXkoTeSKt8pXo85M5W+tuZJnDzXh0q4w Jky6Reg4KMwFK/5PlzcJ4tJGhVkL+QquHt7XnYH6oqOgG8af6k4dSKUEJfDJIgko4BpA 1420OJJHYdfhtg1ozIUPgNhUPYqwJlLFgOgLhSJfITb/OgZfYB2x0qHevmcoL1P794Gq ghJCHqNfn6nyyHqqChyjIz0PAlWwpCHD9lBShg4a0HblqkWsJQ94G6jHBS1o2tgJvK2u Tc2zVRQM9qSzkN0Xyk6X1Ys+99/nnwEykGoLPe7VzEQai+3Yj4JdeC2ZTAs9xW9TJuaq yMqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hwOxAJR3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 57/60] accel/tcg: Report unaligned atomics for user-only Date: Tue, 2 Nov 2021 07:07:37 -0400 Message-Id: <20211102110740.215699-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82d; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the new cpu_loop_exit_sigbus for atomic_mmu_lookup, which has access to complete alignment info from the TCGMemOpIdx arg. Reviewed-by: Warner Losh Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index c4f69908e9..1ee64f01fc 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -474,11 +474,22 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, int size, int prot, uintptr_t retaddr) { + MemOp mop = get_memop(oi); + int a_bits = get_alignment_bits(mop); + void *ret; + + /* Enforce guest required alignment. */ + if (unlikely(addr & ((1 << a_bits) - 1))) { + MMUAccessType t = prot == PAGE_READ ? MMU_DATA_LOAD : MMU_DATA_STORE; + cpu_loop_exit_sigbus(env_cpu(env), addr, t, retaddr); + } + /* Enforce qemu required alignment. */ if (unlikely(addr & (size - 1))) { cpu_loop_exit_atomic(env_cpu(env), retaddr); } - void *ret = g2h(env_cpu(env), addr); + + ret = g2h(env_cpu(env), addr); set_helper_retaddr(retaddr); return ret; } From patchwork Tue Nov 2 11:07:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516685 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4444897iml; Tue, 2 Nov 2021 05:03:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxzg8xVNt8yJ1x9fbxBptdD5+M/AGKAqwlUPyMShWswSD2Fu0kMcl5p7aYgBwKQvDD/suoy X-Received: by 2002:a05:6808:10d2:: with SMTP id s18mr4735395ois.30.1635854598384; Tue, 02 Nov 2021 05:03:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635854598; cv=none; d=google.com; s=arc-20160816; b=vHgO4xNeACBC9jyY+4vHZ01Q6M048FXgSiMu76CLYldVXP+oOLgxjbCkIuMLBuSk6s WDrjMJohZrII9xgzNORtZu0mbCDFRxWvSePt1Yrc3KvkxwKEBGDitcU5CbNJuz0DuJ8w t3tRowWWnTJwobBxBRugCg+dt+DbbERt7V3dTzeERpIOqlNnp/S9L5XnFKUSInurbm9G zUoItaiBPMBT+Z4XZ3wT7HYBx7ihKHhFbuI13rFl9qUi2qcyRYA2BkFX2l3o6K/i4EjI /EItUGuA+C5L+wUtDr5dYwsgZ+pwclZAWMg1F5tFQUTXNx7MOAGDZj31y3YrzDTzGkG2 zY+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MIsR5ntgtAsaxoJ+NtIU7qk3vK65x7GB6eb5bSAQ4NA=; b=lCTbsxlK7TvjqwsNoVph5fsWJy9GUr/gWfdvjunUEr496ahJN0d15daMC2HJ66pxB5 fb//Ai+b2dgolh9pJJONdwIeKB92XGccffTq0iMoHXa/zIHqa6570fg85hX/Ir7uZ5Cm +hJ5O4pK4wNTEGn19xrPaXL98DRGDb2NZENMaIjNo8VqWMCNPZpPFg9/e9aYJcZ8ssa+ uo8waWS4jh0WG5ZtErkenKd7GFp6VlPOE/p1FABzuCdOK7Uri5lmOJ1GZeOPF31GeKcc lxaTWNxRzr9fBj+XG3Xb+VBBND5xRmBXPANdlUMduxD8SPcI18kMqcc+QxFhiD+N2sNa j1Vg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=idtZ3bpW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 58/60] accel/tcg: Report unaligned load/store for user-only Date: Tue, 2 Nov 2021 07:07:38 -0400 Message-Id: <20211102110740.215699-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82e; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?b?YXVkw6k=?= , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the new cpu_loop_exit_sigbus for cpu_mmu_lookup. Reviewed-by: Warner Losh Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 1ee64f01fc..aaf47d89d2 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -218,9 +218,14 @@ static void validate_memop(MemOpIdx oi, MemOp expected) static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t ra, MMUAccessType type) { + MemOp mop = get_memop(oi); + int a_bits = get_alignment_bits(mop); void *ret; - /* TODO: Enforce guest required alignment. */ + /* Enforce guest required alignment. */ + if (unlikely(addr & ((1 << a_bits) - 1))) { + cpu_loop_exit_sigbus(env_cpu(env), addr, type, ra); + } ret = g2h(env_cpu(env), addr); set_helper_retaddr(ra); From patchwork Tue Nov 2 11:07:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516678 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4438200iml; Tue, 2 Nov 2021 04:56:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyELTic1EsNj9w8aW+KnXb4N3VdObkwkR/WfNThWonofODamRYeeqZNEr2TFnbz+4K7F1vC X-Received: by 2002:a05:6808:34a:: with SMTP id j10mr2147999oie.6.1635854215866; Tue, 02 Nov 2021 04:56:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635854215; cv=none; d=google.com; s=arc-20160816; b=E+ECxuOh9WF+fxR/rGxy/8W2pUb9tcYtuU/7I0oPFzB6K/uGLGS3jJiQOPmqVExwbh bx2t4txJkMDwaw2Xg9FZgm0to7vj+JGGaeT7x3KIGnDd/iwURgkZRtvTQ+TDKKaiCi+l /2scQZ2x1qFB70Y6050xnLGmlMvDc5jOAq3Dg8PKwz8K/TMuaeklxHOBpIIa6A+cPa+5 ENBYWkvv3vNd2OIHkI+RZoUrVI5FRWx07jO+ookCkDJnz93qVRZLpSSHj9jzZYfZhyBC 7iVtIPL+qrYFpnz8N9VnVeQrumHDK2ISHra6mvlfIKFW/Sy6BhsGF6htaKmOY9p1Pgr+ hnvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7mVMLvhvHhRE4SNYEq8lTvIaJ67DT2EyP7H4YHihO6k=; b=U9StnR0VBxxKDjIQH2MoNDxHBEUbn12VpGs157cT6Aq7x4ihBg9X3ca3mFaNr6G5LS ceQq68wa59mHw5BgIAOKTPr4m3YzSwi/8qKThHBl7ZBSXq3G5EQvHBWlSADWCtN0drRy fKhsOz0kgwgLor3fiBSNc3Dob5SxZoobeTJV1BuFDOUTxtG1LC3/x/kXSmu2ToNQKn6J hds92MXixtcgNe0z3QtJjQs/XfEgy6oTYwMfMr1nw8zbpRy00PmkKCiLPz6beokPGJ9u J5gcWojBwAamBWyXkXgyrhQs6bxCZdJDFUwHDnC52Hx6SLevSreb3TMw5tycoiANzJhd hOqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EXCMgBL6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 59/60] tcg: Add helper_unaligned_{ld, st} for user-only sigbus Date: Tue, 2 Nov 2021 07:07:39 -0400 Message-Id: <20211102110740.215699-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82b; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?b?YXVkw6k=?= , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" To be called from tcg generated code on hosts that support unaligned accesses natively, in response to an access that is supposed to be aligned. Reviewed-by: Warner Losh Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 5 +++++ accel/tcg/user-exec.c | 11 +++++++++++ 2 files changed, 16 insertions(+) -- 2.25.1 diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index 8c86365611..bf40942de4 100644 --- a/include/tcg/tcg-ldst.h +++ b/include/tcg/tcg-ldst.h @@ -70,5 +70,10 @@ void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr); +#else + +void QEMU_NORETURN helper_unaligned_ld(CPUArchState *env, target_ulong addr); +void QEMU_NORETURN helper_unaligned_st(CPUArchState *env, target_ulong addr); + #endif /* CONFIG_SOFTMMU */ #endif /* TCG_LDST_H */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index aaf47d89d2..1528a21fad 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -27,6 +27,7 @@ #include "exec/helper-proto.h" #include "qemu/atomic128.h" #include "trace/trace-root.h" +#include "tcg/tcg-ldst.h" #include "internal.h" __thread uintptr_t helper_retaddr; @@ -215,6 +216,16 @@ static void validate_memop(MemOpIdx oi, MemOp expected) #endif } +void helper_unaligned_ld(CPUArchState *env, target_ulong addr) +{ + cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_LOAD, GETPC()); +} + +void helper_unaligned_st(CPUArchState *env, target_ulong addr) +{ + cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_STORE, GETPC()); +} + static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t ra, MMUAccessType type) { From patchwork Tue Nov 2 11:07:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516681 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp4439582iml; Tue, 2 Nov 2021 04:58:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx/vnnopQrDmRGEumLUaRDl4hLb7g8v3Z0csqY7lzHT6IToyP7uPU7dn8ozQEpf1DEV4QIY X-Received: by 2002:a05:6808:116:: with SMTP id b22mr4815952oie.80.1635854313141; Tue, 02 Nov 2021 04:58:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635854313; cv=none; d=google.com; s=arc-20160816; b=s2OOcLdBFnvb1cuSVZHNynZUlOQCBKy24q5V0AX38/IdRMzB3IyMy0e6raTCcdl8Ba SbESOFxU4LENup9kPGpSKX0JitVD+GEAB3dFKJeAHijfLHQKma7sh537ycHfmXEvsXdD 5GSrtWhv0nZxBr5gMis3VmN4GwpWew+JMHJZY8Z5MkS2Iqeu/TRz+PEdFB4K8hIPV04u HYQtrcrNrIa2DjbCePh72a388m/XwnTDPqj/wsldbRxSV/0Z/b8k0yzXbjiJtYDHTIC8 SkcTrpU+D1TDz5WWi/ckvb8ToFAIDVUx7oAu+OTXuU8LIwY+dPTR11eUeXj84+OcUhnE WVMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7lLZzifCuDAFtBOJRXRut8iWPXEYL/L2LC9pwY/6QWY=; b=Dhh+HSZa1AGawRJIqqJkFhjcNASOf6BYyeR1NJnl1E0lZ1wlfr+A8uQw7i5ZUx8E4B NiebpAMxBAsVJXsvfKz9L7qbOLdjIf05EoUyhyZNXYlVs6Dagu/F4KxGi1wsIuahDxw0 kKxvTonwz5KhcGbgd+XzPxbYstVVH1wYdfW71eqi3hLX/Tm/SclMrTMl81kB07f02pSh incRvJuW4tIso2jQZ0xtvYN0OsPYMiw4O/HTP3nZ2W6p4vlRQdZFlKLTpI3dbRJhk1NT jxPyta9s/ZRkysGPrRjxFHzdgsvlBTz6DS9P5gxscpweIllboZI8BMSk6eH6JjX9wmnN VPTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G1hYnCJ1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id bm25sm12730854qkb.4.2021.11.02.04.11.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 04:11:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 60/60] linux-user: Handle BUS_ADRALN in host_signal_handler Date: Tue, 2 Nov 2021 07:07:40 -0400 Message-Id: <20211102110740.215699-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org> References: <20211102110740.215699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82d; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Handle BUS_ADRALN via cpu_loop_exit_sigbus, but allow other SIGBUS si_codes to continue into the host-to-guest signal conversion code. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/signal.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.25.1 diff --git a/linux-user/signal.c b/linux-user/signal.c index df2c8678d0..81c45bfce9 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -860,6 +860,9 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) cpu_loop_exit_sigsegv(cpu, guest_addr, access_type, maperr, pc); } else { sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + if (info->si_code == BUS_ADRALN) { + cpu_loop_exit_sigbus(cpu, guest_addr, access_type, pc); + } } sync_sig = true;