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[209.51.188.17]) by mx.google.com with ESMTPS id j26si992304ota.83.2021.10.19.20.23.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 20:23:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EQ45ZpCs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39184 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1md2Cl-0000De-E0 for patch@linaro.org; Tue, 19 Oct 2021 23:23:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46924) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1md26O-0006e5-LK for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:16 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:44712) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1md26L-0000xC-5L for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:15 -0400 Received: by mail-pg1-x52f.google.com with SMTP id c4so14192138pgv.11 for ; Tue, 19 Oct 2021 20:17:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ur4NYkKvb4IwfCVRQ66xGSUcq2q0ktl5nOkYZP/fju8=; b=EQ45ZpCss11u9/H9zCTM1UlxDR2TGB5KJirQvX8fhq663PGxaAASGAUs9PTiCUFdxL 68enrZz6TMy7yIAxgbPZ0BRWwkSL3OWobI8pHl2oy4AJOd59JvAiKs06I512REplpcdj zhxp75iVha4rpBND+caFTsPd+0eKSH0fdRbep0eXfsl1ibw1VK0M6On+9HJqeZldyn5o fAzEqvNs28zq6Y3dbzt1dMnQDJfyReN43myv3cKqsqyzazbJxwQ+LrRnUcuVILzmmNgp N5G6OZQAfrVY5Uci1youjFF/j2hxpSLU/zIOBtPdTDlpM0xfLwl6L5NalGsD5ohDMj2b BL0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ur4NYkKvb4IwfCVRQ66xGSUcq2q0ktl5nOkYZP/fju8=; b=jVrBGEsUWGDeBn7oIY8nrIePZ/Hbox7wZgk+w6cauv4zv6sExdjxpewvvkHYB7NEvG btiwGzgD1KDmEwoy+t7FsBf+xqkfb9tIYwAOktDvYBjkqK9ilCHIED6xk0pUUSaowVHw CCHNBhaquW5CaxIlYI74fdwQk8W19nem7IOp3mdrW51/xs0IFzzLjCXPKoFrmNipX7/k pix/93Z/ZeNxSXKByZwWDhIoGUiw8FQf2KAtIe+GmTSOTNaDF8GEuTxkcL7DA6KxGIKC NDoV4g12NnNTbGOAXeWoOF6W4t3cjEYVk0wYrux8nlJFjKHnRFicVRsPgyntuwAJTwpA TwbA== X-Gm-Message-State: AOAM532LZSE9uE/8jTPNRUs3GOYhzWOPSb8GocxVilPrSS9ItXhz4vAb ixip/ZOqNN0kqvcHmBsyB/0qivQQiA9VxQ== X-Received: by 2002:a62:77d8:0:b0:44c:8618:1bed with SMTP id s207-20020a6277d8000000b0044c86181bedmr3734409pfc.27.1634699831758; Tue, 19 Oct 2021 20:17:11 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id c8sm505364pjr.38.2021.10.19.20.17.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 20:17:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 01/15] target/riscv: Move cpu_get_tb_cpu_state out of line Date: Tue, 19 Oct 2021 20:16:55 -0700 Message-Id: <20211020031709.359469-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020031709.359469-1-richard.henderson@linaro.org> References: <20211020031709.359469-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the function to cpu_helper.c, as it is large and growing. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 47 ++------------------------------------- target/riscv/cpu_helper.c | 46 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 45 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9e55b2f5b1..7084efc452 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -413,51 +413,8 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) return cpu->cfg.vlen >> (sew + 3 - lmul); } -static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *pflags) -{ - uint32_t flags = 0; - - *pc = env->pc; - *cs_base = 0; - - if (riscv_has_ext(env, RVV)) { - uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); - bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); - flags = FIELD_DP32(flags, TB_FLAGS, VILL, - FIELD_EX64(env->vtype, VTYPE, VILL)); - flags = FIELD_DP32(flags, TB_FLAGS, SEW, - FIELD_EX64(env->vtype, VTYPE, VSEW)); - flags = FIELD_DP32(flags, TB_FLAGS, LMUL, - FIELD_EX64(env->vtype, VTYPE, VLMUL)); - flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); - } else { - flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); - } - -#ifdef CONFIG_USER_ONLY - flags |= TB_FLAGS_MSTATUS_FS; -#else - flags |= cpu_mmu_index(env, 0); - if (riscv_cpu_fp_enabled(env)) { - flags |= env->mstatus & MSTATUS_FS; - } - - if (riscv_has_ext(env, RVH)) { - if (env->priv == PRV_M || - (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); - } - - flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, - get_field(env->mstatus_hs, MSTATUS_FS)); - } -#endif - - *pflags = flags; -} +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags); RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d41d5cd27c..14d1d3cb72 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -35,6 +35,52 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags) +{ + uint32_t flags = 0; + + *pc = env->pc; + *cs_base = 0; + + if (riscv_has_ext(env, RVV)) { + uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); + bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); + flags = FIELD_DP32(flags, TB_FLAGS, VILL, + FIELD_EX64(env->vtype, VTYPE, VILL)); + flags = FIELD_DP32(flags, TB_FLAGS, SEW, + FIELD_EX64(env->vtype, VTYPE, VSEW)); + flags = FIELD_DP32(flags, TB_FLAGS, LMUL, + FIELD_EX64(env->vtype, VTYPE, VLMUL)); + flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); + } else { + flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); + } + +#ifdef CONFIG_USER_ONLY + flags |= TB_FLAGS_MSTATUS_FS; +#else + flags |= cpu_mmu_index(env, 0); + if (riscv_cpu_fp_enabled(env)) { + flags |= env->mstatus & MSTATUS_FS; + } + + if (riscv_has_ext(env, RVH)) { + if (env->priv == PRV_M || + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); + } + + flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, + get_field(env->mstatus_hs, MSTATUS_FS)); + } +#endif + + *pflags = flags; +} + #ifndef CONFIG_USER_ONLY static int riscv_cpu_local_irq_pending(CPURISCVState *env) { From patchwork Wed Oct 20 03:16:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515988 Delivered-To: patch@linaro.org Received: by 2002:adf:a11e:0:0:0:0:0 with SMTP id o30csp1323194wro; Tue, 19 Oct 2021 20:27:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyv/KvZgC816J3hGo8DlY0Ar5BHX6zk/FxfAzD1qRGJCMBccMCZPeCF3HBJ31J59hrNzYWA X-Received: by 2002:a05:6830:1ad5:: with SMTP id r21mr8466981otc.98.1634700469745; Tue, 19 Oct 2021 20:27:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634700469; cv=none; d=google.com; s=arc-20160816; b=A1fpU5FaNxRBxzrd9HmUohZQ2MLtgNlNwTvB8it594aOvB4uyIRkETWwA/JAlmU5FK M/yGwpcXkIKOwrI3n+Cp0YRTA0G0QQF4ToOCTXk0TRBYQqL/3BkTie1JbUjv74bdQGl4 5MMjQ2vNSXTSyNOiedv8r5qhdEgOuE7y4mFsuUWON1cYT60/f9BFnvdnQUn5HvQHH+pw MSfjpTVkI/0DL16ytsPqldBbrowiF7yvPobgCtVf7Y+LbrCVUFdfT8iueIJXq0Zloirh U+87k5pamwqAsD2hYrQaOzSR7TI1oHzpUBtYp+0Mg90iIecG3EhFO9xABlKZ6jnM4nad Fj2w== ARC-Message-Signature: i=1; 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Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu_bits.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 999187a9ee..e248c6bf6d 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -364,9 +364,11 @@ #define MISA32_MXL 0xC0000000 #define MISA64_MXL 0xC000000000000000ULL -#define MXL_RV32 1 -#define MXL_RV64 2 -#define MXL_RV128 3 +typedef enum { + MXL_RV32 = 1, + MXL_RV64 = 2, + MXL_RV128 = 3, +} RISCVMXL; /* sstatus CSR bits */ #define SSTATUS_UIE 0x00000001 From patchwork Wed Oct 20 03:16:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515980 Delivered-To: patch@linaro.org Received: by 2002:adf:a11e:0:0:0:0:0 with SMTP id o30csp1318064wro; Tue, 19 Oct 2021 20:19:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxR0V0MWXJL9M5AAVVLY1GrJsB54vzB+OoevVU52IiyXV2uMHDmnGDGMoo7cnc17HQpDq/Q X-Received: by 2002:a05:6830:4009:: with SMTP id h9mr8465281ots.186.1634699972893; Tue, 19 Oct 2021 20:19:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634699972; cv=none; d=google.com; s=arc-20160816; b=nMGsSVUHgWCXRF74Kiv51fGJny9rx7xP3qmYt8ZO007/hN+0IYv2dh2fFWvE/Q8Zcx b8dZuopSPGz0lG3+SuIazJFy3GHfw9At1K0L0rHfmjW4+z+bSn+V41HFMSxgkl4Pwwfk gnrUKvui+/VGzctAe6XGnh3AGg7SYYh3eunrdmaTczO4v3cVBDrKi0YZq9h72jWuf3qb k7tPYs7YpUCEB2au9xOlh/vC5Us+/x12yliXtlnEgM2Mve2xmNA5f/kRDa2G2gEmQGs1 cXYe2ar5tB7q+9PhKdc7WkRlQEScPvlWNcenuHoBLVNudqOZzuizKQVqQvv/d35KSAMj DIvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=D7GROSee3GJQveP1Z96iGynB+uxZ+vhs7m8ajRi9Jq8=; b=Hdmy0EKl1MXWLWC25dGHakxGYUHqLVN+/JnnGjhHcjcn7TAUFCVB+id+vfCP8wQKQU VnbmUzYmSsTb9Xor1k9zXRCHwNGzEq10HPd+3q74JO6hCH0CZatNwO5TXE9KsYPYxnH7 z29YMR/h+m6IW+PMfnDCmpN71P/vvBVG8AQ5PDvw3PZ+OOglhR1gkkz4ZR0brvShTfgp 7EGcnEBzRKchqJdN+u+AvjDF6twFsaiD1kzXgPJHzpRN+jwJ1GknRJxji+2taqEHyhA4 qjk67i7x36H+NPXecXiEo6CLy6iZywpgOmIXRIY4BzzxJfDbkfiM4PmXdV8hQXLVZBez 6Dwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=xavMbKR0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j132si1028107oih.190.2021.10.19.20.19.32 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 20:19:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=xavMbKR0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54396 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1md28Z-0008Fi-W8 for patch@linaro.org; Tue, 19 Oct 2021 23:19:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46978) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1md26Q-0006iT-Ok for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:18 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:41631) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1md26M-0000yo-P9 for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:18 -0400 Received: by mail-pg1-x530.google.com with SMTP id t184so8252521pgd.8 for ; Tue, 19 Oct 2021 20:17:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D7GROSee3GJQveP1Z96iGynB+uxZ+vhs7m8ajRi9Jq8=; b=xavMbKR0iQ9aH4iGIBhuccV50dgyrKeVeL7ykUweaPvIgpDQHsqxCHlqQsSjTIwJkx ffv92VyhIRfLhN+/kkB+bek5lzChj8PthSzZaBKSgZIV8suW0xgZKWQql5sVzvA3nKrH 6ZX7AQRWXg2sulwz1Mou3BxCTyzQM8DTKuS4vb9LgLV7ui0k4dXFDT3AfXNu4zmwkrFt il3u/1pItUdpy3lryBKIA2N8mDHYh2Uhy+9ZjJSZiSU3aEW2tB3opRnPpyF6VxjE5EX1 Gw7wKCOeZHUHBa7rnkKsuJVB91dhGtRr52XkEjtK2QlKo4R7K41cxNDdP4sITsNUWik0 dcwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D7GROSee3GJQveP1Z96iGynB+uxZ+vhs7m8ajRi9Jq8=; b=LE6BGv6SAWBqh0aWqaXhNgGTsRHd0b9o9UwzrMIfWXL4gXe6bHjh5KTJYDwPtA4eDK bY0NT8XUF5fGJaJ/G8e0MZjQJe500An27gjWrXLSXlHxy1U0nFosdlkMG9JjKI7QkQoE J63s2UwSSmCNVyZmaBWUvgmkxLxG0QWcja2vlJD9qxk4F71iliLf/SM4yk04n5X609Qb UrPfoDK9lxkuuOe+Qx4hj6G0MNry3MT9fmzLE1hPQ21seq5sKkbnve9wvH5ab2wN0FB7 Mbcq9kXZo+nApDntnfkjWsySeUbfbTBxB+U7mF6xs5dqm1UlM3kktEtd0oel8OYxg1v6 yjvQ== X-Gm-Message-State: AOAM530OSIs7KCJ/KLZ+y2WT0FiKksPzrd4ldcA5Ax3jg1FRxHDGHmJ5 x8o70GCWuevvCALjTqKNPJt5ckbMYx4AUw== X-Received: by 2002:a05:6a00:16cb:b0:44b:bd38:e068 with SMTP id l11-20020a056a0016cb00b0044bbd38e068mr3796530pfc.34.1634699833232; Tue, 19 Oct 2021 20:17:13 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id c8sm505364pjr.38.2021.10.19.20.17.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 20:17:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 03/15] target/riscv: Split misa.mxl and misa.ext Date: Tue, 19 Oct 2021 20:16:57 -0700 Message-Id: <20211020031709.359469-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020031709.359469-1-richard.henderson@linaro.org> References: <20211020031709.359469-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The hw representation of misa.mxl is at the high bits of the misa csr. Representing this in the same way inside QEMU results in overly complex code trying to check that field. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 15 +++---- linux-user/elfload.c | 2 +- linux-user/riscv/cpu_loop.c | 2 +- target/riscv/cpu.c | 78 +++++++++++++++++++++---------------- target/riscv/csr.c | 44 ++++++++++++++------- target/riscv/gdbstub.c | 8 ++-- target/riscv/machine.c | 10 +++-- target/riscv/translate.c | 10 +++-- 8 files changed, 100 insertions(+), 69 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7084efc452..e708fcc168 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -25,6 +25,7 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" #include "qom/object.h" +#include "cpu_bits.h" #define TCG_GUEST_DEFAULT_MO 0 @@ -51,9 +52,6 @@ # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 #endif -#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) -#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) - #define RV(x) ((target_ulong)1 << (x - 'A')) #define RVI RV('I') @@ -133,8 +131,12 @@ struct CPURISCVState { target_ulong priv_ver; target_ulong bext_ver; target_ulong vext_ver; - target_ulong misa; - target_ulong misa_mask; + + /* RISCVMXL, but uint32_t for vmstate migration */ + uint32_t misa_mxl; /* current mxl */ + uint32_t misa_mxl_max; /* max mxl for this cpu */ + uint32_t misa_ext; /* current extensions */ + uint32_t misa_ext_mask; /* max ext for this cpu */ uint32_t features; @@ -313,7 +315,7 @@ struct RISCVCPU { static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) { - return (env->misa & ext) != 0; + return (env->misa_ext & ext) != 0; } static inline bool riscv_feature(CPURISCVState *env, int feature) @@ -322,7 +324,6 @@ static inline bool riscv_feature(CPURISCVState *env, int feature) } #include "cpu_user.h" -#include "cpu_bits.h" extern const char * const riscv_int_regnames[]; extern const char * const riscv_fpr_regnames[]; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 2404d482ba..214c1aa40d 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1448,7 +1448,7 @@ static uint32_t get_elf_hwcap(void) uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); - return cpu->env.misa & mask; + return cpu->env.misa_ext & mask; #undef MISA_BIT } diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 9859a366e4..e5bb6d908a 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -133,7 +133,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) env->gpr[xSP] = regs->sp; env->elf_flags = info->elf_flags; - if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) { + if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) { error_report("Incompatible ELF: RVE cpu requires RVE ABI binary"); exit(EXIT_FAILURE); } diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 660f9ce131..ca4c9cc9d1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,16 +110,13 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) bool riscv_cpu_is_32bit(CPURISCVState *env) { - if (env->misa & RV64) { - return false; - } - - return true; + return env->misa_mxl == MXL_RV32; } -static void set_misa(CPURISCVState *env, target_ulong misa) +static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) { - env->misa_mask = env->misa = misa; + env->misa_mxl_max = env->misa_mxl = mxl; + env->misa_ext_mask = env->misa_ext = ext; } static void set_priv_version(CPURISCVState *env, int priv_ver) @@ -148,9 +145,9 @@ static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; #if defined(TARGET_RISCV32) - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #elif defined(TARGET_RISCV64) - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif set_priv_version(env, PRIV_VERSION_1_11_0); } @@ -160,20 +157,20 @@ static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, RV64); + set_misa(env, MXL_RV64, 0); } static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); } static void rv64_sifive_e_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } @@ -182,20 +179,20 @@ static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, RV32); + set_misa(env, MXL_RV32, 0); } static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); } static void rv32_sifive_e_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } @@ -203,7 +200,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) static void rv32_ibex_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVC | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); qdev_prop_set_bit(DEVICE(obj), "mmu", false); qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); @@ -212,7 +209,7 @@ static void rv32_ibex_cpu_init(Object *obj) static void rv32_imafcu_nommu_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); set_resetvec(env, DEFAULT_RSTVEC); qdev_prop_set_bit(DEVICE(obj), "mmu", false); @@ -360,6 +357,7 @@ static void riscv_cpu_reset(DeviceState *dev) mcc->parent_reset(dev); #ifndef CONFIG_USER_ONLY + env->misa_mxl = env->misa_mxl_max; env->priv = PRV_M; env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); env->mcause = 0; @@ -388,7 +386,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) CPURISCVState *env = &cpu->env; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); int priv_version = 0; - target_ulong target_misa = env->misa; Error *local_err = NULL; cpu_exec_realizefn(cs, &local_err); @@ -434,8 +431,23 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_resetvec(env, cpu->cfg.resetvec); - /* If only XLEN is set for misa, then set misa from properties */ - if (env->misa == RV32 || env->misa == RV64) { + /* Validate that MISA_MXL is set properly. */ + switch (env->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + break; +#endif + case MXL_RV32: + break; + default: + g_assert_not_reached(); + } + assert(env->misa_mxl_max == env->misa_mxl); + + /* If only MISA_EXT is unset for misa, then set it from properties */ + if (env->misa_ext == 0) { + uint32_t ext = 0; + /* Do some ISA extension error checking */ if (cpu->cfg.ext_i && cpu->cfg.ext_e) { error_setg(errp, @@ -462,38 +474,38 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_i) { - target_misa |= RVI; + ext |= RVI; } if (cpu->cfg.ext_e) { - target_misa |= RVE; + ext |= RVE; } if (cpu->cfg.ext_m) { - target_misa |= RVM; + ext |= RVM; } if (cpu->cfg.ext_a) { - target_misa |= RVA; + ext |= RVA; } if (cpu->cfg.ext_f) { - target_misa |= RVF; + ext |= RVF; } if (cpu->cfg.ext_d) { - target_misa |= RVD; + ext |= RVD; } if (cpu->cfg.ext_c) { - target_misa |= RVC; + ext |= RVC; } if (cpu->cfg.ext_s) { - target_misa |= RVS; + ext |= RVS; } if (cpu->cfg.ext_u) { - target_misa |= RVU; + ext |= RVU; } if (cpu->cfg.ext_h) { - target_misa |= RVH; + ext |= RVH; } if (cpu->cfg.ext_v) { int vext_version = VEXT_VERSION_0_07_1; - target_misa |= RVV; + ext |= RVV; if (!is_power_of_2(cpu->cfg.vlen)) { error_setg(errp, "Vector extension VLEN must be power of 2"); @@ -532,7 +544,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_vext_version(env, vext_version); } - set_misa(env, target_misa); + set_misa(env, env->misa_mxl, ext); } riscv_cpu_register_gdb_regs_for_features(cs); @@ -705,7 +717,7 @@ char *riscv_isa_string(RISCVCPU *cpu) char *isa_str = g_new(char, maxlen); char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); for (i = 0; i < sizeof(riscv_exts); i++) { - if (cpu->env.misa & RV(riscv_exts[i])) { + if (cpu->env.misa_ext & RV(riscv_exts[i])) { *p++ = qemu_tolower(riscv_exts[i]); } } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 23fbbd3216..d0c86a300d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -39,7 +39,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) /* loose check condition for fcsr in vector extension */ - if ((csrno == CSR_FCSR) && (env->misa & RVV)) { + if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) { return RISCV_EXCP_NONE; } if (!env->debugger && !riscv_cpu_fp_enabled(env)) { @@ -51,7 +51,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) static RISCVException vs(CPURISCVState *env, int csrno) { - if (env->misa & RVV) { + if (env->misa_ext & RVV) { return RISCV_EXCP_NONE; } return RISCV_EXCP_ILLEGAL_INST; @@ -557,7 +557,22 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno, static RISCVException read_misa(CPURISCVState *env, int csrno, target_ulong *val) { - *val = env->misa; + target_ulong misa; + + switch (env->misa_mxl) { + case MXL_RV32: + misa = (target_ulong)MXL_RV32 << 30; + break; +#ifdef TARGET_RISCV64 + case MXL_RV64: + misa = (target_ulong)MXL_RV64 << 62; + break; +#endif + default: + g_assert_not_reached(); + } + + *val = misa | env->misa_ext; return RISCV_EXCP_NONE; } @@ -583,8 +598,13 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } + /* + * misa.MXL writes are not supported by QEMU. + * Drop writes to those bits. + */ + /* Mask extensions that are not supported by this hart */ - val &= env->misa_mask; + val &= env->misa_ext_mask; /* Mask extensions that are not supported by QEMU */ val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); @@ -601,20 +621,14 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, val &= ~RVC; } - /* misa.MXL writes are not supported by QEMU */ - if (riscv_cpu_is_32bit(env)) { - val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL); - } else { - val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL); + /* If nothing changed, do nothing. */ + if (val == env->misa_ext) { + return RISCV_EXCP_NONE; } /* flush translation cache */ - if (val != env->misa) { - tb_flush(env_cpu(env)); - } - - env->misa = val; - + tb_flush(env_cpu(env)); + env->misa_ext = val; return RISCV_EXCP_NONE; } diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index a7a9c0b1fe..5257df0217 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -54,10 +54,10 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) { if (n < 32) { - if (env->misa & RVD) { + if (env->misa_ext & RVD) { return gdb_get_reg64(buf, env->fpr[n]); } - if (env->misa & RVF) { + if (env->misa_ext & RVF) { return gdb_get_reg32(buf, env->fpr[n]); } /* there is hole between ft11 and fflags in fpu.xml */ @@ -191,10 +191,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; - if (env->misa & RVD) { + if (env->misa_ext & RVD) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-64bit-fpu.xml", 0); - } else if (env->misa & RVF) { + } else if (env->misa_ext & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-32bit-fpu.xml", 0); } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 16a08302da..f64b2a96c1 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -140,8 +140,8 @@ static const VMStateDescription vmstate_hyper = { const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", - .version_id = 2, - .minimum_version_id = 2, + .version_id = 3, + .minimum_version_id = 3, .fields = (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), @@ -153,8 +153,10 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), VMSTATE_UINTTL(env.priv_ver, RISCVCPU), VMSTATE_UINTTL(env.vext_ver, RISCVCPU), - VMSTATE_UINTTL(env.misa, RISCVCPU), - VMSTATE_UINTTL(env.misa_mask, RISCVCPU), + VMSTATE_UINT32(env.misa_mxl, RISCVCPU), + VMSTATE_UINT32(env.misa_ext, RISCVCPU), + VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), + VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), VMSTATE_UINT32(env.features, RISCVCPU), VMSTATE_UINTTL(env.priv, RISCVCPU), VMSTATE_UINTTL(env.virt, RISCVCPU), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d2442f0cf5..422f8ab8d0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -55,7 +55,8 @@ typedef struct DisasContext { /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; target_ulong priv_ver; - target_ulong misa; + RISCVMXL xl; + uint32_t misa_ext; uint32_t opcode; uint32_t mstatus_fs; uint32_t mstatus_hs_fs; @@ -86,7 +87,7 @@ typedef struct DisasContext { static inline bool has_ext(DisasContext *ctx, uint32_t ext) { - return ctx->misa & ext; + return ctx->misa_ext & ext; } #ifdef TARGET_RISCV32 @@ -96,7 +97,7 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) #else static inline bool is_32bit(DisasContext *ctx) { - return (ctx->misa & RV32) == RV32; + return ctx->xl == MXL_RV32; } #endif @@ -538,7 +539,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #else ctx->virt_enabled = false; #endif - ctx->misa = env->misa; + ctx->xl = env->misa_mxl; + ctx->misa_ext = env->misa_ext; ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei; ctx->vlen = cpu->cfg.vlen; From patchwork Wed Oct 20 03:16:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515992 Delivered-To: patch@linaro.org Received: by 2002:adf:a11e:0:0:0:0:0 with SMTP id o30csp1328055wro; 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[209.51.188.17]) by mx.google.com with ESMTPS id s187si1102626yba.514.2021.10.19.20.36.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 20:36:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BdpD1dkv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60486 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1md2Oh-0006ff-NB for patch@linaro.org; Tue, 19 Oct 2021 23:36:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47300) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1md26d-0007R1-Ub for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:31 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:45997) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1md26N-000103-Ns for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:31 -0400 Received: by mail-pg1-x531.google.com with SMTP id f5so21217760pgc.12 for ; Tue, 19 Oct 2021 20:17:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ouxGacCHYq5iWO7kFFFtOpM56HfospQii7K/BoDUkfg=; b=BdpD1dkv29yWb48F5IsFOpHSFBm4qkYkqOtPfGgBj2qC82Vat1rmQV9p5Gkz7FDkMH Q00UtOBfnSdGxo4ihrAOdJBQdTJ2J5f2oD2juQrxzID8q+V1OwGOZlIOGzqPW8W/wA6x hwCLdkdAGNjTtPJmD0pUAIUQbTtjWuA0no/M5htLeNdO+ephhom65FLXMl3VQ1l94sZm 1OGGFcjT/hjlo0Zux7HeMLRrIVYrXw5uUItp7bL1b3lRVLZGf5uAfBTo64GallgwqTkF wZ9TDk9U1Dsqj7xbZgCvMY/i20EC6JwS4FqzrImQ4slaGpeO4HUzOoDOJ9LlTfGTiTaS 5uXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ouxGacCHYq5iWO7kFFFtOpM56HfospQii7K/BoDUkfg=; b=7NnO8NtxiHmq3KUTYzmijjDOp4Lm8RKAzCtFbe6B7qxDh2wb+wrr4hNZCjZL54O5ID bllgR0GIVXW1qJNtIOgMl6NMTU3pYjH35TyArT1YEt2qMuWgRQ8G5cPmJrgvBmF46CLG LLGQi5TLr8h1WhcRVV6wMe3gErn+IFRPzey2gWDv4JtKgMI6EUeon3Ad6gEtajzhreOv dIw6W1REXIPmSl68PwT7AtTfgnog6yvtJp/wZRC5jqVK/ElxCRQYDpZGt99H7vzeinGL CoF+2tbtw5W88kN1HwSl5ETjjJgTH+Rnafu+uVF4b0DBZ0JAcOOMpRpY5hi86skysXSx XSQQ== X-Gm-Message-State: AOAM533XZY4eN6hBb34W2xnYlFxPBJEq0hbRiNxFywNhvfHsjGxp/Gfv WeWRpubB+UScxpIbXuDKRR8zMZhwltIkhg== X-Received: by 2002:a63:7010:: with SMTP id l16mr31672647pgc.32.1634699834016; Tue, 19 Oct 2021 20:17:14 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id c8sm505364pjr.38.2021.10.19.20.17.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 20:17:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 04/15] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Date: Tue, 19 Oct 2021 20:16:58 -0700 Message-Id: <20211020031709.359469-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020031709.359469-1-richard.henderson@linaro.org> References: <20211020031709.359469-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Shortly, the set of supported XL will not be just 32 and 64, and representing that properly using the enumeration will be imperative. Two places, booting and gdb, intentionally use misa_mxl_max to emphasize the use of the reset value of misa.mxl, and not the current cpu state. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 9 ++++++++- hw/riscv/boot.c | 2 +- semihosting/arm-compat-semi.c | 2 +- target/riscv/cpu.c | 24 ++++++++++++++---------- target/riscv/cpu_helper.c | 12 ++++++------ target/riscv/csr.c | 24 ++++++++++++------------ target/riscv/gdbstub.c | 2 +- target/riscv/monitor.c | 4 ++-- 8 files changed, 45 insertions(+), 34 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e708fcc168..d0e82135a9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -396,7 +396,14 @@ FIELD(TB_FLAGS, VILL, 8, 1) FIELD(TB_FLAGS, HLSX, 9, 1) FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2) -bool riscv_cpu_is_32bit(CPURISCVState *env); +#ifdef TARGET_RISCV32 +#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) +#else +static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) +{ + return env->misa_mxl; +} +#endif /* * A simplification for VLMAX diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 993bf89064..d1ffc7b56c 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -35,7 +35,7 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) { - return riscv_cpu_is_32bit(&harts->harts[0].env); + return harts->harts[0].env.misa_mxl_max == MXL_RV32; } target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index 01badea99c..37963becae 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -775,7 +775,7 @@ static inline bool is_64bit_semihosting(CPUArchState *env) #if defined(TARGET_ARM) return is_a64(env); #elif defined(TARGET_RISCV) - return !riscv_cpu_is_32bit(env); + return riscv_cpu_mxl(env) != MXL_RV32; #else #error un-handled architecture #endif diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ca4c9cc9d1..bce8fe7ebb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -108,11 +108,6 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) } } -bool riscv_cpu_is_32bit(CPURISCVState *env) -{ - return env->misa_mxl == MXL_RV32; -} - static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) { env->misa_mxl_max = env->misa_mxl = mxl; @@ -249,7 +244,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", (target_ulong)(env->mstatus >> 32)); } @@ -372,10 +367,16 @@ static void riscv_cpu_reset(DeviceState *dev) static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) { RISCVCPU *cpu = RISCV_CPU(s); - if (riscv_cpu_is_32bit(&cpu->env)) { + + switch (riscv_cpu_mxl(&cpu->env)) { + case MXL_RV32: info->print_insn = print_insn_riscv32; - } else { + break; + case MXL_RV64: info->print_insn = print_insn_riscv64; + break; + default: + g_assert_not_reached(); } } @@ -631,10 +632,13 @@ static gchar *riscv_gdb_arch_name(CPUState *cs) RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; - if (riscv_cpu_is_32bit(env)) { + switch (riscv_cpu_mxl(env)) { + case MXL_RV32: return g_strdup("riscv:rv32"); - } else { + case MXL_RV64: return g_strdup("riscv:rv64"); + default: + g_assert_not_reached(); } } diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 14d1d3cb72..403f54171d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -152,7 +152,7 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { - uint64_t sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD; + uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD; uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | MSTATUS64_UXL | sd; @@ -447,7 +447,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, if (first_stage == true) { if (use_background) { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; vm = get_field(env->vsatp, SATP32_MODE); } else { @@ -455,7 +455,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, vm = get_field(env->vsatp, SATP64_MODE); } } else { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; vm = get_field(env->satp, SATP32_MODE); } else { @@ -465,7 +465,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, } widened = 0; } else { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; vm = get_field(env->hgatp, SATP32_MODE); } else { @@ -558,7 +558,7 @@ restart: } target_ulong pte; - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { pte = address_space_ldl(cs->as, pte_addr, attrs, &res); } else { pte = address_space_ldq(cs->as, pte_addr, attrs, &res); @@ -678,7 +678,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, int page_fault_exceptions, vm; uint64_t stap_mode; - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { stap_mode = SATP32_MODE; } else { stap_mode = SATP64_MODE; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d0c86a300d..9c0753bc8b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -95,7 +95,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; } - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { switch (csrno) { case CSR_CYCLEH: if (!get_field(env->hcounteren, COUNTEREN_CY) && @@ -130,7 +130,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) static RISCVException ctr32(CPURISCVState *env, int csrno) { - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { return RISCV_EXCP_ILLEGAL_INST; } @@ -145,7 +145,7 @@ static RISCVException any(CPURISCVState *env, int csrno) static RISCVException any32(CPURISCVState *env, int csrno) { - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { return RISCV_EXCP_ILLEGAL_INST; } @@ -180,7 +180,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno) static RISCVException hmode32(CPURISCVState *env, int csrno) { - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { if (riscv_cpu_virt_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; } else { @@ -486,7 +486,7 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, static int validate_vm(CPURISCVState *env, target_ulong vm) { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { return valid_vm_1_10_32[vm & 0xf]; } else { return valid_vm_1_10_64[vm & 0xf]; @@ -510,7 +510,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | MSTATUS_TW; - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { /* * RV32: MPV and GVA are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. @@ -522,7 +522,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | ((mstatus & MSTATUS_XS) == MSTATUS_XS); - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { mstatus = set_field(mstatus, MSTATUS32_SD, dirty); } else { mstatus = set_field(mstatus, MSTATUS64_SD, dirty); @@ -795,7 +795,7 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno, { target_ulong mask = (sstatus_v1_10_mask); - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { mask |= SSTATUS32_SD; } else { mask |= SSTATUS64_SD; @@ -1006,7 +1006,7 @@ static RISCVException write_satp(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { vm = validate_vm(env, get_field(val, SATP32_MODE)); mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); asid = (val ^ env->satp) & SATP32_ASID; @@ -1034,7 +1034,7 @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) { *val = env->hstatus; - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { /* We only support 64-bit VSXL */ *val = set_field(*val, HSTATUS_VSXL, 2); } @@ -1047,7 +1047,7 @@ static RISCVException write_hstatus(CPURISCVState *env, int csrno, target_ulong val) { env->hstatus = val; - if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) { + if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); } if (get_field(val, HSTATUS_VSBE) != 0) { @@ -1215,7 +1215,7 @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno, return RISCV_EXCP_ILLEGAL_INST; } - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); } else { env->htimedelta = val; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 5257df0217..23429179e2 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -161,7 +161,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) CPURISCVState *env = &cpu->env; GString *s = g_string_new(NULL); riscv_csr_predicate_fn predicate; - int bitsize = riscv_cpu_is_32bit(env) ? 32 : 64; + int bitsize = 16 << env->misa_mxl_max; int i; g_string_printf(s, ""); diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index f7e6ea72b3..7efb4b62c1 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -150,7 +150,7 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env) target_ulong last_size; int last_attr; - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; vm = get_field(env->satp, SATP32_MODE); } else { @@ -220,7 +220,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) return; } - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { if (!(env->satp & SATP32_MODE)) { monitor_printf(mon, "No translation or protection\n"); return; From patchwork Wed Oct 20 03:16:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515978 Delivered-To: patch@linaro.org Received: by 2002:adf:a11e:0:0:0:0:0 with SMTP id o30csp1317621wro; Tue, 19 Oct 2021 20:18:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzXB3d2aOt2mFmA/x5MOCHMZ5WzVfCKmwJLLbwONti38lBf2URDTfmiIEWq507zj53lzgfz X-Received: by 2002:a67:e28a:: with SMTP id g10mr40848363vsf.5.1634699928132; Tue, 19 Oct 2021 20:18:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634699928; cv=none; d=google.com; s=arc-20160816; b=jvahKflzlsoFZkxPbcB5UkTmvpp7oW6cupyu6rukvWZp6/0JRNuv8saK34RRo6kY/T Vx+W5rXq4VqTVZR1UGhkJIyTyElNnzox7Smuk2VzqfELO55F7dvh/Wdhbh+E9YbbZuFZ e4jkAPfocQA2vHy2T0+uxYJY3rDWGz/euHkODfSW+8r4YnShbAZvP1FRCV6UJ46i1nom gBavWV7xkQJ+LQvuaDy2IyT61GnuyCHd+cZXPJYLqDUZoYVP2VAUqIITDvwo60/FCuLS /konqlE734++HkpU3LI+d+9jPPobX5ivTntZ62T/JzqM2y3jv320u/25s2GKaQuDl2Jn I7+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qtBU67E2VBBOP7+0Zsl17oOFCJ6wQGkRCeveFWurByw=; b=sqTlZT7f1LTAdOmMiAZzeDKKF8IwlVO6YugTW5BcEdNqb1v3vc/+A+Iz/1D8CsJ5o0 G+9Ys/6/YUtp+9TcE1lWWrG0VJRti86Op2gfasZBH/jgLH3jv/TNTImbi1LFD7kOGqfW /rcfSayk2Odt3FNAST9Vuk7PIjRCKXQwssJWHVo8ep/gMHBFEz2xeAdtrhwSI7ziA1IM gLUe52uI0Mq6nN1YgQP+eWPkAR9IE1Xa8eyaF6nkdJDS54iWvoxNK+JZKI+M4LmzkSoN SJwGF0MiYK47gdgXhFN9nrAyrsqjujMxsmtYiCB2OqsXdI33IRdajUv2ckncnUiKhCwn e9Sw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=t0+RLheN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Extract the effective XLEN from MISA and MSTATUS and store for use during translation. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 8 ++++++++ target/riscv/cpu_helper.c | 33 +++++++++++++++++++++++++++++++++ target/riscv/csr.c | 3 +++ target/riscv/translate.c | 2 +- 5 files changed, 47 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d0e82135a9..c24bc9a039 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -395,6 +395,8 @@ FIELD(TB_FLAGS, VILL, 8, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 9, 1) FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2) +/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ +FIELD(TB_FLAGS, XL, 12, 2) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bce8fe7ebb..babe271e53 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -355,6 +355,14 @@ static void riscv_cpu_reset(DeviceState *dev) env->misa_mxl = env->misa_mxl_max; env->priv = PRV_M; env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); + if (env->misa_mxl > MXL_RV32) { + /* + * The reset status of SXL/UXL is undefined, but mstatus is WARL + * and we must ensure that the value after init is valid for read. + */ + env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); + env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); + } env->mcause = 0; env->pc = env->resetvec; env->two_stage_lookup = false; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 403f54171d..429afd1f48 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -35,6 +35,37 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } +static RISCVMXL cpu_get_xl(CPURISCVState *env) +{ +#if defined(TARGET_RISCV32) + return MXL_RV32; +#elif defined(CONFIG_USER_ONLY) + return MXL_RV64; +#else + RISCVMXL xl = riscv_cpu_mxl(env); + + /* + * When emulating a 32-bit-only cpu, use RV32. + * When emulating a 64-bit cpu, and MXL has been reduced to RV32, + * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened + * back to RV64 for lower privs. + */ + if (xl != MXL_RV32) { + switch (env->priv) { + case PRV_M: + break; + case PRV_U: + xl = get_field(env->mstatus, MSTATUS64_UXL); + break; + default: /* PRV_S | PRV_H */ + xl = get_field(env->mstatus, MSTATUS64_SXL); + break; + } + } + return xl; +#endif +} + void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -78,6 +109,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, } #endif + flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env)); + *pflags = flags; } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9c0753bc8b..c4a479ddd2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -526,6 +526,9 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, mstatus = set_field(mstatus, MSTATUS32_SD, dirty); } else { mstatus = set_field(mstatus, MSTATUS64_SD, dirty); + /* SXL and UXL fields are for now read only */ + mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64); + mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64); } env->mstatus = mstatus; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 422f8ab8d0..7e7bb67d15 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -539,7 +539,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #else ctx->virt_enabled = false; #endif - ctx->xl = env->misa_mxl; ctx->misa_ext = env->misa_ext; ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei; @@ -551,6 +550,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); + ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->cs = cs; ctx->w = false; ctx->ntemp = 0; From patchwork Wed Oct 20 03:17:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515979 Delivered-To: patch@linaro.org Received: by 2002:adf:a11e:0:0:0:0:0 with SMTP id o30csp1317804wro; Tue, 19 Oct 2021 20:19:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwg30TH8g/R9YIh5Crz2q0oG2SH5g7BHav3vSJWVqkSjw4SsX2l3E1nGdQLazFoMDiUKDTj X-Received: by 2002:a9d:4a8d:: with SMTP id i13mr8740790otf.180.1634699946283; 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Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index f730bd68d1..61fd82d41a 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -743,7 +743,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a) static bool amo_check64(DisasContext *s, arg_rwdvm* a) { - return !is_32bit(s) && amo_check(s, a); + REQUIRE_64BIT(s); + return amo_check(s, a); } GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check) From patchwork Wed Oct 20 03:17:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515989 Delivered-To: patch@linaro.org Received: by 2002:adf:a11e:0:0:0:0:0 with SMTP id o30csp1324117wro; Tue, 19 Oct 2021 20:29:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyvVocmXd6UkUFUYh9DHZs/IYIV6/y8CDU8kTkcR2si6Q6BaAcJqenLwDjNo421OnAPRT++ X-Received: by 2002:a54:4f8f:: with SMTP id g15mr7112345oiy.169.1634700570333; Tue, 19 Oct 2021 20:29:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634700570; cv=none; d=google.com; s=arc-20160816; b=tUGtKbwhnagIRwYvYlXkMZ8dl0slIQLzXPxA3s7tlzTX41Al2q4PLJphDPWVVUhFux ImJibeJkP0GU7vd+fBKXdU864aRBYtEtkr1gmIo/YYiB97mT3dGzIbJv4GWtOaHAMtTc A+WHKlg72rYnUXL6nDimLy+JyouDTCISM0u4CMMDsRdbxhmiQgF4WZnB0fSepa3ZQqHc 9EKw+HZswVbGTN/wLfb4d+kRfVJimPvSCEoOWhsR/JrBH4/0sTej6RxvPNW2VyXVLf75 oevcd0/PSEecn0LT4UZTexj87TicWl5D32bjg8rV/CH9D4klDuErXLKEeo/6aE0pmfUY x2GA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UakmtpX/ULO2Fxh/+VRPEmYBUzLO6qfGKR5m4Cqlo1Y=; b=HWBpOGwDsaIPKyGgodi3jwZw7vSXmt9hkK2Kb6Anrdurxexkr7gvsKnIxzX2AE1aDD PxmFeXA8S7ACxAqMiG1Mz2qssOpBsffsWGPsy7q9vDzd5y2QiMFZ4YUnCqFiQRh36TFY smstaVfbQYb9AhqbLma1XA2TWqYC43jQL1vgtbZjLjmUdq4Xw01w1OqhuZfjyWkFciHH 3CHqVZc8ykzkBpH1RbF5imDGdV2qvbvNHiZHSFWm6kin+22JSx/S6Sn+9f0G5AVZOaxB EVWXf48xAY4s5w9sNq1V1yVjqxQHj3Xw1k3euIuXp4z6CaqU2ER93tmegSFJtqjdLZms t7kg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DmA2mxyA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s20si1693600oiw.134.2021.10.19.20.29.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 20:29:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DmA2mxyA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53002 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1md2ID-0001Nt-Gb for patch@linaro.org; Tue, 19 Oct 2021 23:29:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47122) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1md26U-0006tD-UP for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:22 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:42562) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1md26Q-00012B-Fo for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:22 -0400 Received: by mail-pl1-x62d.google.com with SMTP id w17so3283396plg.9 for ; Tue, 19 Oct 2021 20:17:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UakmtpX/ULO2Fxh/+VRPEmYBUzLO6qfGKR5m4Cqlo1Y=; b=DmA2mxyA655Ycr+H014vUT4DEXePkf0xbHXfa/VlZTFOfcmzHAUZKwgdy1116FBQOX KF+Fd8SlEElIb88rAyI0l2AHv9hapnfZUNx9Gn2zcXHMY5VLgWrDDD1ODfpR+Z7JLgv/ orVav7pQoaDcZmc2pgpmxzy3WdaVA94NBJ5ykGC6bzTZWu47rlvQJkrQ2belmHApM8IZ JhktCnzl1cSfQCte0RO+FvgXuDXHhNusd/9/VBXnd1k9EnArjJZgTq7kU2AKMi54ZJXN EZmZmDucNf3NUtbLfSBrpnTa4f5SwuqLDQe/HKbpMjq8QfjEVjVnDILyiMK7EIKpIRs3 sXUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UakmtpX/ULO2Fxh/+VRPEmYBUzLO6qfGKR5m4Cqlo1Y=; b=N5jQ5/ACXBGjpeULVGj9wsmN/7QQrL3eg5VDh8hpzmQ4nUU3FPpxHm0vAYa6IOEiS0 k3lnIcyn1Wge7P6922Dri72zOUXNA/ESHQbzCYp9LZti+HHQnSB/4kFsqKhfct9XgcAo Z0OTpbym3y6Hc2MfXB5SnTAekVtcPSrJC7eUS380kuLbuMHg4iCXLQtnxm56peGn3baW zEFOyLBnIzpjH2HU54gFdaM9b6BWMwJdMkWcZFGcJeiI9+CehIej5J0t4OFGAP6SN0hP 7xgo9ybpVGBPfhlGBG+/sVLIIfWqUTdgxaZzAs3fS0Ks9mqrGs9UzxoMVRWWx2BDJ7bg YgcA== X-Gm-Message-State: AOAM530dCivBgpPRAixEdc0VNOeaZyCnXzrGvvRsm+FdSXxtTz/q5h2D Ewf04+YNOwMQXz5ogJuosCpZN6qWE4fV+g== X-Received: by 2002:a17:90b:1e49:: with SMTP id pi9mr4413311pjb.144.1634699836020; Tue, 19 Oct 2021 20:17:16 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id c8sm505364pjr.38.2021.10.19.20.17.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 20:17:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 07/15] target/riscv: Properly check SEW in amo_op Date: Tue, 19 Oct 2021 20:17:01 -0700 Message-Id: <20211020031709.359469-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020031709.359469-1-richard.henderson@linaro.org> References: <20211020031709.359469-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We're currently assuming SEW <= 3, and the "else" from the SEW == 3 must be less. Use a switch and explicitly bound both SEW and SEQ for all cases. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 26 +++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 61fd82d41a..a102c3687e 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -704,18 +704,20 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq) gen_helper_exit_atomic(cpu_env); s->base.is_jmp = DISAS_NORETURN; return true; - } else { - if (s->sew == 3) { - if (!is_32bit(s)) { - fn = fnsd[seq]; - } else { - /* Check done in amo_check(). */ - g_assert_not_reached(); - } - } else { - assert(seq < ARRAY_SIZE(fnsw)); - fn = fnsw[seq]; - } + } + + switch (s->sew) { + case 0 ... 2: + assert(seq < ARRAY_SIZE(fnsw)); + fn = fnsw[seq]; + break; + case 3: + /* XLEN check done in amo_check(). */ + assert(seq < ARRAY_SIZE(fnsd)); + fn = fnsd[seq]; + break; + default: + g_assert_not_reached(); } data = FIELD_DP32(data, VDATA, MLEN, s->mlen); From patchwork Wed Oct 20 03:17:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515983 Delivered-To: patch@linaro.org Received: by 2002:adf:a11e:0:0:0:0:0 with SMTP id o30csp1319994wro; Tue, 19 Oct 2021 20:22:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxHXaeDv4yKTEr4wsL4LOr8O530php6f/ld8XOrD8xPMfzcsdlsrEbgTzyD0/UU6ZNV4fu2 X-Received: by 2002:a05:6122:218e:: with SMTP id j14mr36900376vkd.0.1634700160682; Tue, 19 Oct 2021 20:22:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634700160; cv=none; d=google.com; s=arc-20160816; b=t2t0nuZus7YYuFXLxb1J/JqL6Ax1wpCdXnxGxxL+XdwWiwhMqVQBVmVih4oxXcRdwg 9+fJFBVUmsoMzn6KjXuR+cnVFqW+0N4VJ3JrW5i33wKTHfvj58BRqMPNF8l1q/bzhnLI tkS/Qv618eb+2SFf6NOm26k0UMCIsiXt2p8GEytgt7tjAwg+kCgn1/JU1Do1sLZtHXry n1lGKQ/F+ieRx0RpXsV4+LYUgmaHTFhaR+up51c2s3yC+Y2+oNrnkUOa3u8YrbCsjENT M9BzHrVDfrLXJNLc0+sxKCwNRGu5nHKFw01eOMdrUTex/U+ng1xysBzdwrFAumHQVNZC DBYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=eqYHtG7U6Thazj4+tYJjUHiaULEjGKehA71xuneoPd8=; b=QUtNFPB2mb4+uBOnl6Bbw7TgCtAzU3AVSqmR/YtMObKt4slNAK5DrLJd3D0S9HsnXx KFD+GWrmrZynse0IUd0tna7AmQLLOxgIgsEvBD7Eyon9mLhgJ3Tv7mAnOOnEsVdV09rm 9CAh7hEn/1hUdCBaIMV/hgVfUhBsmtQvzrFkG7zpXk3U2tiTPcqu5flU9rSEpr5qxUxx sevnPUt11rHdu+oIadwbX4mDFqvrXHtR/uJgx04ouKCkoeT1DZps8XlMVQZNiRI2uRJJ 6CzgCKu7BtqVawpnU8ZI1U6QPbVrObvFitWjUrApLXPi4tVt4yChHMLo05W9Pkc7SjbK EXUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XQwFxjjP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y19si919608uan.144.2021.10.19.20.22.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 20:22:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XQwFxjjP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34598 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1md2Bb-0005Yu-UR for patch@linaro.org; Tue, 19 Oct 2021 23:22:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47150) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1md26W-0006xr-7z for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:24 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:46918) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1md26R-00012w-7Y for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:23 -0400 Received: by mail-pl1-x631.google.com with SMTP id 21so15106218plo.13 for ; Tue, 19 Oct 2021 20:17:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eqYHtG7U6Thazj4+tYJjUHiaULEjGKehA71xuneoPd8=; b=XQwFxjjPPEYf8nQbLsmMSXt9YdIBCFiR/h040uAcy0bX2lHy+Bzn75A4qsjOZg2aPX HUo07YLRtLeWJGqp95wy1HMZtwvenSz5PoFtnHwaZHljJSecRQ6Kh2FRRkH0vACfc1ol sOpK56AIIr5T1efzOXbEj9xwt1aXpcKwAXfWcE+nmfvBYt5CPqajCO0qR64FxIRLc4ti 0Ei4sHtf40S8Ygo3hvJ+XU5KbOdWB0Zxkoet6oqu3ud6uXUmGbevu97zwAaKSQz+7a8k hPAZ5nsglOTeFpvCubkIb3sbKrpioz/8B715m+SE1M61+CZBiqsRZsnbmACuo8lZSvsL 36PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eqYHtG7U6Thazj4+tYJjUHiaULEjGKehA71xuneoPd8=; b=ZL9dNiLxvOAMRci2BX0M7r+ugU/aioT69oIc7L8y8xY22hIHfDkI8YcbGS1MN0ZIOE wV5TTjBgvN4tM4rokwmP2LRqRX8iI6F5BWwvdyrdnihisLgrFm9Av+QJNR0O7pbnXhFC h0oZvLHs0C1zGpGtHe6h9J4HWzKcQLDiGJs6griltPK+o+4kHy5dF1Uocn5ShV7nIAZ+ xzeBM+zupxs4jt3LETaqyYKMxx4NrjEJoHClB1oJGkVMslyAZ1I3+T+WP8hWpE3L1i/J O9pWQ5uVmlQvu75o3mYa3061vXS+ylNles02Qcn1DmN4Mbvy19PFeme+BTjVEylcDmVP X5Fw== X-Gm-Message-State: AOAM531acmBOHRZl7QrOMI1qC0IRJDwAfehTzWohv3AR/aZbaV9tjJ+X +N5WFFmnr5XG7WGKho5LitPWGzwbcbFmow== X-Received: by 2002:a17:90a:7893:: with SMTP id x19mr4338245pjk.197.1634699836661; Tue, 19 Oct 2021 20:17:16 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id c8sm505364pjr.38.2021.10.19.20.17.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 20:17:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 08/15] target/riscv: Replace is_32bit with get_xl/get_xlen Date: Tue, 19 Oct 2021 20:17:02 -0700 Message-Id: <20211020031709.359469-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020031709.359469-1-richard.henderson@linaro.org> References: <20211020031709.359469-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for RV128, replace a simple predicate with a more versatile test. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 7e7bb67d15..2624d65fc2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -91,16 +91,19 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) } #ifdef TARGET_RISCV32 -# define is_32bit(ctx) true +#define get_xl(ctx) MXL_RV32 #elif defined(CONFIG_USER_ONLY) -# define is_32bit(ctx) false +#define get_xl(ctx) MXL_RV64 #else -static inline bool is_32bit(DisasContext *ctx) -{ - return ctx->xl == MXL_RV32; -} +#define get_xl(ctx) ((ctx)->xl) #endif +/* The word size for this machine mode. */ +static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) +{ + return 16 << get_xl(ctx); +} + /* The word size for this operation. */ static inline int oper_len(DisasContext *ctx) { @@ -282,7 +285,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) static void mark_fs_dirty(DisasContext *ctx) { TCGv tmp; - target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD; + target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD; if (ctx->mstatus_fs != MSTATUS_FS) { /* Remember the state change for the rest of the TB. */ @@ -341,16 +344,16 @@ EX_SH(12) } \ } while (0) -#define REQUIRE_32BIT(ctx) do { \ - if (!is_32bit(ctx)) { \ - return false; \ - } \ +#define REQUIRE_32BIT(ctx) do { \ + if (get_xl(ctx) != MXL_RV32) { \ + return false; \ + } \ } while (0) -#define REQUIRE_64BIT(ctx) do { \ - if (is_32bit(ctx)) { \ - return false; \ - } \ +#define REQUIRE_64BIT(ctx) do { \ + if (get_xl(ctx) < MXL_RV64) { \ + return false; \ + } \ } while (0) static int ex_rvc_register(DisasContext *ctx, int reg) From patchwork Wed Oct 20 03:17:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515981 Delivered-To: patch@linaro.org Received: by 2002:adf:a11e:0:0:0:0:0 with SMTP id o30csp1319865wro; Tue, 19 Oct 2021 20:22:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwfA/rgr6sHJnllrpIigKVr2I9WiHCLJsVDHoD0XiUle5Hmg2GW6o5SsswVnsavf8/1o6op X-Received: by 2002:ab0:14a7:: with SMTP id d36mr4784488uae.96.1634700148700; Tue, 19 Oct 2021 20:22:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634700148; cv=none; d=google.com; s=arc-20160816; b=W5herdNYHBORId2V6S8RAjGIEEO7n+X0CY7yvuwOOyHbxMN0sfBRCdfCUelAhgZlCl OICIj9r4NcMv6MbEIPxj9Yj71/Z4e5aVCnD6HVr0daPWIiDOZ1Mu3BG2T7h1i5UzyvoW 76O9ZyhDYxra+25W49Y5QC1ts4UV11RT2XUoRsXYzzpRnlOb+7zcdXhHDaDjX4a99pYH AOgBKW32xE1ld8kLI4iBYfkP4uL49AuMnq1wCy6XKk+DDqO1sIatY1o9X9jTBnSz1dEe p6JtpGg2UzSTOAAd6vxHr1b7VDjJVKAg2+cdrElXXLrgE4iqZ0aJfwnuJ9CA6jQ3uxyM CpLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Qq8q01GyapUyzRO/Gp843MjA6M8dBmEzgEdu7NiKs7I=; b=oIO/64jnX5FZUKI3zeM0Gn/0BIgGAMVXvh5h68Q7RKLEBpXWkcZLW5StAfFri4DcJ6 HSYovrJ+QZLbVhz4ucNy8nCnT7fYkPTG2aQzZLF9QiOcWWOzVBH12rW14YQMuQ0NeOaE mwUl26OPvRv3yzb3yNT6RWkjkph5BGpOrsyw11x4vrjwkmB7LYkvk2I+rx3f4rfvzt5b Pl056jQzDHNZRRtqKvekP1CFpAbKd+xcbZ4e0FEG8/a3Y3h029sKzHfrrnFXkowOQMOf pEknLw+5ikdsj0409q5dclmjo90rE9hdvZsGWPO+haio6hiyD0PNKa86bR2C7LusKkEP oAGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="Lh/XdMO3"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This will be used for the "d" insns from RV128 as well. Rename oper_len to get_olen to better match get_xlen. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 71 ++++++++++++++++--------- target/riscv/insn_trans/trans_rvb.c.inc | 8 +-- target/riscv/insn_trans/trans_rvi.c.inc | 18 +++---- target/riscv/insn_trans/trans_rvm.c.inc | 10 ++-- 4 files changed, 63 insertions(+), 44 deletions(-) -- 2.25.1 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2624d65fc2..172eea3935 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -67,7 +67,7 @@ typedef struct DisasContext { to any system register, which includes CSR_FRM, so we do not have to reset this known value. */ int frm; - bool w; + RISCVMXL ol; bool virt_enabled; bool ext_ifencei; bool hlsx; @@ -104,12 +104,17 @@ static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) return 16 << get_xl(ctx); } -/* The word size for this operation. */ -static inline int oper_len(DisasContext *ctx) -{ - return ctx->w ? 32 : TARGET_LONG_BITS; -} +/* The operation length, as opposed to the xlen. */ +#ifdef TARGET_RISCV32 +#define get_ol(ctx) MXL_RV32 +#else +#define get_ol(ctx) ((ctx)->ol) +#endif +static inline int get_olen(DisasContext *ctx) +{ + return 16 << get_ol(ctx); +} /* * RISC-V requires NaN-boxing of narrower width floating point values. @@ -222,24 +227,34 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) return ctx->zero; } - switch (ctx->w ? ext : EXT_NONE) { - case EXT_NONE: - return cpu_gpr[reg_num]; - case EXT_SIGN: - t = temp_new(ctx); - tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); - return t; - case EXT_ZERO: - t = temp_new(ctx); - tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); - return t; + switch (get_ol(ctx)) { + case MXL_RV32: + switch (ext) { + case EXT_NONE: + break; + case EXT_SIGN: + t = temp_new(ctx); + tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); + return t; + case EXT_ZERO: + t = temp_new(ctx); + tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); + return t; + default: + g_assert_not_reached(); + } + break; + case MXL_RV64: + break; + default: + g_assert_not_reached(); } - g_assert_not_reached(); + return cpu_gpr[reg_num]; } static TCGv dest_gpr(DisasContext *ctx, int reg_num) { - if (reg_num == 0 || ctx->w) { + if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { return temp_new(ctx); } return cpu_gpr[reg_num]; @@ -248,10 +263,15 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num) static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) { if (reg_num != 0) { - if (ctx->w) { + switch (get_ol(ctx)) { + case MXL_RV32: tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); - } else { + break; + case MXL_RV64: tcg_gen_mov_tl(cpu_gpr[reg_num], t); + break; + default: + g_assert_not_reached(); } } } @@ -412,7 +432,7 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, target_long)) { TCGv dest, src1; - int max_len = oper_len(ctx); + int max_len = get_olen(ctx); if (a->shamt >= max_len) { return false; @@ -431,7 +451,7 @@ static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, TCGv)) { TCGv dest, src1, src2; - int max_len = oper_len(ctx); + int max_len = get_olen(ctx); if (a->shamt >= max_len) { return false; @@ -455,7 +475,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); TCGv ext2 = tcg_temp_new(); - tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1); + tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1); func(dest, src1, ext2); gen_set_gpr(ctx, a->rd, dest); @@ -555,7 +575,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->cs = cs; - ctx->w = false; ctx->ntemp = 0; memset(ctx->temp, 0, sizeof(ctx->temp)); @@ -579,9 +598,9 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) CPURISCVState *env = cpu->env_ptr; uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); + ctx->ol = ctx->xl; decode_opc(env, ctx, opcode16); ctx->base.pc_next = ctx->pc_succ_insn; - ctx->w = false; for (int i = ctx->ntemp - 1; i >= 0; --i) { tcg_temp_free(ctx->temp[i]); diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 3095624f32..9ef8ab94ad 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -344,7 +344,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl); } @@ -370,7 +370,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_NONE, gen_rorw); } @@ -378,7 +378,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw); } @@ -404,7 +404,7 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_NONE, gen_rolw); } diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 920ae0edb3..c0a46d823f 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -333,14 +333,14 @@ static bool trans_and(DisasContext *ctx, arg_and *a) static bool trans_addiw(DisasContext *ctx, arg_addiw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl); } static bool trans_slliw(DisasContext *ctx, arg_slliw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); } @@ -352,7 +352,7 @@ static void gen_srliw(TCGv dst, TCGv src, target_long shamt) static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw); } @@ -364,42 +364,42 @@ static void gen_sraiw(TCGv dst, TCGv src, target_long shamt) static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw); } static bool trans_addw(DisasContext *ctx, arg_addw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl); } static bool trans_subw(DisasContext *ctx, arg_subw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl); } static bool trans_sllw(DisasContext *ctx, arg_sllw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl); } static bool trans_srlw(DisasContext *ctx, arg_srlw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl); } static bool trans_sraw(DisasContext *ctx, arg_sraw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl); } diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc index b89a85ad3a..9a1fe3c799 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -214,7 +214,7 @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl); } @@ -222,7 +222,7 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_SIGN, gen_div); } @@ -230,7 +230,7 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_ZERO, gen_divu); } @@ -238,7 +238,7 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_SIGN, gen_rem); } @@ -246,6 +246,6 @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_ZERO, gen_remu); } From patchwork Wed Oct 20 03:17:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515985 Delivered-To: patch@linaro.org Received: by 2002:adf:a11e:0:0:0:0:0 with SMTP id o30csp1321487wro; Tue, 19 Oct 2021 20:25:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzFR2aAhPMUGNUkq8YYmp12mqYOQiDiDEv5A6c+co0ZoK5n/rHK0gOKhHIT3bx3SBUIr64/ X-Received: by 2002:a9d:6a06:: with SMTP id g6mr4502772otn.347.1634700306706; Tue, 19 Oct 2021 20:25:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634700306; cv=none; d=google.com; s=arc-20160816; b=VZQDM4MxB4TK4/Jxh0+tfg3ywiMqyYb+KnybwFATJ1IV1+G8oL7F1+fxE1e6wsLnAW 0NRDgpFT4r3clmsKabcbq0h7X8aQyhyliYxbH9g3DkKiosQnqN8Gh20GTVz8DPVTGfXT IX/T+v1nyFqCa5Rq3b/RV2SR8svGkxcaSy87zv6EPA70/8voosQ84DNUilxi/scf97Dw tnML5N46OyUKDXNvFevEGmv8cXCjGlzoCVvz7iP4gjaw/Kx/lxrH8I+nyPzvhR0T0EEM Elkox5jIXbvKSmDMZkzG9LP9E5JFgGgWUQHp5chkXwOkg8bMDZGzSdMZY0PFFhPj1jM+ QW8Q== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id b10si1074190ooi.11.2021.10.19.20.25.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 20:25:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jFg9QEvN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42968 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1md2Dx-0002oZ-RI for patch@linaro.org; Tue, 19 Oct 2021 23:25:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47192) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1md26Y-00075R-Js for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:26 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:56106) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1md26R-00014M-DO for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:26 -0400 Received: by mail-pj1-x102a.google.com with SMTP id om14so1424163pjb.5 for ; Tue, 19 Oct 2021 20:17:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rsNq0xlR7HN/ajZ2yGfZB2/qqFUmURGu/dng6McMdV4=; b=jFg9QEvNaYETsAajZqmvF2EoIF2huhUEkQDM9ohHhoXgQ0bFzWfS248lyM264++3YI 4EGjfbMtL1V8iQqTUgSrTQ9kUtuKZeWCYknMUh900qzb3W9c71SVCpXtcpK+G9oNYDcy hfut32TJBpZOs8/JbfdgBw/+ejTrMjsawaxBAg4VRdWhcKwVFjGFlFhpAEk43aCiN/mq iGtzuEd3CIdHvhjrBhxLFrIuKxHcSAVPMvjKKQtyaIZAopS2wNvSxQ2obYATOC7e7n7e lRk/RPTtV1Z+0BrE7Z3Hl3k8zPqb6K571Eqf9pgKWaqSKvTCGeS1ySDnWl/AggbJkNoX Zujg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rsNq0xlR7HN/ajZ2yGfZB2/qqFUmURGu/dng6McMdV4=; b=ngAxnzSEUTcg9rLuKeg/Yr5oYgsru0+CsrzXirY2ca7OLPfTcTyHllhKIS6+eUSq9N PkcegD283P3iIW2AsubjzW1AUgyhTNSKbdJZE6muPpbmd2Ugs6zfh82R+xhdpmOZ4MCh gduuqauzTQJcF6kjg7KTxXt1FAU78HoeAWRIKLnZSfYrgAngeUcN5+f9H3Mo3f9NcrQs 5YqvDTXOMVF4VVi6h09eb2Djkhb1gop1KsS/sckElVjELwwdF358ylaSPHYsqFBOM9SV em5nMaphqw2aHAV/T1IHs/EcsglWEXZEtMEVshdyV/SDDD3L+bS7ZUIXP/PhUdW57UFT 9nxA== X-Gm-Message-State: AOAM531ZdvhMmeiFsVpvBseWiAI+SEGH5OZxc0Wp3m0xgg1uyVMpKwRl qeznxgRFzG4LPJAyKuTJLq3r7Q45iurFOw== X-Received: by 2002:a17:90b:33c8:: with SMTP id lk8mr4425603pjb.106.1634699837930; Tue, 19 Oct 2021 20:17:17 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id c8sm505364pjr.38.2021.10.19.20.17.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 20:17:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 10/15] target/riscv: Use gen_arith_per_ol for RVM Date: Tue, 19 Oct 2021 20:17:04 -0700 Message-Id: <20211020031709.359469-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020031709.359469-1-richard.henderson@linaro.org> References: <20211020031709.359469-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The multiply high-part instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 16 +++++++++++++++ target/riscv/insn_trans/trans_rvm.c.inc | 26 ++++++++++++++++++++++--- 2 files changed, 39 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 172eea3935..8f5f39d143 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -428,6 +428,22 @@ static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, return true; } +static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, + void (*f_tl)(TCGv, TCGv, TCGv), + void (*f_32)(TCGv, TCGv, TCGv)) +{ + int olen = get_olen(ctx); + + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_arith(ctx, a, ext, f_tl); +} + static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, target_long)) { diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc index 9a1fe3c799..2af0e5c139 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -33,10 +33,16 @@ static void gen_mulh(TCGv ret, TCGv s1, TCGv s2) tcg_temp_free(discard); } +static void gen_mulh_w(TCGv ret, TCGv s1, TCGv s2) +{ + tcg_gen_mul_tl(ret, s1, s2); + tcg_gen_sari_tl(ret, ret, 32); +} + static bool trans_mulh(DisasContext *ctx, arg_mulh *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_NONE, gen_mulh); + return gen_arith_per_ol(ctx, a, EXT_SIGN, gen_mulh, gen_mulh_w); } static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) @@ -54,10 +60,23 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(rh); } +static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + + tcg_gen_ext32s_tl(t1, arg1); + tcg_gen_ext32u_tl(t2, arg2); + tcg_gen_mul_tl(ret, t1, t2); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_gen_sari_tl(ret, ret, 32); +} + static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_NONE, gen_mulhsu); + return gen_arith_per_ol(ctx, a, EXT_NONE, gen_mulhsu, gen_mulhsu_w); } static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2) @@ -71,7 +90,8 @@ static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2) static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_NONE, gen_mulhu); + /* gen_mulh_w works for either sign as input. */ + return gen_arith_per_ol(ctx, a, EXT_ZERO, gen_mulhu, gen_mulh_w); } static void gen_div(TCGv ret, TCGv source1, TCGv source2) From patchwork Wed Oct 20 03:17:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515982 Delivered-To: patch@linaro.org Received: by 2002:adf:a11e:0:0:0:0:0 with SMTP id o30csp1319905wro; Tue, 19 Oct 2021 20:22:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwI+TQXPRk13gKd/iTU889yti2o5r6UTFFgHFDJVPYN+W3DxZL+sPrYCNUcDMajZWIiAFbf X-Received: by 2002:a05:6130:426:: with SMTP id ba38mr4944251uab.108.1634700152882; Tue, 19 Oct 2021 20:22:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634700152; cv=none; d=google.com; s=arc-20160816; b=TbVrpHzQTowQcjx3/J7QAdtMXfbdw922B0gqM5yR4nahdroRBzIWk1dIQ1nTm682lP gINqSxEZ3LZRCzz5cEpMqVukMxY54uxQO2OmZ3tD77p6PmhTBdgx9VPPF+fJDq/Mqrmv DmLVhxAAkYgaz6Enw4zRq5N6noN1clcpfCgF5WuiB7nXCJoaYCoxoLa+LmA0wrKn9NPp 7JLFf8/W4rtb2cjL22RdnJYD0Vi92v85Asp6urCBwDbzpVXfesJRC7/0Cm0hPp7inU7a sv/Y4yygvfvWNimuifGMv2IX+NQtrqKfia7xDgRGfwgudQ02clfTpiTrRUzVQpFHo+yL Sn7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8qboDzk3VhEZDOSy2c6q1MVUzAtWHxO1Mi1Ig7NaMDQ=; b=yOLb9SNMo1e4Sbq+A/KNVTrCsB8WEglU2z6nsSfTf+evHQhLW1UEXhtdrrowkyggek EnQDLfgnqn5tPubtBwUpIuXkMXmVhzRYIR9F8gJtBM/bVTk9ofJfNfCQoYcid7ekG2OH iEGrHs+/jZJeK1kAiwbUJSyRN1W2VtDIkDKgBY8beqpAezbH8P1K9uBznGZDuPzvyJsU nhHTvSiPAElYoJnbF+SPrj+FJI8jcBF+4kEz0V6dBbYYSNV8OWiULaH9f2e2Cb5ytoWx CJERlv2mBamVU3SRxnQ2l8AlwBgLnnOxrgPFwocjb0nGmsBhUC1byVwNZbu+YnXu9/2n v03g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DfyNnSHT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f21si1076396vsl.434.2021.10.19.20.22.32 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 20:22:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DfyNnSHT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33844 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1md2BU-0004za-1w for patch@linaro.org; Tue, 19 Oct 2021 23:22:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47226) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1md26a-0007Bo-4g for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:28 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:36705) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1md26S-00014y-7Y for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:27 -0400 Received: by mail-pj1-x102e.google.com with SMTP id qe4-20020a17090b4f8400b0019f663cfcd1so1431230pjb.1 for ; Tue, 19 Oct 2021 20:17:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8qboDzk3VhEZDOSy2c6q1MVUzAtWHxO1Mi1Ig7NaMDQ=; b=DfyNnSHTT7Cm/d/tKa8mjxxWBbLZrnikgG5+brvdze9JnnhrYy/4+23eGCvrOJLcLW QetNd797P6zGWYsHbRt/U2ZQdsofRZklO7QO0GgbnuTwTdLuBVJZNGqZU4E2oDY6raWd Ey/UdnqCAgavdmcve9oa4BF0i63rBln7R5TWpBNpNDTKp7AZplVZjY9maUdvMSDIRdtY WyplSRtrCJDuJB8G8gcFvbOQ+QCwPxVthz3u+IYGwzSD8JdWBcxUetzkfmBoB0Q+fG6M bKSFxDZe9HCNsjL0vCpDneVboxUcW194Op/n8EUQ66Sbq7HT+8AQQU09ag6u38O8fiAZ MwHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8qboDzk3VhEZDOSy2c6q1MVUzAtWHxO1Mi1Ig7NaMDQ=; b=Yl+Mp2QWNmGZG8w226pvkHZ3Nk1+pi4SoudxFeEebrOFjZYgEe3bqg9sqCycV+zSJJ QQja1fufzaZIbcmaDM7jmpHkQh6oBpy3Qxk5Q0jDbk8yubrSTYZrPhw8RpTeCbC4e8dm hKm4Amojc+qroRKjcOXwG8pSXUUrzQmjjfmnZduEb9XpkN+h8cFnKh9R8U05cqoS1SZQ /IKor4QvsT1xIphhdFdXVvH3sDpaR7MtI6UpZ3RZUmjnamKbiEGvwB4cRVnruQdVju7n I5ZjjfiyKgBWWrUvUOFdJej2QgyD6FWhjco1iM0VYKNipAEYASp+Q5LVR+im6HQXyD6R qnHg== X-Gm-Message-State: AOAM533uf6eHnnxXgb+ulqsAeJNHo+uDdLGOPxo8y7ra65Gdi3MsHALb SlW/mOx7xCo8v8xprtKvYXR8sZnzuafceA== X-Received: by 2002:a17:90a:ba88:: with SMTP id t8mr4351381pjr.15.1634699838722; Tue, 19 Oct 2021 20:17:18 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id c8sm505364pjr.38.2021.10.19.20.17.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 20:17:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 11/15] target/riscv: Adjust trans_rev8_32 for riscv64 Date: Tue, 19 Oct 2021 20:17:05 -0700 Message-Id: <20211020031709.359469-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020031709.359469-1-richard.henderson@linaro.org> References: <20211020031709.359469-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When target_long is 64-bit, we still want a 32-bit bswap for rev8. Since this opcode is specific to RV32, we need not conditionalize. Acked-by: Alistair Francis Reviewed-by: LIU Zhiwei Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 9ef8ab94ad..d6f9e9fc83 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a) return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl); } +static void gen_rev8_32(TCGv ret, TCGv src1) +{ + tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS); +} + static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a) { REQUIRE_32BIT(ctx); REQUIRE_ZBB(ctx); - return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl); + return gen_unary(ctx, a, EXT_NONE, gen_rev8_32); } static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a) From patchwork Wed Oct 20 03:17:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515990 Delivered-To: patch@linaro.org Received: by 2002:adf:a11e:0:0:0:0:0 with SMTP id o30csp1325434wro; Tue, 19 Oct 2021 20:31:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyMx4/kp5CNQJP3WOY47hE20wnohDgWTBXAp5AujB1DQGKoKVlkMXq5RELgMmf/Gfr6/mgQ X-Received: by 2002:a05:6808:301f:: with SMTP id ay31mr7368232oib.98.1634700706866; Tue, 19 Oct 2021 20:31:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634700706; cv=none; d=google.com; s=arc-20160816; b=wz0IIKiR2DngsWwdm45+hRHvUl/0asSmQ8lkufgFgMe+g5+Jq7wmpYZon4xRq9n1lQ fC5S/VRuRD6JozjK+1crzjAdixCn1sVP6vEYoaIykeMr88bELprXCfaZ5WWQx/flZK98 gz7BeQast5AzldlDTBZP9NG8yuEZcYS+zb1EyRwXh3icNQZdXQcJL4FewCOQu5wIk4Jo lKmDI61PT0dB1kmaLBP+hRGAnWnYNu0fgV7UvMGJSXuc/EYSr3bMTXBQ9fIHgDWk2kbY ZMnmRyUgCwYl8GCaXWF8lq9GqSU5FuMidB9u6Z49kD16g1MKVze9sh7r6jTl5QmqkpqY yC+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QFWFub+5wE7W42UBz/jcA4FNUYPA4Vi+1cQLKv1Yk3Y=; b=x98YD4k5Zo9oJsL1tp3gjGw1wTrqgq6BpD0grhbcj7K+d1v2l7oi7SgoMkdyH2DnPO W9YDv+d5QqYqS/XJPulVsnvqLIUD++M1oVImIxJ93ZsDaaFah0xebV1kmew8Vpv+PmfH HXdk74793yBbvTt4Kz7/AQ5Npi/BuS77Ix5gDuibvHdajv6XPEYuBw0eCV0Hpk2vgekL uIX0D+E45m1YN0ircLebuF5dTFYhEmJNj+dL/Fl76LDWoxc2kUi8B/IE5SY32D2qZP+F 18f+M0C2ETO534aJtZ7ImyMZlzZE8dMZmBoqbcKThuox4VxuABDcYylvnrFcjGTVjrGP IFxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RtfOd1nx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 16 ++++++++++++ target/riscv/insn_trans/trans_rvb.c.inc | 33 ++++++++++++------------- 2 files changed, 32 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8f5f39d143..7286791c0f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -511,6 +511,22 @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, return true; } +static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, + void (*f_tl)(TCGv, TCGv), + void (*f_32)(TCGv, TCGv)) +{ + int olen = get_olen(ctx); + + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_unary(ctx, a, ext, f_tl); +} + static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) { DisasContext *ctx = container_of(dcbase, DisasContext, base); diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index d6f9e9fc83..4eb41756fa 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -47,10 +47,18 @@ static void gen_clz(TCGv ret, TCGv arg1) tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS); } +static void gen_clzw(TCGv ret, TCGv arg1) +{ + TCGv t = tcg_temp_new(); + tcg_gen_shli_tl(t, arg1, 32); + tcg_gen_clzi_tl(ret, t, 32); + tcg_temp_free(t); +} + static bool trans_clz(DisasContext *ctx, arg_clz *a) { REQUIRE_ZBB(ctx); - return gen_unary(ctx, a, EXT_ZERO, gen_clz); + return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw); } static void gen_ctz(TCGv ret, TCGv arg1) @@ -58,10 +66,15 @@ static void gen_ctz(TCGv ret, TCGv arg1) tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS); } +static void gen_ctzw(TCGv ret, TCGv arg1) +{ + tcg_gen_ctzi_tl(ret, arg1, 32); +} + static bool trans_ctz(DisasContext *ctx, arg_ctz *a) { REQUIRE_ZBB(ctx); - return gen_unary(ctx, a, EXT_ZERO, gen_ctz); + return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw); } static bool trans_cpop(DisasContext *ctx, arg_cpop *a) @@ -317,14 +330,6 @@ static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a) return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl); } -static void gen_clzw(TCGv ret, TCGv arg1) -{ - TCGv t = tcg_temp_new(); - tcg_gen_shli_tl(t, arg1, 32); - tcg_gen_clzi_tl(ret, t, 32); - tcg_temp_free(t); -} - static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); @@ -332,17 +337,11 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a) return gen_unary(ctx, a, EXT_NONE, gen_clzw); } -static void gen_ctzw(TCGv ret, TCGv arg1) -{ - tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32)); - tcg_gen_ctzi_tl(ret, ret, 64); -} - static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - return gen_unary(ctx, a, EXT_NONE, gen_ctzw); + return gen_unary(ctx, a, EXT_ZERO, gen_ctzw); } static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) From patchwork Wed Oct 20 03:17:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515991 Delivered-To: patch@linaro.org Received: by 2002:adf:a11e:0:0:0:0:0 with SMTP id o30csp1326639wro; Tue, 19 Oct 2021 20:33:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJycB/7EVS6szOP6V4MtXdE1Zc8DqO/frJIojVY1VuuamqW4mldE6te6XqCcaQTfQWvTHP1f X-Received: by 2002:a25:824e:: with SMTP id d14mr46217279ybn.155.1634700835950; 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[209.51.188.17]) by mx.google.com with ESMTPS id n189si1182417ybn.459.2021.10.19.20.33.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 20:33:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PRAmbN1p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57634 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1md2MV-0004i8-66 for patch@linaro.org; Tue, 19 Oct 2021 23:33:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47270) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1md26b-0007IE-Ux for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:29 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:42799) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1md26T-00016c-C7 for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:29 -0400 Received: by mail-pj1-x102d.google.com with SMTP id nn3-20020a17090b38c300b001a03bb6c4ebso1450391pjb.1 for ; Tue, 19 Oct 2021 20:17:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cKoZbWzSzxT9on5m75z+GOkbLcFYhH+2g9pus8gqses=; b=PRAmbN1p9kJCX9fyL3+NTQ+PtAdonTb2ZvGFmNJ/XlRrTr6BVpu5PDqZ07t8esnWVA Q7NSDThxlSuleLd75AS5HxK24LLQY4eTuikAjx0hxRmEkatD4eAau9Jz9ukbh949IuuH faoEjiOdTbZYUln009YPrOBAAvTU3ApVhCkvHanDw0L6jn0qihACwYlENhxz4A9eS0hE dVeeXnbzveJiFTzdd64PnxxCOzCbRYv4bwwwcWzq9S4x+1nmCb8tDMj1irJaW9S1aEUO S33f4l+o+m0uoiAHN7VfVSSshIdoHFpmjsRudv+GQ4i5UqQGepSHicMvQGVVE/V88jTs yMnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cKoZbWzSzxT9on5m75z+GOkbLcFYhH+2g9pus8gqses=; b=IpAMD5toCq0yQyOVA1wo4Tcj2IgqImYsFE/QOrYL8HIGNjKnYnrWXjQU6HzKtRqpLT W+CSDALZWhxWRJZx4CCh7OSlpnDUPpdUb9pvVskYKk2QmbVKhgV21MhXxeZaaHgBJ6SW iqOANYz1bE2S9m0taRJZgF8a6Hh9lt/V6OgBwv8SC9KlWN5yQ+LBs/bP05n+76+f7FXS k7EhsV7Kh74ndP1R/UvRexWtUCsNNsxCnBDvKJruU71X/4sKxl09xCdlGmwCxGqIwqVG YurwyVgA4boHLvVKw84U6q3UwbfKjHKcrgh5kQgyuRaj/wzL1TiCNXshnDhoAAAVYM7L zrFQ== X-Gm-Message-State: AOAM530912/J4plnKPMyLYhuKWXKz9NsiFK3TG0vAPivQAZbBHID6dPN g7t9cTH5GnxgwoqQQEjekU6BUC85NmPoDA== X-Received: by 2002:a17:90a:2a0d:: with SMTP id i13mr4238421pjd.166.1634699839936; Tue, 19 Oct 2021 20:17:19 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id c8sm505364pjr.38.2021.10.19.20.17.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 20:17:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 13/15] target/riscv: Use gen_shift*_per_ol for RVB, RVI Date: Tue, 19 Oct 2021 20:17:07 -0700 Message-Id: <20211020031709.359469-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020031709.359469-1-richard.henderson@linaro.org> References: <20211020031709.359469-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Most shift instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 31 +++++++++ target/riscv/insn_trans/trans_rvb.c.inc | 92 ++++++++++++++----------- target/riscv/insn_trans/trans_rvi.c.inc | 26 +++---- 3 files changed, 97 insertions(+), 52 deletions(-) -- 2.25.1 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 7286791c0f..0b3da060fd 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -463,6 +463,22 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, return true; } +static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, + DisasExtend ext, + void (*f_tl)(TCGv, TCGv, target_long), + void (*f_32)(TCGv, TCGv, target_long)) +{ + int olen = get_olen(ctx); + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_shift_imm_fn(ctx, a, ext, f_tl); +} + static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, TCGv)) { @@ -499,6 +515,21 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, return true; } +static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, + void (*f_tl)(TCGv, TCGv, TCGv), + void (*f_32)(TCGv, TCGv, TCGv)) +{ + int olen = get_olen(ctx); + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_shift(ctx, a, ext, f_tl); +} + static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, void (*func)(TCGv, TCGv)) { diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 4eb41756fa..c8d31907c5 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -227,22 +227,70 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a) return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); } +static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + + /* truncate to 32-bits */ + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_trunc_tl_i32(t2, arg2); + + tcg_gen_rotr_i32(t1, t1, t2); + + /* sign-extend 64-bits */ + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); +} + static bool trans_ror(DisasContext *ctx, arg_ror *a) { REQUIRE_ZBB(ctx); - return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl); + return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw); +} + +static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_rotri_i32(t1, t1, shamt); + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); } static bool trans_rori(DisasContext *ctx, arg_rori *a) { REQUIRE_ZBB(ctx); - return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl); + return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, + tcg_gen_rotri_tl, gen_roriw); +} + +static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + + /* truncate to 32-bits */ + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_trunc_tl_i32(t2, arg2); + + tcg_gen_rotl_i32(t1, t1, t2); + + /* sign-extend 64-bits */ + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); } static bool trans_rol(DisasContext *ctx, arg_rol *a) { REQUIRE_ZBB(ctx); - return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl); + return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw); } static void gen_rev8_32(TCGv ret, TCGv src1) @@ -352,24 +400,6 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl); } -static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv_i32 t1 = tcg_temp_new_i32(); - TCGv_i32 t2 = tcg_temp_new_i32(); - - /* truncate to 32-bits */ - tcg_gen_trunc_tl_i32(t1, arg1); - tcg_gen_trunc_tl_i32(t2, arg2); - - tcg_gen_rotr_i32(t1, t1, t2); - - /* sign-extend 64-bits */ - tcg_gen_ext_i32_tl(ret, t1); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); -} - static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); @@ -383,25 +413,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a) REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); ctx->ol = MXL_RV32; - return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw); -} - -static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv_i32 t1 = tcg_temp_new_i32(); - TCGv_i32 t2 = tcg_temp_new_i32(); - - /* truncate to 32-bits */ - tcg_gen_trunc_tl_i32(t1, arg1); - tcg_gen_trunc_tl_i32(t2, arg2); - - tcg_gen_rotl_i32(t1, t1, t2); - - /* sign-extend 64-bits */ - tcg_gen_ext_i32_tl(ret, t1); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw); } static bool trans_rolw(DisasContext *ctx, arg_rolw *a) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index c0a46d823f..b0fdec97de 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -270,14 +270,26 @@ static bool trans_slli(DisasContext *ctx, arg_slli *a) return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); } +static void gen_srliw(TCGv dst, TCGv src, target_long shamt) +{ + tcg_gen_extract_tl(dst, src, shamt, 32 - shamt); +} + static bool trans_srli(DisasContext *ctx, arg_srli *a) { - return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl); + return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, + tcg_gen_shri_tl, gen_srliw); +} + +static void gen_sraiw(TCGv dst, TCGv src, target_long shamt) +{ + tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt); } static bool trans_srai(DisasContext *ctx, arg_srai *a) { - return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl); + return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, + tcg_gen_sari_tl, gen_sraiw); } static bool trans_add(DisasContext *ctx, arg_add *a) @@ -344,11 +356,6 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a) return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); } -static void gen_srliw(TCGv dst, TCGv src, target_long shamt) -{ - tcg_gen_extract_tl(dst, src, shamt, 32 - shamt); -} - static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { REQUIRE_64BIT(ctx); @@ -356,11 +363,6 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a) return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw); } -static void gen_sraiw(TCGv dst, TCGv src, target_long shamt) -{ - tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt); -} - static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { REQUIRE_64BIT(ctx); From patchwork Wed Oct 20 03:17:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515986 Delivered-To: patch@linaro.org Received: by 2002:adf:a11e:0:0:0:0:0 with SMTP id o30csp1321513wro; Tue, 19 Oct 2021 20:25:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxwFxNc4FoIW8pI9UaiaBB9BCQL1lTD8V7LksNTKNvh6n/soXanx383zKRARFIeIa93Jema X-Received: by 2002:a05:6808:1508:: with SMTP id u8mr5332229oiw.13.1634700309984; Tue, 19 Oct 2021 20:25:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634700309; cv=none; d=google.com; s=arc-20160816; b=lCHybvzfkb4joLcyL1F+k+vegfFQsQTG8wvU7Q8JwSMeaM3NGGdXV86GvYxselppXT ziGpJOc34smPoERNmt7d+3qQMJ+PQPt7FhWvv1rD9qeswvlPHOSFrirZEIz+Taz3f5v0 eEuaBkupkAvACafTQfVxKYMMeKYzY0UgrbYCoati4g7W2ZU20nK1TldEZT4Rifj0O+c+ osZrjd/EHT4b6TAEpBBUEVvs9E/mmPK6Wb4878meVcFdTkgv35h06ByA93X/7jI7oh6G cXkWAmfW18Lt+WdPp24Wyg0T4eEB2p96IMYh/2lRRixbbYAFTQk1+3e+sTY2jpkwY2AJ XGpg== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id j6si1550694otu.343.2021.10.19.20.25.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 20:25:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TA9yB09b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43112 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1md2E0-0002uj-Uw for patch@linaro.org; Tue, 19 Oct 2021 23:25:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47280) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1md26c-0007Lx-JB for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:30 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:36387) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1md26T-00017B-UD for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:30 -0400 Received: by mail-pl1-x635.google.com with SMTP id f21so15138213plb.3 for ; Tue, 19 Oct 2021 20:17:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=10CR3MhgrLCIc6IFDsvW3803qnjtbrRpER/oY1lVkqY=; b=TA9yB09bkL7KEJGWAxzU5OLLXGuP8xurYgX37CB7jJ4NvVsLTt0S6+HH0pBANz6aU8 WhFEIyXeJn8jvwsR1PHApDYZcHFn8/whOkwCxhWc6QokCBzqoQjjzxk6f5uCamWIsh3J CtkfbfVN/LIH6hOxel1yfavd1khVToZ1QfBWVH8FrJ4LpwYe8zBVfOeF2D8c0w4/d5qd IrO633MC6De2TqKjVId076RTamIRYVXCXYHiGctWzPEKeOuvlNpUEQ2SmndfoJyKk16V rbSwAWr5rdamrciYVXqbn0FkdVd2YTNWRJNUu4CkdprbmnCLeHUWoRC7hdAFpd1BpfVO kz0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=10CR3MhgrLCIc6IFDsvW3803qnjtbrRpER/oY1lVkqY=; b=aa0bhezVLCGFKOBLMmztsaLSpFn8Enoqbdh3znmgGYIggyQXEfHIPYamnEF1CmeBa6 GDu7lOkhCc0GXSWGRXb2a8Y/iOsxhkMpT+4YOnQJcHdENy9/QKIrZ2aQ7xy5/QLcm/LG +IqiTmRd6plI4NdtRPnZtrLsWri2V73v4ypsKt28Lg2Q+rRFctUIbWvX9vV/KT7ppCC8 bNEyPm8atifofWkPxyvbummEzzeeJg8dLjAR2MGqek0HaVojMO5Jk5Rc21N2N6IJ+ivU WbNepRt2bOqcHyAsyPiHxG5ARtZ7B8PUzFBE4fm0xMX8US8BSLgC1HCz3xorfmKnq4MJ oOow== X-Gm-Message-State: AOAM531sJc8T8ybDgcthCB7YRXBuJPasJ3IYvBppLQfER57VEMciwLEk n7v9N09AqoI1O5m2EBfEOjnfRlDjaYfS2Q== X-Received: by 2002:a17:90b:17d0:: with SMTP id me16mr4436738pjb.152.1634699840575; Tue, 19 Oct 2021 20:17:20 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id c8sm505364pjr.38.2021.10.19.20.17.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 20:17:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 14/15] target/riscv: Use riscv_csrrw_debug for cpu_dump Date: Tue, 19 Oct 2021 20:17:08 -0700 Message-Id: <20211020031709.359469-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020031709.359469-1-richard.henderson@linaro.org> References: <20211020031709.359469-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the official debug read interface to the csrs, rather than referencing the env slots directly. Put the list of csrs to dump into a table. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.c | 89 +++++++++++++++++++++++----------------------- 1 file changed, 45 insertions(+), 44 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index babe271e53..79071bde4e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -242,51 +242,52 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #endif qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); #ifndef CONFIG_USER_ONLY - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); - if (riscv_cpu_mxl(env) == MXL_RV32) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", - (target_ulong)(env->mstatus >> 32)); + { + static const int dump_csrs[] = { + CSR_MHARTID, + CSR_MSTATUS, + CSR_MSTATUSH, + CSR_HSTATUS, + CSR_VSSTATUS, + CSR_MIP, + CSR_MIE, + CSR_MIDELEG, + CSR_HIDELEG, + CSR_MEDELEG, + CSR_HEDELEG, + CSR_MTVEC, + CSR_STVEC, + CSR_VSTVEC, + CSR_MEPC, + CSR_SEPC, + CSR_VSEPC, + CSR_MCAUSE, + CSR_SCAUSE, + CSR_VSCAUSE, + CSR_MTVAL, + CSR_STVAL, + CSR_HTVAL, + CSR_MTVAL2, + CSR_MSCRATCH, + CSR_SSCRATCH, + CSR_SATP, + }; + + for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { + int csrno = dump_csrs[i]; + target_ulong val = 0; + RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); + + /* + * Rely on the smode, hmode, etc, predicates within csr.c + * to do the filtering of the registers that are present. + */ + if (res == RISCV_EXCP_NONE) { + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", + csr_ops[csrno].name, val); + } + } } - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus", - (target_ulong)env->vsstatus); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp); #endif for (i = 0; i < 32; i++) { From patchwork Wed Oct 20 03:17:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515993 Delivered-To: patch@linaro.org Received: by 2002:adf:a11e:0:0:0:0:0 with SMTP id o30csp1328828wro; Tue, 19 Oct 2021 20:37:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwxgqqHS+Wast1ttcyOQGl/L/OrqHA26c+MT33amdhXTSrkganH8vKJ56nhdBNMym8IX/do X-Received: by 2002:a25:dc87:: with SMTP id y129mr42023028ybe.118.1634701054483; Tue, 19 Oct 2021 20:37:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634701054; cv=none; d=google.com; s=arc-20160816; b=VjROkpCWzpk5xVX9nX7WOJpFf1Quhiqkx8xV4Gs1iIqVz9gjrTVtlCfaJjbKJHm6I3 LdyjDR3OMg3rC2UUrLQWU/0gxqG992HdPQg7y9pNA2rWHDuRqNJB5zyxLp2v8s3Kx/44 j87IclZ+yhnUEw0IcgOXFL0VBXLQI8wmi6EJEggXdrMOEPZ+2WLr+wBxze+ThwrAtiea jqvcvoSct9KcJbvk4tyKbx4tvbGAEEsgTAxRACLpGufVDSJU4gneFz7EhB+bM7Z4mOqr sA30kSEZPnY/w4FykjeSJIeJFu/ueiG4bOi7CCEeWMXHxwWweXBrmoUjFRIppYHf3AWN LgWg== ARC-Message-Signature: i=1; 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Rather than having to compute that difference in many places, compute it only on read. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 3 +-- target/riscv/csr.c | 37 ++++++++++++++++++++++--------------- target/riscv/translate.c | 5 ++--- 3 files changed, 25 insertions(+), 20 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 429afd1f48..0d1132f39d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -185,10 +185,9 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { - uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD; uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | - MSTATUS64_UXL | sd; + MSTATUS64_UXL; bool current_virt = riscv_cpu_virt_enabled(env); g_assert(riscv_has_ext(env, RVH)); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c4a479ddd2..69e4d65fcd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -477,10 +477,28 @@ static RISCVException read_mhartid(CPURISCVState *env, int csrno, } /* Machine Trap Setup */ + +/* We do not store SD explicitly, only compute it on demand. */ +static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) +{ + if ((status & MSTATUS_FS) == MSTATUS_FS || + (status & MSTATUS_XS) == MSTATUS_XS) { + switch (xl) { + case MXL_RV32: + return status | MSTATUS32_SD; + case MXL_RV64: + return status | MSTATUS64_SD; + default: + g_assert_not_reached(); + } + } + return status; +} + static RISCVException read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) { - *val = env->mstatus; + *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); return RISCV_EXCP_NONE; } @@ -498,7 +516,6 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, { uint64_t mstatus = env->mstatus; uint64_t mask = 0; - int dirty; /* flush tlb on mstatus fields that affect VM */ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | @@ -520,12 +537,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, mstatus = (mstatus & ~mask) | (val & mask); - dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | - ((mstatus & MSTATUS_XS) == MSTATUS_XS); - if (riscv_cpu_mxl(env) == MXL_RV32) { - mstatus = set_field(mstatus, MSTATUS32_SD, dirty); - } else { - mstatus = set_field(mstatus, MSTATUS64_SD, dirty); + if (riscv_cpu_mxl(env) == MXL_RV64) { /* SXL and UXL fields are for now read only */ mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64); mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64); @@ -798,13 +810,8 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno, { target_ulong mask = (sstatus_v1_10_mask); - if (riscv_cpu_mxl(env) == MXL_RV32) { - mask |= SSTATUS32_SD; - } else { - mask |= SSTATUS64_SD; - } - - *val = env->mstatus & mask; + /* TODO: Use SXL not MXL. */ + *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); return RISCV_EXCP_NONE; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0b3da060fd..1d6bf01a48 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -305,7 +305,6 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) static void mark_fs_dirty(DisasContext *ctx) { TCGv tmp; - target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD; if (ctx->mstatus_fs != MSTATUS_FS) { /* Remember the state change for the rest of the TB. */ @@ -313,7 +312,7 @@ static void mark_fs_dirty(DisasContext *ctx) tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_temp_free(tmp); } @@ -324,7 +323,7 @@ static void mark_fs_dirty(DisasContext *ctx) tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); tcg_temp_free(tmp); }