From patchwork Tue Oct 19 15:24:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515969 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp833782imp; Tue, 19 Oct 2021 09:34:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxo0ZNdi18j5h2eIXXBfKOqhLb0CrR6JXCIr1FpXB3z1aVPZ1e56sPwe1jmsuZUDYnJRk3D X-Received: by 2002:a9d:6c91:: with SMTP id c17mr6098794otr.114.1634661258781; Tue, 19 Oct 2021 09:34:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634661258; cv=none; d=google.com; s=arc-20160816; b=Uhoxh3nERSaJovErX34o0Slkob8hHokslRaSWn3m2lCEjzr9xrkaqZk8do8L0gOghX iN6WqoHNJAParRkzyTRS+539RtpmppRxX0WlUUWT8dsf9dFp46bNcu6BwdxE+2oGirZ8 0rnrnTkCuUVfUCxO4/5GLo4JrZJtOKbshdiKO/aliCWWns33sEgkkXXdQSNOi0N7AtwQ 3Cp/SkCFW0F7l2INTbgm6YS3nmdzHdJl+mdMnpkwUegPhAvL8qB9/YBKupu0weXuEkrK fSW5weoTgv+mfxoTNkPmk1nALdkjlWYsTqQhGVewo21rab/Uvv7+EYQPgmI3kjsf3G42 O5XA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ur4NYkKvb4IwfCVRQ66xGSUcq2q0ktl5nOkYZP/fju8=; b=0IGMw3xZM8rYpVpSebbOsyEKX+E5gwbpIl9jUd3Qbm0M4XZ0BPVS995smHNg2ewZvW +bvFgnUB9LmoD6CYqBHtGtUyXB+3f1SmwUtxd+18bCqV3A1lMU9W3KGm/6w/L2//kfgt 8Fq97vsXTQedYQo1nIA5w2nWOytbh97JrQjXOjqny8avVDtyTa28Tk3fulZMuPI2VXtI ptARC7aa+rjN211+9yu6pZpVjAKxjUF36Py9jpYY9y6pgagCJIbPLiG0XTcNoy5TxP2c +ZO5+5XDmpEu1gDWBrWdBkLU8tqDFeeRZnbog5trXCHRM2Te+i6p4HHTL25HszGY9M0L CxeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mDeCoX00; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w65si19888041oib.291.2021.10.19.09.34.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 09:34:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mDeCoX00; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52600 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcs4A-0003aW-3d for patch@linaro.org; Tue, 19 Oct 2021 12:34:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54120) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqyr-0004lJ-Cw for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:45 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:34660) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcqyo-0007Se-4E for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:44 -0400 Received: by mail-pl1-x633.google.com with SMTP id g5so13920638plg.1 for ; Tue, 19 Oct 2021 08:24:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ur4NYkKvb4IwfCVRQ66xGSUcq2q0ktl5nOkYZP/fju8=; b=mDeCoX00cF4NTV/f1IQTb6N1EdKjmgcRY/IdoRiiz8WNve5tk8AGlIlwyfr2FkTAjK 9iUIOPHWCvE3xzoF18ibWnK7+UyXxijekwMR+YG34il+rBRrmuk0LOOyoTh0Nq7BKGMP 8EVTrObFM+a/5mwcVZF3GJEiPlsWyQ3uT/DVS7O3eliTgMsik0rf2ibnedl+ojd35bZx ZWAdI0HNyNkz6MGPLtUklh99n6NSpSEOVTgVDTeYtjcFFlUAdxOK1Pp4roip/jTGdrsX mBptRk99fq5/jeJkGpTRq2bCGM0O6lFzaFuPBgsmyQaewqwvez8Za5GzcQlbNi5Bm4+D EKtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ur4NYkKvb4IwfCVRQ66xGSUcq2q0ktl5nOkYZP/fju8=; b=Cy3k+7wcTsNNtRW4BH7Rf9zvWk2VxpC/cCmyXzBmPJxZBDDqX50DsGrs0u5zKykMGL 3r/MVkLn3uHlIvT7GUOS6c2x6U2Srzigu334Tvqw3O0/yoSIgIn1j5kVBhFBWqLp1pzD zij+IrfQ7nYuUatQyPJTDf1xlmJ/K8Kts7n9FSUAXk4aXipG9GzyO9aG38OEbdS94FNQ TI1h2fUxHqqULI4b/MfkR+MKmKmFx6/vWueovtaWahcz8NjT15+eEEPEEgOCFzP2dQmn eNMXQrXaG6+EXHxa+DbR33FcuOTp6E0QmM3Vt6SmT3ZXQt7NrUrC0sBvQY4OX1LwV/q2 gQHg== X-Gm-Message-State: AOAM530y+qQ9t5UyTikiJFPp5b/9eIfonXOHwP5+wTcuiHCiHwh1QGws +UlFi62zuOGt5TU+8Ih28fz22AFM3FPrcQ== X-Received: by 2002:a17:902:f281:b0:13f:3be8:b160 with SMTP id k1-20020a170902f28100b0013f3be8b160mr34074439plc.32.1634657080340; Tue, 19 Oct 2021 08:24:40 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i2sm3293814pjt.19.2021.10.19.08.24.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 08:24:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 01/16] target/riscv: Move cpu_get_tb_cpu_state out of line Date: Tue, 19 Oct 2021 08:24:23 -0700 Message-Id: <20211019152438.269077-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019152438.269077-1-richard.henderson@linaro.org> References: <20211019152438.269077-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the function to cpu_helper.c, as it is large and growing. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 47 ++------------------------------------- target/riscv/cpu_helper.c | 46 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 45 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9e55b2f5b1..7084efc452 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -413,51 +413,8 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) return cpu->cfg.vlen >> (sew + 3 - lmul); } -static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *pflags) -{ - uint32_t flags = 0; - - *pc = env->pc; - *cs_base = 0; - - if (riscv_has_ext(env, RVV)) { - uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); - bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); - flags = FIELD_DP32(flags, TB_FLAGS, VILL, - FIELD_EX64(env->vtype, VTYPE, VILL)); - flags = FIELD_DP32(flags, TB_FLAGS, SEW, - FIELD_EX64(env->vtype, VTYPE, VSEW)); - flags = FIELD_DP32(flags, TB_FLAGS, LMUL, - FIELD_EX64(env->vtype, VTYPE, VLMUL)); - flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); - } else { - flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); - } - -#ifdef CONFIG_USER_ONLY - flags |= TB_FLAGS_MSTATUS_FS; -#else - flags |= cpu_mmu_index(env, 0); - if (riscv_cpu_fp_enabled(env)) { - flags |= env->mstatus & MSTATUS_FS; - } - - if (riscv_has_ext(env, RVH)) { - if (env->priv == PRV_M || - (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); - } - - flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, - get_field(env->mstatus_hs, MSTATUS_FS)); - } -#endif - - *pflags = flags; -} +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags); RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d41d5cd27c..14d1d3cb72 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -35,6 +35,52 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags) +{ + uint32_t flags = 0; + + *pc = env->pc; + *cs_base = 0; + + if (riscv_has_ext(env, RVV)) { + uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); + bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); + flags = FIELD_DP32(flags, TB_FLAGS, VILL, + FIELD_EX64(env->vtype, VTYPE, VILL)); + flags = FIELD_DP32(flags, TB_FLAGS, SEW, + FIELD_EX64(env->vtype, VTYPE, VSEW)); + flags = FIELD_DP32(flags, TB_FLAGS, LMUL, + FIELD_EX64(env->vtype, VTYPE, VLMUL)); + flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); + } else { + flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); + } + +#ifdef CONFIG_USER_ONLY + flags |= TB_FLAGS_MSTATUS_FS; +#else + flags |= cpu_mmu_index(env, 0); + if (riscv_cpu_fp_enabled(env)) { + flags |= env->mstatus & MSTATUS_FS; + } + + if (riscv_has_ext(env, RVH)) { + if (env->priv == PRV_M || + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); + } + + flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, + get_field(env->mstatus_hs, MSTATUS_FS)); + } +#endif + + *pflags = flags; +} + #ifndef CONFIG_USER_ONLY static int riscv_cpu_local_irq_pending(CPURISCVState *env) { From patchwork Tue Oct 19 15:24:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515967 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp826801imp; Tue, 19 Oct 2021 09:27:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzSYXh5O8C95qoZ94+Hb1unp+UNe0TUE2mBUKJ5mMIt4DuEoqhUI/6SaqDQ8+TptgmOUgkz X-Received: by 2002:a37:67ce:: with SMTP id b197mr797183qkc.23.1634660838788; Tue, 19 Oct 2021 09:27:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634660838; cv=none; d=google.com; s=arc-20160816; b=YwOtuwj0+Vqsj4cUmZuyorfUhexiSiq43Y+vfPMycZO+3zbcoN1itziiB5FtpyhJQi NyE9yThaDCivwwvb7NVj8Mps8OGgqB+DKc30vhU4EiLrTGvwuzC5IS1pTGDUSjwnKDP9 akGp56CIl1EKRWtEIMOF7+Z+2kONSHcDHlS3AcvyNejvrLoDNRojXX4OqHDR+ONt4O5x 5fR6hrVrRpQJc/HoMGsuSmt/vBnJACYkCYnVGHEqn0UuXDeGm2dIOHNZjpvGGx9VqY9G qa3ug1SIUznH5pr7grEoY4WXUAmPeMVkmYNKmT5mZf2qmJcoY+zsVwCP6Dkf2Y2AFY/E pw0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JW/tzOqQKK5hRD4CRoj0kca6rOybKGXTUDDhLFOWwb8=; b=UpBrFHr7qp3hmL55xyi9zAhfXGCCdgoGL1dk7zZKjmsapTyYrCrfEGYnU9YpkVaHCS tq/wTEdGY/BtOFlXti+OEeF02YRG8kyEYcsNir+YOt76ys8aRH3FALy0+jAYmb4K6iXe ARJYqEwBCYVSCk6G/ofKmAJy9sP8k8h400Xcoh+JKwzuLOBxd0eSU+sNkqcikfqlfyRd So611PUQIbljGPaf93yClNPN8y0hXMEZfEuPlfEbfybkU3CcMYjI9Tee2ksM5mNq2Ppw XjMy6mqLZ3ubEh96wkNEC5dWZrGxy190GqXZg8aMB8LqeOLGzMHoO68nKKcEmV/2z7sM RQrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=oSHSzyl+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n1si17836270vse.415.2021.10.19.09.27.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 09:27:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=oSHSzyl+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34464 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcrxO-0007Zn-5R for patch@linaro.org; Tue, 19 Oct 2021 12:27:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54200) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqyt-0004pW-Rg for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:48 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:36804) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcqyo-0007Tb-81 for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:47 -0400 Received: by mail-pg1-x535.google.com with SMTP id 75so19699725pga.3 for ; Tue, 19 Oct 2021 08:24:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JW/tzOqQKK5hRD4CRoj0kca6rOybKGXTUDDhLFOWwb8=; b=oSHSzyl+0YEoYo3DImNOanUBwswlpvbVBX5nM0So6eJa3nUXscwS7h9Do9CqBSWePu uxsEDre1AN/LmZ6VhlkNQL4jHKefAF/NCW9kMoHGUEaTDi+X7Q1YPrjeDL6Qy/Zccd8h uNiw5Krptdcizh81zaRoDmaoSP207839+yFDHZtS+JivqdxBPryXuV+wqL9mmfbR7Nxs 4gGMb26bT8WvuMPxkMxFeWc4LtTm1Sr2Gyr78qiFnNhiEbC5Ov/eH8WiKVyV69b1Yvxz Q6PbMK61dBwTs5jwnsVq6zWHfpIO/cR2MhctNPO7bCHHteePhEM9HUPEVG7jdP4Opayx pbnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JW/tzOqQKK5hRD4CRoj0kca6rOybKGXTUDDhLFOWwb8=; b=vMihlgUHYkIbwrzMRuT4fbwRUzNdAHDchvkhIA3HgEyn+gtCt9Eiul1TDSCyJkA42u AOQEk+phVuDsx3OdJKJqAulZs+OjHn6jOPJfr6w43PDUy5c3+znklB3+wrYcxzBfClUT MijlqDU0OnA6F7cX5BtMp3ZsDh14haVkEQ1cif6oasHX0nQjonycq9LFFy3ziQedKOA3 +CkYYENnAEjWFqCxA/rYIsSMmhiBm873C63GVNNlQaUrwbzqHYRHdbdefuD+thVbFWik Xe/5/elhzl/3PLWI3w8mHjyUTYIfTpt1/u6BTdVYDrb3D4gbYrw86pAaMxyFxoRUYYjZ 9p8w== X-Gm-Message-State: AOAM533V2zJ8Veg2Xur0IE0GtBG8VOkWnNBkKw8GJbkgZf93TMsLKHiC 7i5zjusb4ESq5yMxWWkNDkug+xoXEVNoHw== X-Received: by 2002:a63:b91c:: with SMTP id z28mr17756291pge.393.1634657080938; Tue, 19 Oct 2021 08:24:40 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i2sm3293814pjt.19.2021.10.19.08.24.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 08:24:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 02/16] target/riscv: Create RISCVMXL enumeration Date: Tue, 19 Oct 2021 08:24:24 -0700 Message-Id: <20211019152438.269077-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019152438.269077-1-richard.henderson@linaro.org> References: <20211019152438.269077-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the MXL_RV* defines to enumerators. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu_bits.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 999187a9ee..e248c6bf6d 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -364,9 +364,11 @@ #define MISA32_MXL 0xC0000000 #define MISA64_MXL 0xC000000000000000ULL -#define MXL_RV32 1 -#define MXL_RV64 2 -#define MXL_RV128 3 +typedef enum { + MXL_RV32 = 1, + MXL_RV64 = 2, + MXL_RV128 = 3, +} RISCVMXL; /* sstatus CSR bits */ #define SSTATUS_UIE 0x00000001 From patchwork Tue Oct 19 15:24:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515959 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp785935imp; Tue, 19 Oct 2021 08:46:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyD5TLqxmiv2uH/VqG62X2rWOAWUTKp7gyR+dIiqJUGZi8alLmBMMo6fEIBN1JE0f3nRUrq X-Received: by 2002:a9d:37e2:: with SMTP id x89mr6178526otb.300.1634658365060; Tue, 19 Oct 2021 08:46:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634658365; cv=none; d=google.com; s=arc-20160816; b=Df5/kBuGfOpLBO2iOQ9CrNQwzlaBm1TlGVlJvmFbFIq6aVkuTT6Uh2HWN6KbMUa7TK /OmK4v2ALAU6cUfR86t78P3fm8WUr//5pZ0yiro2l/Eo+iAp/yaSlH/PilgkHG5VBtFB 5WpjgoEivEUKXKqjwsxCljmceXthSP2mVJKFGDlxIhydKoJTFMmGJBA1dTH3WL2M8OjP 9TrwTRHr41ZISoAz4vfbn4Eam8I7iwdUH2NNLbnQ7DE/Zz6OfLJQpTjW+MsjJxwVuJmP 0AXhJ6XzWTxQFPKCcLodVjcAgEdM139OKsZPeysuqX8nAzSrlUobhtN0dZ5E45dB9e88 0elQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=axUeM4wR3ZbiQZ9gN07cf/OmbYseQ9DiBDAnxCabNms=; b=H5RyKD/VrY3yMEcit1GqSU3JwRe1c/tL0UHXtoOiAaVB6tK++IISMhlrbqHWYdm8RW f7rmF59pB6V7I5jYcW52EJ1FXNU4VZVqHHDIp6XVQNInJib/EKu30EvOqBNiDVhjM0NC hqYD1q2sm9ff5mJ5cELGmTAR479kQj9P9yn6klEbHQUT9833uCtNbiYeNxJxGt0AvbYX MW9YwhcqtmmDoFio4hZQ1yDYaZBAUqlt6wfIf/tbi9bUye4qPdxyxsgWD06mXcKVFt5V SAbQTao5S+oW8bwDvJh36cb2k5epg6BXzMQ3VNqFYey3+OamxuD3/fgHm6Hlr3GQ4yZV oLeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="RUhG/S6Y"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e30si16237467otb.210.2021.10.19.08.46.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 08:46:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="RUhG/S6Y"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42744 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcrJT-0003gv-N3 for patch@linaro.org; Tue, 19 Oct 2021 11:46:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54236) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqyu-0004qm-NZ for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:49 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:44673) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcqyp-0007Uh-9Y for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:48 -0400 Received: by mail-pj1-x1034.google.com with SMTP id oa12-20020a17090b1bcc00b0019f715462a8so131808pjb.3 for ; Tue, 19 Oct 2021 08:24:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=axUeM4wR3ZbiQZ9gN07cf/OmbYseQ9DiBDAnxCabNms=; b=RUhG/S6YYdTCuPZ4MM1Knxgo8cng9PlOEBTG+10a6BaHwGpqWEJKiWWIv7YM+A1H4M /bKW4DjkYyft23Ya896B0QzjA66D4//Hl8HWz4De+k6nB2W/EFLY6z1R4OTsCPFoYCq4 JdyV5MvzWhx2KuPDYUSA7KDSleXsKNWxiLJXbNazpaj3Kb++cos3bF3JTqaG3k/MrMwT Qni+LsOu76FdQNsmUxpd5EFBhzS3Mha9Pjq7PlTcFU4FSWID1AI50G/1N0ZwLavEHTh1 TwP2KTp0rIOK2cmAmYF5IJh2Gq+g9vWKbzvh2FeYw8x0Rz/f45q4NosXfRa0XewpBkbV 105A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=axUeM4wR3ZbiQZ9gN07cf/OmbYseQ9DiBDAnxCabNms=; b=bLWjs9Ave0nxZsVq+9eRFcIjxZg9Y6kSX+X1J5wNGNw7Mj4HAIiCSHwKVD5228UAtp VzBF6+DjtngAeCEJekc0GI/hioJYalJkHrZMTGEjXhqNijcKzTMEk40iSU3mPNllJDar Kto8AfhB6MKS4cmmy5sujBtvMoKGu2q/nJ5YmohEXiTVciPx7TRhfERCZHNoc9LRf10i /6mrkeuuzCyZMyqKrBKnt23xk3Kz3PDk9sdmSwk7G/JHOdnMRoZo4XKgZvwmU+Ygq0Mh KZtXkttLr09QaAzWsbhVZE8uJoG8bjaV40zdAFHsPte0f6rIAVeI34kUVeUdKem/KEeT ggeA== X-Gm-Message-State: AOAM532cDYwz67ZionSyDqrfuDovfUMtNRlEfAI6Bo0AJR55irr50VIR b4y0qjqpbhJmqCLtriRg7PLGn1WqHExaww== X-Received: by 2002:a17:902:db0a:b0:13e:e968:e144 with SMTP id m10-20020a170902db0a00b0013ee968e144mr33936236plx.43.1634657081803; Tue, 19 Oct 2021 08:24:41 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i2sm3293814pjt.19.2021.10.19.08.24.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 08:24:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 03/16] target/riscv: Split misa.mxl and misa.ext Date: Tue, 19 Oct 2021 08:24:25 -0700 Message-Id: <20211019152438.269077-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019152438.269077-1-richard.henderson@linaro.org> References: <20211019152438.269077-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The hw representation of misa.mxl is at the high bits of the misa csr. Representing this in the same way inside QEMU results in overly complex code trying to check that field. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 15 +++---- linux-user/elfload.c | 2 +- linux-user/riscv/cpu_loop.c | 2 +- target/riscv/cpu.c | 78 +++++++++++++++++++++---------------- target/riscv/csr.c | 44 ++++++++++++++------- target/riscv/gdbstub.c | 8 ++-- target/riscv/machine.c | 10 +++-- target/riscv/translate.c | 10 +++-- 8 files changed, 100 insertions(+), 69 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7084efc452..e708fcc168 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -25,6 +25,7 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" #include "qom/object.h" +#include "cpu_bits.h" #define TCG_GUEST_DEFAULT_MO 0 @@ -51,9 +52,6 @@ # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 #endif -#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) -#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) - #define RV(x) ((target_ulong)1 << (x - 'A')) #define RVI RV('I') @@ -133,8 +131,12 @@ struct CPURISCVState { target_ulong priv_ver; target_ulong bext_ver; target_ulong vext_ver; - target_ulong misa; - target_ulong misa_mask; + + /* RISCVMXL, but uint32_t for vmstate migration */ + uint32_t misa_mxl; /* current mxl */ + uint32_t misa_mxl_max; /* max mxl for this cpu */ + uint32_t misa_ext; /* current extensions */ + uint32_t misa_ext_mask; /* max ext for this cpu */ uint32_t features; @@ -313,7 +315,7 @@ struct RISCVCPU { static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) { - return (env->misa & ext) != 0; + return (env->misa_ext & ext) != 0; } static inline bool riscv_feature(CPURISCVState *env, int feature) @@ -322,7 +324,6 @@ static inline bool riscv_feature(CPURISCVState *env, int feature) } #include "cpu_user.h" -#include "cpu_bits.h" extern const char * const riscv_int_regnames[]; extern const char * const riscv_fpr_regnames[]; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 2404d482ba..214c1aa40d 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1448,7 +1448,7 @@ static uint32_t get_elf_hwcap(void) uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); - return cpu->env.misa & mask; + return cpu->env.misa_ext & mask; #undef MISA_BIT } diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 9859a366e4..e5bb6d908a 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -133,7 +133,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) env->gpr[xSP] = regs->sp; env->elf_flags = info->elf_flags; - if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) { + if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) { error_report("Incompatible ELF: RVE cpu requires RVE ABI binary"); exit(EXIT_FAILURE); } diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1d69d1887e..fdf031a394 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,16 +110,13 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) bool riscv_cpu_is_32bit(CPURISCVState *env) { - if (env->misa & RV64) { - return false; - } - - return true; + return env->misa_mxl == MXL_RV32; } -static void set_misa(CPURISCVState *env, target_ulong misa) +static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) { - env->misa_mask = env->misa = misa; + env->misa_mxl_max = env->misa_mxl = mxl; + env->misa_ext_mask = env->misa_ext = ext; } static void set_priv_version(CPURISCVState *env, int priv_ver) @@ -148,9 +145,9 @@ static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; #if defined(TARGET_RISCV32) - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #elif defined(TARGET_RISCV64) - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif set_priv_version(env, PRIV_VERSION_1_11_0); } @@ -160,20 +157,20 @@ static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, RV64); + set_misa(env, MXL_RV64, 0); } static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); } static void rv64_sifive_e_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } @@ -182,20 +179,20 @@ static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, RV32); + set_misa(env, MXL_RV32, 0); } static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); } static void rv32_sifive_e_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } @@ -203,7 +200,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) static void rv32_ibex_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVC | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); qdev_prop_set_bit(DEVICE(obj), "mmu", false); qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); @@ -212,7 +209,7 @@ static void rv32_ibex_cpu_init(Object *obj) static void rv32_imafcu_nommu_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); set_resetvec(env, DEFAULT_RSTVEC); qdev_prop_set_bit(DEVICE(obj), "mmu", false); @@ -360,6 +357,7 @@ static void riscv_cpu_reset(DeviceState *dev) mcc->parent_reset(dev); #ifndef CONFIG_USER_ONLY + env->misa_mxl = env->misa_mxl_max; env->priv = PRV_M; env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); env->mcause = 0; @@ -388,7 +386,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) CPURISCVState *env = &cpu->env; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); int priv_version = 0; - target_ulong target_misa = env->misa; Error *local_err = NULL; cpu_exec_realizefn(cs, &local_err); @@ -434,8 +431,23 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_resetvec(env, cpu->cfg.resetvec); - /* If only XLEN is set for misa, then set misa from properties */ - if (env->misa == RV32 || env->misa == RV64) { + /* Validate that MISA_MXL is set properly. */ + switch (env->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + break; +#endif + case MXL_RV32: + break; + default: + g_assert_not_reached(); + } + assert(env->misa_mxl_max == env->misa_mxl); + + /* If only MISA_EXT is unset for misa, then set it from properties */ + if (env->misa_ext == 0) { + uint32_t ext = 0; + /* Do some ISA extension error checking */ if (cpu->cfg.ext_i && cpu->cfg.ext_e) { error_setg(errp, @@ -462,38 +474,38 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_i) { - target_misa |= RVI; + ext |= RVI; } if (cpu->cfg.ext_e) { - target_misa |= RVE; + ext |= RVE; } if (cpu->cfg.ext_m) { - target_misa |= RVM; + ext |= RVM; } if (cpu->cfg.ext_a) { - target_misa |= RVA; + ext |= RVA; } if (cpu->cfg.ext_f) { - target_misa |= RVF; + ext |= RVF; } if (cpu->cfg.ext_d) { - target_misa |= RVD; + ext |= RVD; } if (cpu->cfg.ext_c) { - target_misa |= RVC; + ext |= RVC; } if (cpu->cfg.ext_s) { - target_misa |= RVS; + ext |= RVS; } if (cpu->cfg.ext_u) { - target_misa |= RVU; + ext |= RVU; } if (cpu->cfg.ext_h) { - target_misa |= RVH; + ext |= RVH; } if (cpu->cfg.ext_v) { int vext_version = VEXT_VERSION_0_07_1; - target_misa |= RVV; + ext |= RVV; if (!is_power_of_2(cpu->cfg.vlen)) { error_setg(errp, "Vector extension VLEN must be power of 2"); @@ -532,7 +544,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_vext_version(env, vext_version); } - set_misa(env, target_misa); + set_misa(env, env->misa_mxl, ext); } riscv_cpu_register_gdb_regs_for_features(cs); @@ -705,7 +717,7 @@ char *riscv_isa_string(RISCVCPU *cpu) char *isa_str = g_new(char, maxlen); char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); for (i = 0; i < sizeof(riscv_exts); i++) { - if (cpu->env.misa & RV(riscv_exts[i])) { + if (cpu->env.misa_ext & RV(riscv_exts[i])) { *p++ = qemu_tolower(riscv_exts[i]); } } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 23fbbd3216..d0c86a300d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -39,7 +39,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) /* loose check condition for fcsr in vector extension */ - if ((csrno == CSR_FCSR) && (env->misa & RVV)) { + if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) { return RISCV_EXCP_NONE; } if (!env->debugger && !riscv_cpu_fp_enabled(env)) { @@ -51,7 +51,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) static RISCVException vs(CPURISCVState *env, int csrno) { - if (env->misa & RVV) { + if (env->misa_ext & RVV) { return RISCV_EXCP_NONE; } return RISCV_EXCP_ILLEGAL_INST; @@ -557,7 +557,22 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno, static RISCVException read_misa(CPURISCVState *env, int csrno, target_ulong *val) { - *val = env->misa; + target_ulong misa; + + switch (env->misa_mxl) { + case MXL_RV32: + misa = (target_ulong)MXL_RV32 << 30; + break; +#ifdef TARGET_RISCV64 + case MXL_RV64: + misa = (target_ulong)MXL_RV64 << 62; + break; +#endif + default: + g_assert_not_reached(); + } + + *val = misa | env->misa_ext; return RISCV_EXCP_NONE; } @@ -583,8 +598,13 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } + /* + * misa.MXL writes are not supported by QEMU. + * Drop writes to those bits. + */ + /* Mask extensions that are not supported by this hart */ - val &= env->misa_mask; + val &= env->misa_ext_mask; /* Mask extensions that are not supported by QEMU */ val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); @@ -601,20 +621,14 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, val &= ~RVC; } - /* misa.MXL writes are not supported by QEMU */ - if (riscv_cpu_is_32bit(env)) { - val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL); - } else { - val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL); + /* If nothing changed, do nothing. */ + if (val == env->misa_ext) { + return RISCV_EXCP_NONE; } /* flush translation cache */ - if (val != env->misa) { - tb_flush(env_cpu(env)); - } - - env->misa = val; - + tb_flush(env_cpu(env)); + env->misa_ext = val; return RISCV_EXCP_NONE; } diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index a7a9c0b1fe..5257df0217 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -54,10 +54,10 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) { if (n < 32) { - if (env->misa & RVD) { + if (env->misa_ext & RVD) { return gdb_get_reg64(buf, env->fpr[n]); } - if (env->misa & RVF) { + if (env->misa_ext & RVF) { return gdb_get_reg32(buf, env->fpr[n]); } /* there is hole between ft11 and fflags in fpu.xml */ @@ -191,10 +191,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; - if (env->misa & RVD) { + if (env->misa_ext & RVD) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-64bit-fpu.xml", 0); - } else if (env->misa & RVF) { + } else if (env->misa_ext & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-32bit-fpu.xml", 0); } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 16a08302da..f64b2a96c1 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -140,8 +140,8 @@ static const VMStateDescription vmstate_hyper = { const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", - .version_id = 2, - .minimum_version_id = 2, + .version_id = 3, + .minimum_version_id = 3, .fields = (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), @@ -153,8 +153,10 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), VMSTATE_UINTTL(env.priv_ver, RISCVCPU), VMSTATE_UINTTL(env.vext_ver, RISCVCPU), - VMSTATE_UINTTL(env.misa, RISCVCPU), - VMSTATE_UINTTL(env.misa_mask, RISCVCPU), + VMSTATE_UINT32(env.misa_mxl, RISCVCPU), + VMSTATE_UINT32(env.misa_ext, RISCVCPU), + VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), + VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), VMSTATE_UINT32(env.features, RISCVCPU), VMSTATE_UINTTL(env.priv, RISCVCPU), VMSTATE_UINTTL(env.virt, RISCVCPU), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6d7fbca1fa..66857732e8 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -55,7 +55,8 @@ typedef struct DisasContext { /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; target_ulong priv_ver; - target_ulong misa; + RISCVMXL xl; + uint32_t misa_ext; uint32_t opcode; uint32_t mstatus_fs; uint32_t mstatus_hs_fs; @@ -86,7 +87,7 @@ typedef struct DisasContext { static inline bool has_ext(DisasContext *ctx, uint32_t ext) { - return ctx->misa & ext; + return ctx->misa_ext & ext; } #ifdef TARGET_RISCV32 @@ -96,7 +97,7 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) #else static inline bool is_32bit(DisasContext *ctx) { - return (ctx->misa & RV32) == RV32; + return ctx->xl == MXL_RV32; } #endif @@ -513,7 +514,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #else ctx->virt_enabled = false; #endif - ctx->misa = env->misa; + ctx->xl = env->misa_mxl; + ctx->misa_ext = env->misa_ext; ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei; ctx->vlen = cpu->cfg.vlen; From patchwork Tue Oct 19 15:24:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515961 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp790903imp; Tue, 19 Oct 2021 08:51:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw0zey8ECiZzkHyaTKB4SbAO1XAcOKU5fQdiW6ppqt9qerZRIgDgB+2z8Dakc/sSNCxe2Gb X-Received: by 2002:a54:418a:: with SMTP id 10mr4874270oiy.13.1634658680664; Tue, 19 Oct 2021 08:51:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634658680; cv=none; d=google.com; s=arc-20160816; b=edhViNF3nF07pbDxL39E0ezAyUHbqmaygZPglGxKJm78jS5YujIsz1/oTWuBguneX9 IETTOQdQKA471qv++cR/UHVLaKSGodEm+ZtxupwGZOkl5a11S5hKuH2Hnh8h8Rcroazm ds37KEms/DBOEOx8QEF732sRJ9GdOKyAfVDv8JrK1HEQ0JImShBKuhmfeS64AP20j/8h ccR/t+/VPmJl6O5Hx5vGDvfz/N69+u5hgVhk3XKzA9FMX3PVCFMC4jAW8X0YhRGD5PnV X1nZ7JbLWq9xiCRYL6tr2oTCBcZ4JPKsTysM880BK/Un2FNfIDnjDbIq7sLynu+UFnFp BjSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=X6q/MRbAFAFtB483mpgrCV5jJyP32WJZt950gYxzILo=; b=rOffKh7qfwMz5+yusBEcL5UIuNqjDD3ssS90WRtBWsT+AelSPFFKI61KjhXbrPLAIO C+z/dUnLleat2fwiXOxWBcsZpyB6DqNt7GeWtNkjC/KB0jyzxebC9ISzADoAdR2mh/Ff zIcefv4MPelRh17VO2OhR3lpgkNTzODqrgGjYlY6JjuiMwTHhqAmRLmD48A+wCymS+WY dG/387OJm9oJogV/JrTzcbI0Wz48+QFDk+ytkTrPjpTupU7G8KtSaxk0jbu329dOgol0 rzEVeu/UYvpHY84kd49mrfEiRNnJX+m8DdWPnZqskaMzKSwqxqr6m9+ONYd9t05Xfi4O +qwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SRsnxb5i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k17si18193256oof.79.2021.10.19.08.51.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 08:51:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SRsnxb5i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51450 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcrOZ-0001Ax-SC for patch@linaro.org; Tue, 19 Oct 2021 11:51:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54244) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqyu-0004qn-Vv for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:49 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:45742) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcqyq-0007VR-1J for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:48 -0400 Received: by mail-pl1-x62d.google.com with SMTP id s1so12086156plg.12 for ; Tue, 19 Oct 2021 08:24:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X6q/MRbAFAFtB483mpgrCV5jJyP32WJZt950gYxzILo=; b=SRsnxb5iF0BSs6dxcmpsuQ+Wgm0j8uxsC1Ivfi49Z2KRo878yLfXm09AyujgCDmL3/ Cob0TBzpMmJ40vvAT4KaHi4v+8bp9HRYIqhD3QgbkyF1gA5+DKT3i2vzcyD2iJ8cuGFd /7rIiWRDz41DObS0XbQ0U1gCTph6YviHqRPbjcNM8yWo7+Gb2iCaUqvM/zsWPMC/Di1J q+QVbTpBr2lkX+qXlzs9KG2ZIR95sO91zgL35X4JMHL9i6wmhtgR7i4oRcfOVa/L2ZPt 4p8SEgK4BemjwdPJpXo7ZRBlN+oG9umHvRg0ieHsW/C3Aac8X6YfgjWWMrcIqkvAO3Dt TtuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X6q/MRbAFAFtB483mpgrCV5jJyP32WJZt950gYxzILo=; b=29e8UMdFzjB4dKwb+8kF6w3GwNadV0SO1xsxTSvPdFWLEvbWeZdC1N7L90w8tv/5T3 0KFkOlDeOEJbWLM4UOzhSa7Plbofsxz+eQiCF6j5/Ap//EWPrKjDeVR7NSodPlDysNPE 2+FtLfGYrE4euhcS+s1bt/KzF1pCFdKKRjxD2up1qfNht7nzytus0mNnj6/RKthXpc1w ILVUGa2rSYJ9BUNEq4UMr82d/Nm23PrVQcBNGiHPovt+PZgizOCICxmzDNjiflxymWBz OUym2MEab/o2Psmi2No/5c/cXKACd+30NGo15RbnYsMvbIuaotTxi6kyZMmiUKdbaIcO S3tw== X-Gm-Message-State: AOAM532foZKnxtFNC++BDNcPjSgOMdEqcwiwzeXvl7BTmo2TmTZMVDkg M9Qv/r9zuNqqMqeGaNCCplL/6hxEX8u+nA== X-Received: by 2002:a17:902:da83:b0:13f:704:d731 with SMTP id j3-20020a170902da8300b0013f0704d731mr33578161plx.77.1634657082588; Tue, 19 Oct 2021 08:24:42 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i2sm3293814pjt.19.2021.10.19.08.24.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 08:24:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 04/16] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Date: Tue, 19 Oct 2021 08:24:26 -0700 Message-Id: <20211019152438.269077-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019152438.269077-1-richard.henderson@linaro.org> References: <20211019152438.269077-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Shortly, the set of supported XL will not be just 32 and 64, and representing that properly using the enumeration will be imperative. Two places, booting and gdb, intentionally use misa_mxl_max to emphasize the use of the reset value of misa.mxl, and not the current cpu state. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 9 ++++++++- hw/riscv/boot.c | 2 +- semihosting/arm-compat-semi.c | 2 +- target/riscv/cpu.c | 24 ++++++++++++++---------- target/riscv/cpu_helper.c | 12 ++++++------ target/riscv/csr.c | 24 ++++++++++++------------ target/riscv/gdbstub.c | 2 +- target/riscv/monitor.c | 4 ++-- 8 files changed, 45 insertions(+), 34 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e708fcc168..d0e82135a9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -396,7 +396,14 @@ FIELD(TB_FLAGS, VILL, 8, 1) FIELD(TB_FLAGS, HLSX, 9, 1) FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2) -bool riscv_cpu_is_32bit(CPURISCVState *env); +#ifdef TARGET_RISCV32 +#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) +#else +static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) +{ + return env->misa_mxl; +} +#endif /* * A simplification for VLMAX diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 993bf89064..d1ffc7b56c 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -35,7 +35,7 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) { - return riscv_cpu_is_32bit(&harts->harts[0].env); + return harts->harts[0].env.misa_mxl_max == MXL_RV32; } target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index 01badea99c..37963becae 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -775,7 +775,7 @@ static inline bool is_64bit_semihosting(CPUArchState *env) #if defined(TARGET_ARM) return is_a64(env); #elif defined(TARGET_RISCV) - return !riscv_cpu_is_32bit(env); + return riscv_cpu_mxl(env) != MXL_RV32; #else #error un-handled architecture #endif diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fdf031a394..1857670a69 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -108,11 +108,6 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) } } -bool riscv_cpu_is_32bit(CPURISCVState *env) -{ - return env->misa_mxl == MXL_RV32; -} - static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) { env->misa_mxl_max = env->misa_mxl = mxl; @@ -249,7 +244,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", (target_ulong)(env->mstatus >> 32)); } @@ -372,10 +367,16 @@ static void riscv_cpu_reset(DeviceState *dev) static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) { RISCVCPU *cpu = RISCV_CPU(s); - if (riscv_cpu_is_32bit(&cpu->env)) { + + switch (riscv_cpu_mxl(&cpu->env)) { + case MXL_RV32: info->print_insn = print_insn_riscv32; - } else { + break; + case MXL_RV64: info->print_insn = print_insn_riscv64; + break; + default: + g_assert_not_reached(); } } @@ -631,10 +632,13 @@ static gchar *riscv_gdb_arch_name(CPUState *cs) RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; - if (riscv_cpu_is_32bit(env)) { + switch (riscv_cpu_mxl(env)) { + case MXL_RV32: return g_strdup("riscv:rv32"); - } else { + case MXL_RV64: return g_strdup("riscv:rv64"); + default: + g_assert_not_reached(); } } diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 14d1d3cb72..403f54171d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -152,7 +152,7 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { - uint64_t sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD; + uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD; uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | MSTATUS64_UXL | sd; @@ -447,7 +447,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, if (first_stage == true) { if (use_background) { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; vm = get_field(env->vsatp, SATP32_MODE); } else { @@ -455,7 +455,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, vm = get_field(env->vsatp, SATP64_MODE); } } else { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; vm = get_field(env->satp, SATP32_MODE); } else { @@ -465,7 +465,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, } widened = 0; } else { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; vm = get_field(env->hgatp, SATP32_MODE); } else { @@ -558,7 +558,7 @@ restart: } target_ulong pte; - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { pte = address_space_ldl(cs->as, pte_addr, attrs, &res); } else { pte = address_space_ldq(cs->as, pte_addr, attrs, &res); @@ -678,7 +678,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, int page_fault_exceptions, vm; uint64_t stap_mode; - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { stap_mode = SATP32_MODE; } else { stap_mode = SATP64_MODE; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d0c86a300d..9c0753bc8b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -95,7 +95,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; } - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { switch (csrno) { case CSR_CYCLEH: if (!get_field(env->hcounteren, COUNTEREN_CY) && @@ -130,7 +130,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) static RISCVException ctr32(CPURISCVState *env, int csrno) { - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { return RISCV_EXCP_ILLEGAL_INST; } @@ -145,7 +145,7 @@ static RISCVException any(CPURISCVState *env, int csrno) static RISCVException any32(CPURISCVState *env, int csrno) { - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { return RISCV_EXCP_ILLEGAL_INST; } @@ -180,7 +180,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno) static RISCVException hmode32(CPURISCVState *env, int csrno) { - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { if (riscv_cpu_virt_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; } else { @@ -486,7 +486,7 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, static int validate_vm(CPURISCVState *env, target_ulong vm) { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { return valid_vm_1_10_32[vm & 0xf]; } else { return valid_vm_1_10_64[vm & 0xf]; @@ -510,7 +510,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | MSTATUS_TW; - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { /* * RV32: MPV and GVA are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. @@ -522,7 +522,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | ((mstatus & MSTATUS_XS) == MSTATUS_XS); - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { mstatus = set_field(mstatus, MSTATUS32_SD, dirty); } else { mstatus = set_field(mstatus, MSTATUS64_SD, dirty); @@ -795,7 +795,7 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno, { target_ulong mask = (sstatus_v1_10_mask); - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { mask |= SSTATUS32_SD; } else { mask |= SSTATUS64_SD; @@ -1006,7 +1006,7 @@ static RISCVException write_satp(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { vm = validate_vm(env, get_field(val, SATP32_MODE)); mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); asid = (val ^ env->satp) & SATP32_ASID; @@ -1034,7 +1034,7 @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) { *val = env->hstatus; - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { /* We only support 64-bit VSXL */ *val = set_field(*val, HSTATUS_VSXL, 2); } @@ -1047,7 +1047,7 @@ static RISCVException write_hstatus(CPURISCVState *env, int csrno, target_ulong val) { env->hstatus = val; - if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) { + if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); } if (get_field(val, HSTATUS_VSBE) != 0) { @@ -1215,7 +1215,7 @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno, return RISCV_EXCP_ILLEGAL_INST; } - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); } else { env->htimedelta = val; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 5257df0217..23429179e2 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -161,7 +161,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) CPURISCVState *env = &cpu->env; GString *s = g_string_new(NULL); riscv_csr_predicate_fn predicate; - int bitsize = riscv_cpu_is_32bit(env) ? 32 : 64; + int bitsize = 16 << env->misa_mxl_max; int i; g_string_printf(s, ""); diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index f7e6ea72b3..7efb4b62c1 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -150,7 +150,7 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env) target_ulong last_size; int last_attr; - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; vm = get_field(env->satp, SATP32_MODE); } else { @@ -220,7 +220,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) return; } - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { if (!(env->satp & SATP32_MODE)) { monitor_printf(mon, "No translation or protection\n"); return; From patchwork Tue Oct 19 15:24:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515970 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp836966imp; Tue, 19 Oct 2021 09:37:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwy2tcKFJ0YHrnWirGsfMXu293xkW8pkJggiGwvfAvygqs3TEdBqNKrWf6qml7L/H/+Xu/5 X-Received: by 2002:a37:aec4:: with SMTP id x187mr866148qke.217.1634661438825; Tue, 19 Oct 2021 09:37:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634661438; cv=none; d=google.com; s=arc-20160816; b=mfHQ/ezWZ7DBOVkFucPp9ja+0E1xpVwpi4Bbwgkt1HIkqAfSkgj+vUX3FIXjRK5OPI rJMg5X/rYEytK/xpplxqieMWCf4D6Jvb5ComZm5YxQVdmRZkNF+WB1ZOLvKddv8LwRFy 9GZ6KwnNTCtusJ2s1SqR/I3JYWPZiHDq0Z/NDKsRMt+U9h4eFW2OnA1ZXQSQ4tV2fCl8 pGhjtqAjgGiGI1JNfjwLPV7tWyYJ6yNNIetJq7gAXbNXPrv8zCBPTiKC88TB5x6enRN5 LL63IXb0dZCYN+69BYKziWbTPwJ6KdjDFJXaCy2yN1v8hWt6GdSHWHyt4emwZgZ/lTc7 z6Vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JntjpE4dbZf2jEil4I0MzTIE4C49WVyfW1GrdUDx7w8=; b=f9/NIDZC60tTrr+n9EPANua8pySPKw1JNJsGjQOtCsgMeIF6XSwVt73pbgFQLzuFRA E3fb7Rz7YVRWivxFn2SlWQP94atIPkvKrxP1C+3RMjpx7eUbTEQXNz0SFt142ZkeR70D bpOMqP5PRqfOqmlCfAyy8kw23Eui8SpN7SpCeyLyLBFRU4DIh1n9vTKCdo+M7mFmtz6P xVvXvdPu6V3bHdFwyLXHIDbo027rthdn4XP+25fyPY7rsR7am5nybSfDRJ9iU/Lnf2T2 E3PEycneAnHAL17xfwgo3Fvmg/kfSlcH3sQH6q9iXNZPgkjsvYqsUES45Er3CPfc/rpz e4xw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OcCIzw7o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t3si16144368vsh.133.2021.10.19.09.37.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 09:37:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OcCIzw7o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60688 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcs74-0000St-4E for patch@linaro.org; Tue, 19 Oct 2021 12:37:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54388) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqyz-0004zr-0m for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:53 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:46764) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcqyq-0007Vo-Pe for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:52 -0400 Received: by mail-pl1-x62e.google.com with SMTP id 21so13879311plo.13 for ; Tue, 19 Oct 2021 08:24:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JntjpE4dbZf2jEil4I0MzTIE4C49WVyfW1GrdUDx7w8=; b=OcCIzw7oGYWY9GrAUfdi794NtZbx7jvaAYPsc45Qs1QDBGaoD1fyQqlP9/gXf5HMSU iiTBfOQVvJpH4nHUWfTqJVWxntK3r9hp7F0HuKWY79tEqGFGQzMn5GapZkOvdeoPUEQ5 Wjc54wRyOi8aVH827qbyXTJyII6Lrw2DX8vaKv45h0aHFfa86p788G7NfP/2QkATM1O5 GDhnfffLlCew/vEP3rcxipMbGdGhUC/yKnU7aO5k5C22t7yl5fgZeLTgrMDAzO3eyvlL mn5VR3nWG7qVA9orCZuG+by+BZLectcpN2LZhtRo3TxnovmCGWB2yudQIlfSO8sJqcci 1ZiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JntjpE4dbZf2jEil4I0MzTIE4C49WVyfW1GrdUDx7w8=; b=hv/257544Zjvzy4Y6UmEvf9H7cOwh6mXKjCFUkItc2ArJOsM2sHbRmAN1pnM2EW3LK gbrxraNqqwuLY88+l0r+0v4VPb+X+ICCrq84ftynswRs3MkJ2K6d0YZA3GsD7BzvuS0b QITTGUK9ugdE2qLEu4w3Zn1U2pQkQF86rN8cr1Ws0P9QfcyxoIr6lf8jZrVORpjx+Yps mSrYEGn0m2pbqo236RA+bUY2WdjCL+NN1awBpRVGDuHA0TZySbBExtLxP/5sYH9ujbwE jLMrxk6qvOLBMT5MyJPoUKzBB9suyM7ZfwciSCjQyK18ruZNqeaIwfhZWtb7neBBjGKZ fK0g== X-Gm-Message-State: AOAM533fPHLxGerSCgw3QKcLbp3aN5StPpR/+8iFw9nfaqPPETpz6tlG 5Xj3rPOLEO1qWu+mOYoijz7XDhjYsRgAkQ== X-Received: by 2002:a17:902:d488:b0:13f:165e:f491 with SMTP id c8-20020a170902d48800b0013f165ef491mr34260561plg.12.1634657083294; Tue, 19 Oct 2021 08:24:43 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i2sm3293814pjt.19.2021.10.19.08.24.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 08:24:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 05/16] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Date: Tue, 19 Oct 2021 08:24:27 -0700 Message-Id: <20211019152438.269077-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019152438.269077-1-richard.henderson@linaro.org> References: <20211019152438.269077-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Begin adding support for switching XLEN at runtime. Extract the effective XLEN from MISA and MSTATUS and store for use during translation. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 8 ++++++++ target/riscv/cpu_helper.c | 33 +++++++++++++++++++++++++++++++++ target/riscv/csr.c | 3 +++ target/riscv/translate.c | 2 +- 5 files changed, 47 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d0e82135a9..c24bc9a039 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -395,6 +395,8 @@ FIELD(TB_FLAGS, VILL, 8, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 9, 1) FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2) +/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ +FIELD(TB_FLAGS, XL, 12, 2) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1857670a69..4e1920d5f0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -355,6 +355,14 @@ static void riscv_cpu_reset(DeviceState *dev) env->misa_mxl = env->misa_mxl_max; env->priv = PRV_M; env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); + if (env->misa_mxl > MXL_RV32) { + /* + * The reset status of SXL/UXL is undefined, but mstatus is WARL + * and we must ensure that the value after init is valid for read. + */ + env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); + env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); + } env->mcause = 0; env->pc = env->resetvec; env->two_stage_lookup = false; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 403f54171d..429afd1f48 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -35,6 +35,37 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } +static RISCVMXL cpu_get_xl(CPURISCVState *env) +{ +#if defined(TARGET_RISCV32) + return MXL_RV32; +#elif defined(CONFIG_USER_ONLY) + return MXL_RV64; +#else + RISCVMXL xl = riscv_cpu_mxl(env); + + /* + * When emulating a 32-bit-only cpu, use RV32. + * When emulating a 64-bit cpu, and MXL has been reduced to RV32, + * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened + * back to RV64 for lower privs. + */ + if (xl != MXL_RV32) { + switch (env->priv) { + case PRV_M: + break; + case PRV_U: + xl = get_field(env->mstatus, MSTATUS64_UXL); + break; + default: /* PRV_S | PRV_H */ + xl = get_field(env->mstatus, MSTATUS64_SXL); + break; + } + } + return xl; +#endif +} + void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -78,6 +109,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, } #endif + flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env)); + *pflags = flags; } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9c0753bc8b..c4a479ddd2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -526,6 +526,9 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, mstatus = set_field(mstatus, MSTATUS32_SD, dirty); } else { mstatus = set_field(mstatus, MSTATUS64_SD, dirty); + /* SXL and UXL fields are for now read only */ + mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64); + mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64); } env->mstatus = mstatus; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 66857732e8..f7634c175a 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -514,7 +514,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #else ctx->virt_enabled = false; #endif - ctx->xl = env->misa_mxl; ctx->misa_ext = env->misa_ext; ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei; @@ -526,6 +525,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); + ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->cs = cs; ctx->w = false; ctx->ntemp = 0; From patchwork Tue Oct 19 15:24:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515965 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp812727imp; Tue, 19 Oct 2021 09:13:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz73Zf31/kholxZYDIYJdquC+r8irfaf/g0Qj/T+W5AN3vx/A4IBYAxgqtbJgnCqP4a/hED X-Received: by 2002:a05:6102:dc9:: with SMTP id e9mr35783863vst.21.1634660012460; Tue, 19 Oct 2021 09:13:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634660012; cv=none; d=google.com; s=arc-20160816; b=lvoRaKlN7YV5l7jsODbZSDlXRVwTff+zM7aL+tLUCKdfCMq3ePKk9NKPf0Wde3gL5d FeVCPYNtas2k6V2BzyZ4sZGtCgt5Mmoy6Z+L9ylSd6eOZFNFZ/LR4UAEvHAcigoIrYpK n4uxQ+4D5KTWIfadXMsiVOvHRVlVa4OAU5QbO9syCPcmyNyRiIHLcpflkzWYOdi29jc1 Gd6r2uCT1P5EifIgFcqSbJgHBn5KNphDJeOlBDkOcmxfAtmEySP4TN4Y0kz0k2EECogF Tz/2FO/a/RWk+v2/RWacytH6ycOfCnprZ7j476/NQV19Tb477gpp5ah3nkHhSiwnMUQb 5HVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bokkmTqu3PPB9lUNeGMuiR/uQoelWheprwGuLtvEEIw=; b=VpBV5RQDQLPbrPsDq+yHjR86MtOrMnYKUIcLXW4iBE8QWBiJH0iJsbkqpjbtE17hD6 x5CuPFol3Qm1zCyILbvpUEB7NAWmetToDvK/2FkALmhX//oCRk6+MV0nSigLkH/wCcTj YKHLidiKcz2UMmSE1PtoJiceoXPyFRTgi+cAvCGbZ1zRuQZNguGQGCUyZw4PSA6kwfSv IZlECFLu7clZFQR4QOsiCrQo2MbqE8ESbPWprX6kGmgeJhaPp7u7Q9epDWvlrOJ1wygn in2PKh4YA3FcnG3vuqbc1kJhBSr8Hl/Xsz6EN/07RxFNu+/I59BnUT638mQNaELC52Jo 6/zA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="LfPiU/J7"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c14si19223309uav.27.2021.10.19.09.13.32 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 09:13:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="LfPiU/J7"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55640 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcrk3-0000eC-RL for patch@linaro.org; Tue, 19 Oct 2021 12:13:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54300) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqyw-0004sK-E9 for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:50 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:42938) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcqyr-0007Wz-7l for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:50 -0400 Received: by mail-pl1-x633.google.com with SMTP id w17so2057652plg.9 for ; Tue, 19 Oct 2021 08:24:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bokkmTqu3PPB9lUNeGMuiR/uQoelWheprwGuLtvEEIw=; b=LfPiU/J7Rk9HLzqW/R6fqFFZXUAHkNXIgDrh+M1Q3XH4UXUOVSqQY91ffjiG4uFBFK i6U3ln/K1LPB4b+hn7wDGH+cHR4aTsA041sUpDK2icOr60qbac+pYsRlNHmajeUYYjWc oQIesK8NIxlv9us56t/rh/qnWwzxTWEXMc7pYMoKdPxSxZuh9CFnLuU8MB0rRPKAeKK7 WnmP1n4xEobWSUtO7vEybXeNXfv6lzz0be4WjWxdipoAwPvs0seehTcJLt8LazL+F24l p3YcbbNMGMY+rZdwxZ4bDl7yiJ9hr5iFMjJJJwQoggHXvxz6s1eneAuqtqmd7RsfjJvr vBgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bokkmTqu3PPB9lUNeGMuiR/uQoelWheprwGuLtvEEIw=; b=dN8uX6/nDA/55U8NOkK5FzxUXOrAZW3OY+QKVBoVU9+na9f6CxuehuHDtabeqmGuDR MgC+Yi872g7jkaHksIIFPd0mPJQFm3k2bXkwzlrwWSbHkSbF+2yxSr58cs+w3wGghU/V SBCAOtLXW3rzzcDlrVKphYWJF22OJA/a+g3GvwEJXk4N8u9WwqpSUuMIgs3fkymu2JHp aZq9LFHtqn8SOKWMJS4SnEHhDPDpkfF4TLgdhZ6yClfqqZ6r7WMYwkeOD1liIVNvrbeN ZjyzAl2bpYz3Bl0VTObHMEAfSB0EQsFsxosrCSPoN8Ss6XtQAKRwE7ZehY31aN126iPQ KmQQ== X-Gm-Message-State: AOAM530kammNxzgOZpJeLAFG0Q65vssiCFCMqNYAuq6EI5R4Wue/8wTq X8vxnXB2kDDGpl6s7IQffXPvAhWOYzcnzg== X-Received: by 2002:a17:902:9a43:b0:13f:8f31:101c with SMTP id x3-20020a1709029a4300b0013f8f31101cmr26763502plv.76.1634657083903; Tue, 19 Oct 2021 08:24:43 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i2sm3293814pjt.19.2021.10.19.08.24.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 08:24:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 06/16] target/riscv: Use REQUIRE_64BIT in amo_check64 Date: Tue, 19 Oct 2021 08:24:28 -0700 Message-Id: <20211019152438.269077-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019152438.269077-1-richard.henderson@linaro.org> References: <20211019152438.269077-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the same REQUIRE_64BIT check that we use elsewhere, rather than open-coding the use of is_32bit. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 081a5ca34d..d60279b295 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -743,7 +743,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a) static bool amo_check64(DisasContext *s, arg_rwdvm* a) { - return !is_32bit(s) && amo_check(s, a); + REQUIRE_64BIT(s); + return amo_check(s, a); } GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check) From patchwork Tue Oct 19 15:24:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515971 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp838961imp; Tue, 19 Oct 2021 09:39:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzO2myaYRsZTmuffk92E9vYArx7oTXYgebPVZHbgdJVAI5Gjwv4GSEY1O179woF+nZsAizS X-Received: by 2002:a05:6102:358e:: with SMTP id h14mr24929292vsu.0.1634661572631; Tue, 19 Oct 2021 09:39:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634661572; cv=none; d=google.com; s=arc-20160816; b=IqYJjAtevaOUlKH6gi9kw5C48DmNZ8e7UkME9iijMlqylsBgmVLY2ThBycVNeK7t98 Jsz5/XunmdbDGdfiny8WkZl0SHqsguCLx3PaXEgvEzSZXrCzcLDJZ3OW030497ZgKK+d Mh9fL1rIx2+IyB9FwD1HqPV8UlZlOUsLXjxCITuHVGXZw1+7bWeOb4Vm9OdBzn2LxErE azx71oQpeeRMz2rg8i6ml9CmlIproze3MV3zv8iS5qrbObhYWMOQDIJiOsJInvfr4qKV PekdJKZe/R5v1+n8PTBUrsqqujj46cmYHtKKEDPM997/b1OTfPhNJrzHMxVesfjw2q0I tC+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mfu2QZ3gpRQ8C8fsN7554x8wxijvHESDqJdXEHq27p8=; b=IJmB55FhqDhePUGvpSLuQLT7NPd0P5onYfJNIh5Wg++PHvjADNWmovvG7ok+dSJtXd ka663RF18RA82hY0L/PbRDoGjoHP+1Lcxb8ivzP+oqbOngSBBbHjC3s8LZNPu+IQ/XO3 BcIWY7dqMXlZ+6u647VRccp+giAa3XHZ/R7i0Rmx8tZnlA+L65tcbeV/YCalZhryOImC z+wEE6+Fl0HKDwe/VurDPY4BzOe7OhajtBG7jzyBI5gRS7W3ZZHWIGZhMkfd3V/0+5v0 VHNW9vQg+g2ZmM7jdbuHhobwa3tvSx/9jc/H8RNgYTo0XFahrQ0XmgmVuS4l85EZHwwa KWFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a1YR+2BJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c17si13288526uam.103.2021.10.19.09.39.32 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 09:39:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a1YR+2BJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39054 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcs9E-0004qj-2Q for patch@linaro.org; Tue, 19 Oct 2021 12:39:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54428) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqz0-00055V-KX for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:54 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:45746) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcqyr-0007XG-SL for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:54 -0400 Received: by mail-pl1-x631.google.com with SMTP id s1so12086210plg.12 for ; Tue, 19 Oct 2021 08:24:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mfu2QZ3gpRQ8C8fsN7554x8wxijvHESDqJdXEHq27p8=; b=a1YR+2BJtRX9o6BMOYcBV+wrw+PCXiamdbTRbPfuwMVFaTTxWYGRUp1aYeXqPs2IjY 4lKPGb+2/jDEU84sSnPK/a4Dls38eD8gECwRsVKeYMwYD4e686/NUtn4dGVLm1dApfIM p4jqWHtXP+kbj43Dwf2xc6aOgi7vAt7h+DJ+Sour9uCsmGJmKH2hyDdwAD699XRFH6XI IAMGIAIpDruqbHMVtMNt8zd0624C4FMq5WPnhSc0jDA4sNRNVzfWJDRv8as1S/eA19Ta XRlXsFwVyMG0VSxCRgtz8NBwRHJwaycMxjPKetQxZtgDhpAoV1nzMZ4z0FqBWAEg9ek8 9Kjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mfu2QZ3gpRQ8C8fsN7554x8wxijvHESDqJdXEHq27p8=; b=rSXL2Q4hEL3LH7Mc2X4hohV+tpAkyPstHxheJP88C7UyWqcSqaDgKuIUCTwGvPfBRY gBNCDbtolf8a7yXUPdMVtxk5S8ceTmRxFpBvYZ7B00loOMizc3V1i5lyMpdJVsM4OXAD eR0PMSQ6EQYn/cuWmzwNT4jSyeQR6wvmMvO2ysVxKTVCg5Pv9hSB92iTB0ZdGTnmdo1o kp1ROhqqYORApTzho3Voc7QIhnjVcXsOfaKtzIwBsmZ6cqAxNP38CIfsZtN1kyr4uFCq 9C2xIuWdqWho6u8QjzSIglk9W/VqIOa1DmiKM4CwHkY6H6y77KH2iHNH/xT7EtZMIxjP jG+g== X-Gm-Message-State: AOAM532pdS578aBE4OzqiQMUBf7ysZ1LKtBQK6E5e0gRX8AJw+sFBWi+ XZRgClKA9IT1ItGZ+zSoNtkjLVG+PL335g== X-Received: by 2002:a17:90b:1283:: with SMTP id fw3mr589113pjb.99.1634657084471; Tue, 19 Oct 2021 08:24:44 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i2sm3293814pjt.19.2021.10.19.08.24.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 08:24:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 07/16] target/riscv: Properly check SEW in amo_op Date: Tue, 19 Oct 2021 08:24:29 -0700 Message-Id: <20211019152438.269077-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019152438.269077-1-richard.henderson@linaro.org> References: <20211019152438.269077-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We're currently assuming SEW <= 3, and the "else" from the SEW == 3 must be less. Use a switch and explicitly bound both SEW and SEQ for all cases. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 26 +++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index d60279b295..d16446d3bb 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -704,18 +704,20 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq) gen_helper_exit_atomic(cpu_env); s->base.is_jmp = DISAS_NORETURN; return true; - } else { - if (s->sew == 3) { - if (!is_32bit(s)) { - fn = fnsd[seq]; - } else { - /* Check done in amo_check(). */ - g_assert_not_reached(); - } - } else { - assert(seq < ARRAY_SIZE(fnsw)); - fn = fnsw[seq]; - } + } + + switch (s->sew) { + case 0 ... 2: + assert(seq < ARRAY_SIZE(fnsw)); + fn = fnsw[seq]; + break; + case 3: + /* XLEN check done in amo_check(). */ + assert(seq < ARRAY_SIZE(fnsd)); + fn = fnsd[seq]; + break; + default: + g_assert_not_reached(); } data = FIELD_DP32(data, VDATA, MLEN, s->mlen); From patchwork Tue Oct 19 15:24:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515962 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp793786imp; Tue, 19 Oct 2021 08:54:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyfZOjwV/t7bPbELzJyfFEPslQxlnvpSG+yhNxRht9aG1d88wGi7Z03ko9n0cSC1TnWZvKj X-Received: by 2002:a05:6102:304e:: with SMTP id w14mr24187241vsa.52.1634658872478; Tue, 19 Oct 2021 08:54:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634658872; cv=none; d=google.com; s=arc-20160816; b=ll+dcCnqYYidcQO+f8TD9KkWXqiXJDVZkZiwv1L0gkmesNPoqcvqaDipN1fLYWNBP1 t/yOY0tlFwPRvoiLFTVOrfx9NjTNZOEt+hk5awEUwZ++XZoHbMqDko9Ot8WdKwAMzImU n1ks8CgdTlEERVXLHyPcPw3oU68G441QJ1wSPfEq+JIvbyzvBVrozYmFjP6Vi9Ul7i7e lQxlHXHPWKFlfHSzE5iJzRdE0IqkkGDwz3Z/7aLBEyGaMUjHQyvksMFAC4IryCYb4acl Qbh5xBOZQ8c3cp7/3hZYuMSdfv6eHgV947vh+sg7fGiPIxUapNcbpEcXhpZpaPjhzFNZ JDgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=edH/POVbw08zofw7DVs7aX5K2Qy9VoOU3+jO1Dt/KD8=; b=j7Pnm201+k1ejBARpgS6HHyig0p2JvkuuzU/R/CvTXS8lFQUMJ1/D7tMLWZVn4Vyki dIHktzsF9lwdEgQV4ghB44PbsR78IXXi9AsooTMjccjZAfz7cnsXJE52L/rOLo6hQ37v AXK4tp8I6d/lXSSiUfDv/L0bqv6D7RwU8zWDllDQ+YKhWhvFz3MTC0Zbx4c+zU9TMv8/ cEffYFVXVpvHKW+W2ZSeldaOsUP4c+ZtKeVcUvnORh/KwBRaoZ/DZPAAuTApnWmXGJug fTIEgbWJI/VUIAfLMKCXdR1KgYgvSGatj59/sn5hjEtsJxc6ZjF5M+mi5FbM7VwQMNi0 snsw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WDn2ev7F; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f29si6743466vsj.346.2021.10.19.08.54.32 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 08:54:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WDn2ev7F; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:32970 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcrRf-0007wf-OF for patch@linaro.org; Tue, 19 Oct 2021 11:54:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54392) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqyz-00050x-B9 for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:53 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:42940) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcqys-0007YF-MD for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:53 -0400 Received: by mail-pl1-x635.google.com with SMTP id w17so2057695plg.9 for ; Tue, 19 Oct 2021 08:24:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=edH/POVbw08zofw7DVs7aX5K2Qy9VoOU3+jO1Dt/KD8=; b=WDn2ev7F8Y+8lBeRgNTY4J3JqABh1A4rHd9wV5zuPgz2ye5a4mAOq6jnE8XbQZEgPc 2c19grunndK0SMTrpswRNUo6CQNZanENPPpakHIgZzGrKlulsTum/S/1I3UAEUGyzC/u hplB+rdkPwrtgNzjU9eSWVZQ0kXOh7FnubsHDIb18wTBJ6TN9swlMUx9jjo10nlM6Aov KF4eau/jDSmZoxV7FrCpBUvjZ4UcvIVEgfHewajDm3bOACQpQtQauMNevA35034E5JRI 2xjHVI2QX81J0HF66QcVQBPAczf5KLOdzXWaIG8a69M5daH685dlfEi08hX9XC+NILzW H7HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=edH/POVbw08zofw7DVs7aX5K2Qy9VoOU3+jO1Dt/KD8=; b=HLaTueQu3Xa2aTW5LR/4tW9VANVvvST4kEBW29j6t4XtOBNzVz8s2qrLKOKuwcyjzD +aiTh31NdnXClEI2qmlmZTlfInMoxq4Eb0MjluwoSG3/uvQXOczKkZIFCXPDmDHbSN67 ufSQoCqdYv62guxKJJIQf0DZH9O9qinlugqSZY3Rmk62LES45OBzvd6RrzHfL/dTAN7W 8cfOQYuh1O8rr8Us54xYLgy9lWMJZufRIxWHXPfHymrIEZ8pkEN6zNpVxXzo5ic8DHdK 4gbwGEnQ1280qrfOoQxHJ347rXpqLGCexhUUxbcDrNdyoiS4uV1Z+yjRhHHZ1OjVv7H9 JWwQ== X-Gm-Message-State: AOAM530JkrqRQwRMG8WOP0XFyeUICuTbt2m3mRq3HnMtx0T0q60PW8r7 UINuM3/WznyK4C/2XEYNjanshLrSSfjobw== X-Received: by 2002:a17:90a:530f:: with SMTP id x15mr495525pjh.156.1634657085224; Tue, 19 Oct 2021 08:24:45 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i2sm3293814pjt.19.2021.10.19.08.24.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 08:24:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 08/16] target/riscv: Replace is_32bit with get_xl/get_xlen Date: Tue, 19 Oct 2021 08:24:30 -0700 Message-Id: <20211019152438.269077-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019152438.269077-1-richard.henderson@linaro.org> References: <20211019152438.269077-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for RV128, replace a simple predicate with a more versatile test. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f7634c175a..3f1abbac5c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -91,16 +91,19 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) } #ifdef TARGET_RISCV32 -# define is_32bit(ctx) true +#define get_xl(ctx) MXL_RV32 #elif defined(CONFIG_USER_ONLY) -# define is_32bit(ctx) false +#define get_xl(ctx) MXL_RV64 #else -static inline bool is_32bit(DisasContext *ctx) -{ - return ctx->xl == MXL_RV32; -} +#define get_xl(ctx) ((ctx)->xl) #endif +/* The word size for this machine mode. */ +static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) +{ + return 16 << get_xl(ctx); +} + /* The word size for this operation. */ static inline int oper_len(DisasContext *ctx) { @@ -257,7 +260,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) static void mark_fs_dirty(DisasContext *ctx) { TCGv tmp; - target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD; + target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD; if (ctx->mstatus_fs != MSTATUS_FS) { /* Remember the state change for the rest of the TB. */ @@ -316,16 +319,16 @@ EX_SH(12) } \ } while (0) -#define REQUIRE_32BIT(ctx) do { \ - if (!is_32bit(ctx)) { \ - return false; \ - } \ +#define REQUIRE_32BIT(ctx) do { \ + if (get_xl(ctx) != MXL_RV32) { \ + return false; \ + } \ } while (0) -#define REQUIRE_64BIT(ctx) do { \ - if (is_32bit(ctx)) { \ - return false; \ - } \ +#define REQUIRE_64BIT(ctx) do { \ + if (get_xl(ctx) < MXL_RV64) { \ + return false; \ + } \ } while (0) static int ex_rvc_register(DisasContext *ctx, int reg) From patchwork Tue Oct 19 15:24:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515972 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp841677imp; Tue, 19 Oct 2021 09:42:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyGUxup2//V0nhPr9mFJ+SqKzR7kwM73KEl0cU+qxP23l1YGEGhRH2fmob9DpgTp5Ka1TY1 X-Received: by 2002:ab0:5b03:: with SMTP id u3mr1026404uae.41.1634661743272; Tue, 19 Oct 2021 09:42:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634661743; cv=none; d=google.com; s=arc-20160816; b=CjB5JYOyO+0SFUevsfhsThCZOxaV+Rg5Vf7Cq0KVgnQssxB50NRnWOSTd1RO6Yu+mv knYEIb0n+EiMR8BSV2FeqXYA34CO0vOEal6BnTdWNcPygEAFB/Qgrv6Wb2BGR7OeOSSe cXkaBp436q6Z7m6uwqQC5RUe/pwcm8oscc4tPoojjusNqSU189l/r8CZsmZr05FJjoTk zkHHGbFRtT0iSMQkyk0dwv/nCJi5YDlR0H/XdZtM9eBGgV2CYEolvsO2LDNyhMyT9oHv 52pGWXt17yq1qJozULgIDY2Y39PxWgp5wUG/cTVoIwuv5AjdP5+y35RsrKjfAgUdeEyP M0iA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8Q91x8zMEJ+G0plQF7JCwHlzBwbIDPGXFt0sB6UJCPI=; b=c8UzCkIDZ3Arvz+qpDKrUPGfbgtpkNdZxGOOA5aGRXy7fUlK65adIQjYS37NtqourK R50KolGxOt/9e0KaO2bq3sLEEfDIl7+gUxour4uNx5XXPyzIEwQS7YZbWOlxc03qeRVB rIUp1/d6/A/oLK7j+PTVvY+FinSoTlmx7+OeGfOm3s/X686miyYhpZx62KYWndhK7fVr yCj1U/KNdkWOB4+eErFdNJOLx8K635GRFrg1xZmW3Vc3Zmee2jWlntLB8DvDlJfB6f2O AD61W+VEdF+YnW10yWvZSyXyH7eVrN6T5TY9C4Ba+tcbyAUWa97lKNXdPsvp//XYYtTq FdQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=qiwQhWLS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c8si446860vsl.8.2021.10.19.09.42.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 09:42:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=qiwQhWLS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45644 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcsBy-0000mF-JA for patch@linaro.org; Tue, 19 Oct 2021 12:42:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54432) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqz0-00056W-UE for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:55 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:42929) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcqyu-0007ZA-0a for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:54 -0400 Received: by mail-pl1-x629.google.com with SMTP id w17so2057727plg.9 for ; Tue, 19 Oct 2021 08:24:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8Q91x8zMEJ+G0plQF7JCwHlzBwbIDPGXFt0sB6UJCPI=; b=qiwQhWLSvOBOi/WrTa/s7KEx3HVtjYC6/AsiOjMCEQuUaVHJKDYDb9HtHkwPtt1sJY HYngV6+tpCfEpyUtwq2nakYnNSLi5zkNbDzShXFXKpfLsgZbx0el1RhzXmX8VXrxNtS2 R2B61xlPXDi/zD2UvgKM0zssu2NhGVlNbeBI+mlQrxg4UbvSa3WB1uKUZXp82iE07muU QISyGbw0+jEoCoiPFeji1NdozQ0r/v3CwHuZsmOS2eWsOcVSAQaqMPZoYu9bpWytBDjb 6ufYxXvdHjyTBvNGIJwAdwlnqe/gF6/LolwyJGdYk7EZNIi+5M7J2ZngoC2T9LjnGXNH s0Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8Q91x8zMEJ+G0plQF7JCwHlzBwbIDPGXFt0sB6UJCPI=; b=gyP1SBG+lGe/RcaZq/mPQLYiE8p3/2AzqpriFE/9XBq3rBVFYqProx0nYQVBjtA9so 2krLgnuKCHjlju0xTKHqp6vGygGrNgP5jeEQghBLms3JLYNZ3MP7+t+WqFw1c0e6nyIz rRQw783alERXHq5HF2Xj1+utbJ1cXWSXMmVzvOApR3yjPt5twh57b8Wf8LCin2iAk/xx +8hBsUoFuUdKhBqxEDTeKw8taxflTcTJK+tXAUI/BUKq6UFDrRepOMpPBgdulMFK51Ib uEOmvaQmHrid8wh98VElQ2UYWGA51REtmhEUeNRmsxI0rLCwohZiNEx74BNKpO0IEpyd Htmg== X-Gm-Message-State: AOAM533LP64ftf1+nm+4O0DsDo8jbrUsrD7gM5wItBo2kjvymlIVXrTu zB/5CzRHLguTmqSdr0l5ml/IuUoH7HA= X-Received: by 2002:a17:90b:4c0f:: with SMTP id na15mr499559pjb.200.1634657086095; Tue, 19 Oct 2021 08:24:46 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i2sm3293814pjt.19.2021.10.19.08.24.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 08:24:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol Date: Tue, 19 Oct 2021 08:24:31 -0700 Message-Id: <20211019152438.269077-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019152438.269077-1-richard.henderson@linaro.org> References: <20211019152438.269077-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for RV128, consider more than just "w" for operand size modification. This will be used for the "d" insns from RV128 as well. Rename oper_len to get_olen to better match get_xlen. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 71 ++++++++++++++++--------- target/riscv/insn_trans/trans_rvb.c.inc | 8 +-- target/riscv/insn_trans/trans_rvi.c.inc | 18 +++---- target/riscv/insn_trans/trans_rvm.c.inc | 10 ++-- 4 files changed, 63 insertions(+), 44 deletions(-) -- 2.25.1 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3f1abbac5c..6ed925c003 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -67,7 +67,7 @@ typedef struct DisasContext { to any system register, which includes CSR_FRM, so we do not have to reset this known value. */ int frm; - bool w; + RISCVMXL ol; bool virt_enabled; bool ext_ifencei; bool hlsx; @@ -104,12 +104,17 @@ static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) return 16 << get_xl(ctx); } -/* The word size for this operation. */ -static inline int oper_len(DisasContext *ctx) -{ - return ctx->w ? 32 : TARGET_LONG_BITS; -} +/* The operation length, as opposed to the xlen. */ +#ifdef TARGET_RISCV32 +#define get_ol(ctx) MXL_RV32 +#else +#define get_ol(ctx) ((ctx)->ol) +#endif +static inline int get_olen(DisasContext *ctx) +{ + return 16 << get_ol(ctx); +} /* * RISC-V requires NaN-boxing of narrower width floating point values. @@ -197,24 +202,34 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) return ctx->zero; } - switch (ctx->w ? ext : EXT_NONE) { - case EXT_NONE: - return cpu_gpr[reg_num]; - case EXT_SIGN: - t = temp_new(ctx); - tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); - return t; - case EXT_ZERO: - t = temp_new(ctx); - tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); - return t; + switch (get_ol(ctx)) { + case MXL_RV32: + switch (ext) { + case EXT_NONE: + break; + case EXT_SIGN: + t = temp_new(ctx); + tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); + return t; + case EXT_ZERO: + t = temp_new(ctx); + tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); + return t; + default: + g_assert_not_reached(); + } + break; + case MXL_RV64: + break; + default: + g_assert_not_reached(); } - g_assert_not_reached(); + return cpu_gpr[reg_num]; } static TCGv dest_gpr(DisasContext *ctx, int reg_num) { - if (reg_num == 0 || ctx->w) { + if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { return temp_new(ctx); } return cpu_gpr[reg_num]; @@ -223,10 +238,15 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num) static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) { if (reg_num != 0) { - if (ctx->w) { + switch (get_ol(ctx)) { + case MXL_RV32: tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); - } else { + break; + case MXL_RV64: tcg_gen_mov_tl(cpu_gpr[reg_num], t); + break; + default: + g_assert_not_reached(); } } } @@ -387,7 +407,7 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, target_long)) { TCGv dest, src1; - int max_len = oper_len(ctx); + int max_len = get_olen(ctx); if (a->shamt >= max_len) { return false; @@ -406,7 +426,7 @@ static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, TCGv)) { TCGv dest, src1, src2; - int max_len = oper_len(ctx); + int max_len = get_olen(ctx); if (a->shamt >= max_len) { return false; @@ -430,7 +450,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); TCGv ext2 = tcg_temp_new(); - tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1); + tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1); func(dest, src1, ext2); gen_set_gpr(ctx, a->rd, dest); @@ -530,7 +550,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->cs = cs; - ctx->w = false; ctx->ntemp = 0; memset(ctx->temp, 0, sizeof(ctx->temp)); @@ -554,9 +573,9 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) CPURISCVState *env = cpu->env_ptr; uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); + ctx->ol = ctx->xl; decode_opc(env, ctx, opcode16); ctx->base.pc_next = ctx->pc_succ_insn; - ctx->w = false; for (int i = ctx->ntemp - 1; i >= 0; --i) { tcg_temp_free(ctx->temp[i]); diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 185c3e9a60..66dd51de49 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -341,7 +341,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl); } @@ -367,7 +367,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_NONE, gen_rorw); } @@ -375,7 +375,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw); } @@ -401,7 +401,7 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_NONE, gen_rolw); } diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index a6a57c94bb..9cf0383cfb 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -331,14 +331,14 @@ static bool trans_and(DisasContext *ctx, arg_and *a) static bool trans_addiw(DisasContext *ctx, arg_addiw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl); } static bool trans_slliw(DisasContext *ctx, arg_slliw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); } @@ -350,7 +350,7 @@ static void gen_srliw(TCGv dst, TCGv src, target_long shamt) static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw); } @@ -362,42 +362,42 @@ static void gen_sraiw(TCGv dst, TCGv src, target_long shamt) static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw); } static bool trans_addw(DisasContext *ctx, arg_addw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl); } static bool trans_subw(DisasContext *ctx, arg_subw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl); } static bool trans_sllw(DisasContext *ctx, arg_sllw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl); } static bool trans_srlw(DisasContext *ctx, arg_srlw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl); } static bool trans_sraw(DisasContext *ctx, arg_sraw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl); } diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc index b89a85ad3a..9a1fe3c799 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -214,7 +214,7 @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl); } @@ -222,7 +222,7 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_SIGN, gen_div); } @@ -230,7 +230,7 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_ZERO, gen_divu); } @@ -238,7 +238,7 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_SIGN, gen_rem); } @@ -246,6 +246,6 @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_ZERO, gen_remu); } From patchwork Tue Oct 19 15:24:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515968 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp830913imp; Tue, 19 Oct 2021 09:31:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwFKBaXywDjb7rDMEkigcNR43UuAg5LPSbdxaUH457sl4U4hTYp/2UU8VSyAr+UCLJYjpCR X-Received: by 2002:a4a:4ac5:: with SMTP id k188mr5431898oob.23.1634661090896; Tue, 19 Oct 2021 09:31:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634661090; cv=none; d=google.com; s=arc-20160816; b=BmivJ7x4IPo6fQ04aEhthnbME0JxWMciwgNO3YFkdDHseR4lTlFVdLVfjg/Cj0FKJH u2VEjm1owQczEUU/8ZP1yFOqUq/9winLM6g31EEH2qa7vJl2tURpNRRfFR21NCJOzUdF ulNPx0eIw3JSG4qEjS0MYGxTzumXz0giPNPDi0R31V5PPkV3BXp76UZLS+Jjldax4B1d Z+3Y3h2K93CBUugXvuRca8PZgbydsHT+5ePSs33qb66fyxf91P0U+MBkE+qDFIAkSIHF X7y2ocVomubIr6HvpBFvDHwOX1M3Uq6vNx0o+Pzg/aGrH303Iu4n9XpzGzy5rPYvORGU ioog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=70ix3AhGljp8w7VYIEJb5B8tKM59m/WakgkEPwbsgro=; b=TwYVXw2yeqQa4PL+z+8LFB2DU3pHKiLC7vXx0kOMGupfLjWa8Snkph2JK4ZtfsZvpY ubBzVgNX4fUqKJdtvhlqCqemb30k7bHtMHyfPKj2u2t4218eNpcWEkCbwjwlhGLLX4Ax 2ieOlfhfXINhWYdvVGYluYsA0oSThczkVVTdeuc4PRSOHnUDDAZrCM/Q2LPNEQ3tXJ24 Ku45taDZkGSIIWYTRpfUWG11JOvWEkR4na0zi8oXTNjmkx0eqpbHbWVl3icyoy7e6P0V +j494PQ3TfqtUhIE41V7si8tLdOZCohffOHMAxxCVLvT5k7P50zQ0Qo6BEFRoroTc0Pi Tjag== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UiZazeEm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v17si18759109oov.29.2021.10.19.09.31.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 09:31:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UiZazeEm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44586 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcs1Q-0006OX-VO for patch@linaro.org; Tue, 19 Oct 2021 12:31:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54462) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqz2-0005CI-A4 for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:56 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:45749) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcqyu-0007Ze-6j for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:55 -0400 Received: by mail-pl1-x634.google.com with SMTP id s1so12086287plg.12 for ; Tue, 19 Oct 2021 08:24:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=70ix3AhGljp8w7VYIEJb5B8tKM59m/WakgkEPwbsgro=; b=UiZazeEmfmFIwl/fnVf2oVa9qmGGbUcPmAvLbJ8aFZ8HnmGHVEmelARF5uE6yMS3U/ VCcHh9zUoRDXDCWwVV6kX+gBg/a+7iX9k5/GLzuSJX/fesMbxgN3bTmLbzdezLRXWqNI 8QQfHq7ra/I0Y+z3Sci/Esdnlei4aLkeX5Q3/vAMFMfjQeeLSj9sM4Z9XK6kVu3wPIX7 5x9BKfG6942D/krghcWaUT4oM5d6yITyTyQXSjFCcSdlv2x8AXwQ9kikaCruILe0sF6Q +SO8FZX5NKAtA/TTR2iJvnomv5lcl5vOh5weJLDsE1C9yMFkVlmUNsHUffOLKp9bo5yr ZbSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=70ix3AhGljp8w7VYIEJb5B8tKM59m/WakgkEPwbsgro=; b=6K3becVLMQNTCI8Sk7kD+PZPfgIjAcJ3f7en445POF6Uvn5snhcOqLX3GjFijb9ayn Ew5MBzRGnxkTqqjpR6x/LluuZvomeuXt9Detz0Rd3O+aQ1UQbK96oATS2GgnVszcwUfu cvKs6b5Wv+/YWw4M8BBalWauHq6chddcp+Q9moFjGcimCatjApa1MiznfBk4XmyOEi6E LMPkmeqXEMJkwXJ3kCHdOgLZ6xMleAVno72pZV5woL8cBn1CGHcXXEdgL83yUtH84raU UBc65zbhwPknh3aXvB2iWhu90vjAcYl8zfOC6wPvzV1YRVnbuldhfwdyYiWE25HPcZsD kIzg== X-Gm-Message-State: AOAM532rBXI2uDI7xr86CgquMua/lQSKy+D7aJawMmd6EwCdvYpW6Fy/ oXyqd29avSXpr7NKyfJ2UQZje+WlO+idUQ== X-Received: by 2002:a17:902:ed94:b0:138:ca3a:425d with SMTP id e20-20020a170902ed9400b00138ca3a425dmr34238412plj.78.1634657086679; Tue, 19 Oct 2021 08:24:46 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i2sm3293814pjt.19.2021.10.19.08.24.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 08:24:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 10/16] target/riscv: Use gen_arith_per_ol for RVM Date: Tue, 19 Oct 2021 08:24:32 -0700 Message-Id: <20211019152438.269077-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019152438.269077-1-richard.henderson@linaro.org> References: <20211019152438.269077-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The multiply high-part instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 16 +++++++++++++++ target/riscv/insn_trans/trans_rvm.c.inc | 26 ++++++++++++++++++++++--- 2 files changed, 39 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6ed925c003..5d54570cc9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -403,6 +403,22 @@ static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, return true; } +static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, + void (*f_tl)(TCGv, TCGv, TCGv), + void (*f_32)(TCGv, TCGv, TCGv)) +{ + int olen = get_olen(ctx); + + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_arith(ctx, a, ext, f_tl); +} + static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, target_long)) { diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc index 9a1fe3c799..2af0e5c139 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -33,10 +33,16 @@ static void gen_mulh(TCGv ret, TCGv s1, TCGv s2) tcg_temp_free(discard); } +static void gen_mulh_w(TCGv ret, TCGv s1, TCGv s2) +{ + tcg_gen_mul_tl(ret, s1, s2); + tcg_gen_sari_tl(ret, ret, 32); +} + static bool trans_mulh(DisasContext *ctx, arg_mulh *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_NONE, gen_mulh); + return gen_arith_per_ol(ctx, a, EXT_SIGN, gen_mulh, gen_mulh_w); } static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) @@ -54,10 +60,23 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(rh); } +static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + + tcg_gen_ext32s_tl(t1, arg1); + tcg_gen_ext32u_tl(t2, arg2); + tcg_gen_mul_tl(ret, t1, t2); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_gen_sari_tl(ret, ret, 32); +} + static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_NONE, gen_mulhsu); + return gen_arith_per_ol(ctx, a, EXT_NONE, gen_mulhsu, gen_mulhsu_w); } static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2) @@ -71,7 +90,8 @@ static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2) static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_NONE, gen_mulhu); + /* gen_mulh_w works for either sign as input. */ + return gen_arith_per_ol(ctx, a, EXT_ZERO, gen_mulhu, gen_mulh_w); } static void gen_div(TCGv ret, TCGv source1, TCGv source2) From patchwork Tue Oct 19 15:24:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515973 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp843742imp; Tue, 19 Oct 2021 09:44:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyt+H0a3nT3DVIEd6k6Hz4C6z4e0MLfY9e51hCmP05reBGV2TYGgG222B4op5F/kTf3SvPm X-Received: by 2002:a9d:6159:: with SMTP id c25mr6114533otk.286.1634661868748; Tue, 19 Oct 2021 09:44:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634661868; cv=none; d=google.com; s=arc-20160816; b=WGS4AVZ5fMFaxdvSNcpdmkFk5/6BPU20coVgo3P0DTYTMwsKKxx8IOjxoRzT36mcUs 7gCFeBtiiML1Dra5TXltgTFKXKs438AKXqsnJrz47mVQLAHG7YC3qNvyk6EzJh0b9gvb CSQ50BcSJ+HTnyfa/6lTbo5aJXi0HQRWN+rYo2v0PKxQN9BO8ovxb1ONc+BHazqPGofC vw00aypcYsZ6Qpx0L6IgCJCrU1pwBfnVZRAg+xDWOJdD+GmvHcfJXQPH1J7WKJyNed2n tVWTTNF3satK8rst1iKnYzidUB1R1UPrKvalzgmRXc+6HP6bQDDQOeh/Sw6ZduatoXZq xKHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VHU6Zq495CGWvucF4SFdns/LDCGAVtayMjBnfRKFC6c=; b=TzIGIxxy5pxR6XaDDf+2WGUufgw6gT5cfTBOZ1pK21lHiWnGT+gTbyeXqDI/6b/fSz w2v1DBSrxyvQUtf324dsw9fYygFefcmX6xlbF9LXKMSj4UG2vNXH94ru8dN9ga4yUOnm xJbmztSaffJz9vWNVLII2RK2kSUyqDQ4sCWR9ilZ62sJRDVOGA8CYZrv66gH1nRD90UE mpuJC4HCkWWALgY2veFXytlr7wtEcCKBq+OghYiZCK1xe6XvhqnRMlgiTGZeg6PZF0dO Gq9+4BZzkCjO0N10y6jENK2aBPMYR2ib6Qhz6aKYs/YiBUuTSjojR0rflMrOH0EHPHSX ShGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LHWFzxp4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c130si17532739oia.285.2021.10.19.09.44.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 09:44:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LHWFzxp4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52188 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcsE0-0005BP-3M for patch@linaro.org; Tue, 19 Oct 2021 12:44:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54454) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqz1-0005BC-Vf for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:56 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:40783) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcqyu-0007az-Pd for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:55 -0400 Received: by mail-pl1-x62c.google.com with SMTP id v20so13893785plo.7 for ; Tue, 19 Oct 2021 08:24:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VHU6Zq495CGWvucF4SFdns/LDCGAVtayMjBnfRKFC6c=; b=LHWFzxp4yLzmUteDIi1yQFWLmsDtrasHrtgw8oFYMeJMoNUCWK7waiWhe+MvD37lqr v0Dir3kqP5qK97qB1x6QJkeeZLzBVWZkLaoDP6G5aGCObs7IsenuDhIGXrCSx5GLIctk dFx82qN9K5Q8u7vKpz53rV2lPPD4pbiILqmxt27JkFIqV2TS98AjSj6FIJcaTfz2INE+ lvazd3roLgqm9fJqkwG1t5zSllK5pZVSIwXKCorCkFfiivF2BMJO2XrPUCRIHAUElfRZ plIT/SjzOYjod7HEthqy0Yx9igSLlwSVN3/kQbgFIxluosxAFiX/l2BRaUqN/4N+jBng T8QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VHU6Zq495CGWvucF4SFdns/LDCGAVtayMjBnfRKFC6c=; b=rJNoK9bueDAjO4mXKckPg3TZgEivS/t3btxQVsEl25k49VMdOTCKn0Wtlp5myk8kWT paZCEZ9VuaO0xzzO+vAnfCnbO40/au7mzGQ99xoBvpZC+mzNLBs/XODPH95A9puaw5w0 hPGC3kFRT4Yrc057G6iMYf3xSdCbqD9Rt0t1q8eL7ZM95kNAYAz3pq/N6CfTVbVe9mFe 7qBwjCKvxAF9YxJChR4K8o2hrcP+fY37jPCL3vyb/DH5u6XHFlrL8vv3CCNgr7nGKAT+ J1jawMTKJ6+O1FFi/4mh4UKJYyPPFrJEXhgRgC0rxtINx0XpCD5af0nEIhBHcEO2VBjb uCBA== X-Gm-Message-State: AOAM530zLnVtbTLiKvHa5OoCiXLr3Dvq6kCJZMbUzje3fgNqj7Bk8WEF Ik3HV6mw+w1194S6VuHKgbyFKKdkX/I= X-Received: by 2002:a17:90a:7e90:: with SMTP id j16mr448683pjl.139.1634657087519; Tue, 19 Oct 2021 08:24:47 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i2sm3293814pjt.19.2021.10.19.08.24.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 08:24:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 11/16] target/riscv: Adjust trans_rev8_32 for riscv64 Date: Tue, 19 Oct 2021 08:24:33 -0700 Message-Id: <20211019152438.269077-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019152438.269077-1-richard.henderson@linaro.org> References: <20211019152438.269077-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When target_long is 64-bit, we still want a 32-bit bswap for rev8. Since this opcode is specific to RV32, we need not conditionalize. Acked-by: Alistair Francis Reviewed-by: LIU Zhiwei Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 66dd51de49..c62eea433a 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a) return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl); } +static void gen_rev8_32(TCGv ret, TCGv src1) +{ + tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS); +} + static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a) { REQUIRE_32BIT(ctx); REQUIRE_ZBB(ctx); - return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl); + return gen_unary(ctx, a, EXT_NONE, gen_rev8_32); } static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a) From patchwork Tue Oct 19 15:24:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515963 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp796462imp; Tue, 19 Oct 2021 08:57:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxap7XYRBZMTDpG1BDdjK7/UEdeDLfukm2CM/hWDMEKfMqja86/bwzfMG49ONR0fD0z7hAT X-Received: by 2002:a67:d606:: with SMTP id n6mr35663508vsj.51.1634659063829; Tue, 19 Oct 2021 08:57:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634659063; cv=none; d=google.com; s=arc-20160816; b=FtdARXrxfdvQa/KGnhYip7hGuGGoyDomOpBUvSZglZFbtVxNqfg3Xw6189gvdk5WU2 ANU9cUwUN8ehKVMbrIC8IIgUiJsX72ySVhn8Op98wsysFgLOnjkZIwY46YJarpebaSs5 G4LPo0r461jDqAm/ett1B/dVTo/bAdX0zwW6CUxXcawRPn65ki0tUkmwFCJheMBjdzvh YZoHITjspQ8A4hXdzFqqI70IFvQ+KgbGxWTOrOc69jHikty75CHl2BDp38U0tfxeFUVk UD47XEtYWynwF+qWuZoh0yNBFyqvWYXP5pjHb2I9dmK9OmOsJjlIf9L5nZHtd574g9Ht aKjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=c7yPgPOtdXc8cLGoEleP9T3gCAQ/J91zHEOZFu0LBcU=; b=PUPVbayDrQfzl6pkW8L28OR3TagO3S1+K+O4SLGjTi8iOuwZcwR+t9U/CeGdNPVtTe DQ+SpTf3SYqh14PT+wge+8pCAwG2h0A+x8SC0MkbrTHHLr1keUEXb/dJOBK+RhqqHpXT gkPCG9u/6s9aTSvvB+4iSSCsKOyDPjCiKt+GvUObxAJDu/VO9IdXzwHPKqokbgmlhUCZ iiKcMBz3+O4tCVa/IIQxQZAOZJzV8br6zWrSFKfZDQ/HLlBdHpiac1nm4XYq04mEuwOO gxlZJRkPdpvJdrGa31tBQqsSlddPYnDQCclmK2uh8fUYeXIcCLBuIptgvKG5l9kJOlad SzbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YQ+rA+5I; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ba14si22244437uab.229.2021.10.19.08.57.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 08:57:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YQ+rA+5I; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42942 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcrUl-0006OD-5N for patch@linaro.org; Tue, 19 Oct 2021 11:57:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54580) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqz8-0005V1-5W for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:25:02 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:42500) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcqyv-0007bE-D4 for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:25:01 -0400 Received: by mail-pj1-x1033.google.com with SMTP id nn3-20020a17090b38c300b001a03bb6c4ebso157425pjb.1 for ; Tue, 19 Oct 2021 08:24:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c7yPgPOtdXc8cLGoEleP9T3gCAQ/J91zHEOZFu0LBcU=; b=YQ+rA+5ILyHzsnqwm8uC4tM6FqgsnEWS1+svMUGAPrgsGeJLhx8FPRYrGQrjbKK83H mdOZVgzIVOKQo84lYweo+qhCebKtHjkkrnpV9OAG8AhYNHQfBZePGRNvicC3onwJyioK nHRmO0VadPp6PxygRjb+FoWc0aqaeV0oE+x22IAudipSG8tWUgf7hqR2+QVFb/+M49pk noqExgxgb6UOMxOrv6zadjE3YiMUHzZUkTZ3ZhN4M4tL8i27zfcKvjYnQ5oPflbPCBGG 8nAhEQ4WZU4nFNv/4wJNyvbdYPx2WFoi5uBCzqlDtYYaWHcugwo2F/rPIlNM0iRLU6Bq cZdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c7yPgPOtdXc8cLGoEleP9T3gCAQ/J91zHEOZFu0LBcU=; b=Qq7H22a9J422tsGnSBi9oPRsZ1XO0ir6G/kbu0zoY9kgTqoNvH9vp4RNXoiGjRWTHM LzyfCYsA85Qi6z+CxGZF632+muPYM6P/JblQ0+ySRhtxxT1ZvS84d5DEPv9NWOi40/jB aPuGQH77TLzVYe1ZHmbV61Uc1s/PnPSJ9JHRu1r9EJ45XZ/XkQzVMvCiHZTjthFjQESg gFasiABpmUHZMs0GXFok/FDbqorcN4F8vHL/SvrILpwnV5KpR51CPWxoQyYpF0gcmcJL 685/z4Q6aXbl6tmwl+N3UFzzsWHPBz2NqEcLMFJjDZ5z3q48ET98SV46080OwiiUBeeI 7fiQ== X-Gm-Message-State: AOAM533okQYDwdJftEeyro/c95EJAl9Av57i4cuikoDSV+Ca0TGli1h9 3V2L3i4OTrOM73cVOFX00zCumsMK7tssqg== X-Received: by 2002:a17:90b:4c0d:: with SMTP id na13mr480691pjb.232.1634657088073; Tue, 19 Oct 2021 08:24:48 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i2sm3293814pjt.19.2021.10.19.08.24.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 08:24:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 12/16] target/riscv: Use gen_unary_per_ol for RVB Date: Tue, 19 Oct 2021 08:24:34 -0700 Message-Id: <20211019152438.269077-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019152438.269077-1-richard.henderson@linaro.org> References: <20211019152438.269077-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: 2 X-Spam_score: 0.2 X-Spam_bar: / X-Spam_report: (0.2 / 5.0 requ) DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The count zeros instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 16 ++++++++++++ target/riscv/insn_trans/trans_rvb.c.inc | 33 ++++++++++++------------- 2 files changed, 32 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5d54570cc9..ebcd1c8431 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -486,6 +486,22 @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, return true; } +static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, + void (*f_tl)(TCGv, TCGv), + void (*f_32)(TCGv, TCGv)) +{ + int olen = get_olen(ctx); + + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_unary(ctx, a, ext, f_tl); +} + static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) { DisasContext *ctx = container_of(dcbase, DisasContext, base); diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index c62eea433a..0c2120428d 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -47,10 +47,18 @@ static void gen_clz(TCGv ret, TCGv arg1) tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS); } +static void gen_clzw(TCGv ret, TCGv arg1) +{ + TCGv t = tcg_temp_new(); + tcg_gen_shli_tl(t, arg1, 32); + tcg_gen_clzi_tl(ret, t, 32); + tcg_temp_free(t); +} + static bool trans_clz(DisasContext *ctx, arg_clz *a) { REQUIRE_ZBB(ctx); - return gen_unary(ctx, a, EXT_ZERO, gen_clz); + return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw); } static void gen_ctz(TCGv ret, TCGv arg1) @@ -58,10 +66,15 @@ static void gen_ctz(TCGv ret, TCGv arg1) tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS); } +static void gen_ctzw(TCGv ret, TCGv arg1) +{ + tcg_gen_ctzi_tl(ret, arg1, 32); +} + static bool trans_ctz(DisasContext *ctx, arg_ctz *a) { REQUIRE_ZBB(ctx); - return gen_unary(ctx, a, EXT_ZERO, gen_ctz); + return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw); } static bool trans_cpop(DisasContext *ctx, arg_cpop *a) @@ -314,14 +327,6 @@ static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a) return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl); } -static void gen_clzw(TCGv ret, TCGv arg1) -{ - TCGv t = tcg_temp_new(); - tcg_gen_shli_tl(t, arg1, 32); - tcg_gen_clzi_tl(ret, t, 32); - tcg_temp_free(t); -} - static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); @@ -329,17 +334,11 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a) return gen_unary(ctx, a, EXT_NONE, gen_clzw); } -static void gen_ctzw(TCGv ret, TCGv arg1) -{ - tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32)); - tcg_gen_ctzi_tl(ret, ret, 64); -} - static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - return gen_unary(ctx, a, EXT_NONE, gen_ctzw); + return gen_unary(ctx, a, EXT_ZERO, gen_ctzw); } static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) From patchwork Tue Oct 19 15:24:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515974 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp847067imp; Tue, 19 Oct 2021 09:48:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzVds2AwXJZ4MLlxEoim006Au96owymcRh4CQj6nRBF8wVuukBYxf2xjo5cxLJyvWBygJiv X-Received: by 2002:a9d:609b:: with SMTP id m27mr6190480otj.51.1634662081703; Tue, 19 Oct 2021 09:48:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634662081; cv=none; d=google.com; s=arc-20160816; b=X09bFivT9mz/NRInrqhBIIsVBVfUwb19PE/TbJU5hI/3jurXLUYYj+g+SaPWOFD1A5 ksD3eeFMl5UNHSFFU8qUlAwL0QcFDVlcH/YlabB43dxcw0NohmHw3SL0G7zCNMk9es0I ef/wjVczm1thcRnRgHL9HQEA9iiAE9wdZI8+AaIAoQ/Z4ibsCAnhHCQNMBhjqr0PfNpU LZ371NMVRIEONuRHuTRPSs332TgFCQPyPEKYahNlX4VswA6JnnLA5rnZT4vK5yAMhfh4 fyg8QCNp3s6tmHT3j5nC2pUwVkvZ3Fnw16jDYGMpnH3tqNg+cFpcts0xiLeU+tMnICkJ amlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=v38EgObVIQZxnJyRBCc7mAXK+cvyWQc+ZvLKbhcUEpc=; b=bNZ3v3jgx9SiFYjRoTpKK2rHCRCFi98l0BWoGnanpzmGqAmoo+RGzLrPranNWw4H7v bKzNlL9pp2JmZmzdlfprRy3I+vH9QBENOYWD/agJURLRZ0C3E29GQQutFGbXTeTfZuA2 DZG5I1842LJAlvxTzSF/p5TlI2o9I4r7Qb3ylgnbonhDP+QcN5AeBN5dI49h5P0aWP92 v9epIFK73AAJCExrB8SL1U/AmquK94YzKwkJCC8knYT1uhXoNupjFSJ4YcXVH/Wk9K8l jP9y56NNnFc/P3toaLswKbF3BG107AwbfIFC4lS26CSMxFOhCflIOtTLyPbaSpBD09vy Rd7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kRPgEzoo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b21si19450278ots.45.2021.10.19.09.48.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 09:48:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kRPgEzoo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59190 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcsHQ-0001pA-VA for patch@linaro.org; Tue, 19 Oct 2021 12:48:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54510) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqz5-0005MF-Cm for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:59 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:45951) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcqyx-0007bp-5j for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:59 -0400 Received: by mail-pj1-x1032.google.com with SMTP id ls14-20020a17090b350e00b001a00e2251c8so126375pjb.4 for ; Tue, 19 Oct 2021 08:24:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v38EgObVIQZxnJyRBCc7mAXK+cvyWQc+ZvLKbhcUEpc=; b=kRPgEzoop32sbT28tg0ap/UMD/iK23JgbQhXbL/udh0XB8RE4ikdumYCWXGf9s56UE ZPfVLmn37VZOgNe4Mv1RHZuW6Tb5cYRed1VRPWd2OpfN6DpTvVNn6zKDmHEi2vKCdXKF jhbfs+SK9Xt2U4jbtbNUbM8CVM2ObIayK8K9OnB7Z35KUSmC+ih819VnffM6LUPtsj3L 9p0u9kJSOJUDPdNhxR8PAztGfkDBv3Z0QUjS2XayOUfb6ThS39hLcjdZXJLXNr6R7bBR ihsEaNMmvE+q779O4toqmGGaNfY2YCN6lCFVfSFhUo9kIo1uMxmcmOf5zP6xjdEqIICX 7e1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v38EgObVIQZxnJyRBCc7mAXK+cvyWQc+ZvLKbhcUEpc=; b=v2/qSeqb52vp7Ma6llu8zGpKQ5LuJhjLtqgVlWUI7NiFwdG+VaVg30WcyFS94fJdv/ iyM5R7R7TfqtSW7SmKqof1j084vU33F89q2LrVfdc87XQCbY7l2/HvlAwrZrtajulCuy w/dsX1fisoB7wJh8Dh2oCqcv9wvqyKegAWQxPLO/XCe4Rd2hXHM02ugoBMfxG1KjZ2DQ cHq2dWWSscBORWiIgTnths1WURyZxIdi+F8NIuKnnJQR10daT0WQK0/0yjIt0lQWC/kY e9dp3odo2V+T/pCtMyPyqAEbtp2mrKp2gqkMJ28XzcQHENcReO1KVLgnYanqX159tPED mYIw== X-Gm-Message-State: AOAM531opr1b7FkipraWai3Ar5CsAM01xjWBNX2j7ELOxtB5oRyqT/fG t0yaAICsJRof5n/N9k88HaGN04LGBFWTog== X-Received: by 2002:a17:90a:6fc1:: with SMTP id e59mr598677pjk.103.1634657088757; Tue, 19 Oct 2021 08:24:48 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i2sm3293814pjt.19.2021.10.19.08.24.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 08:24:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 13/16] target/riscv: Use gen_shift*_per_ol for RVB, RVI Date: Tue, 19 Oct 2021 08:24:35 -0700 Message-Id: <20211019152438.269077-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019152438.269077-1-richard.henderson@linaro.org> References: <20211019152438.269077-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Most shift instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 31 +++++++++ target/riscv/insn_trans/trans_rvb.c.inc | 92 ++++++++++++++----------- target/riscv/insn_trans/trans_rvi.c.inc | 26 +++---- 3 files changed, 97 insertions(+), 52 deletions(-) -- 2.25.1 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ebcd1c8431..de013fbf9b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -438,6 +438,22 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, return true; } +static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, + DisasExtend ext, + void (*f_tl)(TCGv, TCGv, target_long), + void (*f_32)(TCGv, TCGv, target_long)) +{ + int olen = get_olen(ctx); + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_shift_imm_fn(ctx, a, ext, f_tl); +} + static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, TCGv)) { @@ -474,6 +490,21 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, return true; } +static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, + void (*f_tl)(TCGv, TCGv, TCGv), + void (*f_32)(TCGv, TCGv, TCGv)) +{ + int olen = get_olen(ctx); + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_shift(ctx, a, ext, f_tl); +} + static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, void (*func)(TCGv, TCGv)) { diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 0c2120428d..cc39e6033b 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -227,22 +227,70 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a) return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); } +static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + + /* truncate to 32-bits */ + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_trunc_tl_i32(t2, arg2); + + tcg_gen_rotr_i32(t1, t1, t2); + + /* sign-extend 64-bits */ + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); +} + static bool trans_ror(DisasContext *ctx, arg_ror *a) { REQUIRE_ZBB(ctx); - return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl); + return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw); +} + +static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_rotri_i32(t1, t1, shamt); + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); } static bool trans_rori(DisasContext *ctx, arg_rori *a) { REQUIRE_ZBB(ctx); - return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl); + return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, + tcg_gen_rotri_tl, gen_roriw); +} + +static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + + /* truncate to 32-bits */ + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_trunc_tl_i32(t2, arg2); + + tcg_gen_rotl_i32(t1, t1, t2); + + /* sign-extend 64-bits */ + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); } static bool trans_rol(DisasContext *ctx, arg_rol *a) { REQUIRE_ZBB(ctx); - return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl); + return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw); } static void gen_rev8_32(TCGv ret, TCGv src1) @@ -349,24 +397,6 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl); } -static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv_i32 t1 = tcg_temp_new_i32(); - TCGv_i32 t2 = tcg_temp_new_i32(); - - /* truncate to 32-bits */ - tcg_gen_trunc_tl_i32(t1, arg1); - tcg_gen_trunc_tl_i32(t2, arg2); - - tcg_gen_rotr_i32(t1, t1, t2); - - /* sign-extend 64-bits */ - tcg_gen_ext_i32_tl(ret, t1); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); -} - static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); @@ -380,25 +410,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a) REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); ctx->ol = MXL_RV32; - return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw); -} - -static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv_i32 t1 = tcg_temp_new_i32(); - TCGv_i32 t2 = tcg_temp_new_i32(); - - /* truncate to 32-bits */ - tcg_gen_trunc_tl_i32(t1, arg1); - tcg_gen_trunc_tl_i32(t2, arg2); - - tcg_gen_rotl_i32(t1, t1, t2); - - /* sign-extend 64-bits */ - tcg_gen_ext_i32_tl(ret, t1); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw); } static bool trans_rolw(DisasContext *ctx, arg_rolw *a) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 9cf0383cfb..91dc438a3a 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -268,14 +268,26 @@ static bool trans_slli(DisasContext *ctx, arg_slli *a) return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); } +static void gen_srliw(TCGv dst, TCGv src, target_long shamt) +{ + tcg_gen_extract_tl(dst, src, shamt, 32 - shamt); +} + static bool trans_srli(DisasContext *ctx, arg_srli *a) { - return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl); + return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, + tcg_gen_shri_tl, gen_srliw); +} + +static void gen_sraiw(TCGv dst, TCGv src, target_long shamt) +{ + tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt); } static bool trans_srai(DisasContext *ctx, arg_srai *a) { - return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl); + return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, + tcg_gen_sari_tl, gen_sraiw); } static bool trans_add(DisasContext *ctx, arg_add *a) @@ -342,11 +354,6 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a) return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); } -static void gen_srliw(TCGv dst, TCGv src, target_long shamt) -{ - tcg_gen_extract_tl(dst, src, shamt, 32 - shamt); -} - static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { REQUIRE_64BIT(ctx); @@ -354,11 +361,6 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a) return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw); } -static void gen_sraiw(TCGv dst, TCGv src, target_long shamt) -{ - tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt); -} - static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { REQUIRE_64BIT(ctx); From patchwork Tue Oct 19 15:24:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515966 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp818007imp; Tue, 19 Oct 2021 09:18:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwXr2wjN9ikK6S8UkzBpbiDgfRFBKirnHEk+Jt4ij7c/uXqDufbtbhXkZo0CYIU9dGbAIr0 X-Received: by 2002:a67:d19b:: with SMTP id w27mr36766923vsi.54.1634660293987; Tue, 19 Oct 2021 09:18:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634660293; cv=none; d=google.com; s=arc-20160816; b=snIbJuQOdkjU5eLIIpiQesqI6RZptrQvh+LgBDmO8IamOXd9oTRVSClTidTxIv6zMb 3M3kMf9v23KYsplVjNvP89336YvpkJVHQHwVjo8+8kNyCp9v9Yqrl6RjyB1KGBxhQVYI Z1SesVfqLopa1ghMQ7Dsj2pneKwHPm2hOfHaM2m/wjADlkUwpAE9dgGH7v9n0O3NmJQ6 RPSEO0LVfDwzirob1QgccoD3Pd0F+SEVRwiJTgk2sCTtjeTw6DYGCkgQirIHgUfqPz6H SuAsmfZ2RhbzGl6LEBFHJZcyzqIqSrR2xlV6eNE23FXOo8+5rG0m5jhkh3RaXDE1vkSD J9YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=F1UFzoD53x5hfw3vlmPi31+uulj2FBxfz/+6B4SU6B8=; b=lZglAYnZoG0hj/WW870FN2n3ID7cQwXZxL14I/UjY6LaYtDYrHQ3S7WVLvydkT59/q vAxfP7EtBXS/sJZOGXyA69PIWQeINIHsYNCBQedLsTOiTkLSWdWQXkavsYgq4UYmwsk0 knOGNbCUXsoSdQxpMOV26zRdSO4SzflaPsABji2DjSPCk58i/SMTSTYWYjeOVH7jlKaG gt7ddS+dZaCDEFpA1f4cgXidPO4OtnfMfjyWO5FvxoywabyCLeKvRBgfYPNhKOheaQQ6 /qcqtM10DHF1YdmAsUcS5T+32MeZZ7V18U3VEW6RKXYuuMimP+Ad6MBymGt1Vu4f59aK KTog== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NIj+Wse0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d184si2961253vkg.71.2021.10.19.09.18.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 09:18:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NIj+Wse0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40550 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcrob-00014Q-C8 for patch@linaro.org; Tue, 19 Oct 2021 12:18:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54560) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqz8-0005Sl-1A for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:25:02 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:35456) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcqyx-0007cP-TU for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:25:00 -0400 Received: by mail-pf1-x432.google.com with SMTP id c29so235397pfp.2 for ; Tue, 19 Oct 2021 08:24:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F1UFzoD53x5hfw3vlmPi31+uulj2FBxfz/+6B4SU6B8=; b=NIj+Wse00Hd23DEia3PGKBzDpEJqAMuf3pzKXEOQWejr9wpi+0qJEepNsx9d48/Zbl qaLkTjtAW/D+lO1PiT/Z4ASYhcxPx1y3eS9TeqNOpCwvP1vXrpgs1lAbpx8Z65AIOjoo WH3nui/3fcR6HLAjYzeGxdWDIlcdnt7sebC6rXMPQGn6WavM+qYGT15H6VkvKDtdPml8 D5CiwhiSh6jxFtc5BVQkIbO7vElDpljN17iWC+mI2u3YxPuXSydlgW9ZCmhJZukY3dPy EfX4UcxoclH5BfgdwcRMsGxGLKmatZvde6CTsPz2TzrymuSn0sSY7MpRYxbWdpadXcsQ 8eBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F1UFzoD53x5hfw3vlmPi31+uulj2FBxfz/+6B4SU6B8=; b=qliBHyIJkm+XYuooJZOPiRO3+sdxT/p4QRcpsImmvbk9YBhwXA2aN8wXhMtz76jK8a 2ugKDyjxeL8wmopdR9z77hBmDpAhfaNNg7uyvw8HvHSo7rC1LXLeONKUxgoqw0NxMsm4 hsrlMbl3andGvB6/ixDkYfmovqasE41RFaHpRoycjW6pV9ycg7G5+LaFdvCGeZq0gKn5 hqs4xx/Ay8EukgDIJttGwkRZcHtrkQ4PhweVUkPSM7qE7INt6Nrqdcxts/fxLCOLSDrA TmwXi0lYm5ODgf/MsGblPijlsyKoDOI4AdjJBGoA2oAKjjVvPu7KsMq52/Hj6wfUGUOi upAw== X-Gm-Message-State: AOAM533LP3HRfs2KSJE0puDp9H1OanBLF6mn+St+SsEPjunOZdkvoYx2 wPV3LOA9pIR42/ZOfksgI0h9vX87Mxl30Q== X-Received: by 2002:a62:e90d:0:b0:44d:35a1:e5a0 with SMTP id j13-20020a62e90d000000b0044d35a1e5a0mr518558pfh.54.1634657089311; Tue, 19 Oct 2021 08:24:49 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i2sm3293814pjt.19.2021.10.19.08.24.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 08:24:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 14/16] target/riscv: Align gprs and fprs in cpu_dump Date: Tue, 19 Oct 2021 08:24:36 -0700 Message-Id: <20211019152438.269077-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019152438.269077-1-richard.henderson@linaro.org> References: <20211019152438.269077-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Allocate 8 columns per register name. Reviewed-by: LIU Zhiwei Signed-off-by: Richard Henderson --- target/riscv/cpu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) -- 2.25.1 Reviewed-by: Alistair Francis diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4e1920d5f0..f352c2b74c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -240,7 +240,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); } #endif - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", "pc", env->pc); #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); @@ -290,15 +290,16 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #endif for (i = 0; i < 32; i++) { - qemu_fprintf(f, " %s " TARGET_FMT_lx, + qemu_fprintf(f, " %-8s " TARGET_FMT_lx, riscv_int_regnames[i], env->gpr[i]); if ((i & 3) == 3) { qemu_fprintf(f, "\n"); } } + if (flags & CPU_DUMP_FPU) { for (i = 0; i < 32; i++) { - qemu_fprintf(f, " %s %016" PRIx64, + qemu_fprintf(f, " %-8s %016" PRIx64, riscv_fpr_regnames[i], env->fpr[i]); if ((i & 3) == 3) { qemu_fprintf(f, "\n"); From patchwork Tue Oct 19 15:24:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515975 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp849630imp; Tue, 19 Oct 2021 09:51:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzs54DwGDfFRfTTnIeovXp7vUjCYUJS5w0aYJBuZbKmvJD+TcB14zoo8xaznfZ/b2+28QFZ X-Received: by 2002:a1f:3a47:: with SMTP id h68mr33402930vka.9.1634662277425; Tue, 19 Oct 2021 09:51:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634662277; cv=none; d=google.com; s=arc-20160816; b=I8o73rj+0KKOEQbgsOVQIskBEr7DFcr2pWBQz82MAUhDSSUsagsM9TmIXriuaPX3f9 4SIiz9WZo1ACRURAmHWe21GPHnkvEs7xzvMJ+faKYk8s+P94/MSXrabEIjcp7JphQvpr 02TFFAGomka6v2UiuPkqgTR0LZIaPV6B9TKcI8KIqJANEOKP+ApDBI8TBmHCz0uZ7NMj tKUzGBUcpP02qIuAhUT3qGx2sdJCG8BeazdAYxzUHym678rbHuY2YovXLkFvwZhRIe9D TCqZhyP38PA6aDOxP+8Zw1h8PO1tW7nQ6c57b32Sywo/nFKdbUnWK/Vru3kYbo8NFHkH QL1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=C1T5Mwdpts89xr8x6xmc/boxWuJ+jcHTkvFs44ULios=; b=Ho7DXM0kpUSEnVqwQfLvuZLnAXIb4jnmWEv6RLDvxRnX6USM07fJmpMIXIp0dQEm5f vk3PIlSKiUbh8aYoHSCyjF7Zr2n7UnYckgueAXciPzFyS4PiSgz9Lx9ygjEHCSqa9JFb B5W9el3zdf7YttMEPoWdte6ju0Bu2DeLHwr6dHvOF1u4lqEP/NzA6m1FbFaOuDul1FdY l9MwKIvFhD+Hv4SOMM6u+3K4IVWWSORqgPoya+UJ1PUtMsNRleEbNGOVhfm3hpNKZAcw nb/Ie2PWK/EiVJkAkdY6op/veeSnmocIJAazYPkNmcdQ4+381PCjfXg1XyhxbE5FqyBT HPUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=J3KFDQO1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o21si14662853vsl.217.2021.10.19.09.51.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 09:51:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=J3KFDQO1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39742 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcsKa-0007ex-Oj for patch@linaro.org; Tue, 19 Oct 2021 12:51:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54512) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqz5-0005My-Ih for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:59 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:33356) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcqyx-0007ce-8e for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:24:59 -0400 Received: by mail-pl1-x62e.google.com with SMTP id y4so13943792plb.0 for ; Tue, 19 Oct 2021 08:24:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=C1T5Mwdpts89xr8x6xmc/boxWuJ+jcHTkvFs44ULios=; b=J3KFDQO1KWZxlGH+bunHXaCllB6INBYMD4w5rvMHeBxIFMOG+xBAf7CIVCvEKY6E2O 14nBm0C0t9uYhnn/d2HeXxe33YE4ZYxyRX/qTnkHb2VcjyNtqAIizDkXiFZHS+uPO4DV XTsftCzlcs//1CXBxnx9PcaHqqXnvcLtUFtRC6BJg6D4APK/EGkOblsyVB/YUmyXv9Ii wepIZGFKNlbpR2pqlmGwxO3W/tksbkpLAsIz82mFPMDwJoF6nIMPOErLVJLMy3uLwFSp Yje99U8ngsuDGXgA3HwKNq6q/UXTChNsqmyyEiGTFrsuZXKr6Ciaq3qdxPBabZwsK2P8 TRFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=C1T5Mwdpts89xr8x6xmc/boxWuJ+jcHTkvFs44ULios=; b=iMKsi8/ken0hubDxHpSbaVEk4IsbEnStJcEe/WmbIaxCGSc/1k0u5zusQagprmTrZY 3aNHUE48hDdLm9Wpy56TCAfID6o90SaR1b20L3fcc5cMANXHnXgdNcmg8JGPGokz2gDO N1S0uk8dOUURqH2YjFLjdUYevad3ORi4IOgYlhW2amr1W7oW5gCv3lVfg1esxFAXuMRD hdvSJmmcOuwgHRs88QsXCj2JQA+OJAIdusBiEV8I1lcZjLtYMd6+xgoFbO/2gDZltFF2 e/RF/v+GRwrRv7y4hwVCkB7MqjIhBlGoE/NMYr+ubVf4bgOtIkjS8Twi/BKZ+VIxux21 XCRw== X-Gm-Message-State: AOAM530w18C8tf+dleJ4+1m0LtctukWB3qyFeXncllVcw3xP7UDBUCTe A4IedbMRwW3jd5Szy4OI8se9RCYzm3uPKw== X-Received: by 2002:a17:90b:33cb:: with SMTP id lk11mr649144pjb.0.1634657089914; Tue, 19 Oct 2021 08:24:49 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i2sm3293814pjt.19.2021.10.19.08.24.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 08:24:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump Date: Tue, 19 Oct 2021 08:24:37 -0700 Message-Id: <20211019152438.269077-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019152438.269077-1-richard.henderson@linaro.org> References: <20211019152438.269077-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the official debug read interface to the csrs, rather than referencing the env slots directly. Put the list of csrs to dump into a table. Signed-off-by: Richard Henderson --- target/riscv/cpu.c | 90 +++++++++++++++++++++++----------------------- 1 file changed, 46 insertions(+), 44 deletions(-) -- 2.25.1 Reviewed-by: Alistair Francis diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f352c2b74c..3454b19c17 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -241,52 +241,54 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) } #endif qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", "pc", env->pc); + #ifndef CONFIG_USER_ONLY - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); - if (riscv_cpu_mxl(env) == MXL_RV32) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", - (target_ulong)(env->mstatus >> 32)); + { + static const int dump_csrs[] = { + CSR_MHARTID, + CSR_MSTATUS, + CSR_MSTATUSH, + CSR_HSTATUS, + CSR_VSSTATUS, + CSR_MIP, + CSR_MIE, + CSR_MIDELEG, + CSR_HIDELEG, + CSR_MEDELEG, + CSR_HEDELEG, + CSR_MTVEC, + CSR_STVEC, + CSR_VSTVEC, + CSR_MEPC, + CSR_SEPC, + CSR_VSEPC, + CSR_MCAUSE, + CSR_SCAUSE, + CSR_VSCAUSE, + CSR_MTVAL, + CSR_STVAL, + CSR_HTVAL, + CSR_MTVAL2, + CSR_MSCRATCH, + CSR_SSCRATCH, + CSR_SATP, + }; + + for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { + int csrno = dump_csrs[i]; + target_ulong val = 0; + RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); + + /* + * Rely on the smode, hmode, etc, predicates within csr.c + * to do the filtering of the registers that are present. + */ + if (res == RISCV_EXCP_NONE) { + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", + csr_ops[csrno].name, val); + } + } } - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", - (target_ulong)env->vsstatus); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp); #endif for (i = 0; i < 32; i++) { From patchwork Tue Oct 19 15:24:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515976 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp851550imp; Tue, 19 Oct 2021 09:53:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyzTR6qrc04Dk/6cUKFr7ZziFVtRGnCLSFJpVf0FA/CPGQckOESIdntcGozd0sBpe5z6IAe X-Received: by 2002:a05:6102:160b:: with SMTP id cu11mr21753821vsb.45.1634662413442; Tue, 19 Oct 2021 09:53:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634662413; cv=none; d=google.com; s=arc-20160816; b=D0CH9SxZyhrAibUW2ZNgTi4ixHiUDihSEDOq5LiWCP8AMTA4Uqqme78f2KvYmEDH/e IIi2jB7bSIg7L/TVzFQNBd8W89eFnWNbbaF4ji6o1cfsildt0E5T3dmaPgP5XblpCgjk ps9tpBp139qezUwp3wx53Csc8W08hRyDAjqqyuIYNIpnzTaRKGSWNLRdAqJoPlqmijFa 5zaviPUGJOO/ItfqS6lFT7PkTPqIU9oGgQqiAnvOu+D6eUYWs2RN/5cj8bCBSAVgH5hl Z6tZz37yrhpjx3JA8HqPNwjjjrlMQ67TF10yqMIpQsR6xIcdqQLElZh/tvx+GbttK9Rr NS6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RT2VpKAEfApm7ELgrgjYw2HluCj4mChRvtgjB+9QAL8=; b=SVkXmoicccK7YMbpMaBfa/m1mph23F93g509+R/Zgu7DIKaTWQIKU1Qcm/2tdaiA00 K5AWUQmwzevAqmBeIiWaV7StGsE0bQ0W2ucY/cDfABU9KHHmfgqPR6SK6jCSxM3VMhJJ WMZqF4WJNxgqboAtSzAqakNfpov02Zlz/Ok8fLyUm7X7lkLFodTnlRsJPlbBW2UXwRnd zVyeF5ngRjwlBho5ObfAGIh64qzrY3goCXJTGB8mr9WN9sjNjNRM0PUACDM+vfbtJ8/K MoYUtqbzsARnTOtHkTQHTbjH7Gkl4TKe8SNH/EktrpFQ0KJ2zrodxIxuC8ZBLCc3JrW/ bhnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vpE4vK8n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o1si16307426vsl.356.2021.10.19.09.53.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 09:53:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vpE4vK8n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48622 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcsMm-0005BX-Pd for patch@linaro.org; Tue, 19 Oct 2021 12:53:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54566) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqz7-0005TV-F3 for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:25:01 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:33358) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcqyy-0007dN-3h for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:25:01 -0400 Received: by mail-pl1-x630.google.com with SMTP id y4so13943811plb.0 for ; Tue, 19 Oct 2021 08:24:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RT2VpKAEfApm7ELgrgjYw2HluCj4mChRvtgjB+9QAL8=; b=vpE4vK8nDInCQ0L8wI/0xkgse3rPkmAu0lHL8TcdPqJQG66Y7jAOfx3akoUymzK3y7 Ew1QtUXp8FaeYmtDED62F4fodajz/p1ZsCHOiH7DovMX0U1qWoIFhWIf2TzSmBj3JanH eis0J5MyCi86EFtEFDt2elhgQIz+GZ0PEiy9fYuqAFqeAfXOFTYozoZK0G8mC6Db/1J7 h6NLV8nMpJtdiB11d/xK0djDdJKQg7EBD3KfbUG0Ar52JvSPe0TbceBYqvuo/Efigxfi 2VzuG3/Mue8GDPR0D4Bu/XxCj48GilMu+6CEno6BUhU5QFvn8aySjA9BF9O00oFG7Q6K N2/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RT2VpKAEfApm7ELgrgjYw2HluCj4mChRvtgjB+9QAL8=; b=mHmUWmzZaGW1QwzbgYRWjAJdytYSZjli/BJR8HzlRmxMauRAD74gdSLQj55TYqMmnN eBLoNzFh4dkGNFviZbsOSi7znAlqVlQ086BqDKtqVlas/nG8c25l54oNaW0achbJ+Dym pgx9OUHMNbPlQWx7w3xu92aAOx/9P3cU2/+ljMLBvQ0EWlOYSdSZ/YLaiuwcnPQMIa3B iqn5g6Ger3/bdAVNvox+xtmsa14X5pvgVKN8rCPoNV1K4Hq8ljtlgs1lE8b5tgPwO8O0 3cP1Pl3Xl0lcZwS/qe7HGQJpO8wKi9dFuIMfm/3UTuelbNbwBZTOK9aenjEp/CxE7MO7 1msA== X-Gm-Message-State: AOAM531KqmFhNZ8mSuxSKRekZUWlMS8zeL75+eBEBiHpQAWEavvC5d9t zHWm01YYTePVO6tHxgc4L68aMfnMzOI= X-Received: by 2002:a17:90a:f2c2:: with SMTP id gt2mr551670pjb.2.1634657090576; Tue, 19 Oct 2021 08:24:50 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i2sm3293814pjt.19.2021.10.19.08.24.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 08:24:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 16/16] target/riscv: Compute mstatus.sd on demand Date: Tue, 19 Oct 2021 08:24:38 -0700 Message-Id: <20211019152438.269077-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019152438.269077-1-richard.henderson@linaro.org> References: <20211019152438.269077-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The position of this read-only field is dependent on the current cpu width. Rather than having to compute that difference in many places, compute it only on read. Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 3 +-- target/riscv/csr.c | 37 ++++++++++++++++++++++--------------- target/riscv/translate.c | 5 ++--- 3 files changed, 25 insertions(+), 20 deletions(-) -- 2.25.1 Reviewed-by: Alistair Francis diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 429afd1f48..0d1132f39d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -185,10 +185,9 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { - uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD; uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | - MSTATUS64_UXL | sd; + MSTATUS64_UXL; bool current_virt = riscv_cpu_virt_enabled(env); g_assert(riscv_has_ext(env, RVH)); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c4a479ddd2..69e4d65fcd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -477,10 +477,28 @@ static RISCVException read_mhartid(CPURISCVState *env, int csrno, } /* Machine Trap Setup */ + +/* We do not store SD explicitly, only compute it on demand. */ +static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) +{ + if ((status & MSTATUS_FS) == MSTATUS_FS || + (status & MSTATUS_XS) == MSTATUS_XS) { + switch (xl) { + case MXL_RV32: + return status | MSTATUS32_SD; + case MXL_RV64: + return status | MSTATUS64_SD; + default: + g_assert_not_reached(); + } + } + return status; +} + static RISCVException read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) { - *val = env->mstatus; + *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); return RISCV_EXCP_NONE; } @@ -498,7 +516,6 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, { uint64_t mstatus = env->mstatus; uint64_t mask = 0; - int dirty; /* flush tlb on mstatus fields that affect VM */ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | @@ -520,12 +537,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, mstatus = (mstatus & ~mask) | (val & mask); - dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | - ((mstatus & MSTATUS_XS) == MSTATUS_XS); - if (riscv_cpu_mxl(env) == MXL_RV32) { - mstatus = set_field(mstatus, MSTATUS32_SD, dirty); - } else { - mstatus = set_field(mstatus, MSTATUS64_SD, dirty); + if (riscv_cpu_mxl(env) == MXL_RV64) { /* SXL and UXL fields are for now read only */ mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64); mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64); @@ -798,13 +810,8 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno, { target_ulong mask = (sstatus_v1_10_mask); - if (riscv_cpu_mxl(env) == MXL_RV32) { - mask |= SSTATUS32_SD; - } else { - mask |= SSTATUS64_SD; - } - - *val = env->mstatus & mask; + /* TODO: Use SXL not MXL. */ + *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); return RISCV_EXCP_NONE; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index de013fbf9b..35245aafa7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -280,7 +280,6 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) static void mark_fs_dirty(DisasContext *ctx) { TCGv tmp; - target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD; if (ctx->mstatus_fs != MSTATUS_FS) { /* Remember the state change for the rest of the TB. */ @@ -288,7 +287,7 @@ static void mark_fs_dirty(DisasContext *ctx) tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_temp_free(tmp); } @@ -299,7 +298,7 @@ static void mark_fs_dirty(DisasContext *ctx) tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); tcg_temp_free(tmp); }