From patchwork Fri Oct 15 04:09:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515779 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp132566imi; Thu, 14 Oct 2021 21:12:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyy7dFtHVQ5/I/Qnt7EZE8jgRk89suvc/5MPXfi6e8a9/DQEUKc7UuqDBT+vQTCiSMLSRI+ X-Received: by 2002:a05:6602:2ac1:: with SMTP id m1mr2272948iov.118.1634271137457; Thu, 14 Oct 2021 21:12:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271137; cv=none; d=google.com; s=arc-20160816; b=DGqy3nb2iICjR1lBF2o1lJvaVHD7SDOi0Jq0hvEcZW0W/4NkQD7DmOfvjWhFQN+BRd kxMVUbeCECg2e+GuoohHusd+Asq8JkhfGPY3AnXhYk2WFHvGrX80g2v7Wi7JVXrpIlCI GBTXNc13047wUU+ullbyQsufegzAxuTc3Z1hiNkFYE4xOiiLVcPT7VxcYuoXAsPjGrbN irm0oiARwrESOBKsY7SUYVIds4vsVCZpwNp3T+1eJogSNWSdRyw+O0Z1cv2Mt1xz03Sb CjfjoT69QBZwfqmO2n+27PgsSKB1RcsTCIeFuqFdBnwCT5gH8o52xh5TOySf8emQ9Kwx dlYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KuLneJaR8ad6zfXTHHDWg+qki3lZgiD+ST/qhhyEGtg=; b=jfmFFeBMh4YaPv9oeheWKkg/ZzQLXp2SMKY/yFqKzqM9HpfApL03YK3GfZZyj9Fg/U 6hS32NVb6Ga1dB3IUsSqh05pAyveu4e07uyQlhPHOnK/C7PY3XHFhdbJLVtiQzW9IXlW pxq8yEOXlA3o5a8mak0t6BQqX+KuRckzWZ4M8MfPdhQDs0Vq5FDdZdE9K67mPbyiMFfw N58gg97LUmEbQJx3K565pslLfxaDkzYtYkWwNL0QaJq02PIV3FpFT/b+HdsqQZFdksz8 qZ6HWIOUQuzbEY9gJE0H0l3rbsDLzQiaU04ZLthyqzgcdgpylD5HxxFNGzbunY9VBx9l Q+0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Q8DQDDwo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d3si390336ilf.43.2021.10.14.21.12.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:12:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Q8DQDDwo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEZs-0006fl-Pd for patch@linaro.org; Fri, 15 Oct 2021 00:12:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38616) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYd-0006f5-57 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:10:59 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:41947) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYb-0008WE-7c for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:10:58 -0400 Received: by mail-pj1-x102f.google.com with SMTP id na16-20020a17090b4c1000b0019f5bb661f9so6415392pjb.0 for ; Thu, 14 Oct 2021 21:10:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KuLneJaR8ad6zfXTHHDWg+qki3lZgiD+ST/qhhyEGtg=; b=Q8DQDDwoPV6XOzXFGiN+2e06iPsAqlzS3h9OYiPILk9999LxJ1yf765DaQ4z94o2gO CtYJnqk9Chw4CLku5tXfdWgzs6a02qm2Z/AP2G0XQoWVxyiZWe4MvLVi7rO1EvOWqWpV M12CpK74BDAKupe3kgjq/kItxoIxNzW/KMy6pv7RkKOTG6U+OPx7a2claOb2oc+UMvfg 6LnvbI2Y8YhnrVVxriOIe8H/EEd+HVUYq1wivlnDBUMjJDkFKO8uzOhAyyEtJrdh9XoU TbOJD7WGLNwILfHIo6KE9gJ+qm2WDW2rrDPvhweJQUoU7h6RIlJNuE0JjhRrXTGsWeDY HNHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KuLneJaR8ad6zfXTHHDWg+qki3lZgiD+ST/qhhyEGtg=; b=xIbouTGaPNExh3tMVkO799HB0c6mF982b0PPIzXS8ugr6D3uXJ+mdEB4V2/5wpkAKZ uFBKrlCkIFe9vT9GJKE3ETm92DudnoicbzJMCetVPs5SmU88PJcOCnxQgu9dNRXoc3Yd /cuOP7vl4dN/70A3Anz7IOil7jrdduDJa6Us5xhPM1sMXoDfYDc1q6atGX18OXMK4a8s iZ6IzPQ2fg71U7dB69YCFBc65rHAzClgFpC1YPonNOpv2xbqnWH/vnIxszzvDiCqnF2M sUyIo3uQnqhJJ/g8RBvSzoe3jZyeKfzW7a/6n2JWCmDDyV/PGnfdIQExl2tkjqO4oyzs V8Nw== X-Gm-Message-State: AOAM532icjzrVknR0F9gaTZASmdJ39SNi1CG6GYXVQAS0UlMYcrSEzFR SLSwrHO6rY+RQtQw4ApGLkrrddIlPhhY9w== X-Received: by 2002:a17:90a:de84:: with SMTP id n4mr7006410pjv.226.1634271055778; Thu, 14 Oct 2021 21:10:55 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.10.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:10:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 01/67] accel/tcg: Split out adjust_signal_pc Date: Thu, 14 Oct 2021 21:09:47 -0700 Message-Id: <20211015041053.2769193-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?P?= =?utf-8?q?hilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out a function to adjust the raw signal pc into a value that could be passed to cpu_restore_state. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Adjust pc in place; return MMUAccessType. --- include/exec/exec-all.h | 10 ++++++++++ accel/tcg/user-exec.c | 41 +++++++++++++++++++++++++---------------- 2 files changed, 35 insertions(+), 16 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 9d5987ba04..e54f8e5d65 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -663,6 +663,16 @@ static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, return addr; } +/** + * adjust_signal_pc: + * @pc: raw pc from the host signal ucontext_t. + * @is_write: host memory operation was write, or read-modify-write. + * + * Alter @pc as required for unwinding. Return the type of the + * guest memory access -- host reads may be for guest execution. + */ +MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); + /** * cpu_signal_handler * @signum: host signal number diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e6bb29b42d..c02d509ec6 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -57,18 +57,11 @@ static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu, cpu_loop_exit_noexc(cpu); } -/* 'pc' is the host PC at which the exception was raised. 'address' is - the effective address of the memory exception. 'is_write' is 1 if a - write caused the exception and otherwise 0'. 'old_set' is the - signal set which should be restored */ -static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, - int is_write, sigset_t *old_set) +/* + * Adjust the pc to pass to cpu_restore_state; return the memop type. + */ +MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write) { - CPUState *cpu = current_cpu; - CPUClass *cc; - unsigned long address = (unsigned long)info->si_addr; - MMUAccessType access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; - switch (helper_retaddr) { default: /* @@ -77,7 +70,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * pointer into the generated code that will unwind to the * correct guest pc. */ - pc = helper_retaddr; + *pc = helper_retaddr; break; case 0: @@ -97,7 +90,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * Therefore, adjust to compensate for what will be done later * by cpu_restore_state_from_tb. */ - pc += GETPC_ADJ; + *pc += GETPC_ADJ; break; case 1: @@ -113,12 +106,28 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * * Like tb_gen_code, release the memory lock before cpu_loop_exit. */ - pc = 0; - access_type = MMU_INST_FETCH; mmap_unlock(); - break; + *pc = 0; + return MMU_INST_FETCH; } + return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; +} + +/* + * 'pc' is the host PC at which the exception was raised. + * 'address' is the effective address of the memory exception. + * 'is_write' is 1 if a write caused the exception and otherwise 0. + * 'old_set' is the signal set which should be restored. + */ +static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, + int is_write, sigset_t *old_set) +{ + CPUState *cpu = current_cpu; + CPUClass *cc; + unsigned long address = (unsigned long)info->si_addr; + MMUAccessType access_type = adjust_signal_pc(&pc, is_write); + /* For synchronous signals we expect to be coming from the vCPU * thread (so current_cpu should be valid) and either from running * code or during translation which can fault as we cross pages. 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[209.51.188.17]) by mx.google.com with ESMTPS id i6si5638616ybi.120.2021.10.14.21.14.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:14:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jZuug+o0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59300 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEc6-00043l-Rh for patch@linaro.org; Fri, 15 Oct 2021 00:14:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38650) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYe-0006fF-H7 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:00 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:41949) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYb-0008WM-Sy for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:00 -0400 Received: by mail-pj1-x1031.google.com with SMTP id na16-20020a17090b4c1000b0019f5bb661f9so6415410pjb.0 for ; Thu, 14 Oct 2021 21:10:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Xj+GBWow8u43T9kfx0pjQLSKyRLLPuU7SzICT50Nk5s=; b=jZuug+o019EfKoHhMGR63+bwuoHKY41oienXVmxxvQnShcmhYnHrK9qosb2utXVuRX Wcs2SD4/pSk2U4LDbK6L6CtwlUbyxaqFSquHQUmOVJRPswvycVVrGNTXc3MoLBwzFOz9 XXiA7CtJddmb51ZApyb7vFMSKb8DpfnXyXUsU3EmqXKM7qPsKILVEDw3/gVmGYUwOYg9 k1pdunAQT0TELpQRSnToNhuWwPm3Nlupq4QTlelRKfQwDVn/Ww6nocihIgOakzB+VuOY 2rCWIB6J+3tLBIlq2ZXtBk2fzrw6PLyJIgux/FmMKdGIiN7glUIXCjbsT6YV32BrygZ5 yJWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Xj+GBWow8u43T9kfx0pjQLSKyRLLPuU7SzICT50Nk5s=; b=q0vUc7lk3cVoJaK40305BFSjzHb+8owBA82uHerijqvD1HZUdXGp2kPFlsCuSyKreX ZKHMtCVn+b8mlzkNNaXAkGBrxu4GJchYgt7hOR/TKFpUDarXN48odudapsnwes+DrwRH Q40RmhNGVSVlGwXGmW9UBT7dp5RuAQ0+2PdhtMdwC01TIzGKf3KKaSLMyONx34TVlBZU O57DItiOaOx9FhSL2kAWJ7+FdBOR2vHXXj9965ThkmxFNzspsM0xfPCZan5PDgg/qohD 07S1YPTBx5SAVkQVnxywMUheH4diRH6NWTPTkoeNgou95NorS2dSI791ipY8fZpv5vbl MN2w== X-Gm-Message-State: AOAM531NOjss075MSzliKJm7aeZwsiK6vHzHrUllhcPqACsOkgnoLPyZ pTXuyAfL4eeyc461D59FBRWb0j3FtzNx3Q== X-Received: by 2002:a17:90b:3504:: with SMTP id ls4mr10729905pjb.111.1634271056529; Thu, 14 Oct 2021 21:10:56 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.10.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:10:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 02/67] accel/tcg: Move clear_helper_retaddr to cpu loop Date: Thu, 14 Oct 2021 21:09:48 -0700 Message-Id: <20211015041053.2769193-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently there are only two places that require we reset this value before exiting to the main loop, but that will change. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 3 ++- accel/tcg/user-exec.c | 2 -- 2 files changed, 2 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5fd1ed3422..410588d08a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -451,6 +451,7 @@ void cpu_exec_step_atomic(CPUState *cpu) * memory. */ #ifndef CONFIG_SOFTMMU + clear_helper_retaddr(); tcg_debug_assert(!have_mmap_lock()); #endif if (qemu_mutex_iothread_locked()) { @@ -460,7 +461,6 @@ void cpu_exec_step_atomic(CPUState *cpu) qemu_plugin_disable_mem_helpers(cpu); } - /* * As we start the exclusive region before codegen we must still * be in the region if we longjump out of either the codegen or @@ -905,6 +905,7 @@ int cpu_exec(CPUState *cpu) #endif #ifndef CONFIG_SOFTMMU + clear_helper_retaddr(); tcg_debug_assert(!have_mmap_lock()); #endif if (qemu_mutex_iothread_locked()) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index c02d509ec6..3f3e793b7b 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -175,7 +175,6 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * currently executing TB was modified and must be exited * immediately. Clear helper_retaddr for next execution. */ - clear_helper_retaddr(); cpu_exit_tb_from_sighandler(cpu, old_set); /* NORETURN */ @@ -193,7 +192,6 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * an exception. Undo signal and retaddr state prior to longjmp. */ sigprocmask(SIG_SETMASK, old_set, NULL); - clear_helper_retaddr(); cc = CPU_GET_CLASS(cpu); cc->tcg_ops->tlb_fill(cpu, address, 0, access_type, From patchwork Fri Oct 15 04:09:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515785 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp133817imi; Thu, 14 Oct 2021 21:14:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxMMaXSPF8qgpPqKuFi73gKT+X+/66ExIbRV+eYDLC7vomblRDHxNz4Nn9zvdw/WuS4uWuB X-Received: by 2002:a25:1ac6:: with SMTP id a189mr10485898yba.149.1634271275599; Thu, 14 Oct 2021 21:14:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271275; cv=none; d=google.com; s=arc-20160816; b=IbiiMiIUKFB7Y60TR6t0T/t0YLEty/l9/u9E5BQn/EoHWPOzSNinmTjQWUXgKk5C+u gjmmhgSfpBvMUwQr8xpTeR7ezKPgwkDuyVlI6iUTVLP0fXu7LrLxGD8MTTMGMp2CRDOR LBB1p3afd0OZJZB805RRQcr/Nr8RFS6K+YSN6YsxPiTBAeONNmyjKTKEJbuzcpfGcL6C SCm6hZUJ9/wsnm2pwdGi+vFqDR317pkYmNlC3lX6dvarjoYv8umA9f7RTZH9hMk260NA RPF509vzMOvb1zYzXRBqxlwNODlBWWVkTAQj4aG84LECxOj0RT4oEvuROVJsG1D8Fv4H ac/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=oWBO3F4xYVHiKUc+8+wn/0Gm+2aHBS/NMTMJJaAZTpE=; b=JLm7EqUDXNRBQq3hBBxIB8jwOGtJVSzIkSO9Wdt1y4bdfevtES26YZ1ehq7Vzjw+qH Yq/bLTyNafDkhzuU6kLE3DwGosA9CbbzDaHtmjAI7wP8f2KL08WPrQ/NIvMwIePJLiYx vjLpO0yLyrXEEEs0uX9X/94HI82AvwN+L6EXxfzkkqR4id7+jGD90+0e7GBOUU5tDMUR YTVe9d1qIhQLO5YHCPXI0VN6ZSySfqrc0bC58Zl9RfarwGaSNYJSycOL/v1JiRIFXQxM oE3r8HSUvp0LBqyQQG8nI0DmLfAFY1tcbwOzh4D4k5xCcBe3KcCmlnWrV4xfBzupg6af eJMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WgZSYMdM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Most of the rest will migrate to linux-user/ shortly. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Pass guest address to handle_sigsegv_accerr_write. --- include/exec/exec-all.h | 12 +++++ accel/tcg/user-exec.c | 103 ++++++++++++++++++++++++---------------- 2 files changed, 74 insertions(+), 41 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index e54f8e5d65..5f94d799aa 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -673,6 +673,18 @@ static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, */ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); +/** + * handle_sigsegv_accerr_write: + * @cpu: the cpu context + * @old_set: the sigset_t from the signal ucontext_t + * @host_pc: the host pc, adjusted for the signal + * @host_addr: the host address of the fault + * + * Return true if the write fault has been handled, and should be re-tried. + */ +bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, + uintptr_t host_pc, abi_ptr guest_addr); + /** * cpu_signal_handler * @signum: host signal number diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 3f3e793b7b..cb63e528c5 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -114,6 +114,54 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write) return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; } +/** + * handle_sigsegv_accerr_write: + * @cpu: the cpu context + * @old_set: the sigset_t from the signal ucontext_t + * @host_pc: the host pc, adjusted for the signal + * @guest_addr: the guest address of the fault + * + * Return true if the write fault has been handled, and should be re-tried. + * + * Note that it is important that we don't call page_unprotect() unless + * this is really a "write to nonwriteable page" fault, because + * page_unprotect() assumes that if it is called for an access to + * a page that's writeable this means we had two threads racing and + * another thread got there first and already made the page writeable; + * so we will retry the access. If we were to call page_unprotect() + * for some other kind of fault that should really be passed to the + * guest, we'd end up in an infinite loop of retrying the faulting access. + */ +bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, + uintptr_t host_pc, abi_ptr guest_addr) +{ + switch (page_unprotect(guest_addr, host_pc)) { + case 0: + /* + * Fault not caused by a page marked unwritable to protect + * cached translations, must be the guest binary's problem. + */ + return false; + case 1: + /* + * Fault caused by protection of cached translation; TBs + * invalidated, so resume execution. Retain helper_retaddr + * for a possible second fault. + */ + return true; + case 2: + /* + * Fault caused by protection of cached translation, and the + * currently executing TB was modified and must be exited + * immediately. Clear helper_retaddr for next execution. + */ + cpu_exit_tb_from_sighandler(cpu, old_set); + /* NORETURN */ + default: + g_assert_not_reached(); + } +} + /* * 'pc' is the host PC at which the exception was raised. * 'address' is the effective address of the memory exception. @@ -125,8 +173,9 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, { CPUState *cpu = current_cpu; CPUClass *cc; - unsigned long address = (unsigned long)info->si_addr; + unsigned long host_addr = (unsigned long)info->si_addr; MMUAccessType access_type = adjust_signal_pc(&pc, is_write); + abi_ptr guest_addr; /* For synchronous signals we expect to be coming from the vCPU * thread (so current_cpu should be valid) and either from running @@ -143,49 +192,21 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, #if defined(DEBUG_SIGNAL) printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", - pc, address, is_write, *(unsigned long *)old_set); + pc, host_addr, is_write, *(unsigned long *)old_set); #endif - /* XXX: locking issue */ - /* Note that it is important that we don't call page_unprotect() unless - * this is really a "write to nonwriteable page" fault, because - * page_unprotect() assumes that if it is called for an access to - * a page that's writeable this means we had two threads racing and - * another thread got there first and already made the page writeable; - * so we will retry the access. If we were to call page_unprotect() - * for some other kind of fault that should really be passed to the - * guest, we'd end up in an infinite loop of retrying the faulting - * access. - */ - if (is_write && info->si_signo == SIGSEGV && info->si_code == SEGV_ACCERR && - h2g_valid(address)) { - switch (page_unprotect(h2g(address), pc)) { - case 0: - /* Fault not caused by a page marked unwritable to protect - * cached translations, must be the guest binary's problem. - */ - break; - case 1: - /* Fault caused by protection of cached translation; TBs - * invalidated, so resume execution. Retain helper_retaddr - * for a possible second fault. - */ - return 1; - case 2: - /* Fault caused by protection of cached translation, and the - * currently executing TB was modified and must be exited - * immediately. Clear helper_retaddr for next execution. - */ - cpu_exit_tb_from_sighandler(cpu, old_set); - /* NORETURN */ - - default: - g_assert_not_reached(); - } - } /* Convert forcefully to guest address space, invalid addresses are still valid segv ones */ - address = h2g_nocheck(address); + guest_addr = h2g_nocheck(host_addr); + + /* XXX: locking issue */ + if (is_write && + info->si_signo == SIGSEGV && + info->si_code == SEGV_ACCERR && + h2g_valid(host_addr) && + handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) { + return 1; + } /* * There is no way the target can handle this other than raising @@ -194,7 +215,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, sigprocmask(SIG_SETMASK, old_set, NULL); cc = CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, address, 0, access_type, + cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, MMU_USER_IDX, false, pc); g_assert_not_reached(); } From patchwork Fri Oct 15 04:09:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515780 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp132599imi; Thu, 14 Oct 2021 21:12:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwYpHjbJQE1SIsYSrPGfHaMZrjtUeoDdOycHJ1m2nrXmhuwiZFgAKoYM9gTNpCfE90KTipT X-Received: by 2002:a02:a80b:: with SMTP id f11mr6956856jaj.66.1634271139191; Thu, 14 Oct 2021 21:12:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271139; cv=none; d=google.com; s=arc-20160816; b=OL0E7KdaCIpear2ZnEKAJb/vGRvYqubqNF2YBy+ugkpsp2FQCK82QOr+3HqkrUTwH5 DzQ9V+ESDCm5Xx2RJqcvbo+HrQsci2QlNA6mWKxPCGq55IsC+A96KU6rKi2xyEQve1Wt 9PedCZWcIPs5qcu2ZnzHnoJ5/uc75d4quhRebgiJ/HZcmxS7cNE9HC7x0rrihnnkEbgO 66Cr10jtlt8NJVQIwXfpOe3a1HyxLffhMzOdKHa+s7U2agtr69AlOC3ZMQVHgxyvZH3R Gq+1UnUPAl988YAO4wfYuNuDlZqZ/to5rrwCbU5fThasri0aAcDmrxgCsNfASGgdYo7+ 5ZrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hPg0TWxPCq+nfWOlqCTkACXTywAZGmXvHVDfXz+ELxA=; b=s+bSrrulMSkQ/I1/7qNZKQeO/IPvjSiRgfmGp0C1cFpjou5Zn3GRRES2WVNCRbXl9R ddVMhFdnp3ZbeBOtmNyETuWYa6hweOyOUNHAolKDJf50ayUJWMNRyBxvRKP5sEgZBaIj mruWpBFKb1wPi2QxWPLirgDEQxHigR/N48k7oig/4z2CrPar6CIPJwIv/viGOwFiYwa6 nxBicqNodMCU+pMaAv2Ce7/tooblNDQUXGz68pcbPiKJoCbSHlLZpqo2whyAvUvFPtoE ejA4BPreIWs+Ghy99haEJZNQQxwcRxvkIGHzG2VDh5KQSxfRsAtP1fYez428Avb/BMZB 7r3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ePhDaFwd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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We do use sigsetjmp in the main cpu loop, but we do not save the signal mask as most exits from the cpu loop do not require them. Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index cb63e528c5..744af19397 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -46,17 +46,6 @@ __thread uintptr_t helper_retaddr; //#define DEBUG_SIGNAL -/* exit the current TB from a signal handler. The host registers are - restored in a state compatible with the CPU emulator - */ -static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu, - sigset_t *old_set) -{ - /* XXX: use siglongjmp ? */ - sigprocmask(SIG_SETMASK, old_set, NULL); - cpu_loop_exit_noexc(cpu); -} - /* * Adjust the pc to pass to cpu_restore_state; return the memop type. */ @@ -155,7 +144,8 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, * currently executing TB was modified and must be exited * immediately. Clear helper_retaddr for next execution. */ - cpu_exit_tb_from_sighandler(cpu, old_set); + sigprocmask(SIG_SETMASK, old_set, NULL); + cpu_loop_exit_noexc(cpu); /* NORETURN */ default: g_assert_not_reached(); From patchwork Fri Oct 15 04:09:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515782 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp132612imi; Thu, 14 Oct 2021 21:12:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy4MG9RrUJtWixV6G/Rhe9p8PgTYwJZyuq0HXZ3YEvbghw/CeKybspCXx9F7SbFnjtmSUI0 X-Received: by 2002:a05:6e02:216e:: with SMTP id s14mr2185160ilv.66.1634271140640; Thu, 14 Oct 2021 21:12:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271140; cv=none; d=google.com; s=arc-20160816; b=bFWxJbprePgdq64BEh13CpeY4H4Ih6Sq8GNwMFIAKfdQDlrXWVcgqC50NxVtK3bsy4 rbNo2vAyKcWiYmOIEC8q9IVdIe9OuNuqpC+RBj3dBH6uZJaPFzBZJwD+mqkVGFnjcipl wCLgrA1r4za4MurnyzSDNIspeTbtv+X1fZqgNIigHqe+6VOj18ZLjSXlHyaBGy+2+heH DghU5soevBTAtRP68ul/ar/fti9LVvpD6arLjqftf8xujmM+QLwF6pw5DYL08B/0g7mK hAOiDY4EOeugE4KQ3NnHmeEf552PBQd7Yam0O7p6rL80TtYgib/10OO8Elp3CW5J9G/q UJ7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=oOQU7Pbw0+lekQo/Dc4xCn9/9dfAsnRnEEjuG278GdE=; b=iI7MWXt+CIXO8p4pqEm3j9yNokB7DUEfEOW82faIenpYOGJi2TOvJC/Oj6OD0R+YQT Y5A2j3JdMwiPvyzkhrIPSp5NhcHYxPXDY6lGMnnpoQDEIsS54zH9jNIInQvF1xR1uTc/ Dd4xpgsBgQSjKHcJQhSP9oKeCKdkxbvZOnKthLgUDMsL4KyWjBRmdTnjaGyFT7CddPVk QCEmZQGbftCzA8Xe5Tv9mUSD2CIj4lskN5OswGSueTGPY1JKCLT/BuL4uwTPMfLzbNV4 SOk8mbdvfXldltKswbYez9X8hUFC8ZSipzZoRes0XaNRwgKx+4h6RV9Zczd2Zzkh3xN7 Oy8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=stISHxdx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w17si8848083jad.34.2021.10.14.21.12.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:12:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=stISHxdx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50798 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEZv-0006jz-W0 for patch@linaro.org; Fri, 15 Oct 2021 00:12:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38684) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYg-0006h4-7G for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:02 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:33775) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYd-00007Y-Vy for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:01 -0400 Received: by mail-pl1-x636.google.com with SMTP id y4so5636522plb.0 for ; Thu, 14 Oct 2021 21:10:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oOQU7Pbw0+lekQo/Dc4xCn9/9dfAsnRnEEjuG278GdE=; b=stISHxdxUYcJ+m/mrW/EMrcZISPQEdhH2XWaDecY0jEO20NKcvrdgzQb1UPvD0aouY ZgtEy5wmVv32wGXJUro7lcJYO5NfsXjO+Z0jmjNlK/MHYKq05c++dtZTC6MTZK4khnVB woMC8jAUSyQqiyZKWSVfHy5ddy+PCaTv46nIoQlGgJkcChCDPGUnoH+FAsQv+4w8kVFx BUCCN5GebAenGUvR8mLa8KsTQBTTmzUZE0S3dYSRVQ8dCJVWuzqvihKUOlf8X+iR6Q3R A9Gm6bHYWHN/KIdw2tb65R3NIH0FU7ZaBg5k5sa/wEPRu71u+dIZ0BB8O/mWDfaLznZN 7h7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oOQU7Pbw0+lekQo/Dc4xCn9/9dfAsnRnEEjuG278GdE=; b=odd3epmrTSJWelk3XRPSpzu2EPjuaXR77nrnYpc7Hhdk7UAaGLHXcNQO33PVdcwH6c N5ZIGzV+eAu6ZKPjvbEq7DIj85vL0FFBWW/thNkKt2UeFwY96QWXPYA+NWwanMKvMD1s OyNTEURyAlmbSHn28H/7GCWLH3T5k3Scob950l8k/ocYZzLqAdQEdSvZsZguhvznrBmj CCPHL+sXH0Ao2r6/kOl+9xLLenCLq3Qw0+yVSgJTClm6NTiYRdiJVJYLIEmeIB7S6FYl Ka7CSmyiEmBSvd1Qg0/l3/dkEPB1O2cCDWX6omHyuIVQelyKmFeyBaoBO3fHuBDVxYnh gZvg== X-Gm-Message-State: AOAM530xeDDEYnF39tqqWJwSmcf4aFSoL7iPMERW0zjcgji2NrdmGqmA 9vvp3MX+sDV7kdP/L7S25TRpTSODpDNcFA== X-Received: by 2002:a17:90b:4b46:: with SMTP id mi6mr10276124pjb.161.1634271058598; Thu, 14 Oct 2021 21:10:58 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.10.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:10:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 05/67] configure: Merge riscv32 and riscv64 host architectures Date: Thu, 14 Oct 2021 21:09:51 -0700 Message-Id: <20211015041053.2769193-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The existing code for safe-syscall.inc.S will compile without change for riscv32 and riscv64. We may also drop the meson.build stanza that merges them for tcg/. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- configure | 8 ++------ meson.build | 4 +--- linux-user/host/{riscv64 => riscv}/hostdep.h | 4 ++-- linux-user/host/riscv32/hostdep.h | 11 ----------- linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S | 0 5 files changed, 5 insertions(+), 22 deletions(-) rename linux-user/host/{riscv64 => riscv}/hostdep.h (94%) delete mode 100644 linux-user/host/riscv32/hostdep.h rename linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S (100%) -- 2.25.1 Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/configure b/configure index 039467c04b..d57ad58342 100755 --- a/configure +++ b/configure @@ -570,11 +570,7 @@ elif check_define __s390__ ; then cpu="s390" fi elif check_define __riscv ; then - if check_define _LP64 ; then - cpu="riscv64" - else - cpu="riscv32" - fi + cpu="riscv" elif check_define __arm__ ; then cpu="arm" elif check_define __aarch64__ ; then @@ -587,7 +583,7 @@ ARCH= # Normalise host CPU name and set ARCH. # Note that this case should only have supported host CPUs, not guests. case "$cpu" in - ppc|ppc64|s390x|sparc64|x32|riscv32|riscv64) + ppc|ppc64|s390x|sparc64|x32|riscv) ;; ppc64le) ARCH="ppc64" diff --git a/meson.build b/meson.build index 6b7487b725..1a8fc2c4e0 100644 --- a/meson.build +++ b/meson.build @@ -52,7 +52,7 @@ have_block = have_system or have_tools python = import('python').find_installation() supported_oses = ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', 'sunos', 'linux'] -supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', 'x86_64', +supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64', 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] cpu = host_machine.cpu_family() @@ -342,8 +342,6 @@ if not get_option('tcg').disabled() tcg_arch = 'i386' elif config_host['ARCH'] == 'ppc64' tcg_arch = 'ppc' - elif config_host['ARCH'] in ['riscv32', 'riscv64'] - tcg_arch = 'riscv' endif add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' / tcg_arch, language: ['c', 'cpp', 'objc']) diff --git a/linux-user/host/riscv64/hostdep.h b/linux-user/host/riscv/hostdep.h similarity index 94% rename from linux-user/host/riscv64/hostdep.h rename to linux-user/host/riscv/hostdep.h index 865f0fb9ff..2ba07456ae 100644 --- a/linux-user/host/riscv64/hostdep.h +++ b/linux-user/host/riscv/hostdep.h @@ -5,8 +5,8 @@ * See the COPYING file in the top-level directory. */ -#ifndef RISCV64_HOSTDEP_H -#define RISCV64_HOSTDEP_H +#ifndef RISCV_HOSTDEP_H +#define RISCV_HOSTDEP_H /* We have a safe-syscall.inc.S */ #define HAVE_SAFE_SYSCALL diff --git a/linux-user/host/riscv32/hostdep.h b/linux-user/host/riscv32/hostdep.h deleted file mode 100644 index adf9edbf2d..0000000000 --- a/linux-user/host/riscv32/hostdep.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef RISCV32_HOSTDEP_H -#define RISCV32_HOSTDEP_H - -#endif diff --git a/linux-user/host/riscv64/safe-syscall.inc.S b/linux-user/host/riscv/safe-syscall.inc.S similarity index 100% rename from linux-user/host/riscv64/safe-syscall.inc.S rename to linux-user/host/riscv/safe-syscall.inc.S From patchwork Fri Oct 15 04:09:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515789 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp135416imi; Thu, 14 Oct 2021 21:17:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzjN4sZ2Dg87CcCsjR93HwRXZu3ULcLNlIq2aOEv9DLqVTSL7qbn18xKCWZ98DfFoEuy109 X-Received: by 2002:a05:6e02:893:: with SMTP id z19mr2147042ils.224.1634271466687; Thu, 14 Oct 2021 21:17:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271466; cv=none; d=google.com; s=arc-20160816; b=tmuDW8XTPQHaLixkuC4krRguZaA8BTCAsFj0r+Ud3kk13xBPTrqEaIcrX+OBXPKAKD PMZazNo8amR01rz4eYaeEklddXXUu1xY9gSPIdW94T07XBdkByqyi1Wc5dL1c737H7Qh Oq8ZyOtvyTE4TqiJ5vuURcIcJE0K+SqTOSx+ScItbo7dFihCUF+SAHkPS13I6xVscJkM YRIeJt3wYGdP9iFQntWVJmIZToP5UWCw67Y9fb9pAXa8UR9zpYKvBehPNIpx9FwKZCn1 W+f4ntqnG7MwGIDTcmtDJ3hNWGMpmvqQmyj/3rAZE0LQnyD/jMZpryYcb56ZFd4q54w+ nLAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=A9mkVrBs8KkxTXk1PYgQKfRHS5p1nm/1r22NtGvkuhs=; b=vsx7RLjgvmOKX3iYnEThX0s04q1iCMIwxYQ4aKj83DjuqLWQLG8dfDSrTQ7Lm1Hd+Z HG8+yoeq7tXEf4JxvN7ByOttU9tjT5kgyH602wSHJ3aNKldEDVscP/bfO4kJmD3k0miG kedYnvD1+iI8oq0X2zl2GSA45n9w0oudkcAitLvhD05Yih6vUvCkQ/aIuihAM7py8SHb Q5p4VyJDv4YkWENZvzmW4zbBGz3YgZzpkg+20LHu4xaD8cflKZYUOJkXxVv8Ymv2rP/3 Lr75t9XrRWjxW/sxKMbYJXldS46uMzWUIphRswXIQfFqkC9UeuXT0uovhRrMPC6RcQS2 zv6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LzliRjNY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l12si7819201jak.125.2021.10.14.21.17.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:17:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LzliRjNY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39920 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEfB-0001fA-WB for patch@linaro.org; Fri, 15 Oct 2021 00:17:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38702) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYj-0006nY-Da for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:05 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:42654) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYe-00007j-Sq for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:05 -0400 Received: by mail-pg1-x529.google.com with SMTP id 66so7427845pgc.9 for ; Thu, 14 Oct 2021 21:11:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A9mkVrBs8KkxTXk1PYgQKfRHS5p1nm/1r22NtGvkuhs=; b=LzliRjNYDdOsxA/c9NGwIFQJfFDE7aO7DwVsTbt7JLT5VYBSA6+0JY3pFdQPcAHQEu Wd5QuK6KwWQ5IbUnM9rf9xynkwpWrcX3gXg8uO2mrWfBQ8vgP0eSJwHs1uYnvy9dMht4 Ed6/ZGj+pK4NVmDMZ7rMEZ8FzPpEuO2Hqzoo851XjWX2wckvIxUXG6YuyUuuJ9gZ47YW tjvmp6s50QgV3tdib0WH7vums1uD4kC3J4N5fZTD2rZMtmzb9Ez6FudvOFUEDXW9/kzO rz86vaGdR2llfxh7lJ7/zAHWYX77jgYZgLVyDD/gg89e8h2vQrLYRExIPTyz4P2ujkcG 8HRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A9mkVrBs8KkxTXk1PYgQKfRHS5p1nm/1r22NtGvkuhs=; b=y3VKEt4kD3WR9sVlUDJyKbBcbjR76GoLdUGrPIUYey6elwQTcpaAPobiUe9wrSqfmP 92h6A7VKFZ9GPNkF3OpRcnW1ZhKL3rZJWqrUEzXIsIegN5pshHxbOFPl53hKu+LP87m7 7oT7SYGnvvx+aXkueWihTNnlsGPChGJ/DmuZ2F6qwB2Na0vKLeo/E3r/hFdZ70ilkgBr w+vJCKIjiebr94yZjIC/CNAX7WYhF+jA/tazMjg/2VUDX5qnQauiSO/dTnrDpL1dazPj VwCWKVayj3BTUzxRYPPo7rbShuEWA+6otwQtexpw7wxiR0QMr5pD4vVSeCLlqOpr9xfe Ct3A== X-Gm-Message-State: AOAM532TGNpswZ9iW0eB2b1k9iqai6AedfueVOC3QAJBxSjSMNJHjxU/ YNkr/KduwulwJmC99cRDVfmYCf8jrqD8BA== X-Received: by 2002:a05:6a00:22d1:b0:44c:f752:a216 with SMTP id f17-20020a056a0022d100b0044cf752a216mr9108375pfj.45.1634271059437; Thu, 14 Oct 2021 21:10:59 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.10.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:10:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 06/67] linux-user: Reorg handling for SIGSEGV Date: Thu, 14 Oct 2021 21:09:52 -0700 Message-Id: <20211015041053.2769193-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add stub host-signal.h for all linux-user hosts. Add new code replacing cpu_signal_handler. Full migration will happen one host at a time. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 1 + linux-user/host/arm/host-signal.h | 1 + linux-user/host/i386/host-signal.h | 1 + linux-user/host/mips/host-signal.h | 1 + linux-user/host/ppc/host-signal.h | 1 + linux-user/host/ppc64/host-signal.h | 1 + linux-user/host/riscv/host-signal.h | 1 + linux-user/host/s390/host-signal.h | 1 + linux-user/host/s390x/host-signal.h | 1 + linux-user/host/sparc/host-signal.h | 1 + linux-user/host/sparc64/host-signal.h | 1 + linux-user/host/x32/host-signal.h | 1 + linux-user/host/x86_64/host-signal.h | 1 + linux-user/signal.c | 109 ++++++++++++++++++++++---- 14 files changed, 106 insertions(+), 16 deletions(-) create mode 100644 linux-user/host/aarch64/host-signal.h create mode 100644 linux-user/host/arm/host-signal.h create mode 100644 linux-user/host/i386/host-signal.h create mode 100644 linux-user/host/mips/host-signal.h create mode 100644 linux-user/host/ppc/host-signal.h create mode 100644 linux-user/host/ppc64/host-signal.h create mode 100644 linux-user/host/riscv/host-signal.h create mode 100644 linux-user/host/s390/host-signal.h create mode 100644 linux-user/host/s390x/host-signal.h create mode 100644 linux-user/host/sparc/host-signal.h create mode 100644 linux-user/host/sparc64/host-signal.h create mode 100644 linux-user/host/x32/host-signal.h create mode 100644 linux-user/host/x86_64/host-signal.h -- 2.25.1 diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch64/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/aarch64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/arm/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/i386/host-signal.h b/linux-user/host/i386/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/i386/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/mips/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/ppc/host-signal.h b/linux-user/host/ppc/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/ppc/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/ppc64/host-signal.h b/linux-user/host/ppc64/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/ppc64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/riscv/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/s390/host-signal.h b/linux-user/host/s390/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/s390/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/s390x/host-signal.h b/linux-user/host/s390x/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/s390x/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/sparc/host-signal.h b/linux-user/host/sparc/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/sparc/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/sparc64/host-signal.h b/linux-user/host/sparc64/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/sparc64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/x32/host-signal.h b/linux-user/host/x32/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/x32/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/x86_64/host-signal.h b/linux-user/host/x86_64/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/x86_64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/signal.c b/linux-user/signal.c index 14d8fdfde1..6900acb122 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/bitops.h" #include "exec/gdbstub.h" +#include "hw/core/tcg-cpu-ops.h" #include #include @@ -29,6 +30,7 @@ #include "loader.h" #include "trace.h" #include "signal-common.h" +#include "host-signal.h" static struct target_sigaction sigact_table[TARGET_NSIG]; @@ -769,41 +771,116 @@ static inline void rewind_if_in_safe_syscall(void *puc) } #endif -static void host_signal_handler(int host_signum, siginfo_t *info, - void *puc) +static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) { CPUArchState *env = thread_cpu->env_ptr; CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; - - int sig; target_siginfo_t tinfo; ucontext_t *uc = puc; struct emulated_sigtable *k; + int guest_sig; +#ifdef HOST_SIGNAL_PLACEHOLDER /* the CPU emulator uses some host signals to detect exceptions, we forward to it some signals */ - if ((host_signum == SIGSEGV || host_signum == SIGBUS) + if ((host_sig == SIGSEGV || host_sig == SIGBUS) && info->si_code > 0) { - if (cpu_signal_handler(host_signum, info, puc)) + if (cpu_signal_handler(host_sig, info, puc)) { return; + } } +#else + uintptr_t pc = 0; + bool sync_sig = false; + + /* + * Non-spoofed SIGSEGV and SIGBUS are synchronous, and need special + * handling wrt signal blocking and unwinding. + */ + if ((host_sig == SIGSEGV || host_sig == SIGBUS) && info->si_code > 0) { + MMUAccessType access_type; + uintptr_t host_addr; + abi_ptr guest_addr; + bool is_write; + + host_addr = (uintptr_t)info->si_addr; + + /* + * Convert forcefully to guest address space: addresses outside + * reserved_va are still valid to report via SEGV_MAPERR. + */ + guest_addr = h2g_nocheck(host_addr); + + pc = host_signal_pc(uc); + is_write = host_signal_write(info, uc); + access_type = adjust_signal_pc(&pc, is_write); + + if (host_sig == SIGSEGV) { + const struct TCGCPUOps *tcg_ops; + + if (info->si_code == SEGV_ACCERR && h2g_valid(host_addr)) { + /* If this was a write to a TB protected page, restart. */ + if (is_write && + handle_sigsegv_accerr_write(cpu, &uc->uc_sigmask, + pc, guest_addr)) { + return; + } + + /* + * With reserved_va, the whole address space is PROT_NONE, + * which means that we may get ACCERR when we want MAPERR. + */ + if (page_get_flags(guest_addr) & PAGE_VALID) { + /* maperr = false; */ + } else { + info->si_code = SEGV_MAPERR; + } + } + + sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + + tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, + MMU_USER_IDX, false, pc); + g_assert_not_reached(); + } else { + sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + } + + sync_sig = true; + } +#endif /* get target signal number */ - sig = host_to_target_signal(host_signum); - if (sig < 1 || sig > TARGET_NSIG) + guest_sig = host_to_target_signal(host_sig); + if (guest_sig < 1 || guest_sig > TARGET_NSIG) { return; - trace_user_host_signal(env, host_signum, sig); + } + trace_user_host_signal(env, host_sig, guest_sig); + + host_to_target_siginfo_noswap(&tinfo, info); + k = &ts->sigtab[guest_sig - 1]; + k->info = tinfo; + k->pending = guest_sig; + ts->signal_pending = 1; + +#ifndef HOST_SIGNAL_PLACEHOLDER + /* + * For synchronous signals, unwind the cpu state to the faulting + * insn and then exit back to the main loop so that the signal + * is delivered immediately. + */ + if (sync_sig) { + cpu->exception_index = EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, pc); + } +#endif rewind_if_in_safe_syscall(puc); - host_to_target_siginfo_noswap(&tinfo, info); - k = &ts->sigtab[sig - 1]; - k->info = tinfo; - k->pending = sig; - ts->signal_pending = 1; - - /* Block host signals until target signal handler entered. We + /* + * Block host signals until target signal handler entered. We * can't block SIGSEGV or SIGBUS while we're executing guest * code in case the guest code provokes one in the window between * now and it getting out to the main loop. Signals will be From patchwork Fri Oct 15 04:09:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515788 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp135394imi; Thu, 14 Oct 2021 21:17:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyRSm+HibWWY7nJtbzOlozLqZhBCrB9EFS5vZE4osBkVb68vfIrcApuWTpcUuEjdj1Ia7En X-Received: by 2002:a02:708a:: with SMTP id f132mr7039826jac.72.1634271464278; Thu, 14 Oct 2021 21:17:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271464; cv=none; d=google.com; s=arc-20160816; b=qUz7NW+FwyIZnIDTSKu20SgqwSALU4MrxzMWX/h0r3rAW4emYKL3o8RZedkx/5ytED ch0cEln/h0dJdl3UQCgY/SkWR5UkBKngfN4m6bmIYGbY2+4EEQDsg1barywEpJbhpOCu pKJOF/mBje0C8bE2nat+64l813zv0l07JGOyv9tlGHriCLt//s6wRn20GFUbLqQiyuFP o+08vw2gjdzTmG+IhZJyQNebHSWn76DvCiC0DY0Z47XkKVVTL4/FgWEuJmZSbkLmkDSI i3nX8JEg7qDRfppHURGlLRss3pqSSBBhjRgAYlpfOrjKqSU75KNegPiJswp5Mp/qgWCZ a81g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wzln/o2XfkekbyzBBOI7m5kdlAVyzk60/sywPn/m1vM=; b=QINWuGBb/Tgds1unCklPWkrApSOJvsqHUIW9qU1eH/mDWqqWco4ZodEVQgC3sDIjzx +sYjTBFPcL8eZHAjiz7wbhqpRSbeNuyBNkIlcoBSdjJZEotZ3Ukpq91lFx6ZwmIsoeq1 kLvO9DigDbYeSZzzgMMd73wfbZICJOEYXqr9AlUE1mlgE6i4kEUPrdxczRqZka+GquNl Q3v6W1vlvzNbFyrcsgAieF19+u6AJpm63f2Q7qlhBXA6Rb+ZZAMD0OgM3bEZMpHgR02q 3Sh22vQgrzM0ktHcEz0+bBSYsRTjvGGyH6IXslgjakep8Metv2nvSb/pLVodypZphY9o jT/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mPnWzmZV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n16si5618449ioj.18.2021.10.14.21.17.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:17:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mPnWzmZV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39884 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEf9-0001dw-KT for patch@linaro.org; Fri, 15 Oct 2021 00:17:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38700) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYh-0006js-IM for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:03 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:45634) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYf-00008T-Hk for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:03 -0400 Received: by mail-pl1-x629.google.com with SMTP id s1so3778728plg.12 for ; Thu, 14 Oct 2021 21:11:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wzln/o2XfkekbyzBBOI7m5kdlAVyzk60/sywPn/m1vM=; b=mPnWzmZVnHWYkIxbgNTb8MUhag1MYGh6i2euExc/Y4f6URfsamntIBvGu9pp7+Q7h0 LFFRxeLT7vDnex+74ErhuQQ0MuKcb9fio1R9gtwdwXSNogEkbcZOyGHBsklrRj7LFJKJ wOHPwDkwartv6bQlGDTBJOybnP94FijRVTa+XgL7/zdJvz3kV1HpE771uhI0i4zK2o+O WotcA5toufANlumsf4s/7HDlcn5b+xFL5GnjQPCWMqLuVfo0Cg/Els6VACNKBPuUuiOJ vN4INObUmueeZTRfv1yyIkAKDU9o/2Vphjy1PYWPA4qnQmwDMsvj5qiZfLvn73McwKwF nQaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wzln/o2XfkekbyzBBOI7m5kdlAVyzk60/sywPn/m1vM=; b=3RnQmPYYyjHFrOc3LiyonrrynLdXen54T7MgD6T8Nhv0T7HSspnP/VE7OswrV/GfQt ZfeZdFNI0ckAVKxUjmSV5O7qwUC+9nD8tg5nPLVyQ6FHmCVUWFKZyjxRNZwF4S0LlKo3 I+us9+82JpssPaKIrURY2lb0LClPtTiDHsm0B5VbaLZlzObBej0/LbkMlSk52In/fsOJ 5M1Tn+yRQiLnEmvU0mTCvxTPfVWTdyUGubL+joKzsw27cNl4mTSSRIrIjv+mk5OtdEQ8 w85B233OSuUwZk+kKNZFe6clDt89+pv3rqNDVzFb14mJ1GbYBR64jVzuReC5n4SULzeL /BAg== X-Gm-Message-State: AOAM533i3fDh9sLuLR1Ukpgpj0dUFmVie/0YZFcY5FAOwFcMz6VIr2mW 0BS0LH9m8QJ+QUUOjAtJzg6q125qW3uf5w== X-Received: by 2002:a17:902:ab17:b0:13e:b2e0:58b with SMTP id ik23-20020a170902ab1700b0013eb2e0058bmr9004421plb.9.1634271060073; Thu, 14 Oct 2021 21:11:00 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.10.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:10:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 07/67] linux-user/host/x86: Populate host_signal.h Date: Thu, 14 Oct 2021 21:09:53 -0700 Message-Id: <20211015041053.2769193-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson --- linux-user/host/i386/host-signal.h | 25 ++++- linux-user/host/x32/host-signal.h | 2 +- linux-user/host/x86_64/host-signal.h | 25 ++++- accel/tcg/user-exec.c | 136 +-------------------------- 4 files changed, 50 insertions(+), 138 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/linux-user/host/i386/host-signal.h b/linux-user/host/i386/host-signal.h index f4b4d65031..ccbbee5082 100644 --- a/linux-user/host/i386/host-signal.h +++ b/linux-user/host/i386/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef I386_HOST_SIGNAL_H +#define I386_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_EIP]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe + && (uc->uc_mcontext.gregs[REG_ERR] & 0x2); +} + +#endif diff --git a/linux-user/host/x32/host-signal.h b/linux-user/host/x32/host-signal.h index f4b4d65031..26800591d3 100644 --- a/linux-user/host/x32/host-signal.h +++ b/linux-user/host/x32/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../x86_64/host-signal.h" diff --git a/linux-user/host/x86_64/host-signal.h b/linux-user/host/x86_64/host-signal.h index f4b4d65031..883d2fcf65 100644 --- a/linux-user/host/x86_64/host-signal.h +++ b/linux-user/host/x86_64/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef X86_64_HOST_SIGNAL_H +#define X86_64_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_RIP]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe + && (uc->uc_mcontext.gregs[REG_ERR] & 0x2); +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 744af19397..474cb9cf82 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -29,19 +29,6 @@ #include "trace/trace-root.h" #include "internal.h" -#undef EAX -#undef ECX -#undef EDX -#undef EBX -#undef ESP -#undef EBP -#undef ESI -#undef EDI -#undef EIP -#ifdef __linux__ -#include -#endif - __thread uintptr_t helper_retaddr; //#define DEBUG_SIGNAL @@ -268,123 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__i386__) - -#if defined(__NetBSD__) -#include -#include - -#define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__FreeBSD__) || defined(__DragonFly__) -#include -#include - -#define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip)) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) -#define ERROR_sig(context) ((context)->uc_mcontext.mc_err) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__OpenBSD__) -#include -#define EIP_sig(context) ((context)->sc_eip) -#define TRAP_sig(context) ((context)->sc_trapno) -#define ERROR_sig(context) ((context)->sc_err) -#define MASK_sig(context) ((context)->sc_mask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#else -#define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP 0xe -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; -#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) - ucontext_t *uc = puc; -#elif defined(__OpenBSD__) - struct sigcontext *uc = puc; -#else - ucontext_t *uc = puc; -#endif - unsigned long pc; - int trapno; - -#ifndef REG_EIP -/* for glibc 2.1 */ -#define REG_EIP EIP -#define REG_ERR ERR -#define REG_TRAPNO TRAPNO -#endif - pc = EIP_sig(uc); - trapno = TRAP_sig(uc); - return handle_cpu_signal(pc, info, - trapno == PAGE_FAULT_TRAP ? - (ERROR_sig(uc) >> 1) & 1 : 0, - &MASK_sig(uc)); -} - -#elif defined(__x86_64__) - -#ifdef __NetBSD__ -#include -#define PC_sig(context) _UC_MACHINE_PC(context) -#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__OpenBSD__) -#include -#define PC_sig(context) ((context)->sc_rip) -#define TRAP_sig(context) ((context)->sc_trapno) -#define ERROR_sig(context) ((context)->sc_err) -#define MASK_sig(context) ((context)->sc_mask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__FreeBSD__) || defined(__DragonFly__) -#include -#include - -#define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip)) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) -#define ERROR_sig(context) ((context)->uc_mcontext.mc_err) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#else -#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP 0xe -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - unsigned long pc; -#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) - ucontext_t *uc = puc; -#elif defined(__OpenBSD__) - struct sigcontext *uc = puc; -#else - ucontext_t *uc = puc; -#endif - - pc = PC_sig(uc); - return handle_cpu_signal(pc, info, - TRAP_sig(uc) == PAGE_FAULT_TRAP ? - (ERROR_sig(uc) >> 1) & 1 : 0, - &MASK_sig(uc)); -} - -#elif defined(_ARCH_PPC) +#if defined(_ARCH_PPC) /*********************************************************************** * signal context platform-specific definitions @@ -895,11 +766,6 @@ int cpu_signal_handler(int host_signum, void *pinfo, return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } - -#else - -#error host CPU specific signal handler needed - #endif /* The softmmu versions of these helpers are in cputlb.c. */ From patchwork Fri Oct 15 04:09:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515790 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp135430imi; Thu, 14 Oct 2021 21:17:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxPTagVgTGaw7a9WknV6JkuLlzxQQWjMav6CMEdBOJqlDVRXEMOyOjDhBDGVKE/BVPtwieS X-Received: by 2002:a92:c112:: with SMTP id p18mr2093243ile.61.1634271468304; Thu, 14 Oct 2021 21:17:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271468; cv=none; d=google.com; s=arc-20160816; b=dvE+fosnebBWXtQ4xHe+W07irumUSowBkqUG4ogJzv+wg8N3HGCFjP5cm87Wu/iRei Yk51wd1JIDlmPlJ6YgchM2nhd/kzIaEiw3Br3nXniVaYe9WDO6rY9b8DBbDeKpFODqj3 +Ff96loVJBjHrgsx4Z5mhV1OqpHe15C/8l1fvvFOOlENWLHyHtBnRyr/uMdsoViM32sV ltPb2MchYScbGz6P79HYWIN1IZ/Xxtj0hLxxr8vlBFZtEckm1N9t5CLMbGbmqmfSBBYr 8GCRWrjMW1p8jwK+7GDsZMApGXS8By80nYqa91iORYXyH7VjDAoNCKemlTUtZWArgqw9 KGZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mZJwf7vUbtVzNt6WsxVhQTwK2EfiB3pa1Mn8uyvrhI4=; b=M9z4qAMgP508BBEqhFNOUUEJIAk4EWl1d7b2ZI4LvVVu4dV5u6jVdtuMhCTXWINeLU oc2a4+9Bk11X3Tdz6IYXpzh04jltD2Yt1qn3/KOgDeRYBA1ik7sBq/H4w5WGM8CELhuf XtULoTproJABy7PFCmNESIoCrV+NIDmcTFvsK4Z+N+Q0dbQUR1VqqMMEYdRaL0jRVuab GCCm1H3f38W6o0BE27HWnSj6LTBHhHnIC7/4WMT1gLN3oVOVJynLmE//2lf9ffxUvxMD 45hWY67f3hPCmAj9+RvIZ6VMlU4jy5NMvzSwIoZen6VBXADX57Ij4PvF4Zv2KhBa4rOl es0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gWmcTobF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ay11si6746073jab.119.2021.10.14.21.17.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:17:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gWmcTobF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39996 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEfD-0001hz-LH for patch@linaro.org; Fri, 15 Oct 2021 00:17:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYm-0006yL-I9 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:08 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:35603) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYj-0000B6-Ew for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:08 -0400 Received: by mail-pf1-x42d.google.com with SMTP id c29so7319846pfp.2 for ; Thu, 14 Oct 2021 21:11:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mZJwf7vUbtVzNt6WsxVhQTwK2EfiB3pa1Mn8uyvrhI4=; b=gWmcTobFCd0EJRqpTcf30s/KZwMfLMTvTUd0k1gbTVKI+jOQx/2FugOpJFqLeunKt4 d0FwtPoTDeBZRI+m/nUlYnsXDICe5eksAEedefTeJfOmqbPBr/UbdhBRVC7QN31pz0XA pnCuHF9rYAg6Os7z7Irg95CpOGbbXKPJ0nDamJtqNG63dyZtixNNxRv/tldnZMH9oEnW qRQEgGoDZ1wbiKbxUJhKouk8WkV2KOqmMaAT00Bb9tAcv1f2ytwPd25EE/Y/SotLBMvV QelRouqiKNCBBlWJDctTTQC13EP8SDqYTyNee5cIVbxv0FXCcbaIEgPUxrbN140WpnBX /RzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mZJwf7vUbtVzNt6WsxVhQTwK2EfiB3pa1Mn8uyvrhI4=; b=uj7fxa4Emwe/EFAR60jQmKK4zXGZn07XEmpZHG5tx5RjUhYfB31Y8ekNJ/IC2WgjSh DSOCVejgBEHP8ajIeZHS9jD2bMkL6SDhxoAKh+9VD07F8tdyPIn+oQZuVTSWry2l5866 CXy88NGoRYpybVPFQGNimLo3tb96p8mnZrcvIXgbTTDzkfBkWb7z6HOwr+FUYZTx3OW4 ZwaiYonVsg/IDM5zC7yrSu6ubf8+5UkEgK0nT37PL7wyKU3V2N01934Smc6At07EuIOx 6YumcpNBWS8879n79a9GfhmQ9RtIpqN59fA/7U/PSbyItIM6hxWVULKO1RXLHCeJiCxj 3a3A== X-Gm-Message-State: AOAM532+tWHKNFdzQt/FiircJ+wgVRkpr0X5hg9mXw+AAbBNllsb8zdm wSs578JNnn308iUmkDe6BdycS9jzcAZhcA== X-Received: by 2002:a62:1553:0:b0:44c:67cf:e669 with SMTP id 80-20020a621553000000b0044c67cfe669mr9411921pfv.55.1634271061670; Thu, 14 Oct 2021 21:11:01 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 08/67] linux-user/host/ppc: Populate host_signal.h Date: Thu, 14 Oct 2021 21:09:54 -0700 Message-Id: <20211015041053.2769193-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- linux-user/host/ppc/host-signal.h | 25 ++++++++- linux-user/host/ppc64/host-signal.h | 2 +- accel/tcg/user-exec.c | 79 +---------------------------- 3 files changed, 26 insertions(+), 80 deletions(-) -- 2.25.1 diff --git a/linux-user/host/ppc/host-signal.h b/linux-user/host/ppc/host-signal.h index f4b4d65031..e09756c691 100644 --- a/linux-user/host/ppc/host-signal.h +++ b/linux-user/host/ppc/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef PPC_HOST_SIGNAL_H +#define PPC_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.regs->nip; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.regs->trap != 0x400 + && (uc->uc_mcontext.regs->dsisr & 0x02000000); +} + +#endif diff --git a/linux-user/host/ppc64/host-signal.h b/linux-user/host/ppc64/host-signal.h index f4b4d65031..a353c22a90 100644 --- a/linux-user/host/ppc64/host-signal.h +++ b/linux-user/host/ppc64/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../ppc/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 474cb9cf82..e0cc765069 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,84 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(_ARCH_PPC) - -/*********************************************************************** - * signal context platform-specific definitions - * From Wine - */ -#ifdef linux -/* All Registers access - only for local access */ -#define REG_sig(reg_name, context) \ - ((context)->uc_mcontext.regs->reg_name) -/* Gpr Registers access */ -#define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) -/* Program counter */ -#define IAR_sig(context) REG_sig(nip, context) -/* Machine State Register (Supervisor) */ -#define MSR_sig(context) REG_sig(msr, context) -/* Count register */ -#define CTR_sig(context) REG_sig(ctr, context) -/* User's integer exception register */ -#define XER_sig(context) REG_sig(xer, context) -/* Link register */ -#define LR_sig(context) REG_sig(link, context) -/* Condition register */ -#define CR_sig(context) REG_sig(ccr, context) - -/* Float Registers access */ -#define FLOAT_sig(reg_num, context) \ - (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num]) -#define FPSCR_sig(context) \ - (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4))) -/* Exception Registers access */ -#define DAR_sig(context) REG_sig(dar, context) -#define DSISR_sig(context) REG_sig(dsisr, context) -#define TRAP_sig(context) REG_sig(trap, context) -#endif /* linux */ - -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) -#include -#define IAR_sig(context) ((context)->uc_mcontext.mc_srr0) -#define MSR_sig(context) ((context)->uc_mcontext.mc_srr1) -#define CTR_sig(context) ((context)->uc_mcontext.mc_ctr) -#define XER_sig(context) ((context)->uc_mcontext.mc_xer) -#define LR_sig(context) ((context)->uc_mcontext.mc_lr) -#define CR_sig(context) ((context)->uc_mcontext.mc_cr) -/* Exception Registers access */ -#define DAR_sig(context) ((context)->uc_mcontext.mc_dar) -#define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_exc) -#endif /* __FreeBSD__|| __FreeBSD_kernel__ */ - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) - ucontext_t *uc = puc; -#else - ucontext_t *uc = puc; -#endif - unsigned long pc; - int is_write; - - pc = IAR_sig(uc); - is_write = 0; -#if 0 - /* ppc 4xx case */ - if (DSISR_sig(uc) & 0x00800000) { - is_write = 1; - } -#else - if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) { - is_write = 1; - } -#endif - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__alpha__) +#if defined(__alpha__) int cpu_signal_handler(int host_signum, void *pinfo, void *puc) From patchwork Fri Oct 15 04:09:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515793 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp136524imi; Thu, 14 Oct 2021 21:19:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwH+wf8AjE9YbBz7nsquvS2fwHHN8HH1/g32tVTur62mBNRAp7VygfP/9mTULXEsAZJjCFS X-Received: by 2002:a05:6e02:1649:: with SMTP id v9mr2253502ilu.171.1634271598763; Thu, 14 Oct 2021 21:19:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271598; cv=none; d=google.com; s=arc-20160816; b=MBePT52KYdtuy9/mEHVJTIk3Upfep9hrrzTeYfLAfyjlThSdQZEGeYlljcGt94Y7Oa qsKO9WW+EncLzuJ554uQVuxGxAiKdnvQpIUtdC4GyxxbcxjqniBvk6VlMI5zyVkTV6lX a0WapJarrrWV9FczKyp+fSns+OEzpqSoxd4SJ7rf/VCWNObhbgJudzmpcgPSuJpFM+I8 oOqnyS7sR7XmC4+6nz8R3mnQcF+g1nr/i0+2lzLeu8wyWhgy+ifEygm3PIN1n2X3/6bD 3kC4xX8du/Wvg9s7h0S0A4YJrnguiHeXLeNdNV9W74+xdPpz3+Dd9poXKy9n0vxjt06n s7UQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BJUdaZcFQkGn0Ur44U4wi+Gizq9wqvJWic/PiqjpH80=; b=U7K741a2vijZv3FdlRZnwr9dSNiZHGg8pH0Hap4ekfUQSPVnZ3FvH5JIWdC3ozJwm4 ZPd8oj4HCuzWgfU+dhXlAoVNwdj38qbNABKTchfgCqCrMNnB0AvDf+BRTY/yZl5jyte8 QwvGLwzvwdHNTKOUydQB8n5NtYR3M/UtSMq5FSpK1j/JM53HFDhF/yUOehBpvVIZtWIy 2YcFHdoQsc2AgtrhyvncGNIRvRLJlqGrA5dSa2VDG0g5B7N0K3PiA40D5V+624hzH1pg SujCIvWCXwzhiZf9dWbE5/vqLJrAe/iHgCLhcNZRFFsk99bBG//c8vwm5rAON50lDYzG QwZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=H8DucyRd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/alpha/host-signal.h | 41 +++++++++++++++++++++++++++++ accel/tcg/user-exec.c | 31 +--------------------- 2 files changed, 42 insertions(+), 30 deletions(-) create mode 100644 linux-user/host/alpha/host-signal.h -- 2.25.1 diff --git a/linux-user/host/alpha/host-signal.h b/linux-user/host/alpha/host-signal.h new file mode 100644 index 0000000000..e27704d832 --- /dev/null +++ b/linux-user/host/alpha/host-signal.h @@ -0,0 +1,41 @@ +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef ALPHA_HOST_SIGNAL_H +#define ALPHA_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.sc_pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t *pc = (uint32_t *)host_signal_pc(uc); + uint32_t insn = *pc; + + /* XXX: need kernel patch to get write flag faster */ + switch (insn >> 26) { + case 0x0d: /* stw */ + case 0x0e: /* stb */ + case 0x0f: /* stq_u */ + case 0x24: /* stf */ + case 0x25: /* stg */ + case 0x26: /* sts */ + case 0x27: /* stt */ + case 0x2c: /* stl */ + case 0x2d: /* stq */ + case 0x2e: /* stl_c */ + case 0x2f: /* stq_c */ + return true; + } + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e0cc765069..0db3c5cf3c 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,36 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__alpha__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - uint32_t *pc = uc->uc_mcontext.sc_pc; - uint32_t insn = *pc; - int is_write = 0; - - /* XXX: need kernel patch to get write flag faster */ - switch (insn >> 26) { - case 0x0d: /* stw */ - case 0x0e: /* stb */ - case 0x0f: /* stq_u */ - case 0x24: /* stf */ - case 0x25: /* stg */ - case 0x26: /* sts */ - case 0x27: /* stt */ - case 0x2c: /* stl */ - case 0x2d: /* stq */ - case 0x2e: /* stl_c */ - case 0x2f: /* stq_c */ - is_write = 1; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#elif defined(__sparc__) +#if defined(__sparc__) int cpu_signal_handler(int host_signum, void *pinfo, void *puc) From patchwork Fri Oct 15 04:09:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515786 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp133821imi; Thu, 14 Oct 2021 21:14:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwy4/j+J1V3c0aF00+QdM1W3A3pr2xzRzeJHy/F0apEHrsNu8oSJvjP+mRQE4GsDis51j1X X-Received: by 2002:a92:cbc2:: with SMTP id s2mr2227327ilq.228.1634271276259; Thu, 14 Oct 2021 21:14:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271276; cv=none; d=google.com; s=arc-20160816; b=HNl2jcVUAdV8U7MRPkbrN9aV9uLMHfsLhMbr8qzBgYLmo2YRqZIvBuYwXACLX4w+RF gsM/FOA2vYP2PwYqpKrVV+H6uXGM+I4nIsNdx9jFJP4PCLuHI5njOE7ydHqbg7I6g0NN YdY5TVnPZZ67ivMMKpW552McmXoYl4BGo77EXcXB2ghKdbWNiopp1hSovhe/GKsF4IGF QLbbmEwxHZ5fWc48VGHUYjsy6Eymqnw+8ovhAEdfVRm21p8a5o7AODZiRWn+KeoTJQMz /LLcYrFGlqmJi5qz+PTRN7XrUnDIxs0/ls7vs6L+UmjdF62kCKS+83ycLas/EZSM5itp f9PQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=eZX7omI0tPPRPhD891DSXxNdsSqSoW7wps3jDTVHJCM=; b=blhm1+qVqlCYTNzZv+Wad2uQJG308t9f8bCesB57SCJ8uKXnNJGVLjHnQJkhBIHbyX lX29LfogGF9Iqdfef0IsKFIkAYnrD7hHUHLGUEcLyjt4bGtAAviwUe5h/4gZwVnsH6Qs 50JEJqmGX7rD1iFoqp3PXZ8z0ZMeiwIZNMCE3r0g3XtqaPDndJPqqC1taI3EXl2WYvEP Jogf00xT4EIyJkv5lKcNts7jejHmzKYIpFBKokdxtuFbivxAHWhojwbaAgvia0Mq/UwJ yA40nkcWdYQDw41fYkJ2hBuu5xsPt7C/lkYZGpLwWOTOVkp0PhPLAzJthOugIfzAIZmR LFIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=lWSV+ihw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Drop the *BSD code, to be re-created under bsd-user/ later. Drop the Solaris code as completely unused. Signed-off-by: Richard Henderson --- linux-user/host/sparc/host-signal.h | 54 ++++++++++++++++++++++- linux-user/host/sparc64/host-signal.h | 2 +- accel/tcg/user-exec.c | 62 +-------------------------- 3 files changed, 55 insertions(+), 63 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/linux-user/host/sparc/host-signal.h b/linux-user/host/sparc/host-signal.h index f4b4d65031..232943a1db 100644 --- a/linux-user/host/sparc/host-signal.h +++ b/linux-user/host/sparc/host-signal.h @@ -1 +1,53 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef SPARC_HOST_SIGNAL_H +#define SPARC_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ +#ifdef __arch64__ + return uc->uc_mcontext.mc_gregs[MC_PC]; +#else + return uc->uc_mcontext.gregs[REG_PC]; +#endif +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn = *(uint32_t *)host_signal_pc(uc); + + if ((insn >> 30) == 3) { + switch ((insn >> 19) & 0x3f) { + case 0x05: /* stb */ + case 0x15: /* stba */ + case 0x06: /* sth */ + case 0x16: /* stha */ + case 0x04: /* st */ + case 0x14: /* sta */ + case 0x07: /* std */ + case 0x17: /* stda */ + case 0x0e: /* stx */ + case 0x1e: /* stxa */ + case 0x24: /* stf */ + case 0x34: /* stfa */ + case 0x27: /* stdf */ + case 0x37: /* stdfa */ + case 0x26: /* stqf */ + case 0x36: /* stqfa */ + case 0x25: /* stfsr */ + case 0x3c: /* casa */ + case 0x3e: /* casxa */ + return true; + } + } + return false; +} + +#endif diff --git a/linux-user/host/sparc64/host-signal.h b/linux-user/host/sparc64/host-signal.h index f4b4d65031..1191fe2d40 100644 --- a/linux-user/host/sparc64/host-signal.h +++ b/linux-user/host/sparc64/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../sparc/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0db3c5cf3c..17fe867aeb 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,67 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__sparc__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - int is_write; - uint32_t insn; -#if !defined(__arch64__) || defined(CONFIG_SOLARIS) - uint32_t *regs = (uint32_t *)(info + 1); - void *sigmask = (regs + 20); - /* XXX: is there a standard glibc define ? */ - unsigned long pc = regs[1]; -#else -#ifdef __linux__ - struct sigcontext *sc = puc; - unsigned long pc = sc->sigc_regs.tpc; - void *sigmask = (void *)sc->sigc_mask; -#elif defined(__OpenBSD__) - struct sigcontext *uc = puc; - unsigned long pc = uc->sc_pc; - void *sigmask = (void *)(long)uc->sc_mask; -#elif defined(__NetBSD__) - ucontext_t *uc = puc; - unsigned long pc = _UC_MACHINE_PC(uc); - void *sigmask = (void *)&uc->uc_sigmask; -#endif -#endif - - /* XXX: need kernel patch to get write flag faster */ - is_write = 0; - insn = *(uint32_t *)pc; - if ((insn >> 30) == 3) { - switch ((insn >> 19) & 0x3f) { - case 0x05: /* stb */ - case 0x15: /* stba */ - case 0x06: /* sth */ - case 0x16: /* stha */ - case 0x04: /* st */ - case 0x14: /* sta */ - case 0x07: /* std */ - case 0x17: /* stda */ - case 0x0e: /* stx */ - case 0x1e: /* stxa */ - case 0x24: /* stf */ - case 0x34: /* stfa */ - case 0x27: /* stdf */ - case 0x37: /* stdfa */ - case 0x26: /* stqf */ - case 0x36: /* stqfa */ - case 0x25: /* stfsr */ - case 0x3c: /* casa */ - case 0x3e: /* casxa */ - is_write = 1; - break; - } - } - return handle_cpu_signal(pc, info, is_write, sigmask); -} - -#elif defined(__arm__) +#if defined(__arm__) #if defined(__NetBSD__) #include From patchwork Fri Oct 15 04:09:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515783 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp133809imi; Thu, 14 Oct 2021 21:14:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJylB6dFZBE2J5CNWCNtnrrIksNqFS6BK1WiL+NxAAOG7koNlZjq1l+TrYxGjJU+RUaGHa2r X-Received: by 2002:a25:bb8b:: with SMTP id y11mr10020433ybg.384.1634271275406; Thu, 14 Oct 2021 21:14:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271275; cv=none; d=google.com; s=arc-20160816; b=IMJ3lwn/JssoF6JsVhl0g3OT56L9aUnv66Xf/L95mMmLRF/DBrzbDVRYW7lygxy4BA XxmY5aKoDIwteEn3pH+rB7mKo6VLQasu7vDBeymHfN/PRBBKTH9FUZ3XvHkkYOzVlBQq qlxEgap0Ln9a0PhaVTIO6a6XNn1w02g0Ti5djergt31rGExn1GxWLshyrW8IY4IVHgzu L34RMxY/BBiLCH8Jo901qFDrh3Su2GgipZA07Fvdt9sJESt70sVzOz6sLPaBh4sBLTXO JymwYZ60Bqvq4K1YcQo2WBbTFhsitTvnYDe4FA7pCKxPoLsVVPBtMQapNUf9I41rCnnB mqTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=btQGr7frnhamoWbiryuObxAGescEK943qi/jomZ8OHU=; b=zUR8zqvtKzeUL8BJjy8hG8OOIk1nkzsWUW5HSi3fQCPkjK3+6pyMPn/0QoyKKCFmPX gsg3zh4euScsFsXUGE2XiRhKgrdYrOINEg57vqdS/9a1Kw+yDk63WwFYWiAToMdVvPSY Y+ECmqV8Emtm7KtAR0AV51HNHQMRg8lqBzUEFZByPJnN1vnXYHTDzXKEHedS2DSny7oj 4ov9RjKvFZurKTSWcIEfVy2AzmxIppcoe1h97J+LvaBh2Q5GpJWW1D2fLPWLtKhAsAsO OTuk1UvVPXHZ1szZvz6kBjhGoc51sJbPE1yAUIWgGzwbyAtyenyVUdq/XEtLfY9mtzLE fi7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LOcVIOc7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/arm/host-signal.h | 30 ++++++++++++++++++++- accel/tcg/user-exec.c | 45 +------------------------------ 2 files changed, 30 insertions(+), 45 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-signal.h index f4b4d65031..6932224c1c 100644 --- a/linux-user/host/arm/host-signal.h +++ b/linux-user/host/arm/host-signal.h @@ -1 +1,29 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef ARM_HOST_SIGNAL_H +#define ARM_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.arm_pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + /* + * In the FSR, bit 11 is WnR, assuming a v6 or + * later processor. On v5 we will always report + * this as a read, which will fail later. + */ + uint32_t fsr = uc->uc_mcontext.error_code; + return extract32(fsr, 11, 1); +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 17fe867aeb..5656c654e1 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,50 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__arm__) - -#if defined(__NetBSD__) -#include -#include -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; -#if defined(__NetBSD__) - ucontext_t *uc = puc; - siginfo_t *si = pinfo; -#else - ucontext_t *uc = puc; -#endif - unsigned long pc; - uint32_t fsr; - int is_write; - -#if defined(__NetBSD__) - pc = uc->uc_mcontext.__gregs[_REG_R15]; -#elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) - pc = uc->uc_mcontext.gregs[R15]; -#else - pc = uc->uc_mcontext.arm_pc; -#endif - -#ifdef __NetBSD__ - fsr = si->si_trap; -#else - fsr = uc->uc_mcontext.error_code; -#endif - /* - * In the FSR, bit 11 is WnR, assuming a v6 or - * later processor. On v5 we will always report - * this as a read, which will fail later. - */ - is_write = extract32(fsr, 11, 1); - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__aarch64__) +#if defined(__aarch64__) #if defined(__NetBSD__) From patchwork Fri Oct 15 04:09:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515794 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp137206imi; Thu, 14 Oct 2021 21:21:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwbCIN6xPC6juwd1VXAIPfmDNGrS0ILjKjh5ExsRkkJzDZ2WqR/4h6EnY/3Q0uNHKC15zqC X-Received: by 2002:a25:d3cb:: with SMTP id e194mr10557804ybf.351.1634271680878; Thu, 14 Oct 2021 21:21:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271680; cv=none; d=google.com; s=arc-20160816; b=okxmohyRKIoLn+dVFpeNkGZBbUBHMW3BOWu6Rg4IjkBp8ShxlFGY2pgmLgnkHieYsH VCJfbVP6SdYBR9LaHMdumnZtNj09MMDwmU+UWJax6ac/fmBwxjmcKcjfuZZCk6HAzq3F a44C8NAyRvorB5EGuE9AAIa/h9vr9jMfSl04GIYH2KjtjH6yhO8zOsPwBQs8z3x1MaL4 UBhGVJEKrCgniLGbHHzQEf/Ak6xE0WnlrZosdcjbPKoU/h4TgWktXkmsGPaPztdBEAZS 4sgwBkuLVysPNr1+G475sBoKdluJM4h53eGrlRvXc4VcnOq3gSjsJ4bGoEwqR7EioCmm kKfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UZZkbCa2SkEzYuf3z0736s28yeuiumq4AY1dzCd1e9I=; b=UPcsE1o+VxvAKbxiZbqBNgm4626VdX8f+YIbcERuBaMBcBcAOs13MNE2e1j+KnszHM oHHhrgFfgOanl/JxOFHONOFWhH1hGqkKqx1C9N3P4/s+L+v0TUkaYHh56NG2Y8OACoWY B0nvT66LcfHtMdjiKNQqwaSTylCIaja5CSGdqPs30K8LcBom+lh+Ix+seNrPtORWGfTm KFrJSzR7gZBhpGJnaRw/AWgiVLh20XKBQf/Tdy49GitfKAidBorzQ3NJFNebkMNUpJ6P ZcRCXsfzrKi1XH6HB9PBkmo1es9EoVrYIWrMzCB1Cz1lM13xkz+75x8mVmoiLnxIRl+i dwng== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cVrD63Nq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f13si7191978ybj.493.2021.10.14.21.21.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:21:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cVrD63Nq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51682 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEie-00015o-56 for patch@linaro.org; Fri, 15 Oct 2021 00:21:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYp-00074p-2L for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:11 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:45640) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYl-0000Dt-4r for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:10 -0400 Received: by mail-pl1-x62f.google.com with SMTP id s1so3778890plg.12 for ; Thu, 14 Oct 2021 21:11:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UZZkbCa2SkEzYuf3z0736s28yeuiumq4AY1dzCd1e9I=; b=cVrD63NqDChG2gle/bJX5ee3Cubsz/ViBK52ZdyducVxDuZsLgZtxo4Hl8cIHRhyw4 JZDRzNOhNhnmpYOPLKpFsFfugolmvCpmOvhgnASIwygLWLkDPCXuhqZvCqn8V25gfoL4 h1zr6FisQ0I7U1rAkI2mtV/F1L3vcJs7JFaWU5eqkt17hBYlY4ooEx+O+ug01qnKfAeX hCqQ9z9hIsl3Vt2LEBGdxQXP8xjO1+A2l5Gi8ZuTgI1V6NDsg3VF+vPkIZmBToAsww2v fvr6WuVs0Y0DJJ/rdrpjtUbP6YmUty9JGMR20qU6XOQeXzKWqQk7My8gZBsu8aQ0OGDX anig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UZZkbCa2SkEzYuf3z0736s28yeuiumq4AY1dzCd1e9I=; b=Gynxz23Ae9PSn0OtMPpJHuep8N0wy+2ADZT9MoJq3V2zYMCCAARHlP7DF+4nQLPqKZ qI3z1zJQiiOiNdNg9lhu3dFP1TEjers5n61YZxlibK/RDMWNOlyynhCtxq+8p5yN6B4P Q58KUTIoS9DZgojgr0Aiw0sL0s8/Lerm9+h19DeNSbTLqrNzUcyjU4/eXA/AK6rIqSiP AGVhjF1va8PX1Y+/doLLxEgaCxZ1bC1/iGKZV1pggtPY8p3U76yE8OHaKgdoNDaJ30/i RJMfbIIYLF4GiOxHCr7nBlf9vTwtGaNFECCpIOfnw4a8WcEsEq8+hNWEnrUth21hYzuo XX9A== X-Gm-Message-State: AOAM533q7GvCxJw04m+ru7UuGm4CNoikUBBX1+kiAhtL0WgIE8DP4ivu 2H/FP/XwHAXqACwuKnjJDh4NSfPvYOc4QQ== X-Received: by 2002:a17:90a:f292:: with SMTP id fs18mr10561071pjb.229.1634271065783; Thu, 14 Oct 2021 21:11:05 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 12/67] linux-user/host/aarch64: Populate host_signal.h Date: Thu, 14 Oct 2021 21:09:58 -0700 Message-Id: <20211015041053.2769193-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 74 ++++++++++++++++++++- accel/tcg/user-exec.c | 94 +-------------------------- 2 files changed, 74 insertions(+), 94 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch64/host-signal.h index f4b4d65031..02a55c3372 100644 --- a/linux-user/host/aarch64/host-signal.h +++ b/linux-user/host/aarch64/host-signal.h @@ -1 +1,73 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef AARCH64_HOST_SIGNAL_H +#define AARCH64_HOST_SIGNAL_H + +/* Pre-3.16 kernel headers don't have these, so provide fallback definitions */ +#ifndef ESR_MAGIC +#define ESR_MAGIC 0x45535201 +struct esr_context { + struct _aarch64_ctx head; + uint64_t esr; +}; +#endif + +static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) +{ + return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; +} + +static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) +{ + return (struct _aarch64_ctx *)((char *)hdr + hdr->size); +} + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + struct _aarch64_ctx *hdr; + uint32_t insn; + + /* Find the esr_context, which has the WnR bit in it */ + for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) { + if (hdr->magic == ESR_MAGIC) { + struct esr_context const *ec = (struct esr_context const *)hdr; + uint64_t esr = ec->esr; + + /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ + return extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; + } + } + + /* + * Fall back to parsing instructions; will only be needed + * for really ancient (pre-3.16) kernels. + */ + insn = *(uint32_t *)host_signal_pc(uc); + + return (insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ + || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ + || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ + || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ + || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ + || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ + || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ + /* Ignore bits 10, 11 & 21, controlling indexing. */ + || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */ + || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */ + /* Ignore bits 23 & 24, controlling indexing. */ + || (insn & 0x3a400000) == 0x28000000; /* C3.3.7,14-16 */ +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5656c654e1..0915eb7f95 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,99 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__aarch64__) - -#if defined(__NetBSD__) - -#include -#include - -int cpu_signal_handler(int host_signum, void *pinfo, void *puc) -{ - ucontext_t *uc = puc; - siginfo_t *si = pinfo; - unsigned long pc; - int is_write; - uint32_t esr; - - pc = uc->uc_mcontext.__gregs[_REG_PC]; - esr = si->si_trap; - - /* - * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC - * is 0b10010x: then bit 6 is the WnR bit - */ - is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; - return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask); -} - -#else - -#ifndef ESR_MAGIC -/* Pre-3.16 kernel headers don't have these, so provide fallback definitions */ -#define ESR_MAGIC 0x45535201 -struct esr_context { - struct _aarch64_ctx head; - uint64_t esr; -}; -#endif - -static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) -{ - return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; -} - -static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) -{ - return (struct _aarch64_ctx *)((char *)hdr + hdr->size); -} - -int cpu_signal_handler(int host_signum, void *pinfo, void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - uintptr_t pc = uc->uc_mcontext.pc; - bool is_write; - struct _aarch64_ctx *hdr; - struct esr_context const *esrctx = NULL; - - /* Find the esr_context, which has the WnR bit in it */ - for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) { - if (hdr->magic == ESR_MAGIC) { - esrctx = (struct esr_context const *)hdr; - break; - } - } - - if (esrctx) { - /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ - uint64_t esr = esrctx->esr; - is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; - } else { - /* - * Fall back to parsing instructions; will only be needed - * for really ancient (pre-3.16) kernels. - */ - uint32_t insn = *(uint32_t *)pc; - - is_write = ((insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ - || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ - || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ - || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ - || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ - || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ - || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ - /* Ignore bits 10, 11 & 21, controlling indexing. */ - || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */ - || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */ - /* Ignore bits 23 & 24, controlling indexing. */ - || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */ - } - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#endif - -#elif defined(__s390__) +#if defined(__s390__) int cpu_signal_handler(int host_signum, void *pinfo, void *puc) From patchwork Fri Oct 15 04:09:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515797 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp137962imi; Thu, 14 Oct 2021 21:22:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzZPl+cE9zUE67Ly6osEmL0jGhSpnXnA9HOSFFhK2HRvLiDu1hFf1oBTHHsufKfAVa56QC/ X-Received: by 2002:a25:3046:: with SMTP id w67mr10373728ybw.134.1634271761026; Thu, 14 Oct 2021 21:22:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271761; cv=none; d=google.com; s=arc-20160816; b=KlVgH2WUsTeboUfNxQFNC3FyP8I9aWYGL0x0rbev+92V9LF1wrp4zCYmAGtqWR4VJo /OvmYrREnsF3aE72HumX1qKLG4lsBQQ9Ck+Mn2Y1j3dfWwOMb5cyC/nC78iUGsUId5J5 60TVtIZr3j6Y6WFB0OIMDmx2342J69+Y788X1oszzaZGj9aqrjtXEFwEIkDSS3FINOM9 cZO0zVfH+inDvM63rjzLVzxBg6xbebCMHDfQ0YIenpJ2jhGn8EaIntZcGsDlsEjJQaY3 uY5hsLrKK31vDy6tLsL28loUq0rIucTE0J7plYmbGmnO38oe38sWt8yuzwWE7PEEG4kz /C9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZrcsdPFY+Q0/rnzaDekoblOXqp3EpRf37OahPazOQjQ=; b=PdIPx0jtq4V4sDQFYBOTUpCxMt5P/mdV2twJIkBawyAKQz+FkombZIQu/LUiBs2U6S eZUykrSe5tfW4Nd+boI2+Bagjg6EGacf2OohVDzQ/kWIDRRGZElk917dNpMMMxT4No/T Vqe1yv+3dahzpy8EF3IEfcZu/PEKmrnfh+oj5xdYOy4f/Q/AEiZvm+aSAzPkFuOGe/Yi TDnwHkA4TieszdS7Nc+l9e13CZAnkCWoO2T76O7Hy/sgw0dMTPzICNJU33nFoZbmrSyM /N1G17T38DDe5yL6dyIZ2E0/z/vb6b7T+JLSdQ0NwLGGp8YAdttgnZEk2Bj9k6rwLn79 EBPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=wSRtpghW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/s390/host-signal.h | 93 ++++++++++++++++++++++++++++- linux-user/host/s390x/host-signal.h | 2 +- accel/tcg/user-exec.c | 88 +-------------------------- 3 files changed, 94 insertions(+), 89 deletions(-) -- 2.25.1 diff --git a/linux-user/host/s390/host-signal.h b/linux-user/host/s390/host-signal.h index f4b4d65031..21f59b612a 100644 --- a/linux-user/host/s390/host-signal.h +++ b/linux-user/host/s390/host-signal.h @@ -1 +1,92 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef S390_HOST_SIGNAL_H +#define S390_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.psw.addr; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint16_t *pinsn = (uint16_t *)host_signal_pc(uc); + + /* + * ??? On linux, the non-rt signal handler has 4 (!) arguments instead + * of the normal 2 arguments. The 4th argument contains the "Translation- + * Exception Identification for DAT Exceptions" from the hardware (aka + * "int_parm_long"), which does in fact contain the is_write value. + * The rt signal handler, as far as I can tell, does not give this value + * at all. Not that we could get to it from here even if it were. + * So fall back to parsing instructions. Treat read-modify-write ones as + * writes, which is not fully correct, but for tracking self-modifying code + * this is better than treating them as reads. Checking si_addr page flags + * might be a viable improvement, albeit a racy one. + */ + /* ??? This is not even close to complete. */ + switch (pinsn[0] >> 8) { + case 0x50: /* ST */ + case 0x42: /* STC */ + case 0x40: /* STH */ + case 0xba: /* CS */ + case 0xbb: /* CDS */ + return true; + case 0xc4: /* RIL format insns */ + switch (pinsn[0] & 0xf) { + case 0xf: /* STRL */ + case 0xb: /* STGRL */ + case 0x7: /* STHRL */ + return true; + } + break; + case 0xc8: /* SSF format insns */ + switch (pinsn[0] & 0xf) { + case 0x2: /* CSST */ + return true; + } + break; + case 0xe3: /* RXY format insns */ + switch (pinsn[2] & 0xff) { + case 0x50: /* STY */ + case 0x24: /* STG */ + case 0x72: /* STCY */ + case 0x70: /* STHY */ + case 0x8e: /* STPQ */ + case 0x3f: /* STRVH */ + case 0x3e: /* STRV */ + case 0x2f: /* STRVG */ + return true; + } + break; + case 0xeb: /* RSY format insns */ + switch (pinsn[2] & 0xff) { + case 0x14: /* CSY */ + case 0x30: /* CSG */ + case 0x31: /* CDSY */ + case 0x3e: /* CDSG */ + case 0xe4: /* LANG */ + case 0xe6: /* LAOG */ + case 0xe7: /* LAXG */ + case 0xe8: /* LAAG */ + case 0xea: /* LAALG */ + case 0xf4: /* LAN */ + case 0xf6: /* LAO */ + case 0xf7: /* LAX */ + case 0xfa: /* LAAL */ + case 0xf8: /* LAA */ + return true; + } + break; + } + return false; +} + +#endif diff --git a/linux-user/host/s390x/host-signal.h b/linux-user/host/s390x/host-signal.h index f4b4d65031..0e83f9358d 100644 --- a/linux-user/host/s390x/host-signal.h +++ b/linux-user/host/s390x/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../s390/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0915eb7f95..bfd964b578 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,93 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__s390__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - unsigned long pc; - uint16_t *pinsn; - int is_write = 0; - - pc = uc->uc_mcontext.psw.addr; - - /* - * ??? On linux, the non-rt signal handler has 4 (!) arguments instead - * of the normal 2 arguments. The 4th argument contains the "Translation- - * Exception Identification for DAT Exceptions" from the hardware (aka - * "int_parm_long"), which does in fact contain the is_write value. - * The rt signal handler, as far as I can tell, does not give this value - * at all. Not that we could get to it from here even if it were. - * So fall back to parsing instructions. Treat read-modify-write ones as - * writes, which is not fully correct, but for tracking self-modifying code - * this is better than treating them as reads. Checking si_addr page flags - * might be a viable improvement, albeit a racy one. - */ - /* ??? This is not even close to complete. */ - pinsn = (uint16_t *)pc; - switch (pinsn[0] >> 8) { - case 0x50: /* ST */ - case 0x42: /* STC */ - case 0x40: /* STH */ - case 0xba: /* CS */ - case 0xbb: /* CDS */ - is_write = 1; - break; - case 0xc4: /* RIL format insns */ - switch (pinsn[0] & 0xf) { - case 0xf: /* STRL */ - case 0xb: /* STGRL */ - case 0x7: /* STHRL */ - is_write = 1; - } - break; - case 0xc8: /* SSF format insns */ - switch (pinsn[0] & 0xf) { - case 0x2: /* CSST */ - is_write = 1; - } - break; - case 0xe3: /* RXY format insns */ - switch (pinsn[2] & 0xff) { - case 0x50: /* STY */ - case 0x24: /* STG */ - case 0x72: /* STCY */ - case 0x70: /* STHY */ - case 0x8e: /* STPQ */ - case 0x3f: /* STRVH */ - case 0x3e: /* STRV */ - case 0x2f: /* STRVG */ - is_write = 1; - } - break; - case 0xeb: /* RSY format insns */ - switch (pinsn[2] & 0xff) { - case 0x14: /* CSY */ - case 0x30: /* CSG */ - case 0x31: /* CDSY */ - case 0x3e: /* CDSG */ - case 0xe4: /* LANG */ - case 0xe6: /* LAOG */ - case 0xe7: /* LAXG */ - case 0xe8: /* LAAG */ - case 0xea: /* LAALG */ - case 0xf4: /* LAN */ - case 0xf6: /* LAO */ - case 0xf7: /* LAX */ - case 0xfa: /* LAAL */ - case 0xf8: /* LAA */ - is_write = 1; - } - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__mips__) +#if defined(__mips__) #if defined(__misp16) || defined(__mips_micromips) #error "Unsupported encoding" From patchwork Fri Oct 15 04:10:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515787 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp135392imi; Thu, 14 Oct 2021 21:17:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJylcXx4oXCPURp642UW6o+4a/UzTwnjTgf2AxQxbxedRYmCvt3N/bBaWr+3mZmt8KiYDjzN X-Received: by 2002:a25:2d48:: with SMTP id s8mr10795940ybe.380.1634271464203; Thu, 14 Oct 2021 21:17:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271464; cv=none; d=google.com; s=arc-20160816; b=ioB5v8eTfQIIrkJJSaaL6rZwq0fXcTV/T8Sg5RZ2hENn6i3LKEFgaoJtFhEi5SthtM 0lDa0GXgdwBahDkZCJb7qKwMW+Yv8P+VIN7KMvqzRw9dNGzkymUSXmtC7hgczBLeaCav doCsi+eiVPa+lNRoWHNhnK7eWnsXHb63ItsxP/derCQdVLqnsxwVtSSD9dn9vszUAXuh IJGMbBZa+/0Krdhq+dYa6PwxdPHrb7m0Eok7trufMgWoIwG5ijLKv+QkFaqKNh/mJ8Ss oAhlMez3omYtm4KDzXtjezb2R07+nQ/cctsXunjgdoWH2vsp7ziB5yvrtIat3wQfsu0Y Gh2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SO98PYe76zHX1Te4ncmpUAjeZt6T0p/6OYCNnl9Too8=; b=Eur5eQmHHW0f65CAyFHZelLpw4ObK3jQrRgf60+Q69QaXvD493m5Lyn91BXeE7e00O XtITz0hGOGWK6EB9B5kQ4psI8qihSLdJAdc2gYCyoR4Rqt93ebeaXYfV8DP7rXsBydmm 6qOIFwYWCWVPzwvLD2e2t1G9LDBWS9xOXMb4qOaZma+2MGTGYVsHYR0A+13+NgEI3UEN j1FZtAwuZa9lOPeGZqrzjj9HCCUycE3zC0hTF9dQGGIPP5rHPIeVrK2VtxT1EOqbM+CS 2pbftAaz34h/2TJn2zUOGve4z0gJTrtHGsWFT3Cjyej6q7wkmW8FtNILwQQ+5+0x4yR7 9FpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YCqH71h7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/mips/host-signal.h | 62 +++++++++++++++++++++++++++++- accel/tcg/user-exec.c | 52 +------------------------ 2 files changed, 62 insertions(+), 52 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host-signal.h index f4b4d65031..9c83e51130 100644 --- a/linux-user/host/mips/host-signal.h +++ b/linux-user/host/mips/host-signal.h @@ -1 +1,61 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef MIPS_HOST_SIGNAL_H +#define MIPS_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.pc; +} + +#if defined(__misp16) || defined(__mips_micromips) +#error "Unsupported encoding" +#endif + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn = *(uint32_t *)host_signal_pc(uc); + + /* Detect all store instructions at program counter. */ + switch ((insn >> 26) & 077) { + case 050: /* SB */ + case 051: /* SH */ + case 052: /* SWL */ + case 053: /* SW */ + case 054: /* SDL */ + case 055: /* SDR */ + case 056: /* SWR */ + case 070: /* SC */ + case 071: /* SWC1 */ + case 074: /* SCD */ + case 075: /* SDC1 */ + case 077: /* SD */ +#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 + case 072: /* SWC2 */ + case 076: /* SDC2 */ +#endif + return true; + case 023: /* COP1X */ + /* + * Required in all versions of MIPS64 since + * MIPS64r1 and subsequent versions of MIPS32r2. + */ + switch (insn & 077) { + case 010: /* SWXC1 */ + case 011: /* SDXC1 */ + case 015: /* SUXC1 */ + return true; + } + break; + } + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index bfd964b578..287f03dac5 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,57 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__mips__) - -#if defined(__misp16) || defined(__mips_micromips) -#error "Unsupported encoding" -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - uintptr_t pc = uc->uc_mcontext.pc; - uint32_t insn = *(uint32_t *)pc; - int is_write = 0; - - /* Detect all store instructions at program counter. */ - switch((insn >> 26) & 077) { - case 050: /* SB */ - case 051: /* SH */ - case 052: /* SWL */ - case 053: /* SW */ - case 054: /* SDL */ - case 055: /* SDR */ - case 056: /* SWR */ - case 070: /* SC */ - case 071: /* SWC1 */ - case 074: /* SCD */ - case 075: /* SDC1 */ - case 077: /* SD */ -#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 - case 072: /* SWC2 */ - case 076: /* SDC2 */ -#endif - is_write = 1; - break; - case 023: /* COP1X */ - /* Required in all versions of MIPS64 since - MIPS64r1 and subsequent versions of MIPS32r2. */ - switch (insn & 077) { - case 010: /* SWXC1 */ - case 011: /* SDXC1 */ - case 015: /* SUXC1 */ - is_write = 1; - } - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__riscv) +#if defined(__riscv) int cpu_signal_handler(int host_signum, void *pinfo, void *puc) From patchwork Fri Oct 15 04:10:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515800 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp138950imi; Thu, 14 Oct 2021 21:24:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwUfYmUNWG6MSG1w/kW+RkX6ubAP3juQi3wDHsnQ9kEAT9Rt5FzWmKlKEE9Yhneczn2nTUv X-Received: by 2002:a25:1e02:: with SMTP id e2mr10459199ybe.39.1634271886500; Thu, 14 Oct 2021 21:24:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271886; cv=none; d=google.com; s=arc-20160816; b=hMb1Q8dnfkWgbI4grS5yc5L2sUYuCv6VkS8+qETJz+YEE0urjF4iKjl5DHans9+trV fnPxGLrM0BA16NbGkridxX73PS/0YcjDisaA3sBLU/qOK9iwHtqQ0I7N20voW3PR50Vl y80T4Q76HW3UcjE6q4gX3oODzqyqxhcDEuleGyRm08qDDS0u2uanknmm1ScsS1L+51GQ BW+Uk9swpNDXlmNOSF6tziuGvWz7imtLPeL3gUALIuTdsA89tT7F2zp9OmrjgrtEfc4l UXABT0AzR0sbh4A6fqlmmIMWS8BesLtpWXmt9QAM6y9qw8kR3QmQGf4WEBywEbrblQnc Z7/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yx+lHUm4xHRTq+oGBCcGRXU4RqMZyaNJqFFfjCahKRo=; b=gqNmsZ8tIizRYQrNkYcXU822Do0aYS+K7aWJX6UqFb7CCmbqk4KbUFUwSLsNVxAHCh hrB40C3EsPXcWGf25n5cBKoE/8uzOYv/qoemIwa4Az3K3FzA8pFPz1EmXyZeCgxESZku xSVk/llWoNO2Vgzfam4OvGDyr3xvjCnJawvwL57ymEhvfsSdFKaEGuXfbNriRdUxKRby puMZQntSJpH55RCXNnah9ZxyKcSAIM2MEfy1C0NY7DpLzv2L8haO+iAco8Gp8Y5H+/rt MZ621K7Pjb8cLbdkXcZR0BtSQTyc3kQJjy6W/6+EsxnG0iFd67qOk6Dx0r/wHc74OhIz FTsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Lgc2zpGZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c187si5191486ybc.140.2021.10.14.21.24.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:24:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Lgc2zpGZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbElx-0001r3-RI for patch@linaro.org; Fri, 15 Oct 2021 00:24:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38832) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYp-00078M-Us for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:11 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:46882) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYn-0000Fv-Oh for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:11 -0400 Received: by mail-pg1-x52c.google.com with SMTP id m21so7413728pgu.13 for ; Thu, 14 Oct 2021 21:11:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yx+lHUm4xHRTq+oGBCcGRXU4RqMZyaNJqFFfjCahKRo=; b=Lgc2zpGZqXm7CyOJfiC9Skl5ehvkC+tlzr3c3BDJJBx14Vdipx2NMaMzzquR8Yg6Bs WSVw6VoTUrjMx72Va8fmipgjdatNapd0C+kS6eNwweeWP7nhYJ51EpaHN9jdQizEBQc1 Y8eAJve82wqreyBURLSV6xmD8kSaIAQzJhWFmF7gTDfEZzzAKLw3A9lfNVhQuAu2QOUE cd3OS3DtUZUzCKB3n5iHar3ucGa6mP6QKHcDB0td5n0KuGN0Q42ImzsFFKbWNnvKlq+0 FCwnCsdLQgSa8Bqrt5eeT+8xyJk0+b7HUBgtu5NSYsj7BX0YcVc5DgCQd/I8ganhzH78 tbsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yx+lHUm4xHRTq+oGBCcGRXU4RqMZyaNJqFFfjCahKRo=; b=4dFNarg4t6m0ZTan44rOMQyMe4qKntKGcS1G9Z0sDdVTkDHXp4ilriKoudopRDRWZ5 keT5CTPaihNOS29P+7hRAIxLrabLsV3NheuhYFN5rND6BKGRC4SUojrZsByKPLTHAzPI Z7uVNNOcE/CwFFlqSUSh+NhFFuxHU3FZ23AiQ5HTFBFqRccrIIXonw6PFOm4euzF7aIk TH4f6Vh/R9rfUyOXA5bQEChgj39z8L6OZrPYgsf6z6CH8QpYmQw5RCxxYxvYDOkcv7q9 lrTVaMGLsiO12BXwelzZVpdJ8LCaM8k2rhDA4pEfJapvmJW6hMnzo6DrBbbxTnz8af7p fPmw== X-Gm-Message-State: AOAM530nvtAuKbvlYO5x9M6lpr2e0P3UWtTQUyE1iiNVm5UHjHBjRkhI wqOBCbDkQN91iqnfFnJIrJYwX5FG1Hh5nw== X-Received: by 2002:a65:64d7:: with SMTP id t23mr7219602pgv.237.1634271068252; Thu, 14 Oct 2021 21:11:08 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 15/67] linux-user/host/riscv: Populate host_signal.h Date: Thu, 14 Oct 2021 21:10:01 -0700 Message-Id: <20211015041053.2769193-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 85 +++++++++++++++++- accel/tcg/user-exec.c | 134 ---------------------------- 2 files changed, 84 insertions(+), 135 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/host-signal.h index f4b4d65031..5860dce7d7 100644 --- a/linux-user/host/riscv/host-signal.h +++ b/linux-user/host/riscv/host-signal.h @@ -1 +1,84 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef RISCV_HOST_SIGNAL_H +#define RISCV_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.__gregs[REG_PC]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn = *(uint32_t *)host_signal_pc(uc); + + /* + * Detect store by reading the instruction at the program + * counter. Note: we currently only generate 32-bit + * instructions so we thus only detect 32-bit stores + */ + switch (((insn >> 0) & 0b11)) { + case 3: + switch (((insn >> 2) & 0b11111)) { + case 8: + switch (((insn >> 12) & 0b111)) { + case 0: /* sb */ + case 1: /* sh */ + case 2: /* sw */ + case 3: /* sd */ + case 4: /* sq */ + return true; + default: + break; + } + break; + case 9: + switch (((insn >> 12) & 0b111)) { + case 2: /* fsw */ + case 3: /* fsd */ + case 4: /* fsq */ + return true; + default: + break; + } + break; + default: + break; + } + } + + /* Check for compressed instructions */ + switch (((insn >> 13) & 0b111)) { + case 7: + switch (insn & 0b11) { + case 0: /*c.sd */ + case 2: /* c.sdsp */ + return true; + default: + break; + } + break; + case 6: + switch (insn & 0b11) { + case 0: /* c.sw */ + case 3: /* c.swsp */ + return true; + default: + break; + } + break; + default: + break; + } + + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 287f03dac5..2d9ab0a8b8 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -139,64 +139,6 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, } } -/* - * 'pc' is the host PC at which the exception was raised. - * 'address' is the effective address of the memory exception. - * 'is_write' is 1 if a write caused the exception and otherwise 0. - * 'old_set' is the signal set which should be restored. - */ -static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, - int is_write, sigset_t *old_set) -{ - CPUState *cpu = current_cpu; - CPUClass *cc; - unsigned long host_addr = (unsigned long)info->si_addr; - MMUAccessType access_type = adjust_signal_pc(&pc, is_write); - abi_ptr guest_addr; - - /* For synchronous signals we expect to be coming from the vCPU - * thread (so current_cpu should be valid) and either from running - * code or during translation which can fault as we cross pages. - * - * If neither is true then something has gone wrong and we should - * abort rather than try and restart the vCPU execution. - */ - if (!cpu || !cpu->running) { - printf("qemu:%s received signal outside vCPU context @ pc=0x%" - PRIxPTR "\n", __func__, pc); - abort(); - } - -#if defined(DEBUG_SIGNAL) - printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", - pc, host_addr, is_write, *(unsigned long *)old_set); -#endif - - /* Convert forcefully to guest address space, invalid addresses - are still valid segv ones */ - guest_addr = h2g_nocheck(host_addr); - - /* XXX: locking issue */ - if (is_write && - info->si_signo == SIGSEGV && - info->si_code == SEGV_ACCERR && - h2g_valid(host_addr) && - handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) { - return 1; - } - - /* - * There is no way the target can handle this other than raising - * an exception. Undo signal and retaddr state prior to longjmp. - */ - sigprocmask(SIG_SETMASK, old_set, NULL); - - cc = CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, - MMU_USER_IDX, false, pc); - g_assert_not_reached(); -} - static int probe_access_internal(CPUArchState *env, target_ulong addr, int fault_size, MMUAccessType access_type, bool nonfault, uintptr_t ra) @@ -255,82 +197,6 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__riscv) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - greg_t pc = uc->uc_mcontext.__gregs[REG_PC]; - uint32_t insn = *(uint32_t *)pc; - int is_write = 0; - - /* Detect store by reading the instruction at the program - counter. Note: we currently only generate 32-bit - instructions so we thus only detect 32-bit stores */ - switch (((insn >> 0) & 0b11)) { - case 3: - switch (((insn >> 2) & 0b11111)) { - case 8: - switch (((insn >> 12) & 0b111)) { - case 0: /* sb */ - case 1: /* sh */ - case 2: /* sw */ - case 3: /* sd */ - case 4: /* sq */ - is_write = 1; - break; - default: - break; - } - break; - case 9: - switch (((insn >> 12) & 0b111)) { - case 2: /* fsw */ - case 3: /* fsd */ - case 4: /* fsq */ - is_write = 1; - break; - default: - break; - } - break; - default: - break; - } - } - - /* Check for compressed instructions */ - switch (((insn >> 13) & 0b111)) { - case 7: - switch (insn & 0b11) { - case 0: /*c.sd */ - case 2: /* c.sdsp */ - is_write = 1; - break; - default: - break; - } - break; - case 6: - switch (insn & 0b11) { - case 0: /* c.sw */ - case 3: /* c.swsp */ - is_write = 1; - break; - default: - break; - } - break; - default: - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#endif - /* The softmmu versions of these helpers are in cputlb.c. */ /* From patchwork Fri Oct 15 04:10:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515798 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp138236imi; Thu, 14 Oct 2021 21:23:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwPqdV5FAKO7iLpEh0QRYqlqcYh2G5GDTWQS3va9Kaa4CGGHEirRNHAXl+BZL1xuTzcQYRc X-Received: by 2002:a05:6e02:8a3:: with SMTP id a3mr2175059ilt.88.1634271796091; Thu, 14 Oct 2021 21:23:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271796; cv=none; d=google.com; s=arc-20160816; b=gY45e0EyfTvDJ78kg0AzmLj0UxyIPrTmQ/o1zfqFj2lZ7fYcQkh1flay9DngFeyzgy bqXMMNS5YygSHCvv/L/OzbBb2KJiHvyQJxndaLrgc7NNSnkvm0XlBweCD7Uy4bFjh2FD oh9UJ1wlNUCYiHxGDOT+K+M6DH8+JUL/fxwLUw5RYip74dqpbMzrlQBzj9W7E/otD/p4 zKsiHMI+HmF4sXCV7jkQONzmmMJa8OB6fKo1ehP3gaG29qerQ4PntAWzg8Ns5igIyt6o nJoN8gbZBFzwf7ovC+VanKv7PFq7ve+Z9twy/dixb3uuyFMiVCDgdyUfUuj4GlqwsMmC J15g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+vyWXP6Fx9Nim2ldoxF0eSsJbEhC7OEjuYcEJUYRKoA=; b=xhcdZ6hf1wjCtoVRqRGtU9Vme3BRdFzbzVUMOwlHWcWmbKT6rAB9BhT+8Kiz/zKoW2 FosakZKtaEfoJOQIrnIk2mXQYOlUlfUAKTdaIpomxrzDIPp7M4O6JJ3mUsX8AkZuEWUE SK7WQbTEKCiT72QqrQuhmjgn6lmEiYtk4L/LDpNdTjFMPbeLSHCRBXeoJcdEmkDcVdGh lERLwTzCTq1bYrtl+J3eb+30WKZhMaZK2spZy3V5SWKdM3NVljoXzrAGZI5vy+g4Yaou wL0svHBzbBo4dlFw10QeiAAgoT0SJYkgqo8v5FI37j3OXx8O6hAC8rp8uvCpDGdrjL52 COpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yfhKZec0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Refer to host_signal_handler instead. Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 Reviewed-by: Warner Losh Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index dab5f1d1cd..07be55b7e1 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -6118,7 +6118,7 @@ DO_LDN_2(4, dd, MO_64) * linux-user/ in its get_user/put_user macros. * * TODO: Construct some helpers, written in assembly, that interact with - * handle_cpu_signal to produce memory ops which can properly report errors + * host_signal_handler to produce memory ops which can properly report errors * without racing. */ From patchwork Fri Oct 15 04:10:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515802 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp139781imi; Thu, 14 Oct 2021 21:25:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxl6KpwmJwnHzbWlGB/zv0K5DMB+5Ib+BJwgu2NvXzd+s2H0+bXo+5RfiTKiQBjSjytp5PW X-Received: by 2002:a25:1a07:: with SMTP id a7mr11316539yba.30.1634271954784; Thu, 14 Oct 2021 21:25:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271954; cv=none; d=google.com; s=arc-20160816; b=hFQfQLLooDQFSULxsZgNwSNxiPjRUNJQIAJ2hlGicz6MSxY2InoRdXb6FFiKpvovgO 5Z4uVoKMpjFPkdxy285aA5V43fBCORpPGNo10opcm+83znLpTNS8azI7776eTU3kwAVU V6FJsqGEUp4JE2/j4XXVY7YuL/Re5U114D1TPr1V9x5r/cgmiV4ZOQzB46Kdxem53gr0 6HEvz6H35OvNPvuxq0UoslZ1VtUoUmy2Z3RNFvTGS+NgX+5EWgO9jYyaAWAZIcearDO7 8W6xqgt+vqYPzpwO1bGiuNYg71kSeKoBi5kieTQKoIEb9IF48RnnwaEWI9I+h9QiYW0t EHwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=T6s+8p22L/kJt7ysU37rV/HmGCKRECxNpTVVs5PRRQU=; b=RinFr+DqOR4puzobNEDQLS+nVx6a37kwxZ+u35zy9c5vhu2CFJ84PFdcOEZyGQg42i 23o3YCR4MY/3lWrAB25HchT7AaeNl1N1WzvYLQL5q1b/GkS3XGuKfb6W+UVLZykhzrk6 vmoC6T8dDBEAYNrO4oO/WiPPwEbb0ihMj9XwE42m62kHDAxPjRrzImU4/LDpQijDxwqQ z9Q0wknnOw7ZZVcRsxSwWYchS8kxTTheMMYTozmrOqenXgOcAO05RSVG1cvSF1vhwQGp kWiF6HsTrdiLaU0PIQjYy9Ikzse9zomliPEKmML1Dkc8yAlFQBcg9MIwmmIJSB0EObOS KV8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=REPHbbf4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l125si6846865ybf.10.2021.10.14.21.25.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:25:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=REPHbbf4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40390 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEn4-0003vd-5E for patch@linaro.org; Fri, 15 Oct 2021 00:25:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38856) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYr-0007Cy-6p for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:14 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:33480) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYp-0000H5-8Z for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:12 -0400 Received: by mail-pg1-x52a.google.com with SMTP id j190so698858pgd.0 for ; Thu, 14 Oct 2021 21:11:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T6s+8p22L/kJt7ysU37rV/HmGCKRECxNpTVVs5PRRQU=; b=REPHbbf4TEkbB7/C3FISZnFJs0Y0hSnNMIJyQe4CQKlb5yJcXYR694/1TVG9dSoGp1 ui1RonR0JLBznZhlMQDcCWvcSeq6IsoK0tQ9yK/uV1JZoZiZuZJ0PUYEpdj8Z2ZutgzR vz1DsACToajKO60xGhqhaSGxVHbGyI724yltsiST+GFJ+vY1S5Tn2wJPuwAmOkKQQYs1 Q3J4XA9ZdnLAQbi9hcHkgG71Jg81g3hRI24+SOk44VGQI5+9RQIGrYXDH5aDQAjISJkZ zHsfogb1kToVhHDQEMwd93LU09WR6pkcxSIP678CKRWGc8Fm3cJobI23JqH1lunrUsd6 016A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T6s+8p22L/kJt7ysU37rV/HmGCKRECxNpTVVs5PRRQU=; b=dsnEDLTKMxf8i7dRilfWwj1JDPBewM5+4/szz3jNtpbOLAw72G0owczrF6i3qtjBv5 d4pN5vVZpM6qnRCRnVyBKGClmEAO/Q4iiDT8n4jGEC9UplaFeJ552cp1cYgD3VsGmGo9 ipCefrO1DluZ1UcLyfVVU/vv66z//MWHBiDXrOeHs5tcgC/M7mieUTxAM5w6Qb7rU6BZ 7lsFxOJF5Zh3wqb9ldfktYGL1ZHTieO0VJblqP5T21Ea5TL9KC3F5hdyMsd5DtFVP7nt NDzaVGimF89MEmU/U5FK32IDZqztEMruOQC2h6yhWTcMK4Zrxpq4bbDyBubbeuPBiY93 28Vw== X-Gm-Message-State: AOAM532bnQOhnovnliQstFfZTQQFGIeT5n2GHUks6H6Uru0CDbG6jmIc DbHflbcPpy+jAFNam9iyA0hT+D+0TTb1AA== X-Received: by 2002:a63:7404:: with SMTP id p4mr7213000pgc.222.1634271069860; Thu, 14 Oct 2021 21:11:09 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 17/67] linux-user/host/riscv: Improve host_signal_write Date: Thu, 14 Oct 2021 21:10:03 -0700 Message-Id: <20211015041053.2769193-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not read 4 bytes before we determine the size of the insn. Simplify triple switches in favor of checking major opcodes. Include the missing cases of compact fsd and fsdsp. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 83 ++++++++++------------------- 1 file changed, 28 insertions(+), 55 deletions(-) -- 2.25.1 diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/host-signal.h index 5860dce7d7..ab06d70964 100644 --- a/linux-user/host/riscv/host-signal.h +++ b/linux-user/host/riscv/host-signal.h @@ -17,65 +17,38 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) { - uint32_t insn = *(uint32_t *)host_signal_pc(uc); - /* - * Detect store by reading the instruction at the program - * counter. Note: we currently only generate 32-bit - * instructions so we thus only detect 32-bit stores + * Detect store by reading the instruction at the program counter. + * Do not read more than 16 bits, because we have not yet determined + * the size of the instruction. */ - switch (((insn >> 0) & 0b11)) { - case 3: - switch (((insn >> 2) & 0b11111)) { - case 8: - switch (((insn >> 12) & 0b111)) { - case 0: /* sb */ - case 1: /* sh */ - case 2: /* sw */ - case 3: /* sd */ - case 4: /* sq */ - return true; - default: - break; - } - break; - case 9: - switch (((insn >> 12) & 0b111)) { - case 2: /* fsw */ - case 3: /* fsd */ - case 4: /* fsq */ - return true; - default: - break; - } - break; - default: - break; - } + const uint16_t *pinsn = (const uint16_t *)host_signal_pc(uc); + uint16_t insn = pinsn[0]; + + /* 16-bit instructions */ + switch (insn & 0xe003) { + case 0xa000: /* c.fsd */ + case 0xc000: /* c.sw */ + case 0xe000: /* c.sd (rv64) / c.fsw (rv32) */ + case 0xa002: /* c.fsdsp */ + case 0xc002: /* c.swsp */ + case 0xe002: /* c.sdsp (rv64) / c.fswsp (rv32) */ + return true; } - /* Check for compressed instructions */ - switch (((insn >> 13) & 0b111)) { - case 7: - switch (insn & 0b11) { - case 0: /*c.sd */ - case 2: /* c.sdsp */ - return true; - default: - break; - } - break; - case 6: - switch (insn & 0b11) { - case 0: /* c.sw */ - case 3: /* c.swsp */ - return true; - default: - break; - } - break; - default: - break; + /* 32-bit instructions, major opcodes */ + switch (insn & 0x7f) { + case 0x23: /* store */ + case 0x27: /* store-fp */ + return true; + case 0x2f: /* amo */ + /* + * The AMO function code is in bits 25-31, unread as yet. + * The AMO functions are LR (read), SC (write), and the + * rest are all read-modify-write. + */ + insn = pinsn[1]; + return (insn >> 11) != 2; /* LR */ } return false; From patchwork Fri Oct 15 04:10:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515791 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp136513imi; Thu, 14 Oct 2021 21:19:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyitjpSiQw4cyOgugGmglX1QRMfCmC45Axsqqp0rV5AdZeP6g+MsLUPMYqMoAQmWlj4K6i/ X-Received: by 2002:a25:14d6:: with SMTP id 205mr10252600ybu.93.1634271597007; Thu, 14 Oct 2021 21:19:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271597; cv=none; d=google.com; s=arc-20160816; b=A6lW5jhQz12ns4mEpyHoYmH8vOz3vq7uJ0u+iev2GlobaUnZyzowe0dPdv3sVZV/im zG2MAJvfqIBgiHq1RR6Wp5Z3q6yipC3U/87sJHH2CAsh40p3cGWu07AUJt106Ob8MwBo X1npJhzFi+Tbdu08Pt35J/6IriIbIYzLT7A88aQ6eCFXwT43Vu4RmECcCIYHLj6k8wBZ Al8ouwuaI9O6RC1dPOEtbRGIzdTTQC5Z0V0/W8amiqAbIx0XnLe3kmG3cL7p2iefVtKJ TkFsGtrhr8faznnBm+lPsW4wCGohzNgIy+U871m0+sB2+YlC/NXTNed61LHTtU7/VSKU bnWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BEoOYfyvrRlliP3CVpcV5+AEGq6qhapGY3bb4mVGTHg=; b=eEP+GSnpdbjzgfE7EOhrNEyNgk5VQ19MIKn2SyoLPSnjLBzwoq2FCUIymivnroAsyZ x67kbPBepdr83NiqIJSui8yEr+YYqbySZ+eJdm9oUbJgYsRWaw/xg7EhFlxx3uiEMROS cYc0gZD+eY2VsUImBl3lbt1/WNT9yaeI4rCyTizYPG1ztGojG6PAOwD2f0xAF++MaMdp w4/K0KaFHxn22MLUWp02bIFsV3AqHGDrTMyJV8cM5Ro/ProVVruvGmjTzuwheMgqeVOq j+OERnWyJpfAEm2A1OGZvxPvLZWNkfMSrdQgAzlooI+NOlJ4mpq4mqddosGNyOASnqSV j83g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nguHstMx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w1si7189467ybu.219.2021.10.14.21.19.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:19:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nguHstMx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48312 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEhI-0007IX-AC for patch@linaro.org; Fri, 15 Oct 2021 00:19:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38876) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYt-0007ES-58 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:15 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:47100) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYq-0000Hy-3V for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:13 -0400 Received: by mail-pf1-x42b.google.com with SMTP id i76so5149790pfe.13 for ; Thu, 14 Oct 2021 21:11:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BEoOYfyvrRlliP3CVpcV5+AEGq6qhapGY3bb4mVGTHg=; b=nguHstMxODNDspQVrHP+s1x9jH1NX2XHVabg7k2QUt0njxyAWzrQPWjdYm+tPslwmn 7KoZk0+8/2p7B1H7N8IfQ8afgpRILEN/jCcSyvda55430+XPuyrsHKvtWTR2RTBSfm9p AYTRT5NCVO9lWrFSijPcdRcfHXVdTkAtZGBWvqLJdXbcuUIox3O1oCSoIv7Wg3BBVh0B qLlg/pUKj1BfEc5dDI7UT6pwIhQHjPFmhIx50Q2MyzxwPeUEfxvSgvwUAS340MpWsWcy 0deCcMZoMDTiQ+SRR785uobCe5s3eEOlVdFBMVJl4unO+1QSJk/zEsE2P1roBVtAMQHE jiwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BEoOYfyvrRlliP3CVpcV5+AEGq6qhapGY3bb4mVGTHg=; b=7ly2PC9H2LSCEmEVzRgomMhsHi7htAMZJrxORqiHaLM/EtbJJPYcbAjl7Fsu3j0Uen MpCt9lWoyuCec55sk6Hu/ZzUSmaQR7F+9nNL1oEkvS6qqyyhI3nDKimyWxpNdR8hsVfh TADXFdlk3ngrdRNEtODDiiNMarz/+vL5f4uCXg4q/VgJNLipcVrYTfsaR7zFXBGm6dW5 zOUr8Ik2EDe2JIe7R156ve/5bqxZYTGPt3TT765hWUrQiZlC81yB2v2c2Wxa+z0s+Q1k 24WeYd3dhsxGfGsOtte4yjsktoVusG2WHzrGHI6Xj2bAtLR3CbMwZkJXccJyYa92tawj nh7A== X-Gm-Message-State: AOAM532z6RiTPjWG4JFi9jNtEQZ8AtrjqBaH5p9FQnwu4uj9LLNWEZCA oLhqOH7KxM+e9B4i9URdm+rCIT9uHa076g== X-Received: by 2002:a65:538e:: with SMTP id x14mr7352445pgq.364.1634271070690; Thu, 14 Oct 2021 21:11:10 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 18/67] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Date: Thu, 14 Oct 2021 21:10:04 -0700 Message-Id: <20211015041053.2769193-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?P?= =?utf-8?q?hilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that all of the linux-user hosts have been converted to host-signal.h, drop the compatibility code. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 12 ------------ linux-user/signal.c | 14 -------------- 2 files changed, 26 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5f94d799aa..5dd663c153 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -685,18 +685,6 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, uintptr_t host_pc, abi_ptr guest_addr); -/** - * cpu_signal_handler - * @signum: host signal number - * @pinfo: host siginfo_t - * @puc: host ucontext_t - * - * To be called from the SIGBUS and SIGSEGV signal handler to inform the - * virtual cpu of exceptions. Returns true if the signal was handled by - * the virtual CPU. - */ -int cpu_signal_handler(int signum, void *pinfo, void *puc); - #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/linux-user/signal.c b/linux-user/signal.c index 6900acb122..b816678ba5 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -780,17 +780,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) ucontext_t *uc = puc; struct emulated_sigtable *k; int guest_sig; - -#ifdef HOST_SIGNAL_PLACEHOLDER - /* the CPU emulator uses some host signals to detect exceptions, - we forward to it some signals */ - if ((host_sig == SIGSEGV || host_sig == SIGBUS) - && info->si_code > 0) { - if (cpu_signal_handler(host_sig, info, puc)) { - return; - } - } -#else uintptr_t pc = 0; bool sync_sig = false; @@ -850,7 +839,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) sync_sig = true; } -#endif /* get target signal number */ guest_sig = host_to_target_signal(host_sig); @@ -865,7 +853,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) k->pending = guest_sig; ts->signal_pending = 1; -#ifndef HOST_SIGNAL_PLACEHOLDER /* * For synchronous signals, unwind the cpu state to the faulting * insn and then exit back to the main loop so that the signal @@ -875,7 +862,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) cpu->exception_index = EXCP_INTERRUPT; cpu_loop_exit_restore(cpu, pc); } -#endif rewind_if_in_safe_syscall(puc); From patchwork Fri Oct 15 04:10:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515792 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp136519imi; Thu, 14 Oct 2021 21:19:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxsV9qZdI9/yvBE9NELxEDAj3xC6IHfrBLhfFXoVtARWDXP8eUiUkWaFcIsr0XtvMuza5XJ X-Received: by 2002:a05:6e02:1c43:: with SMTP id d3mr2310594ilg.153.1634271598520; Thu, 14 Oct 2021 21:19:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271598; cv=none; d=google.com; s=arc-20160816; b=dn84Im0nMOmmii+hRlBZB+CjD+9ucgygMKSsnMPH8KcrF37xaZNgOCBMh+6BWetg4x C1b6sTTkak8xsLZJDuy7Rb1C+8Fu2WHnP9U/BdHth4Go4qgAnqOPQX6f/0On7weBPo0Y PJKOfSQbHe570LTJprjXsrDGHICh7+57JKED3qtWEMH9v9Gacs1k+chZ5CcJ1XgYq4gI DQam4Ycyy4m20KGqaul1hXqdi2kNmovSSAXMAzbX2/AXMP/ZQ6lC+yF12O5mWZJyiU8h xOwQzWun1J7EDq1PW5066FiWSA9UPv5DIxQoOFN48dt1w4gUoynTw3Y38232ycDKBWWD +qRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=p8GaNWW3vnRejpH0QBiQY2hh87QfB4bhIFphc+bCE2U=; b=x6fvjeFLq2Vz4AxCHVWDyTanCeIzETX1cYnzdrnPePRCsHxunxt9mv6PNuyS+VvHeH CpEYGTlJvEGviQwHgCBV4OZAHIfUbls1sBHtZS6msUu+/8aowdgcpRL5iMpyBlRfXrVh 3wwu/WM+NJU+hFUWHOkSGUqQNV1uI01a6q5SG9r3fo+EKDB9CDbgl9xcRGLb1sMPhtUo dtKsp9LRLUBQzke7yQgpnWA40HJdLbPxPlDJs5WuOgtOLBA5BgcZ5KymToUdg+pj3tE2 3jltR2hxYrAooOmSsu+Yb//npqShvt9U+O8wPl7aM6yC/B5FL/62iWZ8Tpt317a/2fkG Fhsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dejJWWV6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 206si5647339ioa.60.2021.10.14.21.19.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:19:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dejJWWV6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48440 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEhJ-0007O6-R6 for patch@linaro.org; Fri, 15 Oct 2021 00:19:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38878) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYt-0007EW-6m for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:15 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:35718) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYq-0000Im-VW for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:14 -0400 Received: by mail-pg1-x52b.google.com with SMTP id e7so7463745pgk.2 for ; Thu, 14 Oct 2021 21:11:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=p8GaNWW3vnRejpH0QBiQY2hh87QfB4bhIFphc+bCE2U=; b=dejJWWV6X/iZBhyVdKrm+gz+tC6AeGz+0aY28bMFsYencTyEotWAo553EGcPwSELU3 zwIsefSOFzV5g1WsO+kfnYdqZ0olHhZnrcvDOHeskI4p9pFGhxGOfA4q9Ir0G31yJ8nd c4IW/9Al4nb8XRt9daLBNElDkY0/A66q2kTXTIojYUnpt1Z5afWDW95WgDYbqykQtmkZ Xy1NW3CWN/jA0Wu+yd4t+NRzvlkf5HX38wyVsZ/kTyTmKL1nc/ySQi6LaneH2PMSgVdg mmRmOMzPd5o1o/grnD1xa29f4RPLd3yra86ZYkj4nywKtsmMjro+PspkUBMRK6Y3dJyt Q0rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=p8GaNWW3vnRejpH0QBiQY2hh87QfB4bhIFphc+bCE2U=; b=OWAFRpANthmuTazM/95vo+0LAdQIzKukoedwJkNVJFafrDllfhzjWR7bnFuNm9MRyh W4rwsZaQAqVsNxHI8zd9qgR+h/Q7Z5J48s6u9XRcm8BUoi9DKshXOoJmIgKa7i168hwl 6qtIS1ZfODFOdMQPKX3nRNlq3rvitesxCOaGLlScafioIIY1fw07Pd+ez/06MV/DWpzc w9FvQH7H5GFOo1nydpXSOSFoQlsmd5pZ7ecW1FMy9jFZXSJQXGpOOjusLnXPGNOEXlPr huH3rLoKgtRZ/oNlEmHoIn/5XLMlf/Vuqk6EuVVWENkZO06bvX4JbKQZCkPJUZodv7Vd ZalA== X-Gm-Message-State: AOAM5338Lu9UyCIfaX3MWQ2cBpkqhuK0VyYR3IaevJuQdiL6eiadAuZF xLM+5rxEwR5aPtQaPEYEfUMGnWgqHgvcaA== X-Received: by 2002:a63:6943:: with SMTP id e64mr7281160pgc.480.1634271071338; Thu, 14 Oct 2021 21:11:11 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 19/67] hw/core: Add TCGCPUOps.record_sigsegv Date: Thu, 14 Oct 2021 21:10:05 -0700 Message-Id: <20211015041053.2769193-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?P?= =?utf-8?q?hilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a new user-only interface for updating cpu state before raising a signal. This will replace tlb_fill for user-only and should result in less boilerplate for each guest. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.25.1 diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 6cbe17f2e6..41718b695b 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -111,6 +111,32 @@ struct TCGCPUOps { */ bool (*io_recompile_replay_branch)(CPUState *cpu, const TranslationBlock *tb); +#else + /** + * record_sigsegv: + * @cpu: cpu context + * @addr: faulting guest address + * @access_type: access was read/write/execute + * @maperr: true for invalid page, false for permission fault + * @ra: host pc for unwinding + * + * We are about to raise SIGSEGV with si_code set for @maperr, + * and si_addr set for @addr. Record anything further needed + * for the signal ucontext_t. + * + * If the emulated kernel does not provide anything to the signal + * handler with anything besides the user context registers, and + * the siginfo_t, then this hook need do nothing and may be omitted. + * Otherwise, record the data and return; the caller will raise + * the signal, unwind the cpu state, and return to the main loop. + * + * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided + * so that a "normal" cpu exception can be raised. In this case, + * the signal must be raised by the architecture cpu_loop. + */ + void (*record_sigsegv)(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); #endif /* CONFIG_SOFTMMU */ #endif /* NEED_CPU_H */ From patchwork Fri Oct 15 04:10:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515795 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp137943imi; Thu, 14 Oct 2021 21:22:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx+7qw9W5J4n1zUYegj++w5T9LlYaXBPqjD/NZATZ62qoYGaWwi7EJQRf+ux/T/AhIl8MZ7 X-Received: by 2002:a5d:9145:: with SMTP id y5mr2238270ioq.200.1634271758648; Thu, 14 Oct 2021 21:22:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271758; cv=none; d=google.com; s=arc-20160816; b=yuhZgJbr/o2jWP2qfvfsdJ4qb5rU9wXOj7wrHiYrhVao8/e8LQv21vavIe/LbY7B0z lJNE+FkuaAROfBI2hgVT0VvxORya7tC5ClSsl9xETKUyCDZzEHgQqGor1gLksV40fYfc 5O/bGOFgdcN4RGAZ0IRAEy3tUXAznqniNGWbj18U7ZTJfikZrhw01CC7o1zr+q4h9qPo kl/xikNmN0nbi1MFmA50f7AsNiFk3j063jPdJOl5UWpdCKBqeprWs4gVYJ9X6M+sPfHy ybKgpYHnq1mKRPzEsePJrEnPFWKvg3Byrc4+RcRJNTexUZQguwHkJ0UJ+XZdPzbMNsZY zIXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3zF39zy0stf9vN9RkqNLbl56ZD/55nxRqij6sSa5b3g=; b=FdsMwySFTNPA3/UiSeT8Sswbss3NS8jHCrKWxRSfyYAV5VqCHKBm6k1n4Ydp7sqNUv 47PbxKrpOmLn5CdvMFOcQgyIk+eGT0L+64KVQgOVvG5qmxBT+qaJ7sp6yau3xc9Q3dKJ C6Ot+v04qD3klIgi0g17mfu1i8nhUB42ssMNlVFNtrqMrJCFxMPYgp94hTsXoy9WO5IT 3lwnz5PxtvVnbCfwGbymLtm+d6a8OZ2TSGZev7mbjK44BiV93mJ0L4SjD5+ikQNV6I6u dUrKEHki8vxKXDzQ7pmOA4onJ6aZru5GEw4ozY+vddpVWDayf9WQdx7RJOReVpZpLeNx yBVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vlSwlBzp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b6si8357727ilv.35.2021.10.14.21.22.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:22:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vlSwlBzp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56764 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEjt-0004U1-VL for patch@linaro.org; Fri, 15 Oct 2021 00:22:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38934) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYw-0007HN-SN for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:19 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:34599) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYs-0000Iw-DW for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:17 -0400 Received: by mail-pg1-x52a.google.com with SMTP id 133so7465608pgb.1 for ; Thu, 14 Oct 2021 21:11:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3zF39zy0stf9vN9RkqNLbl56ZD/55nxRqij6sSa5b3g=; b=vlSwlBzpTSzCOo6uDy228i1fRtfDFH0D9XV9HPegBJ5Z9jsFc81UGpszuHaWihay7w nFU1R5qcTFHR4B01h6nj17EmnZbRFnJpGofbURv7rSq0D0lKtsJisvjuzqLNSCb3bpUa i4zxIHIgHhMtBOGHH6jLDBGI8UVWlYRYeDDaEjumBIa1NdBItYueJ+2kV45ZXaOFBW3e C3akOdbiNt3DsIOT6sbxsdUhh9xLA0IRGN5TkpBWDYpWKo2mohoL6Xq92fp5Zo6BGJd/ aNYnsk7FRvA66/s3iYqtC8cQHDoEG0M0QRipRqHKtuCPFjdf9GbYdt3xS3aruYWw3mHr sPiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3zF39zy0stf9vN9RkqNLbl56ZD/55nxRqij6sSa5b3g=; b=AW7CNARYitMpbTwF+OWzmOeuvLwPDhPOzam4NPfOv9KyzvdgwFjTBmQRSqXkUvJK2Y V6BR6HITBX9ZREX04w3UhCB9nV7Yx1xHbFbvhCmyENyaywfe1u70ES/snXDPv3TRrcjf eepqUuJBaUIG/y0WeJP9w7VQ1JO73UoUbNDcygUUxRLDYnQWZ42pFXDnkokclAF4geF9 ZxSLKUOjql+rcP9ijyTG7mvCrH/rUGilKwcN9chSB/b/hMrsu2s7P+nZIJ5QUoExbwa9 KetbEAFawjqTFzXcdFPmH72gGkpaJYUPQY0sWTPAV+4Azc0NhzDZFCfD2UyINV8lwe6T GjwA== X-Gm-Message-State: AOAM532dOLlt6Q3vt72FswFmzUH/O++1GV0Zp+CZYTZ6NQgRXnMVu0wK 2FMArvbZpYl7C86aCYPg5Uz8p00mDLDCTw== X-Received: by 2002:a63:7450:: with SMTP id e16mr3552724pgn.482.1634271072146; Thu, 14 Oct 2021 21:11:12 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 20/67] linux-user: Add cpu_loop_exit_sigsegv Date: Thu, 14 Oct 2021 21:10:06 -0700 Message-Id: <20211015041053.2769193-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?P?= =?utf-8?q?hilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a new interface to be provided by the os emulator for raising SIGSEGV on fault. Use the new record_sigsegv target hook. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 15 +++++++++++++++ accel/tcg/user-exec.c | 33 ++++++++++++++++++--------------- linux-user/signal.c | 30 ++++++++++++++++++++++-------- 3 files changed, 55 insertions(+), 23 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5dd663c153..f74578500c 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -685,6 +685,21 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, uintptr_t host_pc, abi_ptr guest_addr); +/** + * cpu_loop_exit_sigsegv: + * @cpu: the cpu context + * @addr: the guest address of the fault + * @access_type: access was read/write/execute + * @maperr: true for invalid page, false for permission fault + * @ra: host pc for unwinding + * + * Use the TCGCPUOps hook to record cpu state, do guest operating system + * specific things to raise SIGSEGV, and jump to the main cpu loop. + */ +void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); + #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 2d9ab0a8b8..5646f8e527 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -143,35 +143,38 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, int fault_size, MMUAccessType access_type, bool nonfault, uintptr_t ra) { - int flags; + int acc_flag; + bool maperr; switch (access_type) { case MMU_DATA_STORE: - flags = PAGE_WRITE; + acc_flag = PAGE_WRITE_ORG; break; case MMU_DATA_LOAD: - flags = PAGE_READ; + acc_flag = PAGE_READ; break; case MMU_INST_FETCH: - flags = PAGE_EXEC; + acc_flag = PAGE_EXEC; break; default: g_assert_not_reached(); } - if (!guest_addr_valid_untagged(addr) || - page_check_range(addr, 1, flags) < 0) { - if (nonfault) { - return TLB_INVALID_MASK; - } else { - CPUState *cpu = env_cpu(env); - CPUClass *cc = CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_type, - MMU_USER_IDX, false, ra); - g_assert_not_reached(); + if (guest_addr_valid_untagged(addr)) { + int page_flags = page_get_flags(addr); + if (page_flags & acc_flag) { + return 0; /* success */ } + maperr = !(page_flags & PAGE_VALID); + } else { + maperr = true; } - return 0; + + if (nonfault) { + return TLB_INVALID_MASK; + } + + cpu_loop_exit_sigsegv(env_cpu(env), addr, access_type, maperr, ra); } int probe_access_flags(CPUArchState *env, target_ulong addr, diff --git a/linux-user/signal.c b/linux-user/signal.c index b816678ba5..135983747d 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -688,9 +688,27 @@ void force_sigsegv(int oldsig) } force_sig(TARGET_SIGSEGV); } - #endif +void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, bool maperr, uintptr_t ra) +{ + const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + + if (tcg_ops->record_sigsegv) { + tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); + } else if (tcg_ops->tlb_fill) { + tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, ra); + g_assert_not_reached(); + } + + force_sig_fault(TARGET_SIGSEGV, + maperr ? TARGET_SEGV_MAPERR : TARGET_SEGV_ACCERR, + addr); + cpu->exception_index = EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, ra); +} + /* abort execution with signal */ static void QEMU_NORETURN dump_core_and_abort(int target_sig) { @@ -806,7 +824,7 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) access_type = adjust_signal_pc(&pc, is_write); if (host_sig == SIGSEGV) { - const struct TCGCPUOps *tcg_ops; + bool maperr = true; if (info->si_code == SEGV_ACCERR && h2g_valid(host_addr)) { /* If this was a write to a TB protected page, restart. */ @@ -821,18 +839,14 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) * which means that we may get ACCERR when we want MAPERR. */ if (page_get_flags(guest_addr) & PAGE_VALID) { - /* maperr = false; */ + maperr = false; } else { info->si_code = SEGV_MAPERR; } } sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); - - tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; - tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, - MMU_USER_IDX, false, pc); - g_assert_not_reached(); + cpu_loop_exit_sigsegv(cpu, guest_addr, access_type, maperr, pc); } else { sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); } From patchwork Fri Oct 15 04:10:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515804 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp140405imi; Thu, 14 Oct 2021 21:27:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz5c8TPP/1cgv9hLKoQeLWElfaIlv2OdBDn4e+Wq5hsVl2DbdlPJgUFoXNOhEgIHUTIk2Nm X-Received: by 2002:a25:e697:: with SMTP id d145mr10009931ybh.4.1634272027122; Thu, 14 Oct 2021 21:27:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272027; cv=none; d=google.com; s=arc-20160816; b=kbKsBzl99aHrDpiJO7uGq/rcZuurAblt6BzmmGkFs4rRQNlSL7X4SZC3cRA9S4L9e0 09kACV028kZ8np+uEwUZLu7RIv7qBcbrbTexa4V2GSONM2FvbOCD9MCD+Xc+2ju7FQCF Hc8/wK4+cEotxBPYrWBXggP9ONIzYQldTEzg0unhBqDQFc9gbhKiHvcPSIUOZonKlwri DtmEfF6FmLDVY7iMgt933ON9NZS3/ffLyBA2ntvqxDm7r7FSwrTs/mhowocBoVnS2cWO nLcPbdp6av49Mud6otk8tfw6pepE+HbHqRFt9DXDtuNu3z3BzLVZFMHuABIG4wxf3af4 bVIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=v0FpA57qaJCc2VnO4R+7jKC7WxQwlNYWwLwncqceS+8=; b=kOR5fmAL30SD1c/aOSWU+c0lfHxUQRYq9NM6ttk+69g+Wb5Ck4OTrpwaMnft3d3qhX 7fBoQmKnKnIUBaD1vM1992ZRkmol8yO9ma8OPbmG2S9+UbT1eJFbwn9YqQ1H01KXvfVf 7j6TMGJ3LvIno78d+cHrrczkKDHkLrCqJ3g8F8B6w+jmtqPLr9+0T2f0A+oJkXcWSWpS atwbLOd0PQvdK+gC2xPFtdBR6MiYsUe3vFmIJIPiGHc9jisSGtApRh3mOjR/306y5rhJ LE3H8B2923KNystxudZLAMv6xPXUKiVFjrfU9QZDB2pINN1sU/teZfeOALzP+Am5dhze cGkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MJNpwSV+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fill in the stores to trap_arg{1,2} that were missing from the previous user-only alpha_cpu_tlb_fill function. Use maperr to simplify computation of trap_arg1. Remove the code for EXCP_MMFAULT from cpu_loop, as that part is now handled by cpu_loop_exit_sigsegv. Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 13 +++++++++---- linux-user/alpha/cpu_loop.c | 8 -------- target/alpha/cpu.c | 6 ++++-- target/alpha/helper.c | 39 ++++++++++++++++++++++++++++++++----- 4 files changed, 47 insertions(+), 19 deletions(-) -- 2.25.1 diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 772828cc26..d49cc36d07 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -439,9 +439,6 @@ void alpha_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU void alpha_cpu_list(void); -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); @@ -449,7 +446,15 @@ uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env); void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val); uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg); void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val); -#ifndef CONFIG_USER_ONLY + +#ifdef CONFIG_USER_ONLY +void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr); +#else +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 1b00a81385..4cc8e0a55c 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -54,14 +54,6 @@ void cpu_loop(CPUAlphaState *env) fprintf(stderr, "External interrupt. Exit\n"); exit(EXIT_FAILURE); break; - case EXCP_MMFAULT: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID - ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); - info._sifields._sigfault._addr = env->trap_arg0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_UNALIGN: info.si_signo = TARGET_SIGBUS; info.si_errno = 0; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 93e16a2ffb..69f32c3078 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -218,9 +218,11 @@ static const struct SysemuCPUOps alpha_sysemu_ops = { static const struct TCGCPUOps alpha_tcg_ops = { .initialize = alpha_translate_init, - .tlb_fill = alpha_cpu_tlb_fill, -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv = alpha_cpu_record_sigsegv, +#else + .tlb_fill = alpha_cpu_tlb_fill, .cpu_exec_interrupt = alpha_cpu_exec_interrupt, .do_interrupt = alpha_cpu_do_interrupt, .do_transaction_failed = alpha_cpu_do_transaction_failed, diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 81550d9e2f..b7e7f73b15 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -120,15 +120,44 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val) } #if defined(CONFIG_USER_ONLY) -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { AlphaCPU *cpu = ALPHA_CPU(cs); + target_ulong mmcsr, cause; - cs->exception_index = EXCP_MMFAULT; + /* Assuming !maperr, infer the missing protection. */ + switch (access_type) { + case MMU_DATA_LOAD: + mmcsr = MM_K_FOR; + cause = 0; + break; + case MMU_DATA_STORE: + mmcsr = MM_K_FOW; + cause = 1; + break; + case MMU_INST_FETCH: + mmcsr = MM_K_FOE; + cause = -1; + break; + default: + g_assert_not_reached(); + } + if (maperr) { + if (address < BIT_ULL(TARGET_VIRT_ADDR_SPACE_BITS - 1)) { + /* Userspace address, therefore page not mapped. */ + mmcsr = MM_K_TNV; + } else { + /* Kernel or invalid address. */ + mmcsr = MM_K_ACV; + } + } + + /* Record the arguments that PALcode would give to the kernel. */ cpu->env.trap_arg0 = address; - cpu_loop_exit_restore(cs, retaddr); + cpu->env.trap_arg1 = mmcsr; + cpu->env.trap_arg2 = cause; } #else /* Returns the OSF/1 entMM failure indication, or -1 on success. */ From patchwork Fri Oct 15 04:10:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515806 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp141044imi; Thu, 14 Oct 2021 21:28:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzz0LRwPup4MszvUwJfyb5my3RpCTiQC5HACoz3ShT70ubX1FDdwAOVwhs5D7NiEZj+QIMO X-Received: by 2002:a92:4a04:: with SMTP id m4mr2236132ilf.137.1634272105827; Thu, 14 Oct 2021 21:28:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272105; cv=none; d=google.com; s=arc-20160816; b=b1HkgYZnOeNXfo6kEDzNQpYLPB5iMZEzWA2L8r2F0tiEbEpFINb2lXQt86aNfHhNye T2lOxv/9wvl3apZR67XPao3VNDvc9NzNPI0mMQBnQqGZBq8PpO4nwAaADMUg3ixfhX7S ucRtwkXwqD+/JeM4qIrcBWIYx03YnLZwmca0wMcSxkAQc9CEn4cKcQel5FsIN5k2k6Ls 1O/VRdc461oJWnaIEeL0U2tKdlls0pOwUdRRsz58MuvrFxWl7Ik8lXemzxzm7N+1zwN9 s+LCGgzOVNlZnXhrVYulz9yVcmWrIgiEabu4ScMgVVFQEPgjtP0qyQ/dp7m0xSvVgRgp 1g9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gDo26nxZuCe6knbSSj4pxxnp0xROgd5wgByOtwEaQmw=; b=F3ptjH/2AYyWx7wXUWIVP++Jsm9IBfAGM0jGhx9hdOUZ12Ys7dbse2O983WpdpgXL5 nH3+6qefARrR28fG+RgL5Ad3cKNFWe8Ff4ISh82YlyyS2dHmO1In2zHJMWW5vaeXDx9F rnW3f9Fny6lzUSRGGwzoG8I8anNKvfac0SaNVe8F4GdAPxbZNoYt+Ccm6dNHPA0oxCz9 91PuLhGfHxLoIQmDqXZ2dRnGC3rPgYm42B5fzCzKbLPxL/ZFo8lo5ESM65MOnvRXB/Od rFb2VkYe+RcqlxSYYRcgy9KJ43VRPtNuA7aBruIU9lWaDQ8nNw+PMbwcLbduEH1j8w0t yBJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="SUyDN/bf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g4si9292968ila.181.2021.10.14.21.28.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:28:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="SUyDN/bf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48962 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEpV-0001GL-6k for patch@linaro.org; Fri, 15 Oct 2021 00:28:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYw-0007HY-UT for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:19 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:44928) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYt-0000Kq-2z for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:18 -0400 Received: by mail-pf1-x42c.google.com with SMTP id v8so3157928pfu.11 for ; Thu, 14 Oct 2021 21:11:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gDo26nxZuCe6knbSSj4pxxnp0xROgd5wgByOtwEaQmw=; b=SUyDN/bfj0pqlmb4veDFS7djOwRGHBtR8olsDB7rbMU9HqnIaNvkuCOH2u+Bg77bML NpXcn9smrHVUR3O/lG6oCWaiN4/XfH+wiNyxttxthkCuuaKE4dfLJEemRbw0XCLfmTYu pn2ODCUAqMZ3N3jZLVP8sRpii8uYMuL0JDCEONcQolzf0WptIX1o8nWV26pWhSLbnq8p J8hTjb87HrVA1vkBGtRsftOaBl9U8o6EoflgSRiYXjTLUVqWcY6GCSE11wdM8bDZkJUl zU6kb6e4+7yOgIy9+2siq9U30ySKrB5HgriUdnBIfQX8e/GBVjEFuW6BbcX5n3EU/obd Csow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gDo26nxZuCe6knbSSj4pxxnp0xROgd5wgByOtwEaQmw=; b=W0b8GJYyyRs1ZZ7hDe3dSGdRVorINJ8gJKcNNiNNtPX4OVRrcSMRPKNHVx4x0FYHIL 0Z087h4nYLm0qrhXstSQpspg5FUpxjbEK3fNvmxLADFZR1zt3Z4O0n5KjRtQHKQVLuzw f9WKHkN2/XVsc0z58DOsmoIQnbgcNGD6lzRhbXTAsQBZA9W2lQLTS2By9zJyN0G0WSMI S79rS8ln2cmP8ihRpyeXp0o7gbTbQtwNPSsuNb6sMXj4nXsxmyl48+ReE+kxnY3a1jVC 4vn6Ss20dYS7zVO1/BGWAK0s3m48OSRBMg06gOJ6PCZkpXi2quWaL6BpIjzR1QGnJERu OdGg== X-Gm-Message-State: AOAM532RpKQwrEu+/2cEsqMxp2cVKZziOWveuZ/veMlKQbsf+I+/XfeG ofjVNFu4m5STnsJncAL0cvFni/28Ljg= X-Received: by 2002:a63:b204:: with SMTP id x4mr7163143pge.212.1634271073744; Thu, 14 Oct 2021 21:11:13 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 22/67] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup Date: Thu, 14 Oct 2021 21:10:08 -0700 Message-Id: <20211015041053.2769193-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?P?= =?utf-8?q?hilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the new os interface for raising the exception, rather than calling arm_cpu_tlb_fill directly. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 724175210b..e09b7e46a2 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -84,10 +84,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, uintptr_t index; if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE_ORG : PAGE_READ))) { - /* SIGSEGV */ - arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access, - ptr_mmu_idx, false, ra); - g_assert_not_reached(); + cpu_loop_exit_sigsegv(env_cpu(env), ptr, ptr_access, + !(flags & PAGE_VALID), ra); } /* Require both MAP_ANON and PROT_MTE for the page. */ From patchwork Fri Oct 15 04:10:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515796 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp137960imi; Thu, 14 Oct 2021 21:22:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyJdbDPQskb1rcBEKqRdKV/Bv5HLPq6Zo0SBGEWGambr3SCNytLrUIPPRm3/i6GLfqWJOBQ X-Received: by 2002:a25:3b04:: with SMTP id i4mr10809260yba.524.1634271761009; Thu, 14 Oct 2021 21:22:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271761; cv=none; d=google.com; s=arc-20160816; b=qOt62/42uyruJFHRWJ/DrwpF9Cy0487EkVLGSHSDdz2VQCBV08MBgB0v6bxjZjcl5/ hel/f14i8FfNi5NtEeJ9bKSmVlSzXvARpiFUob4PofOeixuldAPHPaAw2FvGVgeRAclf PkJ4XGrjtHg8cj6JIoG6/XZQbigeaC1/1Xg5afCS8CXV6lqtDb1L2ifitdJAfKlIZIwR UTpH2PmE7mmu91lv2ReycllYYLRl0mfxWSumnTzCgVi1byAB6ZYzY87xvQVPdxQHEoSE kxc2wVZczfyvhHt5xRs7O8dWLDeViB6I9lM7LGdB1tbgW6wfxAo87cjnpFOi/9Y8qvUA qNpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FxRJbycecCGMYDwBryMZJTmIk0vSiUV5vp8YTTExVU4=; b=x7prHKRCrbDibcmdBH5lNmWixBuDXIhR25fWQSuPhxJsuF0QefwYP8uCn7LNSYDBll 9Kt/PeXbAyBMWHETrZN1fYpfJEg6gcIV+aE9QjF2mMqdw8bBxpGDnegoef5eo3M46nyn 3OFq/BbMhsIr9q5BcmdSclLin4lcJWfKx/zuhnb51Y+GaM3jhf9EbYp7N4WOxd8M4qD+ bIm2gD0Q1MojEM9wLXzdWusHIvRRHSK2i6KFf2oMrpVv2UKOrE1MCH30dEDPzjDGLB/u GDlevehZbugIMX8Dfv/7b7nwX+sEITXerl+RrsqcDfF5OsO6lkAp/muM/e8WyGoHuOY6 nVug== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WfyhWSFh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This means we cannot remove the code within cpu_loop that decodes EXCP_DATA_ABORT and EXCP_PREFETCH_ABORT. But using the new hook means that we don't have to do the page_get_flags check manually, and we'll be able to restrict the tlb_fill hook to sysemu later. Signed-off-by: Richard Henderson --- target/arm/internals.h | 6 ++++++ target/arm/cpu.c | 6 ++++-- target/arm/cpu_tcg.c | 6 ++++-- target/arm/tlb_helper.c | 36 +++++++++++++++++++----------------- 4 files changed, 33 insertions(+), 21 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/arm/internals.h b/target/arm/internals.h index 3612107ab2..5a7aaf0f51 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -544,9 +544,15 @@ static inline bool arm_extabort_type(MemTxResult result) return result != MEMTX_DECODE_ERROR; } +#ifdef CONFIG_USER_ONLY +void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 641a8c2d3d..7a18a58ca0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2031,10 +2031,12 @@ static const struct SysemuCPUOps arm_sysemu_ops = { static const struct TCGCPUOps arm_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, - .tlb_fill = arm_cpu_tlb_fill, .debug_excp_handler = arm_debug_excp_handler, -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv = arm_cpu_record_sigsegv, +#else + .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_cpu_exec_interrupt, .do_interrupt = arm_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0d5adccf1a..7b3bea2fbb 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -898,10 +898,12 @@ static void pxa270c5_initfn(Object *obj) static const struct TCGCPUOps arm_v7m_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, - .tlb_fill = arm_cpu_tlb_fill, .debug_excp_handler = arm_debug_excp_handler, -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv = arm_cpu_record_sigsegv, +#else + .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, .do_interrupt = arm_v7m_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 3107f9823e..dc5860180f 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -147,28 +147,12 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } -#endif /* !defined(CONFIG_USER_ONLY) */ - bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { ARMCPU *cpu = ARM_CPU(cs); ARMMMUFaultInfo fi = {}; - -#ifdef CONFIG_USER_ONLY - int flags = page_get_flags(useronly_clean_ptr(address)); - if (flags & PAGE_VALID) { - fi.type = ARMFault_Permission; - } else { - fi.type = ARMFault_Translation; - } - fi.level = 3; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); -#else hwaddr phys_addr; target_ulong page_size; int prot, ret; @@ -210,5 +194,23 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_restore_state(cs, retaddr, true); arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); } -#endif } +#else +void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra) +{ + ARMMMUFaultInfo fi = { + .type = maperr ? ARMFault_Translation : ARMFault_Permission, + .level = 3, + }; + ARMCPU *cpu = ARM_CPU(cs); + + /* + * We report both ESR and FAR to signal handlers. + * For now, it's easiest to deliver the fault normally. + */ + cpu_restore_state(cs, ra, true); + arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi); +} +#endif /* !defined(CONFIG_USER_ONLY) */ From patchwork Fri Oct 15 04:10:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515810 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp142512imi; Thu, 14 Oct 2021 21:31:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwNewXkDWO7C3HangCqaeCoYrd6fqOf5v8LFhuvisL4ygTceOqVCmxNI3cGSS2XLfvXjy+H X-Received: by 2002:a25:bd49:: with SMTP id p9mr10249155ybm.319.1634272283792; Thu, 14 Oct 2021 21:31:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272283; cv=none; d=google.com; s=arc-20160816; b=e24gV5+EHucVzt00LJPmCESkR5ltEb4XwV4fvlAtxaxCJqIuokbvAYQcKMRrFmx7z5 NbmebMXPHR3d5+sjYVeZlZV0syZbUa/EsIWHhvbD7SviiT+LgeZGYvTKBkZz4/eLIjC4 t3QzQkgkCMWgtwL2Qak67UkKCwn2EyGizx4NV5IKaLc0/V6CJ8By+bEku5v+B8kyg4lI ZHe6gBoAralWtGNutewPE7XoBqpXHj6A2Aj1hTanMFk4dJe4ykgySfwrjUKpERD747n4 gNvveT8hJGeK7IB96D+i4dpG+565BbLpxvBLeorZJUJ+NoRy9Xgpk3PFvHGh/q0tkV7/ 4f7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LvK67GkX13tDj2L9Y8ql/Gd7bbn2JZgBQ3dF7lXKOxQ=; b=ksPNAfpcCRxUYUKM3KsFtMgta9T/+NFtYN0ILipbROtRDurt4BTslI5jJ5k2TJ7LNO 6wQ8XtsuDasA4W3enClzIeVsy7wOQ1yjpcftb3ARfe6l0BkyZwiFPPbDQv0+fYgHxAlU s3ejREZkarz+br+QN8C5qxdMIq4y0JG16hht+hizNsSlaOKVJU8xEA8+pqYsnPqtJ9af dDuYkJqug1wzyu1rUWKQNy9q7cDf6uU6HJlRidbAAIB+MGOfoOUJlAInaBuZQABKniBe zBNT4zXVCb2yhqsfLLVrfgQ6pgKo3HV4pe1MeV000JC9sn3rncQihg2n2p1qaYRPDEp2 /feg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OInV1vFi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Remove the code from cpu_loop that handled the unnamed 0xaa exception. This makes all of the code in helper.c sysemu only, so remove the ifdefs and move the file to cris_softmmu_ss. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/cris/cpu.h | 8 ++++---- linux-user/cris/cpu_loop.c | 10 ---------- target/cris/cpu.c | 4 ++-- target/cris/helper.c | 18 ------------------ target/cris/meson.build | 7 +++++-- 5 files changed, 11 insertions(+), 36 deletions(-) -- 2.25.1 diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 6603565f83..b445b194ea 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -189,6 +189,10 @@ extern const VMStateDescription vmstate_cris_cpu; void cris_cpu_do_interrupt(CPUState *cpu); void crisv10_cpu_do_interrupt(CPUState *cpu); bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req); + +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #endif void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags); @@ -251,10 +255,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) return !!(env->pregs[PR_CCS] & U_FLAG); } -bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); - /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0 diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index b9085619c4..0d5d268609 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -37,16 +37,6 @@ void cpu_loop(CPUCRISState *env) process_queued_cpu_work(cs); switch (trapnr) { - case 0xaa: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->pregs[PR_EDA]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index c2e7483f5b..ed6c781342 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -205,9 +205,9 @@ static const struct SysemuCPUOps cris_sysemu_ops = { static const struct TCGCPUOps crisv10_tcg_ops = { .initialize = cris_initialize_crisv10_tcg, - .tlb_fill = cris_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = cris_cpu_tlb_fill, .cpu_exec_interrupt = cris_cpu_exec_interrupt, .do_interrupt = crisv10_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ @@ -215,9 +215,9 @@ static const struct TCGCPUOps crisv10_tcg_ops = { static const struct TCGCPUOps crisv32_tcg_ops = { .initialize = cris_initialize_tcg, - .tlb_fill = cris_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = cris_cpu_tlb_fill, .cpu_exec_interrupt = cris_cpu_exec_interrupt, .do_interrupt = cris_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/cris/helper.c b/target/cris/helper.c index 36926faf32..a0d6ecdcd3 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -39,22 +39,6 @@ #define D_LOG(...) do { } while (0) #endif -#if defined(CONFIG_USER_ONLY) - -bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - CRISCPU *cpu = CRIS_CPU(cs); - - cs->exception_index = 0xaa; - cpu->env.pregs[PR_EDA] = address; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - - static void cris_shift_ccs(CPUCRISState *env) { uint32_t ccs; @@ -304,5 +288,3 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return ret; } - -#endif /* !CONFIG_USER_ONLY */ diff --git a/target/cris/meson.build b/target/cris/meson.build index 67c3793c85..c1e326d950 100644 --- a/target/cris/meson.build +++ b/target/cris/meson.build @@ -2,13 +2,16 @@ cris_ss = ss.source_set() cris_ss.add(files( 'cpu.c', 'gdbstub.c', - 'helper.c', 'op_helper.c', 'translate.c', )) cris_softmmu_ss = ss.source_set() -cris_softmmu_ss.add(files('mmu.c', 'machine.c')) +cris_softmmu_ss.add(files( + 'helper.c', + 'machine.c', + 'mmu.c', +)) target_arch += {'cris': cris_ss} target_softmmu_arch += {'cris': cris_softmmu_ss} From patchwork Fri Oct 15 04:10:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515807 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp141748imi; 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[209.51.188.17]) by mx.google.com with ESMTPS id s203si5586646ybb.161.2021.10.14.21.29.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:29:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Y5qiD56R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54142 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEqu-0004ht-O4 for patch@linaro.org; Fri, 15 Oct 2021 00:29:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38992) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ0-0007LQ-K0 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:22 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:40931) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYv-0000MR-MK for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:22 -0400 Received: by mail-pf1-x42f.google.com with SMTP id o133so7289603pfg.7 for ; Thu, 14 Oct 2021 21:11:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z8ecs4LTwGjkTaIMjFwaDU18rjRNxTTeFlYdhpfOXR8=; b=Y5qiD56RsJ8Nq4PW05mNcjMMjwYz2jfPvkW213stwBafxD4PnzgoAYsX1S6nD2Yff5 de+rItUoevaMOdp9l6RQsoWkmi2bTp04yWCaqGqdijdPL17LA3YrNMdKVD3gocNVwcyD kjrpR9U/ZB4FX3dxKpM2yzJA5da660XKvyph7gxMPQNT3RSJ6z/QoQr/F4DeP70SeP5D uc1gu+m2vvDyGsLofkx0IwnME4q0QyYpt27YpksB0IwLjEuPrG8Pc0Ah9bNJ10Zxo+8P 9nKp/gFFNURkgBvFH+y4ksW33d7QdVxSGLR5JG57+51T9Fxxp8jOQjIM3zLd0wUBAZSD Y+RQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z8ecs4LTwGjkTaIMjFwaDU18rjRNxTTeFlYdhpfOXR8=; b=lPD086icM7Ut+6n/ZgF6gWCpa1hd8xPwN2HVCWJCmbRSw4Tza+ZyqY9u2DrscZCCMg B+A/yFU5iQ0JYlSDk+53UNMsQA2kyMWXrK6SndvYV4cw9qQGrVNix/LSHouyqROJtr2t 3knzvfrr23fBOqRVIRT97NStcjYLMdkcM/b84LHFrOt4m6LLbgLx85tFKOtb+AcN2/Fv Z1j2H+s8yKBFUHRjP0lkDLj4b7icp6/Jnq8W1YE/ppL+xP5BTVYNeUGFWHDbiv0icQtd lpWIzxlGu5agtoZCXXut1XGogv+O+IZVgeSW7IPVZ6FQZ+X/1sdz68hAAw7Xc+6WzFZ+ y/rQ== X-Gm-Message-State: AOAM530/xjU5q6CxDrZsx2EKCMbFtCERAHtk6NnI9QD9hqmW/X0RMTwN rlyru+XxYVszQHQoboMbF63XOa0nPth92Q== X-Received: by 2002:a65:62d1:: with SMTP id m17mr7324322pgv.370.1634271076273; Thu, 14 Oct 2021 21:11:16 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 25/67] target/hexagon: Remove hexagon_cpu_tlb_fill Date: Thu, 14 Oct 2021 21:10:11 -0700 Message-Id: <20211015041053.2769193-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Taylor Simpson , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for hexagon linux-user. Remove the code from cpu_loop that raises SIGSEGV. Reviewed-by: Taylor Simpson Signed-off-by: Richard Henderson --- linux-user/hexagon/cpu_loop.c | 24 +----------------------- target/hexagon/cpu.c | 23 ----------------------- 2 files changed, 1 insertion(+), 46 deletions(-) -- 2.25.1 diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index bee2a9e4ea..6b24cbaba9 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -28,8 +28,7 @@ void cpu_loop(CPUHexagonState *env) { CPUState *cs = env_cpu(env); - int trapnr, signum, sigcode; - target_ulong sigaddr; + int trapnr; target_ulong syscallnum; target_ulong ret; @@ -39,10 +38,6 @@ void cpu_loop(CPUHexagonState *env) cpu_exec_end(cs); process_queued_cpu_work(cs); - signum = 0; - sigcode = 0; - sigaddr = 0; - switch (trapnr) { case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ @@ -65,12 +60,6 @@ void cpu_loop(CPUHexagonState *env) env->gpr[0] = ret; } break; - case HEX_EXCP_FETCH_NO_UPAGE: - case HEX_EXCP_PRIV_NO_UREAD: - case HEX_EXCP_PRIV_NO_UWRITE: - signum = TARGET_SIGSEGV; - sigcode = TARGET_SEGV_MAPERR; - break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); break; @@ -79,17 +68,6 @@ void cpu_loop(CPUHexagonState *env) trapnr); exit(EXIT_FAILURE); } - - if (signum) { - target_siginfo_t info = { - .si_signo = signum, - .si_errno = 0, - .si_code = sigcode, - ._sifields._sigfault._addr = sigaddr - }; - queue_signal(env, info.si_signo, QEMU_SI_KILL, &info); - } - process_pending_signals(env); } } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 3338365c16..160a46a3d5 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -245,34 +245,11 @@ static void hexagon_cpu_init(Object *obj) qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property); } -static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ -#ifdef CONFIG_USER_ONLY - switch (access_type) { - case MMU_INST_FETCH: - cs->exception_index = HEX_EXCP_FETCH_NO_UPAGE; - break; - case MMU_DATA_LOAD: - cs->exception_index = HEX_EXCP_PRIV_NO_UREAD; - break; - case MMU_DATA_STORE: - cs->exception_index = HEX_EXCP_PRIV_NO_UWRITE; - break; - } - cpu_loop_exit_restore(cs, retaddr); -#else -#error System mode not implemented for Hexagon -#endif -} - #include "hw/core/tcg-cpu-ops.h" static const struct TCGCPUOps hexagon_tcg_ops = { .initialize = hexagon_translate_init, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, - .tlb_fill = hexagon_tlb_fill, }; static void hexagon_cpu_class_init(ObjectClass *c, void *data) From patchwork Fri Oct 15 04:10:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515814 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp144030imi; Thu, 14 Oct 2021 21:33:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyhWIdNKY6zue1E6+NoSFn5fZpgXgslHEpu6xMKn7b1ZuzgEJ5PhQq4urGv0QVfm3dl9b05 X-Received: by 2002:a25:6908:: with SMTP id e8mr10329175ybc.337.1634272439268; Thu, 14 Oct 2021 21:33:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272439; cv=none; d=google.com; s=arc-20160816; b=FIJG3+9+1WAZuqPXOi5c5pxS/+1TYz9SoS2AQbPki1uyv89uhURzRfsWWoCBR9tkKz ZUfzQzbstdjFVA6AvYbRxIgzIk5dZnfQJNH7Npfb3LEkQ0lB8vuGzfqizhhXejxMoS9U guRAyM8LGS6cjYyjQmITkOmUy13a3YYeIaN2mZ+/FXC2vUFQYziwq/FYLQZ8xOCbMgNa XdD0MEGdks5RO3j+cwFErhxNZCoQKkuEVOuZ52ww0UP8ZWf9oAtZqkjMwf/+3imH0P5n O9mWJdz0RXDBZLrwNG9rRMKd9Vu7SVvRTibapaE7izZGgcL4MmMInZk+lIgzYx6ZICZh X1EA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xDn64Ar0c4NUi8qPBLq+7M9+nijncdxsp88/28xGJnw=; b=FHGndREZ4Obx+elWzkIQbwyJqk/WZvMGL1sflow7XkO5MgIK1zCJs0bY0yKA47JWqB 5qTEeVIgkmcQKxkZ6iG4ZhHWmympDT2zX3XaVZMy9rNQn2G/VdnLu9kG5jinEw6dg5E5 fvbpKoMqs79rxIHxa9rNH6TwMLhN+nt40x4NmD3cwHQEKB3BAxMZ7MwqJGwmGU/17LUI TTgx+UJfomXFYjV9f6SgFkRkKj7Q9MckwweqKtMsZu+AaMSZm5u/o1enhlgX3+7hsRMg kAwvM2jSpgOOJr1ipdIwn54h3x9X1RPhczw/tzmDC9Yj/Auj7/p6YP7e820UulyGxCyg wjzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Yov1R+NL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s128si5632846ybb.78.2021.10.14.21.33.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:33:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Yov1R+NL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEus-000413-GM for patch@linaro.org; Fri, 15 Oct 2021 00:33:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39022) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ2-0007No-LU for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:24 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:34605) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYw-0000Nj-Hv for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:23 -0400 Received: by mail-pg1-x530.google.com with SMTP id 133so7465770pgb.1 for ; Thu, 14 Oct 2021 21:11:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xDn64Ar0c4NUi8qPBLq+7M9+nijncdxsp88/28xGJnw=; b=Yov1R+NL044SWENOR1xG+VONSMx58VYed3LLoUluBL2dM/Wpek9T8T16O7dkctxn7J ND58+ed9JcpXTNwEj3XfFWQdDtKlnw8cPTsmnvPt52Q9atGaKQQwG1n18UIC93r7uULA 9awjU3UnOFXRyi/YNs0Ik/eC1MjtkMmPPaML83cWiMXjK2NqdsE1PFe6u+7sx7ciyRIx /6FSrv+hTJ9pMn+giMKD4jV3HYmY8yCxCl/iWXpMmKGJVh0AVd/Cisb9J7KDzNPp83aZ JYT3xPHU+MQZtWST7kBnG/pV78VbXJqn8+OZRUTw/Pzj6yrEfLxKmzsD/JV6rn5hPHyz s+iA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xDn64Ar0c4NUi8qPBLq+7M9+nijncdxsp88/28xGJnw=; b=3hBA1WE0rZ/PzZepRb8tYibxQtLmciBNqXHvoOXiBoPl9BkdSKjnMpdHmhPJtFmcS0 2SubHS7qdsNrGjn+lMkep/w0U508YwhhXfl2t528J2QMJ3XWnYsZ0JwgIq93O+awWuju uRLdQs3+NPFDTVSjj4nad8Kswbz6Qb1eflKc9isXIUrt3PneeLoOJeECSql9qRXwEc7m Fa3be278VIA3VVkBNl7R5KE4gss8Wn4bogKJYPWYoavRRS8+lcz6qpr+6+ezjvM74+it RL8XWAqghrZwu6jFJO7KMA+Q2QtqPDBlbHCew5deRkGnOnrYMHQR91KmBUdCiQyMFXkx Ulwg== X-Gm-Message-State: AOAM533AheQ08wQ2svfBPDQzmTl4+zkTdONYuvWbFTzU4X3ppxm16lhk U5/6axH/oz/pN4a0bQkABm98+OE/wxIHcQ== X-Received: by 2002:a63:d94b:: with SMTP id e11mr7211521pgj.295.1634271076937; Thu, 14 Oct 2021 21:11:16 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 26/67] target/hppa: Make hppa_cpu_tlb_fill sysemu only Date: Thu, 14 Oct 2021 21:10:12 -0700 Message-Id: <20211015041053.2769193-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for hppa linux-user. Remove the code from cpu_loop that raised SIGSEGV. This makes all of the code in mem_helper.c sysemu only, so remove the ifdefs and move the file to hppa_softmmu_ss. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 +- linux-user/hppa/cpu_loop.c | 16 ---------------- target/hppa/cpu.c | 2 +- target/hppa/mem_helper.c | 15 --------------- target/hppa/meson.build | 6 ++++-- 5 files changed, 6 insertions(+), 35 deletions(-) -- 2.25.1 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index d3cb7a279f..294fd7297f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -323,10 +323,10 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); +#ifndef CONFIG_USER_ONLY bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -#ifndef CONFIG_USER_ONLY void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 81607a9b27..e0a62deeb9 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -144,22 +144,6 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f = env->gr[31]; env->iaoq_b = env->gr[31] + 4; break; - case EXCP_ITLB_MISS: - case EXCP_DTLB_MISS: - case EXCP_NA_ITLB_MISS: - case EXCP_NA_DTLB_MISS: - case EXCP_IMP: - case EXCP_DMP: - case EXCP_DMB: - case EXCP_PAGE_REF: - case EXCP_DMAR: - case EXCP_DMPI: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr = env->cr[CR_IOR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_UNALIGN: info.si_signo = TARGET_SIGBUS; info.si_errno = 0; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 89cba9d7a2..23eb254228 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -145,9 +145,9 @@ static const struct SysemuCPUOps hppa_sysemu_ops = { static const struct TCGCPUOps hppa_tcg_ops = { .initialize = hppa_translate_init, .synchronize_from_tb = hppa_cpu_synchronize_from_tb, - .tlb_fill = hppa_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = hppa_cpu_tlb_fill, .cpu_exec_interrupt = hppa_cpu_exec_interrupt, .do_interrupt = hppa_cpu_do_interrupt, .do_unaligned_access = hppa_cpu_do_unaligned_access, diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index afc5b56c3e..bf07445cd1 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -24,20 +24,6 @@ #include "hw/core/cpu.h" #include "trace.h" -#ifdef CONFIG_USER_ONLY -bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - HPPACPU *cpu = HPPA_CPU(cs); - - /* ??? Test between data page fault and data memory protection trap, - which would affect si_code. */ - cs->exception_index = EXCP_DMP; - cpu->env.cr[CR_IOR] = address; - cpu_loop_exit_restore(cs, retaddr); -} -#else static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) { int i; @@ -392,4 +378,3 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr) hppa_tlb_entry *ent = hppa_find_tlb(env, vaddr); return ent ? ent->ar_type : -1; } -#endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/meson.build b/target/hppa/meson.build index 8a7ff82efc..021e42a2d0 100644 --- a/target/hppa/meson.build +++ b/target/hppa/meson.build @@ -7,13 +7,15 @@ hppa_ss.add(files( 'gdbstub.c', 'helper.c', 'int_helper.c', - 'mem_helper.c', 'op_helper.c', 'translate.c', )) hppa_softmmu_ss = ss.source_set() -hppa_softmmu_ss.add(files('machine.c')) +hppa_softmmu_ss.add(files( + 'machine.c', + 'mem_helper.c', +)) target_arch += {'hppa': hppa_ss} target_softmmu_arch += {'hppa': hppa_softmmu_ss} From patchwork Fri Oct 15 04:10:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515811 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp143318imi; Thu, 14 Oct 2021 21:32:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz8UjUqRQFGPtCvWzOiF7bYFWn/quntzJ4iuCyA54wsX5Ow+cJGlDHO7+6Y+eBuDmd7b18k X-Received: by 2002:a05:6e02:154a:: with SMTP id j10mr2307031ilu.267.1634272366357; Thu, 14 Oct 2021 21:32:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272366; cv=none; d=google.com; s=arc-20160816; b=ZMSlxHsz3+TSt2tNVac0R6Xis0GoTmGIHcVXz4PeW9Q74MA1O5ytdHOoL67ssMqy9o 6iNim/QoSNSkshpg2FwnV7mpwo3g1r35DBq9Kx98N/fj6lJBkHeY9jJWc2uLv9OkDqZy fVY0x99la7cMmTMLBGNCWev9PCJZUxW3El2qnNnkjQkjbch6mLplBNW0s4NO52GT/lQg j4A0dlPVn9L6YZ9DFiN++iEki5UH+4TgOMXgCmJEuWO2+EM6nlqPXLeCgwC65Wj+AaQd xi/IDMYhcoMockmxdPtPCXd77tfXIJnUdJDd3kqXEgAc7V/AvfqL+2VxU07lYggVzNfh 1UhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Bcv7+vrfVWDaxhREKP7oW3QycojCjuZf0xWMtNuZYi8=; b=CSXxaeos6bR0MjoxPB50IlMnOxDuyi5BEhVyKr6p1ZHbUIg/Oy9cLKdiqTXYQpEral mywCkUHCtosrMwAkkEt1Op4lVm4PULePjOje5GUOgtz4PQ2aG0JpsjnwTkNpmempC355 0peh7M+3bC3xTUOTxYgFocQ6+YXiSKISoPrGqzhURNbOx3DIWd82YEaDQUwxz+ZcVMsu XLLR+PRfAwAL1L0CWGB8L6wgZMv/JSazLvvx8ttDSAw8T2lpyEKiSEXQ468GC0dgmzYR 28GZP9/pA4kLKWjtZPpU9YUWYH79NH+JC8WjkvMz82Yc7SXDnhn03HenDhP9YmyLCDSQ eAkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nqjIwyO7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z11si9260610jat.68.2021.10.14.21.32.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:32:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nqjIwyO7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34290 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEth-0001xB-Kz for patch@linaro.org; Fri, 15 Oct 2021 00:32:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ8-0007Se-94 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:30 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:33489) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYy-0000OQ-Ab for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:26 -0400 Received: by mail-pg1-x533.google.com with SMTP id j190so699112pgd.0 for ; Thu, 14 Oct 2021 21:11:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Bcv7+vrfVWDaxhREKP7oW3QycojCjuZf0xWMtNuZYi8=; b=nqjIwyO7/ZRFzBPLOzhopXQZLFm+44ULxd4SnMfqxFopMonT56mMtoiQiD3DaMjYqQ I356AZsJYnrdLddc2Ilv2QCStubgYhuPMVEDfdYZa2Y4y2qLi1DZ1XAVxAs2fNSWJi/4 EXIg0+Optnbz12ixi1cvonfEegRbuwVYr7HZ66WFMGhSRAy+yBy6RLxyUxGeFXfJS93x v5UR1hAYDW2tk4Hbw695Ysdqfaiq6FsvnJXdW06uCndeB7rho3807nYOpQhQzYfiAZ/8 8X5CY/GMu1AvmS96k7BfD9TOELsnFdZvNe3mp4jo8DYEk7Fv0wnV927gPxhVPguMczTm TUjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Bcv7+vrfVWDaxhREKP7oW3QycojCjuZf0xWMtNuZYi8=; b=sHrRtzo57idoP+VOtFYmSPjrvAkC0sVM8QzQKwUsLcSf6UI3ipChjOSn8wqmnbV6Lq 2kLvrcQIKpaS09vKjqH6PKbZR/G03D110zmdXsa01j2YkL9zHbc/CTHKKlWzFd72+7AD 3ggil9Elpw7Dmh/AzUC0QJumkPHo8gHi6rH8ne7SxXi6C1Vr7cMXn4cja3BYDQFN1k3F wBJOF9GrK/m5u/42k6zgtZbz6LGXEzCtHvDFSflzcO4PZh5/IFfrelicSbKRoDby2jfW QMeBi/FWAU6XGB55hIa6gggjDUdRuy1+Q5B5pzT3R60NYtFyXZ4zeGkMCT1hJGMQ3WtN 9Oig== X-Gm-Message-State: AOAM530Nx3jmVe7xFpPf7IRZC3Op/y61OlQ+AcxVGP48z5wCIcPS25Ke RRD46R52Zy1FOmnKpYjLYUhR5X5QQydTCw== X-Received: by 2002:a63:7447:: with SMTP id e7mr7408673pgn.261.1634271077653; Thu, 14 Oct 2021 21:11:17 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 27/67] target/i386: Implement x86_cpu_record_sigsegv Date: Thu, 14 Oct 2021 21:10:13 -0700 Message-Id: <20211015041053.2769193-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?P?= =?utf-8?q?hilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Record cr2, error_code, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. Use the maperr parameter to properly set PG_ERROR_P_MASK. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/i386/tcg/helper-tcg.h | 6 ++++++ target/i386/tcg/tcg-cpu.c | 3 ++- target/i386/tcg/user/excp_helper.c | 23 +++++++++++++++++------ 3 files changed, 25 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 60ca09e95e..0a4401e917 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -43,9 +43,15 @@ bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); #endif /* helper.c */ +#ifdef CONFIG_USER_ONLY +void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif void breakpoint_handler(CPUState *cs); diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 3ecfae34cb..6fdfdf9598 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -72,10 +72,11 @@ static const struct TCGCPUOps x86_tcg_ops = { .synchronize_from_tb = x86_cpu_synchronize_from_tb, .cpu_exec_enter = x86_cpu_exec_enter, .cpu_exec_exit = x86_cpu_exec_exit, - .tlb_fill = x86_cpu_tlb_fill, #ifdef CONFIG_USER_ONLY .fake_user_interrupt = x86_cpu_do_interrupt, + .record_sigsegv = x86_cpu_record_sigsegv, #else + .tlb_fill = x86_cpu_tlb_fill, .do_interrupt = x86_cpu_do_interrupt, .cpu_exec_interrupt = x86_cpu_exec_interrupt, .debug_excp_handler = breakpoint_handler, diff --git a/target/i386/tcg/user/excp_helper.c b/target/i386/tcg/user/excp_helper.c index a89b5228fd..cd507e2a1b 100644 --- a/target/i386/tcg/user/excp_helper.c +++ b/target/i386/tcg/user/excp_helper.c @@ -22,18 +22,29 @@ #include "exec/exec-all.h" #include "tcg/helper-tcg.h" -bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra) { X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; + /* + * The error_code that hw reports as part of the exception frame + * is copied to linux sigcontext.err. The exception_index is + * copied to linux sigcontext.trapno. Short of inventing a new + * place to store the trapno, we cannot let our caller raise the + * signal and set exception_index to EXCP_INTERRUPT. + */ env->cr[2] = addr; - env->error_code = (access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT; - env->error_code |= PG_ERROR_U_MASK; + env->error_code = ((access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT) + | (maperr ? 0 : PG_ERROR_P_MASK) + | PG_ERROR_U_MASK; cs->exception_index = EXCP0E_PAGE; + + /* Disable do_interrupt_user. */ env->exception_is_int = 0; env->exception_next_eip = -1; - cpu_loop_exit_restore(cs, retaddr); + + cpu_loop_exit_restore(cs, ra); } From patchwork Fri Oct 15 04:10:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515801 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp139766imi; Thu, 14 Oct 2021 21:25:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxEebFaRediQoajte2kzG/UWJmKyA+CJUWrK2fLIDobk3yf2MeYlGA8Fmz+RmP3DLFau32G X-Received: by 2002:a25:52d6:: with SMTP id g205mr10956377ybb.333.1634271951027; Thu, 14 Oct 2021 21:25:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271951; cv=none; d=google.com; s=arc-20160816; b=GpVh87b4Fbe3uZFxZpeSMcL05ksrUnrVnHorby2RUiRVWpqMATvuSONUdze0arSH75 LwpPb8b63IlgzkXenfw+0sa7z/O33/xlxJGHb6ugGPPRx5kS5GPOwAyE0umI/oHVuPm1 2AqtpsQBocj+AcWOM9doMFO/L6JiJXH3LvHY4gqjVfpxjPIgNBMbukwaKgGTu2BjrSpf 5wBJ7ErYkIQe7aQrUyYm/U08ABJmj81alIyPsAwmMxcANHWOd0sXDispTt0ixWph0j8/ 8yWw0IPvzvIM1irb8TPq1GkVpzF3i6CpU40MIFMIsLxqVnJ5KTnHiDJVJDKn3yMSHkfF M7mQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/utnMsLyouv7LilvnHYZPxrZ8zRoC/jZ7xS1qGJE894=; b=TaoY/bQYRxL3lVh5ph28KBD9QF7lJLCJCReUKOMjSSn1VHFJJenRC30fOx7vXhdoJ6 s6A4fXXuCjhUIZuBBXRnm2AZmyJjQy6Rm/YTdQw2OmKy8XTDU/tg3/C4RWnBan7bQ+CU b/ToDomnHdtDZZUfMnhvm0ECK/aYnbjUw3mPr4aeAXgylkIReH4gljAvZJVhX6TwBK2F u3jsPkqovSuS6DhZQxNVQBvIANlvsA2FGoH3/O+tGKM2ayJYDpP8QjZHSDKNXxNen7kH a2qby3GVZaXjK45Kmt/VKV3RHznlPk550kkFYWLl4gsOKpl8um4cwFtoKmksy9gsfYXn r1tw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HFNiH3O0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 84si5222152yba.370.2021.10.14.21.25.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:25:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HFNiH3O0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40184 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEn0-0003nY-7i for patch@linaro.org; Fri, 15 Oct 2021 00:25:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39114) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ8-0007Sc-8r for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:30 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:40808) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYy-0000Oh-At for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:26 -0400 Received: by mail-pg1-x52d.google.com with SMTP id q5so7431227pgr.7 for ; Thu, 14 Oct 2021 21:11:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/utnMsLyouv7LilvnHYZPxrZ8zRoC/jZ7xS1qGJE894=; b=HFNiH3O02qLQBBvg1obEw2pNCXQWPNxXjz71Cf5BbG5AvpYlzdMJe/sD+bvGM6Fx9l fiNqUI8Bi5APeNu7pdIuLltRnbVaM7jdeRRSw3Yc+vIfowM6ulpM8yFc8EZv4BeW84Af RGf2C3HifUpwLeoqYbhDM5uZ2jh60UfMiove169hA9WSVY4ZkhmMdGOkwoSuB5h+NjXT t3CjQISIpblujY6oYVDHjLe9PhC4D5UWacoyabohT/HhV29yminaocXYrSH55fV9IBxJ Ko5iCL8zF3L502A4DRqw2Ewfqi6J5+OD7Be1yi0t4na0zkftH/iNppyN/VRiBpOtSHjY AqQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/utnMsLyouv7LilvnHYZPxrZ8zRoC/jZ7xS1qGJE894=; b=tL7ENj2TLlebFz7jltO5JAKUJPK8bfcWQ8QNLcgutXpFoPYm+i/om6WH5j5YdsrDV+ h5SDsYXQ1MPbRCJEJO9RAQidLQggM2zMHaaOLvFr8NHgCC44s1YgqsKnrRZn8u0Yx0Al m0073njPhIiGYty4Xc4pRkKfa7FA43CzXeWPZslKIPveJ75r/I7aeVh4YHDXSGZdhhsn uuKhXeoiDFX+1DCXYlvcE+0J+hlARAO88plUSlpB08B7tkfCl4FhXCjO/YIejeCCckIj /0ixl+07sWwe4V5L8khlZ2FnKHkmhPs0mdABEJ5XHNkXsQiXnVgCMirIWEhUn9kPcA/6 otYQ== X-Gm-Message-State: AOAM530gzQfyhaDdvOvM6DfB/AlAr5fx+zMe3ErXcZvywoE1FKoe1Vgx gdr5PIFrJBsBqxkUHETLvHzpgmsoM2KTAw== X-Received: by 2002:a63:2a92:: with SMTP id q140mr7429761pgq.412.1634271078458; Thu, 14 Oct 2021 21:11:18 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 28/67] target/m68k: Make m68k_cpu_tlb_fill sysemu only Date: Thu, 14 Oct 2021 21:10:14 -0700 Message-Id: <20211015041053.2769193-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?P?= =?utf-8?q?hilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for m68k linux-user. Remove the code from cpu_loop that handled EXCP_ACCESS. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 10 ---------- target/m68k/cpu.c | 2 +- target/m68k/helper.c | 6 +----- 3 files changed, 2 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index ebf32be78f..790bd558c3 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -90,16 +90,6 @@ void cpu_loop(CPUM68KState *env) case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; - case EXCP_ACCESS: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->mmu.ar; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_DEBUG: info.si_signo = TARGET_SIGTRAP; info.si_errno = 0; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 66d22d1189..c7aeb7da9c 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -515,9 +515,9 @@ static const struct SysemuCPUOps m68k_sysemu_ops = { static const struct TCGCPUOps m68k_tcg_ops = { .initialize = m68k_tcg_init, - .tlb_fill = m68k_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = m68k_cpu_tlb_fill, .cpu_exec_interrupt = m68k_cpu_exec_interrupt, .do_interrupt = m68k_cpu_do_interrupt, .do_transaction_failed = m68k_cpu_transaction_failed, diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 137a3e1a3d..5728e48585 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -978,16 +978,12 @@ void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector) } } -#endif - bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType qemu_access_type, int mmu_idx, bool probe, uintptr_t retaddr) { M68kCPU *cpu = M68K_CPU(cs); CPUM68KState *env = &cpu->env; - -#ifndef CONFIG_USER_ONLY hwaddr physical; int prot; int access_type; @@ -1051,12 +1047,12 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (!(access_type & ACCESS_STORE)) { env->mmu.ssw |= M68K_RW_040; } -#endif cs->exception_index = EXCP_ACCESS; env->mmu.ar = address; cpu_loop_exit_restore(cs, retaddr); } +#endif /* !CONFIG_USER_ONLY */ uint32_t HELPER(bitrev)(uint32_t x) { From patchwork Fri Oct 15 04:10:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515815 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp144569imi; Thu, 14 Oct 2021 21:35:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwFmgBxngTBJ7PcN60MArXx3rfVslatoMMw3hbA9OiIyJEyG1YxLDwQwfdyVgeMo1n3QjnA X-Received: by 2002:a25:68c9:: with SMTP id d192mr10463288ybc.476.1634272505605; Thu, 14 Oct 2021 21:35:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272505; cv=none; d=google.com; s=arc-20160816; b=NM9Kz3UFd2wl162Pn1SLrrxfSCYimUTvLUsx+MqH7HsQ6vTjzPr9YUL27VSWo7l8X2 uk+ApBfEU79FSKoLZ8yOTvTZpdWadceRdIi1JyacG1OkRm4mh+lgzqBMoyqdVv7ONY5A YuKXC4SsIAZjJNPvJ3XRB01NiR2zDAezsrupas8SM1KFji1GmxKCBGumGzt6jspP3fuj OqlURCuivHMFYGpej4Xwut69BhH51y4UTsEQZ7Rp8X6e4LiO9hXLJd7J0vgZLBW5e5wR 8HAQ8I+JPKnw80sErD0AYK+/gkNSZXl0l686xHpufx1GWZm4MRS6uoxBo/Ipo5jpXuOL yxiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uBSoYrit32aNGLBOXaD1hzT0A4rXkiN+8LxdOJhc9ag=; b=zJALDusLOg+jqqyyYVOGL40z0fPjp4LxxdoYbc7g3cAHgf7IyY7Zp0zwxRI3iXzrPW rA/NgxRlTI4ZSwgpFWoGGHets89rsWKLi6qWj/3pcI+pGPU4vp84CqBYQDiDlu/QWXnk movDCtR6ybW3UIRom7XqosgewFC4uqqVGxy9avvNTOondsOXkJCQz5QamAzneQCPsfh3 BjQit2WD+suo69IOJCxH8GPfnDycZkZh6BTuYeyCRfTn6lcVrU++Fkeg4ANkYjjUrDau LzySP0wCmwbbq3/My+cX8BvB8JVIS7eQmp99QE623NBXT6KVyi0w6uvBSvvCnwLScM5C 34lQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hvWe4qLd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Remove the code from cpu_loop that handled the unnamed 0xaa exception. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 8 ++++---- linux-user/microblaze/cpu_loop.c | 10 ---------- target/microblaze/cpu.c | 2 +- target/microblaze/helper.c | 13 +------------ 4 files changed, 6 insertions(+), 27 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b7a848bbae..e9cd0b88de 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -394,10 +394,6 @@ void mb_tcg_init(void); #define MMU_USER_IDX 2 /* See NB_MMU_MODES further up the file. */ -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); - typedef CPUMBState CPUArchState; typedef MicroBlazeCPU ArchCPU; @@ -415,6 +411,10 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, } #if !defined(CONFIG_USER_ONLY) +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index 52222eb93f..a94467dd2d 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -37,16 +37,6 @@ void cpu_loop(CPUMBState *env) process_queued_cpu_work(cs); switch (trapnr) { - case 0xaa: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = 0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 15db277925..b9c888b87e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -365,9 +365,9 @@ static const struct SysemuCPUOps mb_sysemu_ops = { static const struct TCGCPUOps mb_tcg_ops = { .initialize = mb_tcg_init, .synchronize_from_tb = mb_cpu_synchronize_from_tb, - .tlb_fill = mb_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = mb_cpu_tlb_fill, .cpu_exec_interrupt = mb_cpu_exec_interrupt, .do_interrupt = mb_cpu_do_interrupt, .do_transaction_failed = mb_cpu_transaction_failed, diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index dd2aecd1d5..a607fe68e5 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -24,18 +24,7 @@ #include "qemu/host-utils.h" #include "exec/log.h" -#if defined(CONFIG_USER_ONLY) - -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - cs->exception_index = 0xaa; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - +#ifndef CONFIG_USER_ONLY static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu, MMUAccessType access_type) { From patchwork Fri Oct 15 04:10:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515803 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp140395imi; Thu, 14 Oct 2021 21:27:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw9psZQGutlUSt/mSaia8xx+gTS/G01GdNe1acwI46UpRbWMJwWddXyfWJ+f+8PB36m0sVt X-Received: by 2002:a25:d94d:: with SMTP id q74mr10008828ybg.196.1634272025860; Thu, 14 Oct 2021 21:27:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272025; cv=none; d=google.com; s=arc-20160816; b=fPGRDm0tu8r2/a0OGus4xiMGhxpMJCzr+GBRm/f3VvjatZ6WL5/hSfOMn9L1ytyA9o FTW2p/Bk40yiB1z/Era79We5eaMfxvcuuslf/nVc9CPxB/jt/I4R69zakiiL80fEJ398 RowRXoYWJYGZnN9dD3b5B5G+MqJC9AbnL+WOxzsabvLcFfOvP6fHEOEplx7nxOtYpSae wTcH3976Ntiynan8JYWPVXtFaRR5HSSXngHJaSGdgTzQmAHmfe9wo1n6zkcql3qgyH7W wDKygJ+yG5/RaAoWRh1hVjPQ3GcHICZMZQhKqSpgJsKqj5jGv0XXRe0qybPanx3/QPxF n8ew== ARC-Message-Signature: i=1; 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This means we can remove tcg/user/tlb_helper.c entirely. Remove the code from cpu_loop that raised SIGSEGV. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/tcg/tcg-internal.h | 7 ++-- linux-user/mips/cpu_loop.c | 11 ------ target/mips/cpu.c | 2 +- target/mips/tcg/user/tlb_helper.c | 59 ------------------------------- target/mips/tcg/meson.build | 3 -- target/mips/tcg/user/meson.build | 3 -- 6 files changed, 5 insertions(+), 80 deletions(-) delete mode 100644 target/mips/tcg/user/tlb_helper.c delete mode 100644 target/mips/tcg/user/meson.build -- 2.25.1 Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index bad3deb611..466768aec4 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -18,9 +18,6 @@ void mips_tcg_init(void); void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; @@ -60,6 +57,10 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, MemTxResult response, uintptr_t retaddr); void cpu_mips_tlb_flush(CPUMIPSState *env); +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + #endif /* !CONFIG_USER_ONLY */ #endif diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index cb03fb066b..b735c99a24 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -158,17 +158,6 @@ done_syscall: } env->active_tc.gpr[2] = ret; break; - case EXCP_TLBL: - case EXCP_TLBS: - case EXCP_AdEL: - case EXCP_AdES: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->CP0_BadVAddr; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_CpU: case EXCP_RI: info.si_signo = TARGET_SIGILL; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 00e0c55d0e..4aae23934b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -539,9 +539,9 @@ static const struct SysemuCPUOps mips_sysemu_ops = { static const struct TCGCPUOps mips_tcg_ops = { .initialize = mips_tcg_init, .synchronize_from_tb = mips_cpu_synchronize_from_tb, - .tlb_fill = mips_cpu_tlb_fill, #if !defined(CONFIG_USER_ONLY) + .tlb_fill = mips_cpu_tlb_fill, .cpu_exec_interrupt = mips_cpu_exec_interrupt, .do_interrupt = mips_cpu_do_interrupt, .do_transaction_failed = mips_cpu_do_transaction_failed, diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_helper.c deleted file mode 100644 index 210c6d529e..0000000000 --- a/target/mips/tcg/user/tlb_helper.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * MIPS TLB (Translation lookaside buffer) helpers. - * - * Copyright (c) 2004-2005 Jocelyn Mayer - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ -#include "qemu/osdep.h" - -#include "cpu.h" -#include "exec/exec-all.h" -#include "internal.h" - -static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type) -{ - CPUState *cs = env_cpu(env); - - env->error_code = 0; - if (access_type == MMU_INST_FETCH) { - env->error_code |= EXCP_INST_NOTAVAIL; - } - - /* Reference to kernel address from user mode or supervisor mode */ - /* Reference to supervisor address from user mode */ - if (access_type == MMU_DATA_STORE) { - cs->exception_index = EXCP_AdES; - } else { - cs->exception_index = EXCP_AdEL; - } - - /* Raise exception */ - if (!(env->hflags & MIPS_HFLAG_DM)) { - env->CP0_BadVAddr = address; - } -} - -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - - /* data access */ - raise_mmu_exception(env, address, access_type); - do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr); -} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 8f6f7508b6..98003779ae 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -28,9 +28,6 @@ mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'mxu_translate.c', )) -if have_user - subdir('user') -endif if have_system subdir('sysemu') endif diff --git a/target/mips/tcg/user/meson.build b/target/mips/tcg/user/meson.build deleted file mode 100644 index 79badcd321..0000000000 --- a/target/mips/tcg/user/meson.build +++ /dev/null @@ -1,3 +0,0 @@ -mips_user_ss.add(files( - 'tlb_helper.c', -)) From patchwork Fri Oct 15 04:10:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515799 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp138951imi; Thu, 14 Oct 2021 21:24:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwQSY5Jsk/3yCvjqgHkgbTRwzU5FjvOcwDkD4sbK2noisB5VB7HiQSFjZau9Va0O2I78G58 X-Received: by 2002:a5b:887:: with SMTP id e7mr10911763ybq.114.1634271886575; Thu, 14 Oct 2021 21:24:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634271886; cv=none; d=google.com; s=arc-20160816; b=f34dPWc/uybD5I+SDEjPXM/ztE1HaLtVNrMavk0Dmbe0UYr8zilArg7z5l3uZaQwRZ x0qQVjWLQ/KqSxWuNpQf+V1aLRfRLHC2e7U5rLCfD5dFrI4vIGtUXn9c69q7cjdtvM5m ptLrEW5dGyphMC1UhHcuFE3Ctp/k044beNgvftYts9HBDQSRRQYlcp5lZCPaJQbkDkh4 0pAhpINXvfbcRcH85m/lGr4fpE91ISAR03Q76vkI+x+182us8Q6C6rfvThDiU+eKaxeW y+eAlydRdGfFBKrJI/AHBwgqNuJt4waNw8wJq5YgXTIH4/caS4dr7Pd7D05p30uN3K4q CaGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uF38/TBQjdWDQM8FyXjqkWfqx61a2FgTbzu2sn+FnBE=; b=MdtoTPMFUQ0GfvjzFpH5LbO+dlV9Cu3vey4+L2L11QWKPvikwFXmpDRB0K4NDtgg9p cbKz+bhf341yMuHokXmyCEJRBa7eSMlIf6W5u2Nn0Y0IFnAHqi6R9vKrdxapjKWikiFA uuCWbtMgmvfyXiirNolwqCluHghjZV+8uiC4jFzNHe6YcigIfpA+NEntG13LDpArrV// JOqW2MUuTHTWBHL7LyqvVLvunR+tNcFXZPBnTwLYBmIuQCythqu9qOnavUJFzt+08dno XCUzh+2ivXIL+9bAmH/yCHCe1pEEze08Q0zPpNXYKbOHbNCQ65S1roOu0FEb1xmjEJOV ZeHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jF3RtzXz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f65si4810277ybi.95.2021.10.14.21.24.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:24:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jF3RtzXz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37126 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbElx-0001nn-U9 for patch@linaro.org; Fri, 15 Oct 2021 00:24:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39028) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ2-0007OK-Ph for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:26 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:38456) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ0-0000Pb-Bk for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:23 -0400 Received: by mail-pj1-x102a.google.com with SMTP id g13-20020a17090a3c8d00b00196286963b9so8450178pjc.3 for ; Thu, 14 Oct 2021 21:11:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uF38/TBQjdWDQM8FyXjqkWfqx61a2FgTbzu2sn+FnBE=; b=jF3RtzXzt5MZzqir004gfvqFOPQopXnZQNA1a5y917Sy5Vq/K35jRfw9abd1JuYe0g 3/ais4O6lVkzC+eGfHxRleTx9PBqlS6uhSctPcdkD1J3CftPCP6yBVdSD4vIgSpMxO7l CGm4NOOZdRu5qDg/mvmHCvlk80I4F4jaPDZ8hD3mUA6ZGx1FJbKRtARTLKh/aYXYChxZ VbKTEY0xszS//0ar/w4CLNM5ex24zd2ziiMaZ4ZCyMQSjKhJXq/g+Wkls6goxWTXQOsJ T0O1CqzygQuQZbW9XMayxJbGkv8PDdf4Z8xMXY3bAPSg7h4/Xa2K0dimsRCttvvH2Zp7 fQKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uF38/TBQjdWDQM8FyXjqkWfqx61a2FgTbzu2sn+FnBE=; b=N9OQskrcwkay3qWzoOzcS4bkrv/SB/lFw8XSW1Dsmb2AUoYvTR6SEpM3Ivg+IGgpBd Lrjhw7cFrGMzXnFLjMVDeqnxT6WB7WtmNEG5z9WntozJLnYnXZZ2iZ9PVBYR6AKgWmna oRHH2kQGr8039Y0oLERD01BiJVAKWdK9FI73gBpfmbFgEyjHkUcMI2VVMa+xsjEo6mum tvhICd+pLsfb9fzKWWoiezn8hb7HpX0s7Td71tMwzQNkabZ5eqozy0NVBJZIt+1Fl2L6 QxU5AQirnTmPf3gH0coeWnhsYBeJG8u/5b4dUKXaEHnUJT/qac/dCGS/blglNIXjlw8o PtBw== X-Gm-Message-State: AOAM531xmEc+SwWgWwi2GNPgkO3ljHElN1HcYcXiTq7fC2swQ6f/yuyB a2aApgZ7yok3z7jJq+4cd4QyWLMaAxu2og== X-Received: by 2002:a17:902:f54c:b0:13f:1e7:e467 with SMTP id h12-20020a170902f54c00b0013f01e7e467mr8958318plf.40.1634271080682; Thu, 14 Oct 2021 21:11:20 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 31/67] target/nios2: Implement nios2_cpu_record_sigsegv Date: Thu, 14 Oct 2021 21:10:17 -0700 Message-Id: <20211015041053.2769193-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?P?= =?utf-8?q?hilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because the linux-user kuser page handling is currently implemented by detecting magic addresses in the unnamed 0xaa trap, we cannot simply remove nios2_cpu_tlb_fill and rely on the fallback code. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 6 ++++++ target/nios2/cpu.c | 6 ++++-- target/nios2/helper.c | 7 ++++--- 3 files changed, 14 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index a80587338a..1a69ed7a49 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -218,9 +218,15 @@ static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) MMU_SUPERVISOR_IDX; } +#ifdef CONFIG_USER_ONLY +void nios2_cpu_record_sigsegv(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif static inline int cpu_interrupts_enabled(CPUNios2State *env) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 947bb09bc1..421cad114a 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -220,9 +220,11 @@ static const struct SysemuCPUOps nios2_sysemu_ops = { static const struct TCGCPUOps nios2_tcg_ops = { .initialize = nios2_tcg_init, - .tlb_fill = nios2_cpu_tlb_fill, -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv = nios2_cpu_record_sigsegv, +#else + .tlb_fill = nios2_cpu_tlb_fill, .cpu_exec_interrupt = nios2_cpu_exec_interrupt, .do_interrupt = nios2_cpu_do_interrupt, .do_unaligned_access = nios2_cpu_do_unaligned_access, diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 53be8398e9..e5c98650e1 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -38,10 +38,11 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[R_EA] = env->regs[R_PC] + 4; } -bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { + /* FIXME: Disentangle kuser page from linux-user sigsegv handling. */ cs->exception_index = 0xaa; cpu_loop_exit_restore(cs, retaddr); } From patchwork Fri Oct 15 04:10:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515817 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp144924imi; Thu, 14 Oct 2021 21:35:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwlMd1DHN8gYicO7I8Kc+hg6A6dHOaSU3Pp5arvT/QqPobOZvmZqlyd+dHqhj04nUYans80 X-Received: by 2002:a25:dac5:: with SMTP id n188mr10673614ybf.85.1634272545471; Thu, 14 Oct 2021 21:35:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272545; cv=none; d=google.com; s=arc-20160816; b=YRj/I6NzQo//FKKu6Ik9eTue7Mu4nMRSZDDX73cX/374vueB6gRngewyatDBaOIECb 1QFaBAxM1Nw6GI6Ll4gJXM96Q47tJvbGUanxu8vBA9r8IzDMawd54FuVzteXnIxeMxy1 TeUUwBoWeJAcY3NOfwvLes8r7MGpUDtvmYt8iffAUYqjuUxu+Hh4JJ66/EL6VSm7l25W D7ZaVs3j+U85lpcC6a+W3XmFpG6+9N48PW29acMoTWxKS3kgMxFC24NDhQq7UKGvSLbB 519TP1sQxG+LbPI6o2byMWJ6aqxzTSAmHyxd8v7mBwni/Uc97GVT5lak29/oFpp+EGTn HoVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jv32Frh7rweOdu9XSPHyzH/l4ZHzlE4pw5zka9V4K8I=; b=VVXoJvMKwAkX7NSHabVponojvu2bpX36jXZ/jhjfAxjBwq92SXmGJU+XTRVj6P/I9P NC9zlTCVKfBoZYny1d8TAU+vryEUhHL27nKkdsuIxQORYKvrUCNbXONDz24mvgSNuRp2 JhKdOW0XrV5FdNTiAh2KyuXuo0yFzIebRDRxa9xPE3ZdTBTXrHPWAjfnibupEly9l0Pp zpdwUG1aYdHUQAU7ATFLjMQqa1UytQGVANvs0u9PS55B4U2hVdM+Z5GNYTfb9cyv6qBh fMQ6gtKwQITNdiLCYQmoTKa1C2QT/V8CwKZ8v4dFHAOjP+AO08n7PgliK9jIa8LYOlCw rmNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="C0pn/RJf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n192si2982197ybf.436.2021.10.14.21.35.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:35:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="C0pn/RJf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45942 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEwa-0001Nq-Pb for patch@linaro.org; Fri, 15 Oct 2021 00:35:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39116) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ8-0007Sd-8x for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:30 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:44001) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ1-0000Pf-2r for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:26 -0400 Received: by mail-pl1-x62f.google.com with SMTP id y1so5586572plk.10 for ; Thu, 14 Oct 2021 21:11:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jv32Frh7rweOdu9XSPHyzH/l4ZHzlE4pw5zka9V4K8I=; b=C0pn/RJfXeJosErKpF0THofxdQkU9lnKZFfdZP0/LmJtrOTLRh2sja8+LvDAnxBE9E 7Q28onp9VrZBy0b0b5/0RuRGBEN0TlqBfawR+vX7twnStRdy9AdA0Yu91tlZdVa+o0LN q2RExSMrS2L9YnLzlR/4nNXBLMgw4Cy88VJ3Uqw96ZtpODPJRidRFEmHJoHUICLmf+f0 egXvyDWA21g+kyjL+FZY018SYymKDJLpN4nU88izN9feal5O2I3FiCRexUezox0gv9rt qg4DTQqMv9r8evGzhZdiZf9lLhh0w/4m3iSsCX/brdNj0uXNLxvPNG1gvHbNf9J8cJDH vTcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jv32Frh7rweOdu9XSPHyzH/l4ZHzlE4pw5zka9V4K8I=; b=nAvd7QMY/l1Ddx1RzrbS7WxkqZpVtsu2fz7IhE4binpnOs/U0T30FVKpRizfL6DH2t vHbWYTUFVRphLstSskz+6Mo9FxiJ2LCCulrVnVEDjrVztAYm/4unIM3KyZ7k70rQvOE3 vyz/4MYoOgUKD8aeJFYzEGk0u3YbsoyXNNn+jb6GfFp7E9hWACw5YB7yKoBw+Ciob40R bFJYhQl3B9ccv3N7NXfz2y5caqTtACijHucXrFB9+0DQkAP0JoqIEhs7/O27H2uKmtZ/ ewnjqsFDW21DPeooeWqsV2TC+OV0HK4X8dLo0LpUCKBEg4tWTD5GpjLjLmRA19Q/qb3x J0Qw== X-Gm-Message-State: AOAM533H6KwnjmMKq4h60xEt0IhHFjt0Y6CYkzk+ZUDjfznNAkvgW17w 9ISqz4ivg1/wUgUieiTPOG4PLx7Txz6Xig== X-Received: by 2002:a17:90b:34a:: with SMTP id fh10mr25171713pjb.51.1634271081301; Thu, 14 Oct 2021 21:11:21 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 32/67] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE Date: Thu, 14 Oct 2021 21:10:18 -0700 Message-Id: <20211015041053.2769193-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The kernel vectors both of these through unhandled_exception, which results in force_sig(SIGSEGV). This isn't very useful for userland when enabling overflow traps or fpu traps, but c'est la vie. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- linux-user/openrisc/cpu_loop.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index f6360db47c..de5417a262 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -56,13 +56,17 @@ void cpu_loop(CPUOpenRISCState *env) break; case EXCP_DPF: case EXCP_IPF: - case EXCP_RANGE: info.si_signo = TARGET_SIGSEGV; info.si_errno = 0; info.si_code = TARGET_SEGV_MAPERR; info._sifields._sigfault._addr = env->pc; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; + case EXCP_RANGE: + case EXCP_FPE: + /* ??? The kernel vectors both of these to unhandled_exception. */ + force_sig(TARGET_SIGSEGV); + break; case EXCP_ALIGN: info.si_signo = TARGET_SIGBUS; info.si_errno = 0; @@ -77,13 +81,6 @@ void cpu_loop(CPUOpenRISCState *env) info._sifields._sigfault._addr = env->pc; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case EXCP_FPE: - info.si_signo = TARGET_SIGFPE; - info.si_errno = 0; - info.si_code = 0; - info._sifields._sigfault._addr = env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_INTERRUPT: /* We processed the pending cpu work above. */ break; From patchwork Fri Oct 15 04:10:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515829 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp149185imi; Thu, 14 Oct 2021 21:44:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyipyWK97gdpQin03NAVd+RQ8tYlpOqjTCBxWzHrzb3UwOfOHs1UILjmjr1FyOZtVnsW101 X-Received: by 2002:a25:cb03:: with SMTP id b3mr10845184ybg.138.1634273043356; Thu, 14 Oct 2021 21:44:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634273043; cv=none; d=google.com; s=arc-20160816; b=vrIazu+XIjSNp44IswFd1vxeJE+LCmqDf6yuukowPp4GBL0Y6k92GwN3RvC+yaJ4M3 IIthrOnWVI6NU9MBnur+XhIsTa8pfHcdKSC1Oz8vsM1siSDxrTILNpz52YPN+QYRR+T0 Cm/tuxPvXifasZnIY6VCzqy0RNC7B5M4lbsuedT28Pqj8dQt/yVmoqIhosf6sL4y5eyQ MDtTH4bjnAH0btEKQ8zUuHxzmiGhorbKQJq5npWzDPmptKK2Mn92lgR1ySrCasoGNdPs 5wZxNPqA7rRDA5ylexJN80Ie9iI8pogFEy1yWgcmodVjyqpnKXZ7kwEoKhEX0Mk6Vmr6 k7hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=B4SaQQZmznpnKQ4FPXFeYarEGh4avP+2dHJ0pw3Dp+w=; b=T+LBfDs4Xwn9S2whN/gF3HeO28Qsp7Mp//OXLFDwyAfq8mfpdpqB9yoV9T6pNXkI0C kKGsZwZOSOk+1ECBeGxsgFeb8JjupUtAPBrznrTLia5oau9ojoq6ItXp22aJiK+IoFVg ejIb+VqIPvuPNfFDO+scvwJqmFTatB8ek96EAFn0EB/69mJaYYIElcM+u6w489zWBrcH ZEV3509yYZ5feZLaWnoQhZZ89RaA0gRlAo7jPT3TupPe4VXH8R6dwHLUQVyUQAgKjr+b 4eO1ZNAUq2nd7dwKjqVTq+mRjy+806Nme3lDhHjh6YWDSsH4LI7rWJ3/akBEQ02RZ7sI 8R3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=snB7U9BC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This makes all of the code in mmu.c sysemu only, so remove the ifdefs and move the file to openrisc_softmmu_ss. Remove the code from cpu_loop that handled EXCP_DPF. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 7 ++++--- linux-user/openrisc/cpu_loop.c | 8 -------- target/openrisc/cpu.c | 2 +- target/openrisc/mmu.c | 9 --------- target/openrisc/meson.build | 2 +- 5 files changed, 6 insertions(+), 22 deletions(-) -- 2.25.1 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 187a4a114e..ee069b080c 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -317,14 +317,15 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); -bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); int print_insn_or1k(bfd_vma addr, disassemble_info *info); #define cpu_list cpu_openrisc_list #ifndef CONFIG_USER_ONLY +bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + extern const VMStateDescription vmstate_openrisc_cpu; void openrisc_cpu_do_interrupt(CPUState *cpu); diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index de5417a262..fb37fb7651 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -54,14 +54,6 @@ void cpu_loop(CPUOpenRISCState *env) cpu_set_gpr(env, 11, ret); } break; - case EXCP_DPF: - case EXCP_IPF: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_RANGE: case EXCP_FPE: /* ??? The kernel vectors both of these to unhandled_exception. */ diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 27cb04152f..dfbafc5236 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -186,9 +186,9 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { static const struct TCGCPUOps openrisc_tcg_ops = { .initialize = openrisc_translate_init, - .tlb_fill = openrisc_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = openrisc_cpu_tlb_fill, .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, .do_interrupt = openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 94df8c7bef..e561ef245b 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -23,11 +23,8 @@ #include "exec/exec-all.h" #include "exec/gdbstub.h" #include "qemu/host-utils.h" -#ifndef CONFIG_USER_ONLY #include "hw/loader.h" -#endif -#ifndef CONFIG_USER_ONLY static inline void get_phys_nommu(hwaddr *phys_addr, int *prot, target_ulong address) { @@ -94,7 +91,6 @@ static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot, return need & PAGE_EXEC ? EXCP_ITLBMISS : EXCP_DTLBMISS; } } -#endif static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, int exception) @@ -112,8 +108,6 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, { OpenRISCCPU *cpu = OPENRISC_CPU(cs); int excp = EXCP_DPF; - -#ifndef CONFIG_USER_ONLY int prot; hwaddr phys_addr; @@ -138,13 +132,11 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, if (probe) { return false; } -#endif raise_mmu_exception(cpu, addr, excp); cpu_loop_exit_restore(cs, retaddr); } -#ifndef CONFIG_USER_ONLY hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { OpenRISCCPU *cpu = OPENRISC_CPU(cs); @@ -177,4 +169,3 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } } -#endif diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build index e445dec4a0..84322086ec 100644 --- a/target/openrisc/meson.build +++ b/target/openrisc/meson.build @@ -10,7 +10,6 @@ openrisc_ss.add(files( 'fpu_helper.c', 'gdbstub.c', 'interrupt_helper.c', - 'mmu.c', 'sys_helper.c', 'translate.c', )) @@ -19,6 +18,7 @@ openrisc_softmmu_ss = ss.source_set() openrisc_softmmu_ss.add(files( 'interrupt.c', 'machine.c', + 'mmu.c', )) target_arch += {'openrisc': openrisc_ss} From patchwork Fri Oct 15 04:10:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515821 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp146786imi; Thu, 14 Oct 2021 21:39:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwem+44h1iMd7fCVUZIOLOcAOHqDFckkucuOaL78KAx54Ye+7NjXJyNnDWl4yDDgxIbXXIQ X-Received: by 2002:a02:ca57:: with SMTP id i23mr6882910jal.101.1634272768489; Thu, 14 Oct 2021 21:39:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272768; cv=none; d=google.com; s=arc-20160816; b=pdfrefRmCLIcrilRjbBD1kqBfosAeYwLrXLl6A7M7s9GcmRFQoIW10AM8o7ubjPGas IT1OjscqOqMiHsp4XophqoZVlm/viZfQJCId8OhXOeuJzC8xu4/XOS4G686DQkaSx3qj lm8GpsBSEZRJ5/kWDNsjCDw6E/hay7ujvYbncK0MRU21UFdv8BHjwEYAe0RpKxwA49ts 9cHRS3MFthd65GVSPteIWO7drlQIRgUY+gfIHo4qxyAU/4amYdYqLwTrgIcr1B39pUnW sISFd6qshJY9w5GkOJtdPC54pRklgC0zdO+QDBYXMWOhSlN8z1cee/EIP8EYwfBVSCVh OUXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KnTU5CAKa2qgMNASytkbtJZqSTjvEtUQYaIow0w1ICM=; b=X3LyLcs2U92l58YhQPibbS4BxZoB/k7Wzjg6ymU+LkGDM23jx16cbazFt5qZqjoNRP s4Wmfa+lMVuFKcHApEMvzVWdoikIlimRGKtbmpeO+5w9lBvXwkTi5/ViEl4AQR6Yas+1 bVzkpu8JF9IBBGFd9x4JULVfhUHcdObe7NhjoiZ+Ymibwf51SHyLBiOZmy/T27xuR9KC vKAp1yuuqf4UloTbPrIJu/gsKzFTQnKkcRUzhY1m1c/QMrAusMhijHSFQ5hJilEzTSNL Hhi7nA3EOys1UubvQ2BtrNzR+rg8g11ipclvGeCWOjyaoguOQf9C4k+j98hcJV29Qonn CDRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a7eb1zlP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. This is exactly what the user-mode ppc_cpu_tlb_fill does, so simply rename it as ppc_cpu_record_sigsegv. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 3 --- target/ppc/internal.h | 9 +++++++++ target/ppc/cpu_init.c | 6 ++++-- target/ppc/user_only_helper.c | 15 +++++++++++---- 4 files changed, 24 insertions(+), 9 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index baa4e7c34d..2242d57718 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1279,9 +1279,6 @@ extern const VMStateDescription vmstate_ppc_cpu; /*****************************************************************************/ void ppc_translate_init(void); -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); #if !defined(CONFIG_USER_ONLY) void ppc_store_sdr1(CPUPPCState *env, target_ulong value); diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 55284369f5..339974b7d8 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -283,5 +283,14 @@ static inline void pte_invalidate(target_ulong *pte0) #define PTE_PTEM_MASK 0x7FFFFFBF #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) +#ifdef CONFIG_USER_ONLY +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#endif #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 6aad01d1d3..ec8da08f0b 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -9014,9 +9014,11 @@ static const struct SysemuCPUOps ppc_sysemu_ops = { static const struct TCGCPUOps ppc_tcg_ops = { .initialize = ppc_translate_init, - .tlb_fill = ppc_cpu_tlb_fill, -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv = ppc_cpu_record_sigsegv, +#else + .tlb_fill = ppc_cpu_tlb_fill, .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .do_interrupt = ppc_cpu_do_interrupt, .cpu_exec_enter = ppc_cpu_exec_enter, diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index aa3f867596..7ff76f7a06 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -21,16 +21,23 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "internal.h" - -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; int exception, error_code; + /* + * Both DSISR and the "trap number" (exception vector offset, + * looked up from exception_index) are present in the linux-user + * signal frame. + * FIXME: we don't actually populate the trap number properly. + * It would be easiest to fill in an env->trap value now. + */ if (access_type == MMU_INST_FETCH) { exception = POWERPC_EXCP_ISI; error_code = 0x40000000; From patchwork Fri Oct 15 04:10:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515805 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp140979imi; Thu, 14 Oct 2021 21:28:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxidn065etfadR4nxseU/aDuEyDzbDiSiAxoOchb4HXIBbQBPqohUtdkubK64xoa7NZ1LD9 X-Received: by 2002:a92:4453:: with SMTP id a19mr2359477ilm.233.1634272099288; Thu, 14 Oct 2021 21:28:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272099; cv=none; d=google.com; s=arc-20160816; b=WrU2+vmrmSCXuE7HzFyZCPmTgh5HhlYG9c0vOeeczsDv0LST40JmUMIBvxJltUAT46 7woYk1V+RiH2DWoq73Lf8MoE3S3GZFnk/g6VV5Ol6mQdLfMnQgPdhiVzUQ0TGA6MsGoQ t4IrrV2qlZPQ9s2RxRIAOSZ0Yx57nsMpnHDILLRnlZtUtTEOkJ4Qyn9wufynh8eGb7dY 9hz+X09lBfSzUs4F7+sGI0Z7ziKk1sYoHsFqfnlDLmZswR560oOhDquh83n2onFYrMla nnF4nq6C3uTVrCLEuEGD4hMF2XDXgww/6z2pxYc99vZq3ss1oxVEKoWxd1zXE8mW7Os+ BgTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8XNUdw8ZsBPFhbrTI2TXzCgV9ZFmSEvuHYyy7MRm+qg=; b=fplE6HcS0soDjyNbS4H8yVR/TNRglGsWbmcjRrmgVNDO2tp7bphiCQiaJ8Hgbyb/Zd z5X2TuR2Rppc26p8iJkEUX4MEgPmruzv0URbY8cvq9js5qxSi7WpfyGFC5JOIvmHbkCx QCZIqx4GDji6OtwxVfs1ZKfHY98J/35+dQnB86j3qEGwmaTOfvYNFAkIJz+ZymTvJL/h pwO7T9rLq2vIVsaZnTDkVCrCZkk9p6zSRDRu3BRrALsAc/11DbtRo/OKwsKNUTot01C6 /+4WivESESmg1gVvvdyBj0MXXjMEjvpJ4UL1cbzM5dByCw/rJKQ1WrWvRbwn8jL17+5W g+PA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eibrXC3p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n6si8202579ilk.28.2021.10.14.21.28.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:28:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eibrXC3p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48660 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEpO-00014Y-K6 for patch@linaro.org; Fri, 15 Oct 2021 00:28:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39122) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ8-0007Sh-F7 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:30 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:51030) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ4-0000QD-68 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:30 -0400 Received: by mail-pj1-x102b.google.com with SMTP id gn3so806949pjb.0 for ; Thu, 14 Oct 2021 21:11:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8XNUdw8ZsBPFhbrTI2TXzCgV9ZFmSEvuHYyy7MRm+qg=; b=eibrXC3pq7bwWEGw+/JDgf1MeNPENERuEkP9wb61HWujRIG89jHx4Xh0EOHquef3nW 20YPz2r+UMGFMrJQUYjZzQgaICuD20TQNGVT9lGDrIt4hdavEB1uzmT2pQe3qJ80VtXA 8xEDWopZSjxd3VQ4hXec01yubEZ4R24aGVFgyh4k9TIjHix0XqSnpusGw/jabSD3i5BP E0zwVrDQUbrfZ9dh92zPa2CL6OK2lSLSY7L1MoUKKS1WKMXdSAAYXLo6IzhoGmK2NtLi 6mjSokBWBiuGgW7rzyM3MC6dpGDvgKyoLtRjVTrbO4lXhNjOeRSK+BDh/oqRjXkGJ1tE InqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8XNUdw8ZsBPFhbrTI2TXzCgV9ZFmSEvuHYyy7MRm+qg=; b=aThp6ofk/bGB5tBevj7k0fcxvL6GWz61k5QAn5Jt8O0mFlt1Hhd/ZVyQZsUJXpsk/P CpPfbEQlG4p9uO5KcSJYO3Ntf5JYA044LCzUq978aQ3DL8YEpcpof5WyLFeX2xu9sGHp mMxfiRYEnYvR7rWELeIxpLqMJpUjdr4aAia3eMjE0kuiuMenSOBQaqW0U7FyIdWH+pRp 80Tx4Yg92pdBBbk8IA7KemjSGkakgnmAaH8WsYKSyrcfShMElcznNHeGjcAZzpljBQAO jHq1/VYXNOjibbWQSJQ30aEMRP3LgTSGXvSncnq/wXz8MkzomD+H7S+MBoG9E1y+97/L n12Q== X-Gm-Message-State: AOAM532JRWJNCNo1iybFpE3vztDirB7WKQ9Xf0fd4IkDz/B8QI57x1by C2SLFIIkL8UgitGSaTQLE+hzhWiigMfkCw== X-Received: by 2002:a17:90b:4a81:: with SMTP id lp1mr10840882pjb.124.1634271083385; Thu, 14 Oct 2021 21:11:23 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 35/67] target/riscv: Make riscv_cpu_tlb_fill sysemu only Date: Thu, 14 Oct 2021 21:10:21 -0700 Message-Id: <20211015041053.2769193-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for riscv linux-user. Remove the code from cpu_loop that raised SIGSEGV. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/riscv/cpu_loop.c | 7 ------- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 21 +-------------------- 3 files changed, 2 insertions(+), 28 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 9859a366e4..aef019b1c8 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -87,13 +87,6 @@ void cpu_loop(CPURISCVState *env) sigcode = TARGET_TRAP_BRKPT; sigaddr = env->pc; break; - case RISCV_EXCP_INST_PAGE_FAULT: - case RISCV_EXCP_LOAD_PAGE_FAULT: - case RISCV_EXCP_STORE_PAGE_FAULT: - signum = TARGET_SIGSEGV; - sigcode = TARGET_SEGV_MAPERR; - sigaddr = env->badaddr; - break; case RISCV_EXCP_SEMIHOST: env->gpr[xA0] = do_common_semihosting(cs); env->pc += 4; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1d69d1887e..2ab89a3f70 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -653,9 +653,9 @@ static const struct SysemuCPUOps riscv_sysemu_ops = { static const struct TCGCPUOps riscv_tcg_ops = { .initialize = riscv_translate_init, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, - .tlb_fill = riscv_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = riscv_cpu_tlb_fill, .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .do_interrupt = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d41d5cd27c..b520d6fc78 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -748,7 +748,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, riscv_cpu_two_stage_lookup(mmu_idx); riscv_raise_exception(env, cs->exception_index, retaddr); } -#endif /* !CONFIG_USER_ONLY */ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -756,7 +755,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; -#ifndef CONFIG_USER_ONLY vaddr im_address; hwaddr pa = 0; int prot, prot2, prot_pmp; @@ -888,25 +886,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } return true; - -#else - switch (access_type) { - case MMU_INST_FETCH: - cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; - break; - case MMU_DATA_LOAD: - cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; - break; - case MMU_DATA_STORE: - cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; - break; - default: - g_assert_not_reached(); - } - env->badaddr = address; - cpu_loop_exit_restore(cs, retaddr); -#endif } +#endif /* !CONFIG_USER_ONLY */ /* * Handle Traps From patchwork Fri Oct 15 04:10:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515825 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp148051imi; Thu, 14 Oct 2021 21:41:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxBmAC7BXj1O/YOnLqrMA7P980YIJlfLV/0t1wiwXEf1Ub+7sWDrcrG6yTOVIZU2LKI7iks X-Received: by 2002:a05:6638:1030:: with SMTP id n16mr6854808jan.36.1634272908615; Thu, 14 Oct 2021 21:41:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272908; cv=none; d=google.com; s=arc-20160816; b=Omm/7tlrfDhFUgQf1r0GASbcVdFgEUc9bXfqyRcxtEwEVodpe9FyjvKxo0X3DFxkZi ooc0cRfLgb9PEMsQ/iibw354oK59LOQmvvlXNBji4WExsou91gMOO1ZA0o0gG1sD+bIr jc4hFVfWJRXSqVfMyQDdq0jXSa98mZD3Tm0ufaDH7CKU4bR6iYBH+F2ko4OutcgCAisa 7xctbmFicbkkLJ+iRk5fHOH1yIGeRLWfxZNd0rIT9T/e3YnIXTb6ssqI56mG3wtbIXOh XDu/jZaqwuZY0xZcNikThI5BiRbL3h+jB9RFj9gyS7OH9c+51+aLDPnwnl0/6b8wkj6z Sihw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=66Bl8EQR5t0ae9YRNU1Dduo8SF5bSu1MJ1ucFe28OE8=; b=aupY+WcSvOT1z+FcaPHn/bq8QgM07t7lb4ocXPuPoK+i6sE3HAQtWHpPqKTSRHzIHA 4aAdQGnqOwnlCbh2cPlfsuVxx+Xd6ZkrrmUYdy2oU0NrsbSrJZjm2Z4txa4oRT8jD+FS EE+Q9zIgWbmwPUif8RzXhdeFgPqdgiXLwSPGspsqDcoPT/PV5BNEHpW2NmY9kF0Jr4gg IaS638Pe237BXmhloLhWJspRyIoxAYxSCXaeVB2/pj6IYm/q2jhQ/LNE4GJbvbvsixn5 Hsgi002/LXHfVC6QzQmthnkk/HVF8DHcroUtjttvoNave/IolwyD9bjj7Dfn1TNNT0S6 b4jA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Yrp9Qtc+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t11si8339758jal.58.2021.10.14.21.41.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:41:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Yrp9Qtc+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34574 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF2R-0004gc-TY for patch@linaro.org; Fri, 15 Oct 2021 00:41:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39130) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ9-0007UM-6t for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:32 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:44659) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ4-0000Rc-5j for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:30 -0400 Received: by mail-pl1-x62f.google.com with SMTP id t11so5587767plq.11 for ; Thu, 14 Oct 2021 21:11:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=66Bl8EQR5t0ae9YRNU1Dduo8SF5bSu1MJ1ucFe28OE8=; b=Yrp9Qtc+SjFsD0nJ4e7B6+81uBpyb+KaeXdnBzQteaCoRZfo9lcEwfZNfoGyaf/I8k t7UiqTt31bDPaI4JGT0qRMxvzWX/usiXdM3K4O/qHrJVA078cAoVFuSp4CFbpSQr4Dfi baXBVcZ4NLhLgZpIuyCQg9M8kALjO4JgPaSYO6uVO9e8hCRHcs41PXwyosBGqhKe9pYc LZRZdj7l+R4paJYDCKxkzAUATcCPhICrE1wb+WzjJEXzd6kQ+agLhIi1KGTSL8xplGyo nfcGVEyvNTr5Gs+3FMxjeMihDZYVM2s7hy/lQirMbNJ0wzbpiMSTVbbRkWje300ZRZ0m 6ljQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=66Bl8EQR5t0ae9YRNU1Dduo8SF5bSu1MJ1ucFe28OE8=; b=WkdQhNrJh6rQp8EXnHYhVBK86RV8nZwj8KOOOpWAkwnW8hw3Tth0r/zrceQ1b7kSAD wsUmsLZ/Ty4q3r9SYKM0Ioxb2FsQ4iPISSarjFxXOpeLfADVDEMy9i8jd2rGBzXPXBQU maRdH6Kz4NxOjwIxjVeHGaWmHjflMaC7heY7hK6v3HLHFOEIUIzDaJFMcq1Ze39HK+fV 2jUP1g93LxvbC8zl84bVSVO57XZqHMoK03UoFbLPWj5b4kGZQEuPmiPzbMG2HNRB29e1 svGAgGZbPbLGkPzhgMCHYUIh/ddD/8gqnj6x2D0fGfAnS7ER7WTRq6+0YUrOkxftmOt6 /CYw== X-Gm-Message-State: AOAM531BJ0cyT+ESbPCBLmB9omDX1UsQX2erJSHjpebpDhWHp2rciqBO dP9I45YuTIxkt9gech0GpaCfge5liyP3BA== X-Received: by 2002:a17:90b:4a48:: with SMTP id lb8mr11106849pjb.236.1634271084168; Thu, 14 Oct 2021 21:11:24 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 36/67] target/s390x: Use probe_access_flags in s390_probe_access Date: Thu, 14 Oct 2021 21:10:22 -0700 Message-Id: <20211015041053.2769193-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Not sure why the user-only code wasn't rewritten to use probe_access_flags at the same time that the sysemu code was converted. For the purpose of user-only, this is an exact replacement. Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 17e3f83641..362a30d99e 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -141,20 +141,12 @@ static int s390_probe_access(CPUArchState *env, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t ra) { +#if defined(CONFIG_USER_ONLY) + return probe_access_flags(env, addr, access_type, mmu_idx, + nonfault, phost, ra); +#else int flags; -#if defined(CONFIG_USER_ONLY) - flags = page_get_flags(addr); - if (!(flags & (access_type == MMU_DATA_LOAD ? PAGE_READ : PAGE_WRITE_ORG))) { - env->__excp_addr = addr; - flags = (flags & PAGE_VALID) ? PGM_PROTECTION : PGM_ADDRESSING; - if (nonfault) { - return flags; - } - tcg_s390_program_interrupt(env, flags, ra); - } - *phost = g2h(env_cpu(env), addr); -#else /* * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr==NULL * to detect if there was an exception during tlb_fill(). @@ -173,8 +165,8 @@ static int s390_probe_access(CPUArchState *env, target_ulong addr, int size, (access_type == MMU_DATA_STORE ? BP_MEM_WRITE : BP_MEM_READ), ra); } -#endif return 0; +#endif } static int access_prepare_nf(S390Access *access, CPUS390XState *env, From patchwork Fri Oct 15 04:10:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515809 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp142486imi; Thu, 14 Oct 2021 21:31:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy4Dd+mPkYZYVw8vNv/mNSyVpfb11XykxAk1zRbUgO9wWsMcynSnFvs9R21apC2JQvoNJaE X-Received: by 2002:a25:dc87:: with SMTP id y129mr11167467ybe.118.1634272281337; Thu, 14 Oct 2021 21:31:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272281; cv=none; d=google.com; s=arc-20160816; b=xClHacDW57kBbzuO16s3I1u+emGDcDSHHIr+b05JWTRoe5nl0TeufATy2UUm57N6Ol JAgkPTXx3knWrSFj047Izx0+e71tK/qPC6smB2Bp8DSUL5r5YLszRqezeupGkUr4PDf6 dgAd77b+AIcs2Dd4jWF50ANGY1jKawA/sGzafVwI6y4eN0p2zWiYqDaEsngXwMUYn/lL 0CaEEnl/5Br+NGPqgAvhmQD+FeUsyrA8KvL1kE6iTIT9sQp0SosYAhDj5Y3W0FXISgKr 2oPqsTbRnbgcBH61Phg6DnLFpWfBDCXXH9m+ayPPlmU/duUNg/hYG/jeKeEEK4LdPt9/ E43A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ij1YRgU0peRo+QSVg6ezzkIr6IGfKaWXUXRkApukMz0=; b=uRT6e+TOCaGpmsUDQ/9okT7HoQhXJRbxshZLUhj9zGn+BlAZg+a0/1zxP9kB8wzxJL UWrRqb2GrTFiOsRgbGdx6WcvGo6oPnq/rOoabddhkp/5ux/FeB9p/GssKtFCYrrOV6Mp 3Q7SzorzU209cc8zYfaKZ/AkmCCtIQyPbnES9K5/Y91tztbZKgpfJvuILpHU9Y76M/oI sn0sSvXbykpUlBybekUbrLAucgyFbRQm3utCa3K3sfo1k4YuJ2795fB9BWZ4QNtsfa2H A0IJYm8VvLvfn7UsGU6urpduy5nrMm+doq4yRCpZ/w9C+O1gLQ8HVHaE+3XNxVEcE4L4 3bVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zjgBXPzO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n70si5732131ybn.418.2021.10.14.21.31.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:31:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zjgBXPzO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57228 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEsK-0006jc-LW for patch@linaro.org; Fri, 15 Oct 2021 00:31:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39134) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ9-0007Uh-9l for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:32 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:56141) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ4-0000S8-7C for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:30 -0400 Received: by mail-pj1-x102e.google.com with SMTP id om14so6317168pjb.5 for ; Thu, 14 Oct 2021 21:11:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ij1YRgU0peRo+QSVg6ezzkIr6IGfKaWXUXRkApukMz0=; b=zjgBXPzOpbCputW+Yq8ae/JelNCmUvLWwkFCLopPHSAyz3iODARYwDN9DJabP4nYkv 2gSxGAWu3RPtqmoG1PmLQ8/eBVau5MA3dsHcKHn/fl3UGIbxD+FcwUdl1DmF2wF+iNKs D8DBU1h5lfMX3GDQRdegbPZaBqSuOQ07+tbjYGhknUtz7g+R16isYts2VZVjwz6bTBcs EXPDbt5zLbn3N/BrOFuMsNJBDXYDi2e+pEWvChOq5cxBeHAtsD+WoZmXgLoYrOpA6MbA k1vu/n9NR/6z+BWACOsTIkzs/jiQ/ziQzyzazKxDMfOlcwZNNV2GQNVUqDrQ1emkYjgR YDxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ij1YRgU0peRo+QSVg6ezzkIr6IGfKaWXUXRkApukMz0=; b=I9wxcm8V0JuZEDCx9N60A3pUIzlKP8UNjGSfCu/pkirgsGthI9XBp2IE1ar47/cJch 9vUsyKHYe6YGpgopfXFigUes/TNWJifA4hV6Xb22MjhQ6sak5RQTZTCGaE8vmaaSj5K5 hADHuJ2aGLwnoAyI6EuUDC7ouANB3XNXiJx4oFkbdr4DlhxSwsAk8clmva81+9OmELLY 91BMUG0TkVn8JSsgvn+/DLegJv2NbcqPcOp2feMkJBMM1/IxNZ2RMMWIluSxOrrdA2cm d29BFplT2ussAtTO5sisinJhuGZb6TFFEb3OsPPilLluwzdCvFkdPUCNcffM5yGbn90X zvgg== X-Gm-Message-State: AOAM531vt8tmLcHjJjvf4CDpoa++niVKqLZg6w/SKUm5L66ZbfW9pr5q ZtxSvadI/2RlIOaF7Y3SRtnWQTiQV3+6pg== X-Received: by 2002:a17:90a:4b47:: with SMTP id o7mr25830092pjl.198.1634271084999; Thu, 14 Oct 2021 21:11:24 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 37/67] target/s390x: Implement s390_cpu_record_sigsegv Date: Thu, 14 Oct 2021 21:10:23 -0700 Message-Id: <20211015041053.2769193-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?P?= =?utf-8?q?hilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the masking of the address from cpu_loop into s390_cpu_record_sigsegv -- this is governed by hw, not linux. This does mean we have to raise our own exception, rather than return to the fallback. Use maperr to choose between PGM_PROTECTION and PGM_ADDRESSING. Use the appropriate si_code for each in cpu_loop. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/s390x-internal.h | 13 ++++++++++--- linux-user/s390x/cpu_loop.c | 13 ++++++------- target/s390x/cpu.c | 6 ++++-- target/s390x/tcg/excp_helper.c | 18 +++++++++++------- 4 files changed, 31 insertions(+), 19 deletions(-) -- 2.25.1 diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 27d4a03ca1..163aa4f94a 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -270,13 +270,20 @@ ObjectClass *s390_cpu_class_by_name(const char *name); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; +#ifdef CONFIG_USER_ONLY +void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr); +#else +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#endif + /* fpu_helper.c */ uint32_t set_cc_nz_f32(float32 v); diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c index 69b69981f6..d089c8417e 100644 --- a/linux-user/s390x/cpu_loop.c +++ b/linux-user/s390x/cpu_loop.c @@ -24,8 +24,6 @@ #include "cpu_loop-common.h" #include "signal-common.h" -/* s390x masks the fault address it reports in si_addr for SIGSEGV and SIGBUS */ -#define S390X_FAIL_ADDR_MASK -4096LL static int get_pgm_data_si_code(int dxc_code) { @@ -111,12 +109,13 @@ void cpu_loop(CPUS390XState *env) n = TARGET_ILL_ILLOPC; goto do_signal_pc; case PGM_PROTECTION: + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_ACCERR, + env->__excp_addr); + break; case PGM_ADDRESSING: - sig = TARGET_SIGSEGV; - /* XXX: check env->error_code */ - n = TARGET_SEGV_MAPERR; - addr = env->__excp_addr & S390X_FAIL_ADDR_MASK; - goto do_signal; + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, + env->__excp_addr); + break; case PGM_EXECUTE: case PGM_SPECIFICATION: case PGM_SPECIAL_OP: diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7b7b05f1d3..593dda75c4 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -266,9 +266,11 @@ static void s390_cpu_reset_full(DeviceState *dev) static const struct TCGCPUOps s390_tcg_ops = { .initialize = s390x_translate_init, - .tlb_fill = s390_cpu_tlb_fill, -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv = s390_cpu_record_sigsegv, +#else + .tlb_fill = s390_cpu_tlb_fill, .cpu_exec_interrupt = s390_cpu_exec_interrupt, .do_interrupt = s390_cpu_do_interrupt, .debug_excp_handler = s390x_cpu_debug_excp_handler, diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 3d6662a53c..b923d080fc 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -89,16 +89,20 @@ void s390_cpu_do_interrupt(CPUState *cs) cs->exception_index = -1; } -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { S390CPU *cpu = S390_CPU(cs); - trigger_pgm_exception(&cpu->env, PGM_ADDRESSING); - /* On real machines this value is dropped into LowMem. Since this - is userland, simply put this someplace that cpu_loop can find it. */ - cpu->env.__excp_addr = address; + trigger_pgm_exception(&cpu->env, maperr ? PGM_ADDRESSING : PGM_PROTECTION); + /* + * On real machines this value is dropped into LowMem. Since this + * is userland, simply put this someplace that cpu_loop can find it. + * S390 only gives the page of the fault, not the exact address. + * C.f. the construction of TEC in mmu_translate(). + */ + cpu->env.__excp_addr = address & TARGET_PAGE_MASK; cpu_loop_exit_restore(cs, retaddr); } From patchwork Fri Oct 15 04:10:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515813 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp144028imi; Thu, 14 Oct 2021 21:33:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx+pBrTClE6R6rrqldLQCDJFX5hzlZmeR5EdnG8PhWqavvV6pHV7WtaImggDQqv2HG8rFI4 X-Received: by 2002:a25:ae10:: with SMTP id a16mr11514385ybj.36.1634272439164; Thu, 14 Oct 2021 21:33:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272439; cv=none; d=google.com; s=arc-20160816; b=qE1wj3QygZ/Tu8vJFIxxZxUAOvtajAX3Lap6sVdWUw/ukKqODz2HLu+t8JRNVylJXC Y1Rk0OejkrU+VL2q+ZeznD85/E0UAixJU1KqYef9jxW7GYqbXq+rYN9y/8uOTh7MukTz 11pNiDv6ZgKat70ofyQqFrjmcWJV6/VddbsXaC9ZywhToc/fhXOpBIJGLdOy220hSUl/ XveCjTe47y7eLU7u9BIZxX4bJhWT1Y09eeLzTmzHf3QOCmQNt4jkUizg+bN8yGdBaYfp q4U0Ntxx6nuJ3o9gAswwyQRSfdnOya/rb6Pt30Wkty2LV5oUQPPwTLixa2nqCgImM/lV UJYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8ZM/9TjmIZZ72copbPvsL/6T35TidGs+EyZyHS5h5dE=; b=vQoVlh285f964N8Oe77GX+U4PcXiKkfVoa6xOWar2QvU+ju8drM8/wgtph/2aUddjy Ffwc9Dx6BQfPhbwQbbv1sIXxxEU1kbOi/JV4MGccBa5ETLCEi04iK8wuHVfc7r+Nzghd 16R6AiGGbt3w4ZphcOVaWzjg5bPXRY2mfeDrDqbvNClLVXIHEP5x3JyLqVIO3rMFwUGF 1z5VsV+5t2XZXiXu56uBuOpkhoswFP92REqtlnQwqrftEJWQeqQPR3k1SolbC5xDyhnE QLAfKx/XUrxaqTKRuNPQKHJuOU/79TKX/IXepE4zv/NTQzgUpExuqXxPvGMrPPqbK08v wz5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="i184fE/Q"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l5si8376694ybt.351.2021.10.14.21.33.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:33:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="i184fE/Q"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37588 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEus-00049A-G4 for patch@linaro.org; Fri, 15 Oct 2021 00:33:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39144) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZA-0007V3-Qr for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:34 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:46709) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ5-0000Sk-0x for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:31 -0400 Received: by mail-pl1-x636.google.com with SMTP id 21so5576384plo.13 for ; Thu, 14 Oct 2021 21:11:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8ZM/9TjmIZZ72copbPvsL/6T35TidGs+EyZyHS5h5dE=; b=i184fE/Q5n892VsRHF0GLiaznZF6PLo9NrUWOp7yXwyqTGPXJzLKvJBaBXmj00nP7c 7BwCBmglrvz855LFjDO6RGLIZzyP3JCdI/G3hlu7/KvuHb6CAs1TtmmrNxv0NHk5Ga1y 2S4wFQ7m6o5/NkluEXdU8gfWD0x7MAXX5KKLOl4LOldf2IROyHDGHDNWWWRGLChg+OPi 5+RgDw+tEAO7anwwm5z+sYqVjn5T4my9cuDNzt+fUzXC6iFHLGKH5jfyvhMU0ioU9HqL nJhuU/AqkZukW2zmuiNrTZ8fD18ACJdW8oDJqPA0mcQVJtMRnReReerS/ptuMNekshDl hJsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8ZM/9TjmIZZ72copbPvsL/6T35TidGs+EyZyHS5h5dE=; b=KXQ+d7LqIUYXnmXBToSdtSraBFsQieS3Ey9poEWf+LNsfgbIXI5gptrQymF4LPzz6u kUAsteMGAE6PhdrA6RDpOO55g3qA1JHC/9hvDJy0p9dqc8GJCfVZUlY2IFtY1Wwri5t3 D3grGhG8GqlGXykhguKtzDzgaTMZz2ig2GCWO1YhpKta0VJoju8inBk2hnEZ8JHX7glJ jXKXaeUL1ySh1WGf9flpbquC/sbDstJhkfnltdHyIQ5a2JB6EXr+cRsb5RKuvOb/4VxE X4ZL+F9boYTTJ1RaY8aILispViB+V2+dzoumSljddOyJ/+al38BZzXRsJneudVgY+B44 wpTQ== X-Gm-Message-State: AOAM532ir48GquBUUbq79B+0D6OBm0sAjLDqds6/n+y45FdqtuoXCyAF fBiv6koafYuz4lMTEr+acx20TnLI0S9MGw== X-Received: by 2002:a17:90b:4f88:: with SMTP id qe8mr10791972pjb.223.1634271085623; Thu, 14 Oct 2021 21:11:25 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 38/67] target/sh4: Make sh4_cpu_tlb_fill sysemu only Date: Thu, 14 Oct 2021 21:10:24 -0700 Message-Id: <20211015041053.2769193-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for sh4 linux-user. Remove the code from cpu_loop that raised SIGSEGV. Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 6 +++--- linux-user/sh4/cpu_loop.c | 8 -------- target/sh4/cpu.c | 2 +- target/sh4/helper.c | 9 +-------- 4 files changed, 5 insertions(+), 20 deletions(-) -- 2.25.1 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index dc81406646..4cfb109f56 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -213,12 +213,12 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, uintptr_t retaddr) QEMU_NORETURN; void sh4_translate_init(void); +void sh4_cpu_list(void); + +#if !defined(CONFIG_USER_ONLY) bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); - -void sh4_cpu_list(void); -#if !defined(CONFIG_USER_ONLY) void superh_cpu_do_interrupt(CPUState *cpu); bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); void cpu_sh4_invalidate_tlb(CPUSH4State *s); diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c index 65b8972e3c..ac9b01840c 100644 --- a/linux-user/sh4/cpu_loop.c +++ b/linux-user/sh4/cpu_loop.c @@ -65,14 +65,6 @@ void cpu_loop(CPUSH4State *env) info.si_code = TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case 0xa0: - case 0xc0: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->tea; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); arch_interrupt = false; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 2047742d03..06b2691dc4 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -236,9 +236,9 @@ static const struct SysemuCPUOps sh4_sysemu_ops = { static const struct TCGCPUOps superh_tcg_ops = { .initialize = sh4_translate_init, .synchronize_from_tb = superh_cpu_synchronize_from_tb, - .tlb_fill = superh_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = superh_cpu_tlb_fill, .cpu_exec_interrupt = superh_cpu_exec_interrupt, .do_interrupt = superh_cpu_do_interrupt, .do_unaligned_access = superh_cpu_do_unaligned_access, diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 53cb9c3b63..6a620e36fc 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -796,8 +796,6 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } -#endif /* !CONFIG_USER_ONLY */ - bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -806,11 +804,6 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, CPUSH4State *env = &cpu->env; int ret; -#ifdef CONFIG_USER_ONLY - ret = (access_type == MMU_DATA_STORE ? MMU_DTLB_VIOLATION_WRITE : - access_type == MMU_INST_FETCH ? MMU_ITLB_VIOLATION : - MMU_DTLB_VIOLATION_READ); -#else target_ulong physical; int prot; @@ -829,7 +822,6 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) { env->pteh = (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_MASK); } -#endif env->tea = address; switch (ret) { @@ -868,3 +860,4 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } cpu_loop_exit_restore(cs, retaddr); } +#endif /* !CONFIG_USER_ONLY */ From patchwork Fri Oct 15 04:10:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515808 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp141754imi; Thu, 14 Oct 2021 21:29:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzZHD5p5e/vFdjsRB4NMwfZ5Em5OpsBSjXdyEp5KUB5WSQZLOBeO2x9SJzmm/ZtwjJNbjxJ X-Received: by 2002:a25:69c7:: with SMTP id e190mr9887271ybc.334.1634272193956; Thu, 14 Oct 2021 21:29:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272193; cv=none; d=google.com; s=arc-20160816; b=LbFjNLJ4DkeCw9ro8Ja13DD/Jz0ervhlhzupWSX/mFRy40K3c3HNuiAf8sSDvbpYXI Lu2ZFQUqoCfSdpw5zIT2zT/vQk5z66UCDDGkTr5qFgvAaSRKfD5/Joof10aEvqTkjEcp Ktl/v4THZrSx7XzcKJbjmsiEPCQrvFQeU+IJYvtSkIx8V/0flij6X3hHYl2kUHKso9GY YPYc7GCI2Yr3BBn8wdTdhv1N9gynAxOxV1XVq7cr9yeU80T9FsD4kj+eTgMx4FZltsZ2 fNgohAqw7/qVj9TOA0JpHxRO1h3I/ChhdfXo3oXFzaDv56KiJI6pjwSC707EjpDA2y6A BoJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OFBASZgYo/dnEXgBhwjQsgVMikt4qFVfoC5aZFh8E0o=; b=zfYbPloYsDrZENDV2GcOims9SPpSeaqpqt2Vm+qhMbWwqy0gWQsUSfBvpbVhM+6EaA hMXCb0hdk697lPsBac4/KdRbwMhcR4iZ27cMMzkbpKkmg4n/uuTZ4VEP/sEcjL4XMYKK DwVTaEawqIDqCwA7biXh0dFLTATf74neH8tO6qwdfpZ/w1ghgKboJxfcHGQ8mTqtQWOR 8ELdXJUOFGaASd8FwHMioNXqG7/vf96yiepl2lKSuDa28loXxTv6dw3YMHLxbHN0LXFF vEcZ/wrvrQ6gNfgHL6oeZwiIE5Kn7YFqcNXpGA4pRzs+P1vGHqQOCvAizl5eG8z/eRnV WNTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="H1tX4L/B"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c1si4931260ybk.442.2021.10.14.21.29.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:29:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="H1tX4L/B"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54074 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEqv-0004fX-51 for patch@linaro.org; Fri, 15 Oct 2021 00:29:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39148) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZB-0007V6-Lf for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:34 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:55088) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEZ8-0000Sz-1k for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:33 -0400 Received: by mail-pj1-x1036.google.com with SMTP id np13so6324867pjb.4 for ; Thu, 14 Oct 2021 21:11:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OFBASZgYo/dnEXgBhwjQsgVMikt4qFVfoC5aZFh8E0o=; b=H1tX4L/B1JPBqT8wf8L9696kVk9MMnG2KbM9vqiQBci/F3M+06X6kRSzkY4BRLfxVG /EZY360+UCQzWVWbOopkEGXVs5QErETUM5LMvqP0dY6LmQ/l5NWBtaeS2zDkR9QMUtn/ MrZVXFYPoy8yBCefAhVrlxeDLx34ThLsBLzG0ZvL2aJXg5jauI/wfQxlvZctQuP4k1IK uSbELWIUZGRQac5nhwzu0PvRZIitFqKf+jaLzNVkCZLE80MJVmc7UZWwXHLqQHDj6fa5 Ai3ahgN2xJI3L0GIQUzEifKysAawjEapgZFtCH9uRJd7zMZOI+vwT75/JNfcFnxufCXL 7dVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OFBASZgYo/dnEXgBhwjQsgVMikt4qFVfoC5aZFh8E0o=; b=hAAuoIrgfGi3xXj1lUDjrszuhnr6+/inY6GadUhQ/nMa5PrqBeO3k7DXnA/JDZjklR 44IQAmIdGSuEAv8AXR7SteRpbpcP9ptIoAgsyz4fsR4DGq9UfJZtQx/2oY0YCccDz/fr trAJf8tOczwX5yojQ9XxrbQ94TtpTKvp7Y2TgkE9+V5L2cQxkTrUm5xxMYRWNYankyO/ 1+rEUi2KUiJ7bICfHUZmR6ixmp7NgXDEJrui2+d4rTI9Ok/TUXOg9dwkCEPLHMGbZG5c X6hPW3D6Uu2EhZkVAhXDMF34aoS6rB+m99OrWVh6GuVKVrVb+UoTG3Ijzl4/5JeM3BIl GLIg== X-Gm-Message-State: AOAM5324XVJGgMqmW3T12d596m5veSgUWsU5dqPGCn/iHmzJr44DdMJp 0U3cfQPvVfno+ul2+fXo3MWWz2m2QGJFWw== X-Received: by 2002:a17:90a:4502:: with SMTP id u2mr25090671pjg.186.1634271086500; Thu, 14 Oct 2021 21:11:26 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 39/67] target/sparc: Make sparc_cpu_tlb_fill sysemu only Date: Thu, 14 Oct 2021 21:10:25 -0700 Message-Id: <20211015041053.2769193-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for sparc linux-user. This makes all of the code in mmu_helper.c sysemu only, so remove the ifdefs and move the file to sparc_softmmu_ss. Remove the code from cpu_loop that handled TT_DFAULT and TT_TFAULT. Cc: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/sparc/cpu_loop.c | 25 ------------------------- target/sparc/cpu.c | 2 +- target/sparc/mmu_helper.c | 25 ------------------------- target/sparc/meson.build | 2 +- 4 files changed, 2 insertions(+), 52 deletions(-) -- 2.25.1 diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index ad29b4eb6a..0ba65e431c 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -219,17 +219,6 @@ void cpu_loop (CPUSPARCState *env) case TT_WIN_UNF: /* window underflow */ restore_window(env); break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->mmuregs[4]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; #else case TT_SPILL: /* window overflow */ save_window(env); @@ -237,20 +226,6 @@ void cpu_loop (CPUSPARCState *env) case TT_FILL: /* window underflow */ restore_window(env); break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - if (trapnr == TT_DFAULT) - info._sifields._sigfault._addr = env->dmmu.mmuregs[4]; - else - info._sifields._sigfault._addr = cpu_tsptr(env)->tpc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; #ifndef TARGET_ABI32 case 0x16e: flush_windows(env); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 21dd27796d..55268ed2a1 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -865,9 +865,9 @@ static const struct SysemuCPUOps sparc_sysemu_ops = { static const struct TCGCPUOps sparc_tcg_ops = { .initialize = sparc_tcg_init, .synchronize_from_tb = sparc_cpu_synchronize_from_tb, - .tlb_fill = sparc_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = sparc_cpu_tlb_fill, .cpu_exec_interrupt = sparc_cpu_exec_interrupt, .do_interrupt = sparc_cpu_do_interrupt, .do_transaction_failed = sparc_cpu_do_transaction_failed, diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index a44473a1c7..2ad47391d0 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -25,30 +25,6 @@ /* Sparc MMU emulation */ -#if defined(CONFIG_USER_ONLY) - -bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - - if (access_type == MMU_INST_FETCH) { - cs->exception_index = TT_TFAULT; - } else { - cs->exception_index = TT_DFAULT; -#ifdef TARGET_SPARC64 - env->dmmu.mmuregs[4] = address; -#else - env->mmuregs[4] = address; -#endif - } - cpu_loop_exit_restore(cs, retaddr); -} - -#else - #ifndef TARGET_SPARC64 /* * Sparc V8 Reference MMU (SRMMU) @@ -926,4 +902,3 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } return phys_addr; } -#endif diff --git a/target/sparc/meson.build b/target/sparc/meson.build index a3638b9503..a801802ee2 100644 --- a/target/sparc/meson.build +++ b/target/sparc/meson.build @@ -6,7 +6,6 @@ sparc_ss.add(files( 'gdbstub.c', 'helper.c', 'ldst_helper.c', - 'mmu_helper.c', 'translate.c', 'win_helper.c', )) @@ -16,6 +15,7 @@ sparc_ss.add(when: 'TARGET_SPARC64', if_true: files('int64_helper.c', 'vis_helpe sparc_softmmu_ss = ss.source_set() sparc_softmmu_ss.add(files( 'machine.c', + 'mmu_helper.c', 'monitor.c', )) From patchwork Fri Oct 15 04:10:26 2021 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id i21si5812898jaj.84.2021.10.14.21.32.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:32:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="Z7n/Hqex"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34374 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEti-00021k-Aq for patch@linaro.org; Fri, 15 Oct 2021 00:32:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39402) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc3-0006PB-0J for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:31 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:33779) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc1-0002kB-Ci for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:30 -0400 Received: by mail-pl1-x62e.google.com with SMTP id y4so5640967plb.0 for ; Thu, 14 Oct 2021 21:14:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kAcqfrBKLTctf7S2SRnWlKvQ84+gE9eIlExzwRxWIv4=; b=Z7n/HqexPf03mPIK5CBZaZhWMlm5GOptriO4bhptblllp3qr4tbFRThMMYhtVqHxrf oD+b1dolGgDJp4SKiJcFgh5OrAd9Kj77xpsY8E6yNUlI/wg4n3gDZn7qqH6iN73yxvUk qJNgVZ0a+RkH1hKEF2OyPrSxd2hxzZeqUgEeuZZ72PvRfCumlqU8wDlR6VWctpuVJUef W8j3qaGnwp+310jhG/diF/y3a5aLDZqbQkWv0WvWMco9N+JjQmdgU/ZYTUyGm3PuBblP N7+F6znwenHxaHzqTGV5h1ZVmJQKmaXIkJSsqXEQ/wZGFuXFondzbDbwVLhBcNOyfx9J nCqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kAcqfrBKLTctf7S2SRnWlKvQ84+gE9eIlExzwRxWIv4=; b=sSEykkskwIWmrB+1ikDEGZJni+tP+E88pyeUpjMLvp2h0pVoVJnyxQqDLDJJks+b7w CChnn0GB/q6huter19HCGFcuEnLVfDW9DmdMPkxTkYPk1YjVF5lBjS9OLSijuONyKVSS E8gEkkTI7cG7rPJdaqsy084xWlSyyuIx6ogCXY1Ds5/F5QMJazdNRrGlohF1Bc2oJwiD uoF5DjT0bnjXh9lG4W4g5z+dWWe4vuszAM7s+Rysudv7KOFfX8pCZt6khBkbOQl/mzqy LtJY4fnRAzCk6Y36kCj9sZhyLKXgwT1Aik+B2Zmj3rerjg2KsIiTYKwcPzvTruNpsnp7 31dw== X-Gm-Message-State: AOAM532YssS2uxlsojCFXkcLKBuxP6UzbKg1zFEqmyArYSkqc33HYcyL KHN8Y4vcUo174wnyVIqlg6+34mdBWSyRMg== X-Received: by 2002:a17:90a:428e:: with SMTP id p14mr25294389pjg.92.1634271267726; Thu, 14 Oct 2021 21:14:27 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 40/67] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only Date: Thu, 14 Oct 2021 21:10:26 -0700 Message-Id: <20211015041053.2769193-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for xtensa linux-user. Remove the code from cpu_loop that raised SIGSEGV. Acked-by: Max Filippov Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 2 +- linux-user/xtensa/cpu_loop.c | 9 --------- target/xtensa/cpu.c | 2 +- target/xtensa/helper.c | 22 +--------------------- 4 files changed, 3 insertions(+), 32 deletions(-) -- 2.25.1 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index f9a510ca46..02143f2f77 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -563,10 +563,10 @@ struct XtensaCPU { }; +#ifndef CONFIG_USER_ONLY bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c index 622afbcd34..a83490ab35 100644 --- a/linux-user/xtensa/cpu_loop.c +++ b/linux-user/xtensa/cpu_loop.c @@ -226,15 +226,6 @@ void cpu_loop(CPUXtensaState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case LOAD_PROHIBITED_CAUSE: - case STORE_PROHIBITED_CAUSE: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr = env->sregs[EXCVADDR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - default: fprintf(stderr, "exccause = %d\n", env->sregs[EXCCAUSE]); g_assert_not_reached(); diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c1cbd03595..224f723236 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -192,10 +192,10 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = { static const struct TCGCPUOps xtensa_tcg_ops = { .initialize = xtensa_translate_init, - .tlb_fill = xtensa_cpu_tlb_fill, .debug_excp_handler = xtensa_breakpoint_handler, #ifndef CONFIG_USER_ONLY + .tlb_fill = xtensa_cpu_tlb_fill, .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, .do_interrupt = xtensa_cpu_do_interrupt, .do_transaction_failed = xtensa_cpu_do_transaction_failed, diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f18ab383fd..29d216ec1b 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -242,27 +242,7 @@ void xtensa_cpu_list(void) } } -#ifdef CONFIG_USER_ONLY - -bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; - - qemu_log_mask(CPU_LOG_INT, - "%s: rw = %d, address = 0x%08" VADDR_PRIx ", size = %d\n", - __func__, access_type, address, size); - env->sregs[EXCVADDR] = address; - env->sregs[EXCCAUSE] = (access_type == MMU_DATA_STORE ? - STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE); - cs->exception_index = EXC_USER; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - +#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) From patchwork Fri Oct 15 04:10:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515816 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp144570imi; Thu, 14 Oct 2021 21:35:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxwwWBfngC2w7SXUCfZV7uxz4FTW0Sr1pnydFgWtzfhMIZf8CrNGyqQAZZVwBs0abUON4N/ X-Received: by 2002:a25:d9c3:: with SMTP id q186mr11681121ybg.71.1634272505631; Thu, 14 Oct 2021 21:35:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272505; cv=none; d=google.com; s=arc-20160816; b=FQg1F/N6OLxAVwDkgUmSr7ZVoUHcDGTyjyPeuFEXDArFS/V0zKv8lo4HdAEdVbhhtn 6lrjBCwlA2UNehmAdjqelBAKP6SlEOAXK10mkSdYq1TmtY75XmB/GKc1xTfM+8EjJmEw 9m/HKj+WHa0Bp/V1V592UBENruEb2j3Fr3l0R+0196DoaSKumGJje3m9EB9hDSPMKwGV 5NTBYLYcstQyuRIXZUgze80WN4xSlD6ApvBPlmIfI8KHf/NFQ/6Fz/+sNcTkhFNE+rqS 5hDfJ+HYwL5Klc6UVA3KNkpdAKgw6Go9xG8NomMJtAPh1Hoh/IZxuQk2DPInMfCcEwEU ZBVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AlAKO3pHLk0w42dzpdqlCWgmBC5kkngUdLfuQLXO9ho=; b=z2XdzJZKZGTO89/EYyppP5UdEysE7zNLmDMj58vtymDdSFhgtaKXLY91t0dfk4+FO5 NSQQVbhkpBLuaVyjwl96u9GYCTBMW2yZGWTuzYWIfMf2Q6KeAXiayCPeKhYn/QER0peu 6BUsrMXl+YfvjIl5zQQl7+R76xzTXv/CzhxVd05q6y+wFP4azcHmNsm1famIJCQkfTIZ QtZyt69MQQjG/n+7x4A6k9HwfiLBEAk/dah9vYmtEIELwMtHWXG2MmF5t/1NhHGpf8bW 7K+s/rqJkfIgDBjbY7xVfoUKf63jhtIIaMi+CVnuoPDiLhEB9TAQ0ewsmmRKOHTrvEgW CP+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="gxL/J4fg"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w13si7225818ybt.170.2021.10.14.21.35.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:35:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="gxL/J4fg"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42710 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEvx-0007dy-01 for patch@linaro.org; Fri, 15 Oct 2021 00:35:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39414) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc3-0006Rc-P6 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:31 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:44015) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc2-0002l4-1E for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:31 -0400 Received: by mail-pl1-x633.google.com with SMTP id y1so5590513plk.10 for ; Thu, 14 Oct 2021 21:14:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AlAKO3pHLk0w42dzpdqlCWgmBC5kkngUdLfuQLXO9ho=; b=gxL/J4fg2UqVuhFY6kvo4FD2c3UJHB2s+ejjFT81o8CcYpDVxep5lRnhe2MIRfXK/q mwQsVwq+gKm+K5gjGZv6kylWShC9TRbDrCtLqKKWZA0CG7EZTfC+Muz3rOnw+aCPrszS 6M1J0hILeIkwBTbxfWWodD52rUvKYUqf3ein5e/ndFnG5wSx+bLzrAuGsNeWq3mVBUyX LC2yidsOofv9vUgiOjKGHFTjpXU80v5ceo1RcDHZGOnEF/kpBtzTrMs3frO9fNlgSWco /tsJRWtCZfm49G8kqaTqiPT5RaBlHDxiCDmoQtaJXnvg25AFKKfqF1EUtOKFQH70wkJR SKPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AlAKO3pHLk0w42dzpdqlCWgmBC5kkngUdLfuQLXO9ho=; b=AJW9pqncHV37JwufH1I//GndVW2W+qq3F1fbU1yWpLdAQalVXw4FDLOl6rMz4yTpvN nxYohLKoiQWwUlnJCeWV6SajGBsIKaDbGYaaSvKXl+H0idwJhqDMGG7ZdriDMplArlqA FgJGyWuglSFbNtkBJi6+RtEs04u9T1yfacHvMM8nn+8X9JZtO9dekbfmOYAK5kEhQyNL eiCMoktPRkOXfSc9cmvKvDwtphbDdnY6+wvLUMGeWvDrfxIEltDM7lXhtXNXYlfSGey4 8Ef+Mhvysudy+eeg0hO/CZJ/z0tkyx4+GgD/n0ZjesUqm0VkBhvt5CZITz9eFiBHx/h/ M1JA== X-Gm-Message-State: AOAM533Ttdbhy72u46hxtic5+DDycIM0fRYJp9oPwGDjE8d5Pexn1PEu juQniGIC7ZCj7EjCX4wqUayLwJDLdY38nQ== X-Received: by 2002:a17:90a:8593:: with SMTP id m19mr10608225pjn.82.1634271268518; Thu, 14 Oct 2021 21:14:28 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 41/67] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Date: Thu, 14 Oct 2021 21:10:27 -0700 Message-Id: <20211015041053.2769193-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?P?= =?utf-8?q?hilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have replaced tlb_fill with record_sigsegv for user mode. Move the declaration to restrict it to system emulation. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 22 ++++++++++------------ linux-user/signal.c | 3 --- 2 files changed, 10 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 41718b695b..8eadd404c8 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -35,18 +35,6 @@ struct TCGCPUOps { void (*cpu_exec_enter)(CPUState *cpu); /** @cpu_exec_exit: Callback for cpu_exec cleanup */ void (*cpu_exec_exit)(CPUState *cpu); - /** - * @tlb_fill: Handle a softmmu tlb miss or user-only address fault - * - * For system mode, if the access is valid, call tlb_set_page - * and return true; if the access is invalid, and probe is - * true, return false; otherwise raise an exception and do - * not return. For user-only mode, always raise an exception - * and do not return. - */ - bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); /** @debug_excp_handler: Callback for handling debug exceptions */ void (*debug_excp_handler)(CPUState *cpu); @@ -68,6 +56,16 @@ struct TCGCPUOps { #ifdef CONFIG_SOFTMMU /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** + * @tlb_fill: Handle a softmmu tlb miss + * + * If the access is valid, call tlb_set_page and return true; + * if the access is invalid and probe is true, return false; + * otherwise raise an exception and do not return. + */ + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); /** * @do_transaction_failed: Callback for handling failed memory transactions * (ie bus faults or external aborts; not MMU faults) diff --git a/linux-user/signal.c b/linux-user/signal.c index 135983747d..9d60abc038 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -697,9 +697,6 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, if (tcg_ops->record_sigsegv) { tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); - } else if (tcg_ops->tlb_fill) { - tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, ra); - g_assert_not_reached(); } force_sig_fault(TARGET_SIGSEGV, From patchwork Fri Oct 15 04:10:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515818 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp145670imi; Thu, 14 Oct 2021 21:37:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxI0NTt19MSZ0osubKebeSUM6VUq4rlaI/0jhZqfGEjFZl6PnpUO9+sXe0NpeZQ0eAmlTbh X-Received: by 2002:a25:e753:: with SMTP id e80mr984541ybh.523.1634272641174; Thu, 14 Oct 2021 21:37:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272641; cv=none; d=google.com; s=arc-20160816; b=LxXGXe6S4Zp2CLA74vteSWIIxGYVqVWVaALxsMPFi5irWpMQg+9bdDNEnXUGS3AAN9 0FFMoLLPChsvcR6+eJml59g0Tb1k/UhIXKbl1BX/XZ51/fbx0dMwRa088cVYHfdfOXUJ IwKRmG6C/tGA/tLuwzqS4DI3/LHVJnhBxRniGIepjuQCQQHZu1EFh+ZUfFia/57bR3Hi n/vTIfD1YLzgaF8DQf/ar+/2G+nnHvbKbZePVcX6X2T7qWpBGHZT5sYUBK3fKAgBEm8Q 7bGMLcZe/w0+Pzm0Fw7HVQ43uxhvw0ljVIyZcqQmgfOL/aMS2NPnnYiF0gJzGK0UPpwm 6yQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9lqN/uiH3UUIeVg5yhYMxWg7ld7QYTaBAGHdI8OeAIs=; b=MQRpoFPDFfTK1b4sKnS7cvVe2OecehmYQBsn+rKRHOSFEmUhkvhUAr6/XPz9xWWt99 kxa+hiz2Sa7dC/uEdRFOzgtg4ueVy/1Y4TJow6D/EOWYleHpt6AJT15mp6j2vDsFl/94 Kz3dHsqsfC4PEtNUQLdtX8oqKTmyBVhm7sTkd04sAhQj6f9OXYvPtdUu/Mq2NU5W8b4N VEIKwVkmWXrYTbsIMfELAemXpoy1/xG3hrUYBstq1ketvGT3FU8hztlIt2+g+gCeRtld EgtRq1Xh2VSWqhMXJOVytYKoLGaG6+ayWjrbq1wXqZON2zFlLCHltp7ZnX4qrT9FcM2i doEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=P5B71VSi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k76si152568ybk.46.2021.10.14.21.37.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:37:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=P5B71VSi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEy8-00038w-Gm for patch@linaro.org; Fri, 15 Oct 2021 00:37:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39426) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc4-0006U8-Ce for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:32 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:39604) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc2-0002lr-MW for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:32 -0400 Received: by mail-pj1-x1029.google.com with SMTP id ls18-20020a17090b351200b001a00250584aso8447411pjb.4 for ; Thu, 14 Oct 2021 21:14:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9lqN/uiH3UUIeVg5yhYMxWg7ld7QYTaBAGHdI8OeAIs=; b=P5B71VSi1+VMlTDxlHkiYLGQsICQM6ftakBQ+W5AWd7paiMDzsaXXwtuMMt75eOFro SVl2Id2rdy+lQfOiAbK4okwACo7ulJaDwy5CwbzTbkwWqWzMSc4iFrSIXENbenU/xf/F H/rNSprsA+KSmeR3BDfazcX1soyZVQ/v6hn0MEZ2QFM7MftW18Caf9BHHkhd9GVa+lql V4U7j8tZsaSuyFKSNPtmQngNquNZJPwIdoIh8WbBFG0V+Zx9FP1KrYI6Awx0a0ErvkcZ cdDO4VruWnI/BzA/+scwuXQZCc4dmfMnDgMbAL216hDGm+VGTqLhc3k+iZfOYwTEfRgz KNFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9lqN/uiH3UUIeVg5yhYMxWg7ld7QYTaBAGHdI8OeAIs=; b=NPcxTi5nCDaSFxT1HYSHMZ77TMWX/FACNKY5L/nYIdR1TX6U7S/yREhNoTIws5xnKt epuRFqX6OXRgw7+Gksb5wFBMxLkIH6uGK2UXfC4lZwY/FAxgVRr1QOLkmbo0X3WnmuCF 9yl9tAdJuzMKnbcu2kpOGUQBXPiCbKjAulLClzNVQb6jynEcLE0H3Wvoo1U/eLffHkqE rOLHTLGus2JnoFv0E2aTU6KoYgAFQ5Sfj8K/EMF52fW+0K8nKGrcSf+V9ocDZgCgXqcm BAsXGXTJLgHfMndKjeKZRecBi+Vx7wND34EDtZBaUVq9G375AVWrEl5SzSJgZxBvVy8I XlrA== X-Gm-Message-State: AOAM530M95F07GJuoykNE43wei6qDU4YZt5F8fDxZXGxyos/Q5AUnWGf wTdflZbw9mvPlY6QsJienPNfQaQGsNI= X-Received: by 2002:a17:90a:1507:: with SMTP id l7mr10749099pja.141.1634271269353; Thu, 14 Oct 2021 21:14:29 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 42/67] Revert "cpu: Move cpu_common_props to hw/core/cpu.c" Date: Thu, 14 Oct 2021 21:10:28 -0700 Message-Id: <20211015041053.2769193-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, Eduardo Habkost Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f. Despite a comment saying why cpu_common_props cannot be placed in a file that is compiled once, it was moved anyway. Revert that. Since then, Property is not defined in hw/core/cpu.h, so it is now easier to declare a function to install the properties rather than the Property array itself. Cc: Eduardo Habkost Suggested-by: Peter Maydell Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 1 + cpu.c | 21 +++++++++++++++++++++ hw/core/cpu-common.c | 17 +---------------- 3 files changed, 23 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b7d5bc1200..1a10497af3 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1008,6 +1008,7 @@ void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) GCC_FMT_ATTR(2, 3); /* $(top_srcdir)/cpu.c */ +void cpu_class_init_props(DeviceClass *dc); void cpu_exec_initfn(CPUState *cpu); void cpu_exec_realizefn(CPUState *cpu, Error **errp); void cpu_exec_unrealizefn(CPUState *cpu); diff --git a/cpu.c b/cpu.c index e1799a15bc..9bce67ef55 100644 --- a/cpu.c +++ b/cpu.c @@ -179,6 +179,27 @@ void cpu_exec_unrealizefn(CPUState *cpu) cpu_list_remove(cpu); } +static Property cpu_common_props[] = { +#ifndef CONFIG_USER_ONLY + /* + * Create a memory property for softmmu CPU object, + * so users can wire up its memory. (This can't go in hw/core/cpu.c + * because that file is compiled only once for both user-mode + * and system builds.) The default if no link is set up is to use + * the system address space. + */ + DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, + MemoryRegion *), +#endif + DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false), + DEFINE_PROP_END_OF_LIST(), +}; + +void cpu_class_init_props(DeviceClass *dc) +{ + device_class_set_props(dc, cpu_common_props); +} + void cpu_exec_initfn(CPUState *cpu) { cpu->as = NULL; diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index e2f5a64604..9e3241b430 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -257,21 +257,6 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu) return cpu->cpu_index; } -static Property cpu_common_props[] = { -#ifndef CONFIG_USER_ONLY - /* Create a memory property for softmmu CPU object, - * so users can wire up its memory. (This can't go in hw/core/cpu.c - * because that file is compiled only once for both user-mode - * and system builds.) The default if no link is set up is to use - * the system address space. - */ - DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, - MemoryRegion *), -#endif - DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false), - DEFINE_PROP_END_OF_LIST(), -}; - static void cpu_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -286,7 +271,7 @@ static void cpu_class_init(ObjectClass *klass, void *data) dc->realize = cpu_common_realizefn; dc->unrealize = cpu_common_unrealizefn; dc->reset = cpu_common_reset; - device_class_set_props(dc, cpu_common_props); + cpu_class_init_props(dc); /* * Reason: CPUs still need special care by board code: wiring up * IRQs, adding reset handlers, halting non-first CPUs, ... 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[209.51.188.17]) by mx.google.com with ESMTPS id d207si5643054ybh.373.2021.10.14.21.47.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:47:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X5WBD+7b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51068 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF7y-0007tW-IG for patch@linaro.org; Fri, 15 Oct 2021 00:47:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39446) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc5-0006YW-Iv for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:33 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:54254) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc3-0002me-Oe for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:33 -0400 Received: by mail-pj1-x102c.google.com with SMTP id ls18so6335456pjb.3 for ; Thu, 14 Oct 2021 21:14:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wpoZicnTiBlydK+sFdKdK9FSFNaqNFWg+Zx3DgtSaaA=; b=X5WBD+7bcnTQNUibf/XWQDujaRiE8XXZglpfDAgA/kP2gXTnWVRfywtW6143hmEk8d Zld794Ip4VggTwMRRDnXmgzJA2l7Oy4R3qmhNIrN4Lc0Y9/X9sR5srDHuMSZKMO7GP9q YY0MOK4xt4q4TaZ1s379aeHzYDk6Z9R5XnECzyknD/r15KSctF2wvREpWFpZLGiam7Uc MP2BCWbpGPLgWNrKbQ/IMv9XtMU62er3ockLXT7xIHS0HywDxQ15NMJ751MQMNhR9dsR 9ZUp5EyNiczLVKBfcipn0yq3pfa/djHvdebJnvAQnAdd4GYDV6sdzhDZzTwBrmz6LgJw 551A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wpoZicnTiBlydK+sFdKdK9FSFNaqNFWg+Zx3DgtSaaA=; b=hBeqLpII2pcioL+RCB0LZPK6ec+SgUU4tFCyIgelOA9LSNz2R1xc0t3MFssaBIbXVF SptIk2xkek6I/RwFhgqX+Os7NadWSwJE4PIXEcstZ4gq7t/8s8ouexVvCvxbT9CcNcOT Wxm8yDyIW5gqOiYJX9Bk11UuMbKg2JwssEjW+3M3EMB7ODNBcwxJpePY/yvxO+MXXcxi Ox02t8sUN++a7iFMygDOevnm88BhMGFNxE5AG54rEcgFbovhZlJZ6juY4I837j2XkiOA VsxtGUmeHhD4+oQcDyr2Qi9olelaYPd66DB0cqGnX8Iu3weRDum1AiZUMa31imeHw26r Hi0w== X-Gm-Message-State: AOAM531H9F76pszPBipeHd/svRdrm/ojk0N9FutNy9nqCBd6r7yFhDgq n2bpqnQ+u8UxkBC6QnEu+OBLWF5w5JbkVg== X-Received: by 2002:a17:90b:4011:: with SMTP id ie17mr25111929pjb.41.1634271270276; Thu, 14 Oct 2021 21:14:30 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 43/67] hw/core: Add TCGCPUOps.record_sigbus Date: Thu, 14 Oct 2021 21:10:29 -0700 Message-Id: <20211015041053.2769193-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a new user-only interface for updating cpu state before raising a signal. This will take the place of do_unaligned_access for user-only and should result in less boilerplate for each guest. Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) -- 2.25.1 Reviewed-by: Warner Losh Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 8eadd404c8..e13898553a 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -135,6 +135,29 @@ struct TCGCPUOps { void (*record_sigsegv)(CPUState *cpu, vaddr addr, MMUAccessType access_type, bool maperr, uintptr_t ra); + /** + * record_sigbus: + * @cpu: cpu context + * @addr: misaligned guest address + * @access_type: access was read/write/execute + * @ra: host pc for unwinding + * + * We are about to raise SIGBUS with si_code BUS_ADRALN, + * and si_addr set for @addr. Record anything further needed + * for the signal ucontext_t. + * + * If the emulated kernel does not provide the signal handler with + * anything besides the user context registers, and the siginfo_t, + * then this hook need do nothing and may be omitted. + * Otherwise, record the data and return; the caller will raise + * the signal, unwind the cpu state, and return to the main loop. + * + * If it is simpler to re-use the sysemu do_unaligned_access code, + * @ra is provided so that a "normal" cpu exception can be raised. + * In this case, the signal must be raised by the architecture cpu_loop. + */ + void (*record_sigbus)(CPUState *cpu, vaddr addr, + MMUAccessType access_type, uintptr_t ra); #endif /* CONFIG_SOFTMMU */ #endif /* NEED_CPU_H */ From patchwork Fri Oct 15 04:10:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515822 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp147152imi; Thu, 14 Oct 2021 21:40:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzFFL3wE/PjL8pWbHkmElSNAjWelQGCmCAv1rGuSF0fTJJ97tjWek38m6hr21/Da7Qxpj6w X-Received: by 2002:a92:cd8e:: with SMTP id r14mr2157985ilb.291.1634272805782; Thu, 14 Oct 2021 21:40:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272805; cv=none; d=google.com; s=arc-20160816; b=AWNw1z3P5vNeY4OUIMBsSsgk+pDXmJZVfgsACzk0tcg8ja39hLb8P5svaa20ucRpoH olhzSsZ5oIqwdZlKd6fp8LmszS+HqC1QsFRF0RzckYZckXv8Qc16Mxfr3Qtwxp7HSDEZ bZPfjp0VMNLQLJWnaAV9ZxXUDFH7qUqOMYTll0NvZ9sxHr4/6wId1UdvMpMMJGuh2s/d n6CAdwEIcvO4U6bgcqwUPBUH/19zyjFUK9NnkemeDD6yYm/0t7JV6e+m+WPolUceWyLD VFvslD5iQzeGW1c84kF2XVEQ/VgHhiX5JGdsnSVL3aLEDzsuXWO3JZq4HpZIaj2peoNO pnAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=67r73sMxmFAFlBR0ViNOs8odKIpwZUQrX4e2focSvME=; b=ZqIDlyTzdFKtLAx3RIw4ez/Er7yV1XuMeKzLPa8iGcB/S6vv3TAmiPYyR7qkalBYxN j+THAP6YKsrux+0cUG7O1nxB6F6ckftYfXDW5EFfzPexLlIJ3APcWlan4AQPUUJ74cl2 cypWU5u8kQUfd++k/4ILmWpDL1BDz+EyWF7dsmAbLyLKPi2bJVUdOgNj/iS8YTPgN1HU tU/MrZbLNtrUDFR1FUqsJFii+krgrb0/pcXxcYiBAsDw3NWIKOOPmP0JT1G0zu9OieJt EZdx6yEhfYCkqezkWuSLgKuJD2fhbao5qrIJzG/nMp2sj5beuivqn2k0XADVV6iMGovm X/Ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PDYhmQPC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z2si5383848ill.147.2021.10.14.21.40.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:40:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PDYhmQPC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56960 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF0m-0000g9-Hx for patch@linaro.org; Fri, 15 Oct 2021 00:40:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39448) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc5-0006Yt-N7 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:33 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:44017) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc4-0002mo-5K for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:33 -0400 Received: by mail-pl1-x635.google.com with SMTP id y1so5590553plk.10 for ; Thu, 14 Oct 2021 21:14:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=67r73sMxmFAFlBR0ViNOs8odKIpwZUQrX4e2focSvME=; b=PDYhmQPC1wqr9JTz7mYBYfET4px6+8klt9olHF+41DAhgt7tLeUyyWOPba8RW7b4RB EIX89Lkfo+jZVUwe92XAnA6Mjesxyna20E1NBcWbTP9TSe4y7nuo6Zk7jGLE9mDPzwYO yj3SklMZb5O7RmFl1F0RhIoB+C0iXMwjviHr/zb68/7MkJco473o6iNCIaGkAGNl4I5a BoXhJvQ2frhpm9HuOdDEmle8fOqEyDqLP0LH3URDlxELuvd6L7nS7hUpvIxX4qZ+NxjS MLgRcCYAKHhVo+ggGmEEmMrkmI0b1vjtZOkQPU+MOLCsZbvqygDx1QzY/NiQ9A/cVf3t /M6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=67r73sMxmFAFlBR0ViNOs8odKIpwZUQrX4e2focSvME=; b=Z/p1ewz3L24+b3gHBaSVMt/WW5mNiTSPeRNLnYdCK9j0LaO7Z6DVGfMQfMfc1Z+XZM DSvehxNxxtC+oBuHIvdBKsjT54+CB58vw1QKAJc/fdbFyYXVBpPMD5vbwc7+VROX8V7M zG3s5otOVTS27+Ymf+U8vn/8eBYGOjczVjrRJOdEOBV0hzMOEP7uWVA4DXVR52nUBLPa XdKV4kHTFS98F7DuEvSPoepjv0vWJ+3NXcw3k9zDeWpdhIAj9aqB85o7y69x/dWRvvEP ibk9bYsRPmHvZ1dFGEFaPh++h0c5FAXwxagsQieVsBvRIy2EddLwnz4kQuH0/+0fAovj jhWg== X-Gm-Message-State: AOAM530e4oXeNb4HREwQFqPxyJU6R+Q/dFK9JY+rjBO23m2Sk4/AjIr5 2kEqbGLMLjgnkldN2lM7yT4feajoZVVTfA== X-Received: by 2002:a17:90a:e7c8:: with SMTP id kb8mr10707601pjb.95.1634271270863; Thu, 14 Oct 2021 21:14:30 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 44/67] linux-user: Add cpu_loop_exit_sigbus Date: Thu, 14 Oct 2021 21:10:30 -0700 Message-Id: <20211015041053.2769193-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a new interface to be provided by the os emulator for raising SIGBUS on fault. Use the new record_sigbus target hook. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 14 ++++++++++++++ linux-user/signal.c | 14 ++++++++++++++ 2 files changed, 28 insertions(+) -- 2.25.1 Reviewed-by: Warner Losh Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f74578500c..6bb2a0f7ec 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -700,6 +700,20 @@ void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, MMUAccessType access_type, bool maperr, uintptr_t ra); +/** + * cpu_loop_exit_sigbus: + * @cpu: the cpu context + * @addr: the guest address of the alignment fault + * @access_type: access was read/write/execute + * @ra: host pc for unwinding + * + * Use the TCGCPUOps hook to record cpu state, do guest operating system + * specific things to raise SIGBUS, and jump to the main cpu loop. + */ +void QEMU_NORETURN cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, + uintptr_t ra); + #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/linux-user/signal.c b/linux-user/signal.c index 9d60abc038..df2c8678d0 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -706,6 +706,20 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, cpu_loop_exit_restore(cpu, ra); } +void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, uintptr_t ra) +{ + const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + + if (tcg_ops->record_sigbus) { + tcg_ops->record_sigbus(cpu, addr, access_type, ra); + } + + force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, addr); + cpu->exception_index = EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, ra); +} + /* abort execution with signal */ static void QEMU_NORETURN dump_core_and_abort(int target_sig) { From patchwork Fri Oct 15 04:10:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515819 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp146228imi; Thu, 14 Oct 2021 21:38:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzznur0hZS5y3r2Do2aurb3IB0dmImRJfRt3ZaJ7TlzNSL8cdSSPZwvNXRUarTSexONjQWR X-Received: by 2002:a05:6e02:1a43:: with SMTP id u3mr2248409ilv.35.1634272702951; Thu, 14 Oct 2021 21:38:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272702; cv=none; d=google.com; s=arc-20160816; b=Dqwovky2ltrTFjcmNbCMvLVowRE/+CDeCE4TkkbvLh86Kyx3Vh9z4qMjxvFRfaRFyX 9hp9IEhLfbX7y4peol8QIUzI4XR27OeazZGqSHUmaVN/9foQV9IlWBWsCXhR8ytBEkZk 2xIhDATSIBLi+KuhqljOBTmca5SU1Z9VAQLv5TCcQhUA5S/SJ28oBXqE2hcdvRlZpPb3 k1c7Zmw1CUh4S8y+8vvznbbDsW3kGGKyG++nHIhFSzU3EeJvcmBeACxgvatlX+eGrZmN lImWQWDtFAFMRT6OZ+okvzpJJDy8HPQTJ+dHN9IuWbGSWwgicV1SfaMZ/czCK256DnTN 2uBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rjBYeTS3X9ZvDGx0FPpXOAHGwl8wPIvp5ueP48Sb5aY=; b=fuDoNj9KMLtGpbtSXP9+Yii3qU3g4ROGuK3kBfXwElJ4l1P5IhqtF+p9c3wIcaRqUV Ct+LdoKFl3GcGTG9yQ88rBiX5Y+W1cz4Ldndd+ZuuTri4v2s4mNfEG/quSeNZcFykhS/ /jjqYaCMVk4w6o+e0Irp3TAaJEX6HmNwH5t49VSwEzrbQRignWCsJBzBIhxbDQGILp7l 5NwwUEDr4vRVkuyLRnwt8bthZ1SJC924Al8Etd+s7NgSV9KC85b2+it95WZB3Lts5bvU r+FynldEP/5vZiqVysF4GW0iyse43Ytt9CMbEq2NhgBEOYw2PL5TAZKr8vdGAMWKm2AK XTXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aii45HRD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v15si6025332iox.45.2021.10.14.21.38.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:38:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aii45HRD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51014 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEz8-0004rZ-6G for patch@linaro.org; Fri, 15 Oct 2021 00:38:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39472) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc6-0006d5-VS for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:34 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:44677) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc4-0002nb-TV for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:34 -0400 Received: by mail-pl1-x634.google.com with SMTP id t11so5591572plq.11 for ; Thu, 14 Oct 2021 21:14:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rjBYeTS3X9ZvDGx0FPpXOAHGwl8wPIvp5ueP48Sb5aY=; b=aii45HRDIzXwwLEg2C5lkj+nmA/V8MBOpjqmMSeRWc3RsuZAcfF8QHVBlrdR9EFXQf cEz6iG8bqfTDrpyQIdZktvg/3RqJQKN4Gix+qOb1G022r5PysBiEkr56Grmb8H62pQdF q3LQ5EZAWuyqYQm8HQAYrTHHTBQyxWkftDqqJJmUf43DvMRrZJURhO3t8AIe6eii++D+ WL4VozPXh4f3HK6vChuEYfIH6TQiOTPEtk8sJtj+gcy8sD4/UwVXHSy2lNrsq5RX3Iiy 4nQsAxRPsEgsywE4a2QtPxaENxCvKv1iqLB8BJXRm5n/trb3uBNc+HisnYrg+da/R729 fHuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rjBYeTS3X9ZvDGx0FPpXOAHGwl8wPIvp5ueP48Sb5aY=; b=Nl1JDQVPcNdIgX+jQkgB73l8Fggnt673kdsh+YQzlLH93/X+3QYEdsNd/z0ouemS+t e1ImX3nw/pBtDIeIlcdTq/VmczyE1yajFHZaT1tpL52hyFsSF2GLooE28hfaT4nCezcJ v3YhGweEkCLI3cDSwLv3jevqFrjvxcRxEl1fI0o8jgr1zgX7Dt3BdQiuzU55FMs14aZy nb3p7LgVQ25esRzR9ZvaO1rS37zvRMLUGXLUJTuoNJrB6iOIJWIiOzryXDxH/tcgujAj 0uwOStKvr+Ee5KBQnJWfJ3n4wTa0jpyUd0iIlYBpNq8ZFOS/iSKomb2YNXdbcFHYLqrI Fcqg== X-Gm-Message-State: AOAM5301QjaeL3GINHGpFrHiDT6J21CYqG0tqBq6bKHcoM1gZ8kjFAJ2 QzQe6cExzV0XfmOiCEVLNg+LY4M9tiA= X-Received: by 2002:a17:90a:7e82:: with SMTP id j2mr10774963pjl.165.1634271271566; Thu, 14 Oct 2021 21:14:31 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 45/67] target/alpha: Implement alpha_cpu_record_sigbus Date: Thu, 14 Oct 2021 21:10:31 -0700 Message-Id: <20211015041053.2769193-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Record trap_arg{0,1,2} for the linux-user signal frame. Raise SIGBUS directly from cpu_loop_exit_sigbus, which means we can remove the code for EXCP_UNALIGN in cpu_loop. Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 8 +++++--- linux-user/alpha/cpu_loop.c | 7 ------- target/alpha/cpu.c | 1 + target/alpha/mem_helper.c | 30 ++++++++++++++++++++++-------- 4 files changed, 28 insertions(+), 18 deletions(-) -- 2.25.1 diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index d49cc36d07..afd975c878 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -282,9 +282,6 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags); hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; #define cpu_list alpha_cpu_list @@ -451,10 +448,15 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val); void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, MMUAccessType access_type, bool maperr, uintptr_t retaddr); +void alpha_cpu_record_sigbus(CPUState *cs, vaddr address, + MMUAccessType access_type, uintptr_t retaddr); #else bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 4cc8e0a55c..4029849d5c 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -54,13 +54,6 @@ void cpu_loop(CPUAlphaState *env) fprintf(stderr, "External interrupt. Exit\n"); exit(EXIT_FAILURE); break; - case EXCP_UNALIGN: - info.si_signo = TARGET_SIGBUS; - info.si_errno = 0; - info.si_code = TARGET_BUS_ADRALN; - info._sifields._sigfault._addr = env->trap_arg0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_OPCDEC: do_sigill: info.si_signo = TARGET_SIGILL; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 69f32c3078..a8990d401b 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -221,6 +221,7 @@ static const struct TCGCPUOps alpha_tcg_ops = { #ifdef CONFIG_USER_ONLY .record_sigsegv = alpha_cpu_record_sigsegv, + .record_sigbus = alpha_cpu_record_sigbus, #else .tlb_fill = alpha_cpu_tlb_fill, .cpu_exec_interrupt = alpha_cpu_exec_interrupt, diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 75e72bc337..47283a0612 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -23,18 +23,12 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" -/* Softmmu support */ -#ifndef CONFIG_USER_ONLY -void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t retaddr) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; uint64_t pc; uint32_t insn; - cpu_restore_state(cs, retaddr, true); + cpu_restore_state(env_cpu(env), retaddr, true); pc = env->pc; insn = cpu_ldl_code(env, pc); @@ -42,6 +36,26 @@ void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, env->trap_arg0 = addr; env->trap_arg1 = insn >> 26; /* opcode */ env->trap_arg2 = (insn >> 21) & 31; /* dest regno */ +} + +#ifdef CONFIG_USER_ONLY +void alpha_cpu_record_sigbus(CPUState *cs, vaddr addr, + MMUAccessType access_type, uintptr_t retaddr) +{ + AlphaCPU *cpu = ALPHA_CPU(cs); + CPUAlphaState *env = &cpu->env; + + do_unaligned_access(env, addr, retaddr); +} +#else +void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + AlphaCPU *cpu = ALPHA_CPU(cs); + CPUAlphaState *env = &cpu->env; + + do_unaligned_access(env, addr, retaddr); cs->exception_index = EXCP_UNALIGN; env->error_code = 0; cpu_loop_exit(cs); From patchwork Fri Oct 15 04:10:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515823 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp147619imi; Thu, 14 Oct 2021 21:40:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx/dUF0DW3sQ/gsFfInyDyDVz3LtOwZyn4ETf9ZHlRKrYC+Y2A0slNOzPzqn6EeWGQ+O5SA X-Received: by 2002:a92:d851:: with SMTP id h17mr2241014ilq.312.1634272853859; Thu, 14 Oct 2021 21:40:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272853; cv=none; d=google.com; s=arc-20160816; b=yBAaFmjBZri4OwvNjq4AYd6RAT5GdZFpM1NK8wmgzhlgwjzqk3cnAcMqvVcpQOzTTQ 5cLM3O8LkbXIGieV30IhoBsETfZnOVteOMjO4YyuwT1ygJBTrQoww7bOtarjy9L3cm0V ZLJsMKt7ZFJckRwzZ3Le/+LdODp4LiDbYTGVEHyskJ1D1QE6Y3GT3D9Pp7L6CsPZgAcx 1Th1Hq2H8OxqGAuBP8F73z5FYzvxagoLIcVrwLa47TLl2gAwHG80p++D5jHnwMxV0Xv7 p6jA0I8q6D3JeI8fYZpQyc9XUWCu0KiH5UzUKUDs95kcbOTCknId0oQTUa57GXZE847d VGaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AiCyvdTR/3QA/VxcdfSHeMxoA2jAV+mFfUYWeOlFIz4=; b=UVtzoAEbx4W/25xyDIo7VM1hQ9inkKJrYU9rhkjgrXYZHF6sdCdIGnkm+SAs2aNYsi kGWCEWLhysXDLPisXffroaPFqQifcjFWB0EzCZ6uJ6NbLIDjz8jWQpyzLcIpRoByl0wA KK+LFWWZ3Aa4AXzxgon0F3W9R7vDQsA44+IwfNuoHe7jf/OjpNpMQGzzBV+tBIVqJR07 iiXu8XKFJNH99eTFFzpjztyqrqT68oXPN/n/kVHMHN4T/vOEqYJywl9peWdT2WAR6qzW g5XY7eIVEVYO78bR561G26qJb3uHVqiq5l86FCsq3y3gz6+wNJRME44ZF0hyn11ER9XH DmcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AzkuZD2w; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This means we have to handle the exception ourselves in cpu_loop, transforming it to the appropriate signal. Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 ++ linux-user/aarch64/cpu_loop.c | 12 +++++++++--- linux-user/arm/cpu_loop.c | 30 ++++++++++++++++++++++++++---- target/arm/cpu.c | 1 + target/arm/cpu_tcg.c | 1 + target/arm/tlb_helper.c | 6 ++++++ 6 files changed, 45 insertions(+), 7 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/arm/internals.h b/target/arm/internals.h index 5a7aaf0f51..89f7610ebc 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -548,6 +548,8 @@ static inline bool arm_extabort_type(MemTxResult result) void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, MMUAccessType access_type, bool maperr, uintptr_t ra); +void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr, + MMUAccessType access_type, uintptr_t ra); #else bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 034b737435..97e0728b67 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -79,7 +79,7 @@ void cpu_loop(CPUARMState *env) { CPUState *cs = env_cpu(env); - int trapnr, ec, fsc, si_code; + int trapnr, ec, fsc, si_code, si_signo; abi_long ret; for (;;) { @@ -121,20 +121,26 @@ void cpu_loop(CPUARMState *env) fsc = extract32(env->exception.syndrome, 0, 6); switch (fsc) { case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + si_signo = TARGET_SIGSEGV; si_code = TARGET_SEGV_MAPERR; break; case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + si_signo = TARGET_SIGSEGV; si_code = TARGET_SEGV_ACCERR; break; case 0x11: /* Synchronous Tag Check Fault */ + si_signo = TARGET_SIGSEGV; si_code = TARGET_SEGV_MTESERR; break; + case 0x21: /* Alignment fault */ + si_signo = TARGET_SIGBUS; + si_code = TARGET_BUS_ADRALN; + break; default: g_assert_not_reached(); } - - force_sig_fault(TARGET_SIGSEGV, si_code, env->exception.vaddress); + force_sig_fault(si_signo, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index ae09adcb95..01cb6eb534 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -25,6 +25,7 @@ #include "cpu_loop-common.h" #include "signal-common.h" #include "semihosting/common-semi.h" +#include "target/arm/syndrome.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -280,7 +281,7 @@ static bool emulate_arm_fpa11(CPUARMState *env, uint32_t opcode) void cpu_loop(CPUARMState *env) { CPUState *cs = env_cpu(env); - int trapnr; + int trapnr, si_signo, si_code; unsigned int n, insn; abi_ulong ret; @@ -423,9 +424,30 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* XXX: check env->error_code */ - force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, - env->exception.vaddress); + /* For user-only we don't set TTBCR_EAE, so look at the FSR. */ + switch (env->exception.fsr & 0x1f) { + case 0x1: /* Alignment */ + si_signo = TARGET_SIGBUS; + si_code = TARGET_BUS_ADRALN; + break; + case 0x3: /* Access flag fault, level 1 */ + case 0x6: /* Access flag fault, level 2 */ + case 0x9: /* Domain fault, level 1 */ + case 0xb: /* Domain fault, level 2 */ + case 0xd: /* Permision fault, level 1 */ + case 0xf: /* Permision fault, level 2 */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_ACCERR; + break; + case 0x5: /* Translation fault, level 1 */ + case 0x7: /* Translation fault, level 2 */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MAPERR; + break; + default: + g_assert_not_reached(); + } + force_sig_fault(si_signo, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a18a58ca0..a211804fd3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2035,6 +2035,7 @@ static const struct TCGCPUOps arm_tcg_ops = { #ifdef CONFIG_USER_ONLY .record_sigsegv = arm_cpu_record_sigsegv, + .record_sigbus = arm_cpu_record_sigbus, #else .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_cpu_exec_interrupt, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 7b3bea2fbb..13d0e9b195 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -902,6 +902,7 @@ static const struct TCGCPUOps arm_v7m_tcg_ops = { #ifdef CONFIG_USER_ONLY .record_sigsegv = arm_cpu_record_sigsegv, + .record_sigbus = arm_cpu_record_sigbus, #else .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index dc5860180f..12a934e924 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -213,4 +213,10 @@ void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr, cpu_restore_state(cs, ra, true); arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi); } + +void arm_cpu_record_sigbus(CPUState *cs, vaddr addr, + MMUAccessType access_type, uintptr_t ra) +{ + arm_cpu_do_unaligned_access(cs, addr, access_type, MMU_USER_IDX, ra); +} #endif /* !defined(CONFIG_USER_ONLY) */ From patchwork Fri Oct 15 04:10:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515837 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp152151imi; Thu, 14 Oct 2021 21:49:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy0xBuoFAQVi/nC/JNYUQS9XexphWXWecGFMALzxDtSfHCsfz9+vNkT3tOYW8AUtV07p9s/ X-Received: by 2002:a92:2001:: with SMTP id j1mr2255762ile.84.1634273370714; Thu, 14 Oct 2021 21:49:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634273370; cv=none; d=google.com; s=arc-20160816; b=GWCFkHakiK1GvXJE9qK3CXKYk3xAIhBjBut6ol4iP5evCCbNg6/xyA2QfCrqMsho9U 30SaAzm+gtMEdQe9TjTSsxPzsAcHNoofKRxfRua+v0uNptjRBlg8ab6A699BpKU1Ypn9 Qmlks/x5mQAhdv+mgWvU5cLTeA6lD5LmrHPE4wEoLGOcF/g1flC1UnBaHSPulGfh1Hbj pt7MRpySUU/Nc5jCHUO32ymRZjyk5XcJN8LKUNZlBAeBtRPMhfH2augNHu7WjUQhjcYw ZSoT2BoOPoTvOO2w+XB0YvDhlIRvR0ruP7QiZEOZ4dut3Tltq0SSSJ59gcSMM7tHP1RM 3wyA== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id k2si7197962ilo.16.2021.10.14.21.49.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:49:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gtye64Ql; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59140 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF9t-0004xs-Vg for patch@linaro.org; Fri, 15 Oct 2021 00:49:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39492) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc7-0006fs-Nw for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:35 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:34751) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc6-0002ow-58 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:35 -0400 Received: by mail-pj1-x1032.google.com with SMTP id q2-20020a17090a2e0200b001a0fd4efd49so2155569pjd.1 for ; Thu, 14 Oct 2021 21:14:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fbekWwHWkYvCfsIkbs+I86iCi1VerGNgnv3kr2JgTV8=; b=gtye64QlPCiBbLjHqNVos/qlT7dkyTO2SNa3K4gwysvsfAekGxicpmUOyT72zufiel SK4eS+hHbKMi+j8KA4COItmQZ5rec1NpVQeAZtK16vIh8Ov9ep4TLGhevwyCwweIcKsT lGjuIU/0VO19NmNRm0K3QbYV+sdijmuaNuuh4ZzWgy8UJRbtvWVUeCQDWWnEZbKiF5Qv nTJdykhv60j58SEcvHwI7mFVZJhF2GQkLSbpbig44NnntLkV9njJ4ne+LmGPkuXAS20p x+Dt1yvyRKAlITtCn1z2Gd50alyT7OUsD4Zfl1CrD7b4W077AZr5BLkER2L+eKsqaiDa kRUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fbekWwHWkYvCfsIkbs+I86iCi1VerGNgnv3kr2JgTV8=; b=t0DrO0TPmLQSg36OIKE7mr2K0X56Pb2rwkQ3hi4ENmoaiIjJJ4SICYmsv75HkkVUC4 ZVN5Ahq+VQ0WuneIcBTwKEy9AAaKcb9a7oi9NXjkNFE0oJ7H6r5pVBN9ioACFVJqwiBO wKg8mng6PIl+C5UIC+py/BVkh0NvAWaDgD/pSs78E7ChfsPId5fiwEloHl/rRAuU3WMj pvRV2xZIXm58I0bFGdm2NpjRAh8MCVpXX2gQBiiCUmRwaSeyUlCqZJpjoZvURQEVwH75 kbCgILxZNAJXEDa3G5adxTtSLUHIMVFpoMPSSuLh//kpgeU/3EsmUnagI+/uUP3SYmF8 pXZA== X-Gm-Message-State: AOAM531HjLQ5/of1OZkOfanB+H37tScjIfD6NGN/BQWSadCWNNYvDm28 +gTqE3tpzmq9lMJ+iBXo2IidXML5IUkwJA== X-Received: by 2002:a17:90a:5108:: with SMTP id t8mr25228071pjh.201.1634271272784; Thu, 14 Oct 2021 21:14:32 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 47/67] linux-user/hppa: Remove EXCP_UNALIGN handling Date: Thu, 14 Oct 2021 21:10:33 -0700 Message-Id: <20211015041053.2769193-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will raise SIGBUS directly from cpu_loop_exit_sigbus. Signed-off-by: Richard Henderson --- linux-user/hppa/cpu_loop.c | 7 ------- 1 file changed, 7 deletions(-) -- 2.25.1 diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index e0a62deeb9..375576c8f0 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -144,13 +144,6 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f = env->gr[31]; env->iaoq_b = env->gr[31] + 4; break; - case EXCP_UNALIGN: - info.si_signo = TARGET_SIGBUS; - info.si_errno = 0; - info.si_code = 0; - info._sifields._sigfault._addr = env->cr[CR_IOR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_ILL: case EXCP_PRIV_OPR: case EXCP_PRIV_REG: From patchwork Fri Oct 15 04:10:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515840 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp153368imi; Thu, 14 Oct 2021 21:52:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzj2dMgoyLziFdc1VRcDmtSwE6sOUkBgH3kTN1b9yBG5OBzHLpGoR4o7a0JWax38tW635Qd X-Received: by 2002:a05:6e02:20ee:: with SMTP id q14mr2195801ilv.176.1634273520099; Thu, 14 Oct 2021 21:52:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634273520; cv=none; d=google.com; s=arc-20160816; b=stZoIT9z7BNNoD+DCn2HgqGvTIFvAb80Jvfe6avzF0YUsGRqn7ebX/vbWbfpcxbKpk s5qWLauZfao//sukM7aWE2JcmjUQ7mBnVnJuor33yYp/mKf8MD2luYF7BS31vrLjDBrs I4VPlZaXZ4ThqFWJPXQNFDUXX2UgBZeYbrlQxuCtbgBTaw7a1MRx7MxwACBSs0tCdqmc 3grGhvPvexpSEwgzfbuJL2aqeUTu42xrMd65UBvLlA+ujj7tbjn08NpbmNpYAmvdLdDz LhpRy/LrlWg2w7VSrmLBWxqPoSZNpvo9w8yqWgOyhA9UW7QV8w9iKb6/QPk7WiOC0jOA fEQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6inZETYo7qpmjRK6t8YVcWmKQsxE4jryCUSCrlDOgJc=; b=Wdd7f07e2VCks45Ac6TgY/iRi4eNrNPvmBJQSiYZuRz7DqY5juLPCUCiyToYhplFSd 7pBPFNId+Zp/k8M+2YAQVPQB1UoNr66LHTXJ9ITWEz+ce+ZBE+IGrHYHn2oUmMzbn9BA U4pYwDEbRlgERE2H+SWUFIujUWaO990SX7egnKvHBdCrbqI47+c/ZNvzgSDjd45Dd8XK D82gkuFUnbP/qrkutcfFSzFB4td6+oiLZJGacSdeezYRdfp5SOkaR4a7tSpvPYMPNkPJ A5vuiGuzDFXrRPWMloozyC7YJaL1AmMTnMjG5fGZvnGxIKaqW6vIMnb6A3FEpqgFPpim D6ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TFtza0gX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g12si6313228ioh.4.2021.10.14.21.51.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:52:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TFtza0gX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38568 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbFCJ-0001lE-85 for patch@linaro.org; Fri, 15 Oct 2021 00:51:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39512) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc8-0006iK-H7 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:36 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:36632) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc6-0002pj-Sx for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:36 -0400 Received: by mail-pl1-x636.google.com with SMTP id f21so5614484plb.3 for ; Thu, 14 Oct 2021 21:14:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6inZETYo7qpmjRK6t8YVcWmKQsxE4jryCUSCrlDOgJc=; b=TFtza0gXQUWkgNtMoeuWv7RWk7RnSLsiD/44n+VWMCt1DFxZ3YVS/OslUNihITMFp0 X3y+B74y8URJoQCIsdA30NpAxxXbi1jluRvZH4O0lIazJGzvVnxHtLBY3hdvUehJRuTF lScGm6BDIV4YdTXrdZ+KK9MAR1mUHb1rT7tZ0hjmrA6uN4A/L1oPkMQtcm144CVDZQtM 1SnTb9VQe8KB98V0gVpcAKJo1Egb6ecUXu60sVwcmu07Q8edu9KhuN33lT/2yjBpbx/N B6KhtJmaVW4RA/bHHN07FVmTLihqoZY9bDMp5FNUl8y000lo6g86KADmcJxErOFwgEND ff5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6inZETYo7qpmjRK6t8YVcWmKQsxE4jryCUSCrlDOgJc=; b=kp3fsknnMBMlMWK62OAkjbh6P0/uqtbXnpBJKR/9mz7+Kcwx7uwMZrmmnq2EyMp1mo dEckkx9jlDlnLkQlBM/ECU4ZE14jEqdIpeR2gWFEK8eiL4250YEikFFhRlHpB/HnPa70 mDp7ItMdv6nWiDoRE9gQB2i5K0opIJuD+PUIpFL+fs7WfGPh4m/N+J1ZFzP1z8PZaG9L oxOWwQI+joOlE+o5gCH3zmjDexlespwtCLWsap9PhJXgMdhTrm/ZhCAOCgUe/g8a9/qL ovjasJ/S6mgmU/POSYjCMbZMd7QW/pq7tuCW+wt9VfMmjcLrL9qLSQlo1SsRPKkaVozv +alg== X-Gm-Message-State: AOAM531zojT+b/XRF/gKa8LHO2oWK7MC2R1ocqgVAl8WYne4blQPIgi5 fjuT3J3rWJShynXqv7mU7q5qfioCeIDAQQ== X-Received: by 2002:a17:90b:4c86:: with SMTP id my6mr10961200pjb.203.1634271273613; Thu, 14 Oct 2021 21:14:33 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 48/67] target/microblaze: Do not set MO_ALIGN for user-only Date: Thu, 14 Oct 2021 21:10:34 -0700 Message-Id: <20211015041053.2769193-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The kernel will fix up unaligned accesses, so emulate that by allowing unaligned accesses to succeed. Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a14ffed784..ef44bca2fd 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -727,6 +727,7 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) } #endif +#ifndef CONFIG_USER_ONLY static void record_unaligned_ess(DisasContext *dc, int rd, MemOp size, bool store) { @@ -739,6 +740,7 @@ static void record_unaligned_ess(DisasContext *dc, int rd, tcg_set_insn_start_param(dc->insn_start, 1, iflags); } +#endif static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, int mem_index, bool rev) @@ -760,12 +762,19 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } + /* + * For system mode, enforce alignment if the cpu configuration + * requires it. For user-mode, the Linux kernel will have fixed up + * any unaligned access, so emulate that by *not* setting MO_ALIGN. + */ +#ifndef CONFIG_USER_ONLY if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, rd, size, false); mop |= MO_ALIGN; } +#endif tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop); @@ -906,12 +915,19 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } + /* + * For system mode, enforce alignment if the cpu configuration + * requires it. For user-mode, the Linux kernel will have fixed up + * any unaligned access, so emulate that by *not* setting MO_ALIGN. + */ +#ifndef CONFIG_USER_ONLY if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, rd, size, true); mop |= MO_ALIGN; } +#endif tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); From patchwork Fri Oct 15 04:10:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515820 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp146235imi; Thu, 14 Oct 2021 21:38:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzwA5Ar8/i0gYBDt27qwNSbqD1W4SkNO2Q75LvUwQukafUuCWPrI6C98MLeJLTB8+wQK/7a X-Received: by 2002:a05:6602:2bf7:: with SMTP id d23mr307025ioy.187.1634272704097; Thu, 14 Oct 2021 21:38:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272704; cv=none; d=google.com; s=arc-20160816; b=OF98RNsnbAAoqp9pX2zi9aIkCrGFcEbCpVIzc2wvuNYaDgRx6uUVS3VL9oF2YC74Wy /achFI8NmDZrxPe2jm0XKTK3WZW2ymWMeNp0BRzfUWAQI5uVGEX0Obc0Z89dbg+ss/V5 Uj5RpAG0mUtEV5vMIyFUVnWzmZu5tUXfiALs573lCnP05V3oCSiec9Fs8jZP4Vl0kisY frGu32fGnk2iwanXFo0OiGPSmf975vbFy1AttuDJDhMonU/dM3bFd1FBPnhW0MwgQYUT lNE1h25gtNwuMJRBPdrthUGJMVL7Iq2YO+xuiFk8gD7xrhgYC8Y1u+EQxZTZY4UZAgoA 1kEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=54O7y5F6cil48JbVjJeuP4tBSWG4MHFPBxntrZflWpI=; b=0YQH5QNjyxGUitI9c6/xpjKIHIkjv5zypTTpG00ySAV17ztIC+jAHrZkdHu/YOYXu/ TQDUWc1cdjn29JOs+1XMOWKWw2T/onVzhMOvNhkAx5OXJiJ+Dh9IA5y+QR3TPgsaLDw+ tLcFgjmEv+fii9pp35ApegOwfYfWSQn6gRvAIkQEAiCHa6Pin3R/YS2FYYXDv7SflI36 IuFuWDvRkst3C7mdsfn5Ri3b4Q0GiObmMPSYigWlIeJ80parfmxteFZMUMtDuDg+82P/ DWbaovm8kymWakkAR4zYzotGcmd7yPwaqOA6MpOkgkSVALX+GObVu1ixqVTfSRMsPELF /FXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=j2F0q+XN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b12si7335077jat.94.2021.10.14.21.38.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:38:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=j2F0q+XN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51124 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEz9-0004w0-EY for patch@linaro.org; Fri, 15 Oct 2021 00:38:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39532) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc9-0006j0-0U for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:37 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:39689) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc7-0002pt-Dl for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:36 -0400 Received: by mail-pl1-x62f.google.com with SMTP id c4so5603165pls.6 for ; Thu, 14 Oct 2021 21:14:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=54O7y5F6cil48JbVjJeuP4tBSWG4MHFPBxntrZflWpI=; b=j2F0q+XNNa4YJAjmRIlOE/2uI6va5is0BkOliZCkPSdM7yJyMQUqHTbOAtG48UZmKP WOFj2VBzpwAVJe5hwAnT4DoEAL5/c88wBCspBHTdpkXBGWryHUcwNKrFNHYyJYJ5vzE5 +QpsoqzihaJgoAt8eR5JWf3O3gNbkjQPeunVM43bjcegqJ/xO95tMCxNBLk3qlrgcy8y OGawaDSThIqkTadqRim9C45riL3gzXFxbwMlQJgengKjWvp1hqIviEHxzzt2DsI3LFRM 4Ze6QHSc6WoYdJkA+YGjp/li2WJcfbqdv04PtKwCbJM3LlbiiN0WSUtWqaZpRiO+ZtGX fKcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=54O7y5F6cil48JbVjJeuP4tBSWG4MHFPBxntrZflWpI=; b=chrrrNmB4YuhsrnPokHtTdvtCc86gnihwLmCz2yFg8C01MkvSivMB88vfRT2kkY4xH RQBMS8VqEXVr/2EN5X/Tt2+yTtPjaIvrpAOWAdpjvsZwAe25zsdDqKdbjaj5ykp4/SRF PX0n3Ds63sQIwpfgy56BVValh59yErVYlEgQFBZ5d87sh5EsIrN/UCYRedB+6bl0Ee0r 9CZCWZb+r16B3XrmEvYuLzX599P0avhE0sdDkJhYt51Gght4+MsXtB2Q/zhYsOTDUlj6 66BjJ7eSZ8bAOTAmGAiWQfGiqopwyU9YLgXUfcBphy+YL2RYx19WFxM9PeYgVXBsZJEY imJQ== X-Gm-Message-State: AOAM530wfwpPSz7/I6njoW8w/YBRFkz2j6RAyPcafxxSRv0XlvQWUp0J 01PogRa28a1Ll8y9/x5yauROpRiU9B3fIw== X-Received: by 2002:a17:90b:2248:: with SMTP id hk8mr10808447pjb.102.1634271274244; Thu, 14 Oct 2021 21:14:34 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 49/67] target/ppc: Move SPR_DSISR setting to powerpc_excp Date: Thu, 14 Oct 2021 21:10:35 -0700 Message-Id: <20211015041053.2769193-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" By doing this while sending the exception, we will have already done the unwinding, which makes the ppc_cpu_do_unaligned_access code a bit cleaner. Update the comment about the expected instruction format. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/ppc/excp_helper.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index b7d1767920..88a8de4b80 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -454,13 +454,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) break; } case POWERPC_EXCP_ALIGN: /* Alignment exception */ - /* Get rS/rD and rA from faulting opcode */ /* - * Note: the opcode fields will not be set properly for a - * direct store load/store, but nobody cares as nobody - * actually uses direct store segments. + * Get rS/rD and rA from faulting opcode. + * Note: We will only invoke ALIGN for atomic operations, + * so all instructions are X-form. */ - env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; + { + uint32_t insn = cpu_ldl_code(env, env->nip); + env->spr[SPR_DSISR] |= (insn & 0x03FF0000) >> 16; + } break; case POWERPC_EXCP_PROGRAM: /* Program exception */ switch (env->error_code & ~0xF) { @@ -1462,14 +1464,9 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int mmu_idx, uintptr_t retaddr) { CPUPPCState *env = cs->env_ptr; - uint32_t insn; - - /* Restore state and reload the insn we executed, for filling in DSISR. */ - cpu_restore_state(cs, retaddr, true); - insn = cpu_ldl_code(env, env->nip); cs->exception_index = POWERPC_EXCP_ALIGN; - env->error_code = insn & 0x03FF0000; - cpu_loop_exit(cs); + env->error_code = 0; + cpu_loop_exit_restore(cs, retaddr); } #endif From patchwork Fri Oct 15 04:10:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515824 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp147631imi; Thu, 14 Oct 2021 21:40:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzwk4i7TQ7QddMHRvFiZcKpibkKkZ9bSclxZO8h7lS1d9pYFCA16oqzS7Gdju2uc4Hv0W84 X-Received: by 2002:a6b:8ed1:: with SMTP id q200mr2189829iod.165.1634272854650; Thu, 14 Oct 2021 21:40:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272854; cv=none; d=google.com; s=arc-20160816; b=CvK1Hfyb1uxslBp/XJAeLdcuXubvnEUyKQGLltDDnWkAC2Gvov1IqPOFaCx4gCf3d1 qjNL5fwX7Y2Fd4tX6dEEmVje6WMlgEUvt/Ub8ZpFaY3WM8siAe2ZqAL3dmdIwLGpmiT/ dzowMtTAI//jxy+c3mnJx9VV2/dhNGMiEizDo3kMNhBI7ZZO3nDALkLr4XtI4EiMmhM3 gROb41EXaiG4UXe9RIb9pa87Ds1DNsvu8XSu4M3NmHun9pOWJC//j6aclVIwC70KhVVj N/QrdmKpZQ7vsXOjymvyoVUxycCbYprqd6/S1zblTBLRGaPalxjxlZ0kqpF3dV0dNpt6 RJEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hDIIDmSt3XkX7dozNp8YyanBuOQiSpBj16JErrhb+ZE=; b=q+ilAeaWkGHw84WozdoSh+MFEEbTupK9pT7B9S6s7Tl7gDdRPhBlzFU/H7lzFd5EmK XEtIyI6YuxkkYHL1bYpg/roGpKnx1UzV7klbRds/BfxFAb6csTw24Mxg4Hk3dI+dGO5s e/m2oFGTOKdVN44Dv3XQZPine6UXntok+esBcvgArbtFbss8tr3//4Dtw47TIe4UNaNw D+jxboca+RoMxuaj5fhaXfBsrCqKYnEuPLmanczFX4a+Z5R4a0oeGE4fmHCNKNa6IGxt NfWT61tksVRoQPjs+r4g3C80guKPOh/LiWQQXXD6WWXXojhF4ZZZ7FcQtB5XTzQ6dFOS Yfcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=poa10+ca; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Cc: qemu-ppc@nongnu.org Reviewed-by: Warner Losh Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/ppc/excp_helper.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.25.1 diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 88a8de4b80..e568a54536 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1465,6 +1465,20 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, { CPUPPCState *env = cs->env_ptr; + switch (env->mmu_model) { + case POWERPC_MMU_SOFT_4xx: + case POWERPC_MMU_SOFT_4xx_Z: + env->spr[SPR_40x_DEAR] = vaddr; + break; + case POWERPC_MMU_BOOKE: + case POWERPC_MMU_BOOKE206: + env->spr[SPR_BOOKE_DEAR] = vaddr; + break; + default: + env->spr[SPR_DAR] = vaddr; + break; + } + cs->exception_index = POWERPC_EXCP_ALIGN; env->error_code = 0; cpu_loop_exit_restore(cs, retaddr); From patchwork Fri Oct 15 04:10:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515826 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp148346imi; Thu, 14 Oct 2021 21:42:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxIIU8iSTlBm6TGWjVXOcZmZgfrqXaamaLm49lTFP355QO7MtGHWWESKOv07LK39pF5EQap X-Received: by 2002:a05:6602:13d3:: with SMTP id o19mr2186106iov.18.1634272943214; Thu, 14 Oct 2021 21:42:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272943; cv=none; d=google.com; s=arc-20160816; b=QAxAk9IrwGESWo3GrpGqWs41TChGCOe9VrfL0LPyvu0TGv5BzOHEbmiz5gomSpkX6v BcZrlerODojMhMAGtSF7LjrU1x/1liKFxlJwIrr753/Yq7YdFey5qaTt9QZlD6utOG0l bT6PS6UDcPeNWZlAUqiTfVwbRHT/XkOuv9yLT2EQk6hFNiMkQT98vvnJwNlkZzrf3pV1 k0F1d6+rDkI7BUBmXcMOF3u1D+9ZjGwYy5QjQ5lNX32arYdG3cWpvBKmvCFhi2ebM2R2 6UzrnrgZTbaZQh2PxGXuKYy4XBdKvKqRB5/d0F91VQ2oCTI+P2K4TzRkf8omzzSg9Pvz uHUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=edXkrbkqOm07djX1rJHm1DMaa+Lm/qwNrJ4BGEQSsuM=; b=pg4j5yGqxj8SZiQsCRJ6dUN2H9WdZPh9p7c3+waO6H7cZnwPnpZcf27QVtn64bcgts dHP881gdkNKWNDKSGvrd9/0s4DF5JHjbNwZJv93DZh0rOstMeuFgOuCsrx5qf0DyVivu kxataDSErzu1tUNpIQcYY62/8+VsEaEi1jFSeGt2saxgEIE2RUiMlgCvac6hlVnHcze+ 1bKVE5kUNnlks6F1YeFRU60pTGMVTnRWOGcfeEBGjuUcm/gFYQ/EH1Ar77rPUYdU4qWb vNF4HlQAnyNs8qL63SoJeh2ArCnypuKdk03gQgmVQogJJ3512GSmgYs/bx6ZXwPps/jA Unyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DcsIbhOX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/ppc/internal.h | 8 +++----- target/ppc/excp_helper.c | 8 +++----- 2 files changed, 6 insertions(+), 10 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 339974b7d8..6aa9484f34 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -211,11 +211,6 @@ void helper_compute_fprf_float16(CPUPPCState *env, float16 arg); void helper_compute_fprf_float32(CPUPPCState *env, float32 arg); void helper_compute_fprf_float128(CPUPPCState *env, float128 arg); -/* Raise a data fault alignment exception for the specified virtual address */ -void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; - /* translate.c */ int ppc_fixup_cpu(PowerPCCPU *cpu); @@ -291,6 +286,9 @@ void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr, bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; #endif #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index e568a54536..17607adbe4 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1454,11 +1454,8 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb) book3s_msgsnd_common(pir, PPC_INTERRUPT_DOORBELL); } -#endif -#endif /* CONFIG_TCG */ -#endif +#endif /* TARGET_PPC64 */ -#ifdef CONFIG_TCG void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) @@ -1483,4 +1480,5 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, env->error_code = 0; cpu_loop_exit_restore(cs, retaddr); } -#endif +#endif /* CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY */ From patchwork Fri Oct 15 04:10:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515843 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp155474imi; Thu, 14 Oct 2021 21:55:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyczSRt5QQjiHZZWo/v+6F+NPBc5Qbf4LskPAlEIrT4MGH9p7mGnLnl1OYEQ//A1wBTATE2 X-Received: by 2002:a25:5557:: with SMTP id j84mr10932367ybb.426.1634273755691; Thu, 14 Oct 2021 21:55:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634273755; cv=none; d=google.com; s=arc-20160816; b=R1eLJQvn4RFJQcIrBCh0uxMr67WEClnOxb5jAtCgiZj67NnPhw0Za64o5hfsA8gXhr sQZWByjciiimS9P3+cEtKDDObJlZ/Bhs7rHrQ2cPoC6NGRYitI4I2V9/NIOURe9W8Gnv ysSHXGn5Bw58NgLh+de2EPZIb9C2l78d1ah5y/alP1/VZlAW74p5QyoRWPYYGoSKWaoC 2bfgbyHykwzrnkdxK3BBtQdU62f/9siPUuk4c6s9xfClpE8V8iwTm1/XX5CNSvFgYiWM SR1NC/xd32MvKjUZC6g1IOC3G04H4ML0LCnbkAbk6wHYAF+ZzhKZIUXcCWOoipB+JBFR e0Ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tQ9zUqcauybUZbu3B5IksrNIUQen6fZFWQH9MsgW1Ec=; b=Sq2o+w+JIgDlSel/oTSyAFjJhUh9XuHjXYjiXA0IK/3oPN//p5xGiUrPSCr/s3hiJ+ kJHKiSbjupeKFX+pto6B6W4mcBD6pTcCr9xVDSYkNBLeC6SISkOOH9MeuvPGSkLUStMb 97l1o0zn70TxeBMWBv12YTAMMFvoYXpzOFN3kudh1occ3RbMDVZWjyqqFBv7ENEB64f6 Lgbuthvoo4slPO7+E2AcmRiQ/g0v3FQOXhauBJ5B6t5QOOPyYBk4fufAN7jxf+sQSzJT sEXNyPkspZTLuF+oHc1pyBvH9dXZlu7+PQYUd8irS6tM4WCcnM9/djiUuT4ASUy5k7Gc Id8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IB9jlkuJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Split out a do_unaligned_access function to share between the user-only s390x_cpu_record_sigbus and the sysemu s390x_do_unaligned_access. Signed-off-by: Richard Henderson --- target/s390x/s390x-internal.h | 8 +++++--- target/s390x/cpu.c | 1 + target/s390x/tcg/excp_helper.c | 27 ++++++++++++++++++++------- 3 files changed, 26 insertions(+), 10 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 163aa4f94a..1a178aed41 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -270,18 +270,20 @@ ObjectClass *s390_cpu_class_by_name(const char *name); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); -void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; #ifdef CONFIG_USER_ONLY void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, MMUAccessType access_type, bool maperr, uintptr_t retaddr); +void s390_cpu_record_sigbus(CPUState *cs, vaddr address, + MMUAccessType access_type, uintptr_t retaddr); #else bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; #endif diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 593dda75c4..ccdbaf84d5 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -269,6 +269,7 @@ static const struct TCGCPUOps s390_tcg_ops = { #ifdef CONFIG_USER_ONLY .record_sigsegv = s390_cpu_record_sigsegv, + .record_sigbus = s390_cpu_record_sigbus, #else .tlb_fill = s390_cpu_tlb_fill, .cpu_exec_interrupt = s390_cpu_exec_interrupt, diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index b923d080fc..4e7648f301 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -82,6 +82,19 @@ void HELPER(data_exception)(CPUS390XState *env, uint32_t dxc) tcg_s390_data_exception(env, dxc, GETPC()); } +/* + * Unaligned accesses are only diagnosed with MO_ALIGN. At the moment, + * this is only for the atomic operations, for which we want to raise a + * specification exception. + */ +static void QEMU_NORETURN do_unaligned_access(CPUState *cs, uintptr_t retaddr) +{ + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + + tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr); +} + #if defined(CONFIG_USER_ONLY) void s390_cpu_do_interrupt(CPUState *cs) @@ -106,6 +119,12 @@ void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, cpu_loop_exit_restore(cs, retaddr); } +void s390_cpu_record_sigbus(CPUState *cs, vaddr address, + MMUAccessType access_type, uintptr_t retaddr) +{ + do_unaligned_access(cs, retaddr); +} + #else /* !CONFIG_USER_ONLY */ static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx) @@ -593,17 +612,11 @@ void s390x_cpu_debug_excp_handler(CPUState *cs) } } -/* Unaligned accesses are only diagnosed with MO_ALIGN. At the moment, - this is only for the atomic operations, for which we want to raise a - specification exception. */ void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; - - tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr); + do_unaligned_access(cs, retaddr); } static void QEMU_NORETURN monitor_event(CPUS390XState *env, From patchwork Fri Oct 15 04:10:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515827 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp148729imi; Thu, 14 Oct 2021 21:43:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy4FamUpxfJiUXwRap8mhI2+i1Rt/yST5oDjkYijIzR3c1x82L8eDGrH2USWDlIEh7lYK1L X-Received: by 2002:a05:6602:3c5:: with SMTP id g5mr2375570iov.42.1634272992816; Thu, 14 Oct 2021 21:43:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634272992; cv=none; d=google.com; s=arc-20160816; b=VrIJbEmHEfJYV2/OFbEfju2UsCHuw2YuiZlEZl6W7ZGjw/tzWOXUZnao/VuVVlVpvU yckdtkszya3U0U/F7+u+D3fFMOk0CmQ7U4Yk8Ftp3V9L97+RE3lwoYsK5vHvW5l+H31Y Rmv4WIIyI+VQuSXD17kC+ooQOKUwvECivMxIAqgmVuk7VdLlv5lS48RiTjc4T4kjFg0d 69Cw6+FmVZJKBX6NaM0rL1VlpIK7gmlDsjMoniekeqozO4KjPKZhJBzTg2pZeJpxFUKG ybTGyCEp4p8ymMA41zb5G7D8IA7msRbFa7Ikjh3LirZWlwDx1fnt1SauSsOxqtuomNxA Uz6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QuBUrcbK5IHnv9/MH2TrxQjSj4HGL7JlA8tE+X8E85A=; b=pru1RE0fnYrdOxgf1OP7/ogMb0cqN9Pe338J98KH0cKd0V7w0/spHunhJ/0QhE4bsJ an2cda3BjEolJQKD+8zF+wuOriesUKujQNS3fRXNRPj65kTsnbpwatd7YU5tGJHAk+Hf p/lGDAq03P9bhDlAR2JNzSOuDqq+tfU8MzsgjXhM8HmJ9bW/BuKXVJOu4+CXJuw1+pG9 mxW3zeR+sFykhCbeUxyV9S6U4MbwgvSR6hFr9y/rC/LHf+vxB56ewadqQNey1ecBpJEG kdElSN4pe5zYuA91ar11qTbICFUNzROT3rc4YzO13GXG8wZk7ZWkKitMXYWT5dV8ajGv Aabw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=giCakC6l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e7si5241374jaf.112.2021.10.14.21.43.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:43:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=giCakC6l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39524 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF3n-000858-3I for patch@linaro.org; Fri, 15 Oct 2021 00:43:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39606) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcB-0006r6-VM for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:41 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:43602) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcA-0002sd-GN for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:39 -0400 Received: by mail-pg1-x530.google.com with SMTP id r2so7430327pgl.10 for ; Thu, 14 Oct 2021 21:14:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QuBUrcbK5IHnv9/MH2TrxQjSj4HGL7JlA8tE+X8E85A=; b=giCakC6l2MtvrckNHO00CDJOIHxjYyiiplMsqYrxIqY7SO11XjAkdl7LxsrcGAL39Z kg+U6SdomLFrTarLwoH76IJ+m7F9S9ufaoMWP433H4wFRsQJ5Mvs/d+wu82L1TMOa0+w wznc58l2+DtSlgByNYs/o9Y+CTD+7pFmjTKLdzYip32HwwDd2kq8OhlK6utG+JThcAQh xtTuPD3IkvreuKzlG4hAy8S+mtc9RNfWsUJxqB7jjep5vgaZfB1S9YAPzFbdeea9bE/N b5tOG7GqCzc9u/fzvs6Oz3jSrkte1GLF5V0+CCwHA3Jjw0UqnkxqmWUsbZs5EficOYiR zgvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QuBUrcbK5IHnv9/MH2TrxQjSj4HGL7JlA8tE+X8E85A=; b=mzXjpMN+wSWmq75H+0gST5AROvfFcVxbQGiicWp/wZeM0WY2bYhcdI/Ne789+R2eHE FtNWdOCT21GGEBtzi5SatGNKlz+nZ+SDyn9B3SXCdXcT529lt5Y0CtjrfoRTC+eRrfmF ql+8fL3yVvBm+kgPYmH+gx9qtzNZt6TCowDe1rDsYojxTspnbiOlPrkYYSNN+t5qkPPY fvY4NxoFRJXpk2moRRufUkoYGlzp+X90oD25ihwjeC/pu0AGTAqV2YzAM/7T1fOVBtli CZUyQblHUP4Exl5Gu7mW/kkIrewkRaH/cEjInkWxt29hPcQxh/z5+0G2h3Q6bAKA0QCT bFng== X-Gm-Message-State: AOAM530A/Dw1wHaJecqYtzDkoUuD4T2NWdFTplLtZ5XwqJRitTMxuoZO 2O9MWyMENiVyTCd7eYfl43SiEUnEhNc= X-Received: by 2002:a63:e116:: with SMTP id z22mr7227749pgh.223.1634271277080; Thu, 14 Oct 2021 21:14:37 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 53/67] linux-user/hppa: Remove POWERPC_EXCP_ALIGN handling Date: Thu, 14 Oct 2021 21:10:39 -0700 Message-Id: <20211015041053.2769193-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SUBJ_WIPE_DEBT=1.004 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will raise SIGBUS directly from cpu_loop_exit_sigbus. Signed-off-by: Richard Henderson --- linux-user/ppc/cpu_loop.c | 8 -------- 1 file changed, 8 deletions(-) -- 2.25.1 diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index 840b23736b..483e669300 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -162,14 +162,6 @@ void cpu_loop(CPUPPCState *env) cpu_abort(cs, "External interrupt while in user mode. " "Aborting\n"); break; - case POWERPC_EXCP_ALIGN: /* Alignment exception */ - /* XXX: check this */ - info.si_signo = TARGET_SIGBUS; - info.si_errno = 0; - info.si_code = TARGET_BUS_ADRALN; - info._sifields._sigfault._addr = env->nip; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case POWERPC_EXCP_PROGRAM: /* Program exception */ case POWERPC_EXCP_HV_EMU: /* HV emulation */ /* XXX: check this */ From patchwork Fri Oct 15 04:10:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515830 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp149613imi; Thu, 14 Oct 2021 21:44:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyjCpC+CUcb8pon2+Z+VYHs607Nvv/ZxwR0rr4nOv32LoJKOc55JoYB9y9OnVvqxzvjNo1J X-Received: by 2002:a25:bb93:: with SMTP id y19mr10800877ybg.266.1634273097571; Thu, 14 Oct 2021 21:44:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634273097; cv=none; d=google.com; s=arc-20160816; b=eOcCy7sfs90DkRowecK5CT+SekiSJ5xNWvCiDQLbQwRrnIRo6w/+uMO9nt+GfBBOgd YViVLhL5qdd+6evhRTFtyTo4cBw6ASoug7H4F2VPC6Yhu3guFXGMAAyFy6JchWvBagMZ TA7J0ZKpu+DM87b67VTo+0iRNJC1eKcm+HrUteoRdRThm4HatJ2C0fb+Vipcis+B6w9V 8jEsfFoq7sLgTZYLB5yh1nRIgviT+OCvVb2dkJpz804FOCtUWsvYKZZ5vBEjuxWhXNd6 dNuFly0AUvyLewYEbQQcYwAwRZTei6L9mcshJkw5FPnthBYPa7bokA3GecEI+vuSDGMB zspg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KU5GqqnHBwJE2oQY4NvVS8KLTvZHsylgeTI1DbvIUb8=; b=RvgWb8b5hAhcQV7hHzqs1G0BQlHgy7VTXtoN5AFT5xflW36NIfpxatZUJWX9yWC1vs 49PP1lPoYLhktLRyWDgHqLMGTSKp87W2vMwxl4286XzPyH3gYhPdwnGZE/LUwnIP2OpV gPT0QdBvj6WxrQYaD+XMbSl9rj3rZ+jZQlWiA75fc/O+HHzmPbqb/42HZ1A3ObPwlgw0 mzzqdxUG/FRUY6Xw0GNmoDofesWuOKW+jqy/kzZ9dNWsZOUqYFkV/UcnCZnAcJS+V4/e i4i2oYydUjN/IK5hP4LIXBVjHT0naO+qiKfQhai+7caTKNZ86k31410DJiQENGBon4JE RiSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=caXEo8Xf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m17si2856909ybm.60.2021.10.14.21.44.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:44:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=caXEo8Xf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45104 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF5U-0003ez-P8 for patch@linaro.org; Fri, 15 Oct 2021 00:44:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39630) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcC-0006rR-VQ for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:41 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:43708) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcB-0002ti-GB for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:40 -0400 Received: by mail-pf1-x436.google.com with SMTP id 187so7279059pfc.10 for ; Thu, 14 Oct 2021 21:14:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KU5GqqnHBwJE2oQY4NvVS8KLTvZHsylgeTI1DbvIUb8=; b=caXEo8XfcVNqQC/PP328NXImnbbtyaPSavWBwvAB8S1sFXsgzGxEDM0d/OTLxO8T3G j5JkZd52oY+nRfjZbQ53ifiztefYGieujZI03+qLI1jEEtFK0KyTDNkYRHMo4enAd5ym /TZBt9pGxA4jjN5A9PttOczJhsWgvXEcH4Tb8FyhxMqvXhj/XcBi7HQJceD1j7mB76cZ AWF8/hvn9spNNvAr19X2HA8clizEy+gJhjnq/6Ux7ZahOxG4k1YgAWTYkxRVpHnylCIF ZsVM7lC3olLeQ8FtjOJohuM6AcCAt8/4U6KpU3ymYLG3tSe9MM7XIsqH1X99ntyKNXlW ZvZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KU5GqqnHBwJE2oQY4NvVS8KLTvZHsylgeTI1DbvIUb8=; b=idiLh04DVC1IXavqpuKOqnwuOXsypp3zuVHdr6oq5zUtDgrPEzVuMXW4vLng8plhhZ kms6CW/pcxRpRF22WvXLy6DWrvP3Hm28Gf0KPacGOlLkUh+cfWFDooGqs1g0o+cLbPpb 0SfjTwut1jBGCyTtWMjr7oQGMZU9hLeoSgsaVekaUvwbXNa6ooc3lohzTHehfYdGSnlq 2CfORpxNyG+O+9rC4UmfPb5txeXAgRHUeE8r3JHVHO+wZ9/TlSIQcLJ3dAfElg0knvw0 S3jCTk8U1OWWGydsWFxjDkcE/q8Y9abDPBNmVifM85eWStagp0EXRKOaH6ncecn9SEqg FNgg== X-Gm-Message-State: AOAM533x+LBZq4b20QGz1fp1XibpmXiBUhsaqi61e822Jrp46Jg1+YXN nwjOL6zXJXlUQRPjuBzymPhGWcD9ZOJK4g== X-Received: by 2002:a63:7450:: with SMTP id e16mr3562995pgn.482.1634271277964; Thu, 14 Oct 2021 21:14:37 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 54/67] target/sh4: Set fault address in superh_cpu_do_unaligned_access Date: Thu, 14 Oct 2021 21:10:40 -0700 Message-Id: <20211015041053.2769193-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, Yoshinori Sato Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We ought to have been recording the virtual address for reporting to the guest trap handler. Cc: Yoshinori Sato Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sh4/op_helper.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.25.1 diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index c0cbb95382..d6d70c339f 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -29,6 +29,9 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { + CPUSH4State *env = cs->env_ptr; + + env->tea = addr; switch (access_type) { case MMU_INST_FETCH: case MMU_DATA_LOAD: @@ -37,6 +40,8 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, case MMU_DATA_STORE: cs->exception_index = 0x100; break; + default: + g_assert_not_reached(); } cpu_loop_exit_restore(cs, retaddr); } From patchwork Fri Oct 15 04:10:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515831 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp150603imi; Thu, 14 Oct 2021 21:46:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyGy8RKZSJOp/Acmg+AuIHO40sLiZWIZSAcdRGDKUFmUPAVhv/wpJjiFUQcvbvHb577dCrx X-Received: by 2002:a25:d290:: with SMTP id j138mr11745029ybg.381.1634273192467; Thu, 14 Oct 2021 21:46:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634273192; cv=none; d=google.com; s=arc-20160816; b=NaDbsohTk4neTUu0PvvXUpj9PnnTGtTohAclaYv08tUpje3ydJRDIiHC8mPcjOjze9 6U/cCQVL02gOd2f7wdQCONFaj+WP/ngAX4ktf9XYrdsWk4F597QxJ/e0UMrJbCkKmMNu w9PVNXMMZ5m3Kcngruw0JXH9bqPrNMp+82UFgAvcWPINmIWwzX2ad6IN/WpeuMetOD9D B1Izs5OSDanlu2g6oJpaGiX8gT63hbDW0Mx0UmCFwx5VBs7tUf0EN0/ZStEsMIOYHZLL k3rLbihl2haRxpiReO4wzBkEYdY2cwBS0VirPDza4FJ1R66bSftZ2k9hd1bWqXVSINlI ixHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=P+LiSx7CkE3blKbhg5ALaxOT08dtFOhalcqlNc9ibvc=; b=m/8NQNTCaK/ubm108eJ1YCxL0yaaze++gg8hWv9ma1P0lKvNaJyZXRuXZuWA3f1T7q s1AW1OUFJR279SckxJY8WycBf5Tzv6MLZqY6Wtjm3Rb97wHFCffiXoPFA+3zPSPpYIxJ q6TeYdaDE6nhkmrOlNjlmQSazFkE6U3Ob1Z8NpiAYi2Ph2iiIcvNsBf/YA4z2bKFhPB8 yTIJI0UYpHKqEFly1Zs9Ej1N2PN9ROlt1HggF+h443KsjuWwYBec0hlbOln2OlV5tYbn AMsBYzNvyOBAmnsGMpTvZoiIIqPCYkQgqphRhm7bFLXjAjlUpcOAnNkbYN9JxF1eVd88 Cxyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fkD5lzW8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c187si5390115ybb.58.2021.10.14.21.46.32 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:46:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fkD5lzW8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47568 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF71-0005Oz-OK for patch@linaro.org; Fri, 15 Oct 2021 00:46:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39632) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcD-0006tE-Jx for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:43 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:46614) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcC-0002ul-24 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:41 -0400 Received: by mail-pf1-x435.google.com with SMTP id i76so5155377pfe.13 for ; Thu, 14 Oct 2021 21:14:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P+LiSx7CkE3blKbhg5ALaxOT08dtFOhalcqlNc9ibvc=; b=fkD5lzW8XEdW/8JddIYnS/3TBxtw+Z4dI0TbGhaI8Owa2wXINxDYLYYG4N0ClA3Xy5 dhDSus9p4jC14sPZXFqh/5UkbhTjlcZyyXyG91Pc1iMvM+H4ALkI8K1yTYG3WR6ltsDu Hym9K1DLHee57sI1ZPRMWz+K0/X8AWVEFEPHOXQfCqqzTfS1JHM5yh29ZRBtmCcTKSYE T34yzzIkzG8r00mnTgYPVuGP2AW8hGXvzBQOp9Yh8LqJWKvFAhBuVdLvVpRVT5uOKpeA eXG1K2QfwdE22EpTNl6Ay8mHRSBlIS3+3RLxvh6Sqo1outCX4mPwXXKpdT4q6XUN56gy zM/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P+LiSx7CkE3blKbhg5ALaxOT08dtFOhalcqlNc9ibvc=; b=0H4ZZ0/6vDxD5ue4Uv3d2sfGhoiyN0pDRJobSQNepeQOQcDrMZ1Ik5fYFemyvuPNCx obxgKGhmxlfYdRIc7K88JfTH347NdE6mW98wx0itD556QGmt3e6j5eGXWBQ+b4PVllTQ yMRPxe5CDp8V2/fu9FyeOvzsNcSC40AAYHac6iX8qk5aTAiDWp7ftXIk3cDCuKFiIRTd o4/j1UBHUEphGdJIJ4JTYlnScYwRSr7fBTMNp7/TSHHDpiBcZnlmMICPdB4aH7fSod/d IXdTefPjzBFEhBhtwN55jhm6Wg0C4eql0oDC0Qe0uVeG5d1ndPXPI6LOY48tJBTHgHvc Bc/A== X-Gm-Message-State: AOAM5327KRvoBiREg1589wcPGIez2KbEj8J/wekSXYUtKuUxhBzI9iLl lFCvRRS5ra35qEZq7kO+YqTucPllO9oMbQ== X-Received: by 2002:a63:f313:: with SMTP id l19mr7496427pgh.40.1634271278750; Thu, 14 Oct 2021 21:14:38 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 55/67] target/sparc: Remove DEBUG_UNALIGNED Date: Thu, 14 Oct 2021 21:10:41 -0700 Message-Id: <20211015041053.2769193-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The printf should have been qemu_log_mask, the parameters themselves no longer compile, and because this is placed before unwinding the PC is actively wrong. We get better (and correct) logging on the other side of raising the exception, in sparc_cpu_do_interrupt. Reviewed-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 9 --------- 1 file changed, 9 deletions(-) -- 2.25.1 diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index bbf3601cb1..0549b6adf1 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -27,7 +27,6 @@ //#define DEBUG_MMU //#define DEBUG_MXCC -//#define DEBUG_UNALIGNED //#define DEBUG_UNASSIGNED //#define DEBUG_ASI //#define DEBUG_CACHE_CONTROL @@ -364,10 +363,6 @@ static void do_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align, uintptr_t ra) { if (addr & align) { -#ifdef DEBUG_UNALIGNED - printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx - "\n", addr, env->pc); -#endif cpu_raise_exception_ra(env, TT_UNALIGNED, ra); } } @@ -1968,10 +1963,6 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; -#ifdef DEBUG_UNALIGNED - printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx - "\n", addr, env->pc); -#endif cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } #endif From patchwork Fri Oct 15 04:10:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515845 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp156533imi; Thu, 14 Oct 2021 21:57:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwJ2yfqNAJ2phTTMXErdVjJd1OcOgOsCR6IiKDIn4OYXJwbvLnWaKbRG83x5PiCe3h0N2AF X-Received: by 2002:a05:6e02:102d:: with SMTP id o13mr2361287ilj.239.1634273870404; Thu, 14 Oct 2021 21:57:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634273870; cv=none; d=google.com; s=arc-20160816; b=Ry2D/3RcVDIut+cKBHfw+hNyjAdAEPJJEv+adx6MklpLAFYG/9yfijyaSimEphI1wO ckXBfHJz9In81KGt8duFysE1JwHJgW2KH8w2UKMFVriXvHUyrxFgyAvCokWCrRflmoxO gKYgm6CwQpiokytDjcoXCYdWi6CdYdE11kEuUmYx3LQphl5KQrWUr1n8pzEszCt9gU84 QZuBz29YbAx3/s2wPRcQFH7+AjqLmWkH4p4uzcXVi9Mdvy3liUd7nJ8DMsVYeN7TV+R8 YNcDvj18uhFiFIyObsezTLyroxVE/pFMxkTzfNClxoJ3TgKQ/YKIRG/8d81h1Xssp/kn zFUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fVhlPoABQmS8wc89+ovGDAnkicIV2MZx6WAeJyRD9lM=; b=dx1KT4wsxbgpH1rkeRIVtPk652Laxh68aYNq9ZQKF0M3fOohU2HJoDGmjd9/JZZKee Vx5Ue/OEXvRFfBCOls/PPO//DgWQX8moB8Ek78USRMrWjEqSZOjdt/F/kI2lZuGWL4VX 90LreUV9edIkyR7haOe9JoOrG031cUR4fNWv2Vim5ISuxD6vHmR2BNcZfP2M3r+C3SKA zz4QaspWb5JOtWSV217uqGf5orG9YoXGWJ+X4IgI/zy8/rd4olPU5p9xmR5wh9CghtNk 5uy9hkaa+lj64Cmb/d6irpNwF1oDWqUgpKsSIRGSzZwv0KpcWsjGfynMAK5iRGm5Aiki a1Dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=qMqrOYwm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Thu, 14 Oct 2021 21:14:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 56/67] target/sparc: Split out build_sfsr Date: Thu, 14 Oct 2021 21:10:42 -0700 Message-Id: <20211015041053.2769193-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/mmu_helper.c | 72 +++++++++++++++++++++++++-------------- 1 file changed, 46 insertions(+), 26 deletions(-) -- 2.25.1 diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 2ad47391d0..014601e701 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -502,16 +502,60 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *tlb, return 0; } +static uint64_t build_sfsr(CPUSPARCState *env, int mmu_idx, int rw) +{ + uint64_t sfsr = SFSR_VALID_BIT; + + switch (mmu_idx) { + case MMU_PHYS_IDX: + sfsr |= SFSR_CT_NOTRANS; + break; + case MMU_USER_IDX: + case MMU_KERNEL_IDX: + sfsr |= SFSR_CT_PRIMARY; + break; + case MMU_USER_SECONDARY_IDX: + case MMU_KERNEL_SECONDARY_IDX: + sfsr |= SFSR_CT_SECONDARY; + break; + case MMU_NUCLEUS_IDX: + sfsr |= SFSR_CT_NUCLEUS; + break; + default: + g_assert_not_reached(); + } + + if (rw == 1) { + sfsr |= SFSR_WRITE_BIT; + } else if (rw == 4) { + sfsr |= SFSR_NF_BIT; + } + + if (env->pstate & PS_PRIV) { + sfsr |= SFSR_PR_BIT; + } + + if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */ + sfsr |= SFSR_OW_BIT; /* overflow (not read before another fault) */ + } + + /* FIXME: ASI field in SFSR must be set */ + + return sfsr; +} + static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, int *prot, MemTxAttrs *attrs, target_ulong address, int rw, int mmu_idx) { CPUState *cs = env_cpu(env); unsigned int i; + uint64_t sfsr; uint64_t context; - uint64_t sfsr = 0; bool is_user = false; + sfsr = build_sfsr(env, mmu_idx, rw); + switch (mmu_idx) { case MMU_PHYS_IDX: g_assert_not_reached(); @@ -520,29 +564,18 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, /* fallthru */ case MMU_KERNEL_IDX: context = env->dmmu.mmu_primary_context & 0x1fff; - sfsr |= SFSR_CT_PRIMARY; break; case MMU_USER_SECONDARY_IDX: is_user = true; /* fallthru */ case MMU_KERNEL_SECONDARY_IDX: context = env->dmmu.mmu_secondary_context & 0x1fff; - sfsr |= SFSR_CT_SECONDARY; break; - case MMU_NUCLEUS_IDX: - sfsr |= SFSR_CT_NUCLEUS; - /* FALLTHRU */ default: context = 0; break; } - if (rw == 1) { - sfsr |= SFSR_WRITE_BIT; - } else if (rw == 4) { - sfsr |= SFSR_NF_BIT; - } - for (i = 0; i < 64; i++) { /* ctx match, vaddr match, valid? */ if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) { @@ -592,22 +625,9 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, return 0; } - if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */ - sfsr |= SFSR_OW_BIT; /* overflow (not read before - another fault) */ - } - - if (env->pstate & PS_PRIV) { - sfsr |= SFSR_PR_BIT; - } - - /* FIXME: ASI field in SFSR must be set */ - env->dmmu.sfsr = sfsr | SFSR_VALID_BIT; - + env->dmmu.sfsr = sfsr; env->dmmu.sfar = address; /* Fault address register */ - env->dmmu.tag_access = (address & ~0x1fffULL) | context; - return 1; } } From patchwork Fri Oct 15 04:10:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515828 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp148936imi; Thu, 14 Oct 2021 21:43:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwkmx8BJ9g7KO9YiDFfqRmxBfhVU8q5vDn9LbrePDbkxdJcYnVURtRnMu5xfeBiznW163jY X-Received: by 2002:a25:e697:: with SMTP id d145mr10068023ybh.4.1634273011889; Thu, 14 Oct 2021 21:43:31 -0700 (PDT) ARC-Seal: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id y2si4915630ybg.51.2021.10.14.21.43.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:43:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=W4LeJ9a2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40262 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF47-000096-5E for patch@linaro.org; Fri, 15 Oct 2021 00:43:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39670) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcF-0006ub-95 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:45 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:37551) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcD-0002w2-KU for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:42 -0400 Received: by mail-pf1-x433.google.com with SMTP id q19so7313409pfl.4 for ; Thu, 14 Oct 2021 21:14:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=muffzeHX3yZuoAcxrWs0UhKgv9u/j8rmCNk7xQHU/Hc=; b=W4LeJ9a2EKradOZjo4wTuB8xqkNzf2KdkMde9V6GZwVepTf93PrFCJ7GPovl6AMirM midF8TuBN6hjPUiNdG1PF5HSd0HpGw8r2+F25/rLP/SiFkktHj7/RE5UY6VpA0iRVP05 mKwe+lvis30h42xwgbYNYrl+GO7EqM4hxg2Ad64jqliABa1Lbg594rNd1jMvZtKwB6fh 8DnywRUl/WMPkVvS8ZY5OP2ikhv1AesClKhjY5I/gkKd1K9DKIl8X79hgn5onURepMMP awkRuMvS6nEyNJ8TwhyBWjCgm3M1k4QzMAH2UrX7Nf6MMcwq3Ja7yv8WE6C9vIrdrkoj vYPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=muffzeHX3yZuoAcxrWs0UhKgv9u/j8rmCNk7xQHU/Hc=; b=j3Sm+Qtq+3xxFwZ8Ra7KMi7y1yktYJ2UTSp9XNhh+YVEKOE/UXMziGjEJKZopGbfPT RA0RKMdPpZBgyhYJUqCU3sP1bsr8OukfuLhhS8NdQ/5gD8eR64LpYlUy5dkzzLd88yTJ 6kRyjue59g7jAnk+ybgUSd3taafvIZrYl0tTgF9spTiNOI6heycFrfBlIfmX/4qicdqH HNUZq2/yf3a0MUkOszvGq4sgNjdKg/nmM62bO27LkmkuRoPA4THLWS2nq2ZCkP3cuq7B uuuUpdc9V9r68wO9wGwhcs4IHr2tqzqu4eAPs/NUwGNfh9jBpIpi3+QREr1Kh6H+jw2R h+yw== X-Gm-Message-State: AOAM531vOxn8ZVup055L4N7jCgZKAXONVYppO5Qg2P4pdHIAOWi86Xi5 It03T7PJzvg7o/WCZWgkXOl67NOMK64zkA== X-Received: by 2002:a65:6aa8:: with SMTP id x8mr7419834pgu.136.1634271280135; Thu, 14 Oct 2021 21:14:40 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 57/67] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Date: Thu, 14 Oct 2021 21:10:43 -0700 Message-Id: <20211015041053.2769193-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We ought to have been recording the virtual address for reporting to the guest trap handler. Move the function to mmu_helper.c, so that we can re-use code shared with get_physical_address_data. Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 13 ------------- target/sparc/mmu_helper.c | 20 ++++++++++++++++++++ 2 files changed, 20 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 0549b6adf1..a3e1cf9b6e 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1953,16 +1953,3 @@ void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, is_asi, size, retaddr); } #endif - -#if !defined(CONFIG_USER_ONLY) -void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, - uintptr_t retaddr) -{ - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - - cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); -} -#endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 014601e701..f2668389b0 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -922,3 +922,23 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } return phys_addr; } + +#ifndef CONFIG_USER_ONLY +void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, + uintptr_t retaddr) +{ + SPARCCPU *cpu = SPARC_CPU(cs); + CPUSPARCState *env = &cpu->env; + +#ifdef TARGET_SPARC64 + env->dmmu.sfsr = build_sfsr(env, mmu_idx, access_type); + env->dmmu.sfar = addr; +#else + env->mmuregs[4] = addr; +#endif + + cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); +} +#endif /* !CONFIG_USER_ONLY */ From patchwork Fri Oct 15 04:10:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515836 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp151795imi; Thu, 14 Oct 2021 21:48:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz2Xzg0AlMmY7B+Xtrbn+tti3pQ6fz6OiMZgKMC/lmiIrF5alKvY/xjeAvfRHXu/lIKOzcf X-Received: by 2002:a92:c54f:: with SMTP id a15mr2296223ilj.126.1634273325178; Thu, 14 Oct 2021 21:48:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634273325; cv=none; d=google.com; s=arc-20160816; b=nWFYLjfpKjTjcIZ1yt2dUrfPEH2Zbz32fHbCv+6MFsFLC0w7ZbGt+KhLFBfcs6AG1o bEvR0gM+wsp2FJ0PR7g5WKd66l90HvQf09fetvbLzqVM6QH8qI0kyFVw/6GMKplP9NpD WOT6CGZsG6/w5DIWQMtJPxPM+jVBdfVwi/e6moTXolJd5edF/e7G5Jrv88G3ZVEpAefa 1k3y9VzybyHkL9iOjEJyCjBubRWQAWoiqGMdBzbioPTuDChsRQDyQFUmlinN2pdZbBRw AHh0BFZdp8onVMqJRPZD8m5bPEQ3E1Ly98XzxMnHtH3Uls00tQZpgJ2faYebxQwn2Tss nuvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pdzh8Ws2GkGBVDH5ETDlAj3vOFqZvQW52CUEjET/TWY=; b=KVW4TZtKMI0WBvYyaADeeVXWk/HZSEGQ3yY0+OMHOyOpQ+mt8KY+AXOXahEMoHSVM1 +KHvFfRCJJzUPc28Y0QEmKo4IAXddckkvWFfLO21s0NcM2iJhS/DvvRHloT21VycFOYQ 34W61JyLkJunZtR65tLZYJVjh20j+9dT3BydhoYIwNRdUa0WULMHOucFx4pvPV9KDxcN Fq56RQ0yFYzN4Q0RBIQ6RJ3KG5Cs+EV5wJq6qsrPu+uYIo7J45m8rOMi3rutNa4nr4QO U2o03BLDLUN2aWlVa1+r7akow69YiC1+3DxGO/b2fL315sVpYXS7DGKI0GOgUumhI3/x uk7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CJCNLq7r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f44si5391104jaa.36.2021.10.14.21.48.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:48:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CJCNLq7r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56502 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF9A-0003AK-D0 for patch@linaro.org; Fri, 15 Oct 2021 00:48:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39710) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcI-0006yL-Es for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:47 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:33780) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcD-0002wS-W9 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:46 -0400 Received: by mail-pl1-x62e.google.com with SMTP id y4so5641229plb.0 for ; Thu, 14 Oct 2021 21:14:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pdzh8Ws2GkGBVDH5ETDlAj3vOFqZvQW52CUEjET/TWY=; b=CJCNLq7rj3AkfgcC6utiwUZqfc7wtb7dTqJ/NvvKces23Khe4OjVa6lQDM2OdBxNsp yZbGB1KpIwMxGJiyK7Ev5GtVKxDrJzX2W5PYUbM41t7qPwQ3UcxPbLQWYRNnfpryASZY /B+bmEjEe6eRWqvtzg/3JOgYdJD3tMjIHmIO9mCOTJJqF33m7Lt4Kg+ejvAXsKAiQUIj 9lVkYs+1MSN91/sMUCl/VjDVP1SDkuyAGIq3zdDEVkm9MxcKhhKQ9uCBGJEfHzGdKzC3 MZ1bmHWz4JVARFvVLc5l60WOuNxFZ12FKlXXJoaE4fHZFN4RrBNI8rLNe3cHnfvipQUJ P6ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pdzh8Ws2GkGBVDH5ETDlAj3vOFqZvQW52CUEjET/TWY=; b=F7sVfWgwjXO06CyjIXmpVLHiympjouTwNrWAuKBvQSmocZzVytfHt6KePDOva4mdgr xssNho6qLUpnd6J4GIsLi6eM8/5m+J+ULyPu/1s2fHeT65erJ+kQwxpCflmHuUGHJQOe sNwvyd5X0uAZnLcKR3YEkTX4eW2GI9bH4mTO8aqVnyWXCsBWV27xXzmEsNlYgjwlASgH DhgJ3s0XP9O8RhRHjq9rUvGgSKz5iQylm47wttXMXHe1KzVy5WurX8ChBvcL2A0FBRLD h2cnUA3VAid2lUlA5M55dQAsSpT/v3wbibOAqv14xVQRk00PUZ3DHSkW+zET9C8wCouF BshA== X-Gm-Message-State: AOAM531tnKl4dZoVutRPW1cfWEmCLRJvlZXLoE0VQM6PyThLNkHBozno p8Zc2BGnDcfo8LkOAEsdzMkWcAoMAZpZMQ== X-Received: by 2002:a17:90a:7345:: with SMTP id j5mr25397984pjs.48.1634271280785; Thu, 14 Oct 2021 21:14:40 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 58/67] accel/tcg: Report unaligned atomics for user-only Date: Thu, 14 Oct 2021 21:10:44 -0700 Message-Id: <20211015041053.2769193-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the new cpu_loop_exit_sigbus for atomic_mmu_lookup, which has access to complete alignment info from the TCGMemOpIdx arg. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) -- 2.25.1 Reviewed-by: Warner Losh Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5646f8e527..92cbffd7c6 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -476,11 +476,22 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, int size, int prot, uintptr_t retaddr) { + MemOp mop = get_memop(oi); + int a_bits = get_alignment_bits(mop); + void *ret; + + /* Enforce guest required alignment. */ + if (unlikely(addr & ((1 << a_bits) - 1))) { + MMUAccessType t = prot == PAGE_READ ? MMU_DATA_LOAD : MMU_DATA_STORE; + cpu_loop_exit_sigbus(env_cpu(env), addr, t, retaddr); + } + /* Enforce qemu required alignment. */ if (unlikely(addr & (size - 1))) { cpu_loop_exit_atomic(env_cpu(env), retaddr); } - void *ret = g2h(env_cpu(env), addr); + + ret = g2h(env_cpu(env), addr); set_helper_retaddr(retaddr); return ret; } From patchwork Fri Oct 15 04:10:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515834 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp151380imi; Thu, 14 Oct 2021 21:47:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz2x1Alk23wCXkjT9TaRV+SQH3ZwjLstU7K3F6G5aw//iLfibZistLed4nryNh4dCTKRwUA X-Received: by 2002:a5d:9d82:: with SMTP id ay2mr2268644iob.128.1634273278394; Thu, 14 Oct 2021 21:47:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634273278; cv=none; d=google.com; s=arc-20160816; b=ZKVm08AwmW/WSD/EB8SwLSKHWTsf9xBrwkyU1SG9La3+xvbiZltC1ilIECPRE5lqSw QHsKnax3RyyT5H890lIsU7Jr364JTZqFaFJIgwd8/gESObqry5/FgrTEUH4FFifBqGpm Jww9rFpoRwgKk45atpeZkfQRcUtCPBd/7UqQmcEOXxpyXM/ogwDq1TecQCjuhUBqf4FJ EfKyuuaHTLDkSMlZni1qSFZXbP/t3gSAHiEe2WEJG/rZmM/7/C+T/rxXJyNYHas6EIxR ZEsqTv0XtQOMTCYklpO3iZ1atirOvANa9efkypKk71cOv7dAZMi5jmPoozaxt0U7jVZx GDxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VGqZOPjwuoviGfiS5SB/EShJZs+j0SuqFPzdROiPbhU=; b=g9RWNAMeDPRT5SnZ/4ZrDZ8fq0AdYKyLZzXuFM1FgYMFzDwK3Ex3eVhR5JUuRmGLST OvK1fia/X2TF9K2LW57/smXzjztQA5U/6b/kv4KfTJu+hGTit3aGW0vJmy4kCpiKbhaE vAk2/O1iPdye2RLMHLxfT/Hs0heI/1t6JQQBv9CUEVhD34dV9xrl3Qu92ADwodBI+03p uMZiuxnzvrZ36V/h27uOyB3JS8g/8nBxMCau15UW4p0xHaP4GwXc7VAHvT6nYYIkPmyK IpOL0qPu2cvzSmjhxCplN9jp9mK6Bv3dBjznjvXR43hlM/F0f8cRU/gpCZ52it9kki0U RIuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bHyCnYFA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d8si8694179jak.53.2021.10.14.21.47.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:47:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bHyCnYFA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53352 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF8P-00011s-KG for patch@linaro.org; Fri, 15 Oct 2021 00:47:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39708) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcI-0006yK-C9 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:47 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:37684) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcE-0002xM-SJ for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:45 -0400 Received: by mail-pl1-x62d.google.com with SMTP id n11so5612973plf.4 for ; Thu, 14 Oct 2021 21:14:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VGqZOPjwuoviGfiS5SB/EShJZs+j0SuqFPzdROiPbhU=; b=bHyCnYFAxOJGBUQhByKTz2G+C+TKM1+9Twr4BQ50SSIdgcpIQVvnNjjNizrhi9vHUX No1gRmsFkRLfVOMn/hUltUj+RX82BMudTBQXRIIjUupe/C0UBvBr+TTgVP4ewFOBTZyg BT4F60+TMaMBQUrt8u5fb+VwATekXE6rLfmm58c5X4fD5ACGtdkL/Gh/3gergKeo61EP qNvWotd3fgjdcXb0CuIBTcG7R5w6zGyGkzbiDYRXRSzF0NuJm8sU6Rd1aGKAXY59MbUz h8MMGs6ANt1k9Ofb6Ovu3Bs7N+lKvYCaUsoHHhnimtkpT9tScRKHapzFggTkEB0W1sxz 7lHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VGqZOPjwuoviGfiS5SB/EShJZs+j0SuqFPzdROiPbhU=; b=uE33lICWkEKYzRDqNeO8geEli/xWeMmC2HKmccHcg/OxMzD3/atwBTAI5ZNsY76FCj 8CO+ObbNVPF7ndK8fhh6fE1EmHuIWNGqnokEACGcqem2y0SxG9z68IZ70CqeKNglNSoJ LFKZKXKk1Ik7QpEaiVDMerv1hjQ1rdCvoY7+zoRxnR5EMEtmOmTvCzhXe+HC+fbvXVJ1 NtUTQT8hs26ApIjObgBD48bbaoLKerHnAdKofAbZoZs3KSVi7mufvouOtzJ1NpYMLsgC jVhQX3ypFJ1p5vY+dU+o3+rI1TTMufcEkixKQuNzkzTqJ4e4M7+UJeGFrmBNqw30jFEb wjDQ== X-Gm-Message-State: AOAM532xUc1xipTTHxxFBzsBV3u9xHQENX4qHFcEBnkEfLQc4sTEUmly s0KbObc4k9M1VQwV6z4SLaCzkGclA6HhAQ== X-Received: by 2002:a17:90a:ac0a:: with SMTP id o10mr24726301pjq.125.1634271281599; Thu, 14 Oct 2021 21:14:41 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 59/67] accel/tcg: Report unaligned load/store for user-only Date: Thu, 14 Oct 2021 21:10:45 -0700 Message-Id: <20211015041053.2769193-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the new cpu_loop_exit_sigbus for cpu_mmu_lookup. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.25.1 Reviewed-by: Warner Losh Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 92cbffd7c6..7d50dd54f6 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -220,9 +220,14 @@ static void validate_memop(MemOpIdx oi, MemOp expected) static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t ra, MMUAccessType type) { + MemOp mop = get_memop(oi); + int a_bits = get_alignment_bits(mop); void *ret; - /* TODO: Enforce guest required alignment. */ + /* Enforce guest required alignment. */ + if (unlikely(addr & ((1 << a_bits) - 1))) { + cpu_loop_exit_sigbus(env_cpu(env), addr, type, ra); + } ret = g2h(env_cpu(env), addr); set_helper_retaddr(ra); From patchwork Fri Oct 15 04:10:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515832 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp150685imi; Thu, 14 Oct 2021 21:46:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwq8QSaokF2kkDATHlUJSbAPFe3GbhHucmiL7yf7HdVS5QtiHv6hxd0u5cydklEce/gtFdx X-Received: by 2002:a25:1ac6:: with SMTP id a189mr10604801yba.149.1634273200262; Thu, 14 Oct 2021 21:46:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634273200; cv=none; d=google.com; s=arc-20160816; b=AhB8jwwmL+yFZYGJ4s0dilPsbCHmgsQZ0H13SwEURjp44VFpLq/XqeGX192qUY0N7Y l2A/f0apa6s0uW722BWUUtBowmDctBH23Jsca7JOfwexBVr1gxvI4VVcccsMsvM8HEj0 AGY3Zqpegp5Dvbe5u1Obugo5x9r55cEseZ40llrHSRmq7eWTftHu8pDFWYLN6OTb9Qyy MDhsQg00BV6A/f6HSJgGW7h1AO2ztSLf5BV6SagqhGCk0xW35Es0pGYnxRxamYtOKAgZ y1CiapHSDy2BEj2cntBOyle7viSqRR0LXBXGMsFmnbXYPTgPHzxf5FNlDQChrTxHecRj MX1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jfz53S3QlKXNPBsRIkUXBiTrLPBdQUAc4SLrCyr0OTo=; b=cjidzRj2paWMPV6so/4JFaf3ZQqhT/IL7UTd6xG0JV9/i52vxP2knBzJdDPpZ4xijj 1VwPB0QdAFyh0UiMbUVEM5/C4dMzkxhfLkf+ZTyi7rlkyUvnLnU6Lu9mE0zgPcc6bfkM 7lkmuFKyUnH1P/E3KdbUEoTcfbnsR34OC4mXs3StncEVWEAPsBAdtRLnS3zX8d3whPrl ks4v3EboUWag+OccVTGxPmviXXpl0meXCCSvuZK6ncMJ7U8HmGIgVxILkhGq9GUog7mI FmdQ0oDdHn77tKhYtu4jOXLlShh6KAQuxtMZPcEO69g1grmi2/B/aARvGKTWDhLoVVXU Vh9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=A0yhjLY4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 5 +++++ accel/tcg/user-exec.c | 11 +++++++++++ 2 files changed, 16 insertions(+) -- 2.25.1 Reviewed-by: Warner Losh Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index 8c86365611..bf40942de4 100644 --- a/include/tcg/tcg-ldst.h +++ b/include/tcg/tcg-ldst.h @@ -70,5 +70,10 @@ void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr); +#else + +void QEMU_NORETURN helper_unaligned_ld(CPUArchState *env, target_ulong addr); +void QEMU_NORETURN helper_unaligned_st(CPUArchState *env, target_ulong addr); + #endif /* CONFIG_SOFTMMU */ #endif /* TCG_LDST_H */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 7d50dd54f6..0473ead5ab 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -27,6 +27,7 @@ #include "exec/helper-proto.h" #include "qemu/atomic128.h" #include "trace/trace-root.h" +#include "tcg/tcg-ldst.h" #include "internal.h" __thread uintptr_t helper_retaddr; @@ -217,6 +218,16 @@ static void validate_memop(MemOpIdx oi, MemOp expected) #endif } +void helper_unaligned_ld(CPUArchState *env, target_ulong addr) +{ + cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_LOAD, GETPC()); +} + +void helper_unaligned_st(CPUArchState *env, target_ulong addr) +{ + cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_STORE, GETPC()); +} + static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t ra, MMUAccessType type) { From patchwork Fri Oct 15 04:10:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515839 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp152841imi; Thu, 14 Oct 2021 21:50:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw1NVKnTMyxxjb58AiisD3b6EqvFvnjt9b5XYW6nDzVzE9IzlYniJSLbsggV3WlIxGq4stU X-Received: by 2002:a92:c261:: with SMTP id h1mr2287171ild.284.1634273459288; Thu, 14 Oct 2021 21:50:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634273459; cv=none; d=google.com; s=arc-20160816; b=TI5eKYR2aWq4XH72RxAaBIqcoS1THGtI2f7oiKgBo+jER+nOEUPvl3MUxXmVT2ehfM wgDaozjc9AqGAHsaBTUZg+abrldxmW6J6svbru9/62yhyocnDjEidNkgVzrVHVmQPO61 ZVTaIPOR/Dr3mHQyF/RfLLvzvltMqi/o6xTEqUtRLt9Y2tqQksS8YWiRoF8hq59KBf76 R72RXQHC3cKKS4LNTkWK1BVOVFzBthBJCTrB4ZVlhjyiSOD+uhLiwcXAsL8XZ1QfsvE7 8K+UWolyy6hLsTzo55oaoYmvVchUNYoGf4ToYMN+EHeBDkk/Lf6siUuBDTTpOvgrXoih 4BsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9im4CvhbPoyQ1RG+uvEuwMG0n0qsYjZQphEGRSBJSzY=; b=vABft32C45SWqPciIyNEiJgbqnhjCu5V8E46s63CcF1/jOn6hUwF+0y5JRBllHpqDd 4AmuNMvRj+b3tEDW3hG1oNauBsThixVgixYbLpKMLpJDHewIoB6xE8/mbCuct9Mz4rLg Y9ee8nqJ0H1waNwi3D+wuY+HVT6Y9gyL+nJGjEvlpJR44vrQTTm/HPVE0gUC+f0jEA2j kBkO2NX5EJs9VeiGlkWM5MnkStTOVtMHXc7SM051zSwduPrFWvN4AJ1Gaq7uAqjA0F58 fD4wc2lMi8kKVgeJCuCD1juntrofyknpQmk+uDEB3ggvLir1uB/Ta1/wBb6Bm/f84VIh uBaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EThQgfXV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p16si9744012iov.22.2021.10.14.21.50.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:50:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EThQgfXV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36430 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbFBK-0000Ib-Io for patch@linaro.org; Fri, 15 Oct 2021 00:50:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39754) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcJ-00070N-Nj for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:49 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:34744) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcH-0002yj-6s for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:47 -0400 Received: by mail-pj1-x102a.google.com with SMTP id q2-20020a17090a2e0200b001a0fd4efd49so2155715pjd.1 for ; Thu, 14 Oct 2021 21:14:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9im4CvhbPoyQ1RG+uvEuwMG0n0qsYjZQphEGRSBJSzY=; b=EThQgfXVM3+gTYBP9riZDdoy7+261/jK33Yl47MmSU3iZ5wuNAQhHQ1LyE8ousV8iH 1AjrG+9rCqBtcryjB1w0B3O6wHWejaW2rlvS0pKjP8jr/WtTvMkugxPr3sADthjBjCls B4ylcrg9BnnlXZyZyvOQ4ZuWnlsZD866jOv1Y0T4cIjsvQqpTfDpz1WlDaN6GO1QKQTl uG+4Xh+32n+YeUZzBDfzEruvVQrqnrnCVEgay2gso4Udk86qLTQCkQj3yvbx1W5MoLbX +3ru5fDt7DSamH5Dv/fbh3xeIkL1nGYBROkdt0DdZULC1rI4TjQ67w5USrW/awd7kEHA iTsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9im4CvhbPoyQ1RG+uvEuwMG0n0qsYjZQphEGRSBJSzY=; b=JTPMjfef1fVec1BRQ+Ts+J3knvehYXY6rgpYnY1V6n47PgLlKmV5gh7ArkyaUH+E5V jqUnXv643pNih2ywG8YNmfRcovP5DcLUaPAAtU9S8dOREzLcSLPj4jZrUY4hnEqPVLzK 87XfDUwpbu185/3Yu+u5N66ERSYYtffZpLBsQ6b+k9zL9qWqH0Jn0fy7LMIRJdO5iayu be78/E/FhxBhHbQquoT4jj3egUnXAe5ryc2E1YA26r/yLTNTzp2RLiIg6S0arVZFyuVV AwcQH9uiu1N4b7lEhnpSEccaD/oNM3tzK1rHluUpKQnPe/jb2eqJbosWA0X4V+IrOa/2 lLUQ== X-Gm-Message-State: AOAM531lmD+tS54dJsEk7mmuNbydDx1TuIZyfF6YietG7oNCIMUXM/FX peWzqG7Ns3LiOkf43VTjCpbcPM1DWTrnog== X-Received: by 2002:a17:90a:1507:: with SMTP id l7mr10750149pja.141.1634271282818; Thu, 14 Oct 2021 21:14:42 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 61/67] linux-user: Handle BUS_ADRALN in host_signal_handler Date: Thu, 14 Oct 2021 21:10:47 -0700 Message-Id: <20211015041053.2769193-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Handle BUS_ADRALN via cpu_loop_exit_sigbus, but allow other SIGBUS si_codes to continue into the host-to-guest signal coversion code. Signed-off-by: Richard Henderson --- linux-user/signal.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/linux-user/signal.c b/linux-user/signal.c index df2c8678d0..81c45bfce9 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -860,6 +860,9 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) cpu_loop_exit_sigsegv(cpu, guest_addr, access_type, maperr, pc); } else { sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + if (info->si_code == BUS_ADRALN) { + cpu_loop_exit_sigbus(cpu, guest_addr, access_type, pc); + } } sync_sig = true; From patchwork Fri Oct 15 04:10:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515846 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp157564imi; Thu, 14 Oct 2021 22:00:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyH9cDu2FZDOE7QngEbqCv3sj2sssJ6c83eO5V97oOMFBqKPgUgQoUrvmX7IKVpR2udDh+N X-Received: by 2002:a6b:c886:: with SMTP id y128mr2264126iof.213.1634274009364; Thu, 14 Oct 2021 22:00:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634274009; cv=none; d=google.com; s=arc-20160816; b=m6RA0TsfGS43jVGGpzfJH/Tg1EpTC9/+3mYwNPJ3JgTkvUcFHhZl5HHzn6l1SiwvZh MJ9z99j9Udohv3JzcqCO3cwx+L2BGNWeEQaKg0ZGrZwvL5ncua+aFpRU87j1ba2IN4qa pVBoODOaSBAGVrNLi73xzkJKfqD9pau/cBM73/5iKLeR8IlF8QIzeO9L3SSbPNgxMJYX ScvbNMqYZ2jhbLhhnOarMp6B1VxicoI91JWq73PKLWJy0uLRXzdxFpOGKF5dD+bAFO/2 zoN9qpdprLIxPDb9oLc2AfQtghnEX2eml2jNcvE7vjHu3sGzF4FsUJPTuQKHHyuUbTOE BzjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mnqEEgywou2/cA2oB9Is2HfT4xL6ufMEEmIOEI3fkHA=; b=hMWGBNTxibb5ZfTWfY7s9Lh/Bd0zcFNw6+2jPfbQBc2f5yyyPSFvCCydQYQwIqXTK9 Bvf7iVPEfehi7WvcYMT/dtMPG7R0/DcKDbNltbk/TA+knv4TLBe78Vj4mrkhVbXBrmxv NFveH1veSC9vAJimMgIunyxvu1XdA18ht645k8GB5MpDxR/dIGRdxSv06jOtViwwiVV8 utV3KFJY248aKk7FcjOQike/N7o4dmhXDCjyPFHM7nN7tVoH/gMPXIGsgXd6jD+d+p0e SE0F5URrqgizNd/NV2rbvMJp/7b4oAnn2/gT5WJguwk+P/+7HPHlkcc7WlqgfxOJUEp6 r62A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rOXSZWqb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l26si6526333iol.87.2021.10.14.22.00.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 22:00:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rOXSZWqb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57242 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbFKC-0005wO-Dd for patch@linaro.org; Fri, 15 Oct 2021 01:00:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcN-00077S-TY for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:52 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:51043) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcH-0002zo-5h for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:51 -0400 Received: by mail-pj1-x102b.google.com with SMTP id gn3so811314pjb.0 for ; Thu, 14 Oct 2021 21:14:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mnqEEgywou2/cA2oB9Is2HfT4xL6ufMEEmIOEI3fkHA=; b=rOXSZWqbdk+BM7eSytOFj5w9whUkaOULo5cQIcz395fdhbcpNl4tU5rEA4laPsLvT0 NIVRgxeHU1EkB3RG/iE7F0q6LWioG3flXOIIde95ZSpOZGg9/V5whOhWanf6cGMHy1to G1rNtp7T2MHUUinvD7T/TL3j0iqmaPdqL3FROWp1FgRaqn9zTJkSOBZBGyoipSitz9ev CDIps/TiENbbpei0lqVSjAVlWyKCZKFs4d35vwicMr/JHMWVkegqFwMvGJksgKAqPko4 reIUSNY0CkYn2ANWRos6wMHiRV+2GnLQT7M1tOFn6PZBN6qImGNG79yhwyQ8A3smb/b0 UTrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mnqEEgywou2/cA2oB9Is2HfT4xL6ufMEEmIOEI3fkHA=; b=ubZcnPCQMg5vKWlOvAqNxbkDG/Gm9FFyJxneC7t48EXt6ylutoYwJm0tRBb/hX5sGR zr1nOOjbQ0UBnaFRtVNmuA6A7yC5tweqZqe5dw4LY5LbAouvBvtZdaEasiN3R7J1O7lM kKfvNIjnLh8Uov14OLV2athl81Dvq9bUGgF25mdEDpj/mFjTvwOWdy60/xh8SNIGPDho B3xmMSt93HJ7mlHMXG1l4idk7i74VWNK3vOz8EXz+KqQ5Gw7iVoBJNkOG3d9uRmx0mBY Zba89BhS41OsPgYvvdA/D9FmEUSbn6ESXMSjmP4CBye7J33FlSGalgGcS3DLNVJ/S37v LL9Q== X-Gm-Message-State: AOAM530fOTRwTkU6aI6csmh33S9cXM0uDiHKo0/OpXDjoWkMFFMY3dFc nVvo9xiNVNTM4otAfUuARnPpvgfs6BS4/w== X-Received: by 2002:a17:90a:e7c8:: with SMTP id kb8mr10708596pjb.95.1634271283741; Thu, 14 Oct 2021 21:14:43 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 62/67] linux-user: Split out do_prctl and subroutines Date: Thu, 14 Oct 2021 21:10:48 -0700 Message-Id: <20211015041053.2769193-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since the prctl constants are supposed to be generic, supply any that are not provided by the host. Split out subroutines for PR_GET_FP_MODE, PR_SET_FP_MODE, PR_GET_VL, PR_SET_VL, PR_RESET_KEYS, PR_SET_TAGGED_ADDR_CTRL, PR_GET_TAGGED_ADDR_CTRL. Return EINVAL for guests that do not support these options rather than pass them on to the host. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 160 ++++++++++ linux-user/aarch64/target_syscall.h | 23 -- linux-user/alpha/target_prctl.h | 1 + linux-user/arm/target_prctl.h | 1 + linux-user/cris/target_prctl.h | 1 + linux-user/hexagon/target_prctl.h | 1 + linux-user/hppa/target_prctl.h | 1 + linux-user/i386/target_prctl.h | 1 + linux-user/m68k/target_prctl.h | 1 + linux-user/microblaze/target_prctl.h | 1 + linux-user/mips/target_prctl.h | 88 ++++++ linux-user/mips/target_syscall.h | 6 - linux-user/mips64/target_prctl.h | 1 + linux-user/mips64/target_syscall.h | 6 - linux-user/nios2/target_prctl.h | 1 + linux-user/openrisc/target_prctl.h | 1 + linux-user/ppc/target_prctl.h | 1 + linux-user/riscv/target_prctl.h | 1 + linux-user/s390x/target_prctl.h | 1 + linux-user/sh4/target_prctl.h | 1 + linux-user/sparc/target_prctl.h | 1 + linux-user/x86_64/target_prctl.h | 1 + linux-user/xtensa/target_prctl.h | 1 + linux-user/syscall.c | 433 +++++++++------------------ 24 files changed, 414 insertions(+), 320 deletions(-) create mode 100644 linux-user/aarch64/target_prctl.h create mode 100644 linux-user/alpha/target_prctl.h create mode 100644 linux-user/arm/target_prctl.h create mode 100644 linux-user/cris/target_prctl.h create mode 100644 linux-user/hexagon/target_prctl.h create mode 100644 linux-user/hppa/target_prctl.h create mode 100644 linux-user/i386/target_prctl.h create mode 100644 linux-user/m68k/target_prctl.h create mode 100644 linux-user/microblaze/target_prctl.h create mode 100644 linux-user/mips/target_prctl.h create mode 100644 linux-user/mips64/target_prctl.h create mode 100644 linux-user/nios2/target_prctl.h create mode 100644 linux-user/openrisc/target_prctl.h create mode 100644 linux-user/ppc/target_prctl.h create mode 100644 linux-user/riscv/target_prctl.h create mode 100644 linux-user/s390x/target_prctl.h create mode 100644 linux-user/sh4/target_prctl.h create mode 100644 linux-user/sparc/target_prctl.h create mode 100644 linux-user/x86_64/target_prctl.h create mode 100644 linux-user/xtensa/target_prctl.h -- 2.25.1 diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h new file mode 100644 index 0000000000..3f5a5d3933 --- /dev/null +++ b/linux-user/aarch64/target_prctl.h @@ -0,0 +1,160 @@ +/* + * AArch64 specific prctl functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef AARCH64_TARGET_PRCTL_H +#define AARCH64_TARGET_PRCTL_H + +static abi_long do_prctl_get_vl(CPUArchState *env) +{ + ARMCPU *cpu = env_archcpu(env); + if (cpu_isar_feature(aa64_sve, cpu)) { + return ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_get_vl do_prctl_get_vl + +static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2) +{ + /* + * We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT. + * Note the kernel definition of sve_vl_valid allows for VQ=512, + * i.e. VL=8192, even though the current architectural maximum is VQ=16. + */ + if (cpu_isar_feature(aa64_sve, env_archcpu(env)) + && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { + ARMCPU *cpu = env_archcpu(env); + uint32_t vq, old_vq; + + old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; + vq = MAX(arg2 / 16, 1); + vq = MIN(vq, cpu->sve_max_vq); + + if (vq < old_vq) { + aarch64_sve_narrow_vq(env, vq); + } + env->vfp.zcr_el[1] = vq - 1; + arm_rebuild_hflags(env); + return vq * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_set_vl do_prctl_set_vl + +static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) +{ + ARMCPU *cpu = env_archcpu(env); + + if (cpu_isar_feature(aa64_pauth, cpu)) { + int all = (PR_PAC_APIAKEY | PR_PAC_APIBKEY | + PR_PAC_APDAKEY | PR_PAC_APDBKEY | PR_PAC_APGAKEY); + int ret = 0; + Error *err = NULL; + + if (arg2 == 0) { + arg2 = all; + } else if (arg2 & ~all) { + return -TARGET_EINVAL; + } + if (arg2 & PR_PAC_APIAKEY) { + ret |= qemu_guest_getrandom(&env->keys.apia, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APIBKEY) { + ret |= qemu_guest_getrandom(&env->keys.apib, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APDAKEY) { + ret |= qemu_guest_getrandom(&env->keys.apda, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APDBKEY) { + ret |= qemu_guest_getrandom(&env->keys.apdb, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APGAKEY) { + ret |= qemu_guest_getrandom(&env->keys.apga, + sizeof(ARMPACKey), &err); + } + if (ret != 0) { + /* + * Some unknown failure in the crypto. The best + * we can do is log it and fail the syscall. + * The real syscall cannot fail this way. + */ + qemu_log_mask(LOG_UNIMP, "PR_PAC_RESET_KEYS: Crypto failure: %s", + error_get_pretty(err)); + error_free(err); + return -TARGET_EIO; + } + return 0; + } + return -TARGET_EINVAL; +} +#define do_prctl_reset_keys do_prctl_reset_keys + +static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2) +{ + abi_ulong valid_mask = PR_TAGGED_ADDR_ENABLE; + ARMCPU *cpu = env_archcpu(env); + + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |= PR_MTE_TCF_MASK; + valid_mask |= PR_MTE_TAG_MASK; + } + + if (arg2 & ~valid_mask) { + return -TARGET_EINVAL; + } + env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE; + + if (cpu_isar_feature(aa64_mte, cpu)) { + switch (arg2 & PR_MTE_TCF_MASK) { + case PR_MTE_TCF_NONE: + case PR_MTE_TCF_SYNC: + case PR_MTE_TCF_ASYNC: + break; + default: + return -EINVAL; + } + + /* + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. + * Note that the syscall values are consistent with hw. + */ + env->cp15.sctlr_el[1] = + deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT); + + /* + * Write PR_MTE_TAG to GCR_EL1[Exclude]. + * Note that the syscall uses an include mask, + * and hardware uses an exclude mask -- invert. + */ + env->cp15.gcr_el1 = + deposit64(env->cp15.gcr_el1, 0, 16, ~arg2 >> PR_MTE_TAG_SHIFT); + arm_rebuild_hflags(env); + } + return 0; +} +#define do_prctl_set_tagged_addr_ctrl do_prctl_set_tagged_addr_ctrl + +static abi_long do_prctl_get_tagged_addr_ctrl(CPUArchState *env) +{ + ARMCPU *cpu = env_archcpu(env); + abi_long ret = 0; + + if (env->tagged_addr_enable) { + ret |= PR_TAGGED_ADDR_ENABLE; + } + if (cpu_isar_feature(aa64_mte, cpu)) { + /* See do_prctl_set_tagged_addr_ctrl. */ + ret |= extract64(env->cp15.sctlr_el[1], 38, 2) << PR_MTE_TCF_SHIFT; + ret = deposit64(ret, PR_MTE_TAG_SHIFT, 16, ~env->cp15.gcr_el1); + } + return ret; +} +#define do_prctl_get_tagged_addr_ctrl do_prctl_get_tagged_addr_ctrl + +#endif /* AARCH64_TARGET_PRCTL_H */ diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h index 76f6c3391d..819f112ab0 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -20,27 +20,4 @@ struct target_pt_regs { #define TARGET_MCL_FUTURE 2 #define TARGET_MCL_ONFAULT 4 -#define TARGET_PR_SVE_SET_VL 50 -#define TARGET_PR_SVE_GET_VL 51 - -#define TARGET_PR_PAC_RESET_KEYS 54 -# define TARGET_PR_PAC_APIAKEY (1 << 0) -# define TARGET_PR_PAC_APIBKEY (1 << 1) -# define TARGET_PR_PAC_APDAKEY (1 << 2) -# define TARGET_PR_PAC_APDBKEY (1 << 3) -# define TARGET_PR_PAC_APGAKEY (1 << 4) - -#define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 -#define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 -# define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) -/* MTE tag check fault modes */ -# define TARGET_PR_MTE_TCF_SHIFT 1 -# define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT) -/* MTE tag inclusion mask */ -# define TARGET_PR_MTE_TAG_SHIFT 3 -# define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIFT) - #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/alpha/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/arm/target_prctl.h b/linux-user/arm/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/arm/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/cris/target_prctl.h b/linux-user/cris/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/cris/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/hexagon/target_prctl.h b/linux-user/hexagon/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/hexagon/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/hppa/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/i386/target_prctl.h b/linux-user/i386/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/i386/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/m68k/target_prctl.h b/linux-user/m68k/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/m68k/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/microblaze/target_prctl.h b/linux-user/microblaze/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/microblaze/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/mips/target_prctl.h b/linux-user/mips/target_prctl.h new file mode 100644 index 0000000000..e028333db9 --- /dev/null +++ b/linux-user/mips/target_prctl.h @@ -0,0 +1,88 @@ +/* + * MIPS specific prctl functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef MIPS_TARGET_PRCTL_H +#define MIPS_TARGET_PRCTL_H + +static abi_long do_prctl_get_fp_mode(CPUArchState *env) +{ + abi_long ret = 0; + + if (env->CP0_Status & (1 << CP0St_FR)) { + ret |= PR_FP_MODE_FR; + } + if (env->CP0_Config5 & (1 << CP0C5_FRE)) { + ret |= PR_FP_MODE_FRE; + } + return ret; +} +#define do_prctl_get_fp_mode do_prctl_get_fp_mode + +static abi_long do_prctl_set_fp_mode(CPUArchState *env, abi_long arg2) +{ + bool old_fr = env->CP0_Status & (1 << CP0St_FR); + bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE); + bool new_fr = arg2 & PR_FP_MODE_FR; + bool new_fre = arg2 & PR_FP_MODE_FRE; + const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE; + + /* If nothing to change, return right away, successfully. */ + if (old_fr == new_fr && old_fre == new_fre) { + return 0; + } + /* Check the value is valid */ + if (arg2 & ~known_bits) { + return -TARGET_EOPNOTSUPP; + } + /* Setting FRE without FR is not supported. */ + if (new_fre && !new_fr) { + return -TARGET_EOPNOTSUPP; + } + if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) { + /* FR1 is not supported */ + return -TARGET_EOPNOTSUPP; + } + if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64)) + && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { + /* cannot set FR=0 */ + return -TARGET_EOPNOTSUPP; + } + if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) { + /* Cannot set FRE=1 */ + return -TARGET_EOPNOTSUPP; + } + + int i; + fpr_t *fpr = env->active_fpu.fpr; + for (i = 0; i < 32 ; i += 2) { + if (!old_fr && new_fr) { + fpr[i].w[!FP_ENDIAN_IDX] = fpr[i + 1].w[FP_ENDIAN_IDX]; + } else if (old_fr && !new_fr) { + fpr[i + 1].w[FP_ENDIAN_IDX] = fpr[i].w[!FP_ENDIAN_IDX]; + } + } + + if (new_fr) { + env->CP0_Status |= (1 << CP0St_FR); + env->hflags |= MIPS_HFLAG_F64; + } else { + env->CP0_Status &= ~(1 << CP0St_FR); + env->hflags &= ~MIPS_HFLAG_F64; + } + if (new_fre) { + env->CP0_Config5 |= (1 << CP0C5_FRE); + if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { + env->hflags |= MIPS_HFLAG_FRE; + } + } else { + env->CP0_Config5 &= ~(1 << CP0C5_FRE); + env->hflags &= ~MIPS_HFLAG_FRE; + } + + return 0; +} +#define do_prctl_set_fp_mode do_prctl_set_fp_mode + +#endif /* MIPS_TARGET_PRCTL_H */ diff --git a/linux-user/mips/target_syscall.h b/linux-user/mips/target_syscall.h index f59057493a..1ce0a5bbf4 100644 --- a/linux-user/mips/target_syscall.h +++ b/linux-user/mips/target_syscall.h @@ -36,10 +36,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env) return 0x40000; } -/* MIPS-specific prctl() options */ -#define TARGET_PR_SET_FP_MODE 45 -#define TARGET_PR_GET_FP_MODE 46 -#define TARGET_PR_FP_MODE_FR (1 << 0) -#define TARGET_PR_FP_MODE_FRE (1 << 1) - #endif /* MIPS_TARGET_SYSCALL_H */ diff --git a/linux-user/mips64/target_prctl.h b/linux-user/mips64/target_prctl.h new file mode 100644 index 0000000000..18da9ae619 --- /dev/null +++ b/linux-user/mips64/target_prctl.h @@ -0,0 +1 @@ +#include "../mips/target_prctl.h" diff --git a/linux-user/mips64/target_syscall.h b/linux-user/mips64/target_syscall.h index cd1e1b4969..74f12365bc 100644 --- a/linux-user/mips64/target_syscall.h +++ b/linux-user/mips64/target_syscall.h @@ -33,10 +33,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env) return 0x40000; } -/* MIPS-specific prctl() options */ -#define TARGET_PR_SET_FP_MODE 45 -#define TARGET_PR_GET_FP_MODE 46 -#define TARGET_PR_FP_MODE_FR (1 << 0) -#define TARGET_PR_FP_MODE_FRE (1 << 1) - #endif /* MIPS64_TARGET_SYSCALL_H */ diff --git a/linux-user/nios2/target_prctl.h b/linux-user/nios2/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/nios2/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/openrisc/target_prctl.h b/linux-user/openrisc/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/openrisc/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/ppc/target_prctl.h b/linux-user/ppc/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/ppc/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/riscv/target_prctl.h b/linux-user/riscv/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/riscv/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/s390x/target_prctl.h b/linux-user/s390x/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/s390x/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/sh4/target_prctl.h b/linux-user/sh4/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/sh4/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/sparc/target_prctl.h b/linux-user/sparc/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/sparc/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/x86_64/target_prctl.h b/linux-user/x86_64/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/x86_64/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/xtensa/target_prctl.h b/linux-user/xtensa/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/xtensa/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 544f5b662f..a417396981 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6291,9 +6291,155 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr) return ret; } #endif /* defined(TARGET_ABI32 */ - #endif /* defined(TARGET_I386) */ +/* + * These constants are generic. Supply any that are missing from the host. + */ +#ifndef PR_SET_NAME +# define PR_SET_NAME 15 +# define PR_GET_NAME 16 +#endif +#ifndef PR_SET_FP_MODE +# define PR_SET_FP_MODE 45 +# define PR_GET_FP_MODE 46 +# define PR_FP_MODE_FR (1 << 0) +# define PR_FP_MODE_FRE (1 << 1) +#endif +#ifndef PR_SVE_SET_VL +# define PR_SVE_SET_VL 50 +# define PR_SVE_GET_VL 51 +# define PR_SVE_VL_LEN_MASK 0xffff +# define PR_SVE_VL_INHERIT (1 << 17) +#endif +#ifndef PR_PAC_RESET_KEYS +# define PR_PAC_RESET_KEYS 54 +# define PR_PAC_APIAKEY (1 << 0) +# define PR_PAC_APIBKEY (1 << 1) +# define PR_PAC_APDAKEY (1 << 2) +# define PR_PAC_APDBKEY (1 << 3) +# define PR_PAC_APGAKEY (1 << 4) +#endif +#ifndef PR_SET_TAGGED_ADDR_CTRL +# define PR_SET_TAGGED_ADDR_CTRL 55 +# define PR_GET_TAGGED_ADDR_CTRL 56 +# define PR_TAGGED_ADDR_ENABLE (1UL << 0) +#endif +#ifndef PR_MTE_TCF_SHIFT +# define PR_MTE_TCF_SHIFT 1 +# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TAG_SHIFT 3 +# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) +#endif + +#include "target_prctl.h" + +static abi_long do_prctl_inval0(CPUArchState *env) +{ + return -TARGET_EINVAL; +} + +static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2) +{ + return -TARGET_EINVAL; +} + +#ifndef do_prctl_get_fp_mode +#define do_prctl_get_fp_mode do_prctl_inval0 +#endif +#ifndef do_prctl_set_fp_mode +#define do_prctl_set_fp_mode do_prctl_inval1 +#endif +#ifndef do_prctl_get_vl +#define do_prctl_get_vl do_prctl_inval0 +#endif +#ifndef do_prctl_set_vl +#define do_prctl_set_vl do_prctl_inval1 +#endif +#ifndef do_prctl_reset_keys +#define do_prctl_reset_keys do_prctl_inval1 +#endif +#ifndef do_prctl_set_tagged_addr_ctrl +#define do_prctl_set_tagged_addr_ctrl do_prctl_inval1 +#endif +#ifndef do_prctl_get_tagged_addr_ctrl +#define do_prctl_get_tagged_addr_ctrl do_prctl_inval0 +#endif + +static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, + abi_long arg3, abi_long arg4, abi_long arg5) +{ + abi_long ret; + + switch (option) { + case PR_GET_PDEATHSIG: + { + int deathsig; + ret = get_errno(prctl(PR_GET_PDEATHSIG, &deathsig, + arg3, arg4, arg5)); + if (!is_error(ret) && arg2 && put_user_s32(deathsig, arg2)) { + return -TARGET_EFAULT; + } + return ret; + } + case PR_GET_NAME: + { + void *name = lock_user(VERIFY_WRITE, arg2, 16, 1); + if (!name) { + return -TARGET_EFAULT; + } + ret = get_errno(prctl(PR_GET_NAME, (uintptr_t)name, + arg3, arg4, arg5)); + unlock_user(name, arg2, 16); + return ret; + } + case PR_SET_NAME: + { + void *name = lock_user(VERIFY_READ, arg2, 16, 1); + if (!name) { + return -TARGET_EFAULT; + } + ret = get_errno(prctl(PR_SET_NAME, (uintptr_t)name, + arg3, arg4, arg5)); + unlock_user(name, arg2, 0); + return ret; + } + case PR_GET_FP_MODE: + return do_prctl_get_fp_mode(env); + case PR_SET_FP_MODE: + return do_prctl_set_fp_mode(env, arg2); + case PR_SVE_GET_VL: + return do_prctl_get_vl(env); + case PR_SVE_SET_VL: + return do_prctl_set_vl(env, arg2); + case PR_PAC_RESET_KEYS: + if (arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_reset_keys(env, arg2); + case PR_SET_TAGGED_ADDR_CTRL: + if (arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_set_tagged_addr_ctrl(env, arg2); + case PR_GET_TAGGED_ADDR_CTRL: + if (arg2 || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_get_tagged_addr_ctrl(env); + case PR_GET_SECCOMP: + case PR_SET_SECCOMP: + /* Disable seccomp to prevent the target disabling syscalls we need. */ + return -TARGET_EINVAL; + default: + /* Most prctl options have no pointer arguments */ + return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + } +} + #define NEW_STACK_SIZE 0x40000 @@ -10630,290 +10776,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, return ret; #endif case TARGET_NR_prctl: - switch (arg1) { - case PR_GET_PDEATHSIG: - { - int deathsig; - ret = get_errno(prctl(arg1, &deathsig, arg3, arg4, arg5)); - if (!is_error(ret) && arg2 - && put_user_s32(deathsig, arg2)) { - return -TARGET_EFAULT; - } - return ret; - } -#ifdef PR_GET_NAME - case PR_GET_NAME: - { - void *name = lock_user(VERIFY_WRITE, arg2, 16, 1); - if (!name) { - return -TARGET_EFAULT; - } - ret = get_errno(prctl(arg1, (unsigned long)name, - arg3, arg4, arg5)); - unlock_user(name, arg2, 16); - return ret; - } - case PR_SET_NAME: - { - void *name = lock_user(VERIFY_READ, arg2, 16, 1); - if (!name) { - return -TARGET_EFAULT; - } - ret = get_errno(prctl(arg1, (unsigned long)name, - arg3, arg4, arg5)); - unlock_user(name, arg2, 0); - return ret; - } -#endif -#ifdef TARGET_MIPS - case TARGET_PR_GET_FP_MODE: - { - CPUMIPSState *env = ((CPUMIPSState *)cpu_env); - ret = 0; - if (env->CP0_Status & (1 << CP0St_FR)) { - ret |= TARGET_PR_FP_MODE_FR; - } - if (env->CP0_Config5 & (1 << CP0C5_FRE)) { - ret |= TARGET_PR_FP_MODE_FRE; - } - return ret; - } - case TARGET_PR_SET_FP_MODE: - { - CPUMIPSState *env = ((CPUMIPSState *)cpu_env); - bool old_fr = env->CP0_Status & (1 << CP0St_FR); - bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE); - bool new_fr = arg2 & TARGET_PR_FP_MODE_FR; - bool new_fre = arg2 & TARGET_PR_FP_MODE_FRE; - - const unsigned int known_bits = TARGET_PR_FP_MODE_FR | - TARGET_PR_FP_MODE_FRE; - - /* If nothing to change, return right away, successfully. */ - if (old_fr == new_fr && old_fre == new_fre) { - return 0; - } - /* Check the value is valid */ - if (arg2 & ~known_bits) { - return -TARGET_EOPNOTSUPP; - } - /* Setting FRE without FR is not supported. */ - if (new_fre && !new_fr) { - return -TARGET_EOPNOTSUPP; - } - if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) { - /* FR1 is not supported */ - return -TARGET_EOPNOTSUPP; - } - if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64)) - && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { - /* cannot set FR=0 */ - return -TARGET_EOPNOTSUPP; - } - if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) { - /* Cannot set FRE=1 */ - return -TARGET_EOPNOTSUPP; - } - - int i; - fpr_t *fpr = env->active_fpu.fpr; - for (i = 0; i < 32 ; i += 2) { - if (!old_fr && new_fr) { - fpr[i].w[!FP_ENDIAN_IDX] = fpr[i + 1].w[FP_ENDIAN_IDX]; - } else if (old_fr && !new_fr) { - fpr[i + 1].w[FP_ENDIAN_IDX] = fpr[i].w[!FP_ENDIAN_IDX]; - } - } - - if (new_fr) { - env->CP0_Status |= (1 << CP0St_FR); - env->hflags |= MIPS_HFLAG_F64; - } else { - env->CP0_Status &= ~(1 << CP0St_FR); - env->hflags &= ~MIPS_HFLAG_F64; - } - if (new_fre) { - env->CP0_Config5 |= (1 << CP0C5_FRE); - if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { - env->hflags |= MIPS_HFLAG_FRE; - } - } else { - env->CP0_Config5 &= ~(1 << CP0C5_FRE); - env->hflags &= ~MIPS_HFLAG_FRE; - } - - return 0; - } -#endif /* MIPS */ -#ifdef TARGET_AARCH64 - case TARGET_PR_SVE_SET_VL: - /* - * We cannot support either PR_SVE_SET_VL_ONEXEC or - * PR_SVE_VL_INHERIT. Note the kernel definition - * of sve_vl_valid allows for VQ=512, i.e. VL=8192, - * even though the current architectural maximum is VQ=16. - */ - ret = -TARGET_EINVAL; - if (cpu_isar_feature(aa64_sve, env_archcpu(cpu_env)) - && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { - CPUARMState *env = cpu_env; - ARMCPU *cpu = env_archcpu(env); - uint32_t vq, old_vq; - - old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; - vq = MAX(arg2 / 16, 1); - vq = MIN(vq, cpu->sve_max_vq); - - if (vq < old_vq) { - aarch64_sve_narrow_vq(env, vq); - } - env->vfp.zcr_el[1] = vq - 1; - arm_rebuild_hflags(env); - ret = vq * 16; - } - return ret; - case TARGET_PR_SVE_GET_VL: - ret = -TARGET_EINVAL; - { - ARMCPU *cpu = env_archcpu(cpu_env); - if (cpu_isar_feature(aa64_sve, cpu)) { - ret = ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; - } - } - return ret; - case TARGET_PR_PAC_RESET_KEYS: - { - CPUARMState *env = cpu_env; - ARMCPU *cpu = env_archcpu(env); - - if (arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - int all = (TARGET_PR_PAC_APIAKEY | TARGET_PR_PAC_APIBKEY | - TARGET_PR_PAC_APDAKEY | TARGET_PR_PAC_APDBKEY | - TARGET_PR_PAC_APGAKEY); - int ret = 0; - Error *err = NULL; - - if (arg2 == 0) { - arg2 = all; - } else if (arg2 & ~all) { - return -TARGET_EINVAL; - } - if (arg2 & TARGET_PR_PAC_APIAKEY) { - ret |= qemu_guest_getrandom(&env->keys.apia, - sizeof(ARMPACKey), &err); - } - if (arg2 & TARGET_PR_PAC_APIBKEY) { - ret |= qemu_guest_getrandom(&env->keys.apib, - sizeof(ARMPACKey), &err); - } - if (arg2 & TARGET_PR_PAC_APDAKEY) { - ret |= qemu_guest_getrandom(&env->keys.apda, - sizeof(ARMPACKey), &err); - } - if (arg2 & TARGET_PR_PAC_APDBKEY) { - ret |= qemu_guest_getrandom(&env->keys.apdb, - sizeof(ARMPACKey), &err); - } - if (arg2 & TARGET_PR_PAC_APGAKEY) { - ret |= qemu_guest_getrandom(&env->keys.apga, - sizeof(ARMPACKey), &err); - } - if (ret != 0) { - /* - * Some unknown failure in the crypto. The best - * we can do is log it and fail the syscall. - * The real syscall cannot fail this way. - */ - qemu_log_mask(LOG_UNIMP, - "PR_PAC_RESET_KEYS: Crypto failure: %s", - error_get_pretty(err)); - error_free(err); - return -TARGET_EIO; - } - return 0; - } - } - return -TARGET_EINVAL; - case TARGET_PR_SET_TAGGED_ADDR_CTRL: - { - abi_ulong valid_mask = TARGET_PR_TAGGED_ADDR_ENABLE; - CPUARMState *env = cpu_env; - ARMCPU *cpu = env_archcpu(env); - - if (cpu_isar_feature(aa64_mte, cpu)) { - valid_mask |= TARGET_PR_MTE_TCF_MASK; - valid_mask |= TARGET_PR_MTE_TAG_MASK; - } - - if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - env->tagged_addr_enable = arg2 & TARGET_PR_TAGGED_ADDR_ENABLE; - - if (cpu_isar_feature(aa64_mte, cpu)) { - switch (arg2 & TARGET_PR_MTE_TCF_MASK) { - case TARGET_PR_MTE_TCF_NONE: - case TARGET_PR_MTE_TCF_SYNC: - case TARGET_PR_MTE_TCF_ASYNC: - break; - default: - return -EINVAL; - } - - /* - * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. - * Note that the syscall values are consistent with hw. - */ - env->cp15.sctlr_el[1] = - deposit64(env->cp15.sctlr_el[1], 38, 2, - arg2 >> TARGET_PR_MTE_TCF_SHIFT); - - /* - * Write PR_MTE_TAG to GCR_EL1[Exclude]. - * Note that the syscall uses an include mask, - * and hardware uses an exclude mask -- invert. - */ - env->cp15.gcr_el1 = - deposit64(env->cp15.gcr_el1, 0, 16, - ~arg2 >> TARGET_PR_MTE_TAG_SHIFT); - arm_rebuild_hflags(env); - } - return 0; - } - case TARGET_PR_GET_TAGGED_ADDR_CTRL: - { - abi_long ret = 0; - CPUARMState *env = cpu_env; - ARMCPU *cpu = env_archcpu(env); - - if (arg2 || arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - if (env->tagged_addr_enable) { - ret |= TARGET_PR_TAGGED_ADDR_ENABLE; - } - if (cpu_isar_feature(aa64_mte, cpu)) { - /* See above. */ - ret |= (extract64(env->cp15.sctlr_el[1], 38, 2) - << TARGET_PR_MTE_TCF_SHIFT); - ret = deposit64(ret, TARGET_PR_MTE_TAG_SHIFT, 16, - ~env->cp15.gcr_el1); - } - return ret; - } -#endif /* AARCH64 */ - case PR_GET_SECCOMP: - case PR_SET_SECCOMP: - /* Disable seccomp to prevent the target disabling syscalls we - * need. */ - return -TARGET_EINVAL; - default: - /* Most prctl options have no pointer arguments */ - return get_errno(prctl(arg1, arg2, arg3, arg4, arg5)); - } + return do_prctl(cpu_env, arg1, arg2, arg3, arg4, arg5); break; #ifdef TARGET_NR_arch_prctl case TARGET_NR_arch_prctl: From patchwork Fri Oct 15 04:10:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515842 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp154193imi; Thu, 14 Oct 2021 21:53:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzaguyTwxqAcUZOlCX3hMgcIlGgbPpDYji3PyGRIoQW/6HGBAfgR/vnzOnS5XQ8OaqXTJ8X X-Received: by 2002:a25:b7d3:: with SMTP id u19mr10459349ybj.158.1634273628742; Thu, 14 Oct 2021 21:53:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634273628; cv=none; d=google.com; s=arc-20160816; b=oHmCrRRU6RkNTk/7+aTN5PfCoZiFDLJZw+u0F05oHRPbr02X8Ocs38Bpk9unDmRgZT yzkhIOobByo2jyPKqJfedgla8zrlNl30p611jrbMAjAJX+YaYWqgIBgWXYurM3wgA073 t99XkQ2LWJnHVeXX9f+gNNrQtQVpe7jrkpYSMAzRdarCjLmrKEn9KIUrgnR7N1qtqq03 Ck3BT2fQBMP2gGTus378wE6IlGhhl3+xTW392rlNicNiAHzbwfLaM0Lx2xxn7l490k+z yyfuRoiqYTa/C+B4Uw3dS/D3mQhhukeEj/CwEyHS/fEB1vKG6q7pd+PKvwiFguy/qjM2 cTxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OxMgM7wzD4BcAcUx2qJmodE4BwJ9QwGNSAt09qoFyFU=; b=RH/yHa3o8nuMqsRY7HI/9hz9BXEuGIALRa9tJqKG5qEH7DOZmf8j/CsyXHe3HOrnTe LeYN4aNqUj3glOa3P0tgbgDrsbIms/8E06iiAdiHn7leOs4agAfKJIAeDEu43luFODF+ MiJx9HWHFuvdaM56QGiY13hQOHT7YTJu2h9LfipSWITW99fFeqcGNsCFzt3uy4zTVoYE vj8WmOthPvxH4lf+NwvWXYkh8OYNlOLruU9+39rlX8XuMUgLp8bb0+D5bo1a24pjh34m zIxZlxC3ClCI5sOK21fW4YQ+z+EubRKDdqT64bhWUGREFXo+0VYv+im6Iz/NwzyaEQz4 0Uww== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=n2oEhFHE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 205si6869494ybn.213.2021.10.14.21.53.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:53:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=n2oEhFHE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42856 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbFE4-0004h9-1U for patch@linaro.org; Fri, 15 Oct 2021 00:53:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39756) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcJ-00070P-T1 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:49 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:45904) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcI-00030d-2S for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:47 -0400 Received: by mail-pf1-x42c.google.com with SMTP id f11so3410927pfc.12 for ; Thu, 14 Oct 2021 21:14:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OxMgM7wzD4BcAcUx2qJmodE4BwJ9QwGNSAt09qoFyFU=; b=n2oEhFHE1FfC+NGrQFPyUFWLxN7nZbYmgUcOZZXMymDYfFnaE6FG98C8jxVGAVAb/n r1niXz3J9VA8S2nYLT+fA8trxPYESN4A0Un874SfVpqHg7AIKpnoYjMmLENVKLa1qZCw Cxa8mXZvQQCBdA7K/SDZkZfsdN6KV+4FjzvLQr0+/Ifg09Sr8fLGI5YQQbemE4ZVlj2u 2W9/z4NaU+Bl1gXhrsGh4bu0c+fmR2V91e6y3qceyS9vjKeF5v+RHhupR1rWqu6IQ2rC WvA5FaNT6zY7+pLWlSEXPAYrq/XPLECr8v/EsnXuVx+VGRa9/rR/qylSHAIGTM81MmMN l6aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OxMgM7wzD4BcAcUx2qJmodE4BwJ9QwGNSAt09qoFyFU=; b=C3g0YuyKDQ+6B7EQ+pO/QmIt4LglhoT7DrivFnUyQUMmSf2BnhvvsZ941BqfE9XC6o tUsELF3Cb0lkwMrtkTWzxXuXVfXYvK4178FysZNHYDq3U3tTf6LYyZi6UrQ7rmjpKv3r IjUNOQZTQAD4f6c9CuqnlDUsLblUwCll5cNfdtA3M54j1eK8HLE0gOfwElxMr5P6Ddq1 ESkaI2dPhZ2TXxDz/sGffhprFG4FJUaNVqEQMKk0WTPyNpEdfJJCeh5PBKVEVSWKZiJO KHL1o+3jAcLY+K5vAnSj2UE4yG0jo7WLxeZ+ry9UXd/P1raHux65xXcGNEoSCis5Iyxe FEag== X-Gm-Message-State: AOAM531Udum5GvQZTGhQKqGlcvsT27jfJE6sdare3I3GqYkbTZ9KujhK +l+EnBwoEw7zXEt5geYr7Bwr4v5K6rfAAw== X-Received: by 2002:a05:6a00:8d0:b0:44c:26e6:1c13 with SMTP id s16-20020a056a0008d000b0044c26e61c13mr9506973pfu.28.1634271284454; Thu, 14 Oct 2021 21:14:44 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 63/67] linux-user: Disable more prctl subcodes Date: Thu, 14 Oct 2021 21:10:49 -0700 Message-Id: <20211015041053.2769193-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a list of subcodes that we want to pass on, a list of subcodes that should not be passed on because they would affect the running qemu itself, and a list that probably could be implemented but require extra work. Do not pass on unknown subcodes. Signed-off-by: Richard Henderson --- linux-user/syscall.c | 56 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 52 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/linux-user/syscall.c b/linux-user/syscall.c index a417396981..7635c2397a 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6334,6 +6334,13 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr) # define PR_MTE_TAG_SHIFT 3 # define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) #endif +#ifndef PR_SET_IO_FLUSHER +# define PR_SET_IO_FLUSHER 57 +# define PR_GET_IO_FLUSHER 58 +#endif +#ifndef PR_SET_SYSCALL_USER_DISPATCH +# define PR_SET_SYSCALL_USER_DISPATCH 59 +#endif #include "target_prctl.h" @@ -6430,13 +6437,54 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, return -TARGET_EINVAL; } return do_prctl_get_tagged_addr_ctrl(env); + + case PR_GET_DUMPABLE: + case PR_SET_DUMPABLE: + case PR_GET_KEEPCAPS: + case PR_SET_KEEPCAPS: + case PR_GET_TIMING: + case PR_SET_TIMING: + case PR_GET_TIMERSLACK: + case PR_SET_TIMERSLACK: + case PR_MCE_KILL: + case PR_MCE_KILL_GET: + case PR_GET_NO_NEW_PRIVS: + case PR_SET_NO_NEW_PRIVS: + case PR_GET_IO_FLUSHER: + case PR_SET_IO_FLUSHER: + /* Some prctl options have no pointer arguments and we can pass on. */ + return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + + case PR_GET_CHILD_SUBREAPER: + case PR_SET_CHILD_SUBREAPER: + case PR_GET_SPECULATION_CTRL: + case PR_SET_SPECULATION_CTRL: + case PR_GET_TID_ADDRESS: + /* TODO */ + return -TARGET_EINVAL; + + case PR_GET_FPEXC: + case PR_SET_FPEXC: + /* Was used for SPE on PowerPC. */ + return -TARGET_EINVAL; + + case PR_GET_ENDIAN: + case PR_SET_ENDIAN: + case PR_GET_FPEMU: + case PR_SET_FPEMU: + case PR_SET_MM: case PR_GET_SECCOMP: case PR_SET_SECCOMP: - /* Disable seccomp to prevent the target disabling syscalls we need. */ - return -TARGET_EINVAL; + case PR_SET_SYSCALL_USER_DISPATCH: + case PR_GET_THP_DISABLE: + case PR_SET_THP_DISABLE: + case PR_GET_TSC: + case PR_SET_TSC: + case PR_GET_UNALIGN: + case PR_SET_UNALIGN: default: - /* Most prctl options have no pointer arguments */ - return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + /* Disable to prevent the target disabling stuff we need. */ + return -TARGET_EINVAL; } } From patchwork Fri Oct 15 04:10:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515838 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp152370imi; Thu, 14 Oct 2021 21:49:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJytycdBC4UoVk0KbiR+LjmUjcswX4j6YZgMFL/bh4tJ4ipFxZwmAtR4Av0HpOPlhi+wX2Ha X-Received: by 2002:a05:6638:3052:: with SMTP id u18mr6984236jak.148.1634273398977; Thu, 14 Oct 2021 21:49:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634273398; cv=none; d=google.com; s=arc-20160816; b=C3ntrgcVy0XHrRvKlBCs2Xnj4p6EetRSPGEL3n3Ox8mzn1gGNL5TchjPur+Flj0cqB qO14O2G7wxJC7nFmtWBrVjM84BVkuONHnIUsFf4EJXxV9wjiqiqObucieOW8dH1CbyVk pu3mVVeUMsN74J06Eo4mOe/BnZK9evz5HaT2cSlVctLgNoK6TZh0Il9YQYGb85tSYWMB IRFqtwjlIgmw7ms0vFbCisg/tnJKpogAqIp/43N+6fr++b7f7GSvSqWdV4CqISdPJeZU r1SRz9mU5fXE0ygCmm/k5A+BvaBdYaukvwf2H9oEdZCdSXKvWVS+wB2fG24tfOtFJlLK W35g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kgbxRfaLnXEAdarkY+uz+mGv9JnWFVB+tvkZlav9GvM=; b=HSKs3My/l6CNzgTzyPT5ddM2d3zY2ThmaW50iMBi4uW/wptx9QTI+jNsi0CHktPz49 vLierkSslCsgjLyfm0s1zXaP/LKPcH4LOR9yRbUpYFfIojQZjsBAIpkH6iuZCiwRxz8i jVxaok2g6TxHS2mOteOjR6oxapHe5ikxWXW4Zojuk5tQ4v/zqz5XHv57Dmfs7bU4qfX0 jVBak8TLATYSnj2n1zskQ4vGPjA4BnhAsxiUkxMf6PLTKlIDA0ZN1fBMcbUUw3yyb7tk +Q8/NUsf7cYLbGDdrO9czcrGoQkymuwmLKWQ2xVzIIGfMBCZm9y+38B/NQA7VgwVWNmz I31w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="aU/NZ9fb"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y18si6240889ioq.44.2021.10.14.21.49.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:49:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="aU/NZ9fb"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33336 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbFAM-0006dU-4W for patch@linaro.org; Fri, 15 Oct 2021 00:49:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39774) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcK-00070R-Hz for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:49 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:40699) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcI-00030m-Eu for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:48 -0400 Received: by mail-pl1-x62b.google.com with SMTP id v20so5597180plo.7 for ; Thu, 14 Oct 2021 21:14:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kgbxRfaLnXEAdarkY+uz+mGv9JnWFVB+tvkZlav9GvM=; b=aU/NZ9fb7fK43uXivA7vwfLR31Sy/r9Ewf2AEE1QITN2wKlQLndOwlSuw17Nx7ayGR 3kPIyUmKiztLN9QwOFBhGm50+MjL9IlsyzhgYOWkn+FM6Alwv4Kvl9UFteKbDM9AeCcq D1qvjT2anwmGiIEXMVcZ4KaV5AkkkkMVsmB7uz9Oqr081QTKuPse57tlORu3wYIsndyZ 47LDeGSYdSunbB2sagXgeYJAVfywrgQjbWe+mRB3Ojlu8OC4mLooCCLr+WetCAdZI8JK e7KF+cHbTyxjEeHVswB7JqCNTkyhl3tczwq+R3z8HKfCDUe+q4ZGFJHVVYBauwC2+DWX eB/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kgbxRfaLnXEAdarkY+uz+mGv9JnWFVB+tvkZlav9GvM=; b=PrOR5DMwM8Axo9spXFiMCJCNZVHs/JXD0XY7eTtvAJmY8VHaE3sVgnpEJRh6E8qJ6o AZApSbV9dntIHu1CU9RI5D38/o/AYNZVbaFH1xSz+01P0nbGaD4rKk4LnM1K+9JdLHUB bsO4Du0kU2+2HzdghRfzvT7ZwtGsarSo0VW07lWfpzB5JyqwjiJPa5VWPcyyja8xiUvt WjCddzBA4ahXYMYpdS15kTrGplXpqiPXQc481U1AQXV5RZR4xfSyfCwwh+o5FEesKtOf rS+r0oFlJCPaDTTnTgCkzHhoqbbwiA66EfL4t4a9IjI+sRiD3JFxJSMuaVEeYKmbdV0n oXHA== X-Gm-Message-State: AOAM530O6RfMiZZMMmab1gYlCWVHscY+QlpYCf/PWmh+nv6W8NLSiMvN tRMGvgrCkkLsj8VJWiYMaDiXUlj4IeKVew== X-Received: by 2002:a17:90b:388c:: with SMTP id mu12mr10977559pjb.146.1634271285073; Thu, 14 Oct 2021 21:14:45 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 64/67] linux-user: Add code for PR_GET/SET_UNALIGN Date: Thu, 14 Oct 2021 21:10:50 -0700 Message-Id: <20211015041053.2769193-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This requires extra work for each target, but adds the common syscall code, and the necessary flag in CPUState. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 3 +++ linux-user/generic/target_prctl_unalign.h | 27 +++++++++++++++++++++++ cpu.c | 20 ++++++++++++----- linux-user/syscall.c | 13 +++++++++-- 4 files changed, 56 insertions(+), 7 deletions(-) create mode 100644 linux-user/generic/target_prctl_unalign.h -- 2.25.1 Reviewed-by: Warner Losh Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 1a10497af3..6202bbf9c3 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -412,6 +412,9 @@ struct CPUState { bool ignore_memory_transaction_failures; + /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ + bool prctl_unalign_sigbus; + struct hax_vcpu_state *hax_vcpu; struct hvf_vcpu_state *hvf; diff --git a/linux-user/generic/target_prctl_unalign.h b/linux-user/generic/target_prctl_unalign.h new file mode 100644 index 0000000000..bc3b83af2a --- /dev/null +++ b/linux-user/generic/target_prctl_unalign.h @@ -0,0 +1,27 @@ +/* + * Generic prctl unalign functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef GENERIC_TARGET_PRCTL_UNALIGN_H +#define GENERIC_TARGET_PRCTL_UNALIGN_H + +static abi_long do_prctl_get_unalign(CPUArchState *env, target_long arg2) +{ + CPUState *cs = env_cpu(env); + uint32_t res = PR_UNALIGN_NOPRINT; + if (cs->prctl_unalign_sigbus) { + res |= PR_UNALIGN_SIGBUS; + } + return put_user_u32(res, arg2); +} +#define do_prctl_get_unalign do_prctl_get_unalign + +static abi_long do_prctl_set_unalign(CPUArchState *env, target_long arg2) +{ + env_cpu(env)->prctl_unalign_sigbus = arg2 & PR_UNALIGN_SIGBUS; + return 0; +} +#define do_prctl_set_unalign do_prctl_set_unalign + +#endif /* GENERIC_TARGET_PRCTL_UNALIGN_H */ diff --git a/cpu.c b/cpu.c index 9bce67ef55..9e388d9cd3 100644 --- a/cpu.c +++ b/cpu.c @@ -179,13 +179,23 @@ void cpu_exec_unrealizefn(CPUState *cpu) cpu_list_remove(cpu); } +/* + * This can't go in hw/core/cpu.c because that file is compiled only + * once for both user-mode and system builds. + */ static Property cpu_common_props[] = { -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY /* - * Create a memory property for softmmu CPU object, - * so users can wire up its memory. (This can't go in hw/core/cpu.c - * because that file is compiled only once for both user-mode - * and system builds.) The default if no link is set up is to use + * Create a property for the user-only object, so users can + * adjust prctl(PR_SET_UNALIGN) from the command-line. + * Has no effect if the target does not support the feature. + */ + DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState, + prctl_unalign_sigbus, false), +#else + /* + * Create a memory property for softmmu CPU object, so users can + * wire up its memory. The default if no link is set up is to use * the system address space. */ DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 7635c2397a..ac3bc8a330 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6375,6 +6375,12 @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2) #ifndef do_prctl_get_tagged_addr_ctrl #define do_prctl_get_tagged_addr_ctrl do_prctl_inval0 #endif +#ifndef do_prctl_get_unalign +#define do_prctl_get_unalign do_prctl_inval1 +#endif +#ifndef do_prctl_set_unalign +#define do_prctl_set_unalign do_prctl_inval1 +#endif static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5) @@ -6438,6 +6444,11 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, } return do_prctl_get_tagged_addr_ctrl(env); + case PR_GET_UNALIGN: + return do_prctl_get_unalign(env, arg2); + case PR_SET_UNALIGN: + return do_prctl_set_unalign(env, arg2); + case PR_GET_DUMPABLE: case PR_SET_DUMPABLE: case PR_GET_KEEPCAPS: @@ -6480,8 +6491,6 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, case PR_SET_THP_DISABLE: case PR_GET_TSC: case PR_SET_TSC: - case PR_GET_UNALIGN: - case PR_SET_UNALIGN: default: /* Disable to prevent the target disabling stuff we need. */ return -TARGET_EINVAL; From patchwork Fri Oct 15 04:10:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515844 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp156223imi; Thu, 14 Oct 2021 21:57:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyN6+gFdkxlBOkUaWoAPlBoCTa9wzUUOpjGyI6WQuwJw+Kh5s3IEDB/872va+ZOh/E5FC9K X-Received: by 2002:a92:c56e:: with SMTP id b14mr2203084ilj.111.1634273837370; Thu, 14 Oct 2021 21:57:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634273837; cv=none; d=google.com; s=arc-20160816; b=KTub1FyB7EYCyYhxx1q7pGqYfymvXOTKhu2mKv8Maz1yDGOTGcl6hrnI/rV009+HDn SQh8i0qPOzaFatCXJ3TOBbve8J16xbauE5VkIp9oQEimzigEClJgB5KEqxWhtagDmXiD OdckZaWZHVB0tyef1onzHTGvq22uJ+TQYjdSWxNA0p5u1XlAnLi58SDziBcSMzl9uEue F4qnru7ojPaDUomfTZl66BSTcMgudJ3xFoyiLmcx5/3Vd3gawMafg3oMBkgqvuGswxhv gljIDJXsm6QgEsoWsUXhlG+YNg8nlqZzn77MhXmy4EmoPSv6D5Zw5Nq71Pf1/ssWCku4 yN0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ibr1nNRFVeuBeAqywwGzrumnaR34sN1fg0KpH5ukJvY=; b=pwDyc6UfwU3dMr/UX9PxyTTqyFUixvkq1jNkNY386igfx9AGgfaCxwDbI9uc1k0IWk miDcNvm9StGqCNJwdhJhqXQdNTKkDS8zSRH/QRePkUl9VW6Bp0nCbCfVwuGHHNjj4YLX 1u+96E7DREZebUoGkz8ReH6ihkHv750p5xuVjRtYDYclVe958JKPHpevmoU/4UymxKVY EVL6bdfTtRgv4BhpZPtsJ7U+hhjBA7HO4/i2PfxmK0vwZRW6o16JWH+GrdFNQ94ARgzY 1SZqFbYNZiSKVvS9ryC4gH9o2jrlorwgbvK0xrm55v3yHGaOvLOsvS12CuI8JGuTX2L6 3e7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PBgmaZxs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r14si7718500ilb.126.2021.10.14.21.57.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:57:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PBgmaZxs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49014 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbFHQ-0000UH-IG for patch@linaro.org; Fri, 15 Oct 2021 00:57:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39792) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcL-00071J-G8 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:49 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:36393) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcJ-00031U-2M for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:49 -0400 Received: by mail-pf1-x429.google.com with SMTP id m26so7315250pff.3 for ; Thu, 14 Oct 2021 21:14:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ibr1nNRFVeuBeAqywwGzrumnaR34sN1fg0KpH5ukJvY=; b=PBgmaZxspbnMhUR0+fkJ9nXkmDq+6mFffz7MMQxHfTXIgQAdHlC8JsgSXYaitvns7R Cxm1YfWq+Raly4pPFAQTcOcsEO7Tv5DNLYsVvSqD/OWabYYy9tj9PuqVjkNRrIH8ZstQ DLkPmMMbVXb7dCTOhJYXd6ePFfINp72U7cCVzUlcxYUOYzJ+t3YdGz8IZC/mHn3mJKY9 XW4uDnkcf6U7cV/i3Oo2SbR5nQNTSa2eBPp7H0vNYmTk0UUPeMlg+AOtaVfHCqgd6LEP zFZe6JEuXjXVJT5/CM+4InZj0Nq/bSJBW4u0YPnOpwRhC+SPDYuFp+R5u+XR1KIPrYCn nkKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ibr1nNRFVeuBeAqywwGzrumnaR34sN1fg0KpH5ukJvY=; b=3Ku7a/2ySxfzyeIS/pv7PkahoI+SVm7nZbBTvkmKJ9GZzwBSImPlqX+Fd9SMZ7BIzg cA+K2taH5skjNkpm8AVgGWE2MbY7eY1n7eXpIiTwR48hfJYd4FToGuGJwOHJsLCLoUwD xeTN2lRpo92rhbNP6n2Un3UVsmgOnuclfCX+kWhZYHxzWY/p3L0z8TFSqfkRMMdW+AjA luhe4v5sl8PqmfUQ/feUDIfKuqRXRqFouPyc6WVss1ex3mNZVDrzIN4g7DgzFXBaESaF eR0094LYvztaCj/ebub2hzruFvOoNwvKCs7FUOT5rjpojgkbC96BsorGw2jGMGOXU47X FDEA== X-Gm-Message-State: AOAM530F9W2PErr6m2jT+OOVKwbLeK+D7w9yt3fAbsdXS8gxFBAvV2w8 defH2NtIiSbDb3ULHz3bK3H4HN8MOt0mlg== X-Received: by 2002:a62:60c2:0:b0:448:7376:20c4 with SMTP id u185-20020a6260c2000000b00448737620c4mr9275709pfb.11.1634271285695; Thu, 14 Oct 2021 21:14:45 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 65/67] target/alpha: Implement prctl_unalign_sigbus Date: Thu, 14 Oct 2021 21:10:51 -0700 Message-Id: <20211015041053.2769193-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson --- linux-user/alpha/target_prctl.h | 2 +- target/alpha/cpu.h | 5 +++++ target/alpha/translate.c | 31 ++++++++++++++++++++++--------- 3 files changed, 28 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prctl.h index eb53b31ad5..5629ddbf39 100644 --- a/linux-user/alpha/target_prctl.h +++ b/linux-user/alpha/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index afd975c878..e819211503 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -383,6 +383,8 @@ enum { #define ENV_FLAG_TB_MASK \ (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN) +#define TB_FLAG_UNALIGN (1u << 1) + static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) { int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX; @@ -470,6 +472,9 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc, *pc = env->pc; *cs_base = 0; *pflags = env->flags & ENV_FLAG_TB_MASK; +#ifdef CONFIG_USER_ONLY + *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif } #ifdef CONFIG_USER_ONLY diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 0eee3a1bcc..2656037b8b 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -45,7 +45,9 @@ typedef struct DisasContext DisasContext; struct DisasContext { DisasContextBase base; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + MemOp unalign; +#else uint64_t palbr; #endif uint32_t tbflags; @@ -68,6 +70,12 @@ struct DisasContext { TCGv sink; }; +#ifdef CONFIG_USER_ONLY +#define UNALIGN(C) (C)->unalign +#else +#define UNALIGN(C) 0 +#endif + /* Target-specific return values from translate_one, indicating the state of the TB. Note that DISAS_NEXT indicates that we are not exiting the TB. */ @@ -270,7 +278,7 @@ static inline DisasJumpType gen_invalid(DisasContext *ctx) static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_f(dest, tmp32); tcg_temp_free_i32(tmp32); } @@ -278,7 +286,7 @@ static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr) static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv tmp = tcg_temp_new(); - tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); gen_helper_memory_to_g(dest, tmp); tcg_temp_free(tmp); } @@ -286,14 +294,14 @@ static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr) static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_s(dest, tmp32); tcg_temp_free_i32(tmp32); } static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr) { - tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -324,6 +332,8 @@ static void gen_load_int(DisasContext *ctx, int ra, int rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else if (!locked) { + op |= UNALIGN(ctx); } dest = ctx->ir[ra]; @@ -340,7 +350,7 @@ static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); gen_helper_f_to_memory(tmp32, addr); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } @@ -348,7 +358,7 @@ static void gen_stg(DisasContext *ctx, TCGv src, TCGv addr) { TCGv tmp = tcg_temp_new(); gen_helper_g_to_memory(tmp, src); - tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); tcg_temp_free(tmp); } @@ -356,13 +366,13 @@ static void gen_sts(DisasContext *ctx, TCGv src, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); gen_helper_s_to_memory(tmp32, src); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr) { - tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -383,6 +393,8 @@ static void gen_store_int(DisasContext *ctx, int ra, int rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else { + op |= UNALIGN(ctx); } src = load_gpr(ctx, ra); @@ -2942,6 +2954,7 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) #ifdef CONFIG_USER_ONLY ctx->ir = cpu_std_ir; + ctx->unalign = (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->palbr = env->palbr; ctx->ir = (ctx->tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_ir); From patchwork Fri Oct 15 04:10:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515841 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp153783imi; Thu, 14 Oct 2021 21:52:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzvn+0dIAWxK0ZCUiHSW4aLV7CZsPu+NBwahurMvA5exgY+qihdgWWqDmPc1DBnysrrZhzp X-Received: by 2002:a25:c78d:: with SMTP id w135mr11161321ybe.66.1634273577459; Thu, 14 Oct 2021 21:52:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634273577; cv=none; d=google.com; s=arc-20160816; b=JEJPAi0Oi2EKMWV8MZlyfsVAs2g/Ek9WAVvJ6tHBcZq9sY6lsp9nkY/a44kfCQpSrB 6rQ1zYBjXFf43Q9rACGewQSVyANxe4UYvWt9eLvy87OA+EXHLh8l9xFlEVqLSiPl1PRq 1brDP3vQ3v8GDRw8wMPHwTOT67FPQknT8tNGCU33enEKCyUnrgbO/ycqY9IrRYjClDDv xLTfckX8fXzNEPbZJPcpcVz2JBV5pMCny+2viOFAPJYul4ZuWi6A+i6gwJGzCX2nXdJQ ygYyL3q8LlWyX35+L/14+7N96YlBNxhvc4n/0pgVIOM+J1KQ6ycIcIH4egTngkE6ZTJV zV2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FDh0xRrxNKle4pRoEftfiIirEtPOD6rcCJZUiwu3wG8=; b=y1b1+gLxWthjzb6r+k4Ul05CSHF8A6NoQRetUgnnus6RZIC28SY8VhbzxMC/S7ozBQ joFmOJ+fv2i+pF7vCjKBgXQ47n8WLBm0rsbtqPc+pGaamJwwpgeagm2Oj7j3tLqO9NIg aWtbWmYo28mbDtWn3pP2KO6ttL+CKqloOuy9okM/CXjo5amf1Tq57ZzfgfKxp+RlMvvj UOhFwKCol5hT5DCAlNB/yA9KHPb9UPAUHOxKgLb0mMEL1VyAivGcTtnpMnJ9ufwuojQM BWdEqNH5r2pf1GvYh2jyISVQBwE8czPvSISJz3lVHZZciIzosCbw5lUkIsFZJPxMY7MT gY4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AbWK5js1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- linux-user/hppa/target_prctl.h | 2 +- target/hppa/cpu.h | 5 ++++- target/hppa/translate.c | 19 +++++++++++++++---- 3 files changed, 20 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h index eb53b31ad5..5629ddbf39 100644 --- a/linux-user/hppa/target_prctl.h +++ b/linux-user/hppa/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 294fd7297f..45fd338b02 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -259,12 +259,14 @@ static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, return hppa_form_gva_psw(env->psw, spc, off); } -/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them. +/* + * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the * same value. */ #define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 +#define TB_FLAG_UNALIGN 0x400 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, target_ulong *cs_base, @@ -279,6 +281,7 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, #ifdef CONFIG_USER_ONLY *pc = env->iaoq_f & -4; *cs_base = env->iaoq_b & -4; + flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; #else /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ flags |= env->psw & (PSW_W | PSW_C | PSW_D); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c3698cf067..fdaa2b12b8 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -272,8 +272,18 @@ typedef struct DisasContext { int mmu_idx; int privilege; bool psw_n_nonzero; + +#ifdef CONFIG_USER_ONLY + MemOp unalign; +#endif } DisasContext; +#ifdef CONFIG_USER_ONLY +#define UNALIGN(C) (C)->unalign +#else +#define UNALIGN(C) 0 +#endif + /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ static int expand_sm_imm(DisasContext *ctx, int val) { @@ -1477,7 +1487,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx == MMU_PHYS_IDX); - tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1495,7 +1505,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx == MMU_PHYS_IDX); - tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1513,7 +1523,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx == MMU_PHYS_IDX); - tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1531,7 +1541,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx == MMU_PHYS_IDX); - tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -4110,6 +4120,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->mmu_idx = MMU_USER_IDX; ctx->iaoq_f = ctx->base.pc_first | MMU_USER_IDX; ctx->iaoq_b = ctx->base.tb->cs_base | MMU_USER_IDX; + ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX); From patchwork Fri Oct 15 04:10:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515835 Delivered-To: patch@linaro.org Received: by 2002:ac0:da11:0:0:0:0:0 with SMTP id d17csp151750imi; Thu, 14 Oct 2021 21:48:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxsXo6g55L0rU4t4mZR833fnoJqAIJY6gg9a4de3107x/g84z6CEt9Ejie5iLl3tcUhyMQc X-Received: by 2002:a05:6e02:20e7:: with SMTP id q7mr2229606ilv.277.1634273318875; Thu, 14 Oct 2021 21:48:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634273318; cv=none; d=google.com; s=arc-20160816; b=Dfk0ZGGaIHA5+yiNJ6+YRLPTZgwrIRMkF/jPw26zGljsXmp5vP8jqTXlnssEa3mOE7 KfYhIi1EXxUTpplRew9rcWUXkgDX3KgS5SLHjOwvCgU5vWZ3nsoTdMtUX0/mLJLrt7qC pVt/HLyYgAfwJu8l+ykW2VP2huHfZj3wJQI4VER2AP/eCMEmpws0fksCLEYH4m3ZrHff J2qz2EtbcvmwVV+Kpd9XwDtL8vcwjhJikj4iWz3NSVXCMKUpryrR5Yn6/0Kq4cPKY6Sd jo2JNhSf3eqGZq5xxpjZ7Gwai2ClLGWTZ/1jZKdlDpdo6lmNeA0rIXtuY8Td92AYfwYb Nk2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QXtWYu3k26efdjnMd2Pt42jkFdW4b3H42VfJHmp983k=; b=SwcgvDsqyPWGlZYoCem1OVD8n5ov8DRGz1vk4n83efq5mT/FKsTajMAIRsCx2DmKnr b19id4c/vXGjo6wFnvMRvflHPz+DO7TkPIeUjSuQ0gy7PIOuTVnGVvGQnlPUyPoEWpbS Phig5afMPTf1Y4i8ZY4iHzaGLBbMJLErUN/kxWoUO7prsto3TOaUM4nIQxFhjMy/piVK umPjjZ/VEfX4TWhe6E7arQUaAVEBdCfJ9WC3TyKcLLZWZXcnxevf5OFaC5d3KlMRMNsO N6fuGTorcolW4bNaOuEfZxVugCav/MVLynd0vQUMxDMZQ26Ei0aQZnp+ZAk8li74P6y/ eVIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SVI14zqg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g5si6957670ild.112.2021.10.14.21.48.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:48:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SVI14zqg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55896 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF94-0002lR-0w for patch@linaro.org; Fri, 15 Oct 2021 00:48:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEcN-000755-87 for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:51 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:37568) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEcK-00033X-Dp for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:50 -0400 Received: by mail-pg1-x52c.google.com with SMTP id s136so4203278pgs.4 for ; Thu, 14 Oct 2021 21:14:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QXtWYu3k26efdjnMd2Pt42jkFdW4b3H42VfJHmp983k=; b=SVI14zqg8H1ZYoKK9vlctQyy74N5XzIlUWRI7+DKjp0nRA2cQUhgzSOmwmpOcS3Eng mNbXt5SaK3pyxOcg6KxwCA+90CozRDTihTtY7Qz6+a0C4XWWUpYXGAA5kHEAF37F24OP PBhBf8tt/irlO1Kx9TmJZToUx8wSd6lfHyx60dVRG/D2tBZXpur5pNGYEp8Ic77JnfWv PV8LBWe8UWBvrrDLtlfr3lwzxRPEE+dyzd+BOPX1IIO6gLVen/tn4Bhk/hbzMmIgDraM FmmvsVIwfm/+KWZnXLGw4RfZAOrJTMZWttfPGRu8dqrMxitYNZk+XMq/bgWzCDPuuCcn 0COQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QXtWYu3k26efdjnMd2Pt42jkFdW4b3H42VfJHmp983k=; b=QJghRzqOiDMTX6KajvydeDQbggaa+HUlZoYvuVkV+fKG5G0SsJIP3ZK/BNe3WYyYYS xtTSChoAD9MV3ozGtlPj92NhTEVnc8be0owppJwt5qrYBISJEUuVgK/TBSOVpH8Y7kjw 6HYQv2/fxXv5l5EuMmojKXydK2iCfjyxib5us+hUUWwAJ2pn8VvSvYeAXPldBEgrw6ez ELK+bXsOJEXTN9NcKMuvQ88txFaUTjsWdz2z1oIlAkB2Dpg54PJQHR+QBslSdWXrXNYa KftygeZ8v2NcAtEFTZu3LqvGYWr/4iANDBXCKZIz6HCX+qVJT8R5lfNr0JMdO+pKfihW JWVw== X-Gm-Message-State: AOAM533rQgBzK1d8cHazQCi5DMGR66TSwFqR0s3XMcbgFtTJXUu/eKpZ 1xXCEaG1VXhk7z8/txEirawQFvhOeztLYg== X-Received: by 2002:a63:db41:: with SMTP id x1mr7400774pgi.474.1634271286926; Thu, 14 Oct 2021 21:14:46 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 67/67] target/sh4: Implement prctl_unalign_sigbus Date: Thu, 14 Oct 2021 21:10:53 -0700 Message-Id: <20211015041053.2769193-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. The Linux kernel does not handle all memory operations: no floating-point and no MAC. Signed-off-by: Richard Henderson --- linux-user/sh4/target_prctl.h | 2 +- target/sh4/cpu.h | 4 +++ target/sh4/translate.c | 50 ++++++++++++++++++++++++----------- 3 files changed, 39 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/linux-user/sh4/target_prctl.h b/linux-user/sh4/target_prctl.h index eb53b31ad5..5629ddbf39 100644 --- a/linux-user/sh4/target_prctl.h +++ b/linux-user/sh4/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 4cfb109f56..fb9dd9db2f 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -83,6 +83,7 @@ #define DELAY_SLOT_RTE (1 << 2) #define TB_FLAG_PENDING_MOVCA (1 << 3) +#define TB_FLAG_UNALIGN (1 << 4) #define GUSA_SHIFT 4 #ifdef CONFIG_USER_ONLY @@ -373,6 +374,9 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc, | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */ | (env->sr & (1u << SR_FD)) /* Bit 15 */ | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ +#ifdef CONFIG_USER_ONLY + *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif } #endif /* SH4_CPU_H */ diff --git a/target/sh4/translate.c b/target/sh4/translate.c index d363050272..7965db586f 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -50,8 +50,10 @@ typedef struct DisasContext { #if defined(CONFIG_USER_ONLY) #define IS_USER(ctx) 1 +#define UNALIGN(C) (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : 0) #else #define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD))) +#define UNALIGN(C) 0 #endif /* Target-specific values for ctx->base.is_jmp. */ @@ -499,7 +501,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -507,7 +510,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -562,19 +566,23 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_UB); return; case 0x2001: /* mov.w Rm,@Rn */ - tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, + MO_TEUW | UNALIGN(ctx)); return; case 0x2002: /* mov.l Rm,@Rn */ - tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, + MO_TEUL | UNALIGN(ctx)); return; case 0x6000: /* mov.b @Rm,Rn */ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB); return; case 0x6001: /* mov.w @Rm,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESW | UNALIGN(ctx)); return; case 0x6002: /* mov.l @Rm,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESL | UNALIGN(ctx)); return; case 0x2004: /* mov.b Rm,@-Rn */ { @@ -590,7 +598,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 2); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); } @@ -599,7 +608,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 4); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); } @@ -610,12 +620,14 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1); return; case 0x6005: /* mov.w @Rm+,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESW | UNALIGN(ctx)); if ( B11_8 != B7_4 ) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); return; case 0x6006: /* mov.l @Rm+,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESL | UNALIGN(ctx)); if ( B11_8 != B7_4 ) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); return; @@ -631,7 +643,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -639,7 +652,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -655,7 +669,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -663,7 +678,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -1257,7 +1273,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); - tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -1273,7 +1290,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); - tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, + MO_TESW | UNALIGN(ctx)); tcg_temp_free(addr); } return;