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[209.51.188.17]) by mx.google.com with ESMTPS id l3si8745064qkj.3.2021.10.12.19.47.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 19:47:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F3goKJDc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40448 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUJ7-0004CQ-Rs for patch@linaro.org; Tue, 12 Oct 2021 22:47:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56618) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUHY-00047O-H9 for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:16 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:39733) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUHU-0004iX-2f for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:16 -0400 Received: by mail-pg1-x52c.google.com with SMTP id g184so885733pgc.6 for ; Tue, 12 Oct 2021 19:46:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wpoZicnTiBlydK+sFdKdK9FSFNaqNFWg+Zx3DgtSaaA=; b=F3goKJDcYjAVrFgq4lCLdpqk2sIyOuqVnptOLqK62FClFhat4mwElRypmysBln4x7c m7F5LFV4H6eiW5AZ/D68jPj53GOBgmmlhwelhLtnyjWzo3ipLLw+4DvH0ZZrzTO8xq+g 663BoRduFvve14z4JrBXJCNmhkkqm+9YtqGqbbChzPFbaArZnbNe/R9x6qBuXvqq/pts k4flv57mbNixCXfLwJQjZ8sgR1WACUA72QuwW3HTtjBpRoLXCfydAu+RCuVj91qbz9jq IUlYaY6eMNAQzt7TcG5c9yAQmK8qaeJcTmyyfLbjo909jXcAGeB4VHVajZfWVAZ7ZKb5 qOEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wpoZicnTiBlydK+sFdKdK9FSFNaqNFWg+Zx3DgtSaaA=; b=LevlYXDZj8NbG7xEe0kdt1kVncdMrJBbRx9JnPTCVJy3PPPEMiNG3h4lg6uvGeUjRV OJ/eJm+Fh4NFUrib52yQHrzEcpw1iJLLhXqqeyKxANnd/05y7NxEV+KcXtLWjHDKXm0t foHCq1qKeul9fOJkyKx9JD0a73oWzoUy5MNd4oFIQNn1NwiLSwbjPcArUkEEU2Yx3ZwQ OEXRzZgqY+Awr+eDA4FitfUSfGcUMNS683xHoGODw51kZPw4de/sHkYp2Tya1IuXskar Ht8cAS+7JzDudLoYFg84k0RzwcbF1Jyh3t28v7f0w9N8F5Rmc7DDYX0Ht4h66P5wBk7V rs5g== X-Gm-Message-State: AOAM532hn3eQB6W7zPwfVT+hdyqGCDvpBD7N1jSQLhrRe87c6Wfe7FD3 vPepWAn4jTbraP1UpF/TTokP/UOdXM4= X-Received: by 2002:a63:7d42:: with SMTP id m2mr25763912pgn.349.1634093170740; Tue, 12 Oct 2021 19:46:10 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/48] hw/core: Add TCGCPUOps.record_sigbus Date: Tue, 12 Oct 2021 19:45:20 -0700 Message-Id: <20211013024607.731881-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a new user-only interface for updating cpu state before raising a signal. This will take the place of do_unaligned_access for user-only and should result in less boilerplate for each guest. Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) -- 2.25.1 diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 8eadd404c8..e13898553a 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -135,6 +135,29 @@ struct TCGCPUOps { void (*record_sigsegv)(CPUState *cpu, vaddr addr, MMUAccessType access_type, bool maperr, uintptr_t ra); + /** + * record_sigbus: + * @cpu: cpu context + * @addr: misaligned guest address + * @access_type: access was read/write/execute + * @ra: host pc for unwinding + * + * We are about to raise SIGBUS with si_code BUS_ADRALN, + * and si_addr set for @addr. Record anything further needed + * for the signal ucontext_t. + * + * If the emulated kernel does not provide the signal handler with + * anything besides the user context registers, and the siginfo_t, + * then this hook need do nothing and may be omitted. + * Otherwise, record the data and return; the caller will raise + * the signal, unwind the cpu state, and return to the main loop. + * + * If it is simpler to re-use the sysemu do_unaligned_access code, + * @ra is provided so that a "normal" cpu exception can be raised. + * In this case, the signal must be raised by the architecture cpu_loop. + */ + void (*record_sigbus)(CPUState *cpu, vaddr addr, + MMUAccessType access_type, uintptr_t ra); #endif /* CONFIG_SOFTMMU */ #endif /* NEED_CPU_H */ From patchwork Wed Oct 13 02:45:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515678 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6081583ime; Tue, 12 Oct 2021 19:51:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxtCHXQOJPCdnzSpvsOVzRMwuETCXTfUCGp5SMHJNTY0fxu20fWA+RQHOR+AAIGXOVffbbJ X-Received: by 2002:a05:6214:628:: with SMTP id a8mr21961722qvx.21.1634093516381; Tue, 12 Oct 2021 19:51:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634093516; cv=none; d=google.com; s=arc-20160816; b=tuQPbwmLS+ewHD2oYn36Xy9Antx1cfFzalxvITN43ZUh/oD9RYVKbdgLuRkXcKatWy 4Z4175GvjeLmiD7LBSPvN6W0yO0HYaq+i/J/iRV429WpunqKGWxjGKLyoZZs1qrANn74 1KNewJs9NCNuvtdsBdeZwFKSG/ZhAPo7WkdMuGo8inDtp04ofQnr6u6JLi53sGE+csbN HGVM0WK4/oyXhNne6vXcuZ3eiELXzmEMwnoKJPnjNzV9oRHX6/p6byPZUyMeG5yQIyEQ bAbKZNwJOIia/hjVEBo1z+P87KXa1AD+dWQSw44w9sL1SFQTpg5ukqsYxrs6lwvyJv71 yoRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=67r73sMxmFAFlBR0ViNOs8odKIpwZUQrX4e2focSvME=; b=dR5VDrgKByWhyUfX41f+42H8nkCgxVCCTuDFOesuy+6OwA8Z8mPUrCY4UqAuFcaHSi 2+smoZ4lu0pA+7uslpYZK253zH5wZHg/ohY98LJlGAuc1TqEdi78gh0GNdE/03jhA5Mv cN9QFxj3T0Y+pRGdQ2SRVbKKbhy1B8jteQ2clBfMYzxVlhP94DOQzpcjLKZovMNnLMgJ 0Up02SFFfMp3D6L60kqNM4SyeKF3CmwqHvZsQbFGaz3ueEsoPABj1IVv7Ao60NPS0YWP ZEwGbhB7NMjvm3otENSbyZN7DuKeMnxIWr3E9oidFIUATfSqEXVjFpl4ru5cb5Xp4iIK yDEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NQbkrqfs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t21si9583255qkj.109.2021.10.12.19.51.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 19:51:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NQbkrqfs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57470 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUN1-0007Nh-TP for patch@linaro.org; Tue, 12 Oct 2021 22:51:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56626) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUHY-00047b-Ql for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:16 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:40831) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUHV-0004iu-9V for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:16 -0400 Received: by mail-pg1-x536.google.com with SMTP id q5so880124pgr.7 for ; Tue, 12 Oct 2021 19:46:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=67r73sMxmFAFlBR0ViNOs8odKIpwZUQrX4e2focSvME=; b=NQbkrqfs0egp/cKGs4184FmagjnKIjA+4rI0Wpp55mzG0OycYcQ76V2fStyNyhsm/Y CixQhytSUYd2axE9lxCx61G4k96vi064v3Fbg+nVjB1pbKgaQcvJ+LUpdiayXGZ8yJDW ToNa76tWTHnPwA3M0dtX7bJ34VLcpteznj92sQN1Y9tGZrDvnCB4yaYgsWAjqTGZZK6A op3y9daij33C62Y1DKecuyybVS0pUMkWPya+7BaFNqD9zdC0j1b3bSgyKUMYYMmVh+1J acjndy/nUznqAjcodELPaXfD3tnGmeNB5/MlSYkFptLGwghGqMeRvbS4O7DLR4FedxRZ Eckw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=67r73sMxmFAFlBR0ViNOs8odKIpwZUQrX4e2focSvME=; b=WULtpRExxYS0GYBwhQekCAVN0fuKBdU1aY8DMFZy+w0O3IYBiW0w99UhmCc6AEDH3G h8TOQMRgFswTtqN8/7x4VikPPVTKAdW496XL8817tGOGJ8wnOQoGI0FvzHGCSXxzrEq1 XrdftnLJ6BKLGT8H+695kbcSrCFq9fZgTS8IJsk06WkLqYDryD12rzCu9C2ZQvHW/kwD KRQ4tdvvV8yEQWfOy2qVfZFmT31SNYqLIw28W3gT9AfS/d7vA1fbFBJF4wF/765TnnZW 2NLVpnQvEw2ONsOB+VDEJQY0j7KyoYj+SENotDIdY4XlektMtF0fUPB6MLZcsZns+8xJ eJrg== X-Gm-Message-State: AOAM530x79RSZqnzDHKQGVr4ulNbTZ3kRDVoTbgPeIUzVM2bx9c/zMX3 tjNcBd7CT7ZsAXW+4Oq6DlFkRO5eCZZ0hA== X-Received: by 2002:a63:d34f:: with SMTP id u15mr25585438pgi.200.1634093171930; Tue, 12 Oct 2021 19:46:11 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 02/48] linux-user: Add cpu_loop_exit_sigbus Date: Tue, 12 Oct 2021 19:45:21 -0700 Message-Id: <20211013024607.731881-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a new interface to be provided by the os emulator for raising SIGBUS on fault. Use the new record_sigbus target hook. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 14 ++++++++++++++ linux-user/signal.c | 14 ++++++++++++++ 2 files changed, 28 insertions(+) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f74578500c..6bb2a0f7ec 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -700,6 +700,20 @@ void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, MMUAccessType access_type, bool maperr, uintptr_t ra); +/** + * cpu_loop_exit_sigbus: + * @cpu: the cpu context + * @addr: the guest address of the alignment fault + * @access_type: access was read/write/execute + * @ra: host pc for unwinding + * + * Use the TCGCPUOps hook to record cpu state, do guest operating system + * specific things to raise SIGBUS, and jump to the main cpu loop. + */ +void QEMU_NORETURN cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, + uintptr_t ra); + #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/linux-user/signal.c b/linux-user/signal.c index 9d60abc038..df2c8678d0 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -706,6 +706,20 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, cpu_loop_exit_restore(cpu, ra); } +void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, uintptr_t ra) +{ + const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + + if (tcg_ops->record_sigbus) { + tcg_ops->record_sigbus(cpu, addr, access_type, ra); + } + + force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, addr); + cpu->exception_index = EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, ra); +} + /* abort execution with signal */ static void QEMU_NORETURN dump_core_and_abort(int target_sig) { From patchwork Wed Oct 13 02:45:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515674 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6080435ime; Tue, 12 Oct 2021 19:49:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyEC3fntLojzc/ItgeiJX0IEMGvufcqeGR4/7CX/63kdXW9vEvKvgdxgWUwYrVdKvYrdPdh X-Received: by 2002:a37:6cc6:: with SMTP id h189mr22803152qkc.321.1634093374850; Tue, 12 Oct 2021 19:49:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634093374; cv=none; d=google.com; s=arc-20160816; b=AUgPzsduk0ICahamM4cXn+ijYeLfH4SiYpSWz/IwHepkiQNmmL0AyMtl9sKJ7W4Ivo XBM1MXdVrOe4ql3nVfTgTbkGCTMPnVuB9v3skHDAuATgdHvtE+TI1deIQ6ugJmXsLmOv 7X1yPYtFOnLhPFqeX33R6AalYf7zYFegqrWFwljmW2x65WT8Z3LFSThNrNuHtPSRuJu7 pyjUWb5GAZSo8OQCCmhczmnRQprUI/cqV+hROo5S+3g2TfVM6vM/T/TmCuaQcMDf1lAi pZ4tOeowZUi6j4vacSuO8rNJJlhhNvec1VpJU/TDvDmHZY8tm9by/kWg2e3T1mXBJUGc TWww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=volRuwbkN3bEYM3ufnxsPhODmGd5KdNsFtolY6QzjdI=; b=f5RLFkxhpX6a+eOeQANqSI/Jit7oqhej/PodR5cCN9a/Kw3Bz9V04PTjdd1X8bIM/R dl0MocKor9JJN0wwd4dItm5WRLGWoFLYm1G3qG6Tvh8LatzOS69FhNdEFXs+rLA+lXZx waQsJ6H35wGh4k4o3FjUs3cuQCsWM98O9sjUp8KrXvWVHIBEhMibVHEnBo7A+r+JuLR4 +u7KTklHFIEScvPn59mRw81ftVpRSLxR2tBINkRK2yKhL5tP30dgV8UiQrnBWPcl8r+v kSsmuuVP6RWRiTZPBz5BmTM7zlBu1oHAGG3G3PvMMIvAOJO1Ew65+Wd5cNc5ZzmrkKZm 3qNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uRcS+hJr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- linux-user/alpha/cpu_loop.c | 15 --------------- 1 file changed, 15 deletions(-) -- 2.25.1 diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 1b00a81385..4029849d5c 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -54,21 +54,6 @@ void cpu_loop(CPUAlphaState *env) fprintf(stderr, "External interrupt. Exit\n"); exit(EXIT_FAILURE); break; - case EXCP_MMFAULT: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID - ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); - info._sifields._sigfault._addr = env->trap_arg0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_UNALIGN: - info.si_signo = TARGET_SIGBUS; - info.si_errno = 0; - info.si_code = TARGET_BUS_ADRALN; - info._sifields._sigfault._addr = env->trap_arg0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_OPCDEC: do_sigill: info.si_signo = TARGET_SIGILL; From patchwork Wed Oct 13 02:45:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515672 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6079674ime; Tue, 12 Oct 2021 19:47:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyAYPVxo67mZzbpJO0UhS6Llbtb9mnQ1dLfautWeAb/81rsAHsjSYnkHyokFgujoXqQnyFm X-Received: by 2002:a05:6214:226e:: with SMTP id gs14mr33609682qvb.4.1634093274095; Tue, 12 Oct 2021 19:47:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634093274; cv=none; d=google.com; s=arc-20160816; b=W2EY0MXBcW8r848i6D9LFJp+37DvzfAH9gsoqNpr85FDqv+ZH9W0jGyZB0w/RiwZBn SGDhQWZ7hoDRWs2WvDQjVo8lZoJmRSYKo3vnZZGxxXMNM3e77JiLxt+46GXHTGDuTuNN GMLs442scUQdIl+DMsccTk62lnExfysYky6dovivgG9r+/XPdbIV9qhoiAFrr49TB2Hc yXQ9z9Uu34iGUwR8ApTsaD9NwIo2iIDpK3gF/J+YWY6tL//g96oScMuOUGST9JiqKi0s zYs+eixA0tf068qeijdPvgLVvnf62N4+KHVGiiyPq/GNfl1INlY1iPZby/4Nip4SmSsq jEfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AiCyvdTR/3QA/VxcdfSHeMxoA2jAV+mFfUYWeOlFIz4=; b=WmFhmmFDnCIgYOkLAPel6JHtRNSkozfe38iXQFJ+1eV/lJMrEXIzs4Wb9XxNbTlxWl y4CHZhObMVZw2P+srXw6y9ac21A714Nma2x5jWl5UMytcChgah65RS+EOwS8MeJU+i87 byeAMNLkQ5qv5r/hCMgVZO/uKWogX2MaTewJBeQ994TX4gDBqTXK5Ww8Gyd3KpSfH0Lm MjmkYgxOonWDCOKjFjRue9UBxHZB/EhaHPZbK5bjs9YHyGnjRcX5jyTrnsY6x3lFN8AH 7cOU9gYyMfr0V6Ucu531Di2YoHyf3qVyH2w71xJZYuhpv5IDIbnGBOKGvJ/oULtxMXIm Pj4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sEm9BYPE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This means we have to handle the exception ourselves in cpu_loop, transforming it to the appropriate signal. Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 ++ linux-user/aarch64/cpu_loop.c | 12 +++++++++--- linux-user/arm/cpu_loop.c | 30 ++++++++++++++++++++++++++---- target/arm/cpu.c | 1 + target/arm/cpu_tcg.c | 1 + target/arm/tlb_helper.c | 6 ++++++ 6 files changed, 45 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/arm/internals.h b/target/arm/internals.h index 5a7aaf0f51..89f7610ebc 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -548,6 +548,8 @@ static inline bool arm_extabort_type(MemTxResult result) void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, MMUAccessType access_type, bool maperr, uintptr_t ra); +void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr, + MMUAccessType access_type, uintptr_t ra); #else bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 034b737435..97e0728b67 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -79,7 +79,7 @@ void cpu_loop(CPUARMState *env) { CPUState *cs = env_cpu(env); - int trapnr, ec, fsc, si_code; + int trapnr, ec, fsc, si_code, si_signo; abi_long ret; for (;;) { @@ -121,20 +121,26 @@ void cpu_loop(CPUARMState *env) fsc = extract32(env->exception.syndrome, 0, 6); switch (fsc) { case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + si_signo = TARGET_SIGSEGV; si_code = TARGET_SEGV_MAPERR; break; case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + si_signo = TARGET_SIGSEGV; si_code = TARGET_SEGV_ACCERR; break; case 0x11: /* Synchronous Tag Check Fault */ + si_signo = TARGET_SIGSEGV; si_code = TARGET_SEGV_MTESERR; break; + case 0x21: /* Alignment fault */ + si_signo = TARGET_SIGBUS; + si_code = TARGET_BUS_ADRALN; + break; default: g_assert_not_reached(); } - - force_sig_fault(TARGET_SIGSEGV, si_code, env->exception.vaddress); + force_sig_fault(si_signo, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index ae09adcb95..01cb6eb534 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -25,6 +25,7 @@ #include "cpu_loop-common.h" #include "signal-common.h" #include "semihosting/common-semi.h" +#include "target/arm/syndrome.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -280,7 +281,7 @@ static bool emulate_arm_fpa11(CPUARMState *env, uint32_t opcode) void cpu_loop(CPUARMState *env) { CPUState *cs = env_cpu(env); - int trapnr; + int trapnr, si_signo, si_code; unsigned int n, insn; abi_ulong ret; @@ -423,9 +424,30 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* XXX: check env->error_code */ - force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, - env->exception.vaddress); + /* For user-only we don't set TTBCR_EAE, so look at the FSR. */ + switch (env->exception.fsr & 0x1f) { + case 0x1: /* Alignment */ + si_signo = TARGET_SIGBUS; + si_code = TARGET_BUS_ADRALN; + break; + case 0x3: /* Access flag fault, level 1 */ + case 0x6: /* Access flag fault, level 2 */ + case 0x9: /* Domain fault, level 1 */ + case 0xb: /* Domain fault, level 2 */ + case 0xd: /* Permision fault, level 1 */ + case 0xf: /* Permision fault, level 2 */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_ACCERR; + break; + case 0x5: /* Translation fault, level 1 */ + case 0x7: /* Translation fault, level 2 */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MAPERR; + break; + default: + g_assert_not_reached(); + } + force_sig_fault(si_signo, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a18a58ca0..a211804fd3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2035,6 +2035,7 @@ static const struct TCGCPUOps arm_tcg_ops = { #ifdef CONFIG_USER_ONLY .record_sigsegv = arm_cpu_record_sigsegv, + .record_sigbus = arm_cpu_record_sigbus, #else .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_cpu_exec_interrupt, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 7b3bea2fbb..13d0e9b195 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -902,6 +902,7 @@ static const struct TCGCPUOps arm_v7m_tcg_ops = { #ifdef CONFIG_USER_ONLY .record_sigsegv = arm_cpu_record_sigsegv, + .record_sigbus = arm_cpu_record_sigbus, #else .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index dc5860180f..12a934e924 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -213,4 +213,10 @@ void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr, cpu_restore_state(cs, ra, true); arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi); } + +void arm_cpu_record_sigbus(CPUState *cs, vaddr addr, + MMUAccessType access_type, uintptr_t ra) +{ + arm_cpu_do_unaligned_access(cs, addr, access_type, MMU_USER_IDX, ra); +} #endif /* !defined(CONFIG_USER_ONLY) */ From patchwork Wed Oct 13 02:45:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515677 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6080467ime; Tue, 12 Oct 2021 19:49:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyBhLyseZz4GEB6pzarSVpVaSrophIydF+4JnZA1fQbBMs/0KPLb16/5awpux4aydYB1jJa X-Received: by 2002:a0c:9c0f:: with SMTP id v15mr33525728qve.8.1634093378474; Tue, 12 Oct 2021 19:49:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634093378; cv=none; d=google.com; s=arc-20160816; b=v9mDyTre3Tcz++NPadwl+Xhm9+AZx2/1wa3i+hk7DisqUW0+3tGqL8OGODj3xDWTkr gxRZQjXrOvflOMO72bcd23JKJsIW3sXimcxh+v4UiLV+gmgKbzZKu9C4H2qhDX2AB907 //8bJP1hka69WEU3/+csJnNXun+/5uy2GDkRlb1LEQsMVehgLb1r+COlrnUtzYMIl88U /Sa6pMFkKKBkQPatheTeeWdDo3Z8jNZ/afmOaBLqbZWAPzFgqlkofUpMNfnzEHgfY469 ypHHuWHJ7EfqOudLD11mPH3rjL3Q+p24vWYTjTV7bSH2KiJu6xMdw2buwSyaKtd0dufX bouw== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id x7si11843090qkp.312.2021.10.12.19.49.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 19:49:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yKI3Oslf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49276 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUKn-0001sv-Vi for patch@linaro.org; Tue, 12 Oct 2021 22:49:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56644) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUHZ-00048k-L8 for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:17 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:46686) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUHX-0004lX-Pb for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:17 -0400 Received: by mail-pl1-x62f.google.com with SMTP id 21so784967plo.13 for ; Tue, 12 Oct 2021 19:46:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=fbekWwHWkYvCfsIkbs+I86iCi1VerGNgnv3kr2JgTV8=; b=yKI3Oslf+ydNniICaebBvl2IVQ8bxJd6Pqb06kvwFHTSAqVVv+SUvWy7WSG/TgHyj7 q8oqlzajKqTX+XAb4clXSVIKfKbH4sJ569V9UWh3yXvWK0EW5qz4UkoA7oyrNEyrKWvz VVijhmESu9l4GjZdIdfv19V1HyQf2imVe47dGqHMJy6VCG6DgFMAaqnEF21kGxQ4h76+ eVzrMyLp7FTen+CUFVHhisjwBQHEuAfC3hwx1uca7HNEVkLJGKQeqILJlGdR9wLsmSsU pM+EzThCalEPO5PMvbUPsonnYsD6jG50mCAE+bnwnALz92YF2VtfoOupQmWTsOeTeWzE yvVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fbekWwHWkYvCfsIkbs+I86iCi1VerGNgnv3kr2JgTV8=; b=iEMdD6qI2S8NEX2uuEa8gP1HjAbb+je96nMyM3V53+5lAx1gkvLZXs9m/iBYuuwpB0 z30SnamM9nVW3nYFUdMPfUORIx6UZwjjb3KGe0m/k+RmWWBkwEJJSuH8ACC9m4EWtgw+ Lbz/At6nQdllrIntyj/DVor56eKUdEBs8H0xKupvNwG9PlT+O1nWlrrirmw0s8KPK2p5 XDJHYT0GSK0vJK+5OEEGXVJCPHOy06r+6YGofzEdwcbax/fI9hFNW6jEF9nanCrONlyL aam1YO9lanj8HOYXhlYyTeQs+psEOcF1AfNggU4jBLJROkuhe0HUif9WXgcbIJBdspfv 0/5w== X-Gm-Message-State: AOAM531ENByWbTtuofpBqUO+uj9nEbSsYxpLcN5/RE0f0ygsosRh/2Dr 6UhdG4qjQt5Q6FvP9dMUzLro9Z8fbUMZEQ== X-Received: by 2002:a17:90b:2493:: with SMTP id nt19mr10659306pjb.78.1634093174311; Tue, 12 Oct 2021 19:46:14 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/48] linux-user/hppa: Remove EXCP_UNALIGN handling Date: Tue, 12 Oct 2021 19:45:24 -0700 Message-Id: <20211013024607.731881-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will raise SIGBUS directly from cpu_loop_exit_sigbus. Signed-off-by: Richard Henderson --- linux-user/hppa/cpu_loop.c | 7 ------- 1 file changed, 7 deletions(-) -- 2.25.1 diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index e0a62deeb9..375576c8f0 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -144,13 +144,6 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f = env->gr[31]; env->iaoq_b = env->gr[31] + 4; break; - case EXCP_UNALIGN: - info.si_signo = TARGET_SIGBUS; - info.si_errno = 0; - info.si_code = 0; - info._sifields._sigfault._addr = env->cr[CR_IOR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_ILL: case EXCP_PRIV_OPR: case EXCP_PRIV_REG: From patchwork Wed Oct 13 02:45:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515671 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6079672ime; Tue, 12 Oct 2021 19:47:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxqN+4H+izfV9Larp43HSFD/bdLQImKadjsVob68J2l5v696PSP4tc6hoJ5Z10QPcJeoijf X-Received: by 2002:ac8:8c:: with SMTP id c12mr26600257qtg.12.1634093274025; Tue, 12 Oct 2021 19:47:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634093274; cv=none; d=google.com; s=arc-20160816; b=0lyUD0HZsu3TZCuTGfXy+4h+dcnoggoZR3NlD4/74QMRHurxzFtzapJaW0S8sDm74m X862aulxZEsVFzqPtsaX4OIID0MMfbO6i0uBxmpy3B6dhuyYXfKmOHckbqLhTMOrqWn5 vmZvIBjD/ogJASvN+MO6xJfLGZOjmmVFczBSuvLrMMmreA5Jkj/fefrJ0snJuH+IYRii 2JMmulxyXUoEUDOS879dvHdXXbYC1vD2xQ5aEclbBOg8jQq+HwUpiTAIF1xHTkRz1C2Y nRxdpCpd4NMRKKYPsMUpCbma7EIEPU3Q+WO/FWmXlvKKCpIxUiqmlXv64TEnoksnmf7W O/1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6inZETYo7qpmjRK6t8YVcWmKQsxE4jryCUSCrlDOgJc=; b=o9KC6ZVt/0cb2LGqL6drFXoZVsFrQ9y93Cz2Ffi4q6+RSMOF5HGuMahBfD2yaGFHyk XualWozK7h/Us6rL5AGsloapkts6Cp3xa2uJ93fPffNcPmxVhIZx8tg5WTgLd75iR4NY Qp3foYJRcU6TPuIJzGkfh8VVOabc9JWsgfAXXXP1ScIGi/UMV5GKRzP0anZLDid8B4JT Wwl7MND596S9qxoGMeoXL3SrZiKyS8JBN0GZujzLi964kdsbN3QzJaftZZFFnFLPlOPN C/CCIl4MwIl0QVr7zE28u4lm+1TF4uOrUZr43++HfUQ5xyhAwuYzqb++3fyGItXHjUem pvxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ig7PRgpd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h16si12402161qko.127.2021.10.12.19.47.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 19:47:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ig7PRgpd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUJ7-0004DK-HO for patch@linaro.org; Tue, 12 Oct 2021 22:47:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56652) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUHa-0004A4-BQ for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:18 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:43947) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUHY-0004ly-QJ for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:18 -0400 Received: by mail-pj1-x102e.google.com with SMTP id k23-20020a17090a591700b001976d2db364so1137572pji.2 for ; Tue, 12 Oct 2021 19:46:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6inZETYo7qpmjRK6t8YVcWmKQsxE4jryCUSCrlDOgJc=; b=ig7PRgpdG8n7pzAMr6+UCtGuWTa1lI5O+SsKxqvAYQemcR8a7yS5tMZRhE4Q/2CbVK ajYp3L8EPG8zAqSFljv/y56lcfhOgl7gXii+HGbSUBv5IjUocANYQFG58MBZjNEPo6VJ 5MNykvGDteAL1Od7uelu9roOiwc5/Hks+UUFaZJ5I5QdZlsh9hVM18tE4Hh7qb0zqYu0 Ik0v32E/y5JFODWbZJ14fz6HsndpjHrNidYADHZxaG5B72NcXt071NWqKSNhXXw9BD1u lxflxB2nFD2MDNUu9HWG831ze+nZxTRH8g8tPYaBZSdMt1LkGSfF85F+UaCTgcNmba5V xiMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6inZETYo7qpmjRK6t8YVcWmKQsxE4jryCUSCrlDOgJc=; b=1GhRtDZcNvMIipfZLvWj8c3r0dbcKM9RlibDTroKj0q7LTnGHgfXP8ep3BzEdCoPuZ oVMUvGDHY1X15oWsHELTeELOnU5aLYO8fLNE5bBihXYUrW89lrdTPKHz6tBNHQFF3Y62 iOmMoQ+1n28ViUYfl5klt6xTauVtDJzzQfvynNv5uXveSlDgSR03TG/FNAk4YfIOweZQ Akub2fEmBsIStuSkB6BVCkrvyQxa9LlNKLq5vDVVzF4nOiVapEaURbidlNXassjDfuqo kVhm5M3nNzuVY2uGncf9nUAbFQXUfN5qhHPb+bWpFc6yXrCciu9vW/pKqDpD6TM8qtlA 0rHA== X-Gm-Message-State: AOAM5304wIgGndUSMHYM3q6Da8pBOMpGloJ+ywpHKAlbfVx6sAMtXQbr dgMjMNHP6IQPGzoAr/d738XzBRuxFk3a2g== X-Received: by 2002:a17:90a:a88a:: with SMTP id h10mr10369400pjq.226.1634093175440; Tue, 12 Oct 2021 19:46:15 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 06/48] target/microblaze: Do not set MO_ALIGN for user-only Date: Tue, 12 Oct 2021 19:45:25 -0700 Message-Id: <20211013024607.731881-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The kernel will fix up unaligned accesses, so emulate that by allowing unaligned accesses to succeed. Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a14ffed784..ef44bca2fd 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -727,6 +727,7 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) } #endif +#ifndef CONFIG_USER_ONLY static void record_unaligned_ess(DisasContext *dc, int rd, MemOp size, bool store) { @@ -739,6 +740,7 @@ static void record_unaligned_ess(DisasContext *dc, int rd, tcg_set_insn_start_param(dc->insn_start, 1, iflags); } +#endif static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, int mem_index, bool rev) @@ -760,12 +762,19 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } + /* + * For system mode, enforce alignment if the cpu configuration + * requires it. For user-mode, the Linux kernel will have fixed up + * any unaligned access, so emulate that by *not* setting MO_ALIGN. + */ +#ifndef CONFIG_USER_ONLY if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, rd, size, false); mop |= MO_ALIGN; } +#endif tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop); @@ -906,12 +915,19 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } + /* + * For system mode, enforce alignment if the cpu configuration + * requires it. For user-mode, the Linux kernel will have fixed up + * any unaligned access, so emulate that by *not* setting MO_ALIGN. + */ +#ifndef CONFIG_USER_ONLY if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, rd, size, true); mop |= MO_ALIGN; } +#endif tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); From patchwork Wed Oct 13 02:45:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515682 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6082955ime; Tue, 12 Oct 2021 19:54:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJztDbayLI+AdMbnku/hyBclfMJRolTLE2N4uxiSE2qRTq4ZTYcqIxVaO82KUPCE+eXthYwA X-Received: by 2002:a37:44ca:: with SMTP id r193mr23013157qka.190.1634093656804; Tue, 12 Oct 2021 19:54:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634093656; cv=none; d=google.com; s=arc-20160816; b=wLCugvOz8y8jJ303rVF/zFe5pSkqXqnsKCxjPfbs3Gfb+iP7v4WZ3a0JkXbSgVwIG0 4hRrkaB9Eslf9hyFnhYwdOIHlRXInnFZIKeo58VQVQcFenVYhq0d2W7l3xSeK8Vfbnom ngKU4J1BokRDWebxhJ6v6Ftz4p+8PCWvhtMHFdkmPdnncVyZkvzo+ZjyuTQGPF7r0673 lNHcepGZ2QxemovbI3E/JTp86a07AQnu8ZnYdbihaP4U9ywnhJAyPovzY3O+UhyytSwt QaRz6KWzVHfLM/6r6gVYS2fIb+T/3aV5nzGehYBzhXXdpH8bibwrmc/T4xwsVyPnCIf4 eOUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=54O7y5F6cil48JbVjJeuP4tBSWG4MHFPBxntrZflWpI=; b=dmY8oZ50MdEBCmBCux7u/Nm+2tHSAZj/XVskCo8KO+/WBb73D6zmWbxJJWjBDnHbpj 8OB2I8CFb5ae2MWyoIyLS9Pi7ngMZLivYFC2I1ApreXi07S2uKf90m58oBSujV0INZ98 4D5vyrz6syKkHL6iMTpRAtmBgaudQcCP1vWHI2OhHTC205nT7aBfQ83u/f42PgAV4V0S BmNAedd5ymdT0brLcK9m6lSfyRoEWif+I+Vb6ib8KvxUNOlB+qpUnZA6jclRaqyw4Ebl VZEz9FF7WNDWZ4Q+PQyAjh8yWPI/UHenbw1XSyJuo1GFiq4K1zGKGKXBD2YOsYE7IMJe wF/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lv3YyLQx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u14si7718319qvv.87.2021.10.12.19.54.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 19:54:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lv3YyLQx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUPI-0004jK-8d for patch@linaro.org; Tue, 12 Oct 2021 22:54:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56678) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUHb-0004DA-Mu for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:20 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:38436) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUHa-0004nM-0k for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:19 -0400 Received: by mail-pf1-x42e.google.com with SMTP id k26so1157625pfi.5 for ; Tue, 12 Oct 2021 19:46:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=54O7y5F6cil48JbVjJeuP4tBSWG4MHFPBxntrZflWpI=; b=lv3YyLQxLme3vKyGGKEiCQFJ+bMDhfxALse0U4TYuoIdTxOE7xWwUmWiT5Z+HSaY0M QFd5NHl0HAE/rNR8Jt/pMVujOVJHixUA3qejy87L6KuQQaqt0Uh8+yJ2r4eaO7ELTZSq ziZpgzp5AaBoNoNvqbFI3Gsb87f0p8NmMADbfKdJkMzY45hGITkRAXqXJPaa2BUnbxD+ pzN2f3S+yJ5k39XOpOIZhfjF4XJOwx/sFa8QpaAS0Gugh9lHM3vIMgwL/iHYjS25qhXg P9KQDJelKmExullvomy8eff9qWj9Zz0q/rrSxB/ll3etagUK5IdwlJ34ydot2SJNPCuf hY7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=54O7y5F6cil48JbVjJeuP4tBSWG4MHFPBxntrZflWpI=; b=v1jO3XJaJKnYYmVL3sp3BqVn/+fKZHfq6I9qafx2qNbiELIqaLoczOXaDTzX5vfQm6 ekpJi+weDv88FgNuEiH5zxMFHLPQtY08D8zziuUD4ZJcyWPUKtEtjeShMgd9w65xmZcU cm1WoyOxMTpkpAIRMfjA7AS5hR8qhuQvaRXAhTgslmGPMe2topFz0OIgqMpjv280hsxf 6kdtpbazvxhyoEIw3JCtj+FxPI3e2b/4Km2GY7E6C/ArAdFm4wfahLGtwYs8Lz1zdGqd proPR011abo1BdrawM20jDSTDUQnuxrXUaVvtXpQOKdT2PicJ8r4pVhng5K0MN7qxYZI QydA== X-Gm-Message-State: AOAM532FhDcY+BOnSZ4t/f6Fq6MvHrEnjWZM11rQ/mKcvyYk2OTeEdMS u0SkcdFfCdt7UcUjv4QV37dk45FTzes7gg== X-Received: by 2002:a63:f145:: with SMTP id o5mr25793340pgk.273.1634093176605; Tue, 12 Oct 2021 19:46:16 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/48] target/ppc: Move SPR_DSISR setting to powerpc_excp Date: Tue, 12 Oct 2021 19:45:26 -0700 Message-Id: <20211013024607.731881-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" By doing this while sending the exception, we will have already done the unwinding, which makes the ppc_cpu_do_unaligned_access code a bit cleaner. Update the comment about the expected instruction format. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/ppc/excp_helper.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index b7d1767920..88a8de4b80 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -454,13 +454,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) break; } case POWERPC_EXCP_ALIGN: /* Alignment exception */ - /* Get rS/rD and rA from faulting opcode */ /* - * Note: the opcode fields will not be set properly for a - * direct store load/store, but nobody cares as nobody - * actually uses direct store segments. + * Get rS/rD and rA from faulting opcode. + * Note: We will only invoke ALIGN for atomic operations, + * so all instructions are X-form. */ - env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; + { + uint32_t insn = cpu_ldl_code(env, env->nip); + env->spr[SPR_DSISR] |= (insn & 0x03FF0000) >> 16; + } break; case POWERPC_EXCP_PROGRAM: /* Program exception */ switch (env->error_code & ~0xF) { @@ -1462,14 +1464,9 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int mmu_idx, uintptr_t retaddr) { CPUPPCState *env = cs->env_ptr; - uint32_t insn; - - /* Restore state and reload the insn we executed, for filling in DSISR. */ - cpu_restore_state(cs, retaddr, true); - insn = cpu_ldl_code(env, env->nip); cs->exception_index = POWERPC_EXCP_ALIGN; - env->error_code = insn & 0x03FF0000; - cpu_loop_exit(cs); + env->error_code = 0; + cpu_loop_exit_restore(cs, retaddr); } #endif From patchwork Wed Oct 13 02:45:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515675 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6080456ime; Tue, 12 Oct 2021 19:49:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzTywRdZSIfpN+c5yrDx+YDBlkmn6YB/u8+ctQhIqx+hcP+yiqGbYrkanlZ+9pCX4mCMyJI X-Received: by 2002:ac8:5809:: with SMTP id g9mr27221306qtg.161.1634093377334; Tue, 12 Oct 2021 19:49:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634093377; cv=none; d=google.com; s=arc-20160816; b=oy9UdQFMiTq/J08KJRXZeBnmSqIx69TtFU/iQ7a2FEZ+Qns+aQMGaXtihBXjc66EbG 7rohvk1DnbtHVPG26NSAIFnlx/VPBfZnuQKrk0KcLV3z8Q1NAsRQV4k+lA8usPRCTWfj 7BI/T26Qbz9aJcJKeDWzMFX5StkipITEW4NkOdmNcsrgrQBJCKPvb1CFmodh2lCOSJ7d DlAdU5I6hrxHxHBbKC2AEzSpB9oFYtwb4dId6e/xSieURVIFWohuqyr1iTovRBsEHmUk J9EONLsedv/WplUkI4EsY6bY8U7CejGu/3bX/bGoJH723AmwDDcNIzzvseEgCSPgCZDe HRgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SttDrREQq6hsw1e6wi6gOFRhVJLqzj/IGCKsRbbMdzc=; b=yiiXkNyT8Ukrhm8U2OSYmfJq+rtR0FGVPBZ97Kf2LCNDoAvq6jVGq9FFzyng6btd/V 4v1kQFFX44fmhPbP+uDYWsgNJpou0nMgf70GixHTiL1P1CX5b9Q/Q6XYENhYAkOlCGRn 46vPF5+UbzOSGzjcTZWZ3qUQ8aVBBzFAgGBh2c8RcKc2deZ0jsLBpU7/nGyJF3yiI9Qb tOlC/7QJwByy8w7fyU+/bIpCPnTBA4kDO2mG1cb4gbGvjwdFRMJ88Mkc2PjAxFxsiTc3 KMqpVXr3VC3Xe2CljB3wnAzdi6YDNzzaYRdKMnfST4DkmOvOYb5jzrpfHj8+MKPVlG3O ct8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JsaGtVZ7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Cc: qemu-ppc@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/ppc/excp_helper.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.25.1 diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 88a8de4b80..e568a54536 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1465,6 +1465,20 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, { CPUPPCState *env = cs->env_ptr; + switch (env->mmu_model) { + case POWERPC_MMU_SOFT_4xx: + case POWERPC_MMU_SOFT_4xx_Z: + env->spr[SPR_40x_DEAR] = vaddr; + break; + case POWERPC_MMU_BOOKE: + case POWERPC_MMU_BOOKE206: + env->spr[SPR_BOOKE_DEAR] = vaddr; + break; + default: + env->spr[SPR_DAR] = vaddr; + break; + } + cs->exception_index = POWERPC_EXCP_ALIGN; env->error_code = 0; cpu_loop_exit_restore(cs, retaddr); From patchwork Wed Oct 13 02:45:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515681 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6081808ime; Tue, 12 Oct 2021 19:52:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx7B4uXC0DtBgI2JO8kIthevYoJ6Ez6/gjWFnTMSmo+Ti3vy+5N3BRn4i96jyU6Gt54kNMW X-Received: by 2002:a37:b842:: with SMTP id i63mr22633869qkf.262.1634093538979; Tue, 12 Oct 2021 19:52:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634093538; cv=none; d=google.com; s=arc-20160816; b=mMDqSkOTdMKmBC1N3C7MzipW+WavCXXfam+8wYvcPnF5R8gr8+WKtmWnq0Lo10ojun IzvSOuHtiaHJ/yhgiasXx6DmZeiC64hdrqkQZogQDh40cTA/Om1vOFIWLzVsstsOsZdn 7oz53LM5pj3qOHMe26PKWS8PGsWKjdNFX7wv3UYKj80weqmFPZ8BYl08BEVuBqYTWaWN oAQpZe8RSBPbSzq18xFTAdy45Tumyb3jVhPryCeV5oqI1Fqx4kewPmcU964pwUpOZ/y4 7FyAKDotnhoDXkWPMuWsZcr3G9oOAyqQ9YOvHxUDD4DK39T5U4TinGB6eCTjkgOY+PA5 y5eg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=edXkrbkqOm07djX1rJHm1DMaa+Lm/qwNrJ4BGEQSsuM=; b=yyJcjQWx6Eqmvh3QwIIR+bgiTCu9PVOtHwwlV+DOhD3TMTZpdDQie97P85bwOG74AF X3NqD7PA27b12cI35a2trMEl1ir16kWRzWEG/5M3LdAehFF/5cDhTm6g5dN2QadJcviD Tu8fE5OcczN2yXWfZPRnETCOf49aA9v2x3DgXlgYf0CS/b26jeTHeN/FHZaPuiqeacoF 7e9NHi1YYroM4BppKUNbuhjIYitvRa1S4oKTm95fSa+x+OHBcXyj5GnkhGBsH5wx0gnX wPzzQUTWHLc6LD6A6oFgmYmEx9SpLSIMPTxlDObDKAVsgbc8xsCmyH8zHXCXqeTKGKUU hDWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LdpsrxsU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/ppc/internal.h | 8 +++----- target/ppc/excp_helper.c | 8 +++----- 2 files changed, 6 insertions(+), 10 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 339974b7d8..6aa9484f34 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -211,11 +211,6 @@ void helper_compute_fprf_float16(CPUPPCState *env, float16 arg); void helper_compute_fprf_float32(CPUPPCState *env, float32 arg); void helper_compute_fprf_float128(CPUPPCState *env, float128 arg); -/* Raise a data fault alignment exception for the specified virtual address */ -void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; - /* translate.c */ int ppc_fixup_cpu(PowerPCCPU *cpu); @@ -291,6 +286,9 @@ void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr, bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; #endif #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index e568a54536..17607adbe4 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1454,11 +1454,8 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb) book3s_msgsnd_common(pir, PPC_INTERRUPT_DOORBELL); } -#endif -#endif /* CONFIG_TCG */ -#endif +#endif /* TARGET_PPC64 */ -#ifdef CONFIG_TCG void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) @@ -1483,4 +1480,5 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, env->error_code = 0; cpu_loop_exit_restore(cs, retaddr); } -#endif +#endif /* CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY */ From patchwork Wed Oct 13 02:45:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515686 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6084274ime; Tue, 12 Oct 2021 19:56:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxxP5SJSCAvijQKNyzVB9HVEFJukUSZYZFADkcQRDvtoXTg6YtnTWaoK55DTAePy3t9ao5O X-Received: by 2002:a37:9e8f:: with SMTP id h137mr1941903qke.180.1634093812479; Tue, 12 Oct 2021 19:56:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634093812; cv=none; d=google.com; s=arc-20160816; b=DQu3qMZVRK2YnxtlUyp4GcTiN9ihGT1J1nt6SmmpWOd7GtC8JaJIs5LjKuvACBwAIR 3RZUfxyPg20ChbFqdlsvJCySrYhOKe9SPQgqZlYnR8x4VtmZsYI6KOXmzjx5D7HyCvcP 6flzZZCK+Zbpnw8o+fBszuIq6o1AnAK+hivqmdRaiIhSedCtwdyExdmAKXATpi5lI6aG 6xJk91E1F+EyU0xivElh2yfRbe9zRwKaBAj18qt8Ov7FP5+zG0Sdd1Uaqjy509FQHF+u 6bupvstGNt9wIHjn++rU3IwYHyuqTfP+itqlSMe8CsqBU+jVN+YaL7yMWBxc/+Vxq7j5 s9Zw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tQ9zUqcauybUZbu3B5IksrNIUQen6fZFWQH9MsgW1Ec=; b=rbJsjCewS4ZdcgvO4ONV8MkqJdRIPQyEcCBktBeH+WkOG882HVgfkLdR+cZZgTfdaI cVzlJeTH8qyBDhJ7rU50HakONtWDnoK2fnWu1nVbmfYCX8PJ65TBFYzuuegcDMM0eEeM YTUB42HznYums0HOWit3Q0xdgJzb9qnu3gSD+iYPOhmZmNUmu9hYyJ9v9XGLa8TIfqw8 SXteGNQNOorONFswonf18aO8j40bB1BHtnwYA9IeUrHptNVv9GiS78m6qwxsMHatvMq+ Z9lF51YZNloh04fEoQ4pD8+lNVTejJHIYhwC8bidhL6sa6ujmZu3vm19LUxiqvjWh800 EFgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ss3VVbZb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Split out a do_unaligned_access function to share between the user-only s390x_cpu_record_sigbus and the sysemu s390x_do_unaligned_access. Signed-off-by: Richard Henderson --- target/s390x/s390x-internal.h | 8 +++++--- target/s390x/cpu.c | 1 + target/s390x/tcg/excp_helper.c | 27 ++++++++++++++++++++------- 3 files changed, 26 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 163aa4f94a..1a178aed41 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -270,18 +270,20 @@ ObjectClass *s390_cpu_class_by_name(const char *name); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); -void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; #ifdef CONFIG_USER_ONLY void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, MMUAccessType access_type, bool maperr, uintptr_t retaddr); +void s390_cpu_record_sigbus(CPUState *cs, vaddr address, + MMUAccessType access_type, uintptr_t retaddr); #else bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; #endif diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 593dda75c4..ccdbaf84d5 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -269,6 +269,7 @@ static const struct TCGCPUOps s390_tcg_ops = { #ifdef CONFIG_USER_ONLY .record_sigsegv = s390_cpu_record_sigsegv, + .record_sigbus = s390_cpu_record_sigbus, #else .tlb_fill = s390_cpu_tlb_fill, .cpu_exec_interrupt = s390_cpu_exec_interrupt, diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index b923d080fc..4e7648f301 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -82,6 +82,19 @@ void HELPER(data_exception)(CPUS390XState *env, uint32_t dxc) tcg_s390_data_exception(env, dxc, GETPC()); } +/* + * Unaligned accesses are only diagnosed with MO_ALIGN. At the moment, + * this is only for the atomic operations, for which we want to raise a + * specification exception. + */ +static void QEMU_NORETURN do_unaligned_access(CPUState *cs, uintptr_t retaddr) +{ + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + + tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr); +} + #if defined(CONFIG_USER_ONLY) void s390_cpu_do_interrupt(CPUState *cs) @@ -106,6 +119,12 @@ void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, cpu_loop_exit_restore(cs, retaddr); } +void s390_cpu_record_sigbus(CPUState *cs, vaddr address, + MMUAccessType access_type, uintptr_t retaddr) +{ + do_unaligned_access(cs, retaddr); +} + #else /* !CONFIG_USER_ONLY */ static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx) @@ -593,17 +612,11 @@ void s390x_cpu_debug_excp_handler(CPUState *cs) } } -/* Unaligned accesses are only diagnosed with MO_ALIGN. At the moment, - this is only for the atomic operations, for which we want to raise a - specification exception. */ void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; - - tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr); + do_unaligned_access(cs, retaddr); } static void QEMU_NORETURN monitor_event(CPUS390XState *env, From patchwork Wed Oct 13 02:45:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515690 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6085453ime; Tue, 12 Oct 2021 19:59:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz7YPbkrYHv6EQ0Y21dzAxBDPbG8bNVpuSLQhTguxh97cLieX0fDtoo6uh1mzmOQcNlhj7r X-Received: by 2002:a05:6602:3c5:: with SMTP id g5mr27532103iov.42.1634093950100; Tue, 12 Oct 2021 19:59:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634093950; cv=none; d=google.com; s=arc-20160816; b=By0komDFCQ3qwyny+EqmERJe+R0mJhs9MYRAtw6qKCWrZscyk1aBbUh1a051goS1Qa CDhbuIIw3D0kMa9AEalS6tOccLutOHpyKklxhnISAxo2ynQOQSxxodRUnPam+QxGe/zw l836aLgaXyQNoL6uDCGHPgq6dnynJgNJebBl0mcQ7k+ex3p8NTsSunZymzGGF9fm42Tm +VbbJp2R+1bUNDfzsETYErm5MbUeFu+1dyJQF6RlTt0gonccd7Nes1FQ8B1MpgGKyDPa Lo4hK2Lrj/XZjo9zmdSsuYx0XdukPUgZB0Rad1DkJU2aUaKrNDXS4nhpy4AnEwsG+6Gr DEdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QuBUrcbK5IHnv9/MH2TrxQjSj4HGL7JlA8tE+X8E85A=; b=i3dTvM6MhC1oTYlmgPKONJ1ULvMPtoKH1WKzfr4chhqwO71GXg2xuuHbhW9CjRji7d a7vZS6E3izOt+7ga7XRklCaQByd9p/NjFYyNzdtBp2XikS33BvMk+Rj2hlSVjYacGw7g WIqxzv0D6m+3MktmhaxfHpoW+Pw9Kmg6Tw59DP03CIM/QkVa4FzApEHoyC7cqfoU7QYG I9CII8AEKcjNf3xMpcdJPDmSGsAwzG7kLu8wuvs0G93EHyNQZdwRJ3cUS+G504NcWXDH bECaZHJmdjEmV3U9cKVBDDFMCnrb7JJhFYJUb1OOTylg9vSlAIjclzCHFrCBR7BNEN7x YeHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mYtXtChw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- linux-user/ppc/cpu_loop.c | 8 -------- 1 file changed, 8 deletions(-) -- 2.25.1 diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index 840b23736b..483e669300 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -162,14 +162,6 @@ void cpu_loop(CPUPPCState *env) cpu_abort(cs, "External interrupt while in user mode. " "Aborting\n"); break; - case POWERPC_EXCP_ALIGN: /* Alignment exception */ - /* XXX: check this */ - info.si_signo = TARGET_SIGBUS; - info.si_errno = 0; - info.si_code = TARGET_BUS_ADRALN; - info._sifields._sigfault._addr = env->nip; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case POWERPC_EXCP_PROGRAM: /* Program exception */ case POWERPC_EXCP_HV_EMU: /* HV emulation */ /* XXX: check this */ From patchwork Wed Oct 13 02:45:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515679 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6081726ime; Tue, 12 Oct 2021 19:52:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzQbpNERE4Mt0PPh5OE8E3cBhopgKz254nDCqlqqVbj6sphIcf/+gCN/3QYyDmEZmBHrMX/ X-Received: by 2002:a37:d82:: with SMTP id 124mr22754188qkn.299.1634093530534; Tue, 12 Oct 2021 19:52:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634093530; cv=none; d=google.com; s=arc-20160816; b=EL97COxzeiUdc3/brjpShKWx5Z5gJ8gbUds5DpSXr6nNYx3d5R+jShkg+pSS56iFjb vtr/wrMDOCSxY5Y1SjT+F9iChHo6yr8Xx4FKeB3gbBEmo24O5xB/Id3TKfqi95smv3oY 4xhA5YUE+RrlAITgHEkvGb8dm8P45z4Wf0cLm3coItQXd62bYwCnOcfEh5NhA7k6iVkL t95LoRfcrbxYTUG/ivmoELDDgPLv5wo3Sk2Z+HDqB57ReleAmOEzACIlL+5w5t+slgXq V8l8W/NWYTqYxniaSoivisBuC2kCGR6jscHZdM6XPm1KcKmkjD0V1YKStpwUSH1iGcB9 PEyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KU5GqqnHBwJE2oQY4NvVS8KLTvZHsylgeTI1DbvIUb8=; b=1H/nbJswW1xGNzdMb1bu1QdGWEmwe744RS09zcyd7dvVZXs17LIHdwCZhSY/ltIK1J HuuSRhMWAlJkl9M2J3vHmPGrKHxcT98zO814L03Sqpk91Kd42OFtACG4WDLmi8QkquSe Mb+L0ggl+SpJ0NmxSdnWwH2NFfU+WqiOSibm2Qp4GRkUN6wNSk0UgrTU9ylMH3daVg2p 0VxcXWIAPzhh2CI+8FZzVANkhyq4f92+k4QN/7A++CiCWKUiDeEW/WnfdPnJVYSX6jpe WJ+mqc0UDWEy9BibuahUrIzFqi5ZjSLXUSuVvYTgwXfmOKov+dl1g2YwWm4x87ZuJFJ1 F6Ig== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="VZ9bp/XN"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j3si10424144qtj.349.2021.10.12.19.52.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 19:52:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="VZ9bp/XN"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57888 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUNG-0007e5-1d for patch@linaro.org; Tue, 12 Oct 2021 22:52:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56760) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUHg-0004R9-GA for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:24 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:33682) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUHe-0004ro-Sd for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:24 -0400 Received: by mail-pf1-x42f.google.com with SMTP id t184so297755pfd.0 for ; Tue, 12 Oct 2021 19:46:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KU5GqqnHBwJE2oQY4NvVS8KLTvZHsylgeTI1DbvIUb8=; b=VZ9bp/XN4RwXODAQd3FeXT2cCu3aSR3txc5F+hcP/KyzkvDOuqtKgbB095rPAUUl1O UqbyZjawnHXtbe3yGcARvIYMgVAjA0w1+mjhIvvQfLdgIiV0mt6NT/RwbYzybdvUNjcP tQI5miaN1GvzMUUMv+twRZxnyRw3P68eIvEyl2BgpakGiMWZk8PQovW98BifeEkhGlj5 pavJjQXHTEOnwNlR0mdnEz/TjHfx1cgAJgDBUsVN8qNklB6Np+8OVjolAcf+YtSUDHqe aNXfDzXhU0RosG7i7q2evJ7+flHayuovwniFdDsWQTbesjpCu+Tv/dFy8oSQB2DcR+f5 hDbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KU5GqqnHBwJE2oQY4NvVS8KLTvZHsylgeTI1DbvIUb8=; b=7mHAjJF83jiciuFb1b4iPd+SEqw4xJHnJC/vuRCCbv+Gg2nx1i+xtg/jpBZ3E9SJpt ub8GBStIUBPCzHaHO4UVJyNahNtnu0DAxTqj9qxqJ9m1EYGZI+WBQ/bOwAJkE7mdQztJ IX+Xa0n97hRQMh+/b0pfteg2Yxrl9HqpNkFiflluQ5QLxEUWKA3dbNE01fKnS6ExeoaO 4MfVY+xrpjP0XW77aj6iQr5ZIyHgC9A5BYGIe/5tygx4uX6rP78qk+SLt75ndoN6Rg8S t86iG4VeLKYP/n7LlpqPsIpseSWNNU5Eg/8/mBY8m986WOtGOMHyX0Ud1VKtcqftjI+q 9r4w== X-Gm-Message-State: AOAM533bN2McSYpWxreByOLsLYIZ9hEbyz5WmHZ6y8zDDXMXcrQA5Rls kQN1SoS25kR8joG2M9u5+9IfrA9juLKe5Q== X-Received: by 2002:a63:d806:: with SMTP id b6mr25896744pgh.395.1634093181514; Tue, 12 Oct 2021 19:46:21 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 12/48] target/sh4: Set fault address in superh_cpu_do_unaligned_access Date: Tue, 12 Oct 2021 19:45:31 -0700 Message-Id: <20211013024607.731881-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Yoshinori Sato Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We ought to have been recording the virtual address for reporting to the guest trap handler. Cc: Yoshinori Sato Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sh4/op_helper.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.25.1 diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index c0cbb95382..d6d70c339f 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -29,6 +29,9 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { + CPUSH4State *env = cs->env_ptr; + + env->tea = addr; switch (access_type) { case MMU_INST_FETCH: case MMU_DATA_LOAD: @@ -37,6 +40,8 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, case MMU_DATA_STORE: cs->exception_index = 0x100; break; + default: + g_assert_not_reached(); } cpu_loop_exit_restore(cs, retaddr); } From patchwork Wed Oct 13 02:45:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515676 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6080458ime; Tue, 12 Oct 2021 19:49:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy6Pdo12M7Qd2ziPZDBYix19XMXThBhyHhtGi/prT6pvx6J99RaSG8iW2Vfhd3dBfQRXqS2 X-Received: by 2002:ac8:12:: with SMTP id a18mr26072211qtg.157.1634093377482; Tue, 12 Oct 2021 19:49:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634093377; cv=none; d=google.com; s=arc-20160816; b=zKCx1HkQGKNxQ8TCj6PtL6GPhtRPc7wHuQyQ63RLFwfjY2836Gpd83vrEitQm8ZmfJ RsLhEKJcjR5IiYh0UJ5GRsvKjoMghPav27v/ZF2Jrvz2QeubyohzI5LAjYFeU5QdBIuP unO3OdbwfhXeLU1iL3bdMJ5jAgknLgXbqUwabbquHt4XUedmqo/MlvyZ/ISmMePufO5r W+fgsUsMkpEMBIK7r4qIzOAVKqs5yReOZeAhVs+H9Ghv8oAJyKkcBPS8rrn9zuAGt4+4 YrcIzALfBesL6mmVK4VqmJsvRfgkTnsweFF9UlE8CeKyb9g1RrJ9NYl/qWdTtstWlOIE Xm/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xZtb0PPzu6cBb+iC7eRYJW+bmlWER7T8m0GFx24utaE=; b=cf5rbNKu73OkuGc4JLJLGv89vdtKXdnGy3kQeoBvyW0qMi7Pr7o97HRNmtSZV54LSG ZAauvwFPQqLiSEO1n8/i6nEuYtAWQtjF31UpeQ0SXW/OUoWzWXP1CKSKBdMm4R/eThFL +b6seKlu9540slR0fJ5khujuJcGM8tFbOkTAMlgjBFvunWas5WQnlC1zIKmr4DYj+9If W8NCXDjB5teJfd119QSlNADiuHP81twx+rvjTF7lOpMRLe2/08XwyFpQy3s1CmhHFjeK BVa8j03kVFCzRwlNfIZK9/warsudZuJv1OjTf/fXJqG4ddq9MwaKUSNAQdy2PynOW3Vp ty9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yLNsAHDU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u2si9159323qkb.85.2021.10.12.19.49.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 19:49:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yLNsAHDU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49192 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUKn-0001pk-1M for patch@linaro.org; Tue, 12 Oct 2021 22:49:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56776) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUHh-0004U5-LL for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:25 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:40821) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUHg-0004tE-01 for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:25 -0400 Received: by mail-pg1-x52a.google.com with SMTP id q5so880405pgr.7 for ; Tue, 12 Oct 2021 19:46:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xZtb0PPzu6cBb+iC7eRYJW+bmlWER7T8m0GFx24utaE=; b=yLNsAHDUYOEHlKr8d8bwavKTYKbnMTWTmewqMijoNTgoG1lnUrrXPE0Wv0438Qst3O hTJS1q9bhk93rs6CZOgAKLEy9isOwYbTdQuUxkY22QoSH/IvK1kY/Lzvru3nut2vNvTq gXEPWczFT+EkjJQNjIPLM/0EBTJYXpLWSPvGn9frjozcyKAldOxJRNF9wJnoTiMuKXqP qqN+TOl0KzuSSHDCnv2yzT5yAhw4xgRO81sdtwUEEv3rFg9Hv4H8lBfAVsqSsTDTv32K 6zA6r0Oqs+EKC5TkiBercE5d+BI9DGUd3ERFeQYkPGb3IL5zn5irAO58gRqNTt+WFEVm kZuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xZtb0PPzu6cBb+iC7eRYJW+bmlWER7T8m0GFx24utaE=; b=GUF0/1AxE/yF7oBZ9uv6b9plGkQaVyJdq7XhVOOfFMLCSnkNqBrsOkGUU9QIKcwgih hz9yw3NykSzW1bNQYPD2Bq4XvRruKkQQoLC09M6DPYgqRnz8KoXie7u6HnGlRyQTkpt4 7hGvXqdczwOGoJbtkawdCBJeWrzZ6mSphQhpCnbjj/kh5NWJNxhs4g1UzMnSfqtovbdi 1L+5lgRDGfrEEs55fQx+1FDPnai5ZpMEL7lMzf/BMyYB67jvlvAxD63b6pAcG55+FYRt HOKygrbSSzTAwctW9nTkdyjv95tIlQlXL/uIsWUkx48KkMNWQSaX/dpy/MDH9gLrRAUa jvKg== X-Gm-Message-State: AOAM532SOAHxS/73KTrdVaGNKyoB9p5y/AufCyQSuScHucxvehlkapRh X0HTSto1DTOj7RDv9VTVknwhkuQeIefoFQ== X-Received: by 2002:a05:6a00:1707:b0:44d:47e1:9ffe with SMTP id h7-20020a056a00170700b0044d47e19ffemr4712868pfc.53.1634093182616; Tue, 12 Oct 2021 19:46:22 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 13/48] target/sparc: Remove DEBUG_UNALIGNED Date: Tue, 12 Oct 2021 19:45:32 -0700 Message-Id: <20211013024607.731881-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The printf should have been qemu_log_mask, the parameters themselves no longer compile, and because this is placed before unwinding the PC is actively wrong. We get better (and correct) logging on the other side of raising the exception, in sparc_cpu_do_interrupt. Reviewed-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 9 --------- 1 file changed, 9 deletions(-) -- 2.25.1 diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index abe2889d27..2d0d180ea6 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -27,7 +27,6 @@ //#define DEBUG_MMU //#define DEBUG_MXCC -//#define DEBUG_UNALIGNED //#define DEBUG_UNASSIGNED //#define DEBUG_ASI //#define DEBUG_CACHE_CONTROL @@ -364,10 +363,6 @@ static void do_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align, uintptr_t ra) { if (addr & align) { -#ifdef DEBUG_UNALIGNED - printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx - "\n", addr, env->pc); -#endif cpu_raise_exception_ra(env, TT_UNALIGNED, ra); } } @@ -1968,10 +1963,6 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; -#ifdef DEBUG_UNALIGNED - printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx - "\n", addr, env->pc); -#endif cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } #endif From patchwork Wed Oct 13 02:45:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515684 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6083006ime; Tue, 12 Oct 2021 19:54:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyCNriX/T2XRMkozY0OAFTeIvNJkayWnpD12s/a3BPO4z2yo5ScMIRaHlSytkfZs0IgDRx3 X-Received: by 2002:a05:6214:f06:: with SMTP id gw6mr11860716qvb.26.1634093660473; Tue, 12 Oct 2021 19:54:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634093660; cv=none; d=google.com; s=arc-20160816; b=cPIcT13OAf0oDfKdhGknw8PJQb44NQHSSZzhlNKkoZEvk8GZ0tvEcdMTeu+L2ZFpFC q0fYNUkAwy31H8nsJhyPnIjVEfJSIvxaHWwYRhf4vpSOjei7zDV7RzyEMW+Qy5wS7q2S HVxm4B7cf2NVQL1HAqNtu+rEP/Sg5WXLr5cKI6ocE9C1f6Idmu2dU5oLH1sWxZ6QGduQ 8pZRtwWGLt76TJkh+GuDJ7XmFLtd/kz42/6Y47W7PTnUVItPU7QXiIxo2WKq6v8bUlpK ntrMGPchNMqjK2UN2MVb03TOxH2aigaP8PsZHmZXuC/i2/UCgCPAPnAA1FjnLTEZg/kv 6cfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fVhlPoABQmS8wc89+ovGDAnkicIV2MZx6WAeJyRD9lM=; b=MEhoRupY+dG3v8AEV66nndJOHzpELDLAp1Z9dZvnoteX5wwUL24W+tiwzCnc/OWmtY 61Fv7Fb1Bn579ni72biofAUmQCqdxrVxR6Fka84CXbEEbEx9xY0ijX3T238VEwusctxT G1IZtMEzkLOFIOWhtJwk9bzWN6tEM9Mn0xYwCkqYLAT8yX9N+dbk9CgZ+ikY8tcZI59O p1+FdpfadfbxO2qP12sLe0NLtsVl12gOQ+ncMHcZsi2g8OrrGrL3S/mUQdQ/bTliFXMi iECMoHsn9m4L+jsaSiOfqVS8cmX2xptyZ2lBLZWlodqRcL8e1IOMLtYJmAMX+xh4bLvF ucng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KM63TzmC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 12 Oct 2021 19:46:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 14/48] target/sparc: Split out build_sfsr Date: Tue, 12 Oct 2021 19:45:33 -0700 Message-Id: <20211013024607.731881-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/mmu_helper.c | 72 +++++++++++++++++++++++++-------------- 1 file changed, 46 insertions(+), 26 deletions(-) -- 2.25.1 diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 2ad47391d0..014601e701 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -502,16 +502,60 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *tlb, return 0; } +static uint64_t build_sfsr(CPUSPARCState *env, int mmu_idx, int rw) +{ + uint64_t sfsr = SFSR_VALID_BIT; + + switch (mmu_idx) { + case MMU_PHYS_IDX: + sfsr |= SFSR_CT_NOTRANS; + break; + case MMU_USER_IDX: + case MMU_KERNEL_IDX: + sfsr |= SFSR_CT_PRIMARY; + break; + case MMU_USER_SECONDARY_IDX: + case MMU_KERNEL_SECONDARY_IDX: + sfsr |= SFSR_CT_SECONDARY; + break; + case MMU_NUCLEUS_IDX: + sfsr |= SFSR_CT_NUCLEUS; + break; + default: + g_assert_not_reached(); + } + + if (rw == 1) { + sfsr |= SFSR_WRITE_BIT; + } else if (rw == 4) { + sfsr |= SFSR_NF_BIT; + } + + if (env->pstate & PS_PRIV) { + sfsr |= SFSR_PR_BIT; + } + + if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */ + sfsr |= SFSR_OW_BIT; /* overflow (not read before another fault) */ + } + + /* FIXME: ASI field in SFSR must be set */ + + return sfsr; +} + static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, int *prot, MemTxAttrs *attrs, target_ulong address, int rw, int mmu_idx) { CPUState *cs = env_cpu(env); unsigned int i; + uint64_t sfsr; uint64_t context; - uint64_t sfsr = 0; bool is_user = false; + sfsr = build_sfsr(env, mmu_idx, rw); + switch (mmu_idx) { case MMU_PHYS_IDX: g_assert_not_reached(); @@ -520,29 +564,18 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, /* fallthru */ case MMU_KERNEL_IDX: context = env->dmmu.mmu_primary_context & 0x1fff; - sfsr |= SFSR_CT_PRIMARY; break; case MMU_USER_SECONDARY_IDX: is_user = true; /* fallthru */ case MMU_KERNEL_SECONDARY_IDX: context = env->dmmu.mmu_secondary_context & 0x1fff; - sfsr |= SFSR_CT_SECONDARY; break; - case MMU_NUCLEUS_IDX: - sfsr |= SFSR_CT_NUCLEUS; - /* FALLTHRU */ default: context = 0; break; } - if (rw == 1) { - sfsr |= SFSR_WRITE_BIT; - } else if (rw == 4) { - sfsr |= SFSR_NF_BIT; - } - for (i = 0; i < 64; i++) { /* ctx match, vaddr match, valid? */ if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) { @@ -592,22 +625,9 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, return 0; } - if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */ - sfsr |= SFSR_OW_BIT; /* overflow (not read before - another fault) */ - } - - if (env->pstate & PS_PRIV) { - sfsr |= SFSR_PR_BIT; - } - - /* FIXME: ASI field in SFSR must be set */ - env->dmmu.sfsr = sfsr | SFSR_VALID_BIT; - + env->dmmu.sfsr = sfsr; env->dmmu.sfar = address; /* Fault address register */ - env->dmmu.tag_access = (address & ~0x1fffULL) | context; - return 1; } } From patchwork Wed Oct 13 02:45:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515680 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6081728ime; Tue, 12 Oct 2021 19:52:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwd03/dAmHdDcrULZQJyNmTyvY38Cqtg/iQdpPVoIUEspb2O5cy5qp91ac7qPIIWvx40TIp X-Received: by 2002:a0c:f489:: with SMTP id i9mr14194862qvm.64.1634093530703; Tue, 12 Oct 2021 19:52:10 -0700 (PDT) ARC-Seal: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id l2si9075118qkj.273.2021.10.12.19.52.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 19:52:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qNbgAgts; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUNG-0007bo-6A for patch@linaro.org; Tue, 12 Oct 2021 22:52:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUHj-0004bK-Kv for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:27 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:38432) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUHh-0004ug-S2 for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:27 -0400 Received: by mail-pf1-x429.google.com with SMTP id k26so1157870pfi.5 for ; Tue, 12 Oct 2021 19:46:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cpKP9lLV+B3lJJVGxWZYd41x3ok2BfFIwAyas9V94EU=; b=qNbgAgtsmxcP/dppXY9myvaF/cqSMVldOv19fEi7f07XGiyc7IuyOTWDOQ4VGs/hgY wdzEK0nErQVlzJCgwfmOyxT5uLi7HwdQT9Cj1fav2BGNMMMJynTvUwcNE0cvjF/vbVFw Fr1B5B4KutUfTDEN4Ug96eyjov9VnC+a1PY2chl3MoA38y0x2wHeE99o4EqSR36AJ5aW WRdw+fqzE7SqXvAKk2wj8t+fYhqx92Lw3YjmvCf1L/FNqT3Fbsrrv5xAMdsv9HCoHOce CgzCnjugRG/nNsq4X6aYraCxDjgWUprWfItAm5zWOeR/melPlRtGj+opTSNZDpMF5CCT n+XQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cpKP9lLV+B3lJJVGxWZYd41x3ok2BfFIwAyas9V94EU=; b=R0PbaMD70jN9xLsxBsQhr+2buMj9SuCeoX6JeIC6GIGtucZOcOeuRV64PgZESBWjyp e3A6fG/2hSOiLrf5wDuAcjiCoWlE1i5n8lUkCfAghwMNUIlbLeRoRwzRyYJdL7qkSGc5 4z40/X5sp/XJGDPSarByTcJxL8EPoR0Vv+43kmznhagDkuN3wQWHLYGcGgUtcS5CLPZJ p+Ci+VA/XsEY7NeqLeerh1yhN8fJJbhrn8O0a1OW32eXWuiB9GX0op0emZxOMfp7bLH9 xtZSi/Ku2MkMeAfISRY37gyvPurnzKU60Kjyw8gxe4OvhfR2d9rTskWoXubqbEav28DN rpXg== X-Gm-Message-State: AOAM531Cq/5W4oR86PGlw8SFkpMGiYiQ3tJ2cbiJd85CfsfhC7Y4mPO0 TjITRsEqBi8UDm3XeW4uTUPMRPCcZKc1tg== X-Received: by 2002:a63:191a:: with SMTP id z26mr25169692pgl.373.1634093184614; Tue, 12 Oct 2021 19:46:24 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 15/48] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Date: Tue, 12 Oct 2021 19:45:34 -0700 Message-Id: <20211013024607.731881-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We ought to have been recording the virtual address for reporting to the guest trap handler. Move the function to mmu_helper.c, so that we can re-use code shared with get_physical_address_data. Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 13 ------------- target/sparc/mmu_helper.c | 20 ++++++++++++++++++++ 2 files changed, 20 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 2d0d180ea6..299fc386ea 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1953,16 +1953,3 @@ void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, is_asi, size, retaddr); } #endif - -#if !defined(CONFIG_USER_ONLY) -void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, - uintptr_t retaddr) -{ - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - - cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); -} -#endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 014601e701..f2668389b0 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -922,3 +922,23 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } return phys_addr; } + +#ifndef CONFIG_USER_ONLY +void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, + uintptr_t retaddr) +{ + SPARCCPU *cpu = SPARC_CPU(cs); + CPUSPARCState *env = &cpu->env; + +#ifdef TARGET_SPARC64 + env->dmmu.sfsr = build_sfsr(env, mmu_idx, access_type); + env->dmmu.sfar = addr; +#else + env->mmuregs[4] = addr; +#endif + + cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); +} +#endif /* !CONFIG_USER_ONLY */ From patchwork Wed Oct 13 02:45:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515683 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6082994ime; Tue, 12 Oct 2021 19:54:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxP983KlGbNUF0zfOXVmP499WT2v3qrOAOLnMnwWKVm1AUu4N2dJ+EB7H62rOgwBhI/2dH4 X-Received: by 2002:a0c:c983:: with SMTP id b3mr24706714qvk.26.1634093659833; Tue, 12 Oct 2021 19:54:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634093659; cv=none; d=google.com; s=arc-20160816; b=SqldNtxbH9l+jAPCcDYIWDwzv5qqFbV8WU2yoMCHdmZeCgQhhSwOUqztDYPcO9Lyf5 BSyFmvLLEcwVqIxa8Fa+YI6DLtZZj2eB4xsSIr6xkHewoT6aNL/tWedgb0elp/UftoIu KmxvWxcIuDYIxOQe9dYr2APWFGU0nTdIe5/7CjuLpmAzsrN1WjqlCefZSd6zSkpjopeD i8PjHcjlM8TINBOklixTJLB3KHwNVrOzdZnHSmcFGe3GQNIirdmc3NsPdLAQff+qxyGX RLNOwdw7gFVwwogX37zxpCIB0qI4Ih5ZphFgE18fi7o9A/jTr4o10rWtt9qqINuRcL3E zRCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=te2kf7hHJE1D45OuAMtE7bn/toedNLWAWMCQPiNKbOQ=; b=x2aLEbOUkvSVyBpyGJKOibVpMz6r/KUKVyaTwdXlg2gXqe1iiJF5pTszvSquTu8hub twDerZNjD4NzXxS0K0g9By4k39AH6e3cSYFKyDJtjdQJHh+zfCu0gtCI/FUYfGGVgr7B isqpTYJQPwbgMR5ROHtTRpSHWc4x2IsauRiLLZJ/vrWUwBSA3Rg4FfHuixDk0NNqYTF6 Z2O2cX/Z0yV3VqCEPWMtiMG+jwA8JJu++LvvpiHU/yamMT6Kb1pw0FJCYhuOSouO2UdF 8HsZOb5hh8NoyTGVkd9OoAzHkk7KIdV7HcKXsPbMOJwR7rl4HMfMeso1pIAwphm80YIh bccw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vCMCfN2K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 24si9074789qtu.9.2021.10.12.19.54.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 19:54:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vCMCfN2K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38174 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUPL-00051U-A5 for patch@linaro.org; Tue, 12 Oct 2021 22:54:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56824) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUHk-0004eR-HE for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:28 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:40705) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUHi-0004uy-Ow for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:28 -0400 Received: by mail-pf1-x42d.google.com with SMTP id o133so1147657pfg.7 for ; Tue, 12 Oct 2021 19:46:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=te2kf7hHJE1D45OuAMtE7bn/toedNLWAWMCQPiNKbOQ=; b=vCMCfN2KQG7/hmOP9Hlf0qxSJHIKTywetAlsuCgeqYsEXqoxyZg2WwuMf9aPSjfYpt 4FgIDAtKrOTtEIlkXKacAp+On76Mz2NFEn3HfsQ+c5U/a6qeX8/u4IbX+lqh89/SrxO/ aijrTAHWC/qePlqpu7qZPTlSJRcxoQVDoNxIBmdUpAz1m+GkekrsJwUmLbEqBeMg06Gh 7NZ0QgG/V642YeWscHyIjEcCT3npsXU1wPAzX0en3vvwUA0g2ZwRAXvnIKjtFO4YNlC6 oAfk0drt08VGUzzDzBztUDAyZX5GtaC4ICLURsniwbpuCJWKmATIXILCBYyi5GEhkYmZ /sCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=te2kf7hHJE1D45OuAMtE7bn/toedNLWAWMCQPiNKbOQ=; b=5VnwY9cPxpABqezzkQwSuKAYJIDIp73+yVSVOZCeNfAo7T4CjOj62ie++2ILGkv4lC 8+fVbAZ0S46VhuTMT/0a91ZB6FMCNdyXzBk1h/k/WhqqFbd9fPNd4Gw1UYIex8erDPnO b0ShJrDNLtyV42RztizSxWUIiRuUcEXrMePslE3rLAPtO7Zjm7DgS6JpK1XesXPAe+vU Ss1f7a8/GticckTNPYBYr09q2Jr29ErVTEhY2ifzZR7c9vR/WlrDo1O5WDrx9NLDqBql LMUzUt2qpWJe0aLeHFSihw27Ja9enDj674Xp0eQASIBQsdRP6weOhxBzKrjqI2FQnuMn xqzw== X-Gm-Message-State: AOAM532ltcIGoXEkc6vFv4/43EdAl0IKkXxhQ6ahSL88HxPzBc6T3Yot F2T1SO0gYEn3ZcGe0XMM8Zwp01HdNkU= X-Received: by 2002:a62:33c2:0:b0:44d:ab9:2e92 with SMTP id z185-20020a6233c2000000b0044d0ab92e92mr18541758pfz.10.1634093185387; Tue, 12 Oct 2021 19:46:25 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 16/48] accel/tcg: Report unaligned atomics for user-only Date: Tue, 12 Oct 2021 19:45:35 -0700 Message-Id: <20211013024607.731881-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the new cpu_loop_exit_sigbus for atomic_mmu_lookup, which has access to complete alignment info from the TCGMemOpIdx arg. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 83ed76cef9..5dcd58c6d5 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -547,11 +547,22 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, int size, int prot, uintptr_t retaddr) { + MemOp mop = get_memop(oi); + int a_bits = get_alignment_bits(mop); + void *ret; + + /* Enforce guest required alignment. */ + if (unlikely(addr & ((1 << a_bits) - 1))) { + MMUAccessType t = prot == PAGE_READ ? MMU_DATA_LOAD : MMU_DATA_STORE; + cpu_loop_exit_sigbus(env_cpu(env), addr, t, retaddr); + } + /* Enforce qemu required alignment. */ if (unlikely(addr & (size - 1))) { cpu_loop_exit_atomic(env_cpu(env), retaddr); } - void *ret = g2h(env_cpu(env), addr); + + ret = g2h(env_cpu(env), addr); set_helper_retaddr(retaddr); return ret; } From patchwork Wed Oct 13 02:45:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515685 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6083606ime; Tue, 12 Oct 2021 19:55:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz3tJDZ0nkm8uEpBkhIsgKEJAIvS43h6Qs6WL9LkDyTAEtKho6II5yY+ief7pjbnhS6vLMn X-Received: by 2002:a37:bd01:: with SMTP id n1mr22638622qkf.274.1634093722092; Tue, 12 Oct 2021 19:55:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634093722; cv=none; d=google.com; s=arc-20160816; b=njKRAfHIBbuPq2D2m/8ZkwpHavBPOUpGqNJbqr7k8KWLaWHR7chfnbsOjVAYiHi3os eFKZT64BsWNcWkm4IXTwsWG9E/QQ47di7O98LtgWyJArBU4T6YomaiqKR3/3ncPFMIGd PIY0y6cg4rJywecJmrHGpaJ9acmfYBYy3xc14OnqOoxm5CHruQ0w5FpsnrvbmEmpt+tB IRWlZAu2QkPnkfEsIwwH98bUeoCnwW4Pi2INtgkE/W0D9XNVMkAe/fX5UWVl+Etc05sj pg4iEooOUl+zJd9s9JULfRn8FEFCWcU2Qm1HQzH++C/Pf7BvbiWrrtj682IUsWqC/ZRb 4VmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GDciQRPakuuX9DSUk6eQQR3ypkG2xXbHMYU5/kDhb4Y=; b=ngyd4T/iL3D5GvLo7mP5Pm/V0Znmm3kx/b3PlgmQSQt1QvGE0xFNDlTlnWWEllVtvz FM5YGWn3k+s9Y90fxfs+GjTXN3L2g1qQMyIOzHOJVzVtkF59rnY2KQlZYVK0iLOBvCeu 1sRCjLAUKudtjoDwUfAU/M82hFF9D6eSKvBz5eoFxGFqmDPbf+B9ftEvpVLcAaHBEMxy fh3EXLfhAQHtp0We+ZMBH0DuqMEp1o+v0dNuG98rKk5fysstbxbEA1lnF8//7m37cFxT y7YdFfqGrFzv3ukK88Px2RQ/IT6DI/VJkVIFfv11OC99068AuqicqPr8FR++uLCEHxSv /zaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TRGieUJX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 12 Oct 2021 19:46:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 17/48] target/arm: Use MO_128 for 16 byte atomics Date: Tue, 12 Oct 2021 19:45:36 -0700 Message-Id: <20211013024607.731881-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: qemu-arm@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index c5af779006..4cafd3c11a 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -560,7 +560,7 @@ uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t addr, assert(HAVE_CMPXCHG128); mem_idx = cpu_mmu_index(env, false); - oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); + oi = make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); cmpv = int128_make128(env->exclusive_val, env->exclusive_high); newv = int128_make128(new_lo, new_hi); @@ -630,7 +630,7 @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr, assert(HAVE_CMPXCHG128); mem_idx = cpu_mmu_index(env, false); - oi = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); + oi = make_memop_idx(MO_BE | MO_128 | MO_ALIGN, mem_idx); /* * High and low need to be switched here because this is not actually a @@ -656,7 +656,7 @@ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, assert(HAVE_CMPXCHG128); mem_idx = cpu_mmu_index(env, false); - oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); + oi = make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); cmpv = int128_make128(env->xregs[rs], env->xregs[rs + 1]); newv = int128_make128(new_lo, new_hi); @@ -677,7 +677,7 @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, assert(HAVE_CMPXCHG128); mem_idx = cpu_mmu_index(env, false); - oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); + oi = make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); cmpv = int128_make128(env->xregs[rs + 1], env->xregs[rs]); newv = int128_make128(new_lo, new_hi); From patchwork Wed Oct 13 02:45:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515689 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6084691ime; Tue, 12 Oct 2021 19:57:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwN8d9vyZKFLjH8uAEo5tCaphxs5XZM7U/vUJWiRJbqQbR+gpTlp25rmepSGtO/1bfPvMyK X-Received: by 2002:a05:622a:51:: with SMTP id y17mr25703708qtw.149.1634093867364; Tue, 12 Oct 2021 19:57:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634093867; cv=none; d=google.com; s=arc-20160816; b=GUN41MSPbq6BB26Qnj+O50Ow/nBguylQNQTQFNgWnRMc0H4i+SuFIuoUblj+J8ZyuA nhBCEt+0tOyAc5wAoFuaF3UBmQnivUP3RMFFoj9XPOq5+/6BbapEd2wWaVvevRb2+35f oLewhq/8w2cyOk2LzYRNhbLBC3LYte8hH/rtIZ7mk6n6CvA1Ho2YmZBRQBNYIvwC2Y7a 3PiZTK2iE+KHMHcQSC89Jrh+aDLJwKjh5FT+6DGHL5xefMjVrozMKaHByHn/uKkZvVmG 8DJzgoRNYDHqLH46IXmmh8ZAzwM/9qAZotBsgGC2eqk1moqc6NKmpRkkF+ssqnpFBNwT lOjQ== ARC-Message-Signature: i=1; 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Tue, 12 Oct 2021 19:46:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 18/48] target/i386: Use MO_128 for 16 byte atomics Date: Tue, 12 Oct 2021 19:45:37 -0700 Message-Id: <20211013024607.731881-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/i386/tcg/mem_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 0fd696f9c1..a207e624cb 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -136,7 +136,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0) Int128 newv = int128_make128(env->regs[R_EBX], env->regs[R_ECX]); int mem_idx = cpu_mmu_index(env, false); - MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + MemOpIdx oi = make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx); Int128 oldv = cpu_atomic_cmpxchgo_le_mmu(env, a0, cmpv, newv, oi, ra); if (int128_eq(oldv, cmpv)) { From patchwork Wed Oct 13 02:45:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515693 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6086205ime; Tue, 12 Oct 2021 20:00:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxDMdXA3uZ+Gk/dm4HlsA3qJChHm/SwM9JSO63VeQGEd1S7r2PPOZvFj79VR54DT0eeC1IX X-Received: by 2002:a05:6902:124a:: with SMTP id t10mr33300017ybu.73.1634094028504; Tue, 12 Oct 2021 20:00:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634094028; cv=none; d=google.com; s=arc-20160816; b=g2iNTRmxv4BR3+g3eH62Skn8w0cHiHCOU9qdGz+/G3e5flFC/TI/DVUTrl+OxX+SRb 0eP8eTrp4PKhAG44e15YGitYoMLkfqzYxl3K/WUiR7HYbeXekNbV4sl5ee7PULtA2x6C EUJO5xSrF39Yf8JNxMT+lLIYoDSFZ/E4hvRGIan0548ne4Zf9VRqAuTgO7qeW0CLgOLk w3CjOtp/t+D3Sl47ZmCHbPhp5a75v/qoxdJNoJ3ha2t42L87Dzl+rla8st5kKGAi443u mxVov0E9S+EduKeY4wQ/weLfupU1fLpaw+PTyh76/DTAb4tTEy45fm4v1YK7few0N3Zw gSiw== ARC-Message-Signature: i=1; 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Tue, 12 Oct 2021 19:46:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 19/48] target/ppc: Use MO_128 for 16 byte atomics Date: Tue, 12 Oct 2021 19:45:38 -0700 Message-Id: <20211013024607.731881-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: qemu-ppc@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/ppc/translate.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index b985e9e55b..9ca78ee156 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3462,10 +3462,12 @@ static void gen_std(DisasContext *ctx) if (HAVE_ATOMIC128) { TCGv_i32 oi = tcg_temp_new_i32(); if (ctx->le_mode) { - tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); + tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128, + ctx->mem_idx)); gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); } else { - tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); + tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128, + ctx->mem_idx)); gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); } tcg_temp_free_i32(oi); @@ -4067,11 +4069,11 @@ static void gen_lqarx(DisasContext *ctx) if (HAVE_ATOMIC128) { TCGv_i32 oi = tcg_temp_new_i32(); if (ctx->le_mode) { - tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, + tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_ALIGN, ctx->mem_idx)); gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); } else { - tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, + tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_ALIGN, ctx->mem_idx)); gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); } @@ -4122,7 +4124,7 @@ static void gen_stqcx_(DisasContext *ctx) if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { if (HAVE_CMPXCHG128) { - TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); + TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN); if (ctx->le_mode) { gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi); From patchwork Wed Oct 13 02:45:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515688 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6084472ime; Tue, 12 Oct 2021 19:57:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwk6DtLYlo9DPBRrBwYhQZHI96eOYRTPXj7T79SEcvYuJ3taor/BzMJRpDqUvQDlA0wIUCc X-Received: by 2002:ad4:4bb1:: with SMTP id i17mr32532672qvw.31.1634093838221; Tue, 12 Oct 2021 19:57:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634093838; cv=none; d=google.com; s=arc-20160816; b=ccW6gJVUvq9nZbHIkS6Rs7qTon2KOQs9Cj4vd52LL0QAU5yhRRWcEb/WShrp6yUB7J T+81E9Z5qpqkmm4Y08J2cQ/ES+CrmYjhsQbF65h3kr3BaoVU4Av4+jyw4IlKeyONTWaK dZC+3E3jRkWuQO6phmXDNHRkLKGhFzfsafYymCI5Fu1Ip8C+8dO4WYRPO2iIcbFYcKcr 9c8mJdslI78xLfS1lhWhVTxwCyGEHtYrKL7t5YNv1EP+EEYwyKc+DfiHeadYXuMBDTfh abHFuXs1HpVUHyM5qA+hnSX5deIBlNEPytsr929qPqTI5IyzjaTq0aG79IYMQVGU/56U 6kew== ARC-Message-Signature: i=1; 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Tue, 12 Oct 2021 19:46:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 20/48] target/s390x: Use MO_128 for 16 byte atomics Date: Tue, 12 Oct 2021 19:45:39 -0700 Message-Id: <20211013024607.731881-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , David Hildenbrand Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 4accffe68f..8624385fe1 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1803,7 +1803,7 @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr, assert(HAVE_CMPXCHG128); mem_idx = cpu_mmu_index(env, false); - oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + oi = make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx); oldv = cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); fail = !int128_eq(oldv, cmpv); @@ -1932,7 +1932,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra); cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra); } else if (HAVE_CMPXCHG128) { - MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + MemOpIdx oi = make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx); ov = cpu_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra); cc = !int128_eq(ov, cv); } else { From patchwork Wed Oct 13 02:45:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515687 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6084316ime; Tue, 12 Oct 2021 19:56:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyyGufp0X26Qsds0tXprRZq9oip5CV9MkMNbFZ0Xi3ns5c1w4ynwg6BNhdCP06RSdX4mL1d X-Received: by 2002:a37:93c5:: with SMTP id v188mr22641144qkd.57.1634093817518; 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Reviewed-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hexagon/cpu.h | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.25.1 diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index f7d043865b..f90c187888 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -141,6 +141,15 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong *pc, #endif } +static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else +#error System mode not supported on Hexagon yet +#endif +} + typedef struct CPUHexagonState CPUArchState; typedef HexagonCPU ArchCPU; From patchwork Wed Oct 13 02:45:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515694 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6087709ime; Tue, 12 Oct 2021 20:02:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwYbVxByadS3WaqNvvOsjJib5cbKxeJke8PJgglLGBlHTSPCJhOxLFt7JizwYpNZnnsWb++ X-Received: by 2002:a0c:e885:: with SMTP id b5mr20329588qvo.18.1634094166291; Tue, 12 Oct 2021 20:02:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634094166; cv=none; d=google.com; s=arc-20160816; b=XkWLGBMFkQ+VVO0NgYwte2SOCeXqnExaCkaGpSrnd5pWI5KpFT4w1lTQCMPUeLjYYs bbPNyNzJs7qKKJMMb0qC858AgMktWVWbJbK5F42EHrMoaUk00llM329URqQVMKKvLQxf 6FZafCheCaP+oISKIfGuLexDZyjT7PHuXr1apQ+1dxHxYsYXt0I4vIO8tlnlskZ1Lph6 BbUWevTW7uKqR3yjFa5PCGcD76VP0HhrRZ8uTHNQmdaSZiUpn1y4DWibMpKtS9Np4Rjv kO+JeVi8CIGDovDDk6bD0/WKRqI63TdbduwSIKygktzr8RY0XvM9mYuuYu8pPlwWCI22 T1sQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vKg9NTzxKrduN7hX3FG8JXAhSyUcNbn4J+8MeKzl6AE=; b=y7EXwftZ4WpRBMM8XDZjxVSCem7/KnXhWQ37gSkq1JMbEZyAs6BoH9nontAjuRaP2r uNK4tu0gwNU7gaiobGFLzdPHWOJbyRpQXdKhIf2UmfxCpIZuMWkOSpIxvipM0apeYgu0 TiGVwcIWnHswGoeJQ38cI+sGwNaMouDrGQU4dsyHwzmdjIXNqmSxFDc+o9DFWLp0qxRj 4skzb8Uo5xm6QRy8mJO8Q+iHCbd+mJ4Ucx+/qKFYyWZa2xleYYRf4CklGxAxalVk8zZK hUTrrBCzjm2DbqP/NlILy9wpIYwdUiX2ezebf+8KsH8q1N4y6kmdFje7r41nmtjEv4No C3XQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=whuTvFn4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v12si10715479qkl.346.2021.10.12.20.02.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 20:02:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=whuTvFn4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35112 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUXV-0004wR-GL for patch@linaro.org; Tue, 12 Oct 2021 23:02:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57000) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUHv-0004vF-96 for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:40 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:54180) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUHp-00051h-M6 for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:39 -0400 Received: by mail-pj1-x1031.google.com with SMTP id ls18so1061751pjb.3 for ; Tue, 12 Oct 2021 19:46:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vKg9NTzxKrduN7hX3FG8JXAhSyUcNbn4J+8MeKzl6AE=; b=whuTvFn4rTcYblPjy/MkynjB/Tj6s5L4taukGM6hr7deA8WsF5lR7TsA8+YMAHl1ib vLZYcX4mVt9DphffrPfV7uuBznZL+4CpIkisGAIIYjARQMETbadE2stYhFcXF4g0yx/b Kmk496xsIRH1mgG9vT6sNoC+72Fzrd+7j6JrZbiGxdu+Ud/vRHSCeWt1RRD0p4agaiIj iKROYX/pssmO100U1Bw/QvN8ZYHyrwDFDVhQZ7w0ISTOM/YSTXXwxi2Kr1De2OWakpCx GjLCHtJ9H1/2PvRPcn0J50TYveASlPgnu1MWkD6fmWeaxZMsSKJ0UhFc130CK39BgEh8 I3gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vKg9NTzxKrduN7hX3FG8JXAhSyUcNbn4J+8MeKzl6AE=; b=h8qQRSu7hU7Mt4PQTVIOkslJQSCSfIz+jrLbmfzCT4TkWah/WnTfKD0KEnvOBwAzVB bwRNxYJBdE3r6ya34TYT7bE1fIN/UzhLfmtkEw/0vqNNQtMlt7krl1BqQgtivUhAOUNq e37fWoPOsyyeJwUJFpz6P1E+mti30yT3S33XCY4gCoctl07prylMRffrBZ7SPETiWKbV Nd06FMhGyZhqOFZJZ5X60A6AF03QSC5x9Qxib3Woc0F0qsBKgHvc/V6sULkVRVE9WHOa m0p6UFxByqS0gzCjhfraYEHmyNzhUxVU16vzqISb0ZyTr9akay/dnRINACMiIOSqMRxn wzKA== X-Gm-Message-State: AOAM531ASvBX0goR+MTiOfT00vTW5O5kJOBuk/6guoVmd4keLiKwx9AG EptHCUnjlAFPoYsw1JDMC0XAFn7amD51hg== X-Received: by 2002:a17:90b:1c92:: with SMTP id oo18mr10359292pjb.56.1634093192090; Tue, 12 Oct 2021 19:46:32 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 22/48] accel/tcg: Add cpu_{ld,st}*_mmu interfaces Date: Tue, 12 Oct 2021 19:45:41 -0700 Message-Id: <20211013024607.731881-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These functions are much closer to the softmmu helper functions, in that they take the complete MemOpIdx, and from that they may enforce required alignment. The previous cpu_ldst.h functions did not have alignment info, and so did not enforce it. Retain this by adding MO_UNALN to the MemOp that we create in calling the new functions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/devel/loads-stores.rst | 52 ++++- include/exec/cpu_ldst.h | 245 ++++++++-------------- accel/tcg/cputlb.c | 392 ++++++++++++------------------------ accel/tcg/user-exec.c | 390 +++++++++++++++-------------------- accel/tcg/ldst_common.c.inc | 307 ++++++++++++++++++++++++++++ 5 files changed, 722 insertions(+), 664 deletions(-) create mode 100644 accel/tcg/ldst_common.c.inc -- 2.25.1 diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst index 568274baec..8f0035c821 100644 --- a/docs/devel/loads-stores.rst +++ b/docs/devel/loads-stores.rst @@ -68,15 +68,19 @@ Regexes for git grep - ``\`` - ``\`` -``cpu_{ld,st}*_mmuidx_ra`` -~~~~~~~~~~~~~~~~~~~~~~~~~~ +``cpu_{ld,st}*_mmu`` +~~~~~~~~~~~~~~~~~~~~ -These functions operate on a guest virtual address plus a context, -known as a "mmu index" or ``mmuidx``, which controls how that virtual -address is translated. The meaning of the indexes are target specific, -but specifying a particular index might be necessary if, for instance, -the helper requires an "always as non-privileged" access rather that -the default access for the current state of the guest CPU. +These functions operate on a guest virtual address, plus a context +known as a "mmu index" which controls how that virtual address is +translated, plus a ``MemOp`` which contains alignment requirements +among other things. The ``MemOp`` and mmu index are combined into +a single argument of type ``MemOpIdx``. + +The meaning of the indexes are target specific, but specifying a +particular index might be necessary if, for instance, the helper +requires a "always as non-privileged" access rather than the +default access for the current state of the guest CPU. These functions may cause a guest CPU exception to be taken (e.g. for an alignment fault or MMU fault) which will result in @@ -99,6 +103,35 @@ function, which is a return address into the generated code [#gpc]_. Function names follow the pattern: +load: ``cpu_ld{size}{end}_mmu(env, ptr, oi, retaddr)`` + +store: ``cpu_st{size}{end}_mmu(env, ptr, val, oi, retaddr)`` + +``size`` + - ``b`` : 8 bits + - ``w`` : 16 bits + - ``l`` : 32 bits + - ``q`` : 64 bits + +``end`` + - (empty) : for target endian, or 8 bit sizes + - ``_be`` : big endian + - ``_le`` : little endian + +Regexes for git grep: + - ``\`` + - ``\`` + + +``cpu_{ld,st}*_mmuidx_ra`` +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +These functions work like the ``cpu_{ld,st}_mmu`` functions except +that the ``mmuidx`` parameter is not combined with a ``MemOp``, +and therefore there is no required alignment supplied or enforced. + +Function names follow the pattern: + load: ``cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmuidx, retaddr)`` store: ``cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)`` @@ -132,7 +165,8 @@ of the guest CPU, as determined by ``cpu_mmu_index(env, false)``. These are generally the preferred way to do accesses by guest virtual address from helper functions, unless the access should -be performed with a context other than the default. +be performed with a context other than the default, or alignment +should be enforced for the access. Function names follow the pattern: diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index ce6ce82618..a4dad0772f 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -28,10 +28,12 @@ * load: cpu_ld{sign}{size}{end}_{mmusuffix}(env, ptr) * cpu_ld{sign}{size}{end}_{mmusuffix}_ra(env, ptr, retaddr) * cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmu_idx, retaddr) + * cpu_ld{sign}{size}{end}_mmu(env, ptr, oi, retaddr) * * store: cpu_st{size}{end}_{mmusuffix}(env, ptr, val) * cpu_st{size}{end}_{mmusuffix}_ra(env, ptr, val, retaddr) * cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr) + * cpu_st{size}{end}_mmu(env, ptr, val, oi, retaddr) * * sign is: * (empty): for 32 and 64 bit sizes @@ -53,10 +55,15 @@ * The "mmuidx" suffix carries an extra mmu_idx argument that specifies * the index to use; the "data" and "code" suffixes take the index from * cpu_mmu_index(). + * + * The "mmu" suffix carries the full MemOpIdx, with both mmu_idx and the + * MemOp including alignment requirements. The alignment will be enforced. */ #ifndef CPU_LDST_H #define CPU_LDST_H +#include "exec/memopidx.h" + #if defined(CONFIG_USER_ONLY) /* sparc32plus has 64bit long but 32bit space address * this can make bad result with g2h() and h2g() @@ -118,12 +125,10 @@ typedef target_ulong abi_ptr; uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr); int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr); - uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr); int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr); uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr); uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr); - uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr); int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr); uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr); @@ -131,37 +136,31 @@ uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr); uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); - uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); - uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val); - void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val); void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val); void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val); - void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val); void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val); void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val); void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, uintptr_t ra); - void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, uintptr_t ra); void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, uintptr_t ra); void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, uintptr_t ra); - void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, uintptr_t ra); void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr, @@ -169,6 +168,71 @@ void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr, void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, uintptr_t ra); +uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); + +void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, + int mmu_idx, uintptr_t ra); +void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, + int mmu_idx, uintptr_t ra); +void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, + int mmu_idx, uintptr_t ra); +void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, + int mmu_idx, uintptr_t ra); +void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, + int mmu_idx, uintptr_t ra); +void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, + int mmu_idx, uintptr_t ra); +void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, + int mmu_idx, uintptr_t ra); + +uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t ra); +uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); +uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); +uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); +uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); +uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); +uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); + +void cpu_stb_mmu(CPUArchState *env, abi_ptr ptr, uint8_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stw_be_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stl_be_mmu(CPUArchState *env, abi_ptr ptr, uint32_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stq_be_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stw_le_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stl_le_mmu(CPUArchState *env, abi_ptr ptr, uint32_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stq_le_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val, + MemOpIdx oi, uintptr_t ra); + #if defined(CONFIG_USER_ONLY) extern __thread uintptr_t helper_retaddr; @@ -193,119 +257,6 @@ static inline void clear_helper_retaddr(void) helper_retaddr = 0; } -/* - * Provide the same *_mmuidx_ra interface as for softmmu. - * The mmu_idx argument is ignored. - */ - -static inline uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldub_data_ra(env, addr, ra); -} - -static inline int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldsb_data_ra(env, addr, ra); -} - -static inline uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_lduw_be_data_ra(env, addr, ra); -} - -static inline int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldsw_be_data_ra(env, addr, ra); -} - -static inline uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldl_be_data_ra(env, addr, ra); -} - -static inline uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldq_be_data_ra(env, addr, ra); -} - -static inline uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_lduw_le_data_ra(env, addr, ra); -} - -static inline int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldsw_le_data_ra(env, addr, ra); -} - -static inline uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldl_le_data_ra(env, addr, ra); -} - -static inline uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldq_le_data_ra(env, addr, ra); -} - -static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, int mmu_idx, uintptr_t ra) -{ - cpu_stb_data_ra(env, addr, val, ra); -} - -static inline void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stw_be_data_ra(env, addr, val, ra); -} - -static inline void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stl_be_data_ra(env, addr, val, ra); -} - -static inline void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint64_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stq_be_data_ra(env, addr, val, ra); -} - -static inline void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stw_le_data_ra(env, addr, val, ra); -} - -static inline void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stl_le_data_ra(env, addr, val, ra); -} - -static inline void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint64_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stq_le_data_ra(env, addr, val, ra); -} - #else /* Needed for TCG_OVERSIZED_GUEST */ @@ -336,46 +287,6 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; } -uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); - -uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); - -uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); - -void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t retaddr); - -void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t retaddr); -void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t retaddr); -void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, - int mmu_idx, uintptr_t retaddr); - -void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t retaddr); -void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t retaddr); -void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, - int mmu_idx, uintptr_t retaddr); - #endif /* defined(CONFIG_USER_ONLY) */ #ifdef TARGET_WORDS_BIGENDIAN @@ -391,6 +302,9 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, # define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra # define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra # define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra +# define cpu_ldw_mmu cpu_ldw_be_mmu +# define cpu_ldl_mmu cpu_ldl_be_mmu +# define cpu_ldq_mmu cpu_ldq_be_mmu # define cpu_stw_data cpu_stw_be_data # define cpu_stl_data cpu_stl_be_data # define cpu_stq_data cpu_stq_be_data @@ -400,6 +314,9 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, # define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra # define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra # define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra +# define cpu_stw_mmu cpu_stw_be_mmu +# define cpu_stl_mmu cpu_stl_be_mmu +# define cpu_stq_mmu cpu_stq_be_mmu #else # define cpu_lduw_data cpu_lduw_le_data # define cpu_ldsw_data cpu_ldsw_le_data @@ -413,6 +330,9 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, # define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra # define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra # define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra +# define cpu_ldw_mmu cpu_ldw_le_mmu +# define cpu_ldl_mmu cpu_ldl_le_mmu +# define cpu_ldq_mmu cpu_ldq_le_mmu # define cpu_stw_data cpu_stw_le_data # define cpu_stl_data cpu_stl_le_data # define cpu_stq_data cpu_stq_le_data @@ -422,6 +342,9 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, # define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra # define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra # define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra +# define cpu_stw_mmu cpu_stw_le_mmu +# define cpu_stl_mmu cpu_stl_le_mmu +# define cpu_stq_mmu cpu_stq_le_mmu #endif uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 46140ccff3..b350cafa3d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1839,6 +1839,25 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, cpu_loop_exit_atomic(env_cpu(env), retaddr); } +/* + * Verify that we have passed the correct MemOp to the correct function. + * + * In the case of the helper_*_mmu functions, we will have done this by + * using the MemOp to look up the helper during code generation. + * + * In the case of the cpu_*_mmu functions, this is up to the caller. + * We could present one function to target code, and dispatch based on + * the MemOp, but so far we have worked hard to avoid an indirect function + * call along the memory path. + */ +static void validate_memop(MemOpIdx oi, MemOp expected) +{ +#ifdef CONFIG_DEBUG_TCG + MemOp have = get_memop(oi) & (MO_SIZE | MO_BSWAP); + assert(have == expected); +#endif +} + /* * Load Helpers * @@ -1992,6 +2011,7 @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi, static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_UB); return load_helper(env, addr, oi, retaddr, MO_UB, false, full_ldub_mmu); } @@ -2004,6 +2024,7 @@ tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_LEUW); return load_helper(env, addr, oi, retaddr, MO_LEUW, false, full_le_lduw_mmu); } @@ -2017,6 +2038,7 @@ tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_BEUW); return load_helper(env, addr, oi, retaddr, MO_BEUW, false, full_be_lduw_mmu); } @@ -2030,6 +2052,7 @@ tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_LEUL); return load_helper(env, addr, oi, retaddr, MO_LEUL, false, full_le_ldul_mmu); } @@ -2043,6 +2066,7 @@ tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_BEUL); return load_helper(env, addr, oi, retaddr, MO_BEUL, false, full_be_ldul_mmu); } @@ -2056,6 +2080,7 @@ tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_LEQ); return load_helper(env, addr, oi, retaddr, MO_LEQ, false, helper_le_ldq_mmu); } @@ -2063,6 +2088,7 @@ uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_BEQ); return load_helper(env, addr, oi, retaddr, MO_BEQ, false, helper_be_ldq_mmu); } @@ -2108,186 +2134,56 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, */ static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t retaddr, - MemOp op, FullLoadHelper *full_load) + MemOpIdx oi, uintptr_t retaddr, + FullLoadHelper *full_load) { - MemOpIdx oi = make_memop_idx(op, mmu_idx); uint64_t ret; trace_guest_ld_before_exec(env_cpu(env), addr, oi); - ret = full_load(env, addr, oi, retaddr); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return ret; } -uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, mmu_idx, ra, MO_UB, full_ldub_mmu); + return cpu_load_helper(env, addr, oi, ra, full_ldub_mmu); } -int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return (int8_t)cpu_ldub_mmuidx_ra(env, addr, mmu_idx, ra); + return cpu_load_helper(env, addr, oi, ra, full_be_lduw_mmu); } -uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUW, full_be_lduw_mmu); + return cpu_load_helper(env, addr, oi, ra, full_be_ldul_mmu); } -int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra); + return cpu_load_helper(env, addr, oi, MO_BEQ, helper_be_ldq_mmu); } -uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUL, full_be_ldul_mmu); + return cpu_load_helper(env, addr, oi, ra, full_le_lduw_mmu); } -uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEQ, helper_be_ldq_mmu); + return cpu_load_helper(env, addr, oi, ra, full_le_ldul_mmu); } -uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUW, full_le_lduw_mmu); -} - -int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return (int16_t)cpu_lduw_le_mmuidx_ra(env, addr, mmu_idx, ra); -} - -uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUL, full_le_ldul_mmu); -} - -uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEQ, helper_le_ldq_mmu); -} - -uint32_t cpu_ldub_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_ldub_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr); -} - -int cpu_ldsb_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr) -{ - return cpu_ldsb_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr); -} - -uint32_t cpu_lduw_be_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_lduw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr); -} - -int cpu_ldsw_be_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr) -{ - return cpu_ldsw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr); -} - -uint32_t cpu_ldl_be_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_ldl_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr); -} - -uint64_t cpu_ldq_be_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_ldq_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr); -} - -uint32_t cpu_lduw_le_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_lduw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr); -} - -int cpu_ldsw_le_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr) -{ - return cpu_ldsw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr); -} - -uint32_t cpu_ldl_le_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_ldl_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr); -} - -uint64_t cpu_ldq_le_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_ldq_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr); -} - -uint32_t cpu_ldub_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldub_data_ra(env, ptr, 0); -} - -int cpu_ldsb_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldsb_data_ra(env, ptr, 0); -} - -uint32_t cpu_lduw_be_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_lduw_be_data_ra(env, ptr, 0); -} - -int cpu_ldsw_be_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldsw_be_data_ra(env, ptr, 0); -} - -uint32_t cpu_ldl_be_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldl_be_data_ra(env, ptr, 0); -} - -uint64_t cpu_ldq_be_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldq_be_data_ra(env, ptr, 0); -} - -uint32_t cpu_lduw_le_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_lduw_le_data_ra(env, ptr, 0); -} - -int cpu_ldsw_le_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldsw_le_data_ra(env, ptr, 0); -} - -uint32_t cpu_ldl_le_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldl_le_data_ra(env, ptr, 0); -} - -uint64_t cpu_ldq_le_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldq_le_data_ra(env, ptr, 0); + return cpu_load_helper(env, addr, oi, ra, helper_le_ldq_mmu); } /* @@ -2324,6 +2220,9 @@ store_memop(void *haddr, uint64_t val, MemOp op) } } +static void full_stb_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr); + static void __attribute__((noinline)) store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val, uintptr_t retaddr, size_t size, uintptr_t mmu_idx, @@ -2387,13 +2286,13 @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val, for (i = 0; i < size; ++i) { /* Big-endian extract. */ uint8_t val8 = val >> (((size - 1) * 8) - (i * 8)); - helper_ret_stb_mmu(env, addr + i, val8, oi, retaddr); + full_stb_mmu(env, addr + i, val8, oi, retaddr); } } else { for (i = 0; i < size; ++i) { /* Little-endian extract. */ uint8_t val8 = val >> (i * 8); - helper_ret_stb_mmu(env, addr + i, val8, oi, retaddr); + full_stb_mmu(env, addr + i, val8, oi, retaddr); } } } @@ -2496,46 +2395,83 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, store_memop(haddr, val, op); } -void __attribute__((noinline)) -helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, - MemOpIdx oi, uintptr_t retaddr) +static void __attribute__((noinline)) +full_stb_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_UB); store_helper(env, addr, val, oi, retaddr, MO_UB); } +void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, + MemOpIdx oi, uintptr_t retaddr) +{ + full_stb_mmu(env, addr, val, oi, retaddr); +} + +static void full_le_stw_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr) +{ + validate_memop(oi, MO_LEUW); + store_helper(env, addr, val, oi, retaddr, MO_LEUW); +} + void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, MemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, MO_LEUW); + full_le_stw_mmu(env, addr, val, oi, retaddr); +} + +static void full_be_stw_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr) +{ + validate_memop(oi, MO_BEUW); + store_helper(env, addr, val, oi, retaddr, MO_BEUW); } void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, MemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, MO_BEUW); + full_be_stw_mmu(env, addr, val, oi, retaddr); +} + +static void full_le_stl_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr) +{ + validate_memop(oi, MO_LEUL); + store_helper(env, addr, val, oi, retaddr, MO_LEUL); } void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, MO_LEUL); + full_le_stl_mmu(env, addr, val, oi, retaddr); +} + +static void full_be_stl_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr) +{ + validate_memop(oi, MO_BEUL); + store_helper(env, addr, val, oi, retaddr, MO_BEUL); } void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, MO_BEUL); + full_be_stl_mmu(env, addr, val, oi, retaddr); } void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_LEQ); store_helper(env, addr, val, oi, retaddr, MO_LEQ); } void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_BEQ); store_helper(env, addr, val, oi, retaddr, MO_BEQ); } @@ -2543,137 +2479,61 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, * Store Helpers for cpu_ldst.h */ -static inline void QEMU_ALWAYS_INLINE -cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val, - int mmu_idx, uintptr_t retaddr, MemOp op) +typedef void FullStoreHelper(CPUArchState *env, target_ulong addr, + uint64_t val, MemOpIdx oi, uintptr_t retaddr); + +static inline void cpu_store_helper(CPUArchState *env, target_ulong addr, + uint64_t val, MemOpIdx oi, uintptr_t ra, + FullStoreHelper *full_store) { - MemOpIdx oi = make_memop_idx(op, mmu_idx); - trace_guest_st_before_exec(env_cpu(env), addr, oi); - - store_helper(env, addr, val, oi, retaddr, op); - + full_store(env, addr, val, oi, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } -void cpu_stb_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val, - int mmu_idx, uintptr_t retaddr) +void cpu_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_UB); + cpu_store_helper(env, addr, val, oi, retaddr, full_stb_mmu); } -void cpu_stw_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val, - int mmu_idx, uintptr_t retaddr) +void cpu_stw_be_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUW); + cpu_store_helper(env, addr, val, oi, retaddr, full_be_stw_mmu); } -void cpu_stl_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val, - int mmu_idx, uintptr_t retaddr) +void cpu_stl_be_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUL); + cpu_store_helper(env, addr, val, oi, retaddr, full_be_stl_mmu); } -void cpu_stq_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val, - int mmu_idx, uintptr_t retaddr) +void cpu_stq_be_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEQ); + cpu_store_helper(env, addr, val, oi, retaddr, helper_be_stq_mmu); } -void cpu_stw_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val, - int mmu_idx, uintptr_t retaddr) +void cpu_stw_le_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUW); + cpu_store_helper(env, addr, val, oi, retaddr, full_le_stw_mmu); } -void cpu_stl_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val, - int mmu_idx, uintptr_t retaddr) +void cpu_stl_le_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUL); + cpu_store_helper(env, addr, val, oi, retaddr, full_le_stl_mmu); } -void cpu_stq_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val, - int mmu_idx, uintptr_t retaddr) +void cpu_stq_le_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEQ); + cpu_store_helper(env, addr, val, oi, retaddr, helper_le_stq_mmu); } -void cpu_stb_data_ra(CPUArchState *env, target_ulong ptr, - uint32_t val, uintptr_t retaddr) -{ - cpu_stb_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr); -} - -void cpu_stw_be_data_ra(CPUArchState *env, target_ulong ptr, - uint32_t val, uintptr_t retaddr) -{ - cpu_stw_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr); -} - -void cpu_stl_be_data_ra(CPUArchState *env, target_ulong ptr, - uint32_t val, uintptr_t retaddr) -{ - cpu_stl_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr); -} - -void cpu_stq_be_data_ra(CPUArchState *env, target_ulong ptr, - uint64_t val, uintptr_t retaddr) -{ - cpu_stq_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr); -} - -void cpu_stw_le_data_ra(CPUArchState *env, target_ulong ptr, - uint32_t val, uintptr_t retaddr) -{ - cpu_stw_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr); -} - -void cpu_stl_le_data_ra(CPUArchState *env, target_ulong ptr, - uint32_t val, uintptr_t retaddr) -{ - cpu_stl_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr); -} - -void cpu_stq_le_data_ra(CPUArchState *env, target_ulong ptr, - uint64_t val, uintptr_t retaddr) -{ - cpu_stq_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr); -} - -void cpu_stb_data(CPUArchState *env, target_ulong ptr, uint32_t val) -{ - cpu_stb_data_ra(env, ptr, val, 0); -} - -void cpu_stw_be_data(CPUArchState *env, target_ulong ptr, uint32_t val) -{ - cpu_stw_be_data_ra(env, ptr, val, 0); -} - -void cpu_stl_be_data(CPUArchState *env, target_ulong ptr, uint32_t val) -{ - cpu_stl_be_data_ra(env, ptr, val, 0); -} - -void cpu_stq_be_data(CPUArchState *env, target_ulong ptr, uint64_t val) -{ - cpu_stq_be_data_ra(env, ptr, val, 0); -} - -void cpu_stw_le_data(CPUArchState *env, target_ulong ptr, uint32_t val) -{ - cpu_stw_le_data_ra(env, ptr, val, 0); -} - -void cpu_stl_le_data(CPUArchState *env, target_ulong ptr, uint32_t val) -{ - cpu_stl_le_data_ra(env, ptr, val, 0); -} - -void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val) -{ - cpu_stq_le_data_ra(env, ptr, val, 0); -} +#include "ldst_common.c.inc" /* * First set of functions passes in OI and RETADDR. diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5dcd58c6d5..7d50dd54f6 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -202,300 +202,232 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, /* The softmmu versions of these helpers are in cputlb.c. */ -uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) +/* + * Verify that we have passed the correct MemOp to the correct function. + * + * We could present one function to target code, and dispatch based on + * the MemOp, but so far we have worked hard to avoid an indirect function + * call along the memory path. + */ +static void validate_memop(MemOpIdx oi, MemOp expected) { - MemOpIdx oi = make_memop_idx(MO_UB, MMU_USER_IDX); - uint32_t ret; +#ifdef CONFIG_DEBUG_TCG + MemOp have = get_memop(oi) & (MO_SIZE | MO_BSWAP); + assert(have == expected); +#endif +} - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret = ldub_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); +static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t ra, MMUAccessType type) +{ + MemOp mop = get_memop(oi); + int a_bits = get_alignment_bits(mop); + void *ret; + + /* Enforce guest required alignment. */ + if (unlikely(addr & ((1 << a_bits) - 1))) { + cpu_loop_exit_sigbus(env_cpu(env), addr, type, ra); + } + + ret = g2h(env_cpu(env), addr); + set_helper_retaddr(ra); return ret; } -int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr) +uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return (int8_t)cpu_ldub_data(env, ptr); -} + void *haddr; + uint8_t ret; -uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr) -{ - MemOpIdx oi = make_memop_idx(MO_BEUW, MMU_USER_IDX); - uint32_t ret; - - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret = lduw_be_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); + validate_memop(oi, MO_UB); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret = ldub_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } -int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr) +uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return (int16_t)cpu_lduw_be_data(env, ptr); -} + void *haddr; + uint16_t ret; -uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr) -{ - MemOpIdx oi = make_memop_idx(MO_BEUL, MMU_USER_IDX); - uint32_t ret; - - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret = ldl_be_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); + validate_memop(oi, MO_BEUW); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret = lduw_be_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } -uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr) +uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - MemOpIdx oi = make_memop_idx(MO_BEQ, MMU_USER_IDX); + void *haddr; + uint32_t ret; + + validate_memop(oi, MO_BEUL); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret = ldl_be_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + return ret; +} + +uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; uint64_t ret; - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret = ldq_be_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); + validate_memop(oi, MO_BEQ); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret = ldq_be_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } -uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr) +uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - MemOpIdx oi = make_memop_idx(MO_LEUW, MMU_USER_IDX); + void *haddr; + uint16_t ret; + + validate_memop(oi, MO_LEUW); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret = lduw_le_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + return ret; +} + +uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; uint32_t ret; - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret = lduw_le_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); + validate_memop(oi, MO_LEUL); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret = ldl_le_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } -int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr) +uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return (int16_t)cpu_lduw_le_data(env, ptr); -} - -uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr) -{ - MemOpIdx oi = make_memop_idx(MO_LEUL, MMU_USER_IDX); - uint32_t ret; - - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret = ldl_le_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); - return ret; -} - -uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr) -{ - MemOpIdx oi = make_memop_idx(MO_LEQ, MMU_USER_IDX); + void *haddr; uint64_t ret; - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret = ldq_le_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); + validate_memop(oi, MO_LEQ); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret = ldq_le_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } -uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) +void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, + MemOpIdx oi, uintptr_t ra) { - uint32_t ret; + void *haddr; - set_helper_retaddr(retaddr); - ret = cpu_ldub_data(env, ptr); + validate_memop(oi, MO_UB); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stb_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } -int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) +void cpu_stw_be_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, + MemOpIdx oi, uintptr_t ra) { - return (int8_t)cpu_ldub_data_ra(env, ptr, retaddr); -} + void *haddr; -uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) -{ - uint32_t ret; - - set_helper_retaddr(retaddr); - ret = cpu_lduw_be_data(env, ptr); + validate_memop(oi, MO_BEUW); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stw_be_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } -int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) +void cpu_stl_be_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, + MemOpIdx oi, uintptr_t ra) { - return (int16_t)cpu_lduw_be_data_ra(env, ptr, retaddr); -} + void *haddr; -uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) -{ - uint32_t ret; - - set_helper_retaddr(retaddr); - ret = cpu_ldl_be_data(env, ptr); + validate_memop(oi, MO_BEUL); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stl_be_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } -uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) +void cpu_stq_be_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, + MemOpIdx oi, uintptr_t ra) { - uint64_t ret; + void *haddr; - set_helper_retaddr(retaddr); - ret = cpu_ldq_be_data(env, ptr); + validate_memop(oi, MO_BEQ); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stq_be_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } -uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) +void cpu_stw_le_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, + MemOpIdx oi, uintptr_t ra) { - uint32_t ret; + void *haddr; - set_helper_retaddr(retaddr); - ret = cpu_lduw_le_data(env, ptr); + validate_memop(oi, MO_LEUW); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stw_le_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } -int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) +void cpu_stl_le_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, + MemOpIdx oi, uintptr_t ra) { - return (int16_t)cpu_lduw_le_data_ra(env, ptr, retaddr); -} + void *haddr; -uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) -{ - uint32_t ret; - - set_helper_retaddr(retaddr); - ret = cpu_ldl_le_data(env, ptr); + validate_memop(oi, MO_LEUL); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stl_le_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } -uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) +void cpu_stq_le_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, + MemOpIdx oi, uintptr_t ra) { - uint64_t ret; + void *haddr; - set_helper_retaddr(retaddr); - ret = cpu_ldq_le_data(env, ptr); - clear_helper_retaddr(); - return ret; -} - -void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val) -{ - MemOpIdx oi = make_memop_idx(MO_UB, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stb_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) -{ - MemOpIdx oi = make_memop_idx(MO_BEUW, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stw_be_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) -{ - MemOpIdx oi = make_memop_idx(MO_BEUL, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stl_be_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val) -{ - MemOpIdx oi = make_memop_idx(MO_BEQ, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stq_be_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) -{ - MemOpIdx oi = make_memop_idx(MO_LEUW, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stw_le_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) -{ - MemOpIdx oi = make_memop_idx(MO_LEUL, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stl_le_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val) -{ - MemOpIdx oi = make_memop_idx(MO_LEQ, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stq_le_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stb_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stw_be_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stl_be_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr, - uint64_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stq_be_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stw_le_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stl_le_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr, - uint64_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stq_le_data(env, ptr, val); + validate_memop(oi, MO_LEQ); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stq_le_p(haddr, val); clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr) @@ -538,6 +470,8 @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr) return ret; } +#include "ldst_common.c.inc" + /* * Do not allow unaligned operations to proceed. Return the host address. * diff --git a/accel/tcg/ldst_common.c.inc b/accel/tcg/ldst_common.c.inc new file mode 100644 index 0000000000..bfefb275e7 --- /dev/null +++ b/accel/tcg/ldst_common.c.inc @@ -0,0 +1,307 @@ +/* + * Routines common to user and system emulation of load/store. + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); + return cpu_ldb_mmu(env, addr, oi, ra); +} + +int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + return (int8_t)cpu_ldub_mmuidx_ra(env, addr, mmu_idx, ra); +} + +uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi = make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx); + return cpu_ldw_be_mmu(env, addr, oi, ra); +} + +int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra); +} + +uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi = make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx); + return cpu_ldl_be_mmu(env, addr, oi, ra); +} + +uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi = make_memop_idx(MO_BEQ | MO_UNALN, mmu_idx); + return cpu_ldq_be_mmu(env, addr, oi, ra); +} + +uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi = make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx); + return cpu_ldw_le_mmu(env, addr, oi, ra); +} + +int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + return (int16_t)cpu_lduw_le_mmuidx_ra(env, addr, mmu_idx, ra); +} + +uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi = make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx); + return cpu_ldl_le_mmu(env, addr, oi, ra); +} + +uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi = make_memop_idx(MO_LEQ | MO_UNALN, mmu_idx); + return cpu_ldq_le_mmu(env, addr, oi, ra); +} + +void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); + cpu_stb_mmu(env, addr, val, oi, ra); +} + +void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi = make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx); + cpu_stw_be_mmu(env, addr, val, oi, ra); +} + +void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi = make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx); + cpu_stl_be_mmu(env, addr, val, oi, ra); +} + +void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi = make_memop_idx(MO_BEQ | MO_UNALN, mmu_idx); + cpu_stq_be_mmu(env, addr, val, oi, ra); +} + +void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi = make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx); + cpu_stw_le_mmu(env, addr, val, oi, ra); +} + +void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi = make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx); + cpu_stl_le_mmu(env, addr, val, oi, ra); +} + +void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi = make_memop_idx(MO_LEQ | MO_UNALN, mmu_idx); + cpu_stq_le_mmu(env, addr, val, oi, ra); +} + +/*--------------------------*/ + +uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_ldub_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return (int8_t)cpu_ldub_data_ra(env, addr, ra); +} + +uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_lduw_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return (int16_t)cpu_lduw_be_data_ra(env, addr, ra); +} + +uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_ldl_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_ldq_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_lduw_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return (int16_t)cpu_lduw_le_data_ra(env, addr, ra); +} + +uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_ldl_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_ldq_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +void cpu_stb_data_ra(CPUArchState *env, abi_ptr addr, + uint32_t val, uintptr_t ra) +{ + cpu_stb_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr addr, + uint32_t val, uintptr_t ra) +{ + cpu_stw_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr addr, + uint32_t val, uintptr_t ra) +{ + cpu_stl_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr addr, + uint64_t val, uintptr_t ra) +{ + cpu_stq_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr addr, + uint32_t val, uintptr_t ra) +{ + cpu_stw_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr addr, + uint32_t val, uintptr_t ra) +{ + cpu_stl_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr addr, + uint64_t val, uintptr_t ra) +{ + cpu_stq_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +/*--------------------------*/ + +uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldub_data_ra(env, addr, 0); +} + +int cpu_ldsb_data(CPUArchState *env, abi_ptr addr) +{ + return (int8_t)cpu_ldub_data(env, addr); +} + +uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_lduw_be_data_ra(env, addr, 0); +} + +int cpu_ldsw_be_data(CPUArchState *env, abi_ptr addr) +{ + return (int16_t)cpu_lduw_be_data(env, addr); +} + +uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldl_be_data_ra(env, addr, 0); +} + +uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldq_be_data_ra(env, addr, 0); +} + +uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_lduw_le_data_ra(env, addr, 0); +} + +int cpu_ldsw_le_data(CPUArchState *env, abi_ptr addr) +{ + return (int16_t)cpu_lduw_le_data(env, addr); +} + +uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldl_le_data_ra(env, addr, 0); +} + +uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldq_le_data_ra(env, addr, 0); +} + +void cpu_stb_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stb_data_ra(env, addr, val, 0); +} + +void cpu_stw_be_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stw_be_data_ra(env, addr, val, 0); +} + +void cpu_stl_be_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stl_be_data_ra(env, addr, val, 0); +} + +void cpu_stq_be_data(CPUArchState *env, abi_ptr addr, uint64_t val) +{ + cpu_stq_be_data_ra(env, addr, val, 0); +} + +void cpu_stw_le_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stw_le_data_ra(env, addr, val, 0); +} + +void cpu_stl_le_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stl_le_data_ra(env, addr, val, 0); +} + +void cpu_stq_le_data(CPUArchState *env, abi_ptr addr, uint64_t val) +{ + cpu_stq_le_data_ra(env, addr, val, 0); +} From patchwork Wed Oct 13 02:45:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515692 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6085808ime; 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Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 87 +++++++++++++++++++++++++++++++++++ include/tcg/tcg.h | 87 ----------------------------------- target/arm/helper-a64.c | 1 - target/m68k/op_helper.c | 1 - target/ppc/mem_helper.c | 1 - target/s390x/tcg/mem_helper.c | 1 - 6 files changed, 87 insertions(+), 91 deletions(-) -- 2.25.1 diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index a4dad0772f..a878fd0105 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -63,6 +63,7 @@ #define CPU_LDST_H #include "exec/memopidx.h" +#include "qemu/int128.h" #if defined(CONFIG_USER_ONLY) /* sparc32plus has 64bit long but 32bit space address @@ -233,6 +234,92 @@ void cpu_stl_le_mmu(CPUArchState *env, abi_ptr ptr, uint32_t val, void cpu_stq_le_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val, MemOpIdx oi, uintptr_t ra); +uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr, + uint64_t cmpv, uint64_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr, + uint64_t cmpv, uint64_t newv, + MemOpIdx oi, uintptr_t retaddr); + +#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ +TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \ + (CPUArchState *env, target_ulong addr, TYPE val, \ + MemOpIdx oi, uintptr_t retaddr); + +#ifdef CONFIG_ATOMIC64 +#define GEN_ATOMIC_HELPER_ALL(NAME) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ + GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ + GEN_ATOMIC_HELPER(NAME, uint64_t, q_be) +#else +#define GEN_ATOMIC_HELPER_ALL(NAME) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) +#endif + +GEN_ATOMIC_HELPER_ALL(fetch_add) +GEN_ATOMIC_HELPER_ALL(fetch_sub) +GEN_ATOMIC_HELPER_ALL(fetch_and) +GEN_ATOMIC_HELPER_ALL(fetch_or) +GEN_ATOMIC_HELPER_ALL(fetch_xor) +GEN_ATOMIC_HELPER_ALL(fetch_smin) +GEN_ATOMIC_HELPER_ALL(fetch_umin) +GEN_ATOMIC_HELPER_ALL(fetch_smax) +GEN_ATOMIC_HELPER_ALL(fetch_umax) + +GEN_ATOMIC_HELPER_ALL(add_fetch) +GEN_ATOMIC_HELPER_ALL(sub_fetch) +GEN_ATOMIC_HELPER_ALL(and_fetch) +GEN_ATOMIC_HELPER_ALL(or_fetch) +GEN_ATOMIC_HELPER_ALL(xor_fetch) +GEN_ATOMIC_HELPER_ALL(smin_fetch) +GEN_ATOMIC_HELPER_ALL(umin_fetch) +GEN_ATOMIC_HELPER_ALL(smax_fetch) +GEN_ATOMIC_HELPER_ALL(umax_fetch) + +GEN_ATOMIC_HELPER_ALL(xchg) + +#undef GEN_ATOMIC_HELPER_ALL +#undef GEN_ATOMIC_HELPER + +Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, + Int128 cmpv, Int128 newv, + MemOpIdx oi, uintptr_t retaddr); +Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr, + Int128 cmpv, Int128 newv, + MemOpIdx oi, uintptr_t retaddr); + +Int128 cpu_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +Int128 cpu_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +void cpu_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val, + MemOpIdx oi, uintptr_t retaddr); +void cpu_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val, + MemOpIdx oi, uintptr_t retaddr); + #if defined(CONFIG_USER_ONLY) extern __thread uintptr_t helper_retaddr; diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 9f398b9afe..83e38487cf 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -33,7 +33,6 @@ #include "qemu/queue.h" #include "tcg/tcg-mo.h" #include "tcg-target.h" -#include "qemu/int128.h" #include "tcg/tcg-cond.h" /* XXX: make safe guess about sizes */ @@ -1312,92 +1311,6 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, #endif #endif /* CONFIG_SOFTMMU */ -uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr, - uint64_t cmpv, uint64_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr, - uint64_t cmpv, uint64_t newv, - MemOpIdx oi, uintptr_t retaddr); - -#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ -TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \ - (CPUArchState *env, target_ulong addr, TYPE val, \ - MemOpIdx oi, uintptr_t retaddr); - -#ifdef CONFIG_ATOMIC64 -#define GEN_ATOMIC_HELPER_ALL(NAME) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ - GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ - GEN_ATOMIC_HELPER(NAME, uint64_t, q_be) -#else -#define GEN_ATOMIC_HELPER_ALL(NAME) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) -#endif - -GEN_ATOMIC_HELPER_ALL(fetch_add) -GEN_ATOMIC_HELPER_ALL(fetch_sub) -GEN_ATOMIC_HELPER_ALL(fetch_and) -GEN_ATOMIC_HELPER_ALL(fetch_or) -GEN_ATOMIC_HELPER_ALL(fetch_xor) -GEN_ATOMIC_HELPER_ALL(fetch_smin) -GEN_ATOMIC_HELPER_ALL(fetch_umin) -GEN_ATOMIC_HELPER_ALL(fetch_smax) -GEN_ATOMIC_HELPER_ALL(fetch_umax) - -GEN_ATOMIC_HELPER_ALL(add_fetch) -GEN_ATOMIC_HELPER_ALL(sub_fetch) -GEN_ATOMIC_HELPER_ALL(and_fetch) -GEN_ATOMIC_HELPER_ALL(or_fetch) -GEN_ATOMIC_HELPER_ALL(xor_fetch) -GEN_ATOMIC_HELPER_ALL(smin_fetch) -GEN_ATOMIC_HELPER_ALL(umin_fetch) -GEN_ATOMIC_HELPER_ALL(smax_fetch) -GEN_ATOMIC_HELPER_ALL(umax_fetch) - -GEN_ATOMIC_HELPER_ALL(xchg) - -#undef GEN_ATOMIC_HELPER_ALL -#undef GEN_ATOMIC_HELPER - -Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, - Int128 cmpv, Int128 newv, - MemOpIdx oi, uintptr_t retaddr); -Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr, - Int128 cmpv, Int128 newv, - MemOpIdx oi, uintptr_t retaddr); - -Int128 cpu_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -Int128 cpu_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -void cpu_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val, - MemOpIdx oi, uintptr_t retaddr); -void cpu_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val, - MemOpIdx oi, uintptr_t retaddr); - #ifdef CONFIG_DEBUG_TCG void tcg_assert_listed_vecop(TCGOpcode); #else diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 4cafd3c11a..b110c57956 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -32,7 +32,6 @@ #include "exec/cpu_ldst.h" #include "qemu/int128.h" #include "qemu/atomic128.h" -#include "tcg/tcg.h" #include "fpu/softfloat.h" #include /* For crc32 */ diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index c1bf73b6f9..cfbc987ba6 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -22,7 +22,6 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "semihosting/semihost.h" -#include "tcg/tcg.h" #if !defined(CONFIG_USER_ONLY) diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index e2282baa8d..39945d9ea5 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -25,7 +25,6 @@ #include "exec/helper-proto.h" #include "helper_regs.h" #include "exec/cpu_ldst.h" -#include "tcg/tcg.h" #include "internal.h" #include "qemu/atomic128.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 8624385fe1..f50c3f88a2 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -27,7 +27,6 @@ #include "exec/cpu_ldst.h" #include "qemu/int128.h" #include "qemu/atomic128.h" -#include "tcg/tcg.h" #include "trace.h" #if !defined(CONFIG_USER_ONLY) From patchwork Wed Oct 13 02:45:43 2021 Content-Type: text/plain; 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Nor should we have been using the plain cpu_*_data set of functions, as they do not handle unwinding properly. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/tcg/msa_helper.c | 420 +++++++++++------------------------ 1 file changed, 135 insertions(+), 285 deletions(-) -- 2.25.1 diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 167d9a591c..a8880ce81c 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8222,79 +8222,42 @@ void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_BYTE) -#if !defined(CONFIG_USER_ONLY) + uintptr_t ra = GETPC(); + #if !defined(HOST_WORDS_BIGENDIAN) - pwd->b[0] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC()); - pwd->b[1] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC()); - pwd->b[2] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC()); - pwd->b[3] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC()); - pwd->b[4] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC()); - pwd->b[5] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC()); - pwd->b[6] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC()); - pwd->b[7] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC()); - pwd->b[8] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC()); - pwd->b[9] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC()); - pwd->b[10] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC()); - pwd->b[11] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC()); - pwd->b[12] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC()); - pwd->b[13] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC()); - pwd->b[14] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC()); - pwd->b[15] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC()); + pwd->b[0] = cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra); + pwd->b[1] = cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra); + pwd->b[2] = cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra); + pwd->b[3] = cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra); + pwd->b[4] = cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra); + pwd->b[5] = cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra); + pwd->b[6] = cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra); + pwd->b[7] = cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra); + pwd->b[8] = cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra); + pwd->b[9] = cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra); + pwd->b[10] = cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra); + pwd->b[11] = cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra); + pwd->b[12] = cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra); + pwd->b[13] = cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra); + pwd->b[14] = cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra); + pwd->b[15] = cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra); #else - pwd->b[0] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC()); - pwd->b[1] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC()); - pwd->b[2] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC()); - pwd->b[3] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC()); - pwd->b[4] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC()); - pwd->b[5] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC()); - pwd->b[6] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC()); - pwd->b[7] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC()); - pwd->b[8] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC()); - pwd->b[9] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC()); - pwd->b[10] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC()); - pwd->b[11] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC()); - pwd->b[12] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC()); - pwd->b[13] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC()); - pwd->b[14] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC()); - pwd->b[15] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->b[0] = cpu_ldub_data(env, addr + (0 << DF_BYTE)); - pwd->b[1] = cpu_ldub_data(env, addr + (1 << DF_BYTE)); - pwd->b[2] = cpu_ldub_data(env, addr + (2 << DF_BYTE)); - pwd->b[3] = cpu_ldub_data(env, addr + (3 << DF_BYTE)); - pwd->b[4] = cpu_ldub_data(env, addr + (4 << DF_BYTE)); - pwd->b[5] = cpu_ldub_data(env, addr + (5 << DF_BYTE)); - pwd->b[6] = cpu_ldub_data(env, addr + (6 << DF_BYTE)); - pwd->b[7] = cpu_ldub_data(env, addr + (7 << DF_BYTE)); - pwd->b[8] = cpu_ldub_data(env, addr + (8 << DF_BYTE)); - pwd->b[9] = cpu_ldub_data(env, addr + (9 << DF_BYTE)); - pwd->b[10] = cpu_ldub_data(env, addr + (10 << DF_BYTE)); - pwd->b[11] = cpu_ldub_data(env, addr + (11 << DF_BYTE)); - pwd->b[12] = cpu_ldub_data(env, addr + (12 << DF_BYTE)); - pwd->b[13] = cpu_ldub_data(env, addr + (13 << DF_BYTE)); - pwd->b[14] = cpu_ldub_data(env, addr + (14 << DF_BYTE)); - pwd->b[15] = cpu_ldub_data(env, addr + (15 << DF_BYTE)); -#else - pwd->b[0] = cpu_ldub_data(env, addr + (7 << DF_BYTE)); - pwd->b[1] = cpu_ldub_data(env, addr + (6 << DF_BYTE)); - pwd->b[2] = cpu_ldub_data(env, addr + (5 << DF_BYTE)); - pwd->b[3] = cpu_ldub_data(env, addr + (4 << DF_BYTE)); - pwd->b[4] = cpu_ldub_data(env, addr + (3 << DF_BYTE)); - pwd->b[5] = cpu_ldub_data(env, addr + (2 << DF_BYTE)); - pwd->b[6] = cpu_ldub_data(env, addr + (1 << DF_BYTE)); - pwd->b[7] = cpu_ldub_data(env, addr + (0 << DF_BYTE)); - pwd->b[8] = cpu_ldub_data(env, addr + (15 << DF_BYTE)); - pwd->b[9] = cpu_ldub_data(env, addr + (14 << DF_BYTE)); - pwd->b[10] = cpu_ldub_data(env, addr + (13 << DF_BYTE)); - pwd->b[11] = cpu_ldub_data(env, addr + (12 << DF_BYTE)); - pwd->b[12] = cpu_ldub_data(env, addr + (11 << DF_BYTE)); - pwd->b[13] = cpu_ldub_data(env, addr + (10 << DF_BYTE)); - pwd->b[14] = cpu_ldub_data(env, addr + (9 << DF_BYTE)); - pwd->b[15] = cpu_ldub_data(env, addr + (8 << DF_BYTE)); -#endif + pwd->b[0] = cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra); + pwd->b[1] = cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra); + pwd->b[2] = cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra); + pwd->b[3] = cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra); + pwd->b[4] = cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra); + pwd->b[5] = cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra); + pwd->b[6] = cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra); + pwd->b[7] = cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra); + pwd->b[8] = cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra); + pwd->b[9] = cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra); + pwd->b[10] = cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra); + pwd->b[11] = cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra); + pwd->b[12] = cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra); + pwd->b[13] = cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra); + pwd->b[14] = cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra); + pwd->b[15] = cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra); #endif } @@ -8302,47 +8265,26 @@ void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_HALF) -#if !defined(CONFIG_USER_ONLY) + uintptr_t ra = GETPC(); + #if !defined(HOST_WORDS_BIGENDIAN) - pwd->h[0] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC()); - pwd->h[1] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC()); - pwd->h[2] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC()); - pwd->h[3] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC()); - pwd->h[4] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC()); - pwd->h[5] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC()); - pwd->h[6] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC()); - pwd->h[7] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC()); + pwd->h[0] = cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra); + pwd->h[1] = cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra); + pwd->h[2] = cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra); + pwd->h[3] = cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra); + pwd->h[4] = cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra); + pwd->h[5] = cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra); + pwd->h[6] = cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra); + pwd->h[7] = cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra); #else - pwd->h[0] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC()); - pwd->h[1] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC()); - pwd->h[2] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC()); - pwd->h[3] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC()); - pwd->h[4] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC()); - pwd->h[5] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC()); - pwd->h[6] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC()); - pwd->h[7] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->h[0] = cpu_lduw_data(env, addr + (0 << DF_HALF)); - pwd->h[1] = cpu_lduw_data(env, addr + (1 << DF_HALF)); - pwd->h[2] = cpu_lduw_data(env, addr + (2 << DF_HALF)); - pwd->h[3] = cpu_lduw_data(env, addr + (3 << DF_HALF)); - pwd->h[4] = cpu_lduw_data(env, addr + (4 << DF_HALF)); - pwd->h[5] = cpu_lduw_data(env, addr + (5 << DF_HALF)); - pwd->h[6] = cpu_lduw_data(env, addr + (6 << DF_HALF)); - pwd->h[7] = cpu_lduw_data(env, addr + (7 << DF_HALF)); -#else - pwd->h[0] = cpu_lduw_data(env, addr + (3 << DF_HALF)); - pwd->h[1] = cpu_lduw_data(env, addr + (2 << DF_HALF)); - pwd->h[2] = cpu_lduw_data(env, addr + (1 << DF_HALF)); - pwd->h[3] = cpu_lduw_data(env, addr + (0 << DF_HALF)); - pwd->h[4] = cpu_lduw_data(env, addr + (7 << DF_HALF)); - pwd->h[5] = cpu_lduw_data(env, addr + (6 << DF_HALF)); - pwd->h[6] = cpu_lduw_data(env, addr + (5 << DF_HALF)); - pwd->h[7] = cpu_lduw_data(env, addr + (4 << DF_HALF)); -#endif + pwd->h[0] = cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra); + pwd->h[1] = cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra); + pwd->h[2] = cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra); + pwd->h[3] = cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra); + pwd->h[4] = cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra); + pwd->h[5] = cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra); + pwd->h[6] = cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra); + pwd->h[7] = cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra); #endif } @@ -8350,31 +8292,18 @@ void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_WORD) -#if !defined(CONFIG_USER_ONLY) + uintptr_t ra = GETPC(); + #if !defined(HOST_WORDS_BIGENDIAN) - pwd->w[0] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC()); - pwd->w[1] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC()); - pwd->w[2] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC()); - pwd->w[3] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC()); + pwd->w[0] = cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra); + pwd->w[1] = cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra); + pwd->w[2] = cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra); + pwd->w[3] = cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra); #else - pwd->w[0] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC()); - pwd->w[1] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC()); - pwd->w[2] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC()); - pwd->w[3] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->w[0] = cpu_ldl_data(env, addr + (0 << DF_WORD)); - pwd->w[1] = cpu_ldl_data(env, addr + (1 << DF_WORD)); - pwd->w[2] = cpu_ldl_data(env, addr + (2 << DF_WORD)); - pwd->w[3] = cpu_ldl_data(env, addr + (3 << DF_WORD)); -#else - pwd->w[0] = cpu_ldl_data(env, addr + (1 << DF_WORD)); - pwd->w[1] = cpu_ldl_data(env, addr + (0 << DF_WORD)); - pwd->w[2] = cpu_ldl_data(env, addr + (3 << DF_WORD)); - pwd->w[3] = cpu_ldl_data(env, addr + (2 << DF_WORD)); -#endif + pwd->w[0] = cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra); + pwd->w[1] = cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra); + pwd->w[2] = cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra); + pwd->w[3] = cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra); #endif } @@ -8382,14 +8311,10 @@ void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_DOUBLE) -#if !defined(CONFIG_USER_ONLY) - pwd->d[0] = helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GETPC()); - pwd->d[1] = helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GETPC()); -#else - pwd->d[0] = cpu_ldq_data(env, addr + (0 << DF_DOUBLE)); - pwd->d[1] = cpu_ldq_data(env, addr + (1 << DF_DOUBLE)); -#endif + uintptr_t ra = GETPC(); + + pwd->d[0] = cpu_ldq_data_ra(env, addr + (0 << DF_DOUBLE), ra); + pwd->d[1] = cpu_ldq_data_ra(env, addr + (1 << DF_DOUBLE), ra); } #define MSA_PAGESPAN(x) \ @@ -8415,81 +8340,44 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); int mmu_idx = cpu_mmu_index(env, false); + uintptr_t ra = GETPC(); + + ensure_writable_pages(env, addr, mmu_idx, ra); - MEMOP_IDX(DF_BYTE) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) #if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC()); + cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[0], ra); + cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[1], ra); + cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[2], ra); + cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[3], ra); + cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[4], ra); + cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[5], ra); + cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[6], ra); + cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[7], ra); + cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[8], ra); + cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[9], ra); + cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[10], ra); + cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[11], ra); + cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[12], ra); + cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[13], ra); + cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[14], ra); + cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[15], ra); #else - helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC()); - helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]); - cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]); - cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]); - cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]); - cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]); - cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]); - cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]); - cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]); - cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]); - cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]); - cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]); - cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]); - cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]); - cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]); - cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]); - cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]); -#else - cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]); - cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]); - cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]); - cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]); - cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]); - cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]); - cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]); - cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]); - cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]); - cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]); - cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]); - cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]); - cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]); - cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]); - cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]); - cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]); -#endif + cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[0], ra); + cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[1], ra); + cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[2], ra); + cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[3], ra); + cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[4], ra); + cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[5], ra); + cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[6], ra); + cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[7], ra); + cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[8], ra); + cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[9], ra); + cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[10], ra); + cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[11], ra); + cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[12], ra); + cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[13], ra); + cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[14], ra); + cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[15], ra); #endif } @@ -8498,49 +8386,28 @@ void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); int mmu_idx = cpu_mmu_index(env, false); + uintptr_t ra = GETPC(); + + ensure_writable_pages(env, addr, mmu_idx, ra); - MEMOP_IDX(DF_HALF) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) #if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC()); + cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[0], ra); + cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[1], ra); + cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[2], ra); + cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[3], ra); + cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[4], ra); + cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[5], ra); + cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[6], ra); + cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[7], ra); #else - helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]); - cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]); - cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]); - cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]); - cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]); - cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]); - cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]); - cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]); -#else - cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]); - cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]); - cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]); - cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]); - cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]); - cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]); - cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]); - cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]); -#endif + cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[0], ra); + cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[1], ra); + cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[2], ra); + cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[3], ra); + cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[4], ra); + cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[5], ra); + cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[6], ra); + cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[7], ra); #endif } @@ -8549,33 +8416,20 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); int mmu_idx = cpu_mmu_index(env, false); + uintptr_t ra = GETPC(); + + ensure_writable_pages(env, addr, mmu_idx, ra); - MEMOP_IDX(DF_WORD) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) #if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC()); + cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[0], ra); + cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[1], ra); + cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[2], ra); + cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[3], ra); #else - helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]); - cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]); - cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]); - cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]); -#else - cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]); - cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]); - cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]); - cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]); -#endif + cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[0], ra); + cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[1], ra); + cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[2], ra); + cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[3], ra); #endif } @@ -8584,14 +8438,10 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); int mmu_idx = cpu_mmu_index(env, false); + uintptr_t ra = GETPC(); - MEMOP_IDX(DF_DOUBLE) ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) - helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC()); - helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC()); -#else - cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]); - cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]); -#endif + + cpu_stq_data_ra(env, addr + (0 << DF_DOUBLE), pwd->d[0], ra); + cpu_stq_data_ra(env, addr + (1 << DF_DOUBLE), pwd->d[1], ra); } From patchwork Wed Oct 13 02:45:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515701 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6091131ime; Tue, 12 Oct 2021 20:08:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJybMk7XwNrqcOr37gadpQhP+3ExOcFe1ekVpBbYjG5bOTFHJv2Z2le5yzFCOMEc2CXI1DMY X-Received: by 2002:a25:1e8a:: with SMTP id e132mr31362758ybe.437.1634094491085; Tue, 12 Oct 2021 20:08:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634094491; cv=none; d=google.com; s=arc-20160816; b=yAqZvThNAyQSqWnX/dE+j28s8gCYlwM4tLEimIGWh4D2hrf/i1Y1CEpeGT0C2NS5Mj lN6275GX1+pUf1GVe5tDzt/doRDB0Uo8VluGyUN5DfzNuJyl7sG/AydfedtwrkXUm6lJ 9su3jpFJgv6CkVxzKUAnlDE8dItb7psbt/U0Ak9LWEEc936TswLo+KVcs7CPcwmQVP0S 2kHMYHTQtgY8gkSWQkT3n/F7aolpnLaZeTw0vZyIWKGb+C64s7+1xRyWGKPeUOSeLG6r 7ISSCZ3DIBZPrexMGxEah3eGblMM328MhAk8V+nrzC68t2dTdqconE+eKq9CktzYwZE+ hR/Q== ARC-Message-Signature: i=1; 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Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/tcg/msa_helper.c | 201 +++++++++++++---------------------- 1 file changed, 71 insertions(+), 130 deletions(-) -- 2.25.1 diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index a8880ce81c..e40c1b7057 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8218,47 +8218,31 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd, #define MEMOP_IDX(DF) #endif +#ifdef TARGET_WORDS_BIGENDIAN +static inline uint64_t bswap16x4(uint64_t x) +{ + uint64_t m = 0x00ff00ff00ff00ffull; + return ((x & m) << 8) | ((x >> 8) & m); +} + +static inline uint64_t bswap32x2(uint64_t x) +{ + return ror64(bswap64(x), 32); +} +#endif + void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); uintptr_t ra = GETPC(); + uint64_t d0, d1; -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->b[0] = cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra); - pwd->b[1] = cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra); - pwd->b[2] = cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra); - pwd->b[3] = cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra); - pwd->b[4] = cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra); - pwd->b[5] = cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra); - pwd->b[6] = cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra); - pwd->b[7] = cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra); - pwd->b[8] = cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra); - pwd->b[9] = cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra); - pwd->b[10] = cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra); - pwd->b[11] = cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra); - pwd->b[12] = cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra); - pwd->b[13] = cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra); - pwd->b[14] = cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra); - pwd->b[15] = cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra); -#else - pwd->b[0] = cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra); - pwd->b[1] = cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra); - pwd->b[2] = cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra); - pwd->b[3] = cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra); - pwd->b[4] = cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra); - pwd->b[5] = cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra); - pwd->b[6] = cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra); - pwd->b[7] = cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra); - pwd->b[8] = cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra); - pwd->b[9] = cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra); - pwd->b[10] = cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra); - pwd->b[11] = cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra); - pwd->b[12] = cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra); - pwd->b[13] = cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra); - pwd->b[14] = cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra); - pwd->b[15] = cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra); -#endif + /* Load 8 bytes at a time. Vector element ordering makes this LE. */ + d0 = cpu_ldq_le_data_ra(env, addr + 0, ra); + d1 = cpu_ldq_le_data_ra(env, addr + 8, ra); + pwd->d[0] = d0; + pwd->d[1] = d1; } void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, @@ -8266,26 +8250,20 @@ void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); uintptr_t ra = GETPC(); + uint64_t d0, d1; -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->h[0] = cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra); - pwd->h[1] = cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra); - pwd->h[2] = cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra); - pwd->h[3] = cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra); - pwd->h[4] = cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra); - pwd->h[5] = cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra); - pwd->h[6] = cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra); - pwd->h[7] = cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra); -#else - pwd->h[0] = cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra); - pwd->h[1] = cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra); - pwd->h[2] = cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra); - pwd->h[3] = cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra); - pwd->h[4] = cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra); - pwd->h[5] = cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra); - pwd->h[6] = cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra); - pwd->h[7] = cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra); + /* + * Load 8 bytes at a time. Use little-endian load, then for + * big-endian target, we must then swap the four halfwords. + */ + d0 = cpu_ldq_le_data_ra(env, addr + 0, ra); + d1 = cpu_ldq_le_data_ra(env, addr + 8, ra); +#ifdef TARGET_WORDS_BIGENDIAN + d0 = bswap16x4(d0); + d1 = bswap16x4(d1); #endif + pwd->d[0] = d0; + pwd->d[1] = d1; } void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, @@ -8293,18 +8271,20 @@ void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); uintptr_t ra = GETPC(); + uint64_t d0, d1; -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->w[0] = cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra); - pwd->w[1] = cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra); - pwd->w[2] = cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra); - pwd->w[3] = cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra); -#else - pwd->w[0] = cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra); - pwd->w[1] = cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra); - pwd->w[2] = cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra); - pwd->w[3] = cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra); + /* + * Load 8 bytes at a time. Use little-endian load, then for + * big-endian target, we must then bswap the two words. + */ + d0 = cpu_ldq_le_data_ra(env, addr + 0, ra); + d1 = cpu_ldq_le_data_ra(env, addr + 8, ra); +#ifdef TARGET_WORDS_BIGENDIAN + d0 = bswap32x2(d0); + d1 = bswap32x2(d1); #endif + pwd->d[0] = d0; + pwd->d[1] = d1; } void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, @@ -8312,9 +8292,12 @@ void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); uintptr_t ra = GETPC(); + uint64_t d0, d1; - pwd->d[0] = cpu_ldq_data_ra(env, addr + (0 << DF_DOUBLE), ra); - pwd->d[1] = cpu_ldq_data_ra(env, addr + (1 << DF_DOUBLE), ra); + d0 = cpu_ldq_data_ra(env, addr + 0, ra); + d1 = cpu_ldq_data_ra(env, addr + 8, ra); + pwd->d[0] = d0; + pwd->d[1] = d1; } #define MSA_PAGESPAN(x) \ @@ -8344,41 +8327,9 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, ensure_writable_pages(env, addr, mmu_idx, ra); -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[0], ra); - cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[1], ra); - cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[2], ra); - cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[3], ra); - cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[4], ra); - cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[5], ra); - cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[6], ra); - cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[7], ra); - cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[8], ra); - cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[9], ra); - cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[10], ra); - cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[11], ra); - cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[12], ra); - cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[13], ra); - cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[14], ra); - cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[15], ra); -#else - cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[0], ra); - cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[1], ra); - cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[2], ra); - cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[3], ra); - cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[4], ra); - cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[5], ra); - cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[6], ra); - cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[7], ra); - cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[8], ra); - cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[9], ra); - cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[10], ra); - cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[11], ra); - cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[12], ra); - cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[13], ra); - cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[14], ra); - cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[15], ra); -#endif + /* Store 8 bytes at a time. Vector element ordering makes this LE. */ + cpu_stq_le_data_ra(env, addr + 0, pwd->d[0], ra); + cpu_stq_le_data_ra(env, addr + 0, pwd->d[1], ra); } void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, @@ -8387,28 +8338,19 @@ void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); int mmu_idx = cpu_mmu_index(env, false); uintptr_t ra = GETPC(); + uint64_t d0, d1; ensure_writable_pages(env, addr, mmu_idx, ra); -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[0], ra); - cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[1], ra); - cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[2], ra); - cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[3], ra); - cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[4], ra); - cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[5], ra); - cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[6], ra); - cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[7], ra); -#else - cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[0], ra); - cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[1], ra); - cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[2], ra); - cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[3], ra); - cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[4], ra); - cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[5], ra); - cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[6], ra); - cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[7], ra); + /* Store 8 bytes at a time. See helper_msa_ld_h. */ + d0 = pwd->d[0]; + d1 = pwd->d[1]; +#ifdef TARGET_WORDS_BIGENDIAN + d0 = bswap16x4(d0); + d1 = bswap16x4(d1); #endif + cpu_stq_le_data_ra(env, addr + 0, d0, ra); + cpu_stq_le_data_ra(env, addr + 8, d1, ra); } void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, @@ -8417,20 +8359,19 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); int mmu_idx = cpu_mmu_index(env, false); uintptr_t ra = GETPC(); + uint64_t d0, d1; ensure_writable_pages(env, addr, mmu_idx, ra); -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[0], ra); - cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[1], ra); - cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[2], ra); - cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[3], ra); -#else - cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[0], ra); - cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[1], ra); - cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[2], ra); - cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[3], ra); + /* Store 8 bytes at a time. See helper_msa_ld_w. */ + d0 = pwd->d[0]; + d1 = pwd->d[1]; +#ifdef TARGET_WORDS_BIGENDIAN + d0 = bswap32x2(d0); + d1 = bswap32x2(d1); #endif + cpu_stq_le_data_ra(env, addr + 0, d0, ra); + cpu_stq_le_data_ra(env, addr + 8, d1, ra); } void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, @@ -8442,6 +8383,6 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, ensure_writable_pages(env, addr, mmu_idx, GETPC()); - cpu_stq_data_ra(env, addr + (0 << DF_DOUBLE), pwd->d[0], ra); - cpu_stq_data_ra(env, addr + (1 << DF_DOUBLE), pwd->d[1], ra); + cpu_stq_data_ra(env, addr + 0, pwd->d[0], ra); + cpu_stq_data_ra(env, addr + 8, pwd->d[1], ra); } From patchwork Wed Oct 13 02:45:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515697 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6088406ime; Tue, 12 Oct 2021 20:03:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyVy/Do18LJUL7v4ACyFlP4HmS0YaVuc4h8P9IA2YoG38D9NZKTMjO9hNWBUYfEBfJzfZhB X-Received: by 2002:ab0:7a53:: with SMTP id a19mr18963018uat.126.1634094238114; Tue, 12 Oct 2021 20:03:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634094238; cv=none; d=google.com; s=arc-20160816; b=quCi9dYw4c2IdHz6xnL7DOSDyMCemGXsWOVMztaFr6LPCVUgX8+EW31sV82/N0/A5q d3akhc+//BNuNyMeFHH2nomeJdQNr59WrSTZrPKnEuoxOovhnikVY9psAIKIx0ajJ3M0 LA7F1vO9nxteuar4dR6zkhxjMnb2sfRU/qZSBFnofnqayJAiCrpFyVtpCRXsdBMpinUk xe9nGue0hzNUY1LWwAZ9+OAE1wcyyG+TGjxTse2dJxOmNW7oMesz/N7misRfk8nkYgMn FaOvz0XZu1zpdpC7fJsNY7I8x2toHTWqFWYx8ww1PEqKozGTGIHs7BeA6Oj+rcQKoYjI /QRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ou9TZeIkVFlPgVg0RJ88Oh2ksyVGkR6IUoehchstShA=; b=vuJLudoRixUNvw26L8Ns1dKOdjlV7op9V8d06N2RI8oSlJdPQ1GWmOPpEZhrAj3UyG oUSn8XLA3lNy+pJoQ95xSYVmUuCS4FsJCcRYxjYUsZW1yDzOw3+4wcZkVyYkAjzptloa P86XCg4/IXI1CxjlGtfZo0IucG3kBWrhvL2epkc5dD9GBPfO2gF8Wa9j+nypHyOvAexx 8xEWZkAG6OzSGDEpMK5uvDm1/YGNlgqE2+CGe21qMM3OhM13O/Vwg9NWYGJXpwUpj9UU pBBMxD1eJKEBhIC22n3zKlU8oRJ15HeD8nqwQpGRQXlXh7tMnlyun70pLN0SmGkuqEme xp8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UGwFSpju; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p197si5447751vke.82.2021.10.12.20.03.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 20:03:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UGwFSpju; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39144 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUYf-0007re-7s for patch@linaro.org; Tue, 12 Oct 2021 23:03:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56998) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUHv-0004vD-91 for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:40 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:43698) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUHs-000541-TQ for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:38 -0400 Received: by mail-pg1-x535.google.com with SMTP id r2so870418pgl.10 for ; Tue, 12 Oct 2021 19:46:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ou9TZeIkVFlPgVg0RJ88Oh2ksyVGkR6IUoehchstShA=; b=UGwFSpjuT2sipPdArEKXbNaaG6OMAitioeoMThq23Z0N9iPMzlbsS8Ihu7Dqo5bg+V zVv4yOtOetSRDFEngWVou4TM2TrtjVxf6dGD3cyV45mnFQkujUnrBFflmNo2TaSgtjaj eKBjeauLhTyRFlBjZtSO49oPliPtQBEC6ImtAW9aDMisu/AbiAjLFdw4XR9wce1wbpu9 6em9BpU5E91KrXnthhMXuqE0zDoWNX01O72zi7AnKshRX7hGgPaTrhFoi8fs2eBhKUAC 8x+1QhlBfmIswENFPwvpQvSVnPmNGSjSLdRD8KE0vRu7s+0+qOcAN2xBkL3QXFLq1DMa 6R6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ou9TZeIkVFlPgVg0RJ88Oh2ksyVGkR6IUoehchstShA=; b=vQBYte3rMiN3TTCFU6IoPW2mvH0LXyPn+CJFT/ziWdsF+GW4x1jIBlF92uYrF56L/F OHltskXbHVWTn1G2kTvzVGLjuZ5Gsb9OuSFmBjYk98OuVDTcBL/sXqLaUJXxb/YxmTyt zZiqB/7QtbCeF/uophjhjfoeB27NCbcEwJgSvEK3QIMJWaRPuPV64AuhtcqoB3ZsTp9M 7KPdPaWxaOnqvUNaGozzRXKub0RK/7Fcw+rCQmmiqwdmjaWTRTPxchq9rGUlkwwrkKI+ ifr8OWuGoqi5hZ/a9IETgcmsuKpwxBhPVI2abutYX72XsfM51COXZOKwnAHN8wPHza0W 9bJQ== X-Gm-Message-State: AOAM530InOXQMC0ztwfD+XD3WF/z3ZSRrW15zkmw3GZOhdnJN2/HdNzx tODFOfzXFC/QDxPB56vPkb05cH2lLohiUA== X-Received: by 2002:aa7:8042:0:b0:44c:78ec:c9a9 with SMTP id y2-20020aa78042000000b0044c78ecc9a9mr34827330pfm.45.1634093195348; Tue, 12 Oct 2021 19:46:35 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 26/48] target/s390x: Use cpu_*_mmu instead of helper_*_mmu Date: Tue, 12 Oct 2021 19:45:45 -0700 Message-Id: <20211013024607.731881-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , David Hildenbrand Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The helper_*_mmu functions were the only thing available when this code was written. This could have been adjusted when we added cpu_*_mmuidx_ra, but now we can most easily use the newest set of interfaces. Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index f50c3f88a2..362a30d99e 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -241,13 +241,13 @@ static void do_access_memset(CPUS390XState *env, vaddr vaddr, char *haddr, * page. This is especially relevant to speed up TLB_NOTDIRTY. */ g_assert(size > 0); - helper_ret_stb_mmu(env, vaddr, byte, oi, ra); + cpu_stb_mmu(env, vaddr, byte, oi, ra); haddr = tlb_vaddr_to_host(env, vaddr, MMU_DATA_STORE, mmu_idx); if (likely(haddr)) { memset(haddr + 1, byte, size - 1); } else { for (i = 1; i < size; i++) { - helper_ret_stb_mmu(env, vaddr + i, byte, oi, ra); + cpu_stb_mmu(env, vaddr + i, byte, oi, ra); } } } @@ -283,7 +283,7 @@ static uint8_t do_access_get_byte(CPUS390XState *env, vaddr vaddr, char **haddr, * Do a single access and test if we can then get access to the * page. This is especially relevant to speed up TLB_NOTDIRTY. */ - byte = helper_ret_ldub_mmu(env, vaddr + offset, oi, ra); + byte = cpu_ldb_mmu(env, vaddr + offset, oi, ra); *haddr = tlb_vaddr_to_host(env, vaddr, MMU_DATA_LOAD, mmu_idx); return byte; #endif @@ -317,7 +317,7 @@ static void do_access_set_byte(CPUS390XState *env, vaddr vaddr, char **haddr, * Do a single access and test if we can then get access to the * page. This is especially relevant to speed up TLB_NOTDIRTY. */ - helper_ret_stb_mmu(env, vaddr + offset, byte, oi, ra); + cpu_stb_mmu(env, vaddr + offset, byte, oi, ra); *haddr = tlb_vaddr_to_host(env, vaddr, MMU_DATA_STORE, mmu_idx); #endif } From patchwork Wed Oct 13 02:45:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515700 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6090759ime; Tue, 12 Oct 2021 20:07:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz+SIoN9O+kqjwjY7GYjcYdI/hcHN32WqPDvclHAGisecqwOjzVO09KhQKKd6zCU2jHFKsX X-Received: by 2002:a67:d88c:: with SMTP id f12mr36687391vsj.33.1634094452203; Tue, 12 Oct 2021 20:07:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634094452; cv=none; d=google.com; s=arc-20160816; b=k8Afzw8aAQV0w+GWBc9Uwm+zG5PMY3RMtxBUctFyvpx2AbIW2S7TpEIPGaZ5u3kRnv oh5JnSfggdIGsDO1TGyAKc0zCsmIVOpC47mr1mSroKikC8J7lMLsmvhXLiBXge6yVhg5 EdiIj8ds+Cy3Wggf6V0/cybpMku6ok+YK/jfIGtzhZ0cpLQkhTafGy9pg9cRMSXwE/MU +Mc+93109hymtpSKZ3/Ckd9MhvqZRukl7B+vjlYqAsveiTe8QRecZBULbSbAD54Z2Rcu WJ3gWeA7pdfZenntAqQOvPVlynPJXJ7HumpnsW/pytKWQEK8dyQt2/ZV6aMW3upEKIL6 WDPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kL7S1VIhGWd0zPGO5R9RGYtF+Izlm+bII/GL/xjRg10=; b=VMLGNkWbQ/JRzVtD2POTntKYDtoHs3NcpwXhZ3q3snQzMP3cTRM6C+SmHb2Ae9uKCe S7RICUS4HWtpfKrvC2einjCQK4w1Z8HUeZ9w61lNzpoFkQr1MjQH6U0xXkU7pOHASqoL YpzGrHtds9vLzLxk9S9ZgF2iqwT14wxDIoHc5SGyyqcgTajm7eTOOq48NeZUHhXyUmhO 9IoXL5vitp/U4BLWhA/OHnWOXPlCVMU2B9EqFtSJ9YOHho8aaE0fELXO7QS8W6Rt05oj j73mg2yQKhbCqgV2X8AfMlZumXTjHbBRl7EhEPF4IyVUn/tOcCuJPlMsc38UfqU45zcf YGqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uA3ACiR7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t17si5876651vso.279.2021.10.12.20.07.32 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 20:07:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uA3ACiR7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45318 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUc6-0003y5-Ki for patch@linaro.org; Tue, 12 Oct 2021 23:07:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57050) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUHx-0004wl-O0 for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:42 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:34648) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUHu-000558-UF for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:41 -0400 Received: by mail-pj1-x1036.google.com with SMTP id ns7-20020a17090b250700b001a0937b87b7so2815261pjb.1 for ; Tue, 12 Oct 2021 19:46:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kL7S1VIhGWd0zPGO5R9RGYtF+Izlm+bII/GL/xjRg10=; b=uA3ACiR76wooQe3fpRNAtoEJQiE+V61ATB/0qVvdFDmwjRkbboFmZR5jCytt1hkfGT DMFNbB5w2LlbF5Aq/2+BExVCRvTbgQgLTidcmQ10MYwSNLByzKmAem2g/dAMe72x3kwq a5Cg/G4Cv3Q8/0MQVHsMzaQE3J/QRzcVU0fu8l89HoOr/X/rPe9srD/8XfdnWUE34ppp Iwzh9f9qkRVYTw2hFmw24EnHpE39kHNyv/i1qHD/vfWHXeTtzlJAKdDBcTaqvZzlIQ6S Q7nwgmkGSTBm57xTVyYSKOgMZAp6SIfEPy1R3K4M0igWyY83zlI0b0U6SRzMyzkO3Scr JYpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kL7S1VIhGWd0zPGO5R9RGYtF+Izlm+bII/GL/xjRg10=; b=ax8Kpg+jSj/k3OABwGFVyIh/4H38Ke+hmvbcPSfL9wQfhvbeqrvz4MkIyPrA6phsSB AkN0l6hKjiCzU5AHmqY1HnuJHMda5fEZBVV43bdHr0D7xnZxHRBRzCDdmL2eoxpGFpiO JitFNz+STjodd2U1D/3XLdevMVlTaDkGFls54wcL4gVLL8fFWYVMldZIO9kb+Y78s2yW vYpLstnucN0wMpIo7beo+U4ed63qBWIUSqP1yMsitkdyy30++seYcyUWALnKx5DGzmoq a8bLX+7z4xwNgctuXm5u/gBXepVjg8SerxPcgpbMH5UjYn1o6tJe2u1LDCQiu7n0PYIQ eWvg== X-Gm-Message-State: AOAM532c8DmwlXkeAh/qd5ld6GFyhmyAeCtCItxMPDekdwLdwTbEiyYO b6QUntRqVL9pefXgyo2uxOT1YAuwaqm4zg== X-Received: by 2002:a17:902:780f:b0:13a:3919:e365 with SMTP id p15-20020a170902780f00b0013a3919e365mr33354705pll.63.1634093196404; Tue, 12 Oct 2021 19:46:36 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 27/48] target/sparc: Use cpu_*_mmu instead of helper_*_mmu Date: Tue, 12 Oct 2021 19:45:46 -0700 Message-Id: <20211013024607.731881-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The helper_*_mmu functions were the only thing available when this code was written. This could have been adjusted when we added cpu_*_mmuidx_ra, but now we can most easily use the newest set of interfaces. Reviewed-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 299fc386ea..a3e1cf9b6e 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1328,27 +1328,27 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, oi = make_memop_idx(memop, idx); switch (size) { case 1: - ret = helper_ret_ldub_mmu(env, addr, oi, GETPC()); + ret = cpu_ldb_mmu(env, addr, oi, GETPC()); break; case 2: if (asi & 8) { - ret = helper_le_lduw_mmu(env, addr, oi, GETPC()); + ret = cpu_ldw_le_mmu(env, addr, oi, GETPC()); } else { - ret = helper_be_lduw_mmu(env, addr, oi, GETPC()); + ret = cpu_ldw_be_mmu(env, addr, oi, GETPC()); } break; case 4: if (asi & 8) { - ret = helper_le_ldul_mmu(env, addr, oi, GETPC()); + ret = cpu_ldl_le_mmu(env, addr, oi, GETPC()); } else { - ret = helper_be_ldul_mmu(env, addr, oi, GETPC()); + ret = cpu_ldl_be_mmu(env, addr, oi, GETPC()); } break; case 8: if (asi & 8) { - ret = helper_le_ldq_mmu(env, addr, oi, GETPC()); + ret = cpu_ldq_le_mmu(env, addr, oi, GETPC()); } else { - ret = helper_be_ldq_mmu(env, addr, oi, GETPC()); + ret = cpu_ldq_be_mmu(env, addr, oi, GETPC()); } break; default: From patchwork Wed Oct 13 02:45:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515696 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6087915ime; Tue, 12 Oct 2021 20:03:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw/zihaC97ySNaE05q6yja5edl8ybKrxqUcabJSwbF6bdbQVQJAAgEyek2ha8V26t/URF9w X-Received: by 2002:a05:6102:2383:: with SMTP id v3mr35297027vsr.52.1634094186619; Tue, 12 Oct 2021 20:03:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634094186; cv=none; d=google.com; s=arc-20160816; b=Wbh1oQuGTUtGZwe+1wtSwOAACn3q5K6BUTcrxgNFCUvMndfUZmmmecW2Wn6zfLX5gO ymQ7/Z5oFaM6MLAtCyfKPnPePl/yVRItD3HkGAmM46yrT0idE8zPnbefnikjmswMCY5g bUbMNG7PCTO2sPcFVYrC/4QQzpioqUQ+vhUhEktIDXD4KD1FYQ5Dlzd9Aj00AELDczM9 ts8j+mMRlkST8UMxeCXKCXGR4YEt7xXChC8/5x3spCc2b/iJnWl4c0mVMo7PTJneAvuE RlikAXkjR1E0oTAwluVaXvsjjNrxaBL+Wh0oqEEnHCyUVUcSt0BcAbcIOsz4gVUa82HJ FNqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=56pglvy67AYwWdSDilcVWIN0xfuG/5o2eEFwbxuVXXQ=; b=nUEzmYHYIUz5dRnlVp4Ys1s73Eb9nol2GqGBWER7Hv35Y323xWJ/H9kwK6y0XYqrWD +/x9Nle/gAn/zp5frxfqEiIevcHufAK2c2dqa1XJDhgDMp59NNE5whLl1ap+FdXizJav dGAaFq4z0UkxZGJFmWmqSZ99o8CkdVswsLcxXV9LxndTN4pzQHtj/EzW4TDmZ0KbEk8i lmF3XUv5EqeIKvZjNzKIhRfSwlGTxejtRoEm0AlPhJp9TUIRphDZ43RYYiOhHNd9zaji AIBlAF9WlgMKpxOlfByk/kwhOsSu6NWDnMIP700IJ+twASpOF7RCfONrdudKzY9PsQdU hrvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Tzg7l2V0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j12si5177779ual.17.2021.10.12.20.03.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 20:03:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Tzg7l2V0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36870 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUXp-0006Az-GN for patch@linaro.org; Tue, 12 Oct 2021 23:03:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57022) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUHw-0004vK-1O for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:40 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:52123) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUHu-00055N-Cf for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:39 -0400 Received: by mail-pj1-x1031.google.com with SMTP id kk10so1083212pjb.1 for ; Tue, 12 Oct 2021 19:46:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=56pglvy67AYwWdSDilcVWIN0xfuG/5o2eEFwbxuVXXQ=; b=Tzg7l2V0zOMh0VFRZG6JHz4lFFxNmlRCDhtau/5pGV7HJJ40gkKczSxqB/KeUyRFXR 9Ac9TiOGKkv5tCYLYgO0MgDaaM9C0z7i49/mzNAwHQCug5UaRpDuIglh8IatIqHiZiYO +ZwSw/LQhD6GYOLuUsNhhsxCGheg4DFhuwVMcy6U3E1NzgYJc2gmKBQg2P7K3Xr2r7yT BmNehhJhdo3QYpysVr13wH21IrlS/ZFrLwOiWK0FJHovzCec2h49G9GyAtCMbVdnpe+6 45ZkWq9X4ZtxR7Gp1JPJws5FNPUTNLpiT7kMfQb3wLTwyk6z2jqdI9Q83DAg2oNVR03V 66Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=56pglvy67AYwWdSDilcVWIN0xfuG/5o2eEFwbxuVXXQ=; b=pd08Qr88kIwpkJuf/RsutQrfGXzPdj2aRoGS8+Vy1lECQeiTclGtHQvJq3PPkluWzU ICSkOeBHrL4/JrH2pJYwut9Q+lUQOWJZf5Glsx/GZmY9KmiBZ8xfPEZDEL9qE+JYlV3y fceeWZQUP2AcPzNk0zQWcTbCaHzKXE20srk6hfmgrLMX27whv6cj7iMfxvNeipfFfcXi igLZ5Teyh81FjoW7ipGwFLZpQzzQ86BrWYm8bycj1ZWWaw4w/UIhaGivckmwyly1iB2s aqSPsNevZkgmpLmHvjSjeMK9hp592rxeKDp6g4yHrZjaBtiRDr0IFLtYQENBjvtNqDwY YK+w== X-Gm-Message-State: AOAM533Nhs6otzbzSF98uAGq6elPk9FF/JOOvMwXC8mcYDQPRRjPnQUy RxQ7eUWVa1Ng8IBdWqykNN2YqDSQtKA+uA== X-Received: by 2002:a17:90b:350c:: with SMTP id ls12mr10459675pjb.36.1634093197096; Tue, 12 Oct 2021 19:46:37 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 28/48] target/arm: Use cpu_*_mmu instead of helper_*_mmu Date: Tue, 12 Oct 2021 19:45:47 -0700 Message-Id: <20211013024607.731881-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The helper_*_mmu functions were the only thing available when this code was written. This could have been adjusted when we added cpu_*_mmuidx_ra, but now we can most easily use the newest set of interfaces. Cc: qemu-arm@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 52 +++++++---------------------------------- target/arm/m_helper.c | 6 ++--- 2 files changed, 11 insertions(+), 47 deletions(-) -- 2.25.1 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index b110c57956..5ae2ecb0f3 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -512,37 +512,19 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, uintptr_t ra = GETPC(); uint64_t o0, o1; bool success; - -#ifdef CONFIG_USER_ONLY - /* ??? Enforce alignment. */ - uint64_t *haddr = g2h(env_cpu(env), addr); - - set_helper_retaddr(ra); - o0 = ldq_le_p(haddr + 0); - o1 = ldq_le_p(haddr + 1); - oldv = int128_make128(o0, o1); - - success = int128_eq(oldv, cmpv); - if (success) { - stq_le_p(haddr + 0, int128_getlo(newv)); - stq_le_p(haddr + 1, int128_gethi(newv)); - } - clear_helper_retaddr(); -#else int mem_idx = cpu_mmu_index(env, false); MemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); MemOpIdx oi1 = make_memop_idx(MO_LEQ, mem_idx); - o0 = helper_le_ldq_mmu(env, addr + 0, oi0, ra); - o1 = helper_le_ldq_mmu(env, addr + 8, oi1, ra); + o0 = cpu_ldq_le_mmu(env, addr + 0, oi0, ra); + o1 = cpu_ldq_le_mmu(env, addr + 8, oi1, ra); oldv = int128_make128(o0, o1); success = int128_eq(oldv, cmpv); if (success) { - helper_le_stq_mmu(env, addr + 0, int128_getlo(newv), oi1, ra); - helper_le_stq_mmu(env, addr + 8, int128_gethi(newv), oi1, ra); + cpu_stq_le_mmu(env, addr + 0, int128_getlo(newv), oi1, ra); + cpu_stq_le_mmu(env, addr + 8, int128_gethi(newv), oi1, ra); } -#endif return !success; } @@ -582,37 +564,19 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, uintptr_t ra = GETPC(); uint64_t o0, o1; bool success; - -#ifdef CONFIG_USER_ONLY - /* ??? Enforce alignment. */ - uint64_t *haddr = g2h(env_cpu(env), addr); - - set_helper_retaddr(ra); - o1 = ldq_be_p(haddr + 0); - o0 = ldq_be_p(haddr + 1); - oldv = int128_make128(o0, o1); - - success = int128_eq(oldv, cmpv); - if (success) { - stq_be_p(haddr + 0, int128_gethi(newv)); - stq_be_p(haddr + 1, int128_getlo(newv)); - } - clear_helper_retaddr(); -#else int mem_idx = cpu_mmu_index(env, false); MemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); MemOpIdx oi1 = make_memop_idx(MO_BEQ, mem_idx); - o1 = helper_be_ldq_mmu(env, addr + 0, oi0, ra); - o0 = helper_be_ldq_mmu(env, addr + 8, oi1, ra); + o1 = cpu_ldq_be_mmu(env, addr + 0, oi0, ra); + o0 = cpu_ldq_be_mmu(env, addr + 8, oi1, ra); oldv = int128_make128(o0, o1); success = int128_eq(oldv, cmpv); if (success) { - helper_be_stq_mmu(env, addr + 0, int128_gethi(newv), oi1, ra); - helper_be_stq_mmu(env, addr + 8, int128_getlo(newv), oi1, ra); + cpu_stq_be_mmu(env, addr + 0, int128_gethi(newv), oi1, ra); + cpu_stq_be_mmu(env, addr + 8, int128_getlo(newv), oi1, ra); } -#endif return !success; } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 62aa12c9d8..2c9922dc29 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -1947,9 +1947,9 @@ static bool do_v7m_function_return(ARMCPU *cpu) * do them as secure, so work out what MMU index that is. */ mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true); - oi = make_memop_idx(MO_LE, arm_to_core_mmu_idx(mmu_idx)); - newpc = helper_le_ldul_mmu(env, frameptr, oi, 0); - newpsr = helper_le_ldul_mmu(env, frameptr + 4, oi, 0); + oi = make_memop_idx(MO_LEUL, arm_to_core_mmu_idx(mmu_idx)); + newpc = cpu_ldl_le_mmu(env, frameptr, oi, 0); + newpsr = cpu_ldl_le_mmu(env, frameptr + 4, oi, 0); /* Consistency checks on new IPSR */ newpsr_exc = newpsr & XPSR_EXCP; From patchwork Wed Oct 13 02:45:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515702 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6091936ime; Tue, 12 Oct 2021 20:09:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyDydk8rf7AAGMb+ThDdwBzyVPrZb9gYFG+hUeWwHZSFbPBlcq+AOV15yIayOnmyxVl3S8w X-Received: by 2002:a25:1b8a:: with SMTP id b132mr31294111ybb.535.1634094571145; Tue, 12 Oct 2021 20:09:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634094571; cv=none; d=google.com; s=arc-20160816; b=Yy9bp56EeAhjYb7Sqb/3Db14H9XD40tkedltrNGiOE8+4f5Nu9HNUjahDwLBUn8NWq NmC4m4UA3qQfnhy7NksvMydtCZ30S0ckoZBegrEimibRbm/+PmkzOghIOiN7hXvIGdfs bG+nwME10BarhjBe5dD77Bze9f9bss7YQabHvWgfl0/waGKSW5hFGKx7gKlJli73j8H+ zYhpgsK+bTj5xD/yJAHprH6TqHO1ue5rWcwRQyTCAYQucFqyPKhxPSPl9W0CNMya95Z4 8QNdudHHnkpe8XUuCXzqed+VDeWSYyr0ue/ORWw7HS2ToRLMJwmJR/TYU8WFu3vaVHrD IWMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=INby5Ty0QNa/n9lUmBDAx1irZEcQEUrI7v6tJBuf6ho=; b=SQRhDRfYramYYSiWjxvSoyXCa5TDh2Hcy5yotGvnzLPUromlcOhfD+zEWaXhrFMkpN BOOgU44jzgUo3NkR7jY7zmA/2BcvqC+gGvfBE4OKVeaeUMw0CCXDpXSZZr8UiC2h97h4 0oPgCuMab6eowa+5otc8CbnQd/8/Xoo3pV2+ab67dZG76Y63PTkGC46QMz1RqkW3nV35 1Dcep64IVXwZXs2kGR24QP385T4fUmGniItxqFVs3MMLXpM/TeeS2j9doOWCNkSynZFX ppxGaUc+YmGlgEW+P8aABZYXojtShNUpWGuObtXQKktMKwriTxKBwmmt0++6GGaUNy/a q9jA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MCEQNpep; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Hide these declarations from code that should not use them. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 74 ++++++++++++++++++++++++++++++++++++++++++ include/tcg/tcg.h | 71 ---------------------------------------- accel/tcg/cputlb.c | 1 + tcg/tcg.c | 1 + tcg/tci.c | 1 + 5 files changed, 77 insertions(+), 71 deletions(-) create mode 100644 include/tcg/tcg-ldst.h -- 2.25.1 diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h new file mode 100644 index 0000000000..8c86365611 --- /dev/null +++ b/include/tcg/tcg-ldst.h @@ -0,0 +1,74 @@ +/* + * Memory helpers that will be used by TCG generated code. + * + * Copyright (c) 2008 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef TCG_LDST_H +#define TCG_LDST_H 1 + +#ifdef CONFIG_SOFTMMU + +/* Value zero-extended to tcg register size. */ +tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); + +/* Value sign-extended to tcg register size. */ +tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); + +void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr); + +#endif /* CONFIG_SOFTMMU */ +#endif /* TCG_LDST_H */ diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 83e38487cf..7069a401f1 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1240,77 +1240,6 @@ uint64_t dup_const(unsigned vece, uint64_t c); : (target_long)dup_const(VECE, C)) #endif -/* - * Memory helpers that will be used by TCG generated code. - */ -#ifdef CONFIG_SOFTMMU -/* Value zero-extended to tcg register size. */ -tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); - -/* Value sign-extended to tcg register size. */ -tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); - -void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - MemOpIdx oi, uintptr_t retaddr); - -/* Temporary aliases until backends are converted. */ -#ifdef TARGET_WORDS_BIGENDIAN -# define helper_ret_ldsw_mmu helper_be_ldsw_mmu -# define helper_ret_lduw_mmu helper_be_lduw_mmu -# define helper_ret_ldsl_mmu helper_be_ldsl_mmu -# define helper_ret_ldul_mmu helper_be_ldul_mmu -# define helper_ret_ldl_mmu helper_be_ldul_mmu -# define helper_ret_ldq_mmu helper_be_ldq_mmu -# define helper_ret_stw_mmu helper_be_stw_mmu -# define helper_ret_stl_mmu helper_be_stl_mmu -# define helper_ret_stq_mmu helper_be_stq_mmu -#else -# define helper_ret_ldsw_mmu helper_le_ldsw_mmu -# define helper_ret_lduw_mmu helper_le_lduw_mmu -# define helper_ret_ldsl_mmu helper_le_ldsl_mmu -# define helper_ret_ldul_mmu helper_le_ldul_mmu -# define helper_ret_ldl_mmu helper_le_ldul_mmu -# define helper_ret_ldq_mmu helper_le_ldq_mmu -# define helper_ret_stw_mmu helper_le_stw_mmu -# define helper_ret_stl_mmu helper_le_stl_mmu -# define helper_ret_stq_mmu helper_le_stq_mmu -#endif -#endif /* CONFIG_SOFTMMU */ - #ifdef CONFIG_DEBUG_TCG void tcg_assert_listed_vecop(TCGOpcode); #else diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b350cafa3d..b69a953447 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -39,6 +39,7 @@ #ifdef CONFIG_PLUGIN #include "qemu/plugin-memory.h" #endif +#include "tcg/tcg-ldst.h" /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ diff --git a/tcg/tcg.c b/tcg/tcg.c index 658be0c6b6..024a22cf39 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -58,6 +58,7 @@ #include "elf.h" #include "exec/log.h" +#include "tcg/tcg-ldst.h" #include "tcg-internal.h" #ifdef CONFIG_TCG_INTERPRETER diff --git a/tcg/tci.c b/tcg/tci.c index 5c08dc0a9a..e76087ccac 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -22,6 +22,7 @@ #include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */ #include "exec/cpu_ldst.h" #include "tcg/tcg-op.h" +#include "tcg/tcg-ldst.h" #include "qemu/compiler.h" #include From patchwork Wed Oct 13 02:45:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515691 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6085702ime; 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[209.51.188.17]) by mx.google.com with ESMTPS id g3si9959997jat.38.2021.10.12.19.59.34 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 19:59:34 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TyH11BbE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56210 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUUQ-000095-31 for patch@linaro.org; Tue, 12 Oct 2021 22:59:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57058) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUHy-0004wo-D8 for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:42 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:46723) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUHw-00056N-Qw for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:42 -0400 Received: by mail-pf1-x431.google.com with SMTP id t15so1120425pfl.13 for ; Tue, 12 Oct 2021 19:46:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jfz53S3QlKXNPBsRIkUXBiTrLPBdQUAc4SLrCyr0OTo=; b=TyH11BbEZlhZZ9CwLFfuKqI5Slkl3q8NgO2ONI2unalRU205XAqYLYiggtzAHObMah Yh2m2uiMIaOTnLzcAY1dkt+VN+AtrwVRE2EIHmMWIQfkqVD+GmgnEWdDN7v0+hYS2Obm vwjQvMgdanDVN93HsVSLX3ZnsKcqsWVuLnRObWWs1N2D3nYm4etBfJMvM0lV2pWUURoB 3zifmzISTh5CxScwTJXj4vyBCCq9PBuYhds1LdAdZjAKWOeYtwRa8/BkHfB9kr2yIHhi icW3lnlsaL9cF2W2Aai5aK+uk1/vvPOSHiV9PrL1G4skbHlG8Lm/Weuj34duCD7jmonF aECg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jfz53S3QlKXNPBsRIkUXBiTrLPBdQUAc4SLrCyr0OTo=; b=Baj7+qWkr/pbMRJkPOqxcjftlXkwiMeE6OFdkJ3nC21BzVMjCNzb2rJBOVnoRkBwDv Ar/vpCiPn4DLOWZcUUrCxiwENZy2Tw1Bgb/dIPr35NCpl54Ttq+JXB6bbXi+bXo+75re plsfQbRKDeEwt77hzQOdUwYMY4aBSXoRxOd9x6BePKxcwz3wDSe+EBI85/o3Y1QLPcjh Uqew9mRmVRi6V3F8x+lo1J6AWtrm+ImOZURYHbsYty2tazti05+4n9OL9Gma4hhG7xmg Zi65YIAsc+kjd48287V7yj7dW+DdVGn2c/Of6PzPjutrww0qgwNJd1TT4WZaGxJKFRRc P/3g== X-Gm-Message-State: AOAM530TA9QOFkyDcwPRpwDrFnxRbch60FkB61VBWENT5BS1ehwMp7aj rJ8pxqHTT/W+tmUUnht/OGE9oxKOBfM= X-Received: by 2002:a63:b214:: with SMTP id x20mr25777738pge.460.1634093198930; Tue, 12 Oct 2021 19:46:38 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 30/48] tcg: Add helper_unaligned_{ld, st} for user-only sigbus Date: Tue, 12 Oct 2021 19:45:49 -0700 Message-Id: <20211013024607.731881-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" To be called from tcg generated code on hosts that support unaligned accesses natively, in response to an access that is supposed to be aligned. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 5 +++++ accel/tcg/user-exec.c | 11 +++++++++++ 2 files changed, 16 insertions(+) -- 2.25.1 diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index 8c86365611..bf40942de4 100644 --- a/include/tcg/tcg-ldst.h +++ b/include/tcg/tcg-ldst.h @@ -70,5 +70,10 @@ void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr); +#else + +void QEMU_NORETURN helper_unaligned_ld(CPUArchState *env, target_ulong addr); +void QEMU_NORETURN helper_unaligned_st(CPUArchState *env, target_ulong addr); + #endif /* CONFIG_SOFTMMU */ #endif /* TCG_LDST_H */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 7d50dd54f6..0473ead5ab 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -27,6 +27,7 @@ #include "exec/helper-proto.h" #include "qemu/atomic128.h" #include "trace/trace-root.h" +#include "tcg/tcg-ldst.h" #include "internal.h" __thread uintptr_t helper_retaddr; @@ -217,6 +218,16 @@ static void validate_memop(MemOpIdx oi, MemOp expected) #endif } +void helper_unaligned_ld(CPUArchState *env, target_ulong addr) +{ + cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_LOAD, GETPC()); +} + +void helper_unaligned_st(CPUArchState *env, target_ulong addr) +{ + cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_STORE, GETPC()); +} + static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t ra, MMUAccessType type) { From patchwork Wed Oct 13 02:45:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515705 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6093346ime; Tue, 12 Oct 2021 20:11:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxfNY+5zCE95mBQn+134JZK6Qkz07eiZz/U2G0WOsl0lmNrhCfIZ0MI2LePxaJ6Hogh8FpF X-Received: by 2002:a05:6902:124a:: with SMTP id t10mr33347831ybu.73.1634094710173; Tue, 12 Oct 2021 20:11:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634094710; cv=none; d=google.com; s=arc-20160816; b=ZrpU1LwVN4hsQb6ghtfgdjaigMvXhdmbd0vbPPafPwx12LP/+xdyKgA7geWYFx6lwN 04R/Ymc49Ou2XejiRtZTaUzTTfQz8DNiZLMnCpTzgVZr+yIlVUVQzJGLQKceIegUUDQj TOIKjjhfLDSo573G2dht2Kn66ukcgpFyeRSk1GDOiw6gvmLpirwmB1lSJzum+BXJErJU 8kLrqMfmKK9uPrB1+yK/r/2NnL0abNtRdDyhIHsMb4ZIBDOjC5d6u/daXGtrfQC1IoE5 /JSr16lCKBpdSJOn4cFvQj1lfgbNW+Ph1xhWkxgVmTWPIOriWFlzclR/8BDjyjEFgSkd +7uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mnqEEgywou2/cA2oB9Is2HfT4xL6ufMEEmIOEI3fkHA=; b=R+/8KrF9GMIyad4vWH4Z2Ulytjxf0rpSiP4/bmNmorpietF0LQa/alkt7nxXk/qdZ6 +K9c8N/TAGJvp4CWUhqIOOfnbBmggIjkqYvQMt9XZmifGDlUDD+VWURTJUarytAfdM5u PycJRsi5rWSzF5j9+txHCF9dmeBZWYxpolY7Yz4TNZ7tmAp+PxkIWt08YNGIaF6ou3+w V7Pe53M1iK+IH7dcZI5950mCH92+EpKfXhOm2M2DUKikxIgYJs7y3gJZ9iQ8AcEM/T7l foIBxgisoMvSPaOTs7cyA3CBqqyeKaNDa4Dn5ljESLAreerl4NeCCxg8XJEHA3oAVcNG a8yg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QJrQCuSU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 125si13178385ybv.400.2021.10.12.20.11.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 20:11:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QJrQCuSU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56998 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUgG-0003aP-FT for patch@linaro.org; Tue, 12 Oct 2021 23:11:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57100) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUI1-0004zq-94 for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:46 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:44990) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUHx-000575-UR for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:44 -0400 Received: by mail-pf1-x42b.google.com with SMTP id w6so1131719pfd.11 for ; Tue, 12 Oct 2021 19:46:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=mnqEEgywou2/cA2oB9Is2HfT4xL6ufMEEmIOEI3fkHA=; b=QJrQCuSUJls/TFlB6Zzg+hASNJ/cQXtSAUfmUXe0I0YhbSe6RhJ7Wiz9noOFtM2Cs6 X56GCgKEFtQLoNV1JhGed3/H7ToAvmnmSQNUJlDL+wGRGqzIirmSf9v9lpN34MuqU+3J DZk+sz64FI8wK6LbyjZSpqJVSTZK4jV7wl1DKaWli9CSmJ8KkvewH0YHWJayaANtd4Qb SoyzDYmVNIDX6DkR08xLuEtqKgOdQ824QX7Z5bC52xssYACK0Kk+Ot4T3oo6cbkBQnzC xLbz9GsZviogXMF8VfNyo475jfD0cs1PFll2XphfL+XgVAOD35pkku4DFZVGKf9SZOY+ v4rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mnqEEgywou2/cA2oB9Is2HfT4xL6ufMEEmIOEI3fkHA=; b=Wa/0HpYAvdQSba/00wbI92w+GgQywVUrlYO5jZlSCWoBMyXCO3INgJ9x9aqyb3fLQJ TIsRNAU4c6KVGhdF9E7n/rM83bNQ/xRFa+FxzIxnsfTeOAPMUi1kjpfon2CWJlW5m0WQ 34CgbIyD8Pmgb1HQi45/kWkfJD64w6z/lGXXLRWYRLU4K1UfQON0hdvN1k20NdztZjQ0 9Mm0VhqzYpzATbmmts36RwVIWcOkGHhmiQRyv0PUUBtxQP5/vsn0+jMUtcYblLVb1H8F e5NzhgzNP6tzSNPoU+kzU4ZqigUyuRUvuOVbjtxUsOhaC3wiTu5KHEJHVecmqKRK/niJ 98AA== X-Gm-Message-State: AOAM533NH49K2PEkrKxwdAyQeWX8Ae73p2LsG4jN6S9fYbCqRbIUA4T2 tqea+9JvWIJCK2SiBpyNEuVpGNutx4E= X-Received: by 2002:a62:2982:0:b0:44c:f2a3:ec62 with SMTP id p124-20020a622982000000b0044cf2a3ec62mr22794351pfp.23.1634093200342; Tue, 12 Oct 2021 19:46:40 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 31/48] linux-user: Split out do_prctl and subroutines Date: Tue, 12 Oct 2021 19:45:50 -0700 Message-Id: <20211013024607.731881-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since the prctl constants are supposed to be generic, supply any that are not provided by the host. Split out subroutines for PR_GET_FP_MODE, PR_SET_FP_MODE, PR_GET_VL, PR_SET_VL, PR_RESET_KEYS, PR_SET_TAGGED_ADDR_CTRL, PR_GET_TAGGED_ADDR_CTRL. Return EINVAL for guests that do not support these options rather than pass them on to the host. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 160 ++++++++++ linux-user/aarch64/target_syscall.h | 23 -- linux-user/alpha/target_prctl.h | 1 + linux-user/arm/target_prctl.h | 1 + linux-user/cris/target_prctl.h | 1 + linux-user/hexagon/target_prctl.h | 1 + linux-user/hppa/target_prctl.h | 1 + linux-user/i386/target_prctl.h | 1 + linux-user/m68k/target_prctl.h | 1 + linux-user/microblaze/target_prctl.h | 1 + linux-user/mips/target_prctl.h | 88 ++++++ linux-user/mips/target_syscall.h | 6 - linux-user/mips64/target_prctl.h | 1 + linux-user/mips64/target_syscall.h | 6 - linux-user/nios2/target_prctl.h | 1 + linux-user/openrisc/target_prctl.h | 1 + linux-user/ppc/target_prctl.h | 1 + linux-user/riscv/target_prctl.h | 1 + linux-user/s390x/target_prctl.h | 1 + linux-user/sh4/target_prctl.h | 1 + linux-user/sparc/target_prctl.h | 1 + linux-user/x86_64/target_prctl.h | 1 + linux-user/xtensa/target_prctl.h | 1 + linux-user/syscall.c | 433 +++++++++------------------ 24 files changed, 414 insertions(+), 320 deletions(-) create mode 100644 linux-user/aarch64/target_prctl.h create mode 100644 linux-user/alpha/target_prctl.h create mode 100644 linux-user/arm/target_prctl.h create mode 100644 linux-user/cris/target_prctl.h create mode 100644 linux-user/hexagon/target_prctl.h create mode 100644 linux-user/hppa/target_prctl.h create mode 100644 linux-user/i386/target_prctl.h create mode 100644 linux-user/m68k/target_prctl.h create mode 100644 linux-user/microblaze/target_prctl.h create mode 100644 linux-user/mips/target_prctl.h create mode 100644 linux-user/mips64/target_prctl.h create mode 100644 linux-user/nios2/target_prctl.h create mode 100644 linux-user/openrisc/target_prctl.h create mode 100644 linux-user/ppc/target_prctl.h create mode 100644 linux-user/riscv/target_prctl.h create mode 100644 linux-user/s390x/target_prctl.h create mode 100644 linux-user/sh4/target_prctl.h create mode 100644 linux-user/sparc/target_prctl.h create mode 100644 linux-user/x86_64/target_prctl.h create mode 100644 linux-user/xtensa/target_prctl.h -- 2.25.1 diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h new file mode 100644 index 0000000000..3f5a5d3933 --- /dev/null +++ b/linux-user/aarch64/target_prctl.h @@ -0,0 +1,160 @@ +/* + * AArch64 specific prctl functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef AARCH64_TARGET_PRCTL_H +#define AARCH64_TARGET_PRCTL_H + +static abi_long do_prctl_get_vl(CPUArchState *env) +{ + ARMCPU *cpu = env_archcpu(env); + if (cpu_isar_feature(aa64_sve, cpu)) { + return ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_get_vl do_prctl_get_vl + +static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2) +{ + /* + * We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT. + * Note the kernel definition of sve_vl_valid allows for VQ=512, + * i.e. VL=8192, even though the current architectural maximum is VQ=16. + */ + if (cpu_isar_feature(aa64_sve, env_archcpu(env)) + && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { + ARMCPU *cpu = env_archcpu(env); + uint32_t vq, old_vq; + + old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; + vq = MAX(arg2 / 16, 1); + vq = MIN(vq, cpu->sve_max_vq); + + if (vq < old_vq) { + aarch64_sve_narrow_vq(env, vq); + } + env->vfp.zcr_el[1] = vq - 1; + arm_rebuild_hflags(env); + return vq * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_set_vl do_prctl_set_vl + +static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) +{ + ARMCPU *cpu = env_archcpu(env); + + if (cpu_isar_feature(aa64_pauth, cpu)) { + int all = (PR_PAC_APIAKEY | PR_PAC_APIBKEY | + PR_PAC_APDAKEY | PR_PAC_APDBKEY | PR_PAC_APGAKEY); + int ret = 0; + Error *err = NULL; + + if (arg2 == 0) { + arg2 = all; + } else if (arg2 & ~all) { + return -TARGET_EINVAL; + } + if (arg2 & PR_PAC_APIAKEY) { + ret |= qemu_guest_getrandom(&env->keys.apia, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APIBKEY) { + ret |= qemu_guest_getrandom(&env->keys.apib, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APDAKEY) { + ret |= qemu_guest_getrandom(&env->keys.apda, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APDBKEY) { + ret |= qemu_guest_getrandom(&env->keys.apdb, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APGAKEY) { + ret |= qemu_guest_getrandom(&env->keys.apga, + sizeof(ARMPACKey), &err); + } + if (ret != 0) { + /* + * Some unknown failure in the crypto. The best + * we can do is log it and fail the syscall. + * The real syscall cannot fail this way. + */ + qemu_log_mask(LOG_UNIMP, "PR_PAC_RESET_KEYS: Crypto failure: %s", + error_get_pretty(err)); + error_free(err); + return -TARGET_EIO; + } + return 0; + } + return -TARGET_EINVAL; +} +#define do_prctl_reset_keys do_prctl_reset_keys + +static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2) +{ + abi_ulong valid_mask = PR_TAGGED_ADDR_ENABLE; + ARMCPU *cpu = env_archcpu(env); + + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |= PR_MTE_TCF_MASK; + valid_mask |= PR_MTE_TAG_MASK; + } + + if (arg2 & ~valid_mask) { + return -TARGET_EINVAL; + } + env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE; + + if (cpu_isar_feature(aa64_mte, cpu)) { + switch (arg2 & PR_MTE_TCF_MASK) { + case PR_MTE_TCF_NONE: + case PR_MTE_TCF_SYNC: + case PR_MTE_TCF_ASYNC: + break; + default: + return -EINVAL; + } + + /* + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. + * Note that the syscall values are consistent with hw. + */ + env->cp15.sctlr_el[1] = + deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT); + + /* + * Write PR_MTE_TAG to GCR_EL1[Exclude]. + * Note that the syscall uses an include mask, + * and hardware uses an exclude mask -- invert. + */ + env->cp15.gcr_el1 = + deposit64(env->cp15.gcr_el1, 0, 16, ~arg2 >> PR_MTE_TAG_SHIFT); + arm_rebuild_hflags(env); + } + return 0; +} +#define do_prctl_set_tagged_addr_ctrl do_prctl_set_tagged_addr_ctrl + +static abi_long do_prctl_get_tagged_addr_ctrl(CPUArchState *env) +{ + ARMCPU *cpu = env_archcpu(env); + abi_long ret = 0; + + if (env->tagged_addr_enable) { + ret |= PR_TAGGED_ADDR_ENABLE; + } + if (cpu_isar_feature(aa64_mte, cpu)) { + /* See do_prctl_set_tagged_addr_ctrl. */ + ret |= extract64(env->cp15.sctlr_el[1], 38, 2) << PR_MTE_TCF_SHIFT; + ret = deposit64(ret, PR_MTE_TAG_SHIFT, 16, ~env->cp15.gcr_el1); + } + return ret; +} +#define do_prctl_get_tagged_addr_ctrl do_prctl_get_tagged_addr_ctrl + +#endif /* AARCH64_TARGET_PRCTL_H */ diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h index 76f6c3391d..819f112ab0 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -20,27 +20,4 @@ struct target_pt_regs { #define TARGET_MCL_FUTURE 2 #define TARGET_MCL_ONFAULT 4 -#define TARGET_PR_SVE_SET_VL 50 -#define TARGET_PR_SVE_GET_VL 51 - -#define TARGET_PR_PAC_RESET_KEYS 54 -# define TARGET_PR_PAC_APIAKEY (1 << 0) -# define TARGET_PR_PAC_APIBKEY (1 << 1) -# define TARGET_PR_PAC_APDAKEY (1 << 2) -# define TARGET_PR_PAC_APDBKEY (1 << 3) -# define TARGET_PR_PAC_APGAKEY (1 << 4) - -#define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 -#define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 -# define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) -/* MTE tag check fault modes */ -# define TARGET_PR_MTE_TCF_SHIFT 1 -# define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT) -/* MTE tag inclusion mask */ -# define TARGET_PR_MTE_TAG_SHIFT 3 -# define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIFT) - #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/alpha/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/arm/target_prctl.h b/linux-user/arm/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/arm/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/cris/target_prctl.h b/linux-user/cris/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/cris/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/hexagon/target_prctl.h b/linux-user/hexagon/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/hexagon/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/hppa/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/i386/target_prctl.h b/linux-user/i386/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/i386/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/m68k/target_prctl.h b/linux-user/m68k/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/m68k/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/microblaze/target_prctl.h b/linux-user/microblaze/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/microblaze/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/mips/target_prctl.h b/linux-user/mips/target_prctl.h new file mode 100644 index 0000000000..e028333db9 --- /dev/null +++ b/linux-user/mips/target_prctl.h @@ -0,0 +1,88 @@ +/* + * MIPS specific prctl functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef MIPS_TARGET_PRCTL_H +#define MIPS_TARGET_PRCTL_H + +static abi_long do_prctl_get_fp_mode(CPUArchState *env) +{ + abi_long ret = 0; + + if (env->CP0_Status & (1 << CP0St_FR)) { + ret |= PR_FP_MODE_FR; + } + if (env->CP0_Config5 & (1 << CP0C5_FRE)) { + ret |= PR_FP_MODE_FRE; + } + return ret; +} +#define do_prctl_get_fp_mode do_prctl_get_fp_mode + +static abi_long do_prctl_set_fp_mode(CPUArchState *env, abi_long arg2) +{ + bool old_fr = env->CP0_Status & (1 << CP0St_FR); + bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE); + bool new_fr = arg2 & PR_FP_MODE_FR; + bool new_fre = arg2 & PR_FP_MODE_FRE; + const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE; + + /* If nothing to change, return right away, successfully. */ + if (old_fr == new_fr && old_fre == new_fre) { + return 0; + } + /* Check the value is valid */ + if (arg2 & ~known_bits) { + return -TARGET_EOPNOTSUPP; + } + /* Setting FRE without FR is not supported. */ + if (new_fre && !new_fr) { + return -TARGET_EOPNOTSUPP; + } + if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) { + /* FR1 is not supported */ + return -TARGET_EOPNOTSUPP; + } + if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64)) + && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { + /* cannot set FR=0 */ + return -TARGET_EOPNOTSUPP; + } + if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) { + /* Cannot set FRE=1 */ + return -TARGET_EOPNOTSUPP; + } + + int i; + fpr_t *fpr = env->active_fpu.fpr; + for (i = 0; i < 32 ; i += 2) { + if (!old_fr && new_fr) { + fpr[i].w[!FP_ENDIAN_IDX] = fpr[i + 1].w[FP_ENDIAN_IDX]; + } else if (old_fr && !new_fr) { + fpr[i + 1].w[FP_ENDIAN_IDX] = fpr[i].w[!FP_ENDIAN_IDX]; + } + } + + if (new_fr) { + env->CP0_Status |= (1 << CP0St_FR); + env->hflags |= MIPS_HFLAG_F64; + } else { + env->CP0_Status &= ~(1 << CP0St_FR); + env->hflags &= ~MIPS_HFLAG_F64; + } + if (new_fre) { + env->CP0_Config5 |= (1 << CP0C5_FRE); + if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { + env->hflags |= MIPS_HFLAG_FRE; + } + } else { + env->CP0_Config5 &= ~(1 << CP0C5_FRE); + env->hflags &= ~MIPS_HFLAG_FRE; + } + + return 0; +} +#define do_prctl_set_fp_mode do_prctl_set_fp_mode + +#endif /* MIPS_TARGET_PRCTL_H */ diff --git a/linux-user/mips/target_syscall.h b/linux-user/mips/target_syscall.h index f59057493a..1ce0a5bbf4 100644 --- a/linux-user/mips/target_syscall.h +++ b/linux-user/mips/target_syscall.h @@ -36,10 +36,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env) return 0x40000; } -/* MIPS-specific prctl() options */ -#define TARGET_PR_SET_FP_MODE 45 -#define TARGET_PR_GET_FP_MODE 46 -#define TARGET_PR_FP_MODE_FR (1 << 0) -#define TARGET_PR_FP_MODE_FRE (1 << 1) - #endif /* MIPS_TARGET_SYSCALL_H */ diff --git a/linux-user/mips64/target_prctl.h b/linux-user/mips64/target_prctl.h new file mode 100644 index 0000000000..18da9ae619 --- /dev/null +++ b/linux-user/mips64/target_prctl.h @@ -0,0 +1 @@ +#include "../mips/target_prctl.h" diff --git a/linux-user/mips64/target_syscall.h b/linux-user/mips64/target_syscall.h index cd1e1b4969..74f12365bc 100644 --- a/linux-user/mips64/target_syscall.h +++ b/linux-user/mips64/target_syscall.h @@ -33,10 +33,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env) return 0x40000; } -/* MIPS-specific prctl() options */ -#define TARGET_PR_SET_FP_MODE 45 -#define TARGET_PR_GET_FP_MODE 46 -#define TARGET_PR_FP_MODE_FR (1 << 0) -#define TARGET_PR_FP_MODE_FRE (1 << 1) - #endif /* MIPS64_TARGET_SYSCALL_H */ diff --git a/linux-user/nios2/target_prctl.h b/linux-user/nios2/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/nios2/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/openrisc/target_prctl.h b/linux-user/openrisc/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/openrisc/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/ppc/target_prctl.h b/linux-user/ppc/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/ppc/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/riscv/target_prctl.h b/linux-user/riscv/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/riscv/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/s390x/target_prctl.h b/linux-user/s390x/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/s390x/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/sh4/target_prctl.h b/linux-user/sh4/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/sh4/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/sparc/target_prctl.h b/linux-user/sparc/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/sparc/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/x86_64/target_prctl.h b/linux-user/x86_64/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/x86_64/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/xtensa/target_prctl.h b/linux-user/xtensa/target_prctl.h new file mode 100644 index 0000000000..eb53b31ad5 --- /dev/null +++ b/linux-user/xtensa/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 544f5b662f..a417396981 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6291,9 +6291,155 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr) return ret; } #endif /* defined(TARGET_ABI32 */ - #endif /* defined(TARGET_I386) */ +/* + * These constants are generic. Supply any that are missing from the host. + */ +#ifndef PR_SET_NAME +# define PR_SET_NAME 15 +# define PR_GET_NAME 16 +#endif +#ifndef PR_SET_FP_MODE +# define PR_SET_FP_MODE 45 +# define PR_GET_FP_MODE 46 +# define PR_FP_MODE_FR (1 << 0) +# define PR_FP_MODE_FRE (1 << 1) +#endif +#ifndef PR_SVE_SET_VL +# define PR_SVE_SET_VL 50 +# define PR_SVE_GET_VL 51 +# define PR_SVE_VL_LEN_MASK 0xffff +# define PR_SVE_VL_INHERIT (1 << 17) +#endif +#ifndef PR_PAC_RESET_KEYS +# define PR_PAC_RESET_KEYS 54 +# define PR_PAC_APIAKEY (1 << 0) +# define PR_PAC_APIBKEY (1 << 1) +# define PR_PAC_APDAKEY (1 << 2) +# define PR_PAC_APDBKEY (1 << 3) +# define PR_PAC_APGAKEY (1 << 4) +#endif +#ifndef PR_SET_TAGGED_ADDR_CTRL +# define PR_SET_TAGGED_ADDR_CTRL 55 +# define PR_GET_TAGGED_ADDR_CTRL 56 +# define PR_TAGGED_ADDR_ENABLE (1UL << 0) +#endif +#ifndef PR_MTE_TCF_SHIFT +# define PR_MTE_TCF_SHIFT 1 +# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TAG_SHIFT 3 +# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) +#endif + +#include "target_prctl.h" + +static abi_long do_prctl_inval0(CPUArchState *env) +{ + return -TARGET_EINVAL; +} + +static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2) +{ + return -TARGET_EINVAL; +} + +#ifndef do_prctl_get_fp_mode +#define do_prctl_get_fp_mode do_prctl_inval0 +#endif +#ifndef do_prctl_set_fp_mode +#define do_prctl_set_fp_mode do_prctl_inval1 +#endif +#ifndef do_prctl_get_vl +#define do_prctl_get_vl do_prctl_inval0 +#endif +#ifndef do_prctl_set_vl +#define do_prctl_set_vl do_prctl_inval1 +#endif +#ifndef do_prctl_reset_keys +#define do_prctl_reset_keys do_prctl_inval1 +#endif +#ifndef do_prctl_set_tagged_addr_ctrl +#define do_prctl_set_tagged_addr_ctrl do_prctl_inval1 +#endif +#ifndef do_prctl_get_tagged_addr_ctrl +#define do_prctl_get_tagged_addr_ctrl do_prctl_inval0 +#endif + +static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, + abi_long arg3, abi_long arg4, abi_long arg5) +{ + abi_long ret; + + switch (option) { + case PR_GET_PDEATHSIG: + { + int deathsig; + ret = get_errno(prctl(PR_GET_PDEATHSIG, &deathsig, + arg3, arg4, arg5)); + if (!is_error(ret) && arg2 && put_user_s32(deathsig, arg2)) { + return -TARGET_EFAULT; + } + return ret; + } + case PR_GET_NAME: + { + void *name = lock_user(VERIFY_WRITE, arg2, 16, 1); + if (!name) { + return -TARGET_EFAULT; + } + ret = get_errno(prctl(PR_GET_NAME, (uintptr_t)name, + arg3, arg4, arg5)); + unlock_user(name, arg2, 16); + return ret; + } + case PR_SET_NAME: + { + void *name = lock_user(VERIFY_READ, arg2, 16, 1); + if (!name) { + return -TARGET_EFAULT; + } + ret = get_errno(prctl(PR_SET_NAME, (uintptr_t)name, + arg3, arg4, arg5)); + unlock_user(name, arg2, 0); + return ret; + } + case PR_GET_FP_MODE: + return do_prctl_get_fp_mode(env); + case PR_SET_FP_MODE: + return do_prctl_set_fp_mode(env, arg2); + case PR_SVE_GET_VL: + return do_prctl_get_vl(env); + case PR_SVE_SET_VL: + return do_prctl_set_vl(env, arg2); + case PR_PAC_RESET_KEYS: + if (arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_reset_keys(env, arg2); + case PR_SET_TAGGED_ADDR_CTRL: + if (arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_set_tagged_addr_ctrl(env, arg2); + case PR_GET_TAGGED_ADDR_CTRL: + if (arg2 || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_get_tagged_addr_ctrl(env); + case PR_GET_SECCOMP: + case PR_SET_SECCOMP: + /* Disable seccomp to prevent the target disabling syscalls we need. */ + return -TARGET_EINVAL; + default: + /* Most prctl options have no pointer arguments */ + return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + } +} + #define NEW_STACK_SIZE 0x40000 @@ -10630,290 +10776,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, return ret; #endif case TARGET_NR_prctl: - switch (arg1) { - case PR_GET_PDEATHSIG: - { - int deathsig; - ret = get_errno(prctl(arg1, &deathsig, arg3, arg4, arg5)); - if (!is_error(ret) && arg2 - && put_user_s32(deathsig, arg2)) { - return -TARGET_EFAULT; - } - return ret; - } -#ifdef PR_GET_NAME - case PR_GET_NAME: - { - void *name = lock_user(VERIFY_WRITE, arg2, 16, 1); - if (!name) { - return -TARGET_EFAULT; - } - ret = get_errno(prctl(arg1, (unsigned long)name, - arg3, arg4, arg5)); - unlock_user(name, arg2, 16); - return ret; - } - case PR_SET_NAME: - { - void *name = lock_user(VERIFY_READ, arg2, 16, 1); - if (!name) { - return -TARGET_EFAULT; - } - ret = get_errno(prctl(arg1, (unsigned long)name, - arg3, arg4, arg5)); - unlock_user(name, arg2, 0); - return ret; - } -#endif -#ifdef TARGET_MIPS - case TARGET_PR_GET_FP_MODE: - { - CPUMIPSState *env = ((CPUMIPSState *)cpu_env); - ret = 0; - if (env->CP0_Status & (1 << CP0St_FR)) { - ret |= TARGET_PR_FP_MODE_FR; - } - if (env->CP0_Config5 & (1 << CP0C5_FRE)) { - ret |= TARGET_PR_FP_MODE_FRE; - } - return ret; - } - case TARGET_PR_SET_FP_MODE: - { - CPUMIPSState *env = ((CPUMIPSState *)cpu_env); - bool old_fr = env->CP0_Status & (1 << CP0St_FR); - bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE); - bool new_fr = arg2 & TARGET_PR_FP_MODE_FR; - bool new_fre = arg2 & TARGET_PR_FP_MODE_FRE; - - const unsigned int known_bits = TARGET_PR_FP_MODE_FR | - TARGET_PR_FP_MODE_FRE; - - /* If nothing to change, return right away, successfully. */ - if (old_fr == new_fr && old_fre == new_fre) { - return 0; - } - /* Check the value is valid */ - if (arg2 & ~known_bits) { - return -TARGET_EOPNOTSUPP; - } - /* Setting FRE without FR is not supported. */ - if (new_fre && !new_fr) { - return -TARGET_EOPNOTSUPP; - } - if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) { - /* FR1 is not supported */ - return -TARGET_EOPNOTSUPP; - } - if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64)) - && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { - /* cannot set FR=0 */ - return -TARGET_EOPNOTSUPP; - } - if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) { - /* Cannot set FRE=1 */ - return -TARGET_EOPNOTSUPP; - } - - int i; - fpr_t *fpr = env->active_fpu.fpr; - for (i = 0; i < 32 ; i += 2) { - if (!old_fr && new_fr) { - fpr[i].w[!FP_ENDIAN_IDX] = fpr[i + 1].w[FP_ENDIAN_IDX]; - } else if (old_fr && !new_fr) { - fpr[i + 1].w[FP_ENDIAN_IDX] = fpr[i].w[!FP_ENDIAN_IDX]; - } - } - - if (new_fr) { - env->CP0_Status |= (1 << CP0St_FR); - env->hflags |= MIPS_HFLAG_F64; - } else { - env->CP0_Status &= ~(1 << CP0St_FR); - env->hflags &= ~MIPS_HFLAG_F64; - } - if (new_fre) { - env->CP0_Config5 |= (1 << CP0C5_FRE); - if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { - env->hflags |= MIPS_HFLAG_FRE; - } - } else { - env->CP0_Config5 &= ~(1 << CP0C5_FRE); - env->hflags &= ~MIPS_HFLAG_FRE; - } - - return 0; - } -#endif /* MIPS */ -#ifdef TARGET_AARCH64 - case TARGET_PR_SVE_SET_VL: - /* - * We cannot support either PR_SVE_SET_VL_ONEXEC or - * PR_SVE_VL_INHERIT. Note the kernel definition - * of sve_vl_valid allows for VQ=512, i.e. VL=8192, - * even though the current architectural maximum is VQ=16. - */ - ret = -TARGET_EINVAL; - if (cpu_isar_feature(aa64_sve, env_archcpu(cpu_env)) - && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { - CPUARMState *env = cpu_env; - ARMCPU *cpu = env_archcpu(env); - uint32_t vq, old_vq; - - old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; - vq = MAX(arg2 / 16, 1); - vq = MIN(vq, cpu->sve_max_vq); - - if (vq < old_vq) { - aarch64_sve_narrow_vq(env, vq); - } - env->vfp.zcr_el[1] = vq - 1; - arm_rebuild_hflags(env); - ret = vq * 16; - } - return ret; - case TARGET_PR_SVE_GET_VL: - ret = -TARGET_EINVAL; - { - ARMCPU *cpu = env_archcpu(cpu_env); - if (cpu_isar_feature(aa64_sve, cpu)) { - ret = ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; - } - } - return ret; - case TARGET_PR_PAC_RESET_KEYS: - { - CPUARMState *env = cpu_env; - ARMCPU *cpu = env_archcpu(env); - - if (arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - int all = (TARGET_PR_PAC_APIAKEY | TARGET_PR_PAC_APIBKEY | - TARGET_PR_PAC_APDAKEY | TARGET_PR_PAC_APDBKEY | - TARGET_PR_PAC_APGAKEY); - int ret = 0; - Error *err = NULL; - - if (arg2 == 0) { - arg2 = all; - } else if (arg2 & ~all) { - return -TARGET_EINVAL; - } - if (arg2 & TARGET_PR_PAC_APIAKEY) { - ret |= qemu_guest_getrandom(&env->keys.apia, - sizeof(ARMPACKey), &err); - } - if (arg2 & TARGET_PR_PAC_APIBKEY) { - ret |= qemu_guest_getrandom(&env->keys.apib, - sizeof(ARMPACKey), &err); - } - if (arg2 & TARGET_PR_PAC_APDAKEY) { - ret |= qemu_guest_getrandom(&env->keys.apda, - sizeof(ARMPACKey), &err); - } - if (arg2 & TARGET_PR_PAC_APDBKEY) { - ret |= qemu_guest_getrandom(&env->keys.apdb, - sizeof(ARMPACKey), &err); - } - if (arg2 & TARGET_PR_PAC_APGAKEY) { - ret |= qemu_guest_getrandom(&env->keys.apga, - sizeof(ARMPACKey), &err); - } - if (ret != 0) { - /* - * Some unknown failure in the crypto. The best - * we can do is log it and fail the syscall. - * The real syscall cannot fail this way. - */ - qemu_log_mask(LOG_UNIMP, - "PR_PAC_RESET_KEYS: Crypto failure: %s", - error_get_pretty(err)); - error_free(err); - return -TARGET_EIO; - } - return 0; - } - } - return -TARGET_EINVAL; - case TARGET_PR_SET_TAGGED_ADDR_CTRL: - { - abi_ulong valid_mask = TARGET_PR_TAGGED_ADDR_ENABLE; - CPUARMState *env = cpu_env; - ARMCPU *cpu = env_archcpu(env); - - if (cpu_isar_feature(aa64_mte, cpu)) { - valid_mask |= TARGET_PR_MTE_TCF_MASK; - valid_mask |= TARGET_PR_MTE_TAG_MASK; - } - - if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - env->tagged_addr_enable = arg2 & TARGET_PR_TAGGED_ADDR_ENABLE; - - if (cpu_isar_feature(aa64_mte, cpu)) { - switch (arg2 & TARGET_PR_MTE_TCF_MASK) { - case TARGET_PR_MTE_TCF_NONE: - case TARGET_PR_MTE_TCF_SYNC: - case TARGET_PR_MTE_TCF_ASYNC: - break; - default: - return -EINVAL; - } - - /* - * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. - * Note that the syscall values are consistent with hw. - */ - env->cp15.sctlr_el[1] = - deposit64(env->cp15.sctlr_el[1], 38, 2, - arg2 >> TARGET_PR_MTE_TCF_SHIFT); - - /* - * Write PR_MTE_TAG to GCR_EL1[Exclude]. - * Note that the syscall uses an include mask, - * and hardware uses an exclude mask -- invert. - */ - env->cp15.gcr_el1 = - deposit64(env->cp15.gcr_el1, 0, 16, - ~arg2 >> TARGET_PR_MTE_TAG_SHIFT); - arm_rebuild_hflags(env); - } - return 0; - } - case TARGET_PR_GET_TAGGED_ADDR_CTRL: - { - abi_long ret = 0; - CPUARMState *env = cpu_env; - ARMCPU *cpu = env_archcpu(env); - - if (arg2 || arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - if (env->tagged_addr_enable) { - ret |= TARGET_PR_TAGGED_ADDR_ENABLE; - } - if (cpu_isar_feature(aa64_mte, cpu)) { - /* See above. */ - ret |= (extract64(env->cp15.sctlr_el[1], 38, 2) - << TARGET_PR_MTE_TCF_SHIFT); - ret = deposit64(ret, TARGET_PR_MTE_TAG_SHIFT, 16, - ~env->cp15.gcr_el1); - } - return ret; - } -#endif /* AARCH64 */ - case PR_GET_SECCOMP: - case PR_SET_SECCOMP: - /* Disable seccomp to prevent the target disabling syscalls we - * need. */ - return -TARGET_EINVAL; - default: - /* Most prctl options have no pointer arguments */ - return get_errno(prctl(arg1, arg2, arg3, arg4, arg5)); - } + return do_prctl(cpu_env, arg1, arg2, arg3, arg4, arg5); break; #ifdef TARGET_NR_arch_prctl case TARGET_NR_arch_prctl: From patchwork Wed Oct 13 02:45:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515695 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6087819ime; Tue, 12 Oct 2021 20:02:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwx2wjOA9FNAS9fXU98DgRSN3PmVEMUTUS+3v+kwcUxQrCZ7nx7B2MYmrJmtLZ3Cjg9hu6N X-Received: by 2002:a25:bb52:: with SMTP id b18mr33489785ybk.506.1634094179833; Tue, 12 Oct 2021 20:02:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634094179; cv=none; d=google.com; s=arc-20160816; b=Ple3kd5UvDspG4ZSoU3OBpp0JU82U9lfj8z6o4mC+dXeAw5exrFTy653LnlsREcvrJ 0RIbfTmKJK97REmJLxQ9sx1cP7sdipwpITy23x0TjKoOccvayIGqfq+r14xXGGh/stPz 2JXpoNjPyezdC/HLNtnkxILekD0wean6y/SwHAhf1V3G4B69d0ob1UHA7cT6ns/2BpN9 LeptrQ1FBJWzk+4tvOR0gH2Lq9MIv7FmoFAYoynV6TndeZ19wc+Wbqu33Y1u6ueM/uRi vzQIyU0KUimxsNcdKtRvIui5iEX8gWNOAlI423d1uKi0ARpeyZb5v6YgUfd/hAABKs9u tEDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OxMgM7wzD4BcAcUx2qJmodE4BwJ9QwGNSAt09qoFyFU=; b=yFiq2G9I3oCOkfZGYsNtv5uG3v4ui5bnV7ZY4mRXYjC+pZcBYKr4M1PU+WtoiikzfP 6KK8JE+KQ3+DLTF+vRaQWJ1D2b7+7V+VtZs3NbObDIMF5SGpmiKP60ZKZiH2s/mV11lP 8LEq8rP3E31JZPDp8sh1feDBID0olN7ApTnYpW5ARme39OLkQhnuuCDm5U4Ksu77FzCi y+aybNScqzYJ9Kkye7U6NNUh2ZAQKK4HcppYvpkG/GenY8nBljLOo8AI9f8EZVTUnZY2 5tmEiZYzL3oLTO4LtbbtVZRs0R1swXqJiOqpx1EsIcklKTRLWtqsa+MSQgTJK4ZK9vBD tW6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Tb6Cp1cg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n75si15174960yba.79.2021.10.12.20.02.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 20:02:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Tb6Cp1cg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36468 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUXj-0005ud-6I for patch@linaro.org; Tue, 12 Oct 2021 23:02:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57086) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUI0-0004yW-Ei for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:44 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:44991) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUHy-00058j-QS for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:44 -0400 Received: by mail-pf1-x42c.google.com with SMTP id w6so1131734pfd.11 for ; Tue, 12 Oct 2021 19:46:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OxMgM7wzD4BcAcUx2qJmodE4BwJ9QwGNSAt09qoFyFU=; b=Tb6Cp1cgY8OBfvyhPmsjUTlr/Dpqx0iV0P617ZHJTnpJyD2bliSSVuXt5LZxGhiZta uXxZ1krBrUCiwxzFRazOgsdNhMeTp9uZlLd/c4ygbMbxCVaxWMVd0a2CLM2E6toBhn5N TU7AXfIvC6tMUCLtHR6ZGEcCydEQ3s0Jm2+VDz38pt9H13KEA6CMjfxAr7+mPbAdFjDj ELt7iiQaVAhFpQYlbmxAUioAEYyJj/MC5KIvi+iYLG3WWt5V5ehsqRdtN7OnLkEtZPg+ F8QNRSkKLZLszVdNLcmRWjb2nsriPjxmHkE4K3eW9FHIZma/v3q6cc8S7zDL2NJDHuCT 5rnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OxMgM7wzD4BcAcUx2qJmodE4BwJ9QwGNSAt09qoFyFU=; b=vnJUHTbIHVV12lClkJSojDO3xpf8r7bugoO2Cr/+JWnqwnoaVwQMmW1NRvfWiLzQka /Qi4A7FB/+zlzEYOr9Gii/X8L7zFnjHnre9EY7EQa61ayrZh5DKAT05j0qQwy2dKu3tO dewJspfdR+MTwi33h9emlhB7nKbf0vyDyGldIAJkCTkqSUpJNTryNuj97ca5QfYsIzep ldiHbQYFBmVKIijV3bpvHb19W89VDx5qwCGN8mFI6t6g3NnAVbyXI8C0qED92+5Li+uk emPzThQf0o9/KfaQ7l+BgGHYO24qB1d7okI8kQXD8+CpuNeGYr9CK0J+qNldM93S0mvC SUPw== X-Gm-Message-State: AOAM530fpU9PWuNK7Tg9k6l0prq8GEeFWI2Q91i9m4wPb52qsvATQorJ Gr7OD0D8icIZGTi7UHxa89Xw4XCWALAvDA== X-Received: by 2002:a62:1995:0:b0:44c:728e:323b with SMTP id 143-20020a621995000000b0044c728e323bmr35081202pfz.54.1634093201429; Tue, 12 Oct 2021 19:46:41 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 32/48] linux-user: Disable more prctl subcodes Date: Tue, 12 Oct 2021 19:45:51 -0700 Message-Id: <20211013024607.731881-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a list of subcodes that we want to pass on, a list of subcodes that should not be passed on because they would affect the running qemu itself, and a list that probably could be implemented but require extra work. Do not pass on unknown subcodes. Signed-off-by: Richard Henderson --- linux-user/syscall.c | 56 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 52 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/linux-user/syscall.c b/linux-user/syscall.c index a417396981..7635c2397a 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6334,6 +6334,13 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr) # define PR_MTE_TAG_SHIFT 3 # define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) #endif +#ifndef PR_SET_IO_FLUSHER +# define PR_SET_IO_FLUSHER 57 +# define PR_GET_IO_FLUSHER 58 +#endif +#ifndef PR_SET_SYSCALL_USER_DISPATCH +# define PR_SET_SYSCALL_USER_DISPATCH 59 +#endif #include "target_prctl.h" @@ -6430,13 +6437,54 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, return -TARGET_EINVAL; } return do_prctl_get_tagged_addr_ctrl(env); + + case PR_GET_DUMPABLE: + case PR_SET_DUMPABLE: + case PR_GET_KEEPCAPS: + case PR_SET_KEEPCAPS: + case PR_GET_TIMING: + case PR_SET_TIMING: + case PR_GET_TIMERSLACK: + case PR_SET_TIMERSLACK: + case PR_MCE_KILL: + case PR_MCE_KILL_GET: + case PR_GET_NO_NEW_PRIVS: + case PR_SET_NO_NEW_PRIVS: + case PR_GET_IO_FLUSHER: + case PR_SET_IO_FLUSHER: + /* Some prctl options have no pointer arguments and we can pass on. */ + return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + + case PR_GET_CHILD_SUBREAPER: + case PR_SET_CHILD_SUBREAPER: + case PR_GET_SPECULATION_CTRL: + case PR_SET_SPECULATION_CTRL: + case PR_GET_TID_ADDRESS: + /* TODO */ + return -TARGET_EINVAL; + + case PR_GET_FPEXC: + case PR_SET_FPEXC: + /* Was used for SPE on PowerPC. */ + return -TARGET_EINVAL; + + case PR_GET_ENDIAN: + case PR_SET_ENDIAN: + case PR_GET_FPEMU: + case PR_SET_FPEMU: + case PR_SET_MM: case PR_GET_SECCOMP: case PR_SET_SECCOMP: - /* Disable seccomp to prevent the target disabling syscalls we need. */ - return -TARGET_EINVAL; + case PR_SET_SYSCALL_USER_DISPATCH: + case PR_GET_THP_DISABLE: + case PR_SET_THP_DISABLE: + case PR_GET_TSC: + case PR_SET_TSC: + case PR_GET_UNALIGN: + case PR_SET_UNALIGN: default: - /* Most prctl options have no pointer arguments */ - return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + /* Disable to prevent the target disabling stuff we need. */ + return -TARGET_EINVAL; } } From patchwork Wed Oct 13 02:45:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515704 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6091969ime; Tue, 12 Oct 2021 20:09:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxqIYhg94mJpX2Hx9r1tAS+yYfgG+7X3AZWTNjRwP3qUQr+aj5kRCyGXr68vBZeg4fxjnrr X-Received: by 2002:ae9:dd85:: with SMTP id r127mr22373641qkf.173.1634094574061; Tue, 12 Oct 2021 20:09:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634094574; cv=none; d=google.com; s=arc-20160816; b=YjoRrVsRvu/+JAaqEmZk+9S2RAqny1WP0S20njQ0EqA01h99eoD6XnB/rHeJ6gFw5h l08lvGJcMcWBslKUHAuYZge3Tc7PU0WtqGYA2V0K+6wmJaEt1zztR7yCbzh130XOH0Hh 4nL+gZlUI3Nu7oREKeZuucmdyUTpFyXY9PASAVZRJHnsIc+Wshp2lpukdbxPlz0QyY0g g+FUKpvazNSMtHpzzfN5Z7gW1DWTzV7rW87uhs6nTpBRcOxe/Zv8ZJf93p1Ll+FIV5vs ruGs9SwbDFsGJrgAqArSYj1foxgZ6pvTa+NIfuRZ6qK74eVLnw4ZEnXdlrkqgJ7NZIwP 8DcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9lqN/uiH3UUIeVg5yhYMxWg7ld7QYTaBAGHdI8OeAIs=; b=Zg6ma1u405cKL5vs09oD2Tc82iJLWRGrCO0V0wb70dx2DTeowQLfXwbkT+5tIuqpSw u4F8g1q16wv3JalRjUDExv6y8M6glvPGRJZxckUP1C9jZ8U3BsceRV0P+STIf5NowvES XmLrhWn3C+Vyr/fYNrTB+xhb0XUjtkI3ycQvHC2WkFcWvFx0eqNDfotX0dmJaYwblQti mOrffbbx97HSPotApEuBoF5mC1uxUZRt8+8AosPERIVP9e7cfZGl5RqOn2tu+3C4afnf IL1Nd93LkkGFqogCziiZoRP9yAHLdnpIma2rZeTPwvIolc8w/tRVU2EKYkl5ESki9kUt eflA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ME+Rk2An; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z23si7434697qkj.147.2021.10.12.20.09.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 20:09:34 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ME+Rk2An; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53582 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUe5-0001Bk-Ds for patch@linaro.org; Tue, 12 Oct 2021 23:09:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57104) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUI1-0004zt-K7 for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:46 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:35762) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUI0-00059a-0A for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:45 -0400 Received: by mail-pg1-x530.google.com with SMTP id e7so902064pgk.2 for ; Tue, 12 Oct 2021 19:46:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9lqN/uiH3UUIeVg5yhYMxWg7ld7QYTaBAGHdI8OeAIs=; b=ME+Rk2AnpC2B5exQwr/bDmShZKfqZNODJjNJYXpZZiL/yi8PfCElC4A1z9VH9UnnuI S7HqUf2X/hizj8C0HA5HkbDfzG647GHVqrabW4th7QAC+OroJwb1JrO8BooJY02F2dZJ sWBwDlwtAkNao2NicnnLhhOE7JxHgJXcnsG84/YWLk0QGAKWh6LcFi9eU0Y0Pu0JP0pK er9AdXKY4Du7ypFVPhMg9aOcxXLQ1S1K5SDaGF7sYBAJasHyv1/C5aG7Hehjq7sR/TG3 Cv7yQc/rNx8IR/yFLGuy1FNFpeIpzulEGdV2UJMAije6Wp0yQLlU6YTAdkU2VB2Pn0CD On8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9lqN/uiH3UUIeVg5yhYMxWg7ld7QYTaBAGHdI8OeAIs=; b=jGjzPITlfQawem5V/cFWDVdIQb5lmX7H6RyWjj8qpw6ZWfhQ+Rd0KRWNflBLfakNg7 i0H+EUXGV8toCbu3Nynu65MXTJ0l4Xg2TGL4MYKyhimWvGYEl/iUyZXmy1adyPdgzQSQ h/IvtBYtKc+9V/4RqBB3IhNtM8uI4phogLkl2Fc1XoUDEGeNJ5lSwJfQoRbL7NBPRoNn FafmVdGFNmcmgB70KnLi1w6X3iw8bcDdOSbyxB718J3wOo9oCtU5fgOVglSV1rKtdzhX 1rz0IIutvbYdGX07foJ79oOiPpAGOEKR0T9jeLNGFr2h/d0YU4AA5XgsqC0YppJ/k+YJ Ea6Q== X-Gm-Message-State: AOAM530rMhdWfib4YS082gKcDre2iCADiKNt0+XfTfQL6wqDdUBgCJqw Au8OFYzXJQkp5bdZh7FxirzmgH3O71+/Bg== X-Received: by 2002:a65:664f:: with SMTP id z15mr25730926pgv.252.1634093202506; Tue, 12 Oct 2021 19:46:42 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 33/48] Revert "cpu: Move cpu_common_props to hw/core/cpu.c" Date: Tue, 12 Oct 2021 19:45:52 -0700 Message-Id: <20211013024607.731881-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f. Despite a comment saying why cpu_common_props cannot be placed in a file that is compiled once, it was moved anyway. Revert that. Since then, Property is not defined in hw/core/cpu.h, so it is now easier to declare a function to install the properties rather than the Property array itself. Cc: Eduardo Habkost Suggested-by: Peter Maydell Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 1 + cpu.c | 21 +++++++++++++++++++++ hw/core/cpu-common.c | 17 +---------------- 3 files changed, 23 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b7d5bc1200..1a10497af3 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1008,6 +1008,7 @@ void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) GCC_FMT_ATTR(2, 3); /* $(top_srcdir)/cpu.c */ +void cpu_class_init_props(DeviceClass *dc); void cpu_exec_initfn(CPUState *cpu); void cpu_exec_realizefn(CPUState *cpu, Error **errp); void cpu_exec_unrealizefn(CPUState *cpu); diff --git a/cpu.c b/cpu.c index e1799a15bc..9bce67ef55 100644 --- a/cpu.c +++ b/cpu.c @@ -179,6 +179,27 @@ void cpu_exec_unrealizefn(CPUState *cpu) cpu_list_remove(cpu); } +static Property cpu_common_props[] = { +#ifndef CONFIG_USER_ONLY + /* + * Create a memory property for softmmu CPU object, + * so users can wire up its memory. (This can't go in hw/core/cpu.c + * because that file is compiled only once for both user-mode + * and system builds.) The default if no link is set up is to use + * the system address space. + */ + DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, + MemoryRegion *), +#endif + DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false), + DEFINE_PROP_END_OF_LIST(), +}; + +void cpu_class_init_props(DeviceClass *dc) +{ + device_class_set_props(dc, cpu_common_props); +} + void cpu_exec_initfn(CPUState *cpu) { cpu->as = NULL; diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index e2f5a64604..9e3241b430 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -257,21 +257,6 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu) return cpu->cpu_index; } -static Property cpu_common_props[] = { -#ifndef CONFIG_USER_ONLY - /* Create a memory property for softmmu CPU object, - * so users can wire up its memory. (This can't go in hw/core/cpu.c - * because that file is compiled only once for both user-mode - * and system builds.) The default if no link is set up is to use - * the system address space. - */ - DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, - MemoryRegion *), -#endif - DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false), - DEFINE_PROP_END_OF_LIST(), -}; - static void cpu_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -286,7 +271,7 @@ static void cpu_class_init(ObjectClass *klass, void *data) dc->realize = cpu_common_realizefn; dc->unrealize = cpu_common_unrealizefn; dc->reset = cpu_common_reset; - device_class_set_props(dc, cpu_common_props); + cpu_class_init_props(dc); /* * Reason: CPUs still need special care by board code: wiring up * IRQs, adding reset handlers, halting non-first CPUs, ... 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[209.51.188.17]) by mx.google.com with ESMTPS id n184si16125610ybb.242.2021.10.12.20.07.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 20:07:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pHBRKtk2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45016 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUbt-0003gU-EV for patch@linaro.org; Tue, 12 Oct 2021 23:07:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUI2-00050N-N5 for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:47 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:41801) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUI0-0005Ah-Oj for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:46 -0400 Received: by mail-pj1-x102f.google.com with SMTP id na16-20020a17090b4c1000b0019f5bb661f9so1173745pjb.0 for ; Tue, 12 Oct 2021 19:46:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=kgbxRfaLnXEAdarkY+uz+mGv9JnWFVB+tvkZlav9GvM=; b=pHBRKtk24reF8JBVq8nmR260wH/coRg+3NOwuHRALROq7ZOc2U7Qc7CSGgJqq06nWq GWmHe2NfiBgglSbPD/6ZliTTyHFjHNmrh4f2QPNmjLuG7myqlen1iOnEOmDS73NS4pl8 av0gG5x+WXYHVBgOjwAYfBBEWkt04IHP4v4e+UL4N85QGxITFnZ01HQ26Fikwy2TMHHE OtG2CgH9UuaGyCLVagrySL6XGmDXvAUdm9T44OJCazstjsk1vzitds0oj1s9mpNnUCpr 3pucZ5qUUZFrJTxvgTPk+ZyODJ3D7hym6AOmDTpYOpN9v6+SBbYdwoKoWeyTo6OJ1i47 zUUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kgbxRfaLnXEAdarkY+uz+mGv9JnWFVB+tvkZlav9GvM=; b=tzylj/FoBgdBgT5buKI9KozwgxLgCMyBitKC10fvGVuzn+FfGvNcNmeubAsAdm9AwA 1M/AMmcFBJIvHT59QzlTn5Ivx/JjvU3tlYFASDtssS0qO/5nw4BOgcoL1ZGiP4QlV4Km qQD3b201inTi9WyV9Es0GyWP1DWdlkBrcwp5Uri49Qt7FWGqqxeuZrbfIvDVwjtcDJcD 84Bmb93OTQRX0dncVixAAeeKUn+1yOx9aAfIMFIcoqlCSIjiRnqs3aDI+VZmo6M9p6P0 QKoJe1rU7YXrDW2RA9UR0Ek1vR1kGGZO0aRO75n5VnYRUcK5AvG0qskmx/XgRTG0u7vU 1EvQ== X-Gm-Message-State: AOAM532ZZIZSetNZDLJSz22DNKS23r7QO0n1AI6kMZfRyNA1Eky9iTnW X6VZkF7NAMzr17Tj1OsPzuLy94Qc0MPswg== X-Received: by 2002:a17:90b:2493:: with SMTP id nt19mr10661536pjb.78.1634093203462; Tue, 12 Oct 2021 19:46:43 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 34/48] linux-user: Add code for PR_GET/SET_UNALIGN Date: Tue, 12 Oct 2021 19:45:53 -0700 Message-Id: <20211013024607.731881-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This requires extra work for each target, but adds the common syscall code, and the necessary flag in CPUState. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 3 +++ linux-user/generic/target_prctl_unalign.h | 27 +++++++++++++++++++++++ cpu.c | 20 ++++++++++++----- linux-user/syscall.c | 13 +++++++++-- 4 files changed, 56 insertions(+), 7 deletions(-) create mode 100644 linux-user/generic/target_prctl_unalign.h -- 2.25.1 diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 1a10497af3..6202bbf9c3 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -412,6 +412,9 @@ struct CPUState { bool ignore_memory_transaction_failures; + /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ + bool prctl_unalign_sigbus; + struct hax_vcpu_state *hax_vcpu; struct hvf_vcpu_state *hvf; diff --git a/linux-user/generic/target_prctl_unalign.h b/linux-user/generic/target_prctl_unalign.h new file mode 100644 index 0000000000..bc3b83af2a --- /dev/null +++ b/linux-user/generic/target_prctl_unalign.h @@ -0,0 +1,27 @@ +/* + * Generic prctl unalign functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef GENERIC_TARGET_PRCTL_UNALIGN_H +#define GENERIC_TARGET_PRCTL_UNALIGN_H + +static abi_long do_prctl_get_unalign(CPUArchState *env, target_long arg2) +{ + CPUState *cs = env_cpu(env); + uint32_t res = PR_UNALIGN_NOPRINT; + if (cs->prctl_unalign_sigbus) { + res |= PR_UNALIGN_SIGBUS; + } + return put_user_u32(res, arg2); +} +#define do_prctl_get_unalign do_prctl_get_unalign + +static abi_long do_prctl_set_unalign(CPUArchState *env, target_long arg2) +{ + env_cpu(env)->prctl_unalign_sigbus = arg2 & PR_UNALIGN_SIGBUS; + return 0; +} +#define do_prctl_set_unalign do_prctl_set_unalign + +#endif /* GENERIC_TARGET_PRCTL_UNALIGN_H */ diff --git a/cpu.c b/cpu.c index 9bce67ef55..9e388d9cd3 100644 --- a/cpu.c +++ b/cpu.c @@ -179,13 +179,23 @@ void cpu_exec_unrealizefn(CPUState *cpu) cpu_list_remove(cpu); } +/* + * This can't go in hw/core/cpu.c because that file is compiled only + * once for both user-mode and system builds. + */ static Property cpu_common_props[] = { -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY /* - * Create a memory property for softmmu CPU object, - * so users can wire up its memory. (This can't go in hw/core/cpu.c - * because that file is compiled only once for both user-mode - * and system builds.) The default if no link is set up is to use + * Create a property for the user-only object, so users can + * adjust prctl(PR_SET_UNALIGN) from the command-line. + * Has no effect if the target does not support the feature. + */ + DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState, + prctl_unalign_sigbus, false), +#else + /* + * Create a memory property for softmmu CPU object, so users can + * wire up its memory. The default if no link is set up is to use * the system address space. */ DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 7635c2397a..ac3bc8a330 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6375,6 +6375,12 @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2) #ifndef do_prctl_get_tagged_addr_ctrl #define do_prctl_get_tagged_addr_ctrl do_prctl_inval0 #endif +#ifndef do_prctl_get_unalign +#define do_prctl_get_unalign do_prctl_inval1 +#endif +#ifndef do_prctl_set_unalign +#define do_prctl_set_unalign do_prctl_inval1 +#endif static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5) @@ -6438,6 +6444,11 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, } return do_prctl_get_tagged_addr_ctrl(env); + case PR_GET_UNALIGN: + return do_prctl_get_unalign(env, arg2); + case PR_SET_UNALIGN: + return do_prctl_set_unalign(env, arg2); + case PR_GET_DUMPABLE: case PR_SET_DUMPABLE: case PR_GET_KEEPCAPS: @@ -6480,8 +6491,6 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, case PR_SET_THP_DISABLE: case PR_GET_TSC: case PR_SET_TSC: - case PR_GET_UNALIGN: - case PR_SET_UNALIGN: default: /* Disable to prevent the target disabling stuff we need. */ return -TARGET_EINVAL; From patchwork Wed Oct 13 02:45:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515709 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6095152ime; Tue, 12 Oct 2021 20:14:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzgS8KHkSDGwcWVKDqoVsFaJt23jTYtNGrk/+nh+RoKZCdLC/RH3ot9M1y4Sr8JQ3AFd/ti X-Received: by 2002:a25:2387:: with SMTP id j129mr30467978ybj.246.1634094880909; Tue, 12 Oct 2021 20:14:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634094880; cv=none; d=google.com; s=arc-20160816; b=AR6JSGtsbNUmpBvR00EmC1CApzDQXvtR94fK1eQ4zS3YhZlJ0Zk3FiTnZDnEJ7DSmr Fy0oOcLqitbcA5mLzs8oGj0QJynDts0dMhBm1zP4mUaQnKVQvTR6TMhH27cvWGZW3xcH r2+QRO8VezULJxM1Euh4nCcAPZSun3ThmiucekU0zNnVbat7vzFvM8ft+jdolm5qsl7R ru1lk99rLCJ0eCHaZtR7TJsSAOBYuXsrM1XIVoHoM0OKLcgF5HWwPFyjy/nuMuvsM7ep EQyCXVyfD+x2TMF5Zk6s0CeVY9T40QG9Skx38GH4HMQaK3nizb8mqRxqZW0vVfohR8rp fxqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=O7p/UQX85gsSrL9h3Ho/u9/oHHasfkLJHADwG/5kd8Q=; b=Ev3B9KR740245tHJwQfk1P1wAhsZRXvtEIZ4k0SVzlUFssBZY1/IBlhehyNf9QqoZH k2rSOHEmQ0A2igBdHPIghqcj0Ga7u3gBTyVr10eJ+7WtCtIYqxUpPjS7XRWGdp/v7vv9 asOmTRxmRrB7WTeoX6BPloP2li/8r4pdXYSO7yrmQINL4Zpm31tl7OX6DEmlBYJjWySi P9bWJzBebzg3fRvJxU53Z+hu92LRDpM+XP94qZPis1wswW9XVSUd7bQeBpRMJIbzqQbg Jy8/AXOcGXCDsmweAZm+xMBgk2pVBgaZL0kkZ2+884ZFFBktW5hNKTfaeKx9ulg3XRYD aCuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fHs3Xehz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 191si13950363ybf.426.2021.10.12.20.14.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 20:14:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fHs3Xehz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37708 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUj2-0001hX-AN for patch@linaro.org; Tue, 12 Oct 2021 23:14:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57146) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUI5-000525-1G for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:50 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:46689) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUI1-0005D8-UM for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:48 -0400 Received: by mail-pl1-x630.google.com with SMTP id 21so785554plo.13 for ; Tue, 12 Oct 2021 19:46:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=O7p/UQX85gsSrL9h3Ho/u9/oHHasfkLJHADwG/5kd8Q=; b=fHs3XehzsGDqCr8ErW7D8aaZ0wYaIj2GHZaxrSkfE5rfa9uGZg6SC24C/3Hbx+rtt4 hzWnKUaOirUFhwuJLD/sOSupqsZrLsTUawW+p4xEZ2MJFtxTneQnbtR+Kz5hqkQp9W0u YrA+CAm/QDzkjJawmh6tWRJA7CaBrGHc3DITt6XFax8IqkHtJylLpzFN6tEDaTZHipSe C+Ec3fFy/DgZsUqG1BfCXT3OKP27kRGolA/Rug5KMroY1AGLyNO7JD8fdjvasjQHnF1f CdafEchjdu01eY+abVzPqjPcCHSIMWM+3Pv+8CIjJQZLE6Bw9Ct9Ex02q2hNr7NXy8kX DKlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O7p/UQX85gsSrL9h3Ho/u9/oHHasfkLJHADwG/5kd8Q=; b=rmWYlyBAGmj3rn92QlW3Fiiwxle3SIdTNN6dc+z8g+ipejp21xus4IJO2GCwTVgIS6 vHUJHm9qDsKYmO3NYyo5Pvzas4GaZ55Z/ypqMcDQMv6JWKUKZB2FA5uH3izZRDjPf+EM 2iOOV73PRSQMubRSCofHzBRYXaxyh72LoDmLiD+zRB6a1wJspYYwX0MFYT8n0Uy8xiFh E/jMiEx/NDEHPDVwp3NhvQG1qLj+a0Igo89BzQdM78IqZ6kNKM1oF30XVAohRaBZeqpA bFPpkx2dm5If3pSVk/hgC6rCz/bd15yFLeSvPhaT0v+JSWwmEBWOCHiGKp2RtghrXrY9 mALA== X-Gm-Message-State: AOAM531/byOzD1OvZgi85iLrNNJp4NFVXS8GZCOjbHdgvxcSoU2yuf70 z3HYjPBDfFwAFRginePO2BjeI8DHmj82lg== X-Received: by 2002:a17:90a:c081:: with SMTP id o1mr10645683pjs.24.1634093204660; Tue, 12 Oct 2021 19:46:44 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 35/48] target/alpha: Reorg fp memory operations Date: Tue, 12 Oct 2021 19:45:54 -0700 Message-Id: <20211013024607.731881-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Pass in the context to each mini-helper, instead of an incorrectly named "flags". Separate gen_load_fp and gen_store_fp, away from the integer helpers. Signed-off-by: Richard Henderson --- target/alpha/translate.c | 83 +++++++++++++++++++++++++++------------- 1 file changed, 57 insertions(+), 26 deletions(-) -- 2.25.1 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index b034206688..bfdd485508 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -267,30 +267,47 @@ static inline DisasJumpType gen_invalid(DisasContext *ctx) return gen_excp(ctx, EXCP_OPCDEC, 0); } -static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags) +static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, t1, flags, MO_LEUL); - gen_helper_memory_to_f(t0, tmp32); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + gen_helper_memory_to_f(dest, tmp32); tcg_temp_free_i32(tmp32); } -static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags) +static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv tmp = tcg_temp_new(); - tcg_gen_qemu_ld_i64(tmp, t1, flags, MO_LEQ); - gen_helper_memory_to_g(t0, tmp); + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + gen_helper_memory_to_g(dest, tmp); tcg_temp_free(tmp); } -static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags) +static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, t1, flags, MO_LEUL); - gen_helper_memory_to_s(t0, tmp32); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + gen_helper_memory_to_s(dest, tmp32); tcg_temp_free_i32(tmp32); } +static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr) +{ + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ); +} + +static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, + void (*func)(DisasContext *, TCGv, TCGv)) +{ + /* Loads to $f31 are prefetches, which we can treat as nops. */ + if (likely(ra != 31)) { + TCGv addr = tcg_temp_new(); + tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); + func(ctx, cpu_fir[ra], addr); + tcg_temp_free(addr); + } +} + static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags) { tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LESL); @@ -338,30 +355,44 @@ static inline void gen_load_mem(DisasContext *ctx, tcg_temp_free(tmp); } -static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags) +static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); - gen_helper_f_to_memory(tmp32, t0); - tcg_gen_qemu_st_i32(tmp32, t1, flags, MO_LEUL); + gen_helper_f_to_memory(tmp32, addr); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); tcg_temp_free_i32(tmp32); } -static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags) +static void gen_stg(DisasContext *ctx, TCGv src, TCGv addr) { TCGv tmp = tcg_temp_new(); - gen_helper_g_to_memory(tmp, t0); - tcg_gen_qemu_st_i64(tmp, t1, flags, MO_LEQ); + gen_helper_g_to_memory(tmp, src); + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ); tcg_temp_free(tmp); } -static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags) +static void gen_sts(DisasContext *ctx, TCGv src, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); - gen_helper_s_to_memory(tmp32, t0); - tcg_gen_qemu_st_i32(tmp32, t1, flags, MO_LEUL); + gen_helper_s_to_memory(tmp32, src); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); tcg_temp_free_i32(tmp32); } +static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr) +{ + tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ); +} + +static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, + void (*func)(DisasContext *, TCGv, TCGv)) +{ + TCGv addr = tcg_temp_new(); + tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); + func(ctx, load_fpr(ctx, ra), addr); + tcg_temp_free(addr); +} + static inline void gen_store_mem(DisasContext *ctx, void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags), @@ -2776,42 +2807,42 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) case 0x20: /* LDF */ REQUIRE_FEN; - gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0); + gen_load_fp(ctx, ra, rb, disp16, gen_ldf); break; case 0x21: /* LDG */ REQUIRE_FEN; - gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0); + gen_load_fp(ctx, ra, rb, disp16, gen_ldg); break; case 0x22: /* LDS */ REQUIRE_FEN; - gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0); + gen_load_fp(ctx, ra, rb, disp16, gen_lds); break; case 0x23: /* LDT */ REQUIRE_FEN; - gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0); + gen_load_fp(ctx, ra, rb, disp16, gen_ldt); break; case 0x24: /* STF */ REQUIRE_FEN; - gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0); + gen_store_fp(ctx, ra, rb, disp16, gen_stf); break; case 0x25: /* STG */ REQUIRE_FEN; - gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0); + gen_store_fp(ctx, ra, rb, disp16, gen_stg); break; case 0x26: /* STS */ REQUIRE_FEN; - gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0); + gen_store_fp(ctx, ra, rb, disp16, gen_sts); break; case 0x27: /* STT */ REQUIRE_FEN; - gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0); + gen_store_fp(ctx, ra, rb, disp16, gen_stt); break; case 0x28: /* LDL */ From patchwork Wed Oct 13 02:45:55 2021 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id 127si13049852ybg.106.2021.10.12.20.13.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 20:13:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xc7Ks3+l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33488 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUhu-00078L-76 for patch@linaro.org; Tue, 12 Oct 2021 23:13:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57182) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUI7-00055b-7M for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:51 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:51081) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUI4-0005Dd-2U for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:50 -0400 Received: by mail-pj1-x102d.google.com with SMTP id k23so1113286pji.0 for ; Tue, 12 Oct 2021 19:46:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Vm1+Nxqkm8aDvZQThXFEpUZIhlx3FOc7BMXpuaOc1Q8=; b=xc7Ks3+lCpaP913FtEZPnaK9DKS36FoxxS5HakJwqJUR055xGDrpXGQVPC5WsJ+Onw itI3QEu6jwLDXIjhc8pRo/qcsC0nBahEIXJZH0/UAo8ZkAJ982b9af3TmzHZPX8Kpt9N AWrvmlDQFlso+hWktEVeMYzFyVK6W8m0obEriWzRgclyALiPxnzr8l3vEDaem346d6t1 T7g8Pqu5gq51DGCRBE9jCeo85B8TAWRxI8DD85rl6zktl+uPrzlTDr37jTsr3vKPCcpq LeW00VWhy4nJ3n4eylxBKvnZwBWdfCmdCc+ohcRuMraYMdTtjFXLSAo3WOnlZIvx45E9 qecw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Vm1+Nxqkm8aDvZQThXFEpUZIhlx3FOc7BMXpuaOc1Q8=; b=FFqBJ6NCxF+9dF1cJqbMJvQRpI8N6+xDFe9NrcDYtbFF1JFnwj5BD27JraocWinU3l QmOup9GCAToQ4s6GHxjjcZApV9ZUUna/LHS60nS+0kS30ZZk0egU5jGXohhahf8g3GIo gVZsIg3CbAVO2cQitKaewXiGxohBOruXhJRqIBciU9XJWl3klJG7xXvmybObuOhEXWp5 SD3Dv1ecZVqo5G8SqLkVG0e/s//45ODEg+ZjPSzLlQLv1HosKR4DsBWvEyJLAp1C08OM bjIW+7d7tBvjs+VoSHUn99+I1xKsXYBPMF+nl5y5GtSPj4fGhuKgf9xrPLjfdJ+eRBaY 5USw== X-Gm-Message-State: AOAM5336yrbhssoVd6Ow+weZTnv9QXhSueDtlgagtKLi49Q3Nw2zCfme ZyChUsZ84ax5u8WHb8aegjHj96imNydj8Q== X-Received: by 2002:a17:90a:6b0a:: with SMTP id v10mr10383617pjj.130.1634093205466; Tue, 12 Oct 2021 19:46:45 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 36/48] target/alpha: Reorg integer memory operations Date: Tue, 12 Oct 2021 19:45:55 -0700 Message-Id: <20211013024607.731881-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Pass in the MemOp instead of a callback. Drop the fp argument; add a locked argument. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/alpha/translate.c | 104 +++++++++++++++------------------------ 1 file changed, 40 insertions(+), 64 deletions(-) -- 2.25.1 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index bfdd485508..0eee3a1bcc 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -308,27 +308,10 @@ static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, } } -static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags) +static void gen_load_int(DisasContext *ctx, int ra, int rb, int32_t disp16, + MemOp op, bool clear, bool locked) { - tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LESL); - tcg_gen_mov_i64(cpu_lock_addr, t1); - tcg_gen_mov_i64(cpu_lock_value, t0); -} - -static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags) -{ - tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LEQ); - tcg_gen_mov_i64(cpu_lock_addr, t1); - tcg_gen_mov_i64(cpu_lock_value, t0); -} - -static inline void gen_load_mem(DisasContext *ctx, - void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, - int flags), - int ra, int rb, int32_t disp16, bool fp, - bool clear) -{ - TCGv tmp, addr, va; + TCGv addr, dest; /* LDQ_U with ra $31 is UNOP. Other various loads are forms of prefetches, which we can treat as nops. No worries about @@ -337,22 +320,20 @@ static inline void gen_load_mem(DisasContext *ctx, return; } - tmp = tcg_temp_new(); - addr = load_gpr(ctx, rb); - - if (disp16) { - tcg_gen_addi_i64(tmp, addr, disp16); - addr = tmp; - } + addr = tcg_temp_new(); + tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { - tcg_gen_andi_i64(tmp, addr, ~0x7); - addr = tmp; + tcg_gen_andi_i64(addr, addr, ~0x7); } - va = (fp ? cpu_fir[ra] : ctx->ir[ra]); - tcg_gen_qemu_load(va, addr, ctx->mem_idx); + dest = ctx->ir[ra]; + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, op); - tcg_temp_free(tmp); + if (locked) { + tcg_gen_mov_i64(cpu_lock_addr, addr); + tcg_gen_mov_i64(cpu_lock_value, dest); + } + tcg_temp_free(addr); } static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr) @@ -393,30 +374,21 @@ static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, tcg_temp_free(addr); } -static inline void gen_store_mem(DisasContext *ctx, - void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, - int flags), - int ra, int rb, int32_t disp16, bool fp, - bool clear) +static void gen_store_int(DisasContext *ctx, int ra, int rb, int32_t disp16, + MemOp op, bool clear) { - TCGv tmp, addr, va; + TCGv addr, src; - tmp = tcg_temp_new(); - addr = load_gpr(ctx, rb); - - if (disp16) { - tcg_gen_addi_i64(tmp, addr, disp16); - addr = tmp; - } + addr = tcg_temp_new(); + tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { - tcg_gen_andi_i64(tmp, addr, ~0x7); - addr = tmp; + tcg_gen_andi_i64(addr, addr, ~0x7); } - va = (fp ? load_fpr(ctx, ra) : load_gpr(ctx, ra)); - tcg_gen_qemu_store(va, addr, ctx->mem_idx); + src = load_gpr(ctx, ra); + tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, op); - tcg_temp_free(tmp); + tcg_temp_free(addr); } static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb, @@ -1511,30 +1483,30 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) case 0x0A: /* LDBU */ REQUIRE_AMASK(BWX); - gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0); + gen_load_int(ctx, ra, rb, disp16, MO_UB, 0, 0); break; case 0x0B: /* LDQ_U */ - gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1); + gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 1, 0); break; case 0x0C: /* LDWU */ REQUIRE_AMASK(BWX); - gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0); + gen_load_int(ctx, ra, rb, disp16, MO_LEUW, 0, 0); break; case 0x0D: /* STW */ REQUIRE_AMASK(BWX); - gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0); + gen_store_int(ctx, ra, rb, disp16, MO_LEUW, 0); break; case 0x0E: /* STB */ REQUIRE_AMASK(BWX); - gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0); + gen_store_int(ctx, ra, rb, disp16, MO_UB, 0); break; case 0x0F: /* STQ_U */ - gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1); + gen_store_int(ctx, ra, rb, disp16, MO_LEQ, 1); break; case 0x10: @@ -2489,11 +2461,15 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) break; case 0x2: /* Longword physical access with lock (hw_ldl_l/p) */ - gen_qemu_ldl_l(va, addr, MMU_PHYS_IDX); + tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL); + tcg_gen_mov_i64(cpu_lock_addr, addr); + tcg_gen_mov_i64(cpu_lock_value, va); break; case 0x3: /* Quadword physical access with lock (hw_ldq_l/p) */ - gen_qemu_ldq_l(va, addr, MMU_PHYS_IDX); + tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEQ); + tcg_gen_mov_i64(cpu_lock_addr, addr); + tcg_gen_mov_i64(cpu_lock_value, va); break; case 0x4: /* Longword virtual PTE fetch (hw_ldl/v) */ @@ -2846,27 +2822,27 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) break; case 0x28: /* LDL */ - gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0); + gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 0); break; case 0x29: /* LDQ */ - gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0); + gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 0, 0); break; case 0x2A: /* LDL_L */ - gen_load_mem(ctx, &gen_qemu_ldl_l, ra, rb, disp16, 0, 0); + gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 1); break; case 0x2B: /* LDQ_L */ - gen_load_mem(ctx, &gen_qemu_ldq_l, ra, rb, disp16, 0, 0); + gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 0, 1); break; case 0x2C: /* STL */ - gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0); + gen_store_int(ctx, ra, rb, disp16, MO_LEUL, 0); break; case 0x2D: /* STQ */ - gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0); + gen_store_int(ctx, ra, rb, disp16, MO_LEQ, 0); break; case 0x2E: /* STL_C */ From patchwork Wed Oct 13 02:45:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515703 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6091946ime; Tue, 12 Oct 2021 20:09:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzjo4oA5SGRY2Cde9HF3hNUOPTY4eoqQB1opA51QdMH2QK6HhXHrbC/9PGbVdfV6QgtrdaN X-Received: by 2002:a05:622a:1492:: with SMTP id t18mr19418065qtx.229.1634094571963; Tue, 12 Oct 2021 20:09:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634094571; cv=none; d=google.com; s=arc-20160816; b=qHXMv1f7VKE1it+7MHav0AbOxI+/x5VNM7zBBTCEJYSmCcrmR431aigvYAPFNyFsh5 L/lgI1Ix9oLu0ttCuloA0SJIT2bEBvS+XhMFH/G7zAQ6k7s6yfjWiuwWH3/WZ19uyojS +RErNElMGg1JkI9dsM7FLxCJUk053arMxvZ7Vhv8Y/MxyucU9AoatARTpAlu+tXewYHe RbM6v/S4EbwNo4oq16Z13esoiLKk6P7mVE9RhdDx1NM9hThl+N4prv/FObF0vUCRZDPQ hrjmYeq/UmEGwK4RHvR0uKuuxKpZoFs79L94FWQ272jtQ7VO/DPjsMgvIrg+eCdL5bdY 3dlw== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id a12si8899443qtm.217.2021.10.12.20.09.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 20:09:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q9ZGXrOx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53284 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUe3-00010X-9C for patch@linaro.org; Tue, 12 Oct 2021 23:09:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57168) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUI5-000526-Td for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:50 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:40714) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUI4-0005E5-2i for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:49 -0400 Received: by mail-pf1-x435.google.com with SMTP id o133so1148151pfg.7 for ; Tue, 12 Oct 2021 19:46:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LZhYgL8dMORR9XrCtBiZKLLwKJx6Df6PYPQ06N0xS2k=; b=q9ZGXrOxdxcXJJRixktzA2UIoPUK1bQ6+D4NdYiHlELlHiGUzoL358i5HfGD4KWrhG zthyLlrMsRvm0kavODDuM/t5+iPHMEZaLLEfrPFnGjN69iMMey1ID5minTkeVbhtisdp F0bkIWJXux6mEO2+pFyiY/Wcj/pA5JQKatzGFdJsRTe0VGHq7wxkVzlW+/Qz6TJxjev/ ylQN0/M2lacG96qr/PfiyVGLOsXiVZv0Bv0p2x4XkrTUMa4/+d+FrMoYhfLz4t7H2eNF 0ExCGMh/wB8bR596aTGaDsoY5gq//OoXPrsBi+3kZ16RJkZtgcqhOpyPyraA4vghRr13 H0Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LZhYgL8dMORR9XrCtBiZKLLwKJx6Df6PYPQ06N0xS2k=; b=iPJ9tL04GryL1UAS+WSnX8z1FMpFV+81/RxvINtPE6otBBb3/49YKdxY+4nfUdaOf3 0qhSmQG5YqquU2yMEuMJh6LDsbp4U+9zcas3XG/mak3K7y7dom6EvXXv0ZzHC4y2qDpI jxgtv8UFojUVZ+CJGR6ySxjyPovkYXx4PiB72Hx9ex8dvzI51rMjGoGYLBKScdt+1w63 ljma3PMbC2hR8ApDHP/QMzDY9FF75tVwVfhJUvFQku+4eLm9iar7RfCO1DuwVOSJAfi4 ArmRYlFpCSME3nG3nLV3MceSzfXxvzUOjgIHePrU59qtctYVguf+jZjoSU4FkreolA/a eJrg== X-Gm-Message-State: AOAM533YOVAWYGBlhrQ65KZwa0FkKykfiA3yfjs/Rzo2akuYAaiDIA0y /BBUJckrapQF6i/6mB4+wG3qfRyyolQwfg== X-Received: by 2002:a63:7d42:: with SMTP id m2mr25765641pgn.349.1634093206405; Tue, 12 Oct 2021 19:46:46 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 37/48] target/alpha: Implement prctl_unalign_sigbus Date: Tue, 12 Oct 2021 19:45:56 -0700 Message-Id: <20211013024607.731881-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson --- linux-user/alpha/target_prctl.h | 2 +- target/alpha/cpu.h | 5 +++++ target/alpha/translate.c | 31 ++++++++++++++++++++++--------- 3 files changed, 28 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prctl.h index eb53b31ad5..5629ddbf39 100644 --- a/linux-user/alpha/target_prctl.h +++ b/linux-user/alpha/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index d49cc36d07..da5ccf7b63 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -386,6 +386,8 @@ enum { #define ENV_FLAG_TB_MASK \ (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN) +#define TB_FLAG_UNALIGN (1u << 1) + static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) { int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX; @@ -468,6 +470,9 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc, *pc = env->pc; *cs_base = 0; *pflags = env->flags & ENV_FLAG_TB_MASK; +#ifdef CONFIG_USER_ONLY + *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif } #ifdef CONFIG_USER_ONLY diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 0eee3a1bcc..2656037b8b 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -45,7 +45,9 @@ typedef struct DisasContext DisasContext; struct DisasContext { DisasContextBase base; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + MemOp unalign; +#else uint64_t palbr; #endif uint32_t tbflags; @@ -68,6 +70,12 @@ struct DisasContext { TCGv sink; }; +#ifdef CONFIG_USER_ONLY +#define UNALIGN(C) (C)->unalign +#else +#define UNALIGN(C) 0 +#endif + /* Target-specific return values from translate_one, indicating the state of the TB. Note that DISAS_NEXT indicates that we are not exiting the TB. */ @@ -270,7 +278,7 @@ static inline DisasJumpType gen_invalid(DisasContext *ctx) static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_f(dest, tmp32); tcg_temp_free_i32(tmp32); } @@ -278,7 +286,7 @@ static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr) static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv tmp = tcg_temp_new(); - tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); gen_helper_memory_to_g(dest, tmp); tcg_temp_free(tmp); } @@ -286,14 +294,14 @@ static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr) static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_s(dest, tmp32); tcg_temp_free_i32(tmp32); } static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr) { - tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -324,6 +332,8 @@ static void gen_load_int(DisasContext *ctx, int ra, int rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else if (!locked) { + op |= UNALIGN(ctx); } dest = ctx->ir[ra]; @@ -340,7 +350,7 @@ static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); gen_helper_f_to_memory(tmp32, addr); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } @@ -348,7 +358,7 @@ static void gen_stg(DisasContext *ctx, TCGv src, TCGv addr) { TCGv tmp = tcg_temp_new(); gen_helper_g_to_memory(tmp, src); - tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); tcg_temp_free(tmp); } @@ -356,13 +366,13 @@ static void gen_sts(DisasContext *ctx, TCGv src, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); gen_helper_s_to_memory(tmp32, src); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr) { - tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -383,6 +393,8 @@ static void gen_store_int(DisasContext *ctx, int ra, int rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else { + op |= UNALIGN(ctx); } src = load_gpr(ctx, ra); @@ -2942,6 +2954,7 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) #ifdef CONFIG_USER_ONLY ctx->ir = cpu_std_ir; + ctx->unalign = (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->palbr = env->palbr; ctx->ir = (ctx->tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_ir); From patchwork Wed Oct 13 02:45:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515706 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6094476ime; Tue, 12 Oct 2021 20:13:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzS2Ll06cnJ69bLgjLvpG/l2r7nCO6bdoCbBvFml0Qgx4DcjkcwlFUNcWy6fjLxAGMHNN+M X-Received: by 2002:a25:4607:: with SMTP id t7mr30466186yba.173.1634094809224; Tue, 12 Oct 2021 20:13:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634094809; cv=none; d=google.com; s=arc-20160816; b=mITf037b6rx/wSemsHUxWcjC1AXjDgjeNWyLDIsTmcDL2Z6FWSVU2SH/O4GJBjed74 qyvvl1uzQlLyb2pcKThrqJRTFD/0RIOI35r1nFlmwRPyHDryjQGwLDMeJI6fMgw10MFU X8H4XvowFKo/sbhVu0gEkqT3YDcgjik7PPDzS4oABzNvAXLO7UE4dJbQndXkHtflAH/f XbekRcp3XSXQbQyfP1ekGLxDmjJg/8hESLoag0SAPCU/d+oc8IgtvKdFSc87jnMbDe2m O7USNkHlcvL7JZZV7IvN26ofPPp9lqtwgGt+t8ZUmVvDw73eTZYj/56HqrnE7u9q9GE3 66xQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FDh0xRrxNKle4pRoEftfiIirEtPOD6rcCJZUiwu3wG8=; b=pcOeWHQnxpQjscD8xDljsnHEWb3lOEbBSIB3qCwEC4C/SuryJ58qaHIQ+TuGfZRv1Q 08WwfdYJrysguootI+zirWcjOvlCv3bbnMH0KE7p+qNr/67JFG0qksjOMT/34y3Iz5TD znPTR1OSA4FemL6ZP9AF8FmhAZgEQSauYl279lkWbKIZcR3t2mch8Ea5hsmZonbWWlgb k6oNgQp2QymqI+blcr4wcARbJxKc3Xj72PSzC3hVzQSAVTK92WVrWdq8r4wSPQm/uggo LScppQQE8GpbgVzAfJVxgrgVTV2DC4kSLAqAVzF8c2Vot4Y6kAHDegOizkBC2eY+F6Pd mtvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FZvQI+F+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s4si14479456ybm.143.2021.10.12.20.13.29 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 20:13:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FZvQI+F+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUhs-00073a-L9 for patch@linaro.org; Tue, 12 Oct 2021 23:13:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57170) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUI6-00052N-CT for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:50 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:39650) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUI4-0005Er-OX for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:50 -0400 Received: by mail-pl1-x630.google.com with SMTP id c4so809552pls.6 for ; Tue, 12 Oct 2021 19:46:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FDh0xRrxNKle4pRoEftfiIirEtPOD6rcCJZUiwu3wG8=; b=FZvQI+F+Ljxp+PFFWKh+4ok6rngYX5aygLyoo2uRJHB4ByTZoEipvFmLEiJrTYjVU2 LkcVKAEM5GuSyfVjidpli1PJPCH/Te1jESpdov4WYEVvoM5ErtREitGuu67YmAQRYfCs w2yokpSBQNOYRUOMzVPSDvy/Z39modyxASZLgevEjB1aBVXYdA+1P0+csClRC7r8RQbk 3sjgvB+b5/wA3Dq4UpVb4tBjjSSqjJO5AsJSzzxVtgKxFPZWQtwhBp4tsZFjqNVXwCt+ SzcJM6dIbka3P6LzVKL6icRaC+MJNIyo0G5Jtigogf1sjmlDdkJ2nuDaRTGymnpI9m0d 2HXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FDh0xRrxNKle4pRoEftfiIirEtPOD6rcCJZUiwu3wG8=; b=dGn3ETQEb+4GU5b6slpc1BUjHRYvij2ND+/EUznxTBfgwFTLdmZns6t9xZZNV1Su0S kDT8FitzuxSNhQwxjfmDkeK6iOyv4RrCkR7iWszg7I/H6BNGF6QjTcqHOjjs+2OhbQS7 Ni4Akx1jdu9vRAbw77CLErdBR5IE2Xdh2GdOCWG8t2UebtsEflYX/TzBdJE6E/aEmEe5 NQjR63/O0nYPm/dvUm+f17/bka7kKhGn0eLfAvdXGcbkm3vjuUAMI6mK0JH5gMlI/5LR sImq1yO13s1iAnbScodXq8OFzpboXJDv5pdyqCHvx81MZgi4+wAYqPFveOwajZ05wdLz pYWg== X-Gm-Message-State: AOAM532zZu5ElLoN+HuHHognb8elwJ42PWFo1nhO3qTrTxONDrO68Fh3 KHS9ewXrHnLcl7B72tTvgj4TJuOuKVkQcw== X-Received: by 2002:a17:90b:3687:: with SMTP id mj7mr10599879pjb.196.1634093207309; Tue, 12 Oct 2021 19:46:47 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 38/48] target/hppa: Implement prctl_unalign_sigbus Date: Tue, 12 Oct 2021 19:45:57 -0700 Message-Id: <20211013024607.731881-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson --- linux-user/hppa/target_prctl.h | 2 +- target/hppa/cpu.h | 5 ++++- target/hppa/translate.c | 19 +++++++++++++++---- 3 files changed, 20 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h index eb53b31ad5..5629ddbf39 100644 --- a/linux-user/hppa/target_prctl.h +++ b/linux-user/hppa/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 294fd7297f..45fd338b02 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -259,12 +259,14 @@ static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, return hppa_form_gva_psw(env->psw, spc, off); } -/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them. +/* + * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the * same value. */ #define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 +#define TB_FLAG_UNALIGN 0x400 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, target_ulong *cs_base, @@ -279,6 +281,7 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, #ifdef CONFIG_USER_ONLY *pc = env->iaoq_f & -4; *cs_base = env->iaoq_b & -4; + flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; #else /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ flags |= env->psw & (PSW_W | PSW_C | PSW_D); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c3698cf067..fdaa2b12b8 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -272,8 +272,18 @@ typedef struct DisasContext { int mmu_idx; int privilege; bool psw_n_nonzero; + +#ifdef CONFIG_USER_ONLY + MemOp unalign; +#endif } DisasContext; +#ifdef CONFIG_USER_ONLY +#define UNALIGN(C) (C)->unalign +#else +#define UNALIGN(C) 0 +#endif + /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ static int expand_sm_imm(DisasContext *ctx, int val) { @@ -1477,7 +1487,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx == MMU_PHYS_IDX); - tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1495,7 +1505,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx == MMU_PHYS_IDX); - tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1513,7 +1523,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx == MMU_PHYS_IDX); - tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1531,7 +1541,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx == MMU_PHYS_IDX); - tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -4110,6 +4120,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->mmu_idx = MMU_USER_IDX; ctx->iaoq_f = ctx->base.pc_first | MMU_USER_IDX; ctx->iaoq_b = ctx->base.tb->cs_base | MMU_USER_IDX; + ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX); From patchwork Wed Oct 13 02:45:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515711 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6097172ime; Tue, 12 Oct 2021 20:18:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwEQ77lm/Kf2JCcsQGg4i0plm2tEfQWeI80fflBHNrpS1dUYvFKXTRSv03/9Ovf9dRBLSGl X-Received: by 2002:a25:1d46:: with SMTP id d67mr33414475ybd.539.1634095092089; Tue, 12 Oct 2021 20:18:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634095092; cv=none; d=google.com; s=arc-20160816; b=IVSwAaoOr6pF6XWmyM/xpZznLYBGQ88snCg4d8LBTKs28TZkx2aMQ7AAfctAm2ARKO G2jUzFsUb5JYPjEc68WWrpdhP9Cz7t7UTOgSk2PKBpYee9uV9lDE5daut/XQMfPki5AC RAhWr/mmTrGIV7wzcwzFCz7EqHkjmzJtUrfte/zb0XuhAB5biRxw1WyimmO2w8n9ZgNl RMQJ6xf9G3pOiTNeo5+Ccf5HEmHlrJMuMY5olW/AKtQ5U/4ZEOsZLGAGlGqvFKiNUk9f X+UVvLvtd1AnAo35K8Nnpn53Wzo5a6vEcSBdsRBee5A+rSH/SfXW93ZaaPILiGRAF4Jc +/ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QXtWYu3k26efdjnMd2Pt42jkFdW4b3H42VfJHmp983k=; b=uBE2wO6GQ0ZNnCEadTgAi8hfo/DTC4jrW0HTSVxtijqKRPEgjY8EX+vdoZvEKFzK7l CW6p9XGfJFnQjYgfjWRIoiFZkbvRkKIwxKPu6Cz5Pvv6pwIfYyDomx33QECA7Luuf0Sp EApgNC6yoVBCkGpQ7K41IM/nCY8R2fCWc03vs+Dg8RmB3yj6oBLv8jRfwtpabieO7hiM 1svFH+4zkNSzYdl+agy+/tiYGpLDDr/LPh+Xvtys4Wtd489mI390z/u9MQoCp1jsvOYY GyhhwKN+NWOsJHFiYHqxZ3WsGPavu98XwsJhNF+zqZ1xqJORDiBbLdG4PeXCvoaDkJz3 EfjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wl9QVGBw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z6si5943888ybm.332.2021.10.12.20.18.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Oct 2021 20:18:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wl9QVGBw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45674 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maUmR-0007ES-G3 for patch@linaro.org; Tue, 12 Oct 2021 23:18:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57184) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maUI7-000578-NM for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:51 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:33681) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maUI5-0005GD-HZ for qemu-devel@nongnu.org; Tue, 12 Oct 2021 22:46:51 -0400 Received: by mail-pf1-x42b.google.com with SMTP id t184so298558pfd.0 for ; Tue, 12 Oct 2021 19:46:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QXtWYu3k26efdjnMd2Pt42jkFdW4b3H42VfJHmp983k=; b=wl9QVGBweAtHsJWe6CaaLNSyPhANbjnrNKE+c7DoFgZF8z5AWWiMQd6Z5pm4GNycG3 CjJ8G7TH5LU4P77tc1wgfxxYcV8FRrz6Sol3LP5yYhZs2dBjyb7s49N3NlM4Kpdw3KEd w6yKLrNSv1sBi1BoiHgJgg95DtZAfyDWTwP4PjuB50nZbQb5CZD4RgP4hFz0DyqQHbsS k7EtY8atb3LbPOcGUXrLB2orf6KLlH2ETijFjP258e1rGen9ndQVP+7hZxM8y7RLUgGy p6e17uqizTHxJGn1aBVAH6Xf3mtAjeJ08CJQZa9wT9SZWHYDFneNwWAj8QxAPixlCqLj 2mxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QXtWYu3k26efdjnMd2Pt42jkFdW4b3H42VfJHmp983k=; b=0aAr2r9ut8s6XYiZBSGmmiceyRvTxu9iu9rpeZr8zCgV/nM1KC05zLJ/SiJdmNcqM7 8xIo1Cx4aHUTMenydbkZSc8Y9ExUaOJCwoD9lXm0CjTMg/biYFYhG63GBzEWI4aaK3Bt O83yJ0jGI2Yal5PlVWX3e8YxNtZYWB6Q7xE15XsV0flRzpoQC5L6fkXGxWTQqYTnXJSj z7V3lG+9V+Z+n9BP5DmpdrHsd6V67pVZTDQJF0340OTEyvGFji8YNkDrzRUK+/VvLxJk o3FrFrpsiVPnwwXQeVko9Mu+wNR/9XRK8dTlmb3FyFEdOnsWZ1v8EUfjWZiZpdBKqYXA LXeg== X-Gm-Message-State: AOAM532cprb77toHsyZIs5zhKmPdV0XBsd1nPH+8J2CKgmrosnYbm0Bk trnfzAqQnyhuSVRlKsq3vKf9CxO0SR1kkA== X-Received: by 2002:a63:2acb:: with SMTP id q194mr25851046pgq.59.1634093208105; Tue, 12 Oct 2021 19:46:48 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id qe17sm4855014pjb.39.2021.10.12.19.46.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 19:46:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 39/48] target/sh4: Implement prctl_unalign_sigbus Date: Tue, 12 Oct 2021 19:45:58 -0700 Message-Id: <20211013024607.731881-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. The Linux kernel does not handle all memory operations: no floating-point and no MAC. Signed-off-by: Richard Henderson --- linux-user/sh4/target_prctl.h | 2 +- target/sh4/cpu.h | 4 +++ target/sh4/translate.c | 50 ++++++++++++++++++++++++----------- 3 files changed, 39 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/linux-user/sh4/target_prctl.h b/linux-user/sh4/target_prctl.h index eb53b31ad5..5629ddbf39 100644 --- a/linux-user/sh4/target_prctl.h +++ b/linux-user/sh4/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 4cfb109f56..fb9dd9db2f 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -83,6 +83,7 @@ #define DELAY_SLOT_RTE (1 << 2) #define TB_FLAG_PENDING_MOVCA (1 << 3) +#define TB_FLAG_UNALIGN (1 << 4) #define GUSA_SHIFT 4 #ifdef CONFIG_USER_ONLY @@ -373,6 +374,9 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc, | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */ | (env->sr & (1u << SR_FD)) /* Bit 15 */ | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ +#ifdef CONFIG_USER_ONLY + *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif } #endif /* SH4_CPU_H */ diff --git a/target/sh4/translate.c b/target/sh4/translate.c index d363050272..7965db586f 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -50,8 +50,10 @@ typedef struct DisasContext { #if defined(CONFIG_USER_ONLY) #define IS_USER(ctx) 1 +#define UNALIGN(C) (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : 0) #else #define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD))) +#define UNALIGN(C) 0 #endif /* Target-specific values for ctx->base.is_jmp. */ @@ -499,7 +501,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -507,7 +510,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -562,19 +566,23 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_UB); return; case 0x2001: /* mov.w Rm,@Rn */ - tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, + MO_TEUW | UNALIGN(ctx)); return; case 0x2002: /* mov.l Rm,@Rn */ - tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, + MO_TEUL | UNALIGN(ctx)); return; case 0x6000: /* mov.b @Rm,Rn */ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB); return; case 0x6001: /* mov.w @Rm,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESW | UNALIGN(ctx)); return; case 0x6002: /* mov.l @Rm,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESL | UNALIGN(ctx)); return; case 0x2004: /* mov.b Rm,@-Rn */ { @@ -590,7 +598,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 2); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); } @@ -599,7 +608,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 4); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); } @@ -610,12 +620,14 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1); return; case 0x6005: /* mov.w @Rm+,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESW | UNALIGN(ctx)); if ( B11_8 != B7_4 ) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); return; case 0x6006: /* mov.l @Rm+,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESL | UNALIGN(ctx)); if ( B11_8 != B7_4 ) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); return; @@ -631,7 +643,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -639,7 +652,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -655,7 +669,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -663,7 +678,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -1257,7 +1273,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); - tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -1273,7 +1290,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); - tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, + MO_TESW | UNALIGN(ctx)); tcg_temp_free(addr); } return; From patchwork Wed Oct 13 02:45:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515710 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6096113ime; 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Signed-off-by: Richard Henderson --- linux-user/signal.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.25.1 diff --git a/linux-user/signal.c b/linux-user/signal.c index df2c8678d0..81c45bfce9 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -860,6 +860,9 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) cpu_loop_exit_sigsegv(cpu, guest_addr, access_type, maperr, pc); } else { sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + if (info->si_code == BUS_ADRALN) { + cpu_loop_exit_sigbus(cpu, guest_addr, access_type, pc); + } } sync_sig = true; From patchwork Wed Oct 13 02:46:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515713 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6097918ime; Tue, 12 Oct 2021 20:19:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwcdUaMhODtCp/FyiiXjX9HgMivpQhxeu3jkiqoAzARAOaeJc0MPhSsiTBHeNKcdN+1t+CL X-Received: by 2002:a25:2bc1:: with SMTP id r184mr31437097ybr.44.1634095160892; Tue, 12 Oct 2021 20:19:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634095160; cv=none; d=google.com; s=arc-20160816; b=0GakFsJlP0uZn9K//40UuHPgYMFL2zArmahH7XaQglwvfQslTzMgaiV+olia2ujWtS EKWlHZuN6QaPZ8nXePiIRoidAqE882KQ4uWcBm7n4RhE8pvMsEZ7auYkjl0JkPw9IzRD hicxf90VnFnB6hQQbqk+aNJtPXZeTyi/SH9vXgUUOgNpeRiHYIdF0ccyMD7SwTsmWVb4 m4fFzBxs1620ZuUrwAeaPoMDfERgqbjIaXqeakKlN3rNE/Qb352tHeYgakgpnsgYx22D F+YSkbUu10DITgvRIablWeu9Aw3REhMxqIj27Q842L0doFCRQbPlOTLS3BqZC7A178cy 9jzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dk0S43b6nxrquRYrbUsZ6pFDuF+19OrA7E9Ry0WMKCU=; b=yCxL0TFZJD3oT8JNty8owJX/O0jBcmR0rYTh+S6B1+LXfpez1bGHxpcBF5FbcARzlS /0XLOvir+JYDiaYkpx2IYDf6AGPVjl5rz6vwjHmuAvnYIQVkSgK8D7DZYND18YGZqJui Pc4z7cOqcuIz+f/6nn/I5OqfprARv8gx1pNFHNowHAgOSGapMussoceLGEkUd/647NdM 8+lwR3E8CgE2YJdpS1ADs9bMABc6fB/liV8oRrDtEV3jQjx55QD/UFV5dxiw+KCOfz9r WLwM3ylspjQCbs7cs8+nJqa4KuqLUOqCwgqazlpTYmMqymDXW3pMHbMHAetY7JbLd9We 3zKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ePbKVg7d; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index b1cfd36f29..61b492d89f 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2765,7 +2765,12 @@ void tcg_gen_lookup_and_goto_ptr(void) static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) { /* Trigger the asserts within as early as possible. */ - (void)get_alignment_bits(op); + unsigned a_bits = get_alignment_bits(op); + + /* Prefer MO_ALIGN+MO_XX over MO_ALIGN_XX+MO_XX */ + if (a_bits == (op & MO_SIZE)) { + op = (op & ~MO_AMASK) | MO_ALIGN; + } switch (op & MO_SIZE) { case MO_8: From patchwork Wed Oct 13 02:46:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515716 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6099181ime; Tue, 12 Oct 2021 20:21:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwiENgxZd6K2McgfBbv9tdQunc7ArLH2zO1k0Uk2nr5b76ljEeoDMFe5kUGxLIX6hOgVfmS X-Received: by 2002:a25:ae66:: with SMTP id g38mr31085656ybe.536.1634095301902; Tue, 12 Oct 2021 20:21:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634095301; cv=none; d=google.com; s=arc-20160816; b=deGMA9E0uP0Ov+V6KoTOxRkGUemBw2Uc9VCmIfvu5zB60P5bavoDUgdrewmR6BNJgj I0KmRZ5wxNBR5QrIJzzd7KqkykO1eyPxL/XGlMWxtK56OXswVOF7gwmYdb+0r8T0kluP A8rUJmNuPmzGEXrTTAy3mYW7E/m3c58roT40eYw1HZWs8425U8pzJuANJn6YSzhg0lJU QVtzYbTSipDx15znmpJDeY1i0F4x1nYPWIJJsRC+0j1hzGCkIPODVEwkynzKOdEKa+/k l3Kck2CMI6qKoL7oaUPNCBihMC1E2MNsrNU1o7o+VioxqTxxQIuXQjstfHvrNHfCYkDI soWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xDlNcMPX+4x4RTjp0DsPf/CfOh4YFwKmpEmxN1K7ZOw=; b=sE5tfmVXw/yCf2DMkwd8nwVSIGDCmGD0C5gEnh3BP5hhu0b3Aqy297086Tq4ZE8UMn AM7KwuH87CMMmTeO4lXKM6yIUo8PXG/HKO6Rv227xqt6tSUiFzcLN1ZO2EYDhRmLckQ3 0dSOI61MvJEVWL+Bj0W9a40IobqAH9VBERn0LXkXuxhVOSh01JNHq9Ip8BdtoZNkrlvg J9Y+PaNO1dx7pnt0lZ4YMVL7k5nYrYBJ44BTVBN/0TTzplrW59aJ6iQHJFkWpAUNSPpa yDBlfThox2HD7Hsu85hTtVTZiCgvWL/jU5WfV3ly2qzHJ215hQmXLbCgIqZUTWkc4qRp YnLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gFsk20Yd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 12 Oct 2021 19:49:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 42/48] tcg/i386: Support raising sigbus for user-only Date: Tue, 12 Oct 2021 19:46:01 -0700 Message-Id: <20211013024607.731881-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 - tcg/i386/tcg-target.c.inc | 103 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 98 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b00a6da293..3b2c9437a0 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -232,9 +232,7 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, #define TCG_TARGET_HAS_MEMORY_BSWAP have_movbe -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #define TCG_TARGET_NEED_POOL_LABELS #endif diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 84b109bb84..e073868d8f 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -22,6 +22,7 @@ * THE SOFTWARE. */ +#include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" #ifdef CONFIG_DEBUG_TCG @@ -421,8 +422,9 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) #define OPC_VZEROUPPER (0x77 | P_EXT) #define OPC_XCHG_ax_r32 (0x90) -#define OPC_GRP3_Ev (0xf7) -#define OPC_GRP5 (0xff) +#define OPC_GRP3_Eb (0xf6) +#define OPC_GRP3_Ev (0xf7) +#define OPC_GRP5 (0xff) #define OPC_GRP14 (0x73 | P_EXT | P_DATA16) /* Group 1 opcode extensions for 0x80-0x83. @@ -444,6 +446,7 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) #define SHIFT_SAR 7 /* Group 3 opcode extensions for 0xf6, 0xf7. To be used with OPC_GRP3. */ +#define EXT3_TESTi 0 #define EXT3_NOT 2 #define EXT3_NEG 3 #define EXT3_MUL 4 @@ -1606,8 +1609,6 @@ static void tcg_out_nopn(TCGContext *s, int n) } #if defined(CONFIG_SOFTMMU) -#include "../tcg-ldst.c.inc" - /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) */ @@ -1916,7 +1917,84 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); return true; } -#elif TCG_TARGET_REG_BITS == 32 +#else + +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo, + TCGReg addrhi, unsigned a_bits) +{ + unsigned a_mask = (1 << a_bits) - 1; + TCGLabelQemuLdst *label; + + /* + * We are expecting a_bits to max out at 7, so we can usually use testb. + * For i686, we have to use testl for %esi/%edi. + */ + if (a_mask <= 0xff && (TCG_TARGET_REG_BITS == 64 || addrlo < 4)) { + tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, addrlo); + tcg_out8(s, a_mask); + } else { + tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_TESTi, addrlo); + tcg_out32(s, a_mask); + } + + /* jne slow_path */ + tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + + label = new_ldst_label(s); + label->is_ld = is_ld; + label->addrlo_reg = addrlo; + label->addrhi_reg = addrhi; + label->raddr = tcg_splitwx_to_rx(s->code_ptr + 4); + label->label_ptr[0] = s->code_ptr; + + s->code_ptr += 4; +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + /* resolve label address */ + tcg_patch32(l->label_ptr[0], s->code_ptr - l->label_ptr[0] - 4); + + if (TCG_TARGET_REG_BITS == 32) { + int ofs = 0; + + tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); + ofs += 4; + + tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); + ofs += 4; + if (TARGET_LONG_BITS == 64) { + tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); + ofs += 4; + } + + tcg_out_pushi(s, (uintptr_t)l->raddr); + } else { + tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], + l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, (uintptr_t)l->raddr); + tcg_out_push(s, TCG_REG_RAX); + } + + /* "Tail call" to the helper, with the return address back inline. */ + tcg_out_jmp(s, (const void *)(l->is_ld ? helper_unaligned_ld + : helper_unaligned_st)); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +#if TCG_TARGET_REG_BITS == 32 # define x86_guest_base_seg 0 # define x86_guest_base_index -1 # define x86_guest_base_offset guest_base @@ -1950,6 +2028,7 @@ static inline int setup_guest_base_seg(void) return 0; } # endif +#endif #endif /* SOFTMMU */ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, @@ -2059,6 +2138,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) #if defined(CONFIG_SOFTMMU) int mem_index; tcg_insn_unit *label_ptr[2]; +#else + unsigned a_bits; #endif datalo = *args++; @@ -2081,6 +2162,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) add_qemu_ldst_label(s, true, is64, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else + a_bits = get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); + } + tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index, x86_guest_base_offset, x86_guest_base_seg, is64, opc); @@ -2148,6 +2234,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) #if defined(CONFIG_SOFTMMU) int mem_index; tcg_insn_unit *label_ptr[2]; +#else + unsigned a_bits; #endif datalo = *args++; @@ -2170,6 +2258,11 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) add_qemu_ldst_label(s, false, is64, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else + a_bits = get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); + } + tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index, x86_guest_base_offset, x86_guest_base_seg, opc); #endif From patchwork Wed Oct 13 02:46:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515708 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6095060ime; Tue, 12 Oct 2021 20:14:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw08VBz6VBjbBWHNiEqv9Y2HVnqGklbO7ttZS/jNs6PLAKpcKVU8cWbxoPiRJ02npUVEiWy X-Received: by 2002:a25:1b56:: with SMTP id b83mr31842594ybb.327.1634094868448; Tue, 12 Oct 2021 20:14:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634094868; cv=none; d=google.com; s=arc-20160816; b=nQCbbiU12ZRe8MVxlCw4/p/TCRwq/wubyJbf+DBlFSrV+L6W3hARYJnDMqdEtCKuGU 1Ye6wvLuNnlHORKGUAPf+T8wc5qDQ/tt/sVFSbPD0wKj8xI5gK2CjABEd+IIk/iMNmM3 qam+L7/yaYa5ZyHk5V2vLPv7Z8nC/VBtoxMw+78kJmkSxzfOAxdKyBkTBQFK9+CstF2o w4p0ILLDmm2bbZkpSELDTYAh4WD51ahGX516QY3/mshL5UCyT6Bly1ukRgdq1fQLXZUY 6dG4TbGohuUCuF8koEpT1d8SjPlo9QM6tUVcm/fUdvmj+lZynYfygO/M5ClMt+xxIBt1 zqBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AEDrLdND+QdiSTD7gFvQs8s8wQuCqaZx5PiFrbiHmIQ=; b=tg4qrQVZFqmYJqu5UJU+IwwSSTxd6l10pl31Y0RgEdKUTHmpAyVNJbG7Sb31eGKJOI /hNAdYwy9LVcXc8s2DsabnIA4utO1geYhSvSNukmJWDIOkgXmspfzhS8jpxMzOGttij+ kgOpFSV4eCjLbS/O3P5mvmvwH639ekg5PlgSRMRp6MfHfqgVESSybWBsaIdmTxRJDMqm lccn1ju1Hfm0xn/g4U+R2I/N9awcc6TMHhqb0vYJ6X4wRta0qDVZ0ErKV1ZMi1jHMJgY OcHE3vtsAfIBbTRZUeD8WKEuOdT6d5WV/KsrQ0wWbTbPCtFT4W9THGNznzCyvy5vszQ7 aAgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eqmAWoxt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 12 Oct 2021 19:49:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 43/48] tcg/aarch64: Support raising sigbus for user-only Date: Tue, 12 Oct 2021 19:46:02 -0700 Message-Id: <20211013024607.731881-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 - tcg/aarch64/tcg-target.c.inc | 91 +++++++++++++++++++++++++++++------- 2 files changed, 74 insertions(+), 19 deletions(-) -- 2.25.1 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 7a93ac8023..876af589ce 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -151,9 +151,7 @@ typedef enum { void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #define TCG_TARGET_NEED_POOL_LABELS #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 5edca8d44d..1f205f90b2 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -10,6 +10,7 @@ * See the COPYING file in the top-level directory for details. */ +#include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" #include "qemu/bitops.h" @@ -443,6 +444,7 @@ typedef enum { I3404_ANDI = 0x12000000, I3404_ORRI = 0x32000000, I3404_EORI = 0x52000000, + I3404_ANDSI = 0x72000000, /* Move wide immediate instructions. */ I3405_MOVN = 0x12800000, @@ -1328,8 +1330,9 @@ static void tcg_out_goto_long(TCGContext *s, const tcg_insn_unit *target) if (offset == sextract64(offset, 0, 26)) { tcg_out_insn(s, 3206, B, offset); } else { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target); - tcg_out_insn(s, 3207, BR, TCG_REG_TMP); + /* Choose X9 as a call-clobbered non-LR temporary. */ + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X9, (intptr_t)target); + tcg_out_insn(s, 3207, BR, TCG_REG_X9); } } @@ -1541,9 +1544,14 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d, } } -#ifdef CONFIG_SOFTMMU -#include "../tcg-ldst.c.inc" +static void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target) +{ + ptrdiff_t offset = tcg_pcrel_diff(s, target); + tcg_debug_assert(offset == sextract64(offset, 0, 21)); + tcg_out_insn(s, 3406, ADR, rd, offset); +} +#ifdef CONFIG_SOFTMMU /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * MemOpIdx oi, uintptr_t ra) */ @@ -1577,13 +1585,6 @@ static void * const qemu_st_helpers[MO_SIZE + 1] = { #endif }; -static inline void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target) -{ - ptrdiff_t offset = tcg_pcrel_diff(s, target); - tcg_debug_assert(offset == sextract64(offset, 0, 21)); - tcg_out_insn(s, 3406, ADR, rd, offset); -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { MemOpIdx oi = lb->oi; @@ -1714,15 +1715,58 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); } +#else +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_reg, + unsigned a_bits) +{ + unsigned a_mask = (1 << a_bits) - 1; + TCGLabelQemuLdst *label = new_ldst_label(s); + + label->is_ld = is_ld; + label->addrlo_reg = addr_reg; + + /* tst addr, #mask */ + tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask); + + label->label_ptr[0] = s->code_ptr; + + /* b.ne slow_path */ + tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); + + label->raddr = tcg_splitwx_to_rx(s->code_ptr); +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + if (!reloc_pc19(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { + return false; + } + + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_X1, l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); + + /* "Tail call" to the helper, with the return address back inline. */ + tcg_out_adr(s, TCG_REG_LR, l->raddr); + tcg_out_goto_long(s, (const void *)(l->is_ld ? helper_unaligned_ld + : helper_unaligned_st)); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} #endif /* CONFIG_SOFTMMU */ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, TCGReg data_r, TCGReg addr_r, TCGType otype, TCGReg off_r) { - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((memop & MO_BSWAP) == 0); - switch (memop & MO_SSIZE) { case MO_UB: tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r); @@ -1756,9 +1800,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop, TCGReg data_r, TCGReg addr_r, TCGType otype, TCGReg off_r) { - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((memop & MO_BSWAP) == 0); - switch (memop & MO_SIZE) { case MO_8: tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r); @@ -1782,6 +1823,10 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, { MemOp memop = get_memop(oi); const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32; + + /* Byte swapping is left to middle-end expansion. */ + tcg_debug_assert((memop & MO_BSWAP) == 0); + #ifdef CONFIG_SOFTMMU unsigned mem_index = get_mmuidx(oi); tcg_insn_unit *label_ptr; @@ -1792,6 +1837,10 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ + unsigned a_bits = get_alignment_bits(memop); + if (a_bits) { + tcg_out_test_alignment(s, true, addr_reg, a_bits); + } if (USE_GUEST_BASE) { tcg_out_qemu_ld_direct(s, memop, ext, data_reg, TCG_REG_GUEST_BASE, otype, addr_reg); @@ -1807,6 +1856,10 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, { MemOp memop = get_memop(oi); const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32; + + /* Byte swapping is left to middle-end expansion. */ + tcg_debug_assert((memop & MO_BSWAP) == 0); + #ifdef CONFIG_SOFTMMU unsigned mem_index = get_mmuidx(oi); tcg_insn_unit *label_ptr; @@ -1817,6 +1870,10 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ + unsigned a_bits = get_alignment_bits(memop); + if (a_bits) { + tcg_out_test_alignment(s, false, addr_reg, a_bits); + } if (USE_GUEST_BASE) { tcg_out_qemu_st_direct(s, memop, data_reg, TCG_REG_GUEST_BASE, otype, addr_reg); From patchwork Wed Oct 13 02:46:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515714 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6098807ime; Tue, 12 Oct 2021 20:20:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz0VajsJ/cPsLjdWcRCI+f2p8DzOVdFfQRxZbEoKz4tcJN5Y119RrE3cpbcufjD1A3+RFUE X-Received: by 2002:a25:1d46:: with SMTP id d67mr33425870ybd.539.1634095258549; Tue, 12 Oct 2021 20:20:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634095258; cv=none; d=google.com; s=arc-20160816; b=wfD25P9wme6hgdZXfeA1HwLnDsMruMsUy5DqkRGWvXp5ruKXFTiSGwMfJWW10paI2m kILQ0RPKFa9X0q7FPwDvQWUFt2SE3qQOfg2FI1CjAGvNCiEV/gKzlbQJqjpeVh1YkW2C owg/nBfFtWtKJhsEe3lXsYSjl1pLzjyjpg1NQjBud1/lrzPz3uNUB5I7LQW5Trq8SebI YrR2AV/RoF0P6O+hzZO5JFfzTQwnfV8KOjzhSxgs5VzPUNoxLifzIRujirE/4YZsXRKK +kSN8vPeYUi8s/IXMxmGxZONMpxjizoCVWuTND7LLt1TvqGBlb6JrKYTBkwMd4R4i9Vm a60w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=z9ajubKXxmD3iBvNRXK8ngdOfUUHM9YOJvnd1B/bzEU=; b=mTaZa8R0uiwds5Hxavu/p7hnUVdusNtWHQbN/uhSeloclAy3ze0xQWIc8X9O7s5tki BCCN985EV6b9sbam5VWJ1Yv0lsg8sztRUMFhh7vGd37oI1vYPrPZNhNyy7vZYdk3oxQ0 vOn2Y+F4GgCFzHXcJOVDTuHVi6QnfvWOpg8cbPerhtDVH3sUVHv16lqdvX2Sl9yYVH/8 ubm9QP1tHunLeOQTTMY8t85Ke8g64ui6hl4Sl5F/8z4jc+TR9T35toX/DhMzksNPtWTq cgUmiN+//XvAuKXy0aANNoY6zREP2vqO+v6pkQIGQy7KHmVO9LUuirXNq6fxkW0QcNpX V5Bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zCyjVORq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 12 Oct 2021 19:49:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 44/48] tcg/ppc: Support raising sigbus for user-only Date: Tue, 12 Oct 2021 19:46:03 -0700 Message-Id: <20211013024607.731881-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 2 - tcg/ppc/tcg-target.c.inc | 98 ++++++++++++++++++++++++++++++++++++---- 2 files changed, 90 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 0943192cde..c775c97b61 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -182,9 +182,7 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #define TCG_TARGET_NEED_POOL_LABELS #endif diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 3e4ca2be88..8a117e0665 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -24,6 +24,7 @@ #include "elf.h" #include "../tcg-pool.c.inc" +#include "../tcg-ldst.c.inc" /* * Standardize on the _CALL_FOO symbols used by GCC: @@ -1881,7 +1882,8 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, } } -static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) +static void tcg_out_call_int(TCGContext *s, int lk, + const tcg_insn_unit *target) { #ifdef _CALL_AIX /* Look through the descriptor. If the branch is in range, and we @@ -1892,7 +1894,7 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) if (in_range_b(diff) && toc == (uint32_t)toc) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc); - tcg_out_b(s, LK, tgt); + tcg_out_b(s, lk, tgt); } else { /* Fold the low bits of the constant into the addresses below. */ intptr_t arg = (intptr_t)target; @@ -1907,7 +1909,7 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs); tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP); - tcg_out32(s, BCCTR | BO_ALWAYS | LK); + tcg_out32(s, BCCTR | BO_ALWAYS | lk); } #elif defined(_CALL_ELF) && _CALL_ELF == 2 intptr_t diff; @@ -1921,16 +1923,21 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) diff = tcg_pcrel_diff(s, target); if (in_range_b(diff)) { - tcg_out_b(s, LK, target); + tcg_out_b(s, lk, target); } else { tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR); - tcg_out32(s, BCCTR | BO_ALWAYS | LK); + tcg_out32(s, BCCTR | BO_ALWAYS | lk); } #else - tcg_out_b(s, LK, target); + tcg_out_b(s, lk, target); #endif } +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) +{ + tcg_out_call_int(s, LK, target); +} + static const uint32_t qemu_ldx_opc[(MO_SSIZE + MO_BSWAP) + 1] = { [MO_UB] = LBZX, [MO_UW] = LHZX, @@ -1960,8 +1967,6 @@ static const uint32_t qemu_exts_opc[4] = { }; #if defined (CONFIG_SOFTMMU) -#include "../tcg-ldst.c.inc" - /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) */ @@ -2227,6 +2232,71 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) tcg_out_b(s, 0, lb->raddr); return true; } +#else + +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo, + TCGReg addrhi, unsigned a_bits) +{ + unsigned a_mask = (1 << a_bits) - 1; + TCGLabelQemuLdst *label = new_ldst_label(s); + + label->is_ld = is_ld; + label->addrlo_reg = addrlo; + label->addrhi_reg = addrhi; + + /* We are expecting a_bits to max out at 7, much lower than ANDI. */ + tcg_debug_assert(a_bits < 16); + tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, a_mask)); + + label->label_ptr[0] = s->code_ptr; + tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK); + + label->raddr = tcg_splitwx_to_rx(s->code_ptr); +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + if (!reloc_pc14(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { + return false; + } + + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + TCGReg arg = TCG_REG_R4; +#ifdef TCG_TARGET_CALL_ALIGN_ARGS + arg |= 1; +#endif + if (l->addrlo_reg != arg) { + tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg); + tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg); + } else if (l->addrhi_reg != arg + 1) { + tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg); + } else { + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R0, arg); + tcg_out_mov(s, TCG_TYPE_I32, arg, arg + 1); + tcg_out_mov(s, TCG_TYPE_I32, arg + 1, TCG_REG_R0); + } + } else { + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R4, l->addrlo_reg); + } + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, TCG_AREG0); + + /* "Tail call" to the helper, with the return address back inline. */ + tcg_out_call_int(s, 0, (const void *)(l->is_ld ? helper_unaligned_ld + : helper_unaligned_st)); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + #endif /* SOFTMMU */ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) @@ -2238,6 +2308,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) #ifdef CONFIG_SOFTMMU int mem_index; tcg_insn_unit *label_ptr; +#else + unsigned a_bits; #endif datalo = *args++; @@ -2258,6 +2330,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) rbase = TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ + a_bits = get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); + } rbase = guest_base ? TCG_GUEST_BASE_REG : 0; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); @@ -2313,6 +2389,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) #ifdef CONFIG_SOFTMMU int mem_index; tcg_insn_unit *label_ptr; +#else + unsigned a_bits; #endif datalo = *args++; @@ -2333,6 +2411,10 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) rbase = TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ + a_bits = get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); + } rbase = guest_base ? TCG_GUEST_BASE_REG : 0; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); From patchwork Wed Oct 13 02:46:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515717 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6100061ime; Tue, 12 Oct 2021 20:23:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxgB9pD0Bbli9nwmLvfOvfSAZqv/6iQ0fvOWiaTMTm1f7WRjK3QMY6HRuAwaleZ9MtaUJ8D X-Received: by 2002:a5d:9f44:: with SMTP id u4mr25062328iot.155.1634095405334; Tue, 12 Oct 2021 20:23:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634095405; cv=none; d=google.com; s=arc-20160816; b=u++ikUP8TpOaaqci/PyjEUrJqfTrjMb5xfWq3hFmG1N4IVrQue0pbJto9CFovDv9wM ZVpMOanPSlsinvp4u3bOV86KphyGGjaX7oHb5cq4eigH2jK1VowutorzqTbP8gLNTTWm CThCmUAl6eob/6CnjqKeUvlcyRuKB9xS6vlq8go4vpJIoqhDXtQ4TMUfX0PShm93nFAe N6CguAD6cLqlaX5AH9c9Cg/anSP9V6jKd0WiqsaAejt84uaG2yer+gBn+Mdr7zGbvrZy cCS7HV5dw2solM1agALAFVzW3kyIg5MONVCS6MmRPkLr7ztww6BZTFc2fJhTl0w71teA m9pQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0w3+xrnKvaU2OEox0ZNuOdUILQRpNN2Q/xBzhKWN3og=; b=rERTUp24KT/KXQxCmCETjnYSCjD8UF6sZWccJbdi3WCHLasSy+DA8ejHNHRzOzMXvc a2jzNDBlzJ+gABW4oMbU7G4uH5DszJ2fKvMESL7R7ZLgSzBbe9ZJ713eML9bkW7wC8eo ccC/iFDlhnjN/yaICuZig8NiIvmhhq1nqrrT1x+j7BEEry1qL3dBaN7JYDwT5In3du2+ 5MwEaOxEvBvtq0MJuJzrn0w8hLDjtFivQ9uWXi8AJNmk48KCLWBlrDLFfahSlHrec3HZ pWDQqKJODahlGxlCBhAbiZelyV226dgPRGCt+ltkUlsKSgpx7rWnUB4dnjN5HUN5jMXn JnyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ESK2Mf7D; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 12 Oct 2021 19:49:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 45/48] tcg/s390: Support raising sigbus for user-only Date: Tue, 12 Oct 2021 19:46:04 -0700 Message-Id: <20211013024607.731881-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 -- tcg/s390x/tcg-target.c.inc | 59 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 57 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 527ada0f63..69217d995b 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -178,9 +178,7 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, /* no need to flush icache explicitly */ } -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #define TCG_TARGET_NEED_POOL_LABELS #endif diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 8938c446c8..bc6a13d797 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -29,6 +29,7 @@ #error "unsupported code generation mode" #endif +#include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" #include "elf.h" @@ -136,6 +137,7 @@ typedef enum S390Opcode { RI_OIHL = 0xa509, RI_OILH = 0xa50a, RI_OILL = 0xa50b, + RI_TMLL = 0xa701, RIE_CGIJ = 0xec7c, RIE_CGRJ = 0xec64, @@ -1804,8 +1806,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data, } #if defined(CONFIG_SOFTMMU) -#include "../tcg-ldst.c.inc" - /* We're expecting to use a 20-bit negative offset on the tlb memory ops. */ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); @@ -1942,6 +1942,53 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) return true; } #else +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, + TCGReg addrlo, unsigned a_bits) +{ + unsigned a_mask = (1 << a_bits) - 1; + TCGLabelQemuLdst *l = new_ldst_label(s); + + l->is_ld = is_ld; + l->addrlo_reg = addrlo; + + /* We are expecting a_bits to max out at 7, much lower than TMLL. */ + tcg_debug_assert(a_bits < 16); + tcg_out_insn(s, RI, TMLL, addrlo, a_mask); + + tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ + l->label_ptr[0] = s->code_ptr; + s->code_ptr += 1; + + l->raddr = tcg_splitwx_to_rx(s->code_ptr); +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + if (!patch_reloc(l->label_ptr[0], R_390_PC16DBL, + (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { + return false; + } + + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); + + /* "Tail call" to the helper, with the return address back inline. */ + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R14, (uintptr_t)l->raddr); + tgen_gotoi(s, S390_CC_ALWAYS, (const void *)(l->is_ld ? helper_unaligned_ld + : helper_unaligned_st)); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg, TCGReg *index_reg, tcg_target_long *disp) { @@ -1980,7 +2027,11 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, #else TCGReg index_reg; tcg_target_long disp; + unsigned a_bits = get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, true, addr_reg, a_bits); + } tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp); tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp); #endif @@ -2007,7 +2058,11 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, #else TCGReg index_reg; tcg_target_long disp; + unsigned a_bits = get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, false, addr_reg, a_bits); + } tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp); tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp); #endif From patchwork Wed Oct 13 02:46:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515712 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6097584ime; Tue, 12 Oct 2021 20:18:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyWAyWmfqal5l2Np+26MeFTW0v/iEMu3pFBHV4Qux1OjnyEs8jWw4e3S5YVGgD75yNs5u+F X-Received: by 2002:a37:2f02:: with SMTP id v2mr22502653qkh.232.1634095130070; Tue, 12 Oct 2021 20:18:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634095130; cv=none; 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Tue, 12 Oct 2021 19:49:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 46/48] tcg/tci: Support raising sigbus for user-only Date: Tue, 12 Oct 2021 19:46:05 -0700 Message-Id: <20211013024607.731881-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index e76087ccac..92a7c81674 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -292,11 +292,11 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr, MemOpIdx oi, const void *tb_ptr) { - MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE); + MemOp mop = get_memop(oi); uintptr_t ra = (uintptr_t)tb_ptr; #ifdef CONFIG_SOFTMMU - switch (mop) { + switch (mop & (MO_BSWAP | MO_SSIZE)) { case MO_UB: return helper_ret_ldub_mmu(env, taddr, oi, ra); case MO_SB: @@ -326,10 +326,14 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr, } #else void *haddr = g2h(env_cpu(env), taddr); + unsigned a_mask = (1u << get_alignment_bits(mop)) - 1; uint64_t ret; set_helper_retaddr(ra); - switch (mop) { + if (taddr & a_mask) { + helper_unaligned_ld(env, taddr); + } + switch (mop & (MO_BSWAP | MO_SSIZE)) { case MO_UB: ret = ldub_p(haddr); break; @@ -377,11 +381,11 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr, static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val, MemOpIdx oi, const void *tb_ptr) { - MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE); + MemOp mop = get_memop(oi); uintptr_t ra = (uintptr_t)tb_ptr; #ifdef CONFIG_SOFTMMU - switch (mop) { + switch (mop & (MO_BSWAP | MO_SIZE)) { case MO_UB: helper_ret_stb_mmu(env, taddr, val, oi, ra); break; @@ -408,9 +412,13 @@ static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val, } #else void *haddr = g2h(env_cpu(env), taddr); + unsigned a_mask = (1u << get_alignment_bits(mop)) - 1; set_helper_retaddr(ra); - switch (mop) { + if (taddr & a_mask) { + helper_unaligned_st(env, taddr); + } + switch (mop & (MO_BSWAP | MO_SIZE)) { case MO_UB: stb_p(haddr, val); break; From patchwork Wed Oct 13 02:46:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515715 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6098975ime; Tue, 12 Oct 2021 20:21:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzb7Aii0qN594bU/FSzIxiAg9KV+NoEnz3+x4zyGqd4wNYu8URzzoktjTx8YVqxJm/pBuS/ X-Received: by 2002:a05:6e02:1747:: with SMTP id y7mr26330845ill.95.1634095279793; Tue, 12 Oct 2021 20:21:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634095279; cv=none; d=google.com; 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Tue, 12 Oct 2021 19:49:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 47/48] tcg/riscv: Support raising sigbus for user-only Date: Tue, 12 Oct 2021 19:46:06 -0700 Message-Id: <20211013024607.731881-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org> References: <20211013024607.731881-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 2 -- tcg/riscv/tcg-target.c.inc | 63 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 61 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index ef78b99e98..11c9b3e4f4 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -165,9 +165,7 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_DEFAULT_MO (0) -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #define TCG_TARGET_NEED_POOL_LABELS #define TCG_TARGET_HAS_MEMORY_BSWAP 0 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 9b13a46fb4..49e84cbe13 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -27,6 +27,7 @@ * THE SOFTWARE. */ +#include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" #ifdef CONFIG_DEBUG_TCG @@ -847,8 +848,6 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) */ #if defined(CONFIG_SOFTMMU) -#include "../tcg-ldst.c.inc" - /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * MemOpIdx oi, uintptr_t ra) */ @@ -1053,6 +1052,54 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) tcg_out_goto(s, l->raddr); return true; } +#else + +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_reg, + unsigned a_bits) +{ + unsigned a_mask = (1 << a_bits) - 1; + TCGLabelQemuLdst *l = new_ldst_label(s); + + l->is_ld = is_ld; + l->addrlo_reg = addr_reg; + + /* We are expecting a_bits to max out at 7, so we can always use andi. */ + tcg_debug_assert(a_bits < 12); + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); + + l->label_ptr[0] = s->code_ptr; + tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0); + + l->raddr = tcg_splitwx_to_rx(s->code_ptr); +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + /* resolve label address */ + if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { + return false; + } + + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); + + /* tail call, with the return address back inline. */ + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (uintptr_t)l->raddr); + tcg_out_call_int(s, (const void *)(l->is_ld ? helper_unaligned_ld + : helper_unaligned_st), true); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + #endif /* CONFIG_SOFTMMU */ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, @@ -1108,6 +1155,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[1]; +#else + unsigned a_bits; #endif TCGReg base = TCG_REG_TMP0; @@ -1130,6 +1179,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) tcg_out_ext32u(s, base, addr_regl); addr_regl = base; } + a_bits = get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, true, addr_regl, a_bits); + } if (guest_base != 0) { tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); } @@ -1174,6 +1227,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[1]; +#else + unsigned a_bits; #endif TCGReg base = TCG_REG_TMP0; @@ -1196,6 +1251,10 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) tcg_out_ext32u(s, base, addr_regl); addr_regl = base; } + a_bits = get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, false, addr_regl, a_bits); + } if (guest_base != 0) { tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); } From patchwork Wed Oct 13 02:46:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515718 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp6101354ime; Tue, 12 Oct 2021 20:25:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz+2sDEzAOlz0z43t+Y4LG0eUr5zooWiqJ27/ggI1iAehWWPE7nnAWXM2aUL4giR3Vg2BBV X-Received: by 2002:a05:6e02:1d17:: with SMTP id i23mr26126789ila.205.1634095545176; Tue, 12 Oct 2021 20:25:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634095545; cv=none; d=google.com; s=arc-20160816; b=hQ2V6GlgFJvEk3w9QYt2fwc77pNgMsHu8IhvXLvzeTyHRXJISilEt50NK6+iE/HHw0 9a7ycXStOPgTPrSASwBt60U4O5yedlXCK7BWt1gnVusFY4HO3iUhiXCP5jiAxtdDcgzA F2wBvyGkQ7HjFbrhkumy8jLFT5i5NZx2+0RTKTlyTjefj4bJJWbjtmlYBjNi6QLL4Uy/ QtTkBs75YS0q2PWLIwmwdntPTQo7bGgFEppaGaAN0n7wDdm8U5a9itXReqCn6Qe8+hBc KdEVNCXSt1t6SDZMTCbGPYaH5/+nUYrJRAeEFXM9bJIpV5dBU7TaG37+ieNDSSiG49PS f46Q== ARC-Message-Signature: i=1; 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tests/tcg/multiarch/sigbus.c | 68 ++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 tests/tcg/multiarch/sigbus.c -- 2.25.1 diff --git a/tests/tcg/multiarch/sigbus.c b/tests/tcg/multiarch/sigbus.c new file mode 100644 index 0000000000..8134c5fd56 --- /dev/null +++ b/tests/tcg/multiarch/sigbus.c @@ -0,0 +1,68 @@ +#define _GNU_SOURCE 1 + +#include +#include +#include +#include + + +unsigned long long x = 0x8877665544332211ull; +void * volatile p = (void *)&x + 1; + +void sigbus(int sig, siginfo_t *info, void *uc) +{ + assert(sig == SIGBUS); + assert(info->si_signo == SIGBUS); +#ifdef BUS_ADRALN + assert(info->si_code == BUS_ADRALN); +#endif + assert(info->si_addr == p); + exit(EXIT_SUCCESS); +} + +int main() +{ + struct sigaction sa = { + .sa_sigaction = sigbus, + .sa_flags = SA_SIGINFO + }; + int allow_fail = 0; + int tmp; + + tmp = sigaction(SIGBUS, &sa, NULL); + assert(tmp == 0); + + /* + * Select an operation that's likely to enforce alignment. + * On many guests that support unaligned accesses by default, + * this is often an atomic operation. + */ +#if defined(__aarch64__) + asm volatile("ldxr %w0,[%1]" : "=r"(tmp) : "r"(p) : "memory"); +#elif defined(__alpha__) + asm volatile("ldl_l %0,0(%1)" : "=r"(tmp) : "r"(p) : "memory"); +#elif defined(__arm__) + asm volatile("ldrex %0,[%1]" : "=r"(tmp) : "r"(p) : "memory"); +#elif defined(__powerpc__) + asm volatile("lwarx %0,0,%1" : "=r"(tmp) : "r"(p) : "memory"); +#elif defined(__riscv_atomic) + asm volatile("lr.w %0,(%1)" : "=r"(tmp) : "r"(p) : "memory"); +#else + /* No insn known to fault unaligned -- try for a straight load. */ + allow_fail = 1; + tmp = *(volatile int *)p; +#endif + + assert(allow_fail); + + /* + * We didn't see a signal. + * We might as well validate the unaligned load worked. + */ + if (BYTE_ORDER == LITTLE_ENDIAN) { + assert(tmp == 0x55443322); + } else { + assert(tmp == 0x77665544); + } + return EXIT_SUCCESS; +}