From patchwork Thu Oct 7 17:47:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515458 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1410696ime; Thu, 7 Oct 2021 10:52:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz7sRxxf998wIVTThyixDQwftO2K8TKAH6RNUGEWTP51uf+2qCpClt/X2sf9HhU1l/+0L1c X-Received: by 2002:aed:3022:: with SMTP id 31mr6694298qte.322.1633629122517; Thu, 07 Oct 2021 10:52:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633629122; cv=none; d=google.com; s=arc-20160816; b=kW21mtJ6FgzncpVuCndcUBu+G2gd+PthAdBHRhd0lZl3wv04F7IwMI34itwtLRp2s4 E+YR2vBKaF2h3Wy0lek0vvB4ziFXmF9VkSSjIHhkmacudhcODlpi3zQkrJlT6f4PBpaV WVJ94WEkkEq2z8LcFXOY8ARBzwZlyC0VfMOOebJdlAg6gglOQsKozBO10IHDBVOYXrpM Lv8qGi9UXoSDd84OxKKLlGYzZBrZIryBuR9COux7lR5MqobJmie9xQN7i4zvKbeDve5O c7eNJArZw2CaMZ76nqMuNdHyal8wip5XFPZpORKDOdLbJcyyu1oX6sCZCOyIub++yY2Q MCQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7VoTqH6Ab5qBEn7dsfX9wElPM3ZHRNrhLAk52+sFWkc=; b=U92AU/lpKBHI+abDhluVeC8jI3NBno2HTVcbQbAwd9Z430IEvFBAaJLZ0lKBBauSHq g8sJNQsqKODrTK01at9xmUyizkjtFy0W5WOn3PKvv+LJwOwm0legVtSYfYhyco7pACtD 4iXzEFlIw+A9nzmrqbHV0EMzsJfx76nJp8708usNNS+g6UCc0IX1qSIwIDDZIpKCxPvI pdlCTmHVshXDEyoMq6l70wTD/b1h3kgwY6y5iLYRxL8eAUcEYG9qsHsK/HM2H/c0YmQD aqJRet2DtfPCBVfSg3HO95o0/XYWvkWNAaPpUeQnEQNqkprEQl7l6CBhizP58hd+wkdY BBgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eBQQOqNf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v32si62263qtc.145.2021.10.07.10.52.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Oct 2021 10:52:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eBQQOqNf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYXYn-0001FX-Vo for patch@linaro.org; Thu, 07 Oct 2021 13:52:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37978) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYXUP-0003xt-1E for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:29 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:44961) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mYXUM-0006oY-0f for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:28 -0400 Received: by mail-pj1-x102c.google.com with SMTP id oa12-20020a17090b1bcc00b0019f715462a8so5698775pjb.3 for ; Thu, 07 Oct 2021 10:47:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7VoTqH6Ab5qBEn7dsfX9wElPM3ZHRNrhLAk52+sFWkc=; b=eBQQOqNftwHqu7X5uxZNh0hwBp0OUBPlFDCWlOwhFQupCe/caqnUDDO54hhZuZCG3S OYPqgDFXW2VH1P3BTMP5mT0cluf9QDueLoiHHh/aKaxgrA8LiJLL9+7Te8ijuL1rg8is efcIuT+Lhw4iiLPM9+6r0YxM0xPB/uV79I9GAfHzrxQzgRMkyGJ0Ghzjc9z0HDrJBKjy HCAx8nv4ZXiYEwFSWn6ELFPhnTcnzlzU/P0UpmdkMV6Yz145F0Q9ZitwuL4NpmmmrWST cS/whTVJht0+tLAF4szG0Bae8LWIxyC/C/qCbGiwH4iwaOenknPXIlgTeLpXxUYXr0nr PKkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7VoTqH6Ab5qBEn7dsfX9wElPM3ZHRNrhLAk52+sFWkc=; b=roeOqHpn+Y3XR3tbCfuGWfK1Q2sBMDr298b9vLVgHmS7YCt51B/1ujAEL3Wy6H7ekA ULkg55BLpHed2EIMhqdud4BYqf/KNCmayX15rRMOfte0zbzecm5PBjCTGupCdbE25Ief 7WRR5TvAna3wLWmNQn512YvHlULi/kwhpI4PW4Kh15QyUtB+2zc72kCeyLSndYItUs43 lp4ZxbIH+8nonA3OjYZc4rshRoRw8J4Twk63LzN1vYFDJhJVF741N/5PtfeTg6e/Kj7Q h0h/FGoPmVpIxiDoroaY6a8nWM5PFuf4FDUJgxo0OryMXxSQdYuPhioFUVd92clIyv4R XTFA== X-Gm-Message-State: AOAM531TY6MW8VGcTFAlnkHUxkoTg5B32iap1k/DV8uff/MP3Luw4gLy iW/bxh/VZhI1af7OuL44OMJM1yWylUb3yw== X-Received: by 2002:a17:90a:e613:: with SMTP id j19mr6993264pjy.102.1633628844623; Thu, 07 Oct 2021 10:47:24 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id 197sm83318pfv.6.2021.10.07.10.47.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 10:47:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line Date: Thu, 7 Oct 2021 10:47:10 -0700 Message-Id: <20211007174722.929993-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org> References: <20211007174722.929993-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the function to cpu_helper.c, as it is large and growing. Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 47 ++------------------------------------- target/riscv/cpu_helper.c | 46 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 45 deletions(-) -- 2.25.1 Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9e55b2f5b1..7084efc452 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -413,51 +413,8 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) return cpu->cfg.vlen >> (sew + 3 - lmul); } -static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *pflags) -{ - uint32_t flags = 0; - - *pc = env->pc; - *cs_base = 0; - - if (riscv_has_ext(env, RVV)) { - uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); - bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); - flags = FIELD_DP32(flags, TB_FLAGS, VILL, - FIELD_EX64(env->vtype, VTYPE, VILL)); - flags = FIELD_DP32(flags, TB_FLAGS, SEW, - FIELD_EX64(env->vtype, VTYPE, VSEW)); - flags = FIELD_DP32(flags, TB_FLAGS, LMUL, - FIELD_EX64(env->vtype, VTYPE, VLMUL)); - flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); - } else { - flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); - } - -#ifdef CONFIG_USER_ONLY - flags |= TB_FLAGS_MSTATUS_FS; -#else - flags |= cpu_mmu_index(env, 0); - if (riscv_cpu_fp_enabled(env)) { - flags |= env->mstatus & MSTATUS_FS; - } - - if (riscv_has_ext(env, RVH)) { - if (env->priv == PRV_M || - (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); - } - - flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, - get_field(env->mstatus_hs, MSTATUS_FS)); - } -#endif - - *pflags = flags; -} +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags); RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d41d5cd27c..14d1d3cb72 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -35,6 +35,52 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags) +{ + uint32_t flags = 0; + + *pc = env->pc; + *cs_base = 0; + + if (riscv_has_ext(env, RVV)) { + uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); + bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); + flags = FIELD_DP32(flags, TB_FLAGS, VILL, + FIELD_EX64(env->vtype, VTYPE, VILL)); + flags = FIELD_DP32(flags, TB_FLAGS, SEW, + FIELD_EX64(env->vtype, VTYPE, VSEW)); + flags = FIELD_DP32(flags, TB_FLAGS, LMUL, + FIELD_EX64(env->vtype, VTYPE, VLMUL)); + flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); + } else { + flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); + } + +#ifdef CONFIG_USER_ONLY + flags |= TB_FLAGS_MSTATUS_FS; +#else + flags |= cpu_mmu_index(env, 0); + if (riscv_cpu_fp_enabled(env)) { + flags |= env->mstatus & MSTATUS_FS; + } + + if (riscv_has_ext(env, RVH)) { + if (env->priv == PRV_M || + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); + } + + flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, + get_field(env->mstatus_hs, MSTATUS_FS)); + } +#endif + + *pflags = flags; +} + #ifndef CONFIG_USER_ONLY static int riscv_cpu_local_irq_pending(CPURISCVState *env) { From patchwork Thu Oct 7 17:47:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515455 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1408441ime; Thu, 7 Oct 2021 10:48:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz7unUeYHMZ25zIFiFko4AOwQkBnNBkCuyamGDbuM68isQgG18aNHPrMRxejz7PKwoR4TeG X-Received: by 2002:a37:6cc6:: with SMTP id h189mr4468680qkc.321.1633628935540; Thu, 07 Oct 2021 10:48:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633628935; cv=none; d=google.com; s=arc-20160816; b=HN4Lp6EAvyooTzJaWQHPVwpkdJqfNIY2RLgumeEl52kK0qQyUIUuXMjzMwg7jX/zk0 2unlktOuZpIjNFQCw96PApED7/sfak1MXIXJRAq0Iy9RGHHglaZeIpUNiXnHMR/0Ht7K 7gzSksig9c2iroiykh4u7pJhupRuV5NHtTL6lRrhx8d3qRQirkk8en9OUqr21x8fxZLC geJqPlA89c8NqrAtq7BtQJs3D2SlXw/8ugQ0ojg6c8otoPx8RWx/gtIED/U6pQl/IHho 28cioezVwp3tiVvgNcPkdRfBIVXRCuVjov5jHxH8ErYZ1j4pwFoJHqdIqQC20MBS8c56 J1Fg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZJ63cbY+lnqN4JixeYMitc/OluC43ZJ3MKKbgpDVcuI=; b=XSiEbrSw11lUoJ+c+Eru+fljAbOHn4Yp9VhTpkRAjOIJJ6JczXH7JYrxeM+EXiL4Ff 5+apC+oQmaJHERU0MD+PtW9IYi2S04RnRO/FZdCuQf7PMiHM/x5q0s/GIE6upBYUtXAu 8aIygnKThNmKcawndEBTMORisfe9HAw6rBAc17irtH0fPu/dA9TTV89HJ5dwnV0C7gLI omjgNMX+PG2M/9oKYWwBlGCcAh94pE7RnEUOpttzRG/C5vUCsAi8VumMDOZedxtjO3Bn ma9yhw91Ofn1C0p+mvg2EiewSvlCjgpHL8trj4hA6dyIGbB2VHSnUDi53rXdw6SJFY5W fCwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OeZ3gZOF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id dv11si122166qvb.102.2021.10.07.10.48.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Oct 2021 10:48:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OeZ3gZOF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50980 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYXVn-0003zy-0r for patch@linaro.org; Thu, 07 Oct 2021 13:48:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37976) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYXUO-0003xo-SR for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:28 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:36476) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mYXUM-0006pe-JY for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:28 -0400 Received: by mail-pg1-x533.google.com with SMTP id 75so521184pga.3 for ; Thu, 07 Oct 2021 10:47:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZJ63cbY+lnqN4JixeYMitc/OluC43ZJ3MKKbgpDVcuI=; b=OeZ3gZOFKMJbuI7ucd6XK1PngGO0j9qKq5axNPtkCWA4SfN3qYPIw30wOxXlFBp7/Q MTHGZdO13It8yH0rwY8vh2E2taidupwSI/Aa72X5Gg8aEvJnPlhKCQ23Hp6OtOiTP2r+ ktBMqQHSGWVPQsDmbJSnQ3AB0062llSaTMz/6hrmCVoaN0MUTflvYwYgWPO9ePzfF4uy xmkjKmYzfRYUhCKnLbG1gh/ui53p7XMZuES27xyUZqwcPNtflYY24N2VAaaCAgyk9NCo BbXguzHW+Y87rbGIBi0HbpyPLfyV2LkJg4zuS+vo5GCm2TOi5mz+O831NNhtE/lu2ZGt ES/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZJ63cbY+lnqN4JixeYMitc/OluC43ZJ3MKKbgpDVcuI=; b=osf/jkIxcJmdudEidNQ6+UbSJ8XJ81+2v5NjjwXx99BGu4wSk/bnRn8gKUwMF5KcYi +yS2Hop6aOZjj6Gm3RR/2qmbhjYgGrbJ9NHNgyzCWQyR1BezU0eQuMQc1VZw6xYJKr8E zvyYIlxbRuXQ+rkBOydQvTtKKceQNf9qHfIfi9mAlAxs03A6Imv3zFdXu9Yns8T2ZLp+ yFsIfLTvaYSxhI3hHUdAI65FNj2SJNWZRvya8OyXiQskDI/6HM9OLTxfAaGiFj6uY2NN 1RY9rV76sFlkE3N+IQgeWQ8MOpgp9NpIq8G/XYhxP1nbJbrcHqBaUSi6gqnEPCYpCO2h nHiw== X-Gm-Message-State: AOAM532eSppb5LwUqKjn7fDl9kHcjhzn7Q2KtM0Df2V36yrXFosSgLW9 S/cTtyy3liAgsr8KsnSRo83nTMyjj4y8Aw== X-Received: by 2002:a63:191a:: with SMTP id z26mr736280pgl.373.1633628845301; Thu, 07 Oct 2021 10:47:25 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id 197sm83318pfv.6.2021.10.07.10.47.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 10:47:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 02/13] target/riscv: Create RISCVMXL enumeration Date: Thu, 7 Oct 2021 10:47:11 -0700 Message-Id: <20211007174722.929993-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org> References: <20211007174722.929993-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the MXL_RV* defines to enumerators. Signed-off-by: Richard Henderson --- target/riscv/cpu_bits.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -- 2.25.1 Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 999187a9ee..e248c6bf6d 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -364,9 +364,11 @@ #define MISA32_MXL 0xC0000000 #define MISA64_MXL 0xC000000000000000ULL -#define MXL_RV32 1 -#define MXL_RV64 2 -#define MXL_RV128 3 +typedef enum { + MXL_RV32 = 1, + MXL_RV64 = 2, + MXL_RV128 = 3, +} RISCVMXL; /* sstatus CSR bits */ #define SSTATUS_UIE 0x00000001 From patchwork Thu Oct 7 17:47:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515456 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1408640ime; Thu, 7 Oct 2021 10:49:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzZA4+ktYD7U4bpaRq54xa8cfCXwZrfdYMeDI4vqnVCGEcbKqEz/wyLkj7tNzAERNLv53an X-Received: by 2002:a37:dc4:: with SMTP id 187mr4596370qkn.310.1633628953563; Thu, 07 Oct 2021 10:49:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633628953; cv=none; d=google.com; s=arc-20160816; b=mVCni8dOFvZlELlGH9zvZXCHBj72NsoT21FGXib5lz538zWhymFkzF+cpOAQqvQPlW VU3J3kSUzHteOmLzyADyRR/0SJKsJoLMY9iLPrnlatkz9nDnN8Xqk3TTPlayDhUE3V/h jN6is10/uZ1ehRf9FKka271aNpX+P7pSiy0mKd7wKrNNIjis2cFq8k8FR3kpvusrG6wJ qnu5Lruvjwxi3ATTDcTZBE4ZhCix95zuck8wBNhHjJm+3mBetIbjc0FMbHQB3WZWvvg8 3+PbR9ryRr1Dw111QswwS0skVDw/rPFKqISuT3C3eP8bSv71xutEJwncXW/mgwnCifSC lAeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GyfOwg5IaXcvLhAxm9r8QrLGrQThfzHQ6LlK1YalTsg=; b=ZUBZ1tT4ZIdcW9KfuGlI28iuDJPbKvIBrAfhkkBs7h6i1pe3d6WGVZ9F97NpHVHZKx Yn8lYhqFe9T1SYHfQWD+vYygSTU14wTx6aIutVUvuxiZP8pduGmZzsadL2DLabCokHGR GPQZ5IFn9BmLNPJS9OEmH7IYi9VIHwuNkqBHhUDA4itxo3Mckk8558NZq1vJgeFXrzhx sYF+Oh/M5oCkdzWdc27D74r4vhb2/jqk4niqfxyEZ011uppesE6B7ZJ+5mRVAQDh9zWN XvkEbGn72YUmGUT6Eux0vtK8hTxfyccDg/hC/N70zh0EtpNOBEiw0zfdiay+yhkB3jnZ 8XwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mvqrZb3e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v35si61073qtc.218.2021.10.07.10.49.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Oct 2021 10:49:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mvqrZb3e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51696 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYXW5-0004UU-09 for patch@linaro.org; Thu, 07 Oct 2021 13:49:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38036) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYXUR-00041p-7u for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:32 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:36477) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mYXUN-0006qb-Pk for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:30 -0400 Received: by mail-pg1-x534.google.com with SMTP id 75so521226pga.3 for ; Thu, 07 Oct 2021 10:47:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GyfOwg5IaXcvLhAxm9r8QrLGrQThfzHQ6LlK1YalTsg=; b=mvqrZb3eEVaMABMXd2zaqc/gaJ+2CDDYBH1H5qNaWf+CBMvmsun5uySCT7lojutqsG xe8kBO69JiaDvAtN41edeNgVO/WIgAZofinOy31IS/Py8go6Dj1tbU91Rq2g/A0Y/Ojx 44BXkAGVP4rgiHKzEnkjOfHRfYFLqZ81uddJG0srnIYm3jHBorFMWXPv65ZbqZMC8iXw B1uDXqx7Ae5U4ZDJIeZlgkDxjJrD/2Ksd+bXBSsk6pEvkYDrItE+cNjB2CoYbp3vVgSc stciF7xhfD1aD4wynLoq3Bq/2uTfZQHHtHEbF95MK2HDTsw1ZfnVRk4+iDV++u2FPtEM GYSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GyfOwg5IaXcvLhAxm9r8QrLGrQThfzHQ6LlK1YalTsg=; b=MzISQQx71EBevwF9SVmcvg+iwPW2IfCAb316+M0Q7zPq6U9ttUBoxFNWw8VIH+T19n hzNJp6RU/n8xCvRiy8e0axyJmzq0Q/8ZDPX6WKTLhxYvncvtNCw72k5WQAR00hzmrWMZ rIQsHP/DmLNje21KUnaUAuCx/zxXqmRnVOB4Ifr6pktmXdpmrJpzP4UbfA0lLLTnImDm gO8LnWnJkk19tm4q8TtfBngtrkDhTXg7rfFOse4s1VpzKDwf1aLC8hHvKcK4Z1DQCZ9p i+nPGKyR0eRtp4Z4uXHtR9eS8UZau/XaSMuiyZ6ssQi2AESIKKAg4YHpRwkcaGkkb1GG y5Eg== X-Gm-Message-State: AOAM5333g9XLWXhDJIUfMNI6F/4gHjKay2FSBCy5Vox0zUFLEcB/JPLS /1y3YTaps7rLZpL4on5vh3KlNQNdmhaupA== X-Received: by 2002:aa7:8042:0:b0:44c:78ec:c9a9 with SMTP id y2-20020aa78042000000b0044c78ecc9a9mr5391061pfm.45.1633628846329; Thu, 07 Oct 2021 10:47:26 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id 197sm83318pfv.6.2021.10.07.10.47.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 10:47:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 03/13] target/riscv: Split misa.mxl and misa.ext Date: Thu, 7 Oct 2021 10:47:12 -0700 Message-Id: <20211007174722.929993-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org> References: <20211007174722.929993-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The hw representation of misa.mxl is at the high bits of the misa csr. Representing this in the same way inside QEMU results in overly complex code trying to check that field. Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 15 ++++---- linux-user/elfload.c | 2 +- linux-user/riscv/cpu_loop.c | 2 +- target/riscv/cpu.c | 77 +++++++++++++++++++++---------------- target/riscv/csr.c | 44 +++++++++++++-------- target/riscv/gdbstub.c | 8 ++-- target/riscv/machine.c | 10 +++-- target/riscv/translate.c | 10 +++-- 8 files changed, 99 insertions(+), 69 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7084efc452..e708fcc168 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -25,6 +25,7 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" #include "qom/object.h" +#include "cpu_bits.h" #define TCG_GUEST_DEFAULT_MO 0 @@ -51,9 +52,6 @@ # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 #endif -#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) -#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) - #define RV(x) ((target_ulong)1 << (x - 'A')) #define RVI RV('I') @@ -133,8 +131,12 @@ struct CPURISCVState { target_ulong priv_ver; target_ulong bext_ver; target_ulong vext_ver; - target_ulong misa; - target_ulong misa_mask; + + /* RISCVMXL, but uint32_t for vmstate migration */ + uint32_t misa_mxl; /* current mxl */ + uint32_t misa_mxl_max; /* max mxl for this cpu */ + uint32_t misa_ext; /* current extensions */ + uint32_t misa_ext_mask; /* max ext for this cpu */ uint32_t features; @@ -313,7 +315,7 @@ struct RISCVCPU { static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) { - return (env->misa & ext) != 0; + return (env->misa_ext & ext) != 0; } static inline bool riscv_feature(CPURISCVState *env, int feature) @@ -322,7 +324,6 @@ static inline bool riscv_feature(CPURISCVState *env, int feature) } #include "cpu_user.h" -#include "cpu_bits.h" extern const char * const riscv_int_regnames[]; extern const char * const riscv_fpr_regnames[]; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 2404d482ba..214c1aa40d 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1448,7 +1448,7 @@ static uint32_t get_elf_hwcap(void) uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); - return cpu->env.misa & mask; + return cpu->env.misa_ext & mask; #undef MISA_BIT } diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 9859a366e4..e5bb6d908a 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -133,7 +133,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) env->gpr[xSP] = regs->sp; env->elf_flags = info->elf_flags; - if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) { + if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) { error_report("Incompatible ELF: RVE cpu requires RVE ABI binary"); exit(EXIT_FAILURE); } diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1d69d1887e..768fea6859 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,16 +110,13 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) bool riscv_cpu_is_32bit(CPURISCVState *env) { - if (env->misa & RV64) { - return false; - } - - return true; + return env->misa_mxl == MXL_RV32; } -static void set_misa(CPURISCVState *env, target_ulong misa) +static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) { - env->misa_mask = env->misa = misa; + env->misa_mxl_max = env->misa_mxl = mxl; + env->misa_ext_mask = env->misa_ext = ext; } static void set_priv_version(CPURISCVState *env, int priv_ver) @@ -148,9 +145,9 @@ static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; #if defined(TARGET_RISCV32) - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #elif defined(TARGET_RISCV64) - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif set_priv_version(env, PRIV_VERSION_1_11_0); } @@ -160,20 +157,20 @@ static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, RV64); + set_misa(env, MXL_RV64, 0); } static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); } static void rv64_sifive_e_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } @@ -182,20 +179,20 @@ static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, RV32); + set_misa(env, MXL_RV32, 0); } static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); } static void rv32_sifive_e_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } @@ -203,7 +200,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) static void rv32_ibex_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVC | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); qdev_prop_set_bit(DEVICE(obj), "mmu", false); qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); @@ -212,7 +209,7 @@ static void rv32_ibex_cpu_init(Object *obj) static void rv32_imafcu_nommu_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); set_resetvec(env, DEFAULT_RSTVEC); qdev_prop_set_bit(DEVICE(obj), "mmu", false); @@ -388,7 +385,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) CPURISCVState *env = &cpu->env; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); int priv_version = 0; - target_ulong target_misa = env->misa; Error *local_err = NULL; cpu_exec_realizefn(cs, &local_err); @@ -434,8 +430,23 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_resetvec(env, cpu->cfg.resetvec); - /* If only XLEN is set for misa, then set misa from properties */ - if (env->misa == RV32 || env->misa == RV64) { + /* Validate that MISA_MXL is set properly. */ + switch (env->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + break; +#endif + case MXL_RV32: + break; + default: + g_assert_not_reached(); + } + assert(env->misa_mxl_max == env->misa_mxl); + + /* If only MISA_EXT is unset for misa, then set it from properties */ + if (env->misa_ext == 0) { + uint32_t ext = 0; + /* Do some ISA extension error checking */ if (cpu->cfg.ext_i && cpu->cfg.ext_e) { error_setg(errp, @@ -462,38 +473,38 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_i) { - target_misa |= RVI; + ext |= RVI; } if (cpu->cfg.ext_e) { - target_misa |= RVE; + ext |= RVE; } if (cpu->cfg.ext_m) { - target_misa |= RVM; + ext |= RVM; } if (cpu->cfg.ext_a) { - target_misa |= RVA; + ext |= RVA; } if (cpu->cfg.ext_f) { - target_misa |= RVF; + ext |= RVF; } if (cpu->cfg.ext_d) { - target_misa |= RVD; + ext |= RVD; } if (cpu->cfg.ext_c) { - target_misa |= RVC; + ext |= RVC; } if (cpu->cfg.ext_s) { - target_misa |= RVS; + ext |= RVS; } if (cpu->cfg.ext_u) { - target_misa |= RVU; + ext |= RVU; } if (cpu->cfg.ext_h) { - target_misa |= RVH; + ext |= RVH; } if (cpu->cfg.ext_v) { int vext_version = VEXT_VERSION_0_07_1; - target_misa |= RVV; + ext |= RVV; if (!is_power_of_2(cpu->cfg.vlen)) { error_setg(errp, "Vector extension VLEN must be power of 2"); @@ -532,7 +543,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_vext_version(env, vext_version); } - set_misa(env, target_misa); + set_misa(env, env->misa_mxl, ext); } riscv_cpu_register_gdb_regs_for_features(cs); @@ -705,7 +716,7 @@ char *riscv_isa_string(RISCVCPU *cpu) char *isa_str = g_new(char, maxlen); char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); for (i = 0; i < sizeof(riscv_exts); i++) { - if (cpu->env.misa & RV(riscv_exts[i])) { + if (cpu->env.misa_ext & RV(riscv_exts[i])) { *p++ = qemu_tolower(riscv_exts[i]); } } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 23fbbd3216..d0c86a300d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -39,7 +39,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) /* loose check condition for fcsr in vector extension */ - if ((csrno == CSR_FCSR) && (env->misa & RVV)) { + if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) { return RISCV_EXCP_NONE; } if (!env->debugger && !riscv_cpu_fp_enabled(env)) { @@ -51,7 +51,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) static RISCVException vs(CPURISCVState *env, int csrno) { - if (env->misa & RVV) { + if (env->misa_ext & RVV) { return RISCV_EXCP_NONE; } return RISCV_EXCP_ILLEGAL_INST; @@ -557,7 +557,22 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno, static RISCVException read_misa(CPURISCVState *env, int csrno, target_ulong *val) { - *val = env->misa; + target_ulong misa; + + switch (env->misa_mxl) { + case MXL_RV32: + misa = (target_ulong)MXL_RV32 << 30; + break; +#ifdef TARGET_RISCV64 + case MXL_RV64: + misa = (target_ulong)MXL_RV64 << 62; + break; +#endif + default: + g_assert_not_reached(); + } + + *val = misa | env->misa_ext; return RISCV_EXCP_NONE; } @@ -583,8 +598,13 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } + /* + * misa.MXL writes are not supported by QEMU. + * Drop writes to those bits. + */ + /* Mask extensions that are not supported by this hart */ - val &= env->misa_mask; + val &= env->misa_ext_mask; /* Mask extensions that are not supported by QEMU */ val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); @@ -601,20 +621,14 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, val &= ~RVC; } - /* misa.MXL writes are not supported by QEMU */ - if (riscv_cpu_is_32bit(env)) { - val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL); - } else { - val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL); + /* If nothing changed, do nothing. */ + if (val == env->misa_ext) { + return RISCV_EXCP_NONE; } /* flush translation cache */ - if (val != env->misa) { - tb_flush(env_cpu(env)); - } - - env->misa = val; - + tb_flush(env_cpu(env)); + env->misa_ext = val; return RISCV_EXCP_NONE; } diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index a7a9c0b1fe..5257df0217 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -54,10 +54,10 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) { if (n < 32) { - if (env->misa & RVD) { + if (env->misa_ext & RVD) { return gdb_get_reg64(buf, env->fpr[n]); } - if (env->misa & RVF) { + if (env->misa_ext & RVF) { return gdb_get_reg32(buf, env->fpr[n]); } /* there is hole between ft11 and fflags in fpu.xml */ @@ -191,10 +191,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; - if (env->misa & RVD) { + if (env->misa_ext & RVD) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-64bit-fpu.xml", 0); - } else if (env->misa & RVF) { + } else if (env->misa_ext & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-32bit-fpu.xml", 0); } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 16a08302da..f64b2a96c1 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -140,8 +140,8 @@ static const VMStateDescription vmstate_hyper = { const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", - .version_id = 2, - .minimum_version_id = 2, + .version_id = 3, + .minimum_version_id = 3, .fields = (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), @@ -153,8 +153,10 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), VMSTATE_UINTTL(env.priv_ver, RISCVCPU), VMSTATE_UINTTL(env.vext_ver, RISCVCPU), - VMSTATE_UINTTL(env.misa, RISCVCPU), - VMSTATE_UINTTL(env.misa_mask, RISCVCPU), + VMSTATE_UINT32(env.misa_mxl, RISCVCPU), + VMSTATE_UINT32(env.misa_ext, RISCVCPU), + VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), + VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), VMSTATE_UINT32(env.features, RISCVCPU), VMSTATE_UINTTL(env.priv, RISCVCPU), VMSTATE_UINTTL(env.virt, RISCVCPU), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d2442f0cf5..422f8ab8d0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -55,7 +55,8 @@ typedef struct DisasContext { /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; target_ulong priv_ver; - target_ulong misa; + RISCVMXL xl; + uint32_t misa_ext; uint32_t opcode; uint32_t mstatus_fs; uint32_t mstatus_hs_fs; @@ -86,7 +87,7 @@ typedef struct DisasContext { static inline bool has_ext(DisasContext *ctx, uint32_t ext) { - return ctx->misa & ext; + return ctx->misa_ext & ext; } #ifdef TARGET_RISCV32 @@ -96,7 +97,7 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) #else static inline bool is_32bit(DisasContext *ctx) { - return (ctx->misa & RV32) == RV32; + return ctx->xl == MXL_RV32; } #endif @@ -538,7 +539,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #else ctx->virt_enabled = false; #endif - ctx->misa = env->misa; + ctx->xl = env->misa_mxl; + ctx->misa_ext = env->misa_ext; ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei; ctx->vlen = cpu->cfg.vlen; From patchwork Thu Oct 7 17:47:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515457 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1408691ime; Thu, 7 Oct 2021 10:49:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxSJMpVUOVkuFoDTyyq3+zWRntg5be1GS2xfcAEedi1mguWfayoi8DyBTDln1Akg+/gj4Rf X-Received: by 2002:a37:bb85:: with SMTP id l127mr4433094qkf.433.1633628957373; Thu, 07 Oct 2021 10:49:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633628957; cv=none; d=google.com; s=arc-20160816; b=UtZ8ZAoKLImJVENOasuvpmrFw6itHHiPOu1PS6C1eVVBeT5R0AUVIhMWAnT0+Y98HW RSg2sMliNo4Rrcyk0FW3Pg/vMj0KLpTz7PF6yT87Qd+0Q75r34DEKzovyRPXGyDFG0ns YUEtRD+g0rT8XvTQFSGEDdehrzAFr1zUj7s+pUXGsREFVvMWn85QiEHs7IO2+Oz/yyfM 0K43gf2c786mxk7/nGkxcZyTXgl3Gui7QV2o58mdfv+is3QJe1GDce+RVx0sGTwRPSfp wahYmT6g8jTZkZAKKWBdMTkTsOOV3qDXGnncLpaam4cCSpOVaebHqvB/EhV313/xulm8 2ZhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DkKVHb98ELN5JSQ/ing5GBpm0Dx1b+HnphMRCHL41ck=; b=VQcxWG/Zrzilt8UlO8XKXbTEqWCVIEFl7ucQ1XTT/3MSk3vnbqUpBjD5OfnxIo8+U+ SYhWIJBUfIuSDWZEoo/LXkNbaoOK9inMKv71hZd53Ms2WwBgHFvjCYeA0BAKuFdxyUrt r6x2lEZb+W5pDQcGn82AxeU8BGqMwvu0U5XJBU6nZV9+QXoSXWuSCsggIX5qKdjUi8P6 F41KVQXWlPFh+MXh6RVUTGktF4NKugbWngeSpgG8SwvmkioSDKr8wcwi5fBc6tC6QOxI /SaInOFECdV+AE885MUrICzxH9PSJ4DWgfPaiP+/zL5pQG4S33yFrTdNC7BljKXjdUOD +s+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=m8B63hyZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f17si47222qkg.411.2021.10.07.10.49.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Oct 2021 10:49:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=m8B63hyZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52418 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYXW8-00051f-QF for patch@linaro.org; Thu, 07 Oct 2021 13:49:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38074) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYXUS-000427-C0 for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:32 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:38625) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mYXUO-0006r0-KH for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:32 -0400 Received: by mail-pf1-x42c.google.com with SMTP id k26so5966799pfi.5 for ; Thu, 07 Oct 2021 10:47:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DkKVHb98ELN5JSQ/ing5GBpm0Dx1b+HnphMRCHL41ck=; b=m8B63hyZE0d1WEBJfoqSTC5l9wYhXyP7mnm9FBn2gFZ39X2A/3MHs2l6Apo/crlFaT yPrk7b7My77VfDdXUe4n/HgsFKJ6QPzqwqq0vLUYHxa4dd0aiC1PNER15zE21FAq3sSg 5TIlt2cDTlolcaKnhaD9AoPcmeh/e0gX8asrQXuCpK59FcP8MzgwFDame9gzPMu/H8zX 1q4RTmVUP0xbHmIeQOTyrHtI9a0VUuMhKQztQhFdfYny9tBWVD+zJ1ijg8UqiQdEazXv u4XHbpNiFMghdUPGlvaFLUwvm/lvDpiNyPCs2cd8yJGKL+e9gUuRoEfDcVgFITwP8Rcv VEaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DkKVHb98ELN5JSQ/ing5GBpm0Dx1b+HnphMRCHL41ck=; b=btM+XH8yTsgPjA55tCwUSMzL4dDR4H2kvSF7EoQMTZkP3NvChe2VcEFCXvpKvitIF7 F/l+uG90QCK8wCcBdPR3ZaFOFHhlp67fR7NRg/nZ7a4evNOE+6e4l1jEvHDul8mpgOo0 7ep6tY1m/XgpGWQQsDa7cExksbA7HmwAlSE6PtrZJy48jtIZmkrEAe1nZjphgbb7wV5v f8AonVPHDc2hVyCizlmdLZZJyUdbh217OnqQsPlJL6+AgCohzizoEcw+fUNL41NkaNo3 qdzIKouEazzdzAngpr8+S8X50OHdx/XqbEuPBbcbWvUul2KUTfsb3QY1WtKFzpwDyEq0 mNfQ== X-Gm-Message-State: AOAM532WqrnuM7cZYQ7kYGyeFAklowIfPjUkNxaayTJuhN3vs9iz4Alx rNOeeAunP74dphgsOor1oXmBq6r9vgtNWg== X-Received: by 2002:a63:4456:: with SMTP id t22mr751961pgk.451.1633628847118; Thu, 07 Oct 2021 10:47:27 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id 197sm83318pfv.6.2021.10.07.10.47.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 10:47:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Date: Thu, 7 Oct 2021 10:47:13 -0700 Message-Id: <20211007174722.929993-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org> References: <20211007174722.929993-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Shortly, the set of supported XL will not be just 32 and 64, and representing that properly using the enumeration will be imperative. Two places, booting and gdb, intentionally use misa_mxl_max to emphasize the use of the reset value of misa.mxl, and not the current cpu state. Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 9 ++++++++- hw/riscv/boot.c | 2 +- semihosting/arm-compat-semi.c | 2 +- target/riscv/cpu.c | 24 ++++++++++++++---------- target/riscv/cpu_helper.c | 12 ++++++------ target/riscv/csr.c | 24 ++++++++++++------------ target/riscv/gdbstub.c | 2 +- target/riscv/monitor.c | 4 ++-- 8 files changed, 45 insertions(+), 34 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e708fcc168..87248b562a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -396,7 +396,14 @@ FIELD(TB_FLAGS, VILL, 8, 1) FIELD(TB_FLAGS, HLSX, 9, 1) FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2) -bool riscv_cpu_is_32bit(CPURISCVState *env); +#ifdef CONFIG_RISCV32 +#define riscv_cpu_mxl(env) MXL_RV32 +#else +static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) +{ + return env->misa_mxl; +} +#endif /* * A simplification for VLMAX diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 993bf89064..d1ffc7b56c 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -35,7 +35,7 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) { - return riscv_cpu_is_32bit(&harts->harts[0].env); + return harts->harts[0].env.misa_mxl_max == MXL_RV32; } target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index 01badea99c..37963becae 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -775,7 +775,7 @@ static inline bool is_64bit_semihosting(CPUArchState *env) #if defined(TARGET_ARM) return is_a64(env); #elif defined(TARGET_RISCV) - return !riscv_cpu_is_32bit(env); + return riscv_cpu_mxl(env) != MXL_RV32; #else #error un-handled architecture #endif diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 768fea6859..7b9aaef0a6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -108,11 +108,6 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) } } -bool riscv_cpu_is_32bit(CPURISCVState *env) -{ - return env->misa_mxl == MXL_RV32; -} - static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) { env->misa_mxl_max = env->misa_mxl = mxl; @@ -249,7 +244,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", (target_ulong)(env->mstatus >> 32)); } @@ -371,10 +366,16 @@ static void riscv_cpu_reset(DeviceState *dev) static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) { RISCVCPU *cpu = RISCV_CPU(s); - if (riscv_cpu_is_32bit(&cpu->env)) { + + switch (riscv_cpu_mxl(&cpu->env)) { + case MXL_RV32: info->print_insn = print_insn_riscv32; - } else { + break; + case MXL_RV64: info->print_insn = print_insn_riscv64; + break; + default: + g_assert_not_reached(); } } @@ -630,10 +631,13 @@ static gchar *riscv_gdb_arch_name(CPUState *cs) RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; - if (riscv_cpu_is_32bit(env)) { + switch (riscv_cpu_mxl(env)) { + case MXL_RV32: return g_strdup("riscv:rv32"); - } else { + case MXL_RV64: return g_strdup("riscv:rv64"); + default: + g_assert_not_reached(); } } diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 14d1d3cb72..403f54171d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -152,7 +152,7 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { - uint64_t sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD; + uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD; uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | MSTATUS64_UXL | sd; @@ -447,7 +447,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, if (first_stage == true) { if (use_background) { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; vm = get_field(env->vsatp, SATP32_MODE); } else { @@ -455,7 +455,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, vm = get_field(env->vsatp, SATP64_MODE); } } else { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; vm = get_field(env->satp, SATP32_MODE); } else { @@ -465,7 +465,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, } widened = 0; } else { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; vm = get_field(env->hgatp, SATP32_MODE); } else { @@ -558,7 +558,7 @@ restart: } target_ulong pte; - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { pte = address_space_ldl(cs->as, pte_addr, attrs, &res); } else { pte = address_space_ldq(cs->as, pte_addr, attrs, &res); @@ -678,7 +678,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, int page_fault_exceptions, vm; uint64_t stap_mode; - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { stap_mode = SATP32_MODE; } else { stap_mode = SATP64_MODE; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d0c86a300d..9c0753bc8b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -95,7 +95,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; } - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { switch (csrno) { case CSR_CYCLEH: if (!get_field(env->hcounteren, COUNTEREN_CY) && @@ -130,7 +130,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) static RISCVException ctr32(CPURISCVState *env, int csrno) { - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { return RISCV_EXCP_ILLEGAL_INST; } @@ -145,7 +145,7 @@ static RISCVException any(CPURISCVState *env, int csrno) static RISCVException any32(CPURISCVState *env, int csrno) { - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { return RISCV_EXCP_ILLEGAL_INST; } @@ -180,7 +180,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno) static RISCVException hmode32(CPURISCVState *env, int csrno) { - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { if (riscv_cpu_virt_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; } else { @@ -486,7 +486,7 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, static int validate_vm(CPURISCVState *env, target_ulong vm) { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { return valid_vm_1_10_32[vm & 0xf]; } else { return valid_vm_1_10_64[vm & 0xf]; @@ -510,7 +510,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | MSTATUS_TW; - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { /* * RV32: MPV and GVA are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. @@ -522,7 +522,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | ((mstatus & MSTATUS_XS) == MSTATUS_XS); - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { mstatus = set_field(mstatus, MSTATUS32_SD, dirty); } else { mstatus = set_field(mstatus, MSTATUS64_SD, dirty); @@ -795,7 +795,7 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno, { target_ulong mask = (sstatus_v1_10_mask); - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { mask |= SSTATUS32_SD; } else { mask |= SSTATUS64_SD; @@ -1006,7 +1006,7 @@ static RISCVException write_satp(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { vm = validate_vm(env, get_field(val, SATP32_MODE)); mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); asid = (val ^ env->satp) & SATP32_ASID; @@ -1034,7 +1034,7 @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) { *val = env->hstatus; - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { /* We only support 64-bit VSXL */ *val = set_field(*val, HSTATUS_VSXL, 2); } @@ -1047,7 +1047,7 @@ static RISCVException write_hstatus(CPURISCVState *env, int csrno, target_ulong val) { env->hstatus = val; - if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) { + if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); } if (get_field(val, HSTATUS_VSBE) != 0) { @@ -1215,7 +1215,7 @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno, return RISCV_EXCP_ILLEGAL_INST; } - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); } else { env->htimedelta = val; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 5257df0217..23429179e2 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -161,7 +161,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) CPURISCVState *env = &cpu->env; GString *s = g_string_new(NULL); riscv_csr_predicate_fn predicate; - int bitsize = riscv_cpu_is_32bit(env) ? 32 : 64; + int bitsize = 16 << env->misa_mxl_max; int i; g_string_printf(s, ""); diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index f7e6ea72b3..7efb4b62c1 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -150,7 +150,7 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env) target_ulong last_size; int last_attr; - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; vm = get_field(env->satp, SATP32_MODE); } else { @@ -220,7 +220,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) return; } - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { if (!(env->satp & SATP32_MODE)) { monitor_printf(mon, "No translation or protection\n"); return; From patchwork Thu Oct 7 17:47:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515461 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1411287ime; Thu, 7 Oct 2021 10:52:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzkO2+TG2eL0cdLUuLJP4g7numHE3WqnDEpWNBCRfWce+OkUFeKe/hSAZVuL2R4kYkjDaTL X-Received: by 2002:ac8:431e:: with SMTP id z30mr6559477qtm.192.1633629171675; Thu, 07 Oct 2021 10:52:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633629171; cv=none; d=google.com; s=arc-20160816; b=Rq3ARyzW/Ooc2RCTqAOD1aQZ9uxm/rNgk1HfwBLL8dAShvhEVd7fp1q36zWhybBzCo Qoc4wspC3vY7sVZi6w1cxxOYUzqaSB16H4H8XomyUbwo4D0rxI/nCkDKLpE596HrYb0p 4q5YCc6kzFAWjK/AaLxajM7uAnXo3lMBwDC6PCldW2uWcMLhkLTlgYckpIiMhirmp+NI 3QMNeecOEEoFWXb/QiDvkfUMQhgOvZed1p7tg9Xawrk3FUQh6Iw1VDW1SB2AHWYuy+Bb 0dRwAWgjtRS2/9p5o51cH/GWqr43m7D2XsYq8H3rb2FcrLmz6NG47rU4V44QVDCj6X/u Wn5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OjRGfpVPKULWg/qA8nsYIOw1P9JnLXCdc48XaUFRhzo=; b=H5ettpYBrY+Qhz8PSAxGMNdKHH0TjbL98hQeQUD5N/yuH78jR2dBGijRemfH4s7D28 RMIYaB8JdF02SuPzlCrjXl7u+0ADkHQUZi/D37wjdg36FQtXkzDuKQaFbMrct5wf8K8h dSuq1qDrB7JUhDEQJHoaVT93QE5u4akb5GMWIdRpXLlXi7EjOdQ9TGh9PbGRkJX/vvxV qLV4nC++NTy1ZbKSuUSAJAX39n4MUjHtxNE2xHlJOdc9xs95YXsL0QMUvzRBkWkbLEHt wVY4MYJkUbIjEfFIxeiki/VZPzOdUqNEx5qNeZ44x1+90pkZe9bSPAhySuti73imG4RR JXHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="YP/uFF/A"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ke6si125979qvb.150.2021.10.07.10.52.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Oct 2021 10:52:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="YP/uFF/A"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33606 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYXZb-00034a-6n for patch@linaro.org; Thu, 07 Oct 2021 13:52:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38152) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYXUV-00043b-5z for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:39 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:34389) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mYXUP-0006rd-7n for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:33 -0400 Received: by mail-pl1-x631.google.com with SMTP id g5so1360348plg.1 for ; Thu, 07 Oct 2021 10:47:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OjRGfpVPKULWg/qA8nsYIOw1P9JnLXCdc48XaUFRhzo=; b=YP/uFF/Ar2YizNlSvxODd4LVwR5sqqffy6rcEMe/6bku3luUXoCA3Zl++U3Nu5FDXN 5CEP0C1klURVKb5pzsanltG4gK/aH+H9x6036m3XCBn765fSHcRAthj1Vg/5eBTEDora RRF1WcAB5/McOqWqcXYo/yEBNwBqwfGSIg4MqoDPBGQ9sMxufHJDAbySrkEn8lr9Wfa5 8TpjcUoCW8MWvnKtHW5/76v8+76fm5KU21yuDH3exx3Ag0qsu1m2DzOyumn8AWjKYk2Z 4b2SIbAam60Aejmys3K95HrbEwc4xBMKDPesBsqcibfR7n8BYitbVVs4ObLZbgnr1Era BgqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OjRGfpVPKULWg/qA8nsYIOw1P9JnLXCdc48XaUFRhzo=; b=cJmEDijcJBA0Y+jFpSiljBMTPiMXHWLMfiy2QJyCgbG6/h8YLoTNVjawzHPzheRruD Tk06mROZtqNqTAdyiBxkc6F/Wzh2hJU1LJxqGBtMFwl04KWeyk5o6Rj8b6NRmuctiwVZ AqAozKADS+kKUxpzdJ888dY/XV0JFT8HeOIXU0voN/mtIwZHH//bemzh0qXY9830UDWl HPxNEYFj4gON8o2bn1jYQNOKNaJhe0b/kpoCWS+PuQUmCK62ZUWNt2xpeSW6uJTbaR1x 4HC1B0WsL0yhzPXo4zFF8DiuovfHZXfwoD3Hj4nznQVcuhuKyGu9R3KvqYiXTVC9ZUjE Ftkw== X-Gm-Message-State: AOAM533CLGOQYhGpKNTrdgwvuUHVyyIQKU9oPNLG8oLfpMRmEgKkC8qD 4G9/2QcrJh0UeO5p3DFwo0MJ+lFJyjt+CA== X-Received: by 2002:a17:90a:7e82:: with SMTP id j2mr6314534pjl.165.1633628847915; Thu, 07 Oct 2021 10:47:27 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id 197sm83318pfv.6.2021.10.07.10.47.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 10:47:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Date: Thu, 7 Oct 2021 10:47:14 -0700 Message-Id: <20211007174722.929993-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org> References: <20211007174722.929993-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Begin adding support for switching XLEN at runtime. Extract the effective XLEN from MISA and MSTATUS and store for use during translation. Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 33 +++++++++++++++++++++++++++++++++ target/riscv/translate.c | 2 +- 3 files changed, 36 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 87248b562a..445ba5b395 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -395,6 +395,8 @@ FIELD(TB_FLAGS, VILL, 8, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 9, 1) FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2) +/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ +FIELD(TB_FLAGS, XL, 12, 2) #ifdef CONFIG_RISCV32 #define riscv_cpu_mxl(env) MXL_RV32 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 403f54171d..429afd1f48 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -35,6 +35,37 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } +static RISCVMXL cpu_get_xl(CPURISCVState *env) +{ +#if defined(TARGET_RISCV32) + return MXL_RV32; +#elif defined(CONFIG_USER_ONLY) + return MXL_RV64; +#else + RISCVMXL xl = riscv_cpu_mxl(env); + + /* + * When emulating a 32-bit-only cpu, use RV32. + * When emulating a 64-bit cpu, and MXL has been reduced to RV32, + * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened + * back to RV64 for lower privs. + */ + if (xl != MXL_RV32) { + switch (env->priv) { + case PRV_M: + break; + case PRV_U: + xl = get_field(env->mstatus, MSTATUS64_UXL); + break; + default: /* PRV_S | PRV_H */ + xl = get_field(env->mstatus, MSTATUS64_SXL); + break; + } + } + return xl; +#endif +} + void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -78,6 +109,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, } #endif + flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env)); + *pflags = flags; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 422f8ab8d0..7e7bb67d15 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -539,7 +539,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #else ctx->virt_enabled = false; #endif - ctx->xl = env->misa_mxl; ctx->misa_ext = env->misa_ext; ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei; @@ -551,6 +550,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); + ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->cs = cs; ctx->w = false; ctx->ntemp = 0; From patchwork Thu Oct 7 17:47:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515466 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1416188ime; Thu, 7 Oct 2021 11:00:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyRWnttVPzYEJ7vgxRBxLSdU6kxLwyIiZG76PK3L0iWQH4hzoJ/7cp+UvbDJ/YVHxXiuuMM X-Received: by 2002:a37:8787:: with SMTP id j129mr4453224qkd.487.1633629615394; Thu, 07 Oct 2021 11:00:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633629615; cv=none; d=google.com; s=arc-20160816; b=H44mNu+JyBFlXWhCr7rMfZY3DcQX5PK2KcXrqfmqu6RtPCqGPCPSAxbDR4qYg6RmF/ dzNxYa/p7zPYQjkVSPdvQwiQGFsAyUBTczEWhOWjBPo6SfutRz93fLF/7DbZFC2lwbo5 x3vmzPbf4KfpdIOsdVZ+07ShvfgCd6a+2Lhc+40Wyy13SKf0tr20SPzpj2MEE2PGkElF mhyhJqyBZZWJXizCqd9LdbtL+EbtQEhUp4HiHYhjAdhZxpLibUriUfDJtYPfN69Br2HO lL4wdy7Omm8mJkovnC1U4PO4F8iYhxom6MAkMXv6BrfXumMIIJj62DZm/c7cZaMUqM2r hHzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HrXgWQxe5rXDfowZg2OUbllL3iUHpHaeDyMxH/BRtUg=; b=Y8SNv1Fb+S4YYzuH0YmSG/+iMEIPlede9ClC7yMrD6Wl4n44TVc9hw/Tynv5BVdJLu sxygu+dIEzu3wXHCl9LjRUi3Hen+BUfGM5x3G9EWTWm2ODT7pxDC0xuO1N/hmIgyRV5/ mN1Lbryh58wVIoBrfTnZwDcZ5WvFkrfiHfRWechU5EdBJSnFUw37W1obXMXGgRg0HP75 o9635su+qVZbTd/5Aqhliybhi2znAL1xHSDsw3y3N8gXmvKXghIwok6rwdH6dD965RBT 2YV6BwOYhQVq5KAHzGYZVtfKAt0MtoqbxnJfCgEBHb9PCtPNcPFiBfI7zcJzsJw456Gh VbIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dYJQabii; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id jk8si1307qvb.236.2021.10.07.11.00.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Oct 2021 11:00:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dYJQabii; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57794 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYXgk-0002Lh-SE for patch@linaro.org; Thu, 07 Oct 2021 14:00:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38164) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYXUV-00043h-9B for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:39 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:46695) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mYXUP-0006sc-Uv for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:33 -0400 Received: by mail-pl1-x62a.google.com with SMTP id w11so4364882plz.13 for ; Thu, 07 Oct 2021 10:47:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HrXgWQxe5rXDfowZg2OUbllL3iUHpHaeDyMxH/BRtUg=; b=dYJQabiiOiy8WlfGMyJ7Hpy9wz6gMdnuucUOLUhfFSYVG64KwaGQB3limVpj7c2s4P 86os2QRDbjK0Ymj5akuDuLQxhaSLKhsfCJbjEw008p7YFozebIIcuCKdbmibX6d4J+q5 kTlOvH+Ppl4PfdiJ7PvxONjiY+dfazZTG43j1W6N+WIYwfDLzD4czyRkhpe72YHUlh2u ySvF6He5Jhx+3knuMI0PhJUwB0qzsbdykOSXD7x/oUGH1iH5jUtStwtNFXPdL1+0OleE I/yoWIGFK5IODHRDqTsG1RRhnFHxf8NBmNDxHvRb0IdyOY/EQKJW6HPY9Jv36tFilxR9 a9iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HrXgWQxe5rXDfowZg2OUbllL3iUHpHaeDyMxH/BRtUg=; b=Cg51sxvTYWVcA7PLCv6Nn3H8G9a4aEt0m82VtsIMaHc1AlKIkorUbmqQpFjWBCiU++ enpwJppvCNFt8KBd2oOPmLjra3Qr90qiXKHyLjDBO/mEC2ZuLj0LoSzcPaf0dcvTKrTy H43Su6AU+LXpo0x+R48xrkIZ3Z7xjd4Qg/ltVUe+wQvB48sxBu5Z7H9sfRzHGJF25uaL wsSFemJLbKSzhHWniAYdNLBY+n0EkMNVDS77MG4+ZndcLNUrNIZF7g4+Ma97cVrwbEJr hh0mBul5Y3e01vQBbi7z3wzHdDpwjZN04DZYxM/zSMg6dLQjBjEYZxoXZrEfCBAzF1EY JOSA== X-Gm-Message-State: AOAM533F1sbsMTBqvckC9YTDEeOrrpWo9yQZdPCAwa6uXZelSvBLWeyw ASovkffXGeqcSIaBfOHD+atAVBu62VEEHQ== X-Received: by 2002:a17:902:8d8c:b0:13d:be20:e279 with SMTP id v12-20020a1709028d8c00b0013dbe20e279mr5017960plo.5.1633628848591; Thu, 07 Oct 2021 10:47:28 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id 197sm83318pfv.6.2021.10.07.10.47.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 10:47:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64 Date: Thu, 7 Oct 2021 10:47:15 -0700 Message-Id: <20211007174722.929993-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org> References: <20211007174722.929993-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the same REQUIRE_64BIT check that we use elsewhere, rather than open-coding the use of is_32bit. Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index fa451938f1..bbc5c93ef1 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -743,7 +743,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a) static bool amo_check64(DisasContext *s, arg_rwdvm* a) { - return !is_32bit(s) && amo_check(s, a); + REQUIRE_64BIT(s); + return amo_check(s, a); } GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check) From patchwork Thu Oct 7 17:47:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515465 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1414675ime; Thu, 7 Oct 2021 10:57:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyvZFg4enPD/xto+5BGNLsvf9dX/Iur+06zOlBkQ9D+s4ekb+pQvZY7tZs2YU0MPiiY/0SM X-Received: by 2002:a37:6d6:: with SMTP id 205mr4377747qkg.417.1633629474638; Thu, 07 Oct 2021 10:57:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633629474; cv=none; d=google.com; s=arc-20160816; b=dDp11cg8bX65Y3b/7x3Afu6Ics3+4weFeT4iP9AEm5OdYUcVKSzJUkdO0+4DcnWdE8 Jd3p/HzHvtfjyNUOrCnS12292czenuVI8Ukq7d/dG/ToHVOTE6yq9KOCtGD/Iq6Uk/OK r7KfAerd3eMK8e/K8ZeuK2xlbzdJ+0/3IevVoxkFF0bRfY4ID9xwvbbDLJvuBj5ppuIw 7893QsjyjsXVQifqSoRvZKfSSbQYRPodHTnCwtrO8WFvLborWGqwqHIEBNhsZBQ+exLN fiR2HyQLbc5y9reob+I24msOHvwaMiKg8Ogyh1dafoxxMP4ryqrS7V2Hu201ldSZu1AM iQ1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=D7b+ydnd4zMrVyDCywxRov6Sf650NgZr4E9SJVFsXBA=; b=vfrbuSnB7OaEcf9l+d862658NYFPYs5TmeXXdZfpbSRVIXeQe+t9/+pSUfh3pNZmSg KoK4y3LTQEnbNW7SWdDEaFpth5WPH/FX1A4eFdkbNOWhfNA7Qs+hQeD4NWSJLgiN/6vZ 66q/vrKF6bAj5Yc5GppBYcnopzd9be/dKeWYssDouW9ZhuN+vzNjbi7ssJv+w5SwXxyi Et2ySR0VJLqcZ1rN+vvcWk0hHj4Ke+b9rDs/AfhP5BNDQcDP7DbW2Cxmxa8+OT77TMaR MWJRtQa3qUU5DNomweZOWnjRcOwi2aenrkmREgRqKBMl7wI0fqiMtQPH3/GOASVGs6Vc bR/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FHV9yYFJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id cv8si19904qvb.9.2021.10.07.10.57.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Oct 2021 10:57:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FHV9yYFJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49290 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYXeU-000579-5W for patch@linaro.org; Thu, 07 Oct 2021 13:57:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38156) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYXUV-00043e-71 for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:39 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:40899) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mYXUR-0006tT-NT for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:34 -0400 Received: by mail-pl1-x62f.google.com with SMTP id j15so4424579plh.7 for ; Thu, 07 Oct 2021 10:47:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D7b+ydnd4zMrVyDCywxRov6Sf650NgZr4E9SJVFsXBA=; b=FHV9yYFJPv4guJVXkntYu4zWE5YrpuTZUSgZ9nJEVFHqqVzW0MTA57t0yv4XAF7VJ1 iUML6/Jo37U961AYGE+wl9CabLdUOGiolI17jD1cnQ5ABACrnXoakg1V78J++4m1V0tP NI4k2uexqwjFgLhnoVGqgZFLFzhiGVpo4fVXtJacv4rBAvNYMIVcf+RuzPXpDkXNIuF/ WT3gE9gkmI13SKPRnIzmEUmACWDkRQZntH4+nerOylWYAM0Sw61+niS0VBBN9b1qnEhu wZPmetJdlV82I2FP15kD7MYwvooSVdnYGsqeThsa8pViDd0MrnkI5uWC22b9KpKA8aRW TlHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D7b+ydnd4zMrVyDCywxRov6Sf650NgZr4E9SJVFsXBA=; b=PZt2/Jd4rB23JGdKl4MVpcRE+WHXumbaXGMcMNPDI2qaXKieZidxGwTZFbsS1Zm2IN 5pcLiVxO+NZoD8ptSecCpidHsBCUqahIupiQDZUi+y8r4BXLHnvcCl594LUhgn+c8gCh Z0an8lTc2o5oCpohytmL3wxbThiPy+6wkwgxpRZu4jVFEMFRe7fjLe7V/cMKKtCtUi8j O+74uT2jMW/w3wIzHur7JsvhU47b+dl18Bw3KolAFFpmvH6r5ZPy1ANeCxkPuaWnUceH L3fwTKiLQLK6fcNp99y5qC9KEoKKJvwLbOXfDB0ToPjgEvLaxC7gbYWCSZ+BudUmh3ak 5wJg== X-Gm-Message-State: AOAM532kh6kJg4tbwzS6sUlqJ8pX6tfg7tTJlYsvzsIo1OnA+3vvmKFO xAEADeUKe87xDsCKQ0oiwXGF06x5/U03Pg== X-Received: by 2002:a17:903:2403:b0:13d:cef7:61f1 with SMTP id e3-20020a170903240300b0013dcef761f1mr5209951plo.48.1633628849388; Thu, 07 Oct 2021 10:47:29 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id 197sm83318pfv.6.2021.10.07.10.47.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 10:47:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 07/13] target/riscv: Properly check SEW in amo_op Date: Thu, 7 Oct 2021 10:47:16 -0700 Message-Id: <20211007174722.929993-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org> References: <20211007174722.929993-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We're currently assuming SEW <= 3, and the "else" from the SEW == 3 must be less. Use a switch and explicitly bound both SEW and SEQ for all cases. Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 26 +++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index bbc5c93ef1..91fca4a2d1 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -704,18 +704,20 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq) gen_helper_exit_atomic(cpu_env); s->base.is_jmp = DISAS_NORETURN; return true; - } else { - if (s->sew == 3) { - if (!is_32bit(s)) { - fn = fnsd[seq]; - } else { - /* Check done in amo_check(). */ - g_assert_not_reached(); - } - } else { - assert(seq < ARRAY_SIZE(fnsw)); - fn = fnsw[seq]; - } + } + + switch (s->sew) { + case 0 ... 2: + assert(seq < ARRAY_SIZE(fnsw)); + fn = fnsw[seq]; + break; + case 3: + /* XLEN check done in amo_check(). */ + assert(seq < ARRAY_SIZE(fnsd)); + fn = fnsd[seq]; + break; + default: + g_assert_not_reached(); } data = FIELD_DP32(data, VDATA, MLEN, s->mlen); From patchwork Thu Oct 7 17:47:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515463 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1412835ime; Thu, 7 Oct 2021 10:55:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyEZQHrsdK/Y4CP28/2QgyxYXoAJFUciaNTPwZqV0hr4Ko6I0TWuhcT+MPfpW1juLHx4q5t X-Received: by 2002:ad4:4e72:: with SMTP id ec18mr4110018qvb.45.1633629311482; Thu, 07 Oct 2021 10:55:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633629311; cv=none; d=google.com; s=arc-20160816; b=bTYdfTG2+hnoCocwCIaknOeglJZK/UW+CeTCg0BCpW2JLU5O+MecxjQtxP/sKabarI m3mlOzhgWU2HzWe1Mtrj1oCjSZYdMMW6W5oOP80U3n+J4705Zv2PPbXECqekOiXgbb3y gU3BsS6dnmy+cxpw2ewFFksLXKftzQZQhRI9bgRI6zN/V3Hzc0R1Qx6oBfIku4gdHHft A7bY9fHDbe+qxqGDbhdRVctXdYVwzAzBChwd/dUyQE6a1XCGjTE91aosOcECekveEnXm KDRWe0DN/qyS11MVJ5oikXiCC6t0U0wREeSVDclYw/PZmIWAWqx7kJSdVCmyU7PPZA5t 2BPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=H87ppfQkVyn08RbjkKfsggea9i4sKXYDOxyW8HmfWE8=; b=GPuUwX83PZ88ZNpY7NpSEst7fDdMYSJOujUS++CIeCicivoM/7CuNPWRkHtyYOMj3L mZeVg5TgdnQnv5GTcKT4TE9IfYhM5WR0rUe1dDENFLQlOLkMwGmdwWq3wo5sd9HsOlzR rpXMnx6W3158eNeNdTA0piEGg01lC5jEInEhMSWtERS/vfGAl4fZOXh5sQDNdJqm6unH UOAcy1rpnhiTfm8hw3LXDg7c9rqxGzf4RLOh/nlE8fxyaih5DET67hPIxYDILrJQ5v2s veNZ/F+eQVJsgS4MDyHf7DUEMVRfhLjA9nqH2ZCVi6ZNQZEyykD2xBBKlbXX5rHQi3xl veAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fV0kqIUD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a9si59889qtn.211.2021.10.07.10.55.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Oct 2021 10:55:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fV0kqIUD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41872 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYXbr-00005M-11 for patch@linaro.org; Thu, 07 Oct 2021 13:55:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38158) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYXUV-00043f-6n for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:39 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:46985) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mYXUR-0006uB-Re for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:34 -0400 Received: by mail-pj1-x1031.google.com with SMTP id pi19-20020a17090b1e5300b0019fdd3557d3so5696184pjb.5 for ; Thu, 07 Oct 2021 10:47:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H87ppfQkVyn08RbjkKfsggea9i4sKXYDOxyW8HmfWE8=; b=fV0kqIUDiKSKvCiP1Ww839PeyZJXTJJg5selSPtXja45mDHsH5F1LaJvvmNZJQc+b5 l9V7hgQ2fE6v0drMW+0i+i8h0ikxEOGerm7PoRTGse2ldigbTNpwiPc2rfzclf9wlmNc kKPf5FdtL1+Q0ROw6QZQRZW09JeKdlrcD61J/wfvvIfYL7g5naoWU7MkCqES3TecEjFW Y3/2YV4QJ1wg0xRA6qaBPZRWcG0z4478xlVXBtjmZPtFNQh5uzWBZnxeH82d01rKIapd 33TnOyMrTajAurHWy4JSvdIX9u7kc0XvP/5rrLG+Cgop5r3e9SoU5XmtsbV2z9Ygwmwf pjhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H87ppfQkVyn08RbjkKfsggea9i4sKXYDOxyW8HmfWE8=; b=kXpk4xNQLSMxstDY8LpqXm0OOgn2osTJ7CJ3MK0Nbm/QNmu6Y7HCvVMRfaBl1eMpea sLoXOLWc+av67S6iLjCuRGYfaeoxb0efX/WycmcTiwiRi3NBY/NvPAD2aHxVpQw2QdbC ul5Uc3wUK/rUoxGPckblzQjvm1ElUktu1OMoyfz6MLtXF/LfDfOC7cwMlnF6p+oKTRgW jF1UuQtOxmr7nisLu/wToISlOdA/r9WudHIqMYxIfPYFxQzuiqrWW45dNeUT6qNJBXzv X9AbAtwQPFUxbyt/xh6q3p/5qAWbGU7XixuU2bov1E28GKCI50mQm34g2JzwigSnKtso bcJQ== X-Gm-Message-State: AOAM531mj51MNILf0nkOZuGznQeEpJCdnIzOx40vidGSxtW0oSK7dupz jea7oGNTyv00RlttTL6x/oYvESRn3CLeYQ== X-Received: by 2002:a17:90b:4f4b:: with SMTP id pj11mr6456275pjb.4.1633628850162; Thu, 07 Oct 2021 10:47:30 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id 197sm83318pfv.6.2021.10.07.10.47.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 10:47:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen Date: Thu, 7 Oct 2021 10:47:17 -0700 Message-Id: <20211007174722.929993-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org> References: <20211007174722.929993-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for RV128, replace a simple predicate with a more versatile test. Signed-off-by: Richard Henderson --- target/riscv/translate.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 7e7bb67d15..5724a62bb0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -91,16 +91,18 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) } #ifdef TARGET_RISCV32 -# define is_32bit(ctx) true +#define get_xl(ctx) MXL_RV32 #elif defined(CONFIG_USER_ONLY) -# define is_32bit(ctx) false +#define get_xl(ctx) MXL_RV64 #else -static inline bool is_32bit(DisasContext *ctx) -{ - return ctx->xl == MXL_RV32; -} +#define get_xl(ctx) ((ctx)->xl) #endif +static inline int get_xlen(DisasContext *ctx) +{ + return 16 << get_xl(ctx); +} + /* The word size for this operation. */ static inline int oper_len(DisasContext *ctx) { @@ -282,7 +284,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) static void mark_fs_dirty(DisasContext *ctx) { TCGv tmp; - target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD; + target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD; if (ctx->mstatus_fs != MSTATUS_FS) { /* Remember the state change for the rest of the TB. */ @@ -341,16 +343,16 @@ EX_SH(12) } \ } while (0) -#define REQUIRE_32BIT(ctx) do { \ - if (!is_32bit(ctx)) { \ - return false; \ - } \ +#define REQUIRE_32BIT(ctx) do { \ + if (get_xl(ctx) != MXL_RV32) { \ + return false; \ + } \ } while (0) -#define REQUIRE_64BIT(ctx) do { \ - if (is_32bit(ctx)) { \ - return false; \ - } \ +#define REQUIRE_64BIT(ctx) do { \ + if (get_xl(ctx) < MXL_RV64) { \ + return false; \ + } \ } while (0) static int ex_rvc_register(DisasContext *ctx, int reg) From patchwork Thu Oct 7 17:47:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515467 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1419693ime; Thu, 7 Oct 2021 11:04:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxSInRKSPvBC/wqSR1cbmsmWQ0YAWQ+hcuEY3d54vvKbI/faspTFDH1Q2zXuh7P6nsFWpoI X-Received: by 2002:ad4:5621:: with SMTP id cb1mr5568451qvb.6.1633629869339; Thu, 07 Oct 2021 11:04:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633629869; cv=none; d=google.com; s=arc-20160816; b=BP15NW5hlTEAvklSfRoFpvdndj5QM+oRT8CcW3x3UCEnyhY1lfoIhuRVX2weBO3iUM MM7k3COEqacWLrpvdoyF3RAKd6HgPJukms89wdkXudrdWb/0rFiQVMyNyJzAvNfFbIeG 0NXP7qD11OFQJSZjxgcR2lnUg/keppcU0mORWbRU2oU7PNlKCzf34dljoDOjMNvb87J1 RCOHAkuViul1iQ/xUOHTmipVafxNeZegd/A4nzuTqWYK8c/dtg6gr4D89dnPpBMSacDV P/5h0Ge+UE3JLRS1dYKM2LJljlhpscwkAWmD7RRyo1d7fdpdkxoOL5OrCiuMWFhWv/WF zBzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5BmUKj5ZFDfEAmKDg/dVXECTi9BNeky+S0S3T1g9RSg=; b=o1NPB33fq2jQAOq4A2seBzu4poXZxdBIYBaLuRXTWemZtEJJz3HilNSEsmVg7Nj8G3 i5fc6V4To510ppHaVfLTX50VocYMqC8JP71RkeC+/9E9qrdiDoQo47ahYZQWKY1UL/TC gjpbcnukBqewa9v2Ov1T20BrGvRfX9yKMdXfkIsLh5LE4xFLyriaPOGWzU1m6fcQdmSY +OOSvOHx3jutHK2e4jv6yGtKOxb3B3QEcUTmFQv+2dWu0qoPty1yuejzwC78v/UUTmDD YU4vz4YoHWEOH/4blYJ7q/PnDpkpnOYnBwnvhUhV4B2ViL4Tkwcl7u+WLMq18E0BM7ff Jl+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cyNp8v5A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 15si89309qtu.119.2021.10.07.11.04.29 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Oct 2021 11:04:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cyNp8v5A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37528 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYXkq-0007km-L0 for patch@linaro.org; Thu, 07 Oct 2021 14:04:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38224) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYXUX-00043p-9b for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:40 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:50762) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mYXUS-0006v0-8V for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:35 -0400 Received: by mail-pj1-x102f.google.com with SMTP id k23so5502098pji.0 for ; Thu, 07 Oct 2021 10:47:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5BmUKj5ZFDfEAmKDg/dVXECTi9BNeky+S0S3T1g9RSg=; b=cyNp8v5AXOK1MgTlXj5kiGWHUdbfsL0ntCkGQy3J+dCxnsij73eABBNe+bFUIYxH2c KVTZ1qgSPMKGQ0ctufRhAFGTt9lPAv+DzUqKxlZNznVFIca3pKNuNPCvcQKkKrt7EihM hdvqsQh8KbfX3omoa4tx3BJmCWew3UeNcEQCLaYVw9iEAv5FSNRuwYi1Rtjg58oPw8iy JG0I3oG9mzRMXYSlcZjP1e5xtnzgh0VCAzT8OtzsdIkjGNUwG9waVdQo1Kg/rZDUjr6z I9bgKSmmm3qU6QCu2OpNBZv9GdKKgyHE90vpKdGkOSJGNLIdp3B5VAoM4fzSc6XCDnlu kOJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5BmUKj5ZFDfEAmKDg/dVXECTi9BNeky+S0S3T1g9RSg=; b=kyGfn+jg1hXVymEkVgw7cffrqXQXlx4kNyn5kcJ21KC0Dzy6XoKikZ8Zcxw0TGKxPt dFIcsJzh9l9khDbChwq3Art9E7yGSXM7a3++5aKjODcNkfvLckHVbsgctwVqPa5V3MXC K5n6rpRT+c/SXinroXi+7Orkghcr5aKbqKdwrXZ95Uz6t4hSCQYwUqZD/2yRznXdIzU6 vJzAEw0VQY5c4nC3iszP2Bow24l4t0USSpeVGlTTuJ9KYNBKCEgIOjhPbPC1mVABJRRt bwhbQodc+ITEbjVe7MTiWzyWQdvFGai6DXi/KLISB5jkptMtxXonL9U60wWOEhaSy9ox VxXw== X-Gm-Message-State: AOAM530B2ih+QLyKsmIHkF5isXYAwQuO54ZzTIkn+euOGetDUWtPuDo3 QG1kkq53BJOHhFMECvJ98QmzbJkSNTb5eA== X-Received: by 2002:a17:902:a710:b029:12b:9b9f:c461 with SMTP id w16-20020a170902a710b029012b9b9fc461mr5253246plq.59.1633628850856; Thu, 07 Oct 2021 10:47:30 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id 197sm83318pfv.6.2021.10.07.10.47.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 10:47:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol Date: Thu, 7 Oct 2021 10:47:18 -0700 Message-Id: <20211007174722.929993-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org> References: <20211007174722.929993-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for RV128, consider more than just "w" for operand size modification. This will be used for the "d" insns from RV128 as well. Rename oper_len to get_olen to better match get_xlen. Signed-off-by: Richard Henderson --- target/riscv/translate.c | 71 ++++++++++++++++--------- target/riscv/insn_trans/trans_rvb.c.inc | 8 +-- target/riscv/insn_trans/trans_rvi.c.inc | 18 +++---- target/riscv/insn_trans/trans_rvm.c.inc | 10 ++-- 4 files changed, 63 insertions(+), 44 deletions(-) -- 2.25.1 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5724a62bb0..6ab5c6aa58 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -67,7 +67,7 @@ typedef struct DisasContext { to any system register, which includes CSR_FRM, so we do not have to reset this known value. */ int frm; - bool w; + RISCVMXL ol; bool virt_enabled; bool ext_ifencei; bool hlsx; @@ -103,12 +103,17 @@ static inline int get_xlen(DisasContext *ctx) return 16 << get_xl(ctx); } -/* The word size for this operation. */ -static inline int oper_len(DisasContext *ctx) -{ - return ctx->w ? 32 : TARGET_LONG_BITS; -} +/* The operation length, as opposed to the xlen. */ +#ifdef TARGET_RISCV32 +#define get_ol(ctx) MXL_RV32 +#else +#define get_ol(ctx) ((ctx)->ol) +#endif +static inline int get_olen(DisasContext *ctx) +{ + return 16 << get_ol(ctx); +} /* * RISC-V requires NaN-boxing of narrower width floating point values. @@ -221,24 +226,34 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) return ctx->zero; } - switch (ctx->w ? ext : EXT_NONE) { - case EXT_NONE: - return cpu_gpr[reg_num]; - case EXT_SIGN: - t = temp_new(ctx); - tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); - return t; - case EXT_ZERO: - t = temp_new(ctx); - tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); - return t; + switch (get_ol(ctx)) { + case MXL_RV32: + switch (ext) { + case EXT_NONE: + break; + case EXT_SIGN: + t = temp_new(ctx); + tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); + return t; + case EXT_ZERO: + t = temp_new(ctx); + tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); + return t; + default: + g_assert_not_reached(); + } + break; + case MXL_RV64: + break; + default: + g_assert_not_reached(); } - g_assert_not_reached(); + return cpu_gpr[reg_num]; } static TCGv dest_gpr(DisasContext *ctx, int reg_num) { - if (reg_num == 0 || ctx->w) { + if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { return temp_new(ctx); } return cpu_gpr[reg_num]; @@ -247,10 +262,15 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num) static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) { if (reg_num != 0) { - if (ctx->w) { + switch (get_ol(ctx)) { + case MXL_RV32: tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); - } else { + break; + case MXL_RV64: tcg_gen_mov_tl(cpu_gpr[reg_num], t); + break; + default: + g_assert_not_reached(); } } } @@ -411,7 +431,7 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, target_long)) { TCGv dest, src1; - int max_len = oper_len(ctx); + int max_len = get_olen(ctx); if (a->shamt >= max_len) { return false; @@ -430,7 +450,7 @@ static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, TCGv)) { TCGv dest, src1, src2; - int max_len = oper_len(ctx); + int max_len = get_olen(ctx); if (a->shamt >= max_len) { return false; @@ -454,7 +474,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); TCGv ext2 = tcg_temp_new(); - tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1); + tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1); func(dest, src1, ext2); gen_set_gpr(ctx, a->rd, dest); @@ -554,7 +574,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->cs = cs; - ctx->w = false; ctx->ntemp = 0; memset(ctx->temp, 0, sizeof(ctx->temp)); @@ -578,9 +597,9 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) CPURISCVState *env = cpu->env_ptr; uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); + ctx->ol = ctx->xl; decode_opc(env, ctx, opcode16); ctx->base.pc_next = ctx->pc_succ_insn; - ctx->w = false; for (int i = ctx->ntemp - 1; i >= 0; --i) { tcg_temp_free(ctx->temp[i]); diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 185c3e9a60..66dd51de49 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -341,7 +341,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl); } @@ -367,7 +367,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_NONE, gen_rorw); } @@ -375,7 +375,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw); } @@ -401,7 +401,7 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_NONE, gen_rolw); } diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 920ae0edb3..c0a46d823f 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -333,14 +333,14 @@ static bool trans_and(DisasContext *ctx, arg_and *a) static bool trans_addiw(DisasContext *ctx, arg_addiw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl); } static bool trans_slliw(DisasContext *ctx, arg_slliw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); } @@ -352,7 +352,7 @@ static void gen_srliw(TCGv dst, TCGv src, target_long shamt) static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw); } @@ -364,42 +364,42 @@ static void gen_sraiw(TCGv dst, TCGv src, target_long shamt) static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw); } static bool trans_addw(DisasContext *ctx, arg_addw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl); } static bool trans_subw(DisasContext *ctx, arg_subw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl); } static bool trans_sllw(DisasContext *ctx, arg_sllw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl); } static bool trans_srlw(DisasContext *ctx, arg_srlw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl); } static bool trans_sraw(DisasContext *ctx, arg_sraw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl); } diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc index b89a85ad3a..9a1fe3c799 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -214,7 +214,7 @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl); } @@ -222,7 +222,7 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_SIGN, gen_div); } @@ -230,7 +230,7 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_ZERO, gen_divu); } @@ -238,7 +238,7 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_SIGN, gen_rem); } @@ -246,6 +246,6 @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_ZERO, gen_remu); } From patchwork Thu Oct 7 17:47:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515459 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1411137ime; Thu, 7 Oct 2021 10:52:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyWkMBDC4CZgMjfds1S8YjIAuSYSvdpbNk5KkM14+3451ojYDsLAYrMObU96DKKfGsl4GEo X-Received: by 2002:ac8:5916:: with SMTP id 22mr2463867qty.158.1633629158687; Thu, 07 Oct 2021 10:52:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633629158; cv=none; d=google.com; s=arc-20160816; b=cEImtqMU0d33khy84tKBkW+92S88Jma/EQi+Kt8pVBkd4LS5eaxHlSEelIFssWEdN1 UVkcvAO2rp3HHwZWTpg7fi0L3maz84bKdWEXEzvARySG0+ByBcYCGnD1PpL+F0mbvJmX rgzeGPuFA4JaML2Xy2vUtm1niuI8ArfSRk8vA6PbW3Ib1KVMt5BiaLukIxacyr5lQ6um zFwyEr4zgZ8EvDdCr/h6AnBZM5yYKzeIQuQ91aAJ8dQRZJTKh1D9o969mFSlzpDD0avO Xr755ca9XdifckDW15P12hCfpgwQ5L0ORd8tCYSWG7AdEdx9iV4KVu33tWUN7U5fW4VD XIVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=N3Hnmm2MQMIa5OCFLOX/oLKZdwWx7vMKA62OCbtMzhw=; b=MKC2RkeFdA9Yt7WplCvAk0cZkoHXh4uy1fZTGusNWDIEB6NJDK6QIqj3s1kyxG0TQ8 Gzqr2vt0Z8wj6GRYMkWSHor3+aCitovPS4NChqiLDttqDy+r3r7piXHvUDiO0f8mHfZ3 NxE+II8NE0ppJwapXPnDad5z3edpBRsKmSdsPBsk+siOF/FYR+HhPbcbWFHWtAh7ja8F HORgsXjlb7zeBoxo8CPhxF5euYBo8ZaiMrCr0ldj1Co95AOqe+7CvOlu3A2ZFSTwTQHS I9D9iDe/D/Zw1Wr9eHrH904UTZbXHmWBnw5vmSbzpcmhoJl5gLnqz0CMGauJfygSmTL+ pYCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=msRXsXsB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g129si58399qkf.4.2021.10.07.10.52.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Oct 2021 10:52:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=msRXsXsB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60994 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYXZO-0002Vs-7R for patch@linaro.org; Thu, 07 Oct 2021 13:52:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38252) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYXUY-000446-FF for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:42 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:50764) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mYXUU-0006vP-Qp for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:38 -0400 Received: by mail-pj1-x1031.google.com with SMTP id k23so5502112pji.0 for ; Thu, 07 Oct 2021 10:47:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N3Hnmm2MQMIa5OCFLOX/oLKZdwWx7vMKA62OCbtMzhw=; b=msRXsXsBG0cT6nChE18nx55qpVzR6LSHzs5DFJY8QZBILrpy74xlkYwmlCO6cRa1Fp 203d5OAiIHByGpDyBoiGIrXPO9t67BFr6dvN8BJxp6BziHrp2vEJKS+M1MmEzmeeyKcS QsmEkoEBu92Uqb99Dm7oQ596iCucpOgj/tfI5EKxV2VsmstnnRco1VyVMu+U9pDvY1yI LPh2+qxEgucbls4A5YXVGuVIzi2oJWFg/AOivU83qvH3AiOYfPKRTg6p01VaVdHi8o14 mn9Ysn1SgJvlUpPwG+gT9l+4d+NNBxbOADRvmhB9UtRyprm+9fw5dIPfGbIkHYSj5lii kSpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N3Hnmm2MQMIa5OCFLOX/oLKZdwWx7vMKA62OCbtMzhw=; b=KD3AUajKORKpZpZEUu6s4tHY5VkWh/LC2E8FT56y2NDOo8eOQJ5k04o5W0wYTdwOg+ 9QKq9kLgkEoihVEyuImBCOeyMr6N3q9Pl87sjV4IkUf+jNuaPjyshfz9MxWEgsW/r67C ceAXTzOvmauTp8rN41uOJrQxtBTM7FI4Lo5lu5MEr5+vEaEp8RQyH0CkHsrFlvu/x3GJ PgT8JWXK+ry7kbrS/GiB2ewirsZ2NXTBFOE9jkCBvHLjOO8EBg+cV1lbqZJV4LESNg32 YnFKQx+PIUJW/1Mr1yNxx81wzk0JW4VSf/LNruxx+NGxMZn1EVCxLyncEleJgsvFIBdt cRyQ== X-Gm-Message-State: AOAM531vOd2joOLykMh1sCPK91VfO7pMi8Dy7GBg8EopPeDxjxaqazFt vtn2a6O+MFppeDvA09ORdrh7YNMYlYLQpw== X-Received: by 2002:a17:902:7d89:b0:13c:a5e1:f0f1 with SMTP id a9-20020a1709027d8900b0013ca5e1f0f1mr5094542plm.24.1633628851468; Thu, 07 Oct 2021 10:47:31 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id 197sm83318pfv.6.2021.10.07.10.47.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 10:47:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 10/13] target/riscv: Use gen_arith_per_ol for RVM Date: Thu, 7 Oct 2021 10:47:19 -0700 Message-Id: <20211007174722.929993-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org> References: <20211007174722.929993-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The multiply high-part instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Signed-off-by: Richard Henderson --- target/riscv/translate.c | 16 +++++++++++++++ target/riscv/insn_trans/trans_rvm.c.inc | 26 ++++++++++++++++++++++--- 2 files changed, 39 insertions(+), 3 deletions(-) -- 2.25.1 Reviewed-by: LIU Zhiwei diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6ab5c6aa58..f960929c16 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -427,6 +427,22 @@ static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, return true; } +static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, + void (*f_tl)(TCGv, TCGv, TCGv), + void (*f_32)(TCGv, TCGv, TCGv)) +{ + int olen = get_olen(ctx); + + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_arith(ctx, a, ext, f_tl); +} + static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, target_long)) { diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc index 9a1fe3c799..2af0e5c139 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -33,10 +33,16 @@ static void gen_mulh(TCGv ret, TCGv s1, TCGv s2) tcg_temp_free(discard); } +static void gen_mulh_w(TCGv ret, TCGv s1, TCGv s2) +{ + tcg_gen_mul_tl(ret, s1, s2); + tcg_gen_sari_tl(ret, ret, 32); +} + static bool trans_mulh(DisasContext *ctx, arg_mulh *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_NONE, gen_mulh); + return gen_arith_per_ol(ctx, a, EXT_SIGN, gen_mulh, gen_mulh_w); } static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) @@ -54,10 +60,23 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(rh); } +static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + + tcg_gen_ext32s_tl(t1, arg1); + tcg_gen_ext32u_tl(t2, arg2); + tcg_gen_mul_tl(ret, t1, t2); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_gen_sari_tl(ret, ret, 32); +} + static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_NONE, gen_mulhsu); + return gen_arith_per_ol(ctx, a, EXT_NONE, gen_mulhsu, gen_mulhsu_w); } static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2) @@ -71,7 +90,8 @@ static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2) static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_NONE, gen_mulhu); + /* gen_mulh_w works for either sign as input. */ + return gen_arith_per_ol(ctx, a, EXT_ZERO, gen_mulhu, gen_mulh_w); } static void gen_div(TCGv ret, TCGv source1, TCGv source2) From patchwork Thu Oct 7 17:47:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515460 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1411144ime; Thu, 7 Oct 2021 10:52:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw4a4IRl3cx+PuUG6sDzMpA8A5Emdgs3CKmq/IpurZs/N00omwliiO2mnG7lZS+vA7OTvNg X-Received: by 2002:a37:684a:: with SMTP id d71mr3848364qkc.382.1633629159337; Thu, 07 Oct 2021 10:52:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633629159; cv=none; d=google.com; s=arc-20160816; b=v+DFcTzcZCvQjpJnmzWxXUw4wKQX8/zyeq9tlcr+3npCHWxgq5ptqn6uoJ48EH/a6F KG3LAbDTsGWy+V6LYpfPtn+1Tplj1AC4W6ryH+fDRXABRNErfOWxO6Zz2B/tdMr+34EH BSLSaCJlyZ0Yw3vmyvMpsYjJoJaEKOrps7M3c4Wz/0tnfgsjLjLxwAQV2SLcpMzHeHq/ ORCe3ma1xFTHDumJoVccsCZV8msF2hCNHwFl7Z5luuu2GAvAyMwk3jc07dYFbmoWXJK5 8PCA+WoGgaDvAmrBokzNP5MX/yP7sxuhjsZ3H4t/dpn0qWTptvrI5wcU6UtLytEkC6jD 5A1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vZLRJy8/jxA2VUmbIFcOC3CPI+naiU5qep1MI8LkbwQ=; b=M+muNRD4cu9yyPW7WuyuQxL3hfXi+LC96fgwg2YDkr6FOSceSFN6VqFzzgMjqcFV0m xYATaHSu4ynu+nMi+dmNO83oIFaxH92idIcwc3fClmJ57UB4Du3pPY88YnQaoZYIfvwK dmUs7PwAju0a13leJTY7CR2LtbFes+U31/2EV4Fn3sHz7bhIa3KrfrlBmSbFfRuWcbHv oPVoZCPPsT0lO6Z/tkWoOg5Ogl7Aqf75zblW2VehYIQNndeiRxGKTlZxlS+7hTqnytjG BzMwDIY1RUVRSnpJWRFDT5zQI9D4VrETouMYTY/9wbcGwnfJlLuNQD7c8dG4/nZM+RBN BbXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Q4BrtGvX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id iv15si9119qvb.64.2021.10.07.10.52.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Oct 2021 10:52:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Q4BrtGvX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:32818 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYXZO-0002XZ-Rp for patch@linaro.org; Thu, 07 Oct 2021 13:52:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38250) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYXUY-000445-Ap for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:42 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:42744) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mYXUU-0006w0-SC for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:38 -0400 Received: by mail-pl1-x636.google.com with SMTP id l6so4378779plh.9 for ; Thu, 07 Oct 2021 10:47:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vZLRJy8/jxA2VUmbIFcOC3CPI+naiU5qep1MI8LkbwQ=; b=Q4BrtGvXKnX/ujXqGxKCkAksE5Fw1FmhYITG69nWjvXz1j1JYhm84BGCUCVfHoUjfh 6C670soZKysgs6FeL3y03hYCsAdnwkuKS3i6EBBcL/Ruox0kyAbkRIkgOCpgol+3YYA7 dSpCZWLrNW94iVndyzajP1gRs8G/9idNsn4X+XzMt73DdO0Yvgc1kiKMpfAGlmBqnPET fX/aiaINe0eQ5lXk/DjWa6bi2mNGIQ+BfGOmRGwmoS9dYeBtJ8/EOY4eE+ezya2Ee/U2 3t83pgIjpuKSd/uhoihhGP/7AT9rO1T4WWJgJ9sTzxVsOTbdN55zx/PXIAOdULwrwtBL KCiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vZLRJy8/jxA2VUmbIFcOC3CPI+naiU5qep1MI8LkbwQ=; b=39AjdXIzatKGK/7UR9k92TP2P3vgC+0xA5pqlPejHHJGuKm/Lm8xtI5fg9vygCY3ol l84Ge81z9uZ2F+QvOy7DD+UQgLQRP0cqW+IdyFGf7Zuw7IhOF9mJIWkoqf6TrhVHVmN9 OS9SdZ+WUCtEsC9XVYOiztEWlCuf2On1uVOEhx2DOh1suL7tUO9LMwWsnOGSH7qdrshC X7Z1MDNgeL+3sVb1bsI2jZK7XFJdN7i8kbrQXs/55y7Lj1QvTE6zBw9GszJDDOxfHc8b w2S3WbL/IzwiNrgeW3Wq9zNhi/bTSpybNAssaaHPeEik/YEZwxRYx9dJQD6itVY8umnK zfLg== X-Gm-Message-State: AOAM532gVseT0q5hVKThLeKwx4w3g226AQvFocxc7jMdBuQwhWf9uv6U VtGDz5ixprcBZOn+Ie2QwVjTX1WaFN/wwg== X-Received: by 2002:a17:90a:4306:: with SMTP id q6mr6931896pjg.202.1633628852086; Thu, 07 Oct 2021 10:47:32 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id 197sm83318pfv.6.2021.10.07.10.47.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 10:47:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 11/13] target/riscv: Adjust trans_rev8_32 for riscv64 Date: Thu, 7 Oct 2021 10:47:20 -0700 Message-Id: <20211007174722.929993-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org> References: <20211007174722.929993-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When target_long is 64-bit, we still want a 32-bit bswap for rev8. Since this opcode is specific to RV32, we need not conditionalize. Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.25.1 Reviewed-by: LIU Zhiwei diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 66dd51de49..c62eea433a 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a) return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl); } +static void gen_rev8_32(TCGv ret, TCGv src1) +{ + tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS); +} + static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a) { REQUIRE_32BIT(ctx); REQUIRE_ZBB(ctx); - return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl); + return gen_unary(ctx, a, EXT_NONE, gen_rev8_32); } static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a) From patchwork Thu Oct 7 17:47:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515462 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1412688ime; Thu, 7 Oct 2021 10:54:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzn4ZD7ty8MZHJqdC8XVSz9CM/d9ed31opgGkRGXtuMSLUYxvu/MQuuQpzovCI5n3bR5C/C X-Received: by 2002:a37:9b58:: with SMTP id d85mr2459789qke.239.1633629294957; Thu, 07 Oct 2021 10:54:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633629294; cv=none; d=google.com; s=arc-20160816; b=MkgrKxQnzIeIdkA38Dc6fghCrxuYporh1mi6tGhOxu7+SMXeLMSPnOluaoUd8W0+x0 9kSBqOEvdnWEaGdNhIBGeS4aniN6n1ICiFzSaRe+SHzNURqD2d9LE+IoPJIov5U46fdX IqWf9CC2F8AvjuKnxC2EV0mhza5bfzRGMZEO+YPZI8TsMOuxh2NCe6hYqGgtQ95wmgCD P0TQUjG7tTMTr29H4G1CT7ro9tLMGrlznqRfesoJVykudfSsVc0B0yk+MpVQu5/nm2wp 2DCUnhaOzMPtt3dhCYJhqcz2Qg/vqoeOEj6KdwBfgvmY0LxemWc3Iddx6G4nu7BBnVCG 01Xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XBpFvHyAXfKxFmNRmo3FDaOehv00YfeTHltGHuiouDk=; b=i+5sd++i8m1xp5fR+fALuS6Ij7117M0jedPsDEzRd6F+7PzDYTebTEY6RTQ1dY2m3W 4+ZddiO7Rl+g67hYvAk/DcHJv1rePU5gdpHuchiBhGk3WNhk/fiwIgitwdWne0GWLBFP 67f8H0GZAb7gKszfJxa+QuF7gz3/kmCNj1y+SWfTKir0G/aeGyiBfF9QIQIoJmochc9w xpWxm1txRr1oadNIRdU7JjWNCOnyMdN+qZxKyeOtXsUjeYiGvySnpLkfr3I4nhx2fT7a XlhSEFkVwbIp0bp2Z1LVMt0IL8FJMVulzM40NX8FEEq3tYT0no+FtfVX2Q09M0n3X666 U6Cw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QZB4D9fv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h7si55319qkp.337.2021.10.07.10.54.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Oct 2021 10:54:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QZB4D9fv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40660 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYXbZ-0007jr-Go for patch@linaro.org; Thu, 07 Oct 2021 13:54:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38286) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYXUb-00044L-NM for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:44 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:46015) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mYXUU-0006wR-Po for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:41 -0400 Received: by mail-pj1-x102d.google.com with SMTP id ls14-20020a17090b350e00b001a00e2251c8so5695570pjb.4 for ; Thu, 07 Oct 2021 10:47:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XBpFvHyAXfKxFmNRmo3FDaOehv00YfeTHltGHuiouDk=; b=QZB4D9fvFkzhdRbgvQpM+Vyj30PFl4nL9NioDzPcRuZ9wxV1tHZhlWWp/YErYws/X/ tUcaIYFaOETQzneMSpb1Nadot8Vy55m/BcMnwaOwNlKZv56c3Fiwx5IE3Qll97jpdnOO ICRKlSOz9nIitW3SX9GUsHiqa8SFlvbxZrKR1QC/ahlM4tcGV44z/Lku2ezZOjCcnmpV Ss1kNc0Zir+EXhZMDu+PaKxveB6b9E4ngpH8lXvQ0ZOlbDNX/Mx77DMkkuL6aJqTN201 6ZyTqtl+JXO1oq1QzSy0jfsJ+0jKq+uARomLrrsA9BuEALsbiwEMfMTGATxl/gJ/XuPd VTsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XBpFvHyAXfKxFmNRmo3FDaOehv00YfeTHltGHuiouDk=; b=v+FLRjcqXCOeookHEDqXUBADi+LEPEFx61i9vEvIPtCdUjDgLNffoXzLM+htKom1vp nr+BBciuOtZQLAK8ahp6z3JfAy3/PjgSwi0fnNGZ5xigpTg08k6QRxGCmFNqhOlQ5kOX AdeXX9gcy8qOiB5wLnJU7LKVBC0HSCCmciLYahUkheoikK/GGFS9QgTrVC7Cwli8Mrgc nYQQGEGv+P5phmbH4/TInj5/ZCmOOePhPDk39baW2+5QRjJfwOaRU74n3K/ggXZN0IGw yNZnZmmXUouXumIrJ0oVYRE2RI9w9psPL+23HJ96TuWD967lbYdTvEy2DQSigqAduTXz u2Aw== X-Gm-Message-State: AOAM532FeBVLvbZkxeg6PlOOihfFPWbqb1+B+YQYU4XNNmKaSOx3m37S rcnbknSwnlwZdqyHTj0d9mNNFrkcNB8gQg== X-Received: by 2002:a17:902:7843:b0:13d:c728:69c9 with SMTP id e3-20020a170902784300b0013dc72869c9mr5035407pln.55.1633628852686; Thu, 07 Oct 2021 10:47:32 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id 197sm83318pfv.6.2021.10.07.10.47.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 10:47:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 12/13] target/riscv: Use gen_unary_per_ol for RVB Date: Thu, 7 Oct 2021 10:47:21 -0700 Message-Id: <20211007174722.929993-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org> References: <20211007174722.929993-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The count zeros instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Signed-off-by: Richard Henderson --- target/riscv/translate.c | 16 ++++++++++++ target/riscv/insn_trans/trans_rvb.c.inc | 33 ++++++++++++------------- 2 files changed, 32 insertions(+), 17 deletions(-) -- 2.25.1 Reviewed-by: LIU Zhiwei diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f960929c16..be458ae0c2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -510,6 +510,22 @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, return true; } +static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, + void (*f_tl)(TCGv, TCGv), + void (*f_32)(TCGv, TCGv)) +{ + int olen = get_olen(ctx); + + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_unary(ctx, a, ext, f_tl); +} + static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) { DisasContext *ctx = container_of(dcbase, DisasContext, base); diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index c62eea433a..adc35b6491 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -47,10 +47,18 @@ static void gen_clz(TCGv ret, TCGv arg1) tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS); } +static void gen_clzw(TCGv ret, TCGv arg1) +{ + TCGv t = tcg_temp_new(); + tcg_gen_shli_tl(t, arg1, 32); + tcg_gen_clzi_tl(ret, t, 32); + tcg_temp_free(t); +} + static bool trans_clz(DisasContext *ctx, arg_clz *a) { REQUIRE_ZBB(ctx); - return gen_unary(ctx, a, EXT_ZERO, gen_clz); + return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw); } static void gen_ctz(TCGv ret, TCGv arg1) @@ -58,10 +66,15 @@ static void gen_ctz(TCGv ret, TCGv arg1) tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS); } +static void gen_ctzw(TCGv ret, TCGv arg1) +{ + tcg_gen_ctzi_tl(ret, ret, 32); +} + static bool trans_ctz(DisasContext *ctx, arg_ctz *a) { REQUIRE_ZBB(ctx); - return gen_unary(ctx, a, EXT_ZERO, gen_ctz); + return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw); } static bool trans_cpop(DisasContext *ctx, arg_cpop *a) @@ -314,14 +327,6 @@ static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a) return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl); } -static void gen_clzw(TCGv ret, TCGv arg1) -{ - TCGv t = tcg_temp_new(); - tcg_gen_shli_tl(t, arg1, 32); - tcg_gen_clzi_tl(ret, t, 32); - tcg_temp_free(t); -} - static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); @@ -329,17 +334,11 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a) return gen_unary(ctx, a, EXT_NONE, gen_clzw); } -static void gen_ctzw(TCGv ret, TCGv arg1) -{ - tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32)); - tcg_gen_ctzi_tl(ret, ret, 64); -} - static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - return gen_unary(ctx, a, EXT_NONE, gen_ctzw); + return gen_unary(ctx, a, EXT_ZERO, gen_ctzw); } static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) From patchwork Thu Oct 7 17:47:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515464 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1412905ime; Thu, 7 Oct 2021 10:55:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwXM3gEKdwIFiAOyTBqVTRSQm3pCNMMvpRic//R9AyzBIyeI4i/dx4EMgHFrMKSJqsgf2Lq X-Received: by 2002:ac8:5f13:: with SMTP id x19mr6716277qta.305.1633629317887; Thu, 07 Oct 2021 10:55:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633629317; cv=none; d=google.com; s=arc-20160816; b=qIdlrHNR3d/Ga6CLGgTApPh01rP366EVt9PhqnlmttyDolKlfWUsz74mQJqXsCa49G lnOcvoLSz1TxbGZW3PVR1iUj+hM8EEL9HvMKL7G0HLEKQPWo8tI7WU/63vAVyrSOxjtH BO15Q+SkXeJoZ0IMjor2mgevTIP3J6e6TkKSA+fMEX5ZRzp2cqGB0OKK4xNh2Qo/YqjD BVQmowk4RkPjuopXZkZQnMU0bQrk2XrwY5OR31RLyQU5/lKBOMmtvMJsPdl5H3WFYjPA u/Cx6X1d0g9r8Bc2k596g/LCM9D+YV+0dy49uVGKH8a3J7FBOGJn5rL0xMHJfQI210Ja 2ecw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xgVgN3nv5jhHcDS7Ua2oeBb2JMX8tUz0628CF3KrShU=; b=JVPrwARtuP04iugmChELQXFIgmCEAq4kEaBJ/0o/Z3m5FVY3PN4VfOsOm2nfkbzWAu gi0ECogbPptnkBpTvSpmIByv4HPMonBJ0dZbZ71qFvqRLdwqhyQwcYanMwSAKCv5vCAC ohKtUHJ6uztfmZiim7yNFKt5Qy1b6EzE52t7/FwjyqjAN9ioppPUGh6N2T91TMCJw6xK pIB39pCOB1ExNhCZ9CPww1M6tKHLWAyng9vLQMZ2p9NFU352w9gXgan8BV+6++Nug15b Wj5/pERotIc84d7hGXoC0UnvZAKxhFL3ykjL3AAVBQWRaydf0kCEzvW+OVwL5D6q7OFv QxQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zEvnxj9e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b9si86289qvv.219.2021.10.07.10.55.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Oct 2021 10:55:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zEvnxj9e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42188 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYXbx-0000JK-8u for patch@linaro.org; Thu, 07 Oct 2021 13:55:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38292) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYXUc-00044R-Kj for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:44 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:40848) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mYXUW-0006wz-TR for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:42 -0400 Received: by mail-pg1-x536.google.com with SMTP id h3so506290pgb.7 for ; Thu, 07 Oct 2021 10:47:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xgVgN3nv5jhHcDS7Ua2oeBb2JMX8tUz0628CF3KrShU=; b=zEvnxj9enVvk7Gn2zclO+slqfc1RMJmjLjK6FSiKLdQ+c5HJwAzzMD/ewJDGcizui9 Z5Pw94iShalvycIFB4SgNso5I2IGe/ULLP4OlrYTiz91kaRI7oGVSw9OxRgSchQPB+c6 TxlS5EL8py/8UTIom5efCc/lOPgbaCIgCRAdkC9DE4GPMmAxOyzoN7+Z6ONWXCTmf/gn cgb8mQGpxPblwWM4vWm4cd3SQmkObpGyacP7QFZhcOMeZzlZX4yBetd3LKwbx2kGs1dP V81IosEq0fxSHNlPqEaoq4zkxWyJYAyRJ/+w/eBx9swErgnp/PIxKwtHWOw3IQoQfjji LBGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xgVgN3nv5jhHcDS7Ua2oeBb2JMX8tUz0628CF3KrShU=; b=ufUzDdxlqJW+kMHth8hD/uHq13vOlHk5RNDZrCBkaHP95jz7q1zF74/AKAkz75g5iI snX0HaQTifUNUxq2aqswdnMYikBV3MDjE6IDrKAJEtlHCQYZDCEQrDA0z5R84NWKYcZ0 D/KRMwxFpz+fmoz46kONqRpN2GzHmjB69Yo8VTnEQg3IK5ZhGPSjD/I2HiUIG3c/D97Q oAduBNJ5pgAsmNT53MzI+Ybn+T1Eu+M2/4YtJOarb9DJ16xTJKtlTHKWmnEtLV7BDIFx M9s/DlmYx3byKUUWj54jPYFn7uwF+yiq4tmTX7rcoK4OaoO1vUbf+/jRM+uWAA+FFG+G wRdQ== X-Gm-Message-State: AOAM533opuAv4TXQqG33wl83cscWpJAgcU1V1FjpOhFG14QVIMKVFpdP 4op4gERPcVxIZtjx/z6yWGX2JQxwj3d90g== X-Received: by 2002:a63:1a64:: with SMTP id a36mr768435pgm.225.1633628853461; Thu, 07 Oct 2021 10:47:33 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id 197sm83318pfv.6.2021.10.07.10.47.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 10:47:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI Date: Thu, 7 Oct 2021 10:47:22 -0700 Message-Id: <20211007174722.929993-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org> References: <20211007174722.929993-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Most shift instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Signed-off-by: Richard Henderson --- target/riscv/translate.c | 31 +++++++++ target/riscv/insn_trans/trans_rvb.c.inc | 92 ++++++++++++++----------- target/riscv/insn_trans/trans_rvi.c.inc | 26 +++---- 3 files changed, 97 insertions(+), 52 deletions(-) -- 2.25.1 Reviewed-by: LIU Zhiwei diff --git a/target/riscv/translate.c b/target/riscv/translate.c index be458ae0c2..dbe3670ff3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -462,6 +462,22 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, return true; } +static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, + DisasExtend ext, + void (*f_tl)(TCGv, TCGv, target_long), + void (*f_32)(TCGv, TCGv, target_long)) +{ + int olen = get_olen(ctx); + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_shift_imm_fn(ctx, a, ext, f_tl); +} + static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, TCGv)) { @@ -498,6 +514,21 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, return true; } +static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, + void (*f_tl)(TCGv, TCGv, TCGv), + void (*f_32)(TCGv, TCGv, TCGv)) +{ + int olen = get_olen(ctx); + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_shift(ctx, a, ext, f_tl); +} + static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, void (*func)(TCGv, TCGv)) { diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index adc35b6491..9b9c9c8bc4 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -227,22 +227,70 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a) return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); } +static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + + /* truncate to 32-bits */ + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_trunc_tl_i32(t2, arg2); + + tcg_gen_rotr_i32(t1, t1, t2); + + /* sign-extend 64-bits */ + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); +} + static bool trans_ror(DisasContext *ctx, arg_ror *a) { REQUIRE_ZBB(ctx); - return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl); + return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw); +} + +static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_rotri_i32(t1, t1, shamt); + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); } static bool trans_rori(DisasContext *ctx, arg_rori *a) { REQUIRE_ZBB(ctx); - return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl); + return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, + tcg_gen_rotri_tl, gen_roriw); +} + +static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + + /* truncate to 32-bits */ + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_trunc_tl_i32(t2, arg2); + + tcg_gen_rotl_i32(t1, t1, t2); + + /* sign-extend 64-bits */ + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); } static bool trans_rol(DisasContext *ctx, arg_rol *a) { REQUIRE_ZBB(ctx); - return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl); + return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw); } static void gen_rev8_32(TCGv ret, TCGv src1) @@ -349,24 +397,6 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl); } -static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv_i32 t1 = tcg_temp_new_i32(); - TCGv_i32 t2 = tcg_temp_new_i32(); - - /* truncate to 32-bits */ - tcg_gen_trunc_tl_i32(t1, arg1); - tcg_gen_trunc_tl_i32(t2, arg2); - - tcg_gen_rotr_i32(t1, t1, t2); - - /* sign-extend 64-bits */ - tcg_gen_ext_i32_tl(ret, t1); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); -} - static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); @@ -380,25 +410,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a) REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); ctx->ol = MXL_RV32; - return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw); -} - -static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv_i32 t1 = tcg_temp_new_i32(); - TCGv_i32 t2 = tcg_temp_new_i32(); - - /* truncate to 32-bits */ - tcg_gen_trunc_tl_i32(t1, arg1); - tcg_gen_trunc_tl_i32(t2, arg2); - - tcg_gen_rotl_i32(t1, t1, t2); - - /* sign-extend 64-bits */ - tcg_gen_ext_i32_tl(ret, t1); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw); } static bool trans_rolw(DisasContext *ctx, arg_rolw *a) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index c0a46d823f..b0fdec97de 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -270,14 +270,26 @@ static bool trans_slli(DisasContext *ctx, arg_slli *a) return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); } +static void gen_srliw(TCGv dst, TCGv src, target_long shamt) +{ + tcg_gen_extract_tl(dst, src, shamt, 32 - shamt); +} + static bool trans_srli(DisasContext *ctx, arg_srli *a) { - return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl); + return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, + tcg_gen_shri_tl, gen_srliw); +} + +static void gen_sraiw(TCGv dst, TCGv src, target_long shamt) +{ + tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt); } static bool trans_srai(DisasContext *ctx, arg_srai *a) { - return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl); + return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, + tcg_gen_sari_tl, gen_sraiw); } static bool trans_add(DisasContext *ctx, arg_add *a) @@ -344,11 +356,6 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a) return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); } -static void gen_srliw(TCGv dst, TCGv src, target_long shamt) -{ - tcg_gen_extract_tl(dst, src, shamt, 32 - shamt); -} - static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { REQUIRE_64BIT(ctx); @@ -356,11 +363,6 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a) return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw); } -static void gen_sraiw(TCGv dst, TCGv src, target_long shamt) -{ - tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt); -} - static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { REQUIRE_64BIT(ctx);