From patchwork Wed Oct 6 20:48:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 515418 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp740672ime; Wed, 6 Oct 2021 13:48:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxezNiAH8AmfOAxNihWnWLAdqmXAn1lEhMGA/FDXkGjCU7cjr08nEpge2ay7c8N9Ikgcvkh X-Received: by 2002:a17:90b:3b88:: with SMTP id pc8mr325447pjb.93.1633553314084; Wed, 06 Oct 2021 13:48:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633553314; cv=none; d=google.com; s=arc-20160816; b=r4dbCOhC3/kJRu2teFgyDlbHfE4+Y0xAhQOV+i9jeEFWSRkRrSf3gfKhYKUEHcHtL+ f8cwlbTm0HirGhj4Lo4hpNuSO+AcurWYDFuULqjLacTRjBitg6yogHKKIVb8hCojyCZZ OSHc0dOIbrxAvJRH9wy4M0GyGPVedYEkpCeCeslyCZl0Q5YQb1TYN9svzrAkMRccUBG3 N8iwvxNqi8n6NT01/i95KjlQscCJWVYjI/4y+joZtKhq+3Mql5jGDhc6BtiI8ZXVMjHL iXEx4BSXqQP7wgRFPGD5pKBrIYJXDlm9v3fqF5Kxu0ASiFJyDEbqHB1BKHMqiyiQNLTX fFzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=R4j4McPlc/+lAeM9Wl4HLExls29kqJZ7/vF2Ck1kcqA=; b=dla7ERNSU6TBvA2F4G7wNAgn4i0VHq75rXkZI24Y8sGYxBDY/mDa8wjo1PEO5NsVpy 4AJEsa4RVOLJQBVZFmicHBZC8VRu+V7wr1qV0nY0FGQQIEHirlNKpqDFhQbh/vLxzzZX oAvfN5J3gJ7UcfbXF68mWP6NMlsAQ/48H6A5SKDScQ1MT3++RXga6elXLST4tC1wKwbr VQfLnnRSp7ubtRRqMwkSoK6tKZ1xjO4Sok0gA+DAIH8LTy9H1yyb5Zp+FOMwWNHFqGPx YjAhBo+b/+MrSL85AJj3bsgOUlC8K68Djbec6ZBQMrjHW6mnQNTVGZ+TN+ncEbIkL7nk ckIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E2FXwHy8; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t11si29800533pgu.251.2021.10.06.13.48.33; Wed, 06 Oct 2021 13:48:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E2FXwHy8; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229677AbhJFUuY (ORCPT + 17 others); Wed, 6 Oct 2021 16:50:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232147AbhJFUuY (ORCPT ); Wed, 6 Oct 2021 16:50:24 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA677C061746 for ; Wed, 6 Oct 2021 13:48:31 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id y26so15803842lfa.11 for ; Wed, 06 Oct 2021 13:48:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=R4j4McPlc/+lAeM9Wl4HLExls29kqJZ7/vF2Ck1kcqA=; b=E2FXwHy8vYhenDZFy+97/bSDcaYarSzPGF4sKDxUKKPWqdg5Tns39SAxX794DM65P8 HcAl5sl3nnD40tEvkP9CRBxm9xNOv9W5DH6Z+iYtMnED+gg6acg7JwcrTHePZpOHFzNJ nTFURiSbmPdimg/Ukm00wyj2NOUfqk2ZdY1RRWENhfUKOcCUpZlMnJOcb5024ypR8vWj jAZKQ8h4kUY/GJEZezMmoYJCq12mLXHy+Zve0eDTz6dTKFabySzxDORciw9MmK/tGo0/ 06zLs98mKrC8GuP9KgEXA4kpRxyJ462SJWPtaRfkFmyT39NfZhcc6uLU6b9IfStCH9HA /wog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=R4j4McPlc/+lAeM9Wl4HLExls29kqJZ7/vF2Ck1kcqA=; b=zOhB3Dw3XqKn/iLsSc7y3DU2tT2xMLXoxEPs08EUTCF5eM2N2iZJVxREzXkSg4buy5 FEn7n0e7lDh+Q3kqSaY2Z8k19zyTVWCLXkQDTR8BYm3yG3XgeRg2b+ZsVSRC0ONUW7rI PfZCrlBheBzDQU3dPnljSmXN1UQXMCgUdfSbm9s7Gf8iM3UMWEwdYiMZYBudNIXudi8L DGr3k+HImFUGP6TRAPDAIDNqKyJBrfDfRXknD7M4QMtdjahwLAOT9NafyO75W/819RCg XKyeb2qi+NkFnF2SkXaXqqYy6YUWniCAX1TGLg6I/W0fbXRBoWgOXAoqi9JPzPn8B7AJ WC2g== X-Gm-Message-State: AOAM5306SfXpFSxcc9xDvz/VHlIBse3P5HvSsBYSk92BiJ8tOBP8u0G7 wMRMPgeR8xkJ60GJCPpdY+2y3w== X-Received: by 2002:a2e:7203:: with SMTP id n3mr229653ljc.195.1633553310086; Wed, 06 Oct 2021 13:48:30 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y19sm2378787ljc.116.2021.10.06.13.48.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Oct 2021 13:48:29 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 1/2] drm/msm/dsi: untangle cphy setting from the src pll setting Date: Wed, 6 Oct 2021 23:48:27 +0300 Message-Id: <20211006204828.1218225-1-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move DPHY/CPHY setting from msm_dsi_host_set_src_pll() to new function msm_dsi_host_set_phy_mode(). Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi.h | 2 ++ drivers/gpu/drm/msm/dsi/dsi_host.c | 8 ++++++++ drivers/gpu/drm/msm/dsi/dsi_manager.c | 3 +++ 3 files changed, 13 insertions(+) -- 2.33.0 diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index b50db91cb8a7..7dfb6d198ca9 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -118,6 +118,8 @@ unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host); struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host); int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer); void msm_dsi_host_unregister(struct mipi_dsi_host *host); +void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, + struct msm_dsi_phy *src_phy); int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, struct msm_dsi_phy *src_phy); void msm_dsi_host_reset_phy(struct mipi_dsi_host *host); diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index e269df285136..1ffcd0577e99 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -2224,6 +2224,14 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, wmb(); } +void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, + struct msm_dsi_phy *src_phy) +{ + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + + msm_host->cphy_mode = src_phy->cphy_mode; +} + int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, struct msm_dsi_phy *src_phy) { diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index c41d39f5b7cf..49a0a0841487 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -77,6 +77,7 @@ static int dsi_mgr_setup_components(int id) return ret; msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE); + msm_dsi_host_set_phy_mode(msm_dsi->host, msm_dsi->phy); ret = msm_dsi_host_set_src_pll(msm_dsi->host, msm_dsi->phy); } else if (!other_dsi) { ret = 0; @@ -104,6 +105,8 @@ static int dsi_mgr_setup_components(int id) MSM_DSI_PHY_MASTER); msm_dsi_phy_set_usecase(clk_slave_dsi->phy, MSM_DSI_PHY_SLAVE); + msm_dsi_host_set_phy_mode(msm_dsi->host, msm_dsi->phy); + msm_dsi_host_set_phy_mode(other_dsi->host, other_dsi->phy); ret = msm_dsi_host_set_src_pll(msm_dsi->host, clk_master_dsi->phy); if (ret) return ret; From patchwork Wed Oct 6 20:48:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 515419 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp740711ime; Wed, 6 Oct 2021 13:48:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwdX6tS2kbBXayiXfRiqgl43UOiIq0Zdnby/LnjisZoGaJBHW6PMnsSNRIU9EmBg/khyPbw X-Received: by 2002:a17:902:6ac2:b0:13e:2b51:ca27 with SMTP id i2-20020a1709026ac200b0013e2b51ca27mr27971plt.65.1633553317533; Wed, 06 Oct 2021 13:48:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633553317; cv=none; d=google.com; s=arc-20160816; b=NYcZ2qP36AU4U9ZUDv2KKczHK6tHpAZPrnK/ioO0O4NPv3VVJLmtvC6bcRtoz21os4 M/K7zTqj4P7ngq8XgeESbYxIgZe09HaLD4EtEM0Sm0H9CMSmhqH8ih3hIi+XhHjQCviM TfMwEGnZSh/I8kQ68IFMLuatoCNxkJcQ4zKVdq4fc9rNZfxgCrrfnHkwut0WsJsXuHFr ouXd7UqpGhDyK5vIwZvrp+pkrYaLfQbN+sf5jUTO8LED98NMOm3trdCiwZcXWqtwWwWX smrUXLZLrbD6pU7h2aDGzR9smWuin7Otk+bXA4LN9/FTWitnmv6Cfk5w5nf3UTFhR7Hs Gqmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=omBxJqx/FyuXHNB3iSfAI33Nu5vXJyXne6zSU6njhHw=; b=N4H/Es7+MCyz1cwk5ljRvMbAES2sjF/swbB2l8v/9s7ohAR8Sgz3g/Sk1Kh+y4YmfK IOG07Bu2aIjP4goWWcZbA4GlzcaTQPewVPDn4KyN7vKoWd9sjJl7lxEEPKmig+X3UpDq NHyM/QBCYLdQKKwYlSqjdPPchO+DI8EpC3wZ7z8ZdTpXUM/1ElFJx3M++cZYm2dqLaPh u+X61/lDLT/UU8sasT6H5d/VUeNw8k5IoddKsPffW/GEZllxMLuhwFAs4ErlZcHEpu6e +FVQt3aFG9R997tnLDWEIK44ofN8/l0c+vHHdO8m2pFQxb8wnWmF7Rw/cW+Oftxgb21p SUMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kMXzRWnK; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t11si29800533pgu.251.2021.10.06.13.48.35; Wed, 06 Oct 2021 13:48:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kMXzRWnK; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232147AbhJFUuZ (ORCPT + 17 others); Wed, 6 Oct 2021 16:50:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231749AbhJFUuZ (ORCPT ); Wed, 6 Oct 2021 16:50:25 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7DCF6C061746 for ; Wed, 6 Oct 2021 13:48:32 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id y26so15803919lfa.11 for ; Wed, 06 Oct 2021 13:48:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=omBxJqx/FyuXHNB3iSfAI33Nu5vXJyXne6zSU6njhHw=; b=kMXzRWnKXIXhCAcuRaafEUEmwhOd6NWc2nEUh4LClHTs3R5bCtkIYFIrS9/Raog3Ku D9NVdxNw0AhF7oynGKTQtWVEkdlzqV4QVksSstJ7iiiXsM1irYJUsF4WQmFQMcUOkvcZ 4W4rzmCo2Z7QfJwiCOliCag0FYJ2x6Q9lLE2Khlexe0X5VsDoP1uaIMhMD+zlz6shRjs qqAskVVYkxk9n2HLXFN+odr0++5h6qMv5XJbr+200nIyXOA6Q2Q96ND3AVjU7nPpOYYX 7q9tnCZr6z7eugPd1jwCd+Da5GcGR3etXmaPv5WLAwd2rbOMi8BF+3oMoUyyrx3QckY0 fCJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=omBxJqx/FyuXHNB3iSfAI33Nu5vXJyXne6zSU6njhHw=; b=eDFzwtQgf1JIpPDtRHBlxIV7BfuZQmMb5hqCa95MOs1zCkLdGGYsLJqNZ/Ed56YXuE ULwh1ovSy0qi+xeZcYYJVeOBUxdj9dazhIp8hqkz8AijCSQc5ftx+PirKuGaAbp2nrE1 ob2xke80QUWlSQDQPskYIoAU0+mWJ1EbBspD2oPJpBYaeZM5fnGUJJhfb1zmC1cEpOJT LVqihOVb4JmstLFffAjGX4zAcwFaMl/D+wbdmasZEy5UN7Bf6IGDIFNqb4hocBsu16fb RS1oXcP6OSLHSydrUw5DODRWaPhlGhBbrKn/vatJKeB4FGujHGzLeSEFK2EBWw2FGmj8 shPw== X-Gm-Message-State: AOAM530G9JVODF7xWADnAYUkDC5ozz2cXKDwil/GQNP6MHKKxkYkzwwW ygBGwmYFWCi/madqKOMejElSILEWzCtlsQ== X-Received: by 2002:a05:6512:1291:: with SMTP id u17mr238075lfs.226.1633553310810; Wed, 06 Oct 2021 13:48:30 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y19sm2378787ljc.116.2021.10.06.13.48.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Oct 2021 13:48:30 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 2/2] drm/msm/dsi: stop setting clock parents manually Date: Wed, 6 Oct 2021 23:48:28 +0300 Message-Id: <20211006204828.1218225-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211006204828.1218225-1-dmitry.baryshkov@linaro.org> References: <20211006204828.1218225-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There is no reason to set clock parents manually, use device tree to assign DSI/display clock parents to DSI PHY clocks. Dropping this manual setup allows us to drop repeating code and to move registration of hw clock providers to generic place. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi.h | 2 - drivers/gpu/drm/msm/dsi/dsi_host.c | 53 --------------------------- drivers/gpu/drm/msm/dsi/dsi_manager.c | 11 +----- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 11 ------ 4 files changed, 2 insertions(+), 75 deletions(-) -- 2.33.0 diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 7dfb6d198ca9..c03a8d09c764 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -173,8 +173,6 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, void msm_dsi_phy_disable(struct msm_dsi_phy *phy); void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy, enum msm_dsi_phy_usecase uc); -int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy, - struct clk **byte_clk_provider, struct clk **pixel_clk_provider); void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy); int msm_dsi_phy_pll_restore_state(struct msm_dsi_phy *phy); void msm_dsi_phy_snapshot(struct msm_disp_state *disp_state, struct msm_dsi_phy *phy); diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 1ffcd0577e99..9600b4fa27eb 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -2232,59 +2232,6 @@ void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, msm_host->cphy_mode = src_phy->cphy_mode; } -int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, - struct msm_dsi_phy *src_phy) -{ - struct msm_dsi_host *msm_host = to_msm_dsi_host(host); - struct clk *byte_clk_provider, *pixel_clk_provider; - int ret; - - msm_host->cphy_mode = src_phy->cphy_mode; - - ret = msm_dsi_phy_get_clk_provider(src_phy, - &byte_clk_provider, &pixel_clk_provider); - if (ret) { - pr_info("%s: can't get provider from pll, don't set parent\n", - __func__); - return 0; - } - - ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider); - if (ret) { - pr_err("%s: can't set parent to byte_clk_src. ret=%d\n", - __func__, ret); - goto exit; - } - - ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider); - if (ret) { - pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n", - __func__, ret); - goto exit; - } - - if (msm_host->dsi_clk_src) { - ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider); - if (ret) { - pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n", - __func__, ret); - goto exit; - } - } - - if (msm_host->esc_clk_src) { - ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider); - if (ret) { - pr_err("%s: can't set parent to esc_clk_src. ret=%d\n", - __func__, ret); - goto exit; - } - } - -exit: - return ret; -} - void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 49a0a0841487..9342a822ad20 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -78,10 +78,7 @@ static int dsi_mgr_setup_components(int id) msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE); msm_dsi_host_set_phy_mode(msm_dsi->host, msm_dsi->phy); - ret = msm_dsi_host_set_src_pll(msm_dsi->host, msm_dsi->phy); - } else if (!other_dsi) { - ret = 0; - } else { + } else if (other_dsi) { struct msm_dsi *master_link_dsi = IS_MASTER_DSI_LINK(id) ? msm_dsi : other_dsi; struct msm_dsi *slave_link_dsi = IS_MASTER_DSI_LINK(id) ? @@ -107,13 +104,9 @@ static int dsi_mgr_setup_components(int id) MSM_DSI_PHY_SLAVE); msm_dsi_host_set_phy_mode(msm_dsi->host, msm_dsi->phy); msm_dsi_host_set_phy_mode(other_dsi->host, other_dsi->phy); - ret = msm_dsi_host_set_src_pll(msm_dsi->host, clk_master_dsi->phy); - if (ret) - return ret; - ret = msm_dsi_host_set_src_pll(other_dsi->host, clk_master_dsi->phy); } - return ret; + return 0; } static int enable_phy(struct msm_dsi *msm_dsi, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 8c65ef6968ca..8ec331e751a2 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -890,17 +890,6 @@ bool msm_dsi_phy_set_continuous_clock(struct msm_dsi_phy *phy, bool enable) return phy->cfg->ops.set_continuous_clock(phy, enable); } -int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy, - struct clk **byte_clk_provider, struct clk **pixel_clk_provider) -{ - if (byte_clk_provider) - *byte_clk_provider = phy->provided_clocks->hws[DSI_BYTE_PLL_CLK]->clk; - if (pixel_clk_provider) - *pixel_clk_provider = phy->provided_clocks->hws[DSI_PIXEL_PLL_CLK]->clk; - - return 0; -} - void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy) { if (phy->cfg->ops.save_pll_state) {