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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.11.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:11:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 01/41] accel/tcg: Split out adjust_signal_pc Date: Fri, 1 Oct 2021 13:11:11 -0400 Message-Id: <20211001171151.1739472-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out a function to adjust the raw signal pc into a value that could be passed to cpu_restore_state. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Adjust pc in place; return MMUAccessType. --- include/exec/exec-all.h | 10 ++++++++++ accel/tcg/user-exec.c | 41 +++++++++++++++++++++++++---------------- 2 files changed, 35 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 9d5987ba04..e54f8e5d65 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -663,6 +663,16 @@ static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, return addr; } +/** + * adjust_signal_pc: + * @pc: raw pc from the host signal ucontext_t. + * @is_write: host memory operation was write, or read-modify-write. + * + * Alter @pc as required for unwinding. Return the type of the + * guest memory access -- host reads may be for guest execution. + */ +MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); + /** * cpu_signal_handler * @signum: host signal number diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 8fed542622..cef025d001 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -57,18 +57,11 @@ static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu, cpu_loop_exit_noexc(cpu); } -/* 'pc' is the host PC at which the exception was raised. 'address' is - the effective address of the memory exception. 'is_write' is 1 if a - write caused the exception and otherwise 0'. 'old_set' is the - signal set which should be restored */ -static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, - int is_write, sigset_t *old_set) +/* + * Adjust the pc to pass to cpu_restore_state; return the memop type. + */ +MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write) { - CPUState *cpu = current_cpu; - CPUClass *cc; - unsigned long address = (unsigned long)info->si_addr; - MMUAccessType access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; - switch (helper_retaddr) { default: /* @@ -77,7 +70,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * pointer into the generated code that will unwind to the * correct guest pc. */ - pc = helper_retaddr; + *pc = helper_retaddr; break; case 0: @@ -97,7 +90,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * Therefore, adjust to compensate for what will be done later * by cpu_restore_state_from_tb. */ - pc += GETPC_ADJ; + *pc += GETPC_ADJ; break; case 1: @@ -113,12 +106,28 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * * Like tb_gen_code, release the memory lock before cpu_loop_exit. */ - pc = 0; - access_type = MMU_INST_FETCH; mmap_unlock(); - break; + *pc = 0; + return MMU_INST_FETCH; } + return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; +} + +/* + * 'pc' is the host PC at which the exception was raised. + * 'address' is the effective address of the memory exception. + * 'is_write' is 1 if a write caused the exception and otherwise 0. + * 'old_set' is the signal set which should be restored. + */ +static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, + int is_write, sigset_t *old_set) +{ + CPUState *cpu = current_cpu; + CPUClass *cc; + unsigned long address = (unsigned long)info->si_addr; + MMUAccessType access_type = adjust_signal_pc(&pc, is_write); + /* For synchronous signals we expect to be coming from the vCPU * thread (so current_cpu should be valid) and either from running * code or during translation which can fault as we cross pages. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.11.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:11:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 02/41] accel/tcg: Move clear_helper_retaddr to cpu loop Date: Fri, 1 Oct 2021 13:11:12 -0400 Message-Id: <20211001171151.1739472-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x834.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently there are only two places that require we reset this value before exiting to the main loop, but that will change. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 3 ++- accel/tcg/user-exec.c | 2 -- 2 files changed, 2 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5fd1ed3422..410588d08a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -451,6 +451,7 @@ void cpu_exec_step_atomic(CPUState *cpu) * memory. */ #ifndef CONFIG_SOFTMMU + clear_helper_retaddr(); tcg_debug_assert(!have_mmap_lock()); #endif if (qemu_mutex_iothread_locked()) { @@ -460,7 +461,6 @@ void cpu_exec_step_atomic(CPUState *cpu) qemu_plugin_disable_mem_helpers(cpu); } - /* * As we start the exclusive region before codegen we must still * be in the region if we longjump out of either the codegen or @@ -905,6 +905,7 @@ int cpu_exec(CPUState *cpu) #endif #ifndef CONFIG_SOFTMMU + clear_helper_retaddr(); tcg_debug_assert(!have_mmap_lock()); #endif if (qemu_mutex_iothread_locked()) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index cef025d001..e94f1fed00 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -175,7 +175,6 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * currently executing TB was modified and must be exited * immediately. Clear helper_retaddr for next execution. */ - clear_helper_retaddr(); cpu_exit_tb_from_sighandler(cpu, old_set); /* NORETURN */ @@ -193,7 +192,6 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * an exception. Undo signal and retaddr state prior to longjmp. */ sigprocmask(SIG_SETMASK, old_set, NULL); - clear_helper_retaddr(); cc = CPU_GET_CLASS(cpu); cc->tcg_ops->tlb_fill(cpu, address, 0, access_type, From patchwork Fri Oct 1 17:11:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515053 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp997506jaf; Fri, 1 Oct 2021 10:14:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzR71UVR+WEZjIfZ3ILBzbRwKNfvs4uwmHTRNNOIOsIwTPZaYt2bl6mvg+W9KGuxeY6aDc0 X-Received: by 2002:adf:a2d7:: with SMTP id t23mr5559673wra.156.1633108451521; Fri, 01 Oct 2021 10:14:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633108451; cv=none; d=google.com; s=arc-20160816; b=fPBnb13a7jWA1ItHsHeL0NIm/9FCYJVHN/GvDnfTWZd6owXX4NMpwGSGQHK/26U2Im GDitSBTfYzNonJokOU3EAzYOE/9mxkVlEw2oYO5BmqwuclR3nUM3/ObSsEV2pJm97s7U zHPhe7vWZ7Db8ywRjd3pUEGurVHrHEEZiQLXS5MKpKmmHbZqz2SzV3neAWdA6EnW4PcA MhpeWGmAstrXxcUSlDRzVmjeYew/wbluMEDqXmrOO11s+I4EWGHUy94lk1MfcT08mDl3 i8X6/z0LGZqNdjZKvuTBWx/5+1kN7CXKx39DL/kHjDzBHEGrgpFFuiUzMUHoxWAmihz/ hZPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=d0XAyTZlMLuZKO7GS2lQ57aRasECVtACHoF9DI2hSaY=; b=hwjFIzcu/e84eBxSoHCzc551+WjaOlcdg+MHFN0v7P50YemfmIGvyydk7wB8spOSnh A5Yd6+ieeuiw0LDeWkoSm0kueX/B+i63wuvcRFtC7xVb540XHE7+yJB3GbjH9m7WOrLg Tq/CpnyxVnHAtWhMHcLBQTOuYkbZcGfcSn/8xW8+477QR7is4YCJzHrokyoUsyRbmzDt iWo/M17iPViDeUSlFhFTjSaZqRyiXrZPhWlDq9h1YA2zeq81fkm000hFxJOREDfokeLc OdX0+IT4DLHUoyNvyxdRB6zFO03Tt9okmy2/2sCN+d8z+iOESM9wuDJhXLrdbdxoJbKY t9og== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SRB5ZbVB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.11.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:11:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 03/41] accel/tcg: Split out handle_sigsegv_accerr_write Date: Fri, 1 Oct 2021 13:11:13 -0400 Message-Id: <20211001171151.1739472-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x834.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the major portion of handle_cpu_signal which is specific to tcg, handling the page protections for the translations. Most of the rest will migrate to linux-user/ shortly. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Pass guest address to handle_sigsegv_accerr_write. --- include/exec/exec-all.h | 12 +++++ accel/tcg/user-exec.c | 103 ++++++++++++++++++++++++---------------- 2 files changed, 74 insertions(+), 41 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index e54f8e5d65..5f94d799aa 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -673,6 +673,18 @@ static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, */ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); +/** + * handle_sigsegv_accerr_write: + * @cpu: the cpu context + * @old_set: the sigset_t from the signal ucontext_t + * @host_pc: the host pc, adjusted for the signal + * @host_addr: the host address of the fault + * + * Return true if the write fault has been handled, and should be re-tried. + */ +bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, + uintptr_t host_pc, abi_ptr guest_addr); + /** * cpu_signal_handler * @signum: host signal number diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e94f1fed00..6f4fc01b60 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -114,6 +114,54 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write) return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; } +/** + * handle_sigsegv_accerr_write: + * @cpu: the cpu context + * @old_set: the sigset_t from the signal ucontext_t + * @host_pc: the host pc, adjusted for the signal + * @guest_addr: the guest address of the fault + * + * Return true if the write fault has been handled, and should be re-tried. + * + * Note that it is important that we don't call page_unprotect() unless + * this is really a "write to nonwriteable page" fault, because + * page_unprotect() assumes that if it is called for an access to + * a page that's writeable this means we had two threads racing and + * another thread got there first and already made the page writeable; + * so we will retry the access. If we were to call page_unprotect() + * for some other kind of fault that should really be passed to the + * guest, we'd end up in an infinite loop of retrying the faulting access. + */ +bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, + uintptr_t host_pc, abi_ptr guest_addr) +{ + switch (page_unprotect(guest_addr, host_pc)) { + case 0: + /* + * Fault not caused by a page marked unwritable to protect + * cached translations, must be the guest binary's problem. + */ + return false; + case 1: + /* + * Fault caused by protection of cached translation; TBs + * invalidated, so resume execution. Retain helper_retaddr + * for a possible second fault. + */ + return true; + case 2: + /* + * Fault caused by protection of cached translation, and the + * currently executing TB was modified and must be exited + * immediately. Clear helper_retaddr for next execution. + */ + cpu_exit_tb_from_sighandler(cpu, old_set); + /* NORETURN */ + default: + g_assert_not_reached(); + } +} + /* * 'pc' is the host PC at which the exception was raised. * 'address' is the effective address of the memory exception. @@ -125,8 +173,9 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, { CPUState *cpu = current_cpu; CPUClass *cc; - unsigned long address = (unsigned long)info->si_addr; + unsigned long host_addr = (unsigned long)info->si_addr; MMUAccessType access_type = adjust_signal_pc(&pc, is_write); + abi_ptr guest_addr; /* For synchronous signals we expect to be coming from the vCPU * thread (so current_cpu should be valid) and either from running @@ -143,49 +192,21 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, #if defined(DEBUG_SIGNAL) printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", - pc, address, is_write, *(unsigned long *)old_set); + pc, host_addr, is_write, *(unsigned long *)old_set); #endif - /* XXX: locking issue */ - /* Note that it is important that we don't call page_unprotect() unless - * this is really a "write to nonwriteable page" fault, because - * page_unprotect() assumes that if it is called for an access to - * a page that's writeable this means we had two threads racing and - * another thread got there first and already made the page writeable; - * so we will retry the access. If we were to call page_unprotect() - * for some other kind of fault that should really be passed to the - * guest, we'd end up in an infinite loop of retrying the faulting - * access. - */ - if (is_write && info->si_signo == SIGSEGV && info->si_code == SEGV_ACCERR && - h2g_valid(address)) { - switch (page_unprotect(h2g(address), pc)) { - case 0: - /* Fault not caused by a page marked unwritable to protect - * cached translations, must be the guest binary's problem. - */ - break; - case 1: - /* Fault caused by protection of cached translation; TBs - * invalidated, so resume execution. Retain helper_retaddr - * for a possible second fault. - */ - return 1; - case 2: - /* Fault caused by protection of cached translation, and the - * currently executing TB was modified and must be exited - * immediately. Clear helper_retaddr for next execution. - */ - cpu_exit_tb_from_sighandler(cpu, old_set); - /* NORETURN */ - - default: - g_assert_not_reached(); - } - } /* Convert forcefully to guest address space, invalid addresses are still valid segv ones */ - address = h2g_nocheck(address); + guest_addr = h2g_nocheck(host_addr); + + /* XXX: locking issue */ + if (is_write && + info->si_signo == SIGSEGV && + info->si_code == SEGV_ACCERR && + h2g_valid(host_addr) && + handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) { + return 1; + } /* * There is no way the target can handle this other than raising @@ -194,7 +215,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, sigprocmask(SIG_SETMASK, old_set, NULL); cc = CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, address, 0, access_type, + cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, MMU_USER_IDX, false, pc); g_assert_not_reached(); } From patchwork Fri Oct 1 17:11:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515064 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1005454jaf; Fri, 1 Oct 2021 10:23:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwS/MVGcSSqoycpo24Fdo80kifX92W3bKouY/zhuErwlnuZLsyvMs7SFUcgQPFD/0Zfw65J X-Received: by 2002:a05:6102:21ce:: with SMTP id r14mr5468593vsg.40.1633109018462; Fri, 01 Oct 2021 10:23:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633109018; cv=none; d=google.com; s=arc-20160816; b=PC1ipZNeksrBJCN4PeVRDJ7FJ4sB23OlS0yDQsuFL3SpHNhk9F12W0JQEkw8TqhRmx ugIcmJyAserdKZF7kx/FLS14NObPu6TtLWKUDjVwbhk07Jz2JCGgK6q6TMfTIafPpg7z jLFpOoY5c3sbWsqa7h/Lygxm+dgqO3yR7s9suF1bfe6glMWokFdG1c9fKcsayvrjLtBG +7n6tBs93e/x0vUIcGOrTOJFSYdPXOzXxLL1L3lgAXnrW6JB6Xcd/dPWcYmlTno9bx9S gxb6S7YK4JRYquMjnYCHfBBXjDCVeg9X39fou8v5o9R9MS+udg6Uhg4lqYfeZlQZn3DN URrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lQDDeP4KrE59xBXWzR54VwCb3z15HLMlRMki+IJBEEo=; b=nu6MY1++T84ucdI1LHUZdVUPGEowrGKRhtJr4bjPEJuS9iIsO93pkMsJ3Z/o5DfoPR HUbGJ56C9pSBI9RiwUsZW6P68xb2bsCLAdpUR6Y8yixIyvN2ymIDDJyjzSmtGH0hKK0Q rAQj8MYEQeLcxij04gYZVNu3MoZt0Vh/mXrGjIHynyRZsCXJpbFO2bUJaX6z0qTIKo/8 rlHTFC0LhhdyhJN8ArqG10sTDgDg58sUH5iZUBmLt1BaP+CiCQOjY0Hg8cBRuRlaTuDm IEeBt/h/Pw6/dIqMtFwuJVzETuwAtoI6YnwLGJmxLi4v100G1Pty76isPgbFijcSMLCg O3Nw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VXoI1wrn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.11.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:11:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 04/41] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Date: Fri, 1 Oct 2021 13:11:14 -0400 Message-Id: <20211001171151.1739472-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f36; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the comment about siglongjmp. We do use sigsetjmp in the main cpu loop, but we do not save the signal mask as most exits from the cpu loop do not require them. Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 6f4fc01b60..de4565f13e 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -46,17 +46,6 @@ __thread uintptr_t helper_retaddr; //#define DEBUG_SIGNAL -/* exit the current TB from a signal handler. The host registers are - restored in a state compatible with the CPU emulator - */ -static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu, - sigset_t *old_set) -{ - /* XXX: use siglongjmp ? */ - sigprocmask(SIG_SETMASK, old_set, NULL); - cpu_loop_exit_noexc(cpu); -} - /* * Adjust the pc to pass to cpu_restore_state; return the memop type. */ @@ -155,7 +144,8 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, * currently executing TB was modified and must be exited * immediately. Clear helper_retaddr for next execution. */ - cpu_exit_tb_from_sighandler(cpu, old_set); + sigprocmask(SIG_SETMASK, old_set, NULL); + cpu_loop_exit_noexc(cpu); /* NORETURN */ default: g_assert_not_reached(); From patchwork Fri Oct 1 17:11:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515057 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1000211jaf; Fri, 1 Oct 2021 10:17:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyh4owPbZZioZ1DbaunnChT1FaYR5mokJFbEaiWf2StvX1dSVC4ka5VIMTE1bAkg790zTu9 X-Received: by 2002:a5d:64cf:: with SMTP id f15mr13581362wri.284.1633108638574; Fri, 01 Oct 2021 10:17:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633108638; cv=none; d=google.com; s=arc-20160816; b=f4T3cMj81+YYBDLiZSsZWt1G2o0u2UG//NvSaQWvPZx5+aQFdpLXGTB9rgaeBUhHSO waEt1xCkKZWEqZH2clT91d4+hejFM/LZ83Ln6rPdnz0hktBNL4XaRimoTH/IBZeJhMSC Kq/V6degfbOtUyWtigJYiTyKXgiPkyFPBVKOUnr29OSZZoLJIjPw1MhFWZhLHszR0ifr nsNBZYgI6//jlBAeR++g7pZzXe7ELFt1QtEHeZBhDUxC/0G7YHAeHYgfYW2Z6ADBFC6N rcEH10NAnEDeA/GizmWtsUrdHPpXPxrSOzT2+Ex4LEtiiO0J6S391s88avyALmUoXTPx H6Sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nXiWOopBLOLRsE3QCVjUHoJD6t3B8cBROMNMjuCuDVo=; b=N+M1XGnIgX9S3sRiOIynOm/607dPn0EM1IOKE4kcOKfl7f1E7EAz8tYgkCY30FlLL4 wXMGK9x6v0cacrMJ5goAb8tT07hX2SHmsFeLIcDeXNHGeEwTI6S3E8TCFG1XMFe4XZ4E K8nClD7T7ED3MzbMEBdp2yfP6R4iBuj2tBrtKXvR4iI6ZCjoErtfGA6PVj8uU+GKyMji Qwf2esMVYSW9/E1i+cFBzZPrF9Yn6g2APtFtNOtaI2d9PKpziPr/S/5tTg5d6RVyzXk4 3zSDnpKPf5Fjdokr7W/1RFZSOCpbbfuDW2C4dzzSWWolBbNZRNch79xkFuq74AXhCe2L yPYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X3O4gEzG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.11.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:11:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 05/41] configure: Merge riscv32 and riscv64 host architectures Date: Fri, 1 Oct 2021 13:11:15 -0400 Message-Id: <20211001171151.1739472-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::829; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x829.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The existing code for safe-syscall.inc.S will compile without change for riscv32 and riscv64. We may also drop the meson.build stanza that merges them for tcg/. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- configure | 8 ++------ meson.build | 4 +--- linux-user/host/{riscv64 => riscv}/hostdep.h | 4 ++-- linux-user/host/riscv32/hostdep.h | 11 ----------- linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S | 0 5 files changed, 5 insertions(+), 22 deletions(-) rename linux-user/host/{riscv64 => riscv}/hostdep.h (94%) delete mode 100644 linux-user/host/riscv32/hostdep.h rename linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S (100%) -- 2.25.1 diff --git a/configure b/configure index 1043ccce4f..23ede08582 100755 --- a/configure +++ b/configure @@ -650,11 +650,7 @@ elif check_define __s390__ ; then cpu="s390" fi elif check_define __riscv ; then - if check_define _LP64 ; then - cpu="riscv64" - else - cpu="riscv32" - fi + cpu="riscv" elif check_define __arm__ ; then cpu="arm" elif check_define __aarch64__ ; then @@ -667,7 +663,7 @@ ARCH= # Normalise host CPU name and set ARCH. # Note that this case should only have supported host CPUs, not guests. case "$cpu" in - ppc|ppc64|s390x|sparc64|x32|riscv32|riscv64) + ppc|ppc64|s390x|sparc64|x32|riscv) ;; ppc64le) ARCH="ppc64" diff --git a/meson.build b/meson.build index 7bdbbbdf02..30cb165b3b 100644 --- a/meson.build +++ b/meson.build @@ -56,7 +56,7 @@ have_block = have_system or have_tools python = import('python').find_installation() supported_oses = ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', 'sunos', 'linux'] -supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', 'x86_64', +supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64', 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] cpu = host_machine.cpu_family() @@ -278,8 +278,6 @@ if not get_option('tcg').disabled() tcg_arch = 'i386' elif config_host['ARCH'] == 'ppc64' tcg_arch = 'ppc' - elif config_host['ARCH'] in ['riscv32', 'riscv64'] - tcg_arch = 'riscv' endif add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' / tcg_arch, language: ['c', 'cpp', 'objc']) diff --git a/linux-user/host/riscv64/hostdep.h b/linux-user/host/riscv/hostdep.h similarity index 94% rename from linux-user/host/riscv64/hostdep.h rename to linux-user/host/riscv/hostdep.h index 865f0fb9ff..2ba07456ae 100644 --- a/linux-user/host/riscv64/hostdep.h +++ b/linux-user/host/riscv/hostdep.h @@ -5,8 +5,8 @@ * See the COPYING file in the top-level directory. */ -#ifndef RISCV64_HOSTDEP_H -#define RISCV64_HOSTDEP_H +#ifndef RISCV_HOSTDEP_H +#define RISCV_HOSTDEP_H /* We have a safe-syscall.inc.S */ #define HAVE_SAFE_SYSCALL diff --git a/linux-user/host/riscv32/hostdep.h b/linux-user/host/riscv32/hostdep.h deleted file mode 100644 index adf9edbf2d..0000000000 --- a/linux-user/host/riscv32/hostdep.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef RISCV32_HOSTDEP_H -#define RISCV32_HOSTDEP_H - -#endif diff --git a/linux-user/host/riscv64/safe-syscall.inc.S b/linux-user/host/riscv/safe-syscall.inc.S similarity index 100% rename from linux-user/host/riscv64/safe-syscall.inc.S rename to linux-user/host/riscv/safe-syscall.inc.S From patchwork Fri Oct 1 17:11:16 2021 Content-Type: text/plain; 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.11.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:11:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 06/41] linux-user: Reorg handling for SIGSEGV Date: Fri, 1 Oct 2021 13:11:16 -0400 Message-Id: <20211001171151.1739472-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82c; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, Warner Losh , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add stub host-signal.h for all linux-user hosts. Add new code replacing cpu_signal_handler. Full migration will happen one host at a time. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 1 + linux-user/host/arm/host-signal.h | 1 + linux-user/host/i386/host-signal.h | 1 + linux-user/host/mips/host-signal.h | 1 + linux-user/host/ppc/host-signal.h | 1 + linux-user/host/ppc64/host-signal.h | 1 + linux-user/host/riscv/host-signal.h | 1 + linux-user/host/s390/host-signal.h | 1 + linux-user/host/s390x/host-signal.h | 1 + linux-user/host/sparc/host-signal.h | 1 + linux-user/host/sparc64/host-signal.h | 1 + linux-user/host/x32/host-signal.h | 1 + linux-user/host/x86_64/host-signal.h | 1 + linux-user/signal.c | 109 ++++++++++++++++++++++---- 14 files changed, 106 insertions(+), 16 deletions(-) create mode 100644 linux-user/host/aarch64/host-signal.h create mode 100644 linux-user/host/arm/host-signal.h create mode 100644 linux-user/host/i386/host-signal.h create mode 100644 linux-user/host/mips/host-signal.h create mode 100644 linux-user/host/ppc/host-signal.h create mode 100644 linux-user/host/ppc64/host-signal.h create mode 100644 linux-user/host/riscv/host-signal.h create mode 100644 linux-user/host/s390/host-signal.h create mode 100644 linux-user/host/s390x/host-signal.h create mode 100644 linux-user/host/sparc/host-signal.h create mode 100644 linux-user/host/sparc64/host-signal.h create mode 100644 linux-user/host/x32/host-signal.h create mode 100644 linux-user/host/x86_64/host-signal.h -- 2.25.1 diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch64/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/aarch64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/arm/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/i386/host-signal.h b/linux-user/host/i386/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/i386/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/mips/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/ppc/host-signal.h b/linux-user/host/ppc/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/ppc/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/ppc64/host-signal.h b/linux-user/host/ppc64/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/ppc64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/riscv/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/s390/host-signal.h b/linux-user/host/s390/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/s390/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/s390x/host-signal.h b/linux-user/host/s390x/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/s390x/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/sparc/host-signal.h b/linux-user/host/sparc/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/sparc/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/sparc64/host-signal.h b/linux-user/host/sparc64/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/sparc64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/x32/host-signal.h b/linux-user/host/x32/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/x32/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/x86_64/host-signal.h b/linux-user/host/x86_64/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/x86_64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/signal.c b/linux-user/signal.c index 2038216455..bab47a6962 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/bitops.h" #include "exec/gdbstub.h" +#include "hw/core/tcg-cpu-ops.h" #include #include @@ -29,6 +30,7 @@ #include "loader.h" #include "trace.h" #include "signal-common.h" +#include "host-signal.h" static struct target_sigaction sigact_table[TARGET_NSIG]; @@ -766,41 +768,116 @@ static inline void rewind_if_in_safe_syscall(void *puc) } #endif -static void host_signal_handler(int host_signum, siginfo_t *info, - void *puc) +static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) { CPUArchState *env = thread_cpu->env_ptr; CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; - - int sig; target_siginfo_t tinfo; ucontext_t *uc = puc; struct emulated_sigtable *k; + int guest_sig; +#ifdef HOST_SIGNAL_PLACEHOLDER /* the CPU emulator uses some host signals to detect exceptions, we forward to it some signals */ - if ((host_signum == SIGSEGV || host_signum == SIGBUS) + if ((host_sig == SIGSEGV || host_sig == SIGBUS) && info->si_code > 0) { - if (cpu_signal_handler(host_signum, info, puc)) + if (cpu_signal_handler(host_sig, info, puc)) { return; + } } +#else + uintptr_t pc = 0; + bool sync_sig = false; + + /* + * Non-spoofed SIGSEGV and SIGBUS are synchronous, and need special + * handling wrt signal blocking and unwinding. + */ + if ((host_sig == SIGSEGV || host_sig == SIGBUS) && info->si_code > 0) { + MMUAccessType access_type; + uintptr_t host_addr; + abi_ptr guest_addr; + bool is_write; + + host_addr = (uintptr_t)info->si_addr; + + /* + * Convert forcefully to guest address space: addresses outside + * reserved_va are still valid to report via SEGV_MAPERR. + */ + guest_addr = h2g_nocheck(host_addr); + + pc = host_signal_pc(uc); + is_write = host_signal_write(info, uc); + access_type = adjust_signal_pc(&pc, is_write); + + if (host_sig == SIGSEGV) { + const struct TCGCPUOps *tcg_ops; + + if (info->si_code == SEGV_ACCERR && h2g_valid(host_addr)) { + /* If this was a write to a TB protected page, restart. */ + if (is_write && + handle_sigsegv_accerr_write(cpu, &uc->uc_sigmask, + pc, guest_addr)) { + return; + } + + /* + * With reserved_va, the whole address space is PROT_NONE, + * which means that we may get ACCERR when we want MAPERR. + */ + if (page_get_flags(guest_addr) & PAGE_VALID) { + /* maperr = false; */ + } else { + info->si_code = SEGV_MAPERR; + } + } + + sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + + tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, + MMU_USER_IDX, false, pc); + g_assert_not_reached(); + } else { + sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + } + + sync_sig = true; + } +#endif /* get target signal number */ - sig = host_to_target_signal(host_signum); - if (sig < 1 || sig > TARGET_NSIG) + guest_sig = host_to_target_signal(host_sig); + if (guest_sig < 1 || guest_sig > TARGET_NSIG) { return; - trace_user_host_signal(env, host_signum, sig); + } + trace_user_host_signal(env, host_sig, guest_sig); + + host_to_target_siginfo_noswap(&tinfo, info); + k = &ts->sigtab[guest_sig - 1]; + k->info = tinfo; + k->pending = guest_sig; + ts->signal_pending = 1; + +#ifndef HOST_SIGNAL_PLACEHOLDER + /* + * For synchronous signals, unwind the cpu state to the faulting + * insn and then exit back to the main loop so that the signal + * is delivered immediately. + */ + if (sync_sig) { + cpu->exception_index = EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, pc); + } +#endif rewind_if_in_safe_syscall(puc); - host_to_target_siginfo_noswap(&tinfo, info); - k = &ts->sigtab[sig - 1]; - k->info = tinfo; - k->pending = sig; - ts->signal_pending = 1; - - /* Block host signals until target signal handler entered. We + /* + * Block host signals until target signal handler entered. We * can't block SIGSEGV or SIGBUS while we're executing guest * code in case the guest code provokes one in the window between * now and it getting out to the main loop. Signals will be From patchwork Fri Oct 1 17:11:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515054 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp997592jaf; Fri, 1 Oct 2021 10:14:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz66Q9XfagisQ9r5LKm6iA7yBxCew3LbyGtMOB4q+74b2PzbBpNXGdfZQWEFa/g4mvhU18x X-Received: by 2002:a1c:f002:: with SMTP id a2mr5714035wmb.79.1633108457704; Fri, 01 Oct 2021 10:14:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633108457; cv=none; d=google.com; s=arc-20160816; b=FCgZOaG/OWHgPG2culg2Xm3AUrU5pFETkPlC9bq0knCeviQw4O92g7E0/4CXTgnj1+ bcHYW7Bd37vDNhDFKANuhDIdh8JYYK7rJbFKmCyKsCx9kEZ1UizzzCprduSLuqi6HJJ2 CRE0gxUXN+RGT02ongjJzU4lXHXQ/wrEiAfNukmigiG/eGctxaWY4E9lptXoj9hWNaC8 ikYT/QMJ4NV3c5WIF7Bup2jX1CGUHFbIyohIg7XCYI8PinInLer+Z9u8pj2rAfrEOra5 FtdJn6bA7irDxiAWknfVZmUgvvR5CLlXLbENFgwoN2UE/K8BPJTUYH9L67eRrb0XoL5w Xjzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=eo69a6qpbSWMyVxfRxEgkjHG9EovPVD2b2o16GmRH3A=; b=qLzxkN1mrkw8zgLhsCNTjcq5vf61S6cKaM5VvrB6bHEl6nH5exff4sl3p5NLO0WaaJ Nk+CupUF6mcbifCDJdbLFE9LiAPx0eru+2bb91L3IMZIEAjrrjDC16azEPRKSfImJD1L iW7LujmHf7ZJ3TedamD3I5kqotW6NLmz02o0E1PmASsbTxT6ipqAI80hDAnmvvb8qzAR TogY+VcXTg/DiqW7Ehkz5nCWmr31p7lBnJw6JRE6sfjJzW+OobzDwWW92d1tZzdgFUgr MUaR3Uk6YLMITm8Bemh4bip4Qn9NNoGI2m5iiPzugStuTyGfrtNyGensdIFg84LNOWfm dcwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XRgiJ10U; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.11.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:11:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 07/41] linux-user/host/x86: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:17 -0400 Message-Id: <20211001171151.1739472-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::830; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x830.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson --- linux-user/host/i386/host-signal.h | 25 ++++- linux-user/host/x32/host-signal.h | 2 +- linux-user/host/x86_64/host-signal.h | 25 ++++- accel/tcg/user-exec.c | 136 +-------------------------- 4 files changed, 50 insertions(+), 138 deletions(-) -- 2.25.1 diff --git a/linux-user/host/i386/host-signal.h b/linux-user/host/i386/host-signal.h index f4b4d65031..ccbbee5082 100644 --- a/linux-user/host/i386/host-signal.h +++ b/linux-user/host/i386/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef I386_HOST_SIGNAL_H +#define I386_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_EIP]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe + && (uc->uc_mcontext.gregs[REG_ERR] & 0x2); +} + +#endif diff --git a/linux-user/host/x32/host-signal.h b/linux-user/host/x32/host-signal.h index f4b4d65031..26800591d3 100644 --- a/linux-user/host/x32/host-signal.h +++ b/linux-user/host/x32/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../x86_64/host-signal.h" diff --git a/linux-user/host/x86_64/host-signal.h b/linux-user/host/x86_64/host-signal.h index f4b4d65031..883d2fcf65 100644 --- a/linux-user/host/x86_64/host-signal.h +++ b/linux-user/host/x86_64/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef X86_64_HOST_SIGNAL_H +#define X86_64_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_RIP]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe + && (uc->uc_mcontext.gregs[REG_ERR] & 0x2); +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index de4565f13e..b5d06183db 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -29,19 +29,6 @@ #include "trace/trace-root.h" #include "trace/mem.h" -#undef EAX -#undef ECX -#undef EDX -#undef EBX -#undef ESP -#undef EBP -#undef ESI -#undef EDI -#undef EIP -#ifdef __linux__ -#include -#endif - __thread uintptr_t helper_retaddr; //#define DEBUG_SIGNAL @@ -268,123 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__i386__) - -#if defined(__NetBSD__) -#include -#include - -#define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__FreeBSD__) || defined(__DragonFly__) -#include -#include - -#define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip)) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) -#define ERROR_sig(context) ((context)->uc_mcontext.mc_err) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__OpenBSD__) -#include -#define EIP_sig(context) ((context)->sc_eip) -#define TRAP_sig(context) ((context)->sc_trapno) -#define ERROR_sig(context) ((context)->sc_err) -#define MASK_sig(context) ((context)->sc_mask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#else -#define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP 0xe -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; -#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) - ucontext_t *uc = puc; -#elif defined(__OpenBSD__) - struct sigcontext *uc = puc; -#else - ucontext_t *uc = puc; -#endif - unsigned long pc; - int trapno; - -#ifndef REG_EIP -/* for glibc 2.1 */ -#define REG_EIP EIP -#define REG_ERR ERR -#define REG_TRAPNO TRAPNO -#endif - pc = EIP_sig(uc); - trapno = TRAP_sig(uc); - return handle_cpu_signal(pc, info, - trapno == PAGE_FAULT_TRAP ? - (ERROR_sig(uc) >> 1) & 1 : 0, - &MASK_sig(uc)); -} - -#elif defined(__x86_64__) - -#ifdef __NetBSD__ -#include -#define PC_sig(context) _UC_MACHINE_PC(context) -#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__OpenBSD__) -#include -#define PC_sig(context) ((context)->sc_rip) -#define TRAP_sig(context) ((context)->sc_trapno) -#define ERROR_sig(context) ((context)->sc_err) -#define MASK_sig(context) ((context)->sc_mask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__FreeBSD__) || defined(__DragonFly__) -#include -#include - -#define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip)) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) -#define ERROR_sig(context) ((context)->uc_mcontext.mc_err) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#else -#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP 0xe -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - unsigned long pc; -#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) - ucontext_t *uc = puc; -#elif defined(__OpenBSD__) - struct sigcontext *uc = puc; -#else - ucontext_t *uc = puc; -#endif - - pc = PC_sig(uc); - return handle_cpu_signal(pc, info, - TRAP_sig(uc) == PAGE_FAULT_TRAP ? - (ERROR_sig(uc) >> 1) & 1 : 0, - &MASK_sig(uc)); -} - -#elif defined(_ARCH_PPC) +#if defined(_ARCH_PPC) /*********************************************************************** * signal context platform-specific definitions @@ -895,11 +766,6 @@ int cpu_signal_handler(int host_signum, void *pinfo, return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } - -#else - -#error host CPU specific signal handler needed - #endif /* The softmmu versions of these helpers are in cputlb.c. */ From patchwork Fri Oct 1 17:11:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515059 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1000553jaf; Fri, 1 Oct 2021 10:17:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJziyWt7OM19Ij1h1uh/FuZwbpBgOLt45DuK+NYgPRHMQJbmuT13OTqHw/meXBaVlzLyNOJb X-Received: by 2002:a67:1004:: with SMTP id 4mr5718672vsq.26.1633108662207; Fri, 01 Oct 2021 10:17:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633108662; cv=none; d=google.com; s=arc-20160816; b=KylFZlx6D1ydt5cJQvw6AJiIEOm8wzmButFn6C07jFiu2jWxna6ecOS9xSQoM6kjgt yxo7qw4sg/bDEBFcwV1ZArupr/5AU6lu891b2j2YtCE9dCRCtSVhglF+kovDWD46nXzr AwNv52uUB+a77QXxjLOc4TW2vl6KRXLPDOUYJmWjdJlyM1JqypRJwr1guH/0oQC0IDRd XNkxdFF4sthLg2wbyz+r9e2I3yVFLgD/Tib5nfrnPzaN/tuoXFQKu5E21E8cxIr500of VblpZslOVKCvYbkkV6wXwZbss0pLA9S8lr55sG8uDDAj++Mm2Z/xwA8fY7ZEhWk+OIgl uuHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6fVjVy4AkVzaH6Z0yyaREpJWIPed0v0p7SS/ifUGXt0=; b=QB3jcsGtZ51PwNdvctgClEFUfUlodr0/RKYTiFlk78wAqhORrWiHHojcOBsgQtaqqP cxiw4to+TOzM/87v2BuOk2sQaC+wg/dcjyCyzaaBFVR/QA2xC6UpUqJb9ZGQABGeIwB2 jJUoymFy+3JZblur9v1pXjZQnv7Bqkc6FCdJRJfNCkd6G2AO5uSZaoPwPMIA7xLQ1RGs hZQ3wtmmzrWnY0SapwjAXkbK6a9ZrsvwpcaDDJk7yDbDhquIf0XAsxTqlVPDXkuJuFmx +M2Qhv3hHPLQz1d/Xv4UjRy+8qhHb+sM9Eo5kfaMcqvCiw0+UzbADoSpbDcUipFUcqP6 3ZBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WD6ib4KH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.11.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 08/41] linux-user/host/ppc: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:18 -0400 Message-Id: <20211001171151.1739472-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2d; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- linux-user/host/ppc/host-signal.h | 25 ++++++++- linux-user/host/ppc64/host-signal.h | 2 +- accel/tcg/user-exec.c | 79 +---------------------------- 3 files changed, 26 insertions(+), 80 deletions(-) -- 2.25.1 diff --git a/linux-user/host/ppc/host-signal.h b/linux-user/host/ppc/host-signal.h index f4b4d65031..e09756c691 100644 --- a/linux-user/host/ppc/host-signal.h +++ b/linux-user/host/ppc/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef PPC_HOST_SIGNAL_H +#define PPC_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.regs->nip; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.regs->trap != 0x400 + && (uc->uc_mcontext.regs->dsisr & 0x02000000); +} + +#endif diff --git a/linux-user/host/ppc64/host-signal.h b/linux-user/host/ppc64/host-signal.h index f4b4d65031..a353c22a90 100644 --- a/linux-user/host/ppc64/host-signal.h +++ b/linux-user/host/ppc64/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../ppc/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index b5d06183db..e9e530e2e1 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,84 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(_ARCH_PPC) - -/*********************************************************************** - * signal context platform-specific definitions - * From Wine - */ -#ifdef linux -/* All Registers access - only for local access */ -#define REG_sig(reg_name, context) \ - ((context)->uc_mcontext.regs->reg_name) -/* Gpr Registers access */ -#define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) -/* Program counter */ -#define IAR_sig(context) REG_sig(nip, context) -/* Machine State Register (Supervisor) */ -#define MSR_sig(context) REG_sig(msr, context) -/* Count register */ -#define CTR_sig(context) REG_sig(ctr, context) -/* User's integer exception register */ -#define XER_sig(context) REG_sig(xer, context) -/* Link register */ -#define LR_sig(context) REG_sig(link, context) -/* Condition register */ -#define CR_sig(context) REG_sig(ccr, context) - -/* Float Registers access */ -#define FLOAT_sig(reg_num, context) \ - (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num]) -#define FPSCR_sig(context) \ - (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4))) -/* Exception Registers access */ -#define DAR_sig(context) REG_sig(dar, context) -#define DSISR_sig(context) REG_sig(dsisr, context) -#define TRAP_sig(context) REG_sig(trap, context) -#endif /* linux */ - -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) -#include -#define IAR_sig(context) ((context)->uc_mcontext.mc_srr0) -#define MSR_sig(context) ((context)->uc_mcontext.mc_srr1) -#define CTR_sig(context) ((context)->uc_mcontext.mc_ctr) -#define XER_sig(context) ((context)->uc_mcontext.mc_xer) -#define LR_sig(context) ((context)->uc_mcontext.mc_lr) -#define CR_sig(context) ((context)->uc_mcontext.mc_cr) -/* Exception Registers access */ -#define DAR_sig(context) ((context)->uc_mcontext.mc_dar) -#define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_exc) -#endif /* __FreeBSD__|| __FreeBSD_kernel__ */ - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) - ucontext_t *uc = puc; -#else - ucontext_t *uc = puc; -#endif - unsigned long pc; - int is_write; - - pc = IAR_sig(uc); - is_write = 0; -#if 0 - /* ppc 4xx case */ - if (DSISR_sig(uc) & 0x00800000) { - is_write = 1; - } -#else - if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) { - is_write = 1; - } -#endif - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__alpha__) +#if defined(__alpha__) int cpu_signal_handler(int host_signum, void *pinfo, void *puc) From patchwork Fri Oct 1 17:11:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515070 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1008743jaf; Fri, 1 Oct 2021 10:28:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJziTL4wmMpVUH7dk8o7Y3ghdcgav75X0PnuZDKW+HzlNmrm23ChVgWKfK4b6vM1NzPIuIdX X-Received: by 2002:a05:6122:1681:: with SMTP id 1mr8554096vkl.9.1633109280429; Fri, 01 Oct 2021 10:28:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633109280; cv=none; d=google.com; s=arc-20160816; b=kpl4pMP8FPmVenPfuMhFwuPR+d0r6ahkDqWVQnsQFjXz6NL80D48Q5otg2ffV57k9i J0ZlwXEQC2uOkVhWDUtu+ynI/09tZfSqtZsVxbiOBQ5YwbPrPty0WeZprZ64SF/Sd+X9 16Frw5/kmnGN2nBNb4YnA6vCGiAGX9TC6f/wW2s8BH4xupf7rd0V67RYP365s2CqrHY2 zkpUa2jgUnonWTLjpuHc/p5hRe1g7064VoGW2KcGK78forQrGkPstKmvEWk6T0h63J9o JiDJfcMgxhqYnmVy0T1UNtzgLPG6MWTogc9VSYE7WB9pQLfft7cPQgpPChAdCEYRsBjn A12Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lavEGkgqky/ZtxbH6vUwcfGBAKCbGr33b9BznRGO5aU=; b=DkL0RLkdsiTr63DUkhN9Eqq9dI8UD7LW9xiTsRzk/35WKifUMv64I5G5DXf+4fS6dP ug5b75U6RCRDwV/0rHGROa6LYOltgN10jkJS46xT8X6sBLaCR3SJnY3h/Y5O04OtQde7 1Q56OhWOfxOY8GHC9PoQMAO1X1O+1R2UNRelawOqVEY/uOo1css3TqoyMf79miqmYp1V fDGd8EldrbH4ieYHRLrC7jD1UFwRRRbTrdJPMop3EwdFRoh68lHRpjuiZR3u/5efeUOU kI4vSKRbn8VIeRxTU3b+o5rH5iIbRrjFDIBZAVKtqPuIUaHAR3YxdhrQTeOv/e+QbYvi 4YPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zARl9BpO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 09/41] linux-user/host/alpha: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:19 -0400 Message-Id: <20211001171151.1739472-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82f; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/alpha/host-signal.h | 41 +++++++++++++++++++++++++++++ accel/tcg/user-exec.c | 31 +--------------------- 2 files changed, 42 insertions(+), 30 deletions(-) create mode 100644 linux-user/host/alpha/host-signal.h -- 2.25.1 diff --git a/linux-user/host/alpha/host-signal.h b/linux-user/host/alpha/host-signal.h new file mode 100644 index 0000000000..e27704d832 --- /dev/null +++ b/linux-user/host/alpha/host-signal.h @@ -0,0 +1,41 @@ +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef ALPHA_HOST_SIGNAL_H +#define ALPHA_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.sc_pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t *pc = (uint32_t *)host_signal_pc(uc); + uint32_t insn = *pc; + + /* XXX: need kernel patch to get write flag faster */ + switch (insn >> 26) { + case 0x0d: /* stw */ + case 0x0e: /* stb */ + case 0x0f: /* stq_u */ + case 0x24: /* stf */ + case 0x25: /* stg */ + case 0x26: /* sts */ + case 0x27: /* stt */ + case 0x2c: /* stl */ + case 0x2d: /* stq */ + case 0x2e: /* stl_c */ + case 0x2f: /* stq_c */ + return true; + } + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e9e530e2e1..b895b5c8bd 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,36 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__alpha__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - uint32_t *pc = uc->uc_mcontext.sc_pc; - uint32_t insn = *pc; - int is_write = 0; - - /* XXX: need kernel patch to get write flag faster */ - switch (insn >> 26) { - case 0x0d: /* stw */ - case 0x0e: /* stb */ - case 0x0f: /* stq_u */ - case 0x24: /* stf */ - case 0x25: /* stg */ - case 0x26: /* sts */ - case 0x27: /* stt */ - case 0x2c: /* stl */ - case 0x2d: /* stq */ - case 0x2e: /* stl_c */ - case 0x2f: /* stq_c */ - is_write = 1; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#elif defined(__sparc__) +#if defined(__sparc__) int cpu_signal_handler(int host_signum, void *pinfo, void *puc) From patchwork Fri Oct 1 17:11:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515074 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1011635jaf; Fri, 1 Oct 2021 10:31:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxvP5DiT2cCOAOjsTq7c8BJXdx0OFWDKHC3iU+QPZhYrCbr5HsbdVDfL3YVkviGOppMqFPt X-Received: by 2002:a67:c295:: with SMTP id k21mr2879769vsj.37.1633109489221; Fri, 01 Oct 2021 10:31:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633109489; cv=none; d=google.com; s=arc-20160816; b=CUKBx9mMzz2r9lOuYeaqGBD8rgrlb8dM6d9qpxk0F/8TFH2syqJA+ZlLo+JqfMoI9W PugXbXO3l+7RSVrxkWu0JP9e4XsKIBtqt+mEmdoXBNOVivTJVZieKs/wlEaPJXabkzQW DXvvMIssMW+BnwXz/UYn6wJL/6JK9DjcTOu/1f5BioO8aPqJe8LocKlWIrlx1a80RHBZ rboyb3qHv0qlSs87EdQTgzW/a+BQTYFdtEXj3UkmEqkP9O3UMAsrUndttpxc4AkTqLVK BQgU2K2T2MSgGwJfZ6PzaptAvLUc7yX5CN357J2l7YgazZNGG+y5uf5EdYpKSjCQPgHr xZyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SHk0L4QVJKHbdhHw2ZILrKhqMEpfB7Y/GR3loPVJEL4=; b=St/t4nCHOfWN5POCEE38Uq2kq8n7JvBR2saWKLnDRu/0rV9pk8zN8C8zBatY9S0O2u Hvh6syBiZtd4+5oz0cxa4jIryAieatC+/nygNPE2K02E1Ynz7DdBUTMzWlayU9es/6JQ ElO2yEcVq1S67fyyXVTVR6booj28VR6C8Rk46B8iRxBClWSwf3BUKkhULKlmyeZuEBNs 80c08x/Tv9eiKlQC4/TD90iq3ZKm6AFRerGbUlEDwZbIPXnajYf0hJOI5XdhJ/Gx+VvD D4Xt4xo9xxpnuvvfhYkgKHQku+DIPhqGuUhiiw1nu2VOuG7iCKEGwYCzUTqTDTzrVkeQ E5wg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VOPV7a5M; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 10/41] linux-user/host/sparc: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:20 -0400 Message-Id: <20211001171151.1739472-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::833; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x833.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Drop the Solais code as completely unused. Signed-off-by: Richard Henderson --- linux-user/host/sparc/host-signal.h | 54 ++++++++++++++++++++++- linux-user/host/sparc64/host-signal.h | 2 +- accel/tcg/user-exec.c | 62 +-------------------------- 3 files changed, 55 insertions(+), 63 deletions(-) -- 2.25.1 diff --git a/linux-user/host/sparc/host-signal.h b/linux-user/host/sparc/host-signal.h index f4b4d65031..232943a1db 100644 --- a/linux-user/host/sparc/host-signal.h +++ b/linux-user/host/sparc/host-signal.h @@ -1 +1,53 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef SPARC_HOST_SIGNAL_H +#define SPARC_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ +#ifdef __arch64__ + return uc->uc_mcontext.mc_gregs[MC_PC]; +#else + return uc->uc_mcontext.gregs[REG_PC]; +#endif +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn = *(uint32_t *)host_signal_pc(uc); + + if ((insn >> 30) == 3) { + switch ((insn >> 19) & 0x3f) { + case 0x05: /* stb */ + case 0x15: /* stba */ + case 0x06: /* sth */ + case 0x16: /* stha */ + case 0x04: /* st */ + case 0x14: /* sta */ + case 0x07: /* std */ + case 0x17: /* stda */ + case 0x0e: /* stx */ + case 0x1e: /* stxa */ + case 0x24: /* stf */ + case 0x34: /* stfa */ + case 0x27: /* stdf */ + case 0x37: /* stdfa */ + case 0x26: /* stqf */ + case 0x36: /* stqfa */ + case 0x25: /* stfsr */ + case 0x3c: /* casa */ + case 0x3e: /* casxa */ + return true; + } + } + return false; +} + +#endif diff --git a/linux-user/host/sparc64/host-signal.h b/linux-user/host/sparc64/host-signal.h index f4b4d65031..1191fe2d40 100644 --- a/linux-user/host/sparc64/host-signal.h +++ b/linux-user/host/sparc64/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../sparc/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index b895b5c8bd..c7d083db92 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,67 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__sparc__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - int is_write; - uint32_t insn; -#if !defined(__arch64__) || defined(CONFIG_SOLARIS) - uint32_t *regs = (uint32_t *)(info + 1); - void *sigmask = (regs + 20); - /* XXX: is there a standard glibc define ? */ - unsigned long pc = regs[1]; -#else -#ifdef __linux__ - struct sigcontext *sc = puc; - unsigned long pc = sc->sigc_regs.tpc; - void *sigmask = (void *)sc->sigc_mask; -#elif defined(__OpenBSD__) - struct sigcontext *uc = puc; - unsigned long pc = uc->sc_pc; - void *sigmask = (void *)(long)uc->sc_mask; -#elif defined(__NetBSD__) - ucontext_t *uc = puc; - unsigned long pc = _UC_MACHINE_PC(uc); - void *sigmask = (void *)&uc->uc_sigmask; -#endif -#endif - - /* XXX: need kernel patch to get write flag faster */ - is_write = 0; - insn = *(uint32_t *)pc; - if ((insn >> 30) == 3) { - switch ((insn >> 19) & 0x3f) { - case 0x05: /* stb */ - case 0x15: /* stba */ - case 0x06: /* sth */ - case 0x16: /* stha */ - case 0x04: /* st */ - case 0x14: /* sta */ - case 0x07: /* std */ - case 0x17: /* stda */ - case 0x0e: /* stx */ - case 0x1e: /* stxa */ - case 0x24: /* stf */ - case 0x34: /* stfa */ - case 0x27: /* stdf */ - case 0x37: /* stdfa */ - case 0x26: /* stqf */ - case 0x36: /* stqfa */ - case 0x25: /* stfsr */ - case 0x3c: /* casa */ - case 0x3e: /* casxa */ - is_write = 1; - break; - } - } - return handle_cpu_signal(pc, info, is_write, sigmask); -} - -#elif defined(__arm__) +#if defined(__arm__) #if defined(__NetBSD__) #include From patchwork Fri Oct 1 17:11:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515061 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1003388jaf; Fri, 1 Oct 2021 10:20:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz0bk/8ltuG/q/9cEyyuy6EdFdzxz1CLRfLZHaMqboGIvVuftJqvaoh9Qsx1CnfvnZqfUVu X-Received: by 2002:a67:26c2:: with SMTP id m185mr5237883vsm.2.1633108856654; Fri, 01 Oct 2021 10:20:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633108856; cv=none; d=google.com; s=arc-20160816; b=PJXeYeZ0RFfVKiO+Tj1QsOU00Snrk7ivJRhMJ/8SOwPWKW8mVvG/t0tg1O6oKfIWVA gglsECf7vKufFSa+MZXKz3XN+npdeq0EWnmiYrdSAMjOfyPCeUiLiY+xKC5oE1Uw0XZ1 kboYCBIi2QzOy8HKlk75pP6Mo2ajAXVm1CIdP5pC/yC9AUnWNeQPhhHllfwI0XXf1ova nkc97kLd+VSTXUanY1AKvgffEqDoCOSgbP2keZ2s9MqPzqUM7wmZQ0NJz29Oc9iP/Rij Dr1sh61JIvXEazMe4ks2IC/89qqbaxjlhyf6ft//FTJ2GNf01bXD1vcOcaxOtFCgIEuY i7Vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=sCS25t/S/07LT/4q9hu7ybFQaqd9aKvTlaQnlQkDGSw=; b=XV1iIchgyb7+DYieIvLkr9QLq6VhlFy3gOFesFigcdGXwr4aOjXxLPe6Gp+svbP9xr 50oWQw/a/F2/wbEs12D9JnOcCsrrHBOFfmlIxdjAXYaYlpaGNVcv8whurEVZQ+4ABLiW WXmB3h7+g8dA6XSttj8F7YuAH4uy5nGZM4LX6+SxS8YYu8eFXijOZk/qVCh4V8VXQAEG WIjKFUmm25MuRM/upvjSU/qfTIF0NyBnflzY9WQOuk6HE0d1yDwBZPnUjgsWCWgs7Tl9 2jUi3t1FgoCeBkw4vfApW5TM/ogKjGIUGw1nCeC4/le6LTWVkmxnie4SlbuhwJUIjnhh s5RQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZDOIDG7Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 11/41] linux-user/host/arm: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:21 -0400 Message-Id: <20211001171151.1739472-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::836; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x836.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson --- linux-user/host/arm/host-signal.h | 30 ++++++++++++++++++++- accel/tcg/user-exec.c | 45 +------------------------------ 2 files changed, 30 insertions(+), 45 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-signal.h index f4b4d65031..6932224c1c 100644 --- a/linux-user/host/arm/host-signal.h +++ b/linux-user/host/arm/host-signal.h @@ -1 +1,29 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef ARM_HOST_SIGNAL_H +#define ARM_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.arm_pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + /* + * In the FSR, bit 11 is WnR, assuming a v6 or + * later processor. On v5 we will always report + * this as a read, which will fail later. + */ + uint32_t fsr = uc->uc_mcontext.error_code; + return extract32(fsr, 11, 1); +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index c7d083db92..e9c29f917d 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,50 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__arm__) - -#if defined(__NetBSD__) -#include -#include -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; -#if defined(__NetBSD__) - ucontext_t *uc = puc; - siginfo_t *si = pinfo; -#else - ucontext_t *uc = puc; -#endif - unsigned long pc; - uint32_t fsr; - int is_write; - -#if defined(__NetBSD__) - pc = uc->uc_mcontext.__gregs[_REG_R15]; -#elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) - pc = uc->uc_mcontext.gregs[R15]; -#else - pc = uc->uc_mcontext.arm_pc; -#endif - -#ifdef __NetBSD__ - fsr = si->si_trap; -#else - fsr = uc->uc_mcontext.error_code; -#endif - /* - * In the FSR, bit 11 is WnR, assuming a v6 or - * later processor. On v5 we will always report - * this as a read, which will fail later. - */ - is_write = extract32(fsr, 11, 1); - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__aarch64__) +#if defined(__aarch64__) #if defined(__NetBSD__) From patchwork Fri Oct 1 17:11:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515058 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1000363jaf; Fri, 1 Oct 2021 10:17:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyuqIS5dfs22SvZj8JymG6nmo7e/pC57tI0yq7vFTuwV9NUF1VOANqfZeTJQ9NbOgaeDk+O X-Received: by 2002:a05:600c:2201:: with SMTP id z1mr5805127wml.55.1633108648022; Fri, 01 Oct 2021 10:17:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633108648; cv=none; d=google.com; s=arc-20160816; b=bD+3NN/L3L4sOMhPIdO4M1zwBUzwIEQ9WeDH40McMp1vNXWU6najVba8F90+yRmw6K IC6Jzw9YQnYRjMlQadB2WcdhRsndYDtjEEZHsGKY2UuaZKzXTgexsyptdGimo5tAtBwr HFa1sxVqCTw1etpsVDn8348IHXebn6xAlYOrxN+65quhBbLvkU1sKVqSXkSiilIBypSt o55ivTh/qJw1gOgUELjtDaentzAiXJMkjswPqVRjub3rHLo9l4OIcpSwF2CiFWmnxi6o z6Qg1buauq1arBL3iEgGtf0MNwNYqs9hUsLWUQKbICeFIGGqgMhpImInFP2oj40+menS V/Rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xfI870gEd9IvWUORblCHYU3iuTigO27Yz4cJ6DbnRFo=; b=bwGWRbK0GUojm2xiOryrmwucxKCXdXq6DgTGrU1FwKkReM+Ci3cW7Y2FcWIU4F2htv 5C7OXQU51xY7KFx9TsuJ3d8okmKDFzDvmrP0juPdRArmM8nXqhiNGaUjWXzMn9iAv4tq Af4zpDjEyafqrmHgDSH5DMxhx2ebClRW2AfL2QVBfI9x49Rz/8VivIgcZBirq+P0g5xL UDxb1nKxOl5abKBJfyKqJdC29TZViOWUgrcMnNrnab218GyWdRewOSnkk7ezqZtdvuQS N5CebTl70rp4686Ldu/GjhCp3pjJ1evqJrBL9zJBnaHXyv3FWkYYxafa5edyMWom1PjY zWtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=T89kgklu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 12/41] linux-user/host/aarch64: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:22 -0400 Message-Id: <20211001171151.1739472-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82f; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 74 ++++++++++++++++++++- accel/tcg/user-exec.c | 94 +-------------------------- 2 files changed, 74 insertions(+), 94 deletions(-) -- 2.25.1 diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch64/host-signal.h index f4b4d65031..02a55c3372 100644 --- a/linux-user/host/aarch64/host-signal.h +++ b/linux-user/host/aarch64/host-signal.h @@ -1 +1,73 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef AARCH64_HOST_SIGNAL_H +#define AARCH64_HOST_SIGNAL_H + +/* Pre-3.16 kernel headers don't have these, so provide fallback definitions */ +#ifndef ESR_MAGIC +#define ESR_MAGIC 0x45535201 +struct esr_context { + struct _aarch64_ctx head; + uint64_t esr; +}; +#endif + +static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) +{ + return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; +} + +static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) +{ + return (struct _aarch64_ctx *)((char *)hdr + hdr->size); +} + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + struct _aarch64_ctx *hdr; + uint32_t insn; + + /* Find the esr_context, which has the WnR bit in it */ + for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) { + if (hdr->magic == ESR_MAGIC) { + struct esr_context const *ec = (struct esr_context const *)hdr; + uint64_t esr = ec->esr; + + /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ + return extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; + } + } + + /* + * Fall back to parsing instructions; will only be needed + * for really ancient (pre-3.16) kernels. + */ + insn = *(uint32_t *)host_signal_pc(uc); + + return (insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ + || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ + || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ + || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ + || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ + || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ + || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ + /* Ignore bits 10, 11 & 21, controlling indexing. */ + || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */ + || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */ + /* Ignore bits 23 & 24, controlling indexing. */ + || (insn & 0x3a400000) == 0x28000000; /* C3.3.7,14-16 */ +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e9c29f917d..8f4e788304 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,99 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__aarch64__) - -#if defined(__NetBSD__) - -#include -#include - -int cpu_signal_handler(int host_signum, void *pinfo, void *puc) -{ - ucontext_t *uc = puc; - siginfo_t *si = pinfo; - unsigned long pc; - int is_write; - uint32_t esr; - - pc = uc->uc_mcontext.__gregs[_REG_PC]; - esr = si->si_trap; - - /* - * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC - * is 0b10010x: then bit 6 is the WnR bit - */ - is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; - return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask); -} - -#else - -#ifndef ESR_MAGIC -/* Pre-3.16 kernel headers don't have these, so provide fallback definitions */ -#define ESR_MAGIC 0x45535201 -struct esr_context { - struct _aarch64_ctx head; - uint64_t esr; -}; -#endif - -static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) -{ - return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; -} - -static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) -{ - return (struct _aarch64_ctx *)((char *)hdr + hdr->size); -} - -int cpu_signal_handler(int host_signum, void *pinfo, void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - uintptr_t pc = uc->uc_mcontext.pc; - bool is_write; - struct _aarch64_ctx *hdr; - struct esr_context const *esrctx = NULL; - - /* Find the esr_context, which has the WnR bit in it */ - for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) { - if (hdr->magic == ESR_MAGIC) { - esrctx = (struct esr_context const *)hdr; - break; - } - } - - if (esrctx) { - /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ - uint64_t esr = esrctx->esr; - is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; - } else { - /* - * Fall back to parsing instructions; will only be needed - * for really ancient (pre-3.16) kernels. - */ - uint32_t insn = *(uint32_t *)pc; - - is_write = ((insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ - || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ - || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ - || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ - || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ - || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ - || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ - /* Ignore bits 10, 11 & 21, controlling indexing. */ - || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */ - || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */ - /* Ignore bits 23 & 24, controlling indexing. */ - || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */ - } - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#endif - -#elif defined(__s390__) +#if defined(__s390__) int cpu_signal_handler(int host_signum, void *pinfo, void *puc) From patchwork Fri Oct 1 17:11:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515078 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1014070jaf; Fri, 1 Oct 2021 10:34:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy/zupQz8naECl61fBW4Fd8MYUwjK2MFQB6y916PujfragyhoKxGEPrHWCidu0M8r0QZhUs X-Received: by 2002:adf:e102:: with SMTP id t2mr14028176wrz.430.1633109663024; Fri, 01 Oct 2021 10:34:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633109663; cv=none; d=google.com; s=arc-20160816; b=XVzWCbwBW5R4oEFFeaYIsxK4LME9hFtrGqPctpr2N48iH1QI0StrJ/RJrG1hgABUJN Cz4/wH5v6U4kYIpJ/4kT9MV/FKee92X6bDieaL4AbMzGN0vU3wUmy0FQOOisktCiErCq mz0EunyK9HESPWodHM8nTli8b4JTBryZHmc+sNNbNeQpmlVltkDxzH2+2g+k6FdPSRbi 0Tt7Szt2dE9pkIaxgq0vA9i9zd+/M4BbklHStHESP+d1pxcJg5s8wGn6gXXHj3235zBW cbZI1MAmOMfYFA83lMxFTU+rlCtWR8D+tqJDuIk5If5d/6dFEgowXMW/uovCNBQORNsb z6cA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FVBR6xN38KGZK6ffFbaN/UMF6D1nBrL7MvtjajehkgQ=; b=UH0yBQIfYtUb5WslaPYCmMU1C3NEZ2YiDJPkRv7UnJQf8V2qHanrfrEUV3dTk6UvxB hriGEOXYvc+seL6TbTGMJknlx8aDR8L2SOZI5S3OcWOr+EIBhrLHXahkrIMJWyCG4khc 3dRTt/AYkQYsdxqVI+lJNGmKmUdeDiqRmM/I2QX5k/SPQiaz52eKMezI21k5R2ZOx6Ig TimPchb99aeQ7AxBnP+71+6yNvpMbsy+7H3UGAXS5jk8jqIwKV6SPjt8RRM0NwqNF+tb thGode2ceBZNJhY4jplH0ye/uppjkgApInrdQ6pLHa6YJ6UKA/zFTXk/FTo64Ujgy5ME lZPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AZobUYr0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 13/41] linux-user/host/s390: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:23 -0400 Message-Id: <20211001171151.1739472-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82c; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/s390/host-signal.h | 93 ++++++++++++++++++++++++++++- linux-user/host/s390x/host-signal.h | 2 +- accel/tcg/user-exec.c | 88 +-------------------------- 3 files changed, 94 insertions(+), 89 deletions(-) -- 2.25.1 diff --git a/linux-user/host/s390/host-signal.h b/linux-user/host/s390/host-signal.h index f4b4d65031..21f59b612a 100644 --- a/linux-user/host/s390/host-signal.h +++ b/linux-user/host/s390/host-signal.h @@ -1 +1,92 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef S390_HOST_SIGNAL_H +#define S390_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.psw.addr; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint16_t *pinsn = (uint16_t *)host_signal_pc(uc); + + /* + * ??? On linux, the non-rt signal handler has 4 (!) arguments instead + * of the normal 2 arguments. The 4th argument contains the "Translation- + * Exception Identification for DAT Exceptions" from the hardware (aka + * "int_parm_long"), which does in fact contain the is_write value. + * The rt signal handler, as far as I can tell, does not give this value + * at all. Not that we could get to it from here even if it were. + * So fall back to parsing instructions. Treat read-modify-write ones as + * writes, which is not fully correct, but for tracking self-modifying code + * this is better than treating them as reads. Checking si_addr page flags + * might be a viable improvement, albeit a racy one. + */ + /* ??? This is not even close to complete. */ + switch (pinsn[0] >> 8) { + case 0x50: /* ST */ + case 0x42: /* STC */ + case 0x40: /* STH */ + case 0xba: /* CS */ + case 0xbb: /* CDS */ + return true; + case 0xc4: /* RIL format insns */ + switch (pinsn[0] & 0xf) { + case 0xf: /* STRL */ + case 0xb: /* STGRL */ + case 0x7: /* STHRL */ + return true; + } + break; + case 0xc8: /* SSF format insns */ + switch (pinsn[0] & 0xf) { + case 0x2: /* CSST */ + return true; + } + break; + case 0xe3: /* RXY format insns */ + switch (pinsn[2] & 0xff) { + case 0x50: /* STY */ + case 0x24: /* STG */ + case 0x72: /* STCY */ + case 0x70: /* STHY */ + case 0x8e: /* STPQ */ + case 0x3f: /* STRVH */ + case 0x3e: /* STRV */ + case 0x2f: /* STRVG */ + return true; + } + break; + case 0xeb: /* RSY format insns */ + switch (pinsn[2] & 0xff) { + case 0x14: /* CSY */ + case 0x30: /* CSG */ + case 0x31: /* CDSY */ + case 0x3e: /* CDSG */ + case 0xe4: /* LANG */ + case 0xe6: /* LAOG */ + case 0xe7: /* LAXG */ + case 0xe8: /* LAAG */ + case 0xea: /* LAALG */ + case 0xf4: /* LAN */ + case 0xf6: /* LAO */ + case 0xf7: /* LAX */ + case 0xfa: /* LAAL */ + case 0xf8: /* LAA */ + return true; + } + break; + } + return false; +} + +#endif diff --git a/linux-user/host/s390x/host-signal.h b/linux-user/host/s390x/host-signal.h index f4b4d65031..0e83f9358d 100644 --- a/linux-user/host/s390x/host-signal.h +++ b/linux-user/host/s390x/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../s390/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 8f4e788304..0810b71ba0 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,93 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__s390__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - unsigned long pc; - uint16_t *pinsn; - int is_write = 0; - - pc = uc->uc_mcontext.psw.addr; - - /* - * ??? On linux, the non-rt signal handler has 4 (!) arguments instead - * of the normal 2 arguments. The 4th argument contains the "Translation- - * Exception Identification for DAT Exceptions" from the hardware (aka - * "int_parm_long"), which does in fact contain the is_write value. - * The rt signal handler, as far as I can tell, does not give this value - * at all. Not that we could get to it from here even if it were. - * So fall back to parsing instructions. Treat read-modify-write ones as - * writes, which is not fully correct, but for tracking self-modifying code - * this is better than treating them as reads. Checking si_addr page flags - * might be a viable improvement, albeit a racy one. - */ - /* ??? This is not even close to complete. */ - pinsn = (uint16_t *)pc; - switch (pinsn[0] >> 8) { - case 0x50: /* ST */ - case 0x42: /* STC */ - case 0x40: /* STH */ - case 0xba: /* CS */ - case 0xbb: /* CDS */ - is_write = 1; - break; - case 0xc4: /* RIL format insns */ - switch (pinsn[0] & 0xf) { - case 0xf: /* STRL */ - case 0xb: /* STGRL */ - case 0x7: /* STHRL */ - is_write = 1; - } - break; - case 0xc8: /* SSF format insns */ - switch (pinsn[0] & 0xf) { - case 0x2: /* CSST */ - is_write = 1; - } - break; - case 0xe3: /* RXY format insns */ - switch (pinsn[2] & 0xff) { - case 0x50: /* STY */ - case 0x24: /* STG */ - case 0x72: /* STCY */ - case 0x70: /* STHY */ - case 0x8e: /* STPQ */ - case 0x3f: /* STRVH */ - case 0x3e: /* STRV */ - case 0x2f: /* STRVG */ - is_write = 1; - } - break; - case 0xeb: /* RSY format insns */ - switch (pinsn[2] & 0xff) { - case 0x14: /* CSY */ - case 0x30: /* CSG */ - case 0x31: /* CDSY */ - case 0x3e: /* CDSG */ - case 0xe4: /* LANG */ - case 0xe6: /* LAOG */ - case 0xe7: /* LAXG */ - case 0xe8: /* LAAG */ - case 0xea: /* LAALG */ - case 0xf4: /* LAN */ - case 0xf6: /* LAO */ - case 0xf7: /* LAX */ - case 0xfa: /* LAAL */ - case 0xf8: /* LAA */ - is_write = 1; - } - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__mips__) +#if defined(__mips__) #if defined(__misp16) || defined(__mips_micromips) #error "Unsupported encoding" From patchwork Fri Oct 1 17:11:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515090 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1021158jaf; Fri, 1 Oct 2021 10:43:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxmttul/jwhnsqGBICEnQDApiGZnRtH1rBxjyHjj8jzzIw8Rq7Y75paIh1U/QA3SAqm4Ko+ X-Received: by 2002:a37:2f46:: with SMTP id v67mr10778979qkh.474.1633110218667; Fri, 01 Oct 2021 10:43:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633110218; cv=none; d=google.com; s=arc-20160816; b=MBEtXo7/MlyciiuLi3P78isPC4aldjz2hDtBladXM05CU4+3q1zb6mQOHRjjrsyezL So+Z5VVXpSzKgElhhnDDHXxolyHmLDacs9QdeatpMisDjChwA/MgDF9ShdCZjVCp0CZe YnRvojBMsz8R/NKXprpsUn1+mH0bj9sDuguTtC/O936+ovCd5tatI5Nfp6pT21zHgXR2 EVPJKictk5FqFI+r3VL05cI/rnwbTRpM7p656bMFvbdpgZzCgSs/znV9Mg2c0ZzOQpOi dYGR1pQ4RR6Y1zNN+bD3ljLP6W2ZsZDzYIxjbsHXAjtXjIQDGI9oj9GuV10U2r8wawkE QS0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=TsF7+ye4ZFBKtVDH6YOEuxIjbYiQw3V/Xwn+HbNdAZw=; b=L71KZtFLu83dnWphXQK34Doq1hLZ6dspXky5FeGR/LeeA5/1VlxbA13CfMV3uUYJe0 5XSEdYoaUA8FfSc47ffi+1Ro7SGVm/kS8ras0E1Pk+lu6y+1kr+sS+xtFT0Z+TCVDLVt T8ZzgoEg/NpZZREMyuHpu2TYwkLG/jWqsjLt/6obnlFwrccsd6dxdSX6ZFhD6j2BJpi/ mjiY1/KwSIq7EdRHyUtmIFysT3tviDWWUXE/oQc+2E1vL9ER9HvXpzO/AnBa7nS9v+wq fRW7raltdQNYH52WxgOVtlKINI75apkIGHlHgEoZZOhrS9ZV7E+w6jBXJTUSUrx7yQGH 3Kaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=xcfH53GO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 14/41] linux-user/host/mips: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:24 -0400 Message-Id: <20211001171151.1739472-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2e; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/mips/host-signal.h | 62 +++++++++++++++++++++++++++++- accel/tcg/user-exec.c | 52 +------------------------ 2 files changed, 62 insertions(+), 52 deletions(-) -- 2.25.1 diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host-signal.h index f4b4d65031..9c83e51130 100644 --- a/linux-user/host/mips/host-signal.h +++ b/linux-user/host/mips/host-signal.h @@ -1 +1,61 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef MIPS_HOST_SIGNAL_H +#define MIPS_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.pc; +} + +#if defined(__misp16) || defined(__mips_micromips) +#error "Unsupported encoding" +#endif + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn = *(uint32_t *)host_signal_pc(uc); + + /* Detect all store instructions at program counter. */ + switch ((insn >> 26) & 077) { + case 050: /* SB */ + case 051: /* SH */ + case 052: /* SWL */ + case 053: /* SW */ + case 054: /* SDL */ + case 055: /* SDR */ + case 056: /* SWR */ + case 070: /* SC */ + case 071: /* SWC1 */ + case 074: /* SCD */ + case 075: /* SDC1 */ + case 077: /* SD */ +#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 + case 072: /* SWC2 */ + case 076: /* SDC2 */ +#endif + return true; + case 023: /* COP1X */ + /* + * Required in all versions of MIPS64 since + * MIPS64r1 and subsequent versions of MIPS32r2. + */ + switch (insn & 077) { + case 010: /* SWXC1 */ + case 011: /* SDXC1 */ + case 015: /* SUXC1 */ + return true; + } + break; + } + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0810b71ba0..42d1ad189b 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,57 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__mips__) - -#if defined(__misp16) || defined(__mips_micromips) -#error "Unsupported encoding" -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - uintptr_t pc = uc->uc_mcontext.pc; - uint32_t insn = *(uint32_t *)pc; - int is_write = 0; - - /* Detect all store instructions at program counter. */ - switch((insn >> 26) & 077) { - case 050: /* SB */ - case 051: /* SH */ - case 052: /* SWL */ - case 053: /* SW */ - case 054: /* SDL */ - case 055: /* SDR */ - case 056: /* SWR */ - case 070: /* SC */ - case 071: /* SWC1 */ - case 074: /* SCD */ - case 075: /* SDC1 */ - case 077: /* SD */ -#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 - case 072: /* SWC2 */ - case 076: /* SDC2 */ -#endif - is_write = 1; - break; - case 023: /* COP1X */ - /* Required in all versions of MIPS64 since - MIPS64r1 and subsequent versions of MIPS32r2. */ - switch (insn & 077) { - case 010: /* SWXC1 */ - case 011: /* SDXC1 */ - case 015: /* SUXC1 */ - is_write = 1; - } - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__riscv) +#if defined(__riscv) int cpu_signal_handler(int host_signum, void *pinfo, void *puc) From patchwork Fri Oct 1 17:11:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515065 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1005508jaf; Fri, 1 Oct 2021 10:23:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwFTARdG1ZP+qEsjohBvFUldm+/b3MgBkSQYO2SV+fjskCPqfbnKPVtROya4ooxfDj4cg+0 X-Received: by 2002:ab0:5fc2:: with SMTP id g2mr2858013uaj.132.1633109023449; Fri, 01 Oct 2021 10:23:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633109023; cv=none; d=google.com; s=arc-20160816; b=G9eoOdTh8ciFEGIU3qLuG9TXLCK4ClOsq8movMliXsW72llRA4y1jw0X7pLfPoMvNi 4Bg4hs1f3NaX8b1FboPZrwTLI7a0EcdPPSxHz9pp1tOpR0feB39of4I/2HOH1QDcl1CK SpCwFx42vV82kKqBIHr4I6bPfLKHENiUdXlLWxe45wgwI3szHKgsU1S5qCXpUM6m5sf6 1fVa5/hp2Sr/oaBJOgbcBPqa29q+6CZtSpGFFFBTMKsgLq7dqfXF+8uWJo57bi+HBSg+ GRIAtdlJTiod0VzZKYzwoWLAC4CFwCLwldNOeDrYPv8VHeGwqz2cGD7iei485CYMK2Tc D78g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=b88MeJ0VB21CqXeC9kfaVd7KTqjTS4pXJD2Bd6nXvIA=; b=JExwFIESDgJdmwHm/nqQkUcXSFB7MvhA7IgDehJgmrE4AYJV7PeTgNMEUg5S+2N1k+ nTWdbkPPU/ht6a/Dv6Gi3yIUhFGzLZWyClLk4Pf/owSAOfvtkcacjHzbgw+9ybxJp9Vu FTo1x6hvX7edGEHIJIBlnjbnli+/twmqBt5/hLf7blsBeHjH7Cw1YiZAZ2Ly6N4eSMXI kZO9rMctazovyXaEOwiWQNFW4rpbPTRmEIWtyuPxQ2OsTb6H4RW7nTLz/iol7kCueaS3 eJ1iPDihqsPtA9NPe6DsErT2KR/ZnaI5z4WtvTCGo26OIF/MzCi7Wl8AB8lBxLM9UU7M CdrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eUZtB5RD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 15/41] linux-user/host/riscv: Populate host_signal.h Date: Fri, 1 Oct 2021 13:11:25 -0400 Message-Id: <20211001171151.1739472-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::730; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x730.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 85 +++++++++++++++++- accel/tcg/user-exec.c | 134 ---------------------------- 2 files changed, 84 insertions(+), 135 deletions(-) -- 2.25.1 diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/host-signal.h index f4b4d65031..5860dce7d7 100644 --- a/linux-user/host/riscv/host-signal.h +++ b/linux-user/host/riscv/host-signal.h @@ -1 +1,84 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef RISCV_HOST_SIGNAL_H +#define RISCV_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.__gregs[REG_PC]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn = *(uint32_t *)host_signal_pc(uc); + + /* + * Detect store by reading the instruction at the program + * counter. Note: we currently only generate 32-bit + * instructions so we thus only detect 32-bit stores + */ + switch (((insn >> 0) & 0b11)) { + case 3: + switch (((insn >> 2) & 0b11111)) { + case 8: + switch (((insn >> 12) & 0b111)) { + case 0: /* sb */ + case 1: /* sh */ + case 2: /* sw */ + case 3: /* sd */ + case 4: /* sq */ + return true; + default: + break; + } + break; + case 9: + switch (((insn >> 12) & 0b111)) { + case 2: /* fsw */ + case 3: /* fsd */ + case 4: /* fsq */ + return true; + default: + break; + } + break; + default: + break; + } + } + + /* Check for compressed instructions */ + switch (((insn >> 13) & 0b111)) { + case 7: + switch (insn & 0b11) { + case 0: /*c.sd */ + case 2: /* c.sdsp */ + return true; + default: + break; + } + break; + case 6: + switch (insn & 0b11) { + case 0: /* c.sw */ + case 3: /* c.swsp */ + return true; + default: + break; + } + break; + default: + break; + } + + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 42d1ad189b..01e7e69e7f 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -139,64 +139,6 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, } } -/* - * 'pc' is the host PC at which the exception was raised. - * 'address' is the effective address of the memory exception. - * 'is_write' is 1 if a write caused the exception and otherwise 0. - * 'old_set' is the signal set which should be restored. - */ -static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, - int is_write, sigset_t *old_set) -{ - CPUState *cpu = current_cpu; - CPUClass *cc; - unsigned long host_addr = (unsigned long)info->si_addr; - MMUAccessType access_type = adjust_signal_pc(&pc, is_write); - abi_ptr guest_addr; - - /* For synchronous signals we expect to be coming from the vCPU - * thread (so current_cpu should be valid) and either from running - * code or during translation which can fault as we cross pages. - * - * If neither is true then something has gone wrong and we should - * abort rather than try and restart the vCPU execution. - */ - if (!cpu || !cpu->running) { - printf("qemu:%s received signal outside vCPU context @ pc=0x%" - PRIxPTR "\n", __func__, pc); - abort(); - } - -#if defined(DEBUG_SIGNAL) - printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", - pc, host_addr, is_write, *(unsigned long *)old_set); -#endif - - /* Convert forcefully to guest address space, invalid addresses - are still valid segv ones */ - guest_addr = h2g_nocheck(host_addr); - - /* XXX: locking issue */ - if (is_write && - info->si_signo == SIGSEGV && - info->si_code == SEGV_ACCERR && - h2g_valid(host_addr) && - handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) { - return 1; - } - - /* - * There is no way the target can handle this other than raising - * an exception. Undo signal and retaddr state prior to longjmp. - */ - sigprocmask(SIG_SETMASK, old_set, NULL); - - cc = CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, - MMU_USER_IDX, false, pc); - g_assert_not_reached(); -} - static int probe_access_internal(CPUArchState *env, target_ulong addr, int fault_size, MMUAccessType access_type, bool nonfault, uintptr_t ra) @@ -255,82 +197,6 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__riscv) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - greg_t pc = uc->uc_mcontext.__gregs[REG_PC]; - uint32_t insn = *(uint32_t *)pc; - int is_write = 0; - - /* Detect store by reading the instruction at the program - counter. Note: we currently only generate 32-bit - instructions so we thus only detect 32-bit stores */ - switch (((insn >> 0) & 0b11)) { - case 3: - switch (((insn >> 2) & 0b11111)) { - case 8: - switch (((insn >> 12) & 0b111)) { - case 0: /* sb */ - case 1: /* sh */ - case 2: /* sw */ - case 3: /* sd */ - case 4: /* sq */ - is_write = 1; - break; - default: - break; - } - break; - case 9: - switch (((insn >> 12) & 0b111)) { - case 2: /* fsw */ - case 3: /* fsd */ - case 4: /* fsq */ - is_write = 1; - break; - default: - break; - } - break; - default: - break; - } - } - - /* Check for compressed instructions */ - switch (((insn >> 13) & 0b111)) { - case 7: - switch (insn & 0b11) { - case 0: /*c.sd */ - case 2: /* c.sdsp */ - is_write = 1; - break; - default: - break; - } - break; - case 6: - switch (insn & 0b11) { - case 0: /* c.sw */ - case 3: /* c.swsp */ - is_write = 1; - break; - default: - break; - } - break; - default: - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#endif - /* The softmmu versions of these helpers are in cputlb.c. */ uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) From patchwork Fri Oct 1 17:11:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515081 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1016345jaf; Fri, 1 Oct 2021 10:37:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwHG+bYKSc/dbTLmaDhe0w96ho0mBVi3D8eZvHOMMdDXL0eubKgG9ldiYuVyYFnTgKpXI/a X-Received: by 2002:a67:d488:: with SMTP id g8mr4954280vsj.60.1633109830200; Fri, 01 Oct 2021 10:37:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633109830; cv=none; d=google.com; s=arc-20160816; b=l7D9uFnZDrT8SeL1U3FLV9MyBp0yQkWvJEZvlgk1l1K16Cvv0bAUqJL3hIJb0Y0TyZ CHJPSR6BJpE6MUWxKeKI67Vys9apKDwC8VvVeVmgT4T7zm4iguVPx742XvGOR0rSzo7T ZA95xQtfEJV8srZaJmBlf1G63z8aXRH6621ZwFzKb16pz78ibXk8Z+RL2BWZdalEvJIa rXQ8b3O+gdygR0aYNS7yxg9WUzLgOPXMsScs6/gCVEGKhbZZCAnmhp19zfSROG5SV3xm J4X/Z+g+zaA5//nbCEYbMjZSB1oO2lsouN7ByClQAQdUJ7LeBACeyg+NdsfCTtqQeoI6 vDOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+vyWXP6Fx9Nim2ldoxF0eSsJbEhC7OEjuYcEJUYRKoA=; b=rwfnUy/DNk4VeUhS27/hl9jbPf3GpR/3movUEJJ2pQFrJTHdV8kGBJw++xk17ZYTwJ y/hjLXMDm4hkIiCyH0i5/2TNBYj1ocMhaZpd2Mhr+UiAVVICtUy/3+ldEY3LGFLsstEH VNOMqHOesvwG+25UsU/f5cgCiAGp5VKA5TvekXKCG/+UHW91Lx9GRI87pdz80IReG4F4 Iyx1SoEZcbIwgH09/IxqOmfw2cll3icJthjcho4KVJ0eH9b1aXA7Mq47ocyHpGnyT9eN hz18WQlEB+2TOMXp5Q4kq5wjdQD+RJD+0TGTISKruBJxDtbxFoMRaeKUxwdGX9UheDkv SSqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="U//2ifMm"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 16/41] target/arm: Fixup comment re handle_cpu_signal Date: Fri, 1 Oct 2021 13:11:26 -0400 Message-Id: <20211001171151.1739472-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::733; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x733.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The named function no longer exists. Refer to host_signal_handler instead. Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index dab5f1d1cd..07be55b7e1 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -6118,7 +6118,7 @@ DO_LDN_2(4, dd, MO_64) * linux-user/ in its get_user/put_user macros. * * TODO: Construct some helpers, written in assembly, that interact with - * handle_cpu_signal to produce memory ops which can properly report errors + * host_signal_handler to produce memory ops which can properly report errors * without racing. */ From patchwork Fri Oct 1 17:11:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515072 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1011139jaf; Fri, 1 Oct 2021 10:30:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyn3WonAWFPvoXQ+EOp/AKdF9mdZtEsZhZuV8jRmUWYhLNIozv1J/I+ctn6x/Q1NU4wQo9W X-Received: by 2002:a05:6102:4b0:: with SMTP id r16mr5151897vsa.7.1633109456504; Fri, 01 Oct 2021 10:30:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633109456; cv=none; d=google.com; s=arc-20160816; b=JDAbhDkXB1CFpa/ED8rNZ9iRJqXtLyApL+YNkaK6PYFyQjPqSvNaYElZAv6J9BAvuu D1MMz6cjIehk1S9KSz7SUFTfUpp7Y26876wKvG6nDykCjpKXvs0VKyEnTmsgoIdQSgED qAXHOjTtat/2bl69aHSV8iKfKg40kQWb+k2d8fruiNTike17nf5UPM4A5NMQmx9I9vTH 6mSk0MCUSi0kMVEoKJDSW3ROiQ4QCdKV59Sgc5nRxgz+cD5+uJ783a13yG3BTRhzUVht TvZGYURA4bK2iOn2KN3TUnrxSC4Xv3b3CZsgIpjdez3mLT9kNxF1k1Zv3fHFpeE0OYuV itYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nMBhe6wRyQJffJfKqR3e4B4BjhzuFHvBY7lYZ6XbL2k=; b=mYxjKmNMvJzuoAtFNE1+AZOpy+t8lz/jIpFmaIvz97+iLC7+h0PABUtXczE+Z398jI 2Xa2usR/EQucsehPJgMEimJylsI8gXgKRIYNsALM5N9IA85KvMVNs2q8TgkOY7+0/qbw 24cmb5KdAH8C7e3sKH2qncNayTjVwStjbEMj/oY6fTc++8DPKbVSkq/OfX4TPtkXzN1N CM6gAMQmwRftjq2r+hom7cFaID1q7OHh16Am8QQa6dp8aEj2RM5Z7SeIPVzL7h1EdTeg JyWwXZiJpbPylPRBVeHrvR5z40O5vPxrVzhhZB/VAGQLlTaXDLh9vQM7vnQc3iD+viUD rZew== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hiXQ3mmw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 17/41] linux-user/host/riscv: Improve host_signal_write Date: Fri, 1 Oct 2021 13:11:27 -0400 Message-Id: <20211001171151.1739472-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::736; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x736.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not read 4 bytes before we determine the size of the insn. Simplify triple switches in favor of checking major opcodes. Include the missing cases of compact fsd and fsdsp. Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 83 ++++++++++------------------- 1 file changed, 28 insertions(+), 55 deletions(-) -- 2.25.1 diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/host-signal.h index 5860dce7d7..ab06d70964 100644 --- a/linux-user/host/riscv/host-signal.h +++ b/linux-user/host/riscv/host-signal.h @@ -17,65 +17,38 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) { - uint32_t insn = *(uint32_t *)host_signal_pc(uc); - /* - * Detect store by reading the instruction at the program - * counter. Note: we currently only generate 32-bit - * instructions so we thus only detect 32-bit stores + * Detect store by reading the instruction at the program counter. + * Do not read more than 16 bits, because we have not yet determined + * the size of the instruction. */ - switch (((insn >> 0) & 0b11)) { - case 3: - switch (((insn >> 2) & 0b11111)) { - case 8: - switch (((insn >> 12) & 0b111)) { - case 0: /* sb */ - case 1: /* sh */ - case 2: /* sw */ - case 3: /* sd */ - case 4: /* sq */ - return true; - default: - break; - } - break; - case 9: - switch (((insn >> 12) & 0b111)) { - case 2: /* fsw */ - case 3: /* fsd */ - case 4: /* fsq */ - return true; - default: - break; - } - break; - default: - break; - } + const uint16_t *pinsn = (const uint16_t *)host_signal_pc(uc); + uint16_t insn = pinsn[0]; + + /* 16-bit instructions */ + switch (insn & 0xe003) { + case 0xa000: /* c.fsd */ + case 0xc000: /* c.sw */ + case 0xe000: /* c.sd (rv64) / c.fsw (rv32) */ + case 0xa002: /* c.fsdsp */ + case 0xc002: /* c.swsp */ + case 0xe002: /* c.sdsp (rv64) / c.fswsp (rv32) */ + return true; } - /* Check for compressed instructions */ - switch (((insn >> 13) & 0b111)) { - case 7: - switch (insn & 0b11) { - case 0: /*c.sd */ - case 2: /* c.sdsp */ - return true; - default: - break; - } - break; - case 6: - switch (insn & 0b11) { - case 0: /* c.sw */ - case 3: /* c.swsp */ - return true; - default: - break; - } - break; - default: - break; + /* 32-bit instructions, major opcodes */ + switch (insn & 0x7f) { + case 0x23: /* store */ + case 0x27: /* store-fp */ + return true; + case 0x2f: /* amo */ + /* + * The AMO function code is in bits 25-31, unread as yet. + * The AMO functions are LR (read), SC (write), and the + * rest are all read-modify-write. + */ + insn = pinsn[1]; + return (insn >> 11) != 2; /* LR */ } return false; From patchwork Fri Oct 1 17:11:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515068 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1008238jaf; Fri, 1 Oct 2021 10:27:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw91OVU+vmEqI8+qS7xFpLGvOq2Zh1i24I2qwlJKo69yMWJOuPKNUKnwRCGMnbynZSymbTq X-Received: by 2002:a9f:234a:: with SMTP id 68mr11531421uae.13.1633109236477; Fri, 01 Oct 2021 10:27:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633109236; cv=none; d=google.com; s=arc-20160816; b=j+6SjwBcyxddMGL8b7LzIf0CZhqdiDPw7Zv3hPGfIyQvHGLvCdcnJ47nDdvzOsSL0H K01IpRUQN9MiMILDaalhZmt19DeYvrfrDUfCJ3LUf5RIIMssL7kOHGFxCbSeQFjS03/v Bq694jRY2cJXLEKA2bCYZyDamS/SsMXeLGe0Yzmc6Okgf5OYnxZuQ78FzOCI3kp/W4nu rLsn25BWxjBBRPNHCjajX7jhfAbB/GFeAI2M0gH3mJc7eHMGqla4wCtZZcgtS8wEYEFh 0ZcPMFwo9gkiheyELdMf/9Q6qPBn0qLMsWXy3iIN+lUKzh4k0aLh55fE4/+nitBMg+KG 0bqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=plpjMgZs0Fmj1no4dWQvatctpg292W263ogwu9LIdH8=; b=bgABpHl180EbPVuC3cFSUtI6Wxl7WeoZLWTcWtZ69sYhc6kblc/kKMflGsYl66+bf2 DST1Ti6BiaJAONnzDIBkO9WEpt0e+VqpXyXdLS+HKzBwTd/vA3trkFFVcWzzbJgIWtsF 5QqO+e8hgT2zlf3Mgu909aXjyKiJBhziP2bWr3G9z23re6PjynUf3/3f8zqe8BkpBFfg X2wjJL1YnJ+XM5VdiMxQmXEB77Lpexk6LKGJ5tP7bDveyRzNrJUX/6MVhrB9kiioDxK7 PtJwordwfvSMPi08hifPW9f31PjD1VnBwRlnAAPiRyXp/uz4wVavD24Ok2gecEWpEYF2 h4cg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=otGns6K9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 18/41] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Date: Fri, 1 Oct 2021 13:11:28 -0400 Message-Id: <20211001171151.1739472-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72e; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that all of the linux-user hosts have been converted to host-signal.h, drop the compatibility code. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 12 ------------ linux-user/signal.c | 14 -------------- 2 files changed, 26 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5f94d799aa..5dd663c153 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -685,18 +685,6 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, uintptr_t host_pc, abi_ptr guest_addr); -/** - * cpu_signal_handler - * @signum: host signal number - * @pinfo: host siginfo_t - * @puc: host ucontext_t - * - * To be called from the SIGBUS and SIGSEGV signal handler to inform the - * virtual cpu of exceptions. Returns true if the signal was handled by - * the virtual CPU. - */ -int cpu_signal_handler(int signum, void *pinfo, void *puc); - #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/linux-user/signal.c b/linux-user/signal.c index bab47a6962..537c6c41c0 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -777,17 +777,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) ucontext_t *uc = puc; struct emulated_sigtable *k; int guest_sig; - -#ifdef HOST_SIGNAL_PLACEHOLDER - /* the CPU emulator uses some host signals to detect exceptions, - we forward to it some signals */ - if ((host_sig == SIGSEGV || host_sig == SIGBUS) - && info->si_code > 0) { - if (cpu_signal_handler(host_sig, info, puc)) { - return; - } - } -#else uintptr_t pc = 0; bool sync_sig = false; @@ -847,7 +836,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) sync_sig = true; } -#endif /* get target signal number */ guest_sig = host_to_target_signal(host_sig); @@ -862,7 +850,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) k->pending = guest_sig; ts->signal_pending = 1; -#ifndef HOST_SIGNAL_PLACEHOLDER /* * For synchronous signals, unwind the cpu state to the faulting * insn and then exit back to the main loop so that the signal @@ -872,7 +859,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) cpu->exception_index = EXCP_INTERRUPT; cpu_loop_exit_restore(cpu, pc); } -#endif rewind_if_in_safe_syscall(puc); From patchwork Fri Oct 1 17:11:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515067 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1006947jaf; Fri, 1 Oct 2021 10:25:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzdaEKG3cYsF1qJIu5NHADyfp9OIMMnfno4zTFvAW5dqF7O5frOn4YfKXUK27cVJHFQQ8az X-Received: by 2002:a67:d912:: with SMTP id t18mr5470083vsj.12.1633109139623; Fri, 01 Oct 2021 10:25:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633109139; cv=none; d=google.com; s=arc-20160816; b=UqOJ2gq3d3vMAYtsIMSqrolAY3DxpjRjy4+/n9X5AXkXJG64PmchmXN0ltEQUSwZ3S Uo4PJtyNa1gZWXgzCt0t6rvzJAhK7qM6m3yTboePcy+HdmNFSK+dnHi33vTCoEny295A +MS+JEb1xJ91/e85slX20Xlw8kDy19UKshXpSDRKyxfdVEFhSSl/fYf2v3fLCR8Iu5L3 YKSQnQnEyfsDan1Hi/yO10KXxoAjxT4QESralhCZTpYJhupkpw95vAV/HdpiAUjJIBpq Wsh6gHGhOaHYWBzv1blcIkNeIdRxc53We5tGVnEG3eqCOdOHU4qzG3UGfO9zfDnFHY2Q H22g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=p8GaNWW3vnRejpH0QBiQY2hh87QfB4bhIFphc+bCE2U=; b=Yjw8jus42cYIpekjKPRJk8yDKpakJnm0NbwjeV+9ObzUvNLvV+Trcujx1t8eDsZRag hmdVHHxYvIs5yw34UVeGmOyh91LnyuFQ26V6BwkTUsqAxJRWcL5cbQioONeeJ48LjRFF dMc/omlTrGPNCjnULKJpyZkebRnxd4q9aZSwasJyIZPJaXIxmnZRwd4TcB4QtG2ja/S0 rlj1t9QJDqYOewU0AtIW0uwqPfiQ6Utg3iiCEdRqRgrn+HjZDD9RExe9mPEjDommaX+n w5hGuBF1u0k5LrUFNSnaGzUvPjLCE+wA48rzaCcc48JLa2tTIuh+40+hYSiWI6bZbBpq TbkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ox9tk89i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 19/41] hw/core: Add TCGCPUOps.record_sigsegv Date: Fri, 1 Oct 2021 13:11:29 -0400 Message-Id: <20211001171151.1739472-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72a; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a new user-only interface for updating cpu state before raising a signal. This will replace tlb_fill for user-only and should result in less boilerplate for each guest. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.25.1 diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 6cbe17f2e6..41718b695b 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -111,6 +111,32 @@ struct TCGCPUOps { */ bool (*io_recompile_replay_branch)(CPUState *cpu, const TranslationBlock *tb); +#else + /** + * record_sigsegv: + * @cpu: cpu context + * @addr: faulting guest address + * @access_type: access was read/write/execute + * @maperr: true for invalid page, false for permission fault + * @ra: host pc for unwinding + * + * We are about to raise SIGSEGV with si_code set for @maperr, + * and si_addr set for @addr. Record anything further needed + * for the signal ucontext_t. + * + * If the emulated kernel does not provide anything to the signal + * handler with anything besides the user context registers, and + * the siginfo_t, then this hook need do nothing and may be omitted. + * Otherwise, record the data and return; the caller will raise + * the signal, unwind the cpu state, and return to the main loop. + * + * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided + * so that a "normal" cpu exception can be raised. In this case, + * the signal must be raised by the architecture cpu_loop. + */ + void (*record_sigsegv)(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); #endif /* CONFIG_SOFTMMU */ #endif /* NEED_CPU_H */ From patchwork Fri Oct 1 17:11:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515092 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1023901jaf; Fri, 1 Oct 2021 10:47:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzBXPOU2CWBA0mBXA+2Cu2zUz5taU14SCwFLR3WkBixZjhf8PAqxC2YHK69Mvt8NXBbfpGK X-Received: by 2002:a05:6102:528:: with SMTP id m8mr5338243vsa.43.1633110447326; Fri, 01 Oct 2021 10:47:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633110447; cv=none; d=google.com; s=arc-20160816; b=degVuuODqI4PwZ0E6As4XS1t9ivI1HyemPS8YjQ1OIoliuzRTCYX++F8RmlWhcunkA J66DnYu0dOmA/Ox7V+FwmC4LEhlDN8LQi4mwbacNUE41FBTc1TssotXUIOvmTQfaUmAj 89EnC03qHGjiVtLfAFi0C/OPIYAn/tUZnJFVoZPNl5mq9lg2WfhaDnIfSyHW5zZ0LETq MBlACYh3EVahEhWO77M5cmN+4tdLZm7IiSx0QrvMItePWac6AC6w2yyNWjRJPzsy3GkZ xN2mqgTu+NiUVhHJVarrgJu5OkuRNSjRsAPHPTk5zH+kIxk6q8sbXlnoVJa0ZBMYsT3V gkhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FDhkJIE1evS1cLhaEMVaF6n1Obdz81Be/9kGft2ow5k=; b=z6Ff+xA/pl9oCOUlK7PuuubKZgOyJbDzoQYrLad3gEBtSYATh8lE56zt/NeYeRB3Up 0NbSFq7ok/XLg+dTpDKprx7cJnNteYGhmKUvkz3DbrOJFrW5qAtIznrWx83JctyXvyTA HZ7oVVgtEn0kvvu5WB3yIHGvI9N4TbN1jbJElHTktvJO2HwQAVBSygciuX4sZmSCV5mm BzMEtM4fkI9Z0jVnlMQIszlETC7VL8jotpReOSDIBzpRkNMeSLq3Y1k5xHq1nB3831kG fZ73iAWTlx/AsEKrtoeaKTIs+JCoBGD7GoVJz6JtO9lbvHo5MysYkjWDh1ZOsjOJi9q3 1gEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IxmO67Fn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 20/41] linux-user: Add cpu_loop_exit_segv Date: Fri, 1 Oct 2021 13:11:30 -0400 Message-Id: <20211001171151.1739472-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2c; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a new interface to be provided by the os emulator for raising SIGSEGV on fault. Use the new record_sigsegv target hook. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 15 +++++++++++++++ accel/tcg/user-exec.c | 33 ++++++++++++++++++--------------- linux-user/signal.c | 30 ++++++++++++++++++++++-------- 3 files changed, 55 insertions(+), 23 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5dd663c153..14e554d27d 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -685,6 +685,21 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, uintptr_t host_pc, abi_ptr guest_addr); +/** + * cpu_loop_exit_segv: + * @cpu: the cpu context + * @addr: the guest address of the fault + * @access_type: access was read/write/execute + * @maperr: true for invalid page, false for permission fault + * @ra: host pc for unwinding + * + * Use the TCGCPUOps hook to record cpu state, do guest operating system + * specific things to raise SIGSEGV, and jump to the main cpu loop. + */ +void QEMU_NORETURN cpu_loop_exit_segv(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); + #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 01e7e69e7f..1fd38ea624 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -143,35 +143,38 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, int fault_size, MMUAccessType access_type, bool nonfault, uintptr_t ra) { - int flags; + int acc_flag; + bool maperr; switch (access_type) { case MMU_DATA_STORE: - flags = PAGE_WRITE; + acc_flag = PAGE_WRITE_ORG; break; case MMU_DATA_LOAD: - flags = PAGE_READ; + acc_flag = PAGE_READ; break; case MMU_INST_FETCH: - flags = PAGE_EXEC; + acc_flag = PAGE_EXEC; break; default: g_assert_not_reached(); } - if (!guest_addr_valid_untagged(addr) || - page_check_range(addr, 1, flags) < 0) { - if (nonfault) { - return TLB_INVALID_MASK; - } else { - CPUState *cpu = env_cpu(env); - CPUClass *cc = CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_type, - MMU_USER_IDX, false, ra); - g_assert_not_reached(); + if (guest_addr_valid_untagged(addr)) { + int page_flags = page_get_flags(addr); + if (page_flags & acc_flag) { + return 0; /* success */ } + maperr = !(page_flags & PAGE_VALID); + } else { + maperr = true; } - return 0; + + if (nonfault) { + return TLB_INVALID_MASK; + } + + cpu_loop_exit_segv(env_cpu(env), addr, access_type, maperr, ra); } int probe_access_flags(CPUArchState *env, target_ulong addr, diff --git a/linux-user/signal.c b/linux-user/signal.c index 537c6c41c0..8c22f711f1 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -685,9 +685,27 @@ void force_sigsegv(int oldsig) } force_sig(TARGET_SIGSEGV); } - #endif +void cpu_loop_exit_segv(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, bool maperr, uintptr_t ra) +{ + const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + + if (tcg_ops->record_sigsegv) { + tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); + } else if (tcg_ops->tlb_fill) { + tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, ra); + g_assert_not_reached(); + } + + force_sig_fault(TARGET_SIGSEGV, + maperr ? TARGET_SEGV_MAPERR : TARGET_SEGV_ACCERR, + addr); + cpu->exception_index = EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, ra); +} + /* abort execution with signal */ static void QEMU_NORETURN dump_core_and_abort(int target_sig) { @@ -803,7 +821,7 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) access_type = adjust_signal_pc(&pc, is_write); if (host_sig == SIGSEGV) { - const struct TCGCPUOps *tcg_ops; + bool maperr = true; if (info->si_code == SEGV_ACCERR && h2g_valid(host_addr)) { /* If this was a write to a TB protected page, restart. */ @@ -818,18 +836,14 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) * which means that we may get ACCERR when we want MAPERR. */ if (page_get_flags(guest_addr) & PAGE_VALID) { - /* maperr = false; */ + maperr = false; } else { info->si_code = SEGV_MAPERR; } } sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); - - tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; - tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, - MMU_USER_IDX, false, pc); - g_assert_not_reached(); + cpu_loop_exit_segv(cpu, guest_addr, access_type, maperr, pc); } else { sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); } From patchwork Fri Oct 1 17:11:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515062 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1003694jaf; Fri, 1 Oct 2021 10:21:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz21+CiI4n11CosIr8+4Kvi5Zhc7CykKRkgmZTYU01Xihicay1vq1t/fXH3yNEN8fvj5pKe X-Received: by 2002:a9f:3312:: with SMTP id o18mr11090026uab.108.1633108879662; Fri, 01 Oct 2021 10:21:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633108879; cv=none; d=google.com; s=arc-20160816; b=LLZXJ8BxTTPGbMp4eYc1rm9cuRjHwTNyRbYXtXXGiBRHTeXwClLN4CKLiCc27+xc1g PDY1P+PF33E/z5Nj8n4h0oEm5hcz7M+3X1rhNV8cpbaQ9VAGcjgG5O6ZwJlB+1aueSEJ N/ZNva/LnplcOAHjIwnUSoWTSRNjqbuSg40eoacqGTe4rI7RubzbeQFTuqC+cARsluih 43o/DKNDmmkftblpCYs3oOSyUXydmkVvxD4OVKhnV9F657uy9M3phO4jwmFy2r8QA/r/ cfQ0FwpbelMCWd1LbY13pQZeamrnT+QXILkq1aGSdvmQdCvoxPQkOH1+VB0WUUkjOjMF +gQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Sf9skOTdSQRGdKDCQ03O+bONiWBitaK9Yr/SJ3+lYKM=; b=VwZbSyhgR9p1cdi+N+WPm+gXlL5e+jGe9bn5ZS5y91Ae/Z5CwXuZzycoExkZla3UrM dUwEO1IUQ5fTmexnKAFMVcI717dIA5TGtAu66WpzVLlyYBwEFQ2dA/3L5Euo9aicummH 6zRhQrZkrdj9vZFFGTZ2Q85T3xCUSdsAMiMuXm9TOosiNVlF5sFtJU3uDd9Y8pIk+ZqR BfIhsuWRwRjyQjZLttMC4Lwr1FhBTbatm8LpBaIxbG2atciwIlzZnJUBINgdD9acRt6U WiNUXPLgD/jchAsa0zXcEgf2AgPYXk6I4uTzUfkbm6woo882KA4xC6L1mhdWWbccLvbg frEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yYOAOkIw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 21/41] target/alpha: Make alpha_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:31 -0400 Message-Id: <20211001171151.1739472-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::732; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x732.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for alpha-linux-user. Remove the code from cpu_loop that handled EXCP_MMFAULT. Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 7 ++++--- linux-user/alpha/cpu_loop.c | 8 -------- target/alpha/cpu.c | 2 +- target/alpha/helper.c | 13 +------------ 4 files changed, 6 insertions(+), 24 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 772828cc26..ec6657a490 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -439,9 +439,6 @@ void alpha_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU void alpha_cpu_list(void); -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); @@ -449,12 +446,16 @@ uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env); void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val); uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg); void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val); + #ifndef CONFIG_USER_ONLY void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #endif static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc, diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 1b00a81385..4cc8e0a55c 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -54,14 +54,6 @@ void cpu_loop(CPUAlphaState *env) fprintf(stderr, "External interrupt. Exit\n"); exit(EXIT_FAILURE); break; - case EXCP_MMFAULT: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID - ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); - info._sifields._sigfault._addr = env->trap_arg0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_UNALIGN: info.si_signo = TARGET_SIGBUS; info.si_errno = 0; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 93e16a2ffb..52031ca981 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -218,9 +218,9 @@ static const struct SysemuCPUOps alpha_sysemu_ops = { static const struct TCGCPUOps alpha_tcg_ops = { .initialize = alpha_translate_init, - .tlb_fill = alpha_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = alpha_cpu_tlb_fill, .cpu_exec_interrupt = alpha_cpu_exec_interrupt, .do_interrupt = alpha_cpu_do_interrupt, .do_transaction_failed = alpha_cpu_do_transaction_failed, diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 81550d9e2f..266d56ea73 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -119,18 +119,7 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val) *cpu_alpha_addr_gr(env, reg) = val; } -#if defined(CONFIG_USER_ONLY) -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - AlphaCPU *cpu = ALPHA_CPU(cs); - - cs->exception_index = EXCP_MMFAULT; - cpu->env.trap_arg0 = address; - cpu_loop_exit_restore(cs, retaddr); -} -#else +#ifndef CONFIG_USER_ONLY /* Returns the OSF/1 entMM failure indication, or -1 on success. */ static int get_physical_address(CPUAlphaState *env, target_ulong addr, int prot_need, int mmu_idx, From patchwork Fri Oct 1 17:11:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515076 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1013807jaf; Fri, 1 Oct 2021 10:34:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwzvvQQcy34LtGCSLvR18OE2xUz/BpCM5rMch1qPfXWSi+B2pYLUPVDxOeo2Mt4P+3Ic5BW X-Received: by 2002:a1f:5f4d:: with SMTP id t74mr8615135vkb.5.1633109645099; Fri, 01 Oct 2021 10:34:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633109645; cv=none; d=google.com; s=arc-20160816; b=XZHlVXNPtbWoingil8Mo9kPL1HXcqDriyIzuzr/3A/J5LObSjEpotorrkrmmksm1Pk 4G41Tvd7zmeAfXJoxlIYuxFjaGIYn82W9dPeGplOb80s5r19j+9+s078z/14RIPFSo92 UmT2nxueShqOv+l5F91vGzlKkVF1Dr3Yc/w3QsTjysHybt+liDr7wUKbeMwaRaQ7G6br xj86v5J3eVkRv/QCJP3Liwwuvfv6/f+1uy1DacKp6jpks3qwPm8a+MaHYGpknuaXt7Hp DVozmxkfaoYAEFaqtmh7dVGChiiLUCIaIQ35wl6JkgMOKPCMQzMctciLPMy3HriWlc6K /1ZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=c4orM2+k/w36SObBWIcKDbAPe9+W3VGWuqCQu4MwkhQ=; b=C4FYJ6m6UgMJ05dGBtXQ/e7ODeCwU2ikypI53Xaex7eguTtdOzxd8SdgygHqRl+6TQ ujaSk5MW2xAMxj/qQ49WsMVg6+tRRqxAhP4I9wI/jLFGIb2VsESZHtGY98KtusH20R8R N5NZU7i+ieTdEgenvCl9TuYiqwiC1PHyfq1Yx4pKEptDYN0CrgqEFPI1iyJtO2DzIhWI xR5yRVZGRUYWpZs5fDAT/+E2ww7xrGdWxuoNUAvnER1QTDbSI1zkKPBedr7Oom6TOlVw dKT6axtIV1jd27dX4T1WIGhrZo76Z26SbgDl04WKATpLMbtoHEP7r30bNLCSvFLMSusl oDcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ISZSPyoq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 22/41] target/arm: Use cpu_loop_exit_segv for mte tag lookup Date: Fri, 1 Oct 2021 13:11:32 -0400 Message-Id: <20211001171151.1739472-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2a; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the new os interface for raising the exception, rather than calling arm_cpu_tlb_fill directly. Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 724175210b..1500a498b0 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -84,10 +84,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, uintptr_t index; if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE_ORG : PAGE_READ))) { - /* SIGSEGV */ - arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access, - ptr_mmu_idx, false, ra); - g_assert_not_reached(); + cpu_loop_exit_segv(env_cpu(env), ptr, ptr_access, + !(flags & PAGE_VALID), ra); } /* Require both MAP_ANON and PROT_MTE for the page. */ From patchwork Fri Oct 1 17:11:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515095 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1026111jaf; Fri, 1 Oct 2021 10:50:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwfFhXZDYmQUnt+mSs+kgh9OkFCHjljKvQ7UTVqjUM0YjOx+B/+cOnZVYx4izR1d7e5yX7r X-Received: by 2002:a67:7382:: with SMTP id o124mr5672054vsc.54.1633110627086; Fri, 01 Oct 2021 10:50:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633110627; cv=none; d=google.com; s=arc-20160816; b=ctwYKvXe7l1bgqjJufuN3bNKNsuhmb4dZlQSALfvYMf9kdfPCs3iAa4fYlRxJwtM04 gY6uTPgVI6kxWQalGxc9Fb6kf5Wq7XJCYDgWytIWCuJWU0luwPQFBoWtVfpzhXzscxio l3Liw4ioVQE7vILWSfbBs89h2dji+DiUkSlYEOYV7SRWGT/0DF4EHodF3LSnTQXn1yO2 JruYco5XmJvrzoMJjfzLJEXHwGKVncYI61vdlOh33x9yAEXrc4d3/KbLdUw4EDSi9Qxt 0xc6wPkgDg/vQhEREjU5yzoE7crlqyGTyuD/Cd4fmuW/P85bji79OMPfXvcgJ6uPtpWW +swA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MEdAv6cRA9BBhR4lgddgtqkvjCOWQwmTeigzGsiVe00=; b=zWAhRNIUMytrINU9xaTyoJ5OJeHwNQmLwGnmXAK+XYLeQAK+0esA1vjwPDW+nDL90L wsz3zi7DwpZXKccKBNUfUp9ZRW7qGcWFxlU/ekZl46uyJVibOUEn4NvQYTx0V9V0WY9y eawVv24haF2E6kwPFqEJSERriNNq2cMfXys4W5TVzD2ic1JewC6SN3aqGOYeah1rtJC6 Zm4eNlz5Kac9i5a/jJh6HBpfX6WMKOds8mGQrEN0Ek/yq94jOBZpGbcCA2Ra4f6vc5qv 2t/YVoOcjQ7Qa1XEBdEBM2Az6iqRIcpEKQXPCirQjIztGcIoyMwjwKTbTZ3qgYFiPYIU gy8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="c2/PCTGm"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 23/41] target/arm: Implement arm_cpu_record_sigsegv Date: Fri, 1 Oct 2021 13:11:33 -0400 Message-Id: <20211001171151.1739472-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x834.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because of the complexity of setting ESR, continue to use arm_deliver_fault. This means we cannot remove the code within cpu_loop that decodes EXCP_DATA_ABORT and EXCP_PREFETCH_ABORT. But using the new hook means that we don't have to do the page_get_flags check manually, and we'll be able to restrict the tlb_fill hook to sysemu later. Signed-off-by: Richard Henderson --- target/arm/internals.h | 6 ++++++ target/arm/cpu.c | 6 ++++-- target/arm/cpu_tcg.c | 6 ++++-- target/arm/tlb_helper.c | 36 +++++++++++++++++++----------------- 4 files changed, 33 insertions(+), 21 deletions(-) -- 2.25.1 diff --git a/target/arm/internals.h b/target/arm/internals.h index 9fbb364968..984c84d27e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -544,9 +544,15 @@ static inline bool arm_extabort_type(MemTxResult result) return result != MEMTX_DECODE_ERROR; } +#ifdef CONFIG_USER_ONLY +void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 641a8c2d3d..7a18a58ca0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2031,10 +2031,12 @@ static const struct SysemuCPUOps arm_sysemu_ops = { static const struct TCGCPUOps arm_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, - .tlb_fill = arm_cpu_tlb_fill, .debug_excp_handler = arm_debug_excp_handler, -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv = arm_cpu_record_sigsegv, +#else + .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_cpu_exec_interrupt, .do_interrupt = arm_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0d5adccf1a..7b3bea2fbb 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -898,10 +898,12 @@ static void pxa270c5_initfn(Object *obj) static const struct TCGCPUOps arm_v7m_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, - .tlb_fill = arm_cpu_tlb_fill, .debug_excp_handler = arm_debug_excp_handler, -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv = arm_cpu_record_sigsegv, +#else + .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, .do_interrupt = arm_v7m_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 3107f9823e..dc5860180f 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -147,28 +147,12 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } -#endif /* !defined(CONFIG_USER_ONLY) */ - bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { ARMCPU *cpu = ARM_CPU(cs); ARMMMUFaultInfo fi = {}; - -#ifdef CONFIG_USER_ONLY - int flags = page_get_flags(useronly_clean_ptr(address)); - if (flags & PAGE_VALID) { - fi.type = ARMFault_Permission; - } else { - fi.type = ARMFault_Translation; - } - fi.level = 3; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); -#else hwaddr phys_addr; target_ulong page_size; int prot, ret; @@ -210,5 +194,23 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_restore_state(cs, retaddr, true); arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); } -#endif } +#else +void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra) +{ + ARMMMUFaultInfo fi = { + .type = maperr ? ARMFault_Translation : ARMFault_Permission, + .level = 3, + }; + ARMCPU *cpu = ARM_CPU(cs); + + /* + * We report both ESR and FAR to signal handlers. + * For now, it's easiest to deliver the fault normally. + */ + cpu_restore_state(cs, ra, true); + arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi); +} +#endif /* !defined(CONFIG_USER_ONLY) */ From patchwork Fri Oct 1 17:11:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515079 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1015971jaf; Fri, 1 Oct 2021 10:36:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxe6WWeqMUFOK2tddl0NJgst4bnYta2sXSDJcltYVP5+7skNY1etjUdczi2DnlemkCNtxji X-Received: by 2002:ab0:319a:: with SMTP id d26mr11322527uan.102.1633109799769; Fri, 01 Oct 2021 10:36:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633109799; cv=none; d=google.com; s=arc-20160816; b=Tb80Rq3f7fW9GHH1cKvY/5DYR66aVZpK2aCdiIyt9XjRCpbyeNJwko0LAbOy91Qpt5 UwCp7hmtSCABXoxikMCRrH1duFwUSb7EtYvYLsVoDbt08wWpAgHOeMqTfP8KNo6XRPVe fnN55zdcodDdtuSXi8lNN2ZqGEnOanX77HBybecl5HYrk6851A+5rP4Wcgsd0mP/Wi1p qP1lUUzmlZ8J5s1gRm6gxA+cz7Jvgl9bYPRAIfUtMQFNVcMSI7hWx5Xlny06Pb+NlZKa g83HgqrLhNy/7nPzpjYzpgG6PLmR14pEAkxmj2ZzzHpIrsmhGKqa+Y2Hte3oxDfnEs3L G5Ig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=eeVnsYGPYAHebpgHrC5W3wwVNSfsNcsD0o1AtI7xBGA=; b=NRSlMfr1BDkpNJ26VfEjVFYGsyh7Av4PQL1yXN8Ifx5NrUngUFMBUnSDjj6FAOQD4r CPbm8uNGcUBzo7yV6kz0VFiyqEXm72QtIuHOqPw2QwKx6kD/WtBqFCbd3E8jlIPsV3AD d7kuwuN7jU8cVrY+j08S6f0JLVCmKuH8OcJY7jKNWrBUufp41b1SoBaxFMuShCYNse1w lhkAKTx6LwzSOd2z8bFWEuzRDXv3zB7NcihiFWMwuGv8kd0+0zwbbxAtcEjhDQpNjF1e cItCS16RiTU6c3/iUdvB0BEdFVwbJd013kR4AwHdMw6f4dhNr5Hg0v/kqbfnhpXrPzCO 2vaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CLcl0fmU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 24/41] target/cris: Make cris_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:34 -0400 Message-Id: <20211001171151.1739472-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x834.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , alex.bennee@linaro.org, laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for cris-linux-user. Remove the code from cpu_loop that handled the unnamed 0xaa exception. This makes all of the code in helper.c sysemu only, so remove the ifdefs and move the file to cris_softmmu_ss. Cc: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/cris/cpu.h | 8 ++++---- linux-user/cris/cpu_loop.c | 10 ---------- target/cris/cpu.c | 4 ++-- target/cris/helper.c | 18 ------------------ target/cris/meson.build | 7 +++++-- 5 files changed, 11 insertions(+), 36 deletions(-) -- 2.25.1 diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 6603565f83..b445b194ea 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -189,6 +189,10 @@ extern const VMStateDescription vmstate_cris_cpu; void cris_cpu_do_interrupt(CPUState *cpu); void crisv10_cpu_do_interrupt(CPUState *cpu); bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req); + +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #endif void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags); @@ -251,10 +255,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) return !!(env->pregs[PR_CCS] & U_FLAG); } -bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); - /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0 diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index b9085619c4..0d5d268609 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -37,16 +37,6 @@ void cpu_loop(CPUCRISState *env) process_queued_cpu_work(cs); switch (trapnr) { - case 0xaa: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->pregs[PR_EDA]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index c2e7483f5b..ed6c781342 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -205,9 +205,9 @@ static const struct SysemuCPUOps cris_sysemu_ops = { static const struct TCGCPUOps crisv10_tcg_ops = { .initialize = cris_initialize_crisv10_tcg, - .tlb_fill = cris_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = cris_cpu_tlb_fill, .cpu_exec_interrupt = cris_cpu_exec_interrupt, .do_interrupt = crisv10_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ @@ -215,9 +215,9 @@ static const struct TCGCPUOps crisv10_tcg_ops = { static const struct TCGCPUOps crisv32_tcg_ops = { .initialize = cris_initialize_tcg, - .tlb_fill = cris_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = cris_cpu_tlb_fill, .cpu_exec_interrupt = cris_cpu_exec_interrupt, .do_interrupt = cris_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/cris/helper.c b/target/cris/helper.c index 36926faf32..a0d6ecdcd3 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -39,22 +39,6 @@ #define D_LOG(...) do { } while (0) #endif -#if defined(CONFIG_USER_ONLY) - -bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - CRISCPU *cpu = CRIS_CPU(cs); - - cs->exception_index = 0xaa; - cpu->env.pregs[PR_EDA] = address; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - - static void cris_shift_ccs(CPUCRISState *env) { uint32_t ccs; @@ -304,5 +288,3 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return ret; } - -#endif /* !CONFIG_USER_ONLY */ diff --git a/target/cris/meson.build b/target/cris/meson.build index 67c3793c85..c1e326d950 100644 --- a/target/cris/meson.build +++ b/target/cris/meson.build @@ -2,13 +2,16 @@ cris_ss = ss.source_set() cris_ss.add(files( 'cpu.c', 'gdbstub.c', - 'helper.c', 'op_helper.c', 'translate.c', )) cris_softmmu_ss = ss.source_set() -cris_softmmu_ss.add(files('mmu.c', 'machine.c')) +cris_softmmu_ss.add(files( + 'helper.c', + 'machine.c', + 'mmu.c', +)) target_arch += {'cris': cris_ss} target_softmmu_arch += {'cris': cris_softmmu_ss} From patchwork Fri Oct 1 17:11:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515063 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1004596jaf; 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 25/41] target/hexagon: Remove hexagon_cpu_tlb_fill Date: Fri, 1 Oct 2021 13:11:35 -0400 Message-Id: <20211001171151.1739472-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72e; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Taylor Simpson , alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for hexagon. Remove the code from cpu_loop that raises SIGSEGV. Cc: Taylor Simpson Signed-off-by: Richard Henderson --- linux-user/hexagon/cpu_loop.c | 24 +----------------------- target/hexagon/cpu.c | 23 ----------------------- 2 files changed, 1 insertion(+), 46 deletions(-) -- 2.25.1 Reviewed-by: Taylor Simpson diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index bee2a9e4ea..6b24cbaba9 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -28,8 +28,7 @@ void cpu_loop(CPUHexagonState *env) { CPUState *cs = env_cpu(env); - int trapnr, signum, sigcode; - target_ulong sigaddr; + int trapnr; target_ulong syscallnum; target_ulong ret; @@ -39,10 +38,6 @@ void cpu_loop(CPUHexagonState *env) cpu_exec_end(cs); process_queued_cpu_work(cs); - signum = 0; - sigcode = 0; - sigaddr = 0; - switch (trapnr) { case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ @@ -65,12 +60,6 @@ void cpu_loop(CPUHexagonState *env) env->gpr[0] = ret; } break; - case HEX_EXCP_FETCH_NO_UPAGE: - case HEX_EXCP_PRIV_NO_UREAD: - case HEX_EXCP_PRIV_NO_UWRITE: - signum = TARGET_SIGSEGV; - sigcode = TARGET_SEGV_MAPERR; - break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); break; @@ -79,17 +68,6 @@ void cpu_loop(CPUHexagonState *env) trapnr); exit(EXIT_FAILURE); } - - if (signum) { - target_siginfo_t info = { - .si_signo = signum, - .si_errno = 0, - .si_code = sigcode, - ._sifields._sigfault._addr = sigaddr - }; - queue_signal(env, info.si_signo, QEMU_SI_KILL, &info); - } - process_pending_signals(env); } } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 3338365c16..160a46a3d5 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -245,34 +245,11 @@ static void hexagon_cpu_init(Object *obj) qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property); } -static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ -#ifdef CONFIG_USER_ONLY - switch (access_type) { - case MMU_INST_FETCH: - cs->exception_index = HEX_EXCP_FETCH_NO_UPAGE; - break; - case MMU_DATA_LOAD: - cs->exception_index = HEX_EXCP_PRIV_NO_UREAD; - break; - case MMU_DATA_STORE: - cs->exception_index = HEX_EXCP_PRIV_NO_UWRITE; - break; - } - cpu_loop_exit_restore(cs, retaddr); -#else -#error System mode not implemented for Hexagon -#endif -} - #include "hw/core/tcg-cpu-ops.h" static const struct TCGCPUOps hexagon_tcg_ops = { .initialize = hexagon_translate_init, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, - .tlb_fill = hexagon_tlb_fill, }; static void hexagon_cpu_class_init(ObjectClass *c, void *data) From patchwork Fri Oct 1 17:11:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515088 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1020553jaf; Fri, 1 Oct 2021 10:42:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwQjsI5MOzcB72KLOrri4UpmkBjzkB9kw214rMZ4INxeu9+60vk2OxipbOFA+F6+PndeQv0 X-Received: by 2002:a6b:2c51:: with SMTP id s78mr9244218ios.73.1633110165349; Fri, 01 Oct 2021 10:42:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633110165; cv=none; d=google.com; s=arc-20160816; b=Le7WF4mpTcc7Zc59wvqtoJw8F2RsKzU3lKLMJOor17v2PfvTqadYF0h3NezVoaRTU/ /Wqfon4oJOsjAiX4eWu7icgvCcRy3Alc52qV/f3axSEySQEnPCdETi/UMZSp4jCaHy6E XROXQhUYk34QbMTx6iFrrkPeks6arO/emYqwMWfdZE2QKGa3ukIgFy+JvqxMH2XZIgVB yV2UoLT1w9ODsKiF8zMp2qgFQ5lmqKzUFKkTsl7zkO5PdGjfCLzdhFBp+owpnOHrwxUO +ShYlWMxyzPqSkEmI1iTK6STVaRddnEb4b58Pf+zqeXQGM05S3kajVSGAfgKu2Cy8L/D KzEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Jdc9xUljuMqC9v+WfiNACe7k1BrlAm8+Ia/kMx84Cy4=; b=DwjkXsSuaSoHaaf+ZKjInNXTdxDf3oowBm7rdzjnvMXPCQt6TKA8ienwneogV0OrB9 5zB1UJeriCnDjiA3U0OboxrpL4LRKy52tsB10Ucaa+ueZmFz94d+Vv5ZeO8jb3RW8x9B hM/glRCaeJdQ5DmOav6AOuC5oLuh9OV/+pTU7T19QHKLs/gECHO6xQPo7SS4mzQKEADw NQGqILL/0okDW5liCYB0QT/2LtjHTtmc+BQVimn5mrD2oKV9+Q1nKSm5lHEbuttJy3ho w9YvwK9VEi0FIUQ5U2fhlYqq6t0dplLwXZvF1UUFJELntScEJy9P+srBDDvh4bFBaMZU LnDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vVMy3Qv2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 26/41] target/hppa: Make hppa_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:36 -0400 Message-Id: <20211001171151.1739472-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72e; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for hppa-linux-user. Remove the code from cpu_loop that raised SIGSEGV. This makes all of the code in mem_helper.c sysemu only, so remove the ifdefs and move the file to hppa_softmmu_ss. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 +- linux-user/hppa/cpu_loop.c | 16 ---------------- target/hppa/cpu.c | 2 +- target/hppa/mem_helper.c | 15 --------------- target/hppa/meson.build | 6 ++++-- 5 files changed, 6 insertions(+), 35 deletions(-) -- 2.25.1 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index d3cb7a279f..294fd7297f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -323,10 +323,10 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); +#ifndef CONFIG_USER_ONLY bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -#ifndef CONFIG_USER_ONLY void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 81607a9b27..e0a62deeb9 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -144,22 +144,6 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f = env->gr[31]; env->iaoq_b = env->gr[31] + 4; break; - case EXCP_ITLB_MISS: - case EXCP_DTLB_MISS: - case EXCP_NA_ITLB_MISS: - case EXCP_NA_DTLB_MISS: - case EXCP_IMP: - case EXCP_DMP: - case EXCP_DMB: - case EXCP_PAGE_REF: - case EXCP_DMAR: - case EXCP_DMPI: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr = env->cr[CR_IOR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_UNALIGN: info.si_signo = TARGET_SIGBUS; info.si_errno = 0; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 89cba9d7a2..23eb254228 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -145,9 +145,9 @@ static const struct SysemuCPUOps hppa_sysemu_ops = { static const struct TCGCPUOps hppa_tcg_ops = { .initialize = hppa_translate_init, .synchronize_from_tb = hppa_cpu_synchronize_from_tb, - .tlb_fill = hppa_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = hppa_cpu_tlb_fill, .cpu_exec_interrupt = hppa_cpu_exec_interrupt, .do_interrupt = hppa_cpu_do_interrupt, .do_unaligned_access = hppa_cpu_do_unaligned_access, diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index afc5b56c3e..bf07445cd1 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -24,20 +24,6 @@ #include "hw/core/cpu.h" #include "trace.h" -#ifdef CONFIG_USER_ONLY -bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - HPPACPU *cpu = HPPA_CPU(cs); - - /* ??? Test between data page fault and data memory protection trap, - which would affect si_code. */ - cs->exception_index = EXCP_DMP; - cpu->env.cr[CR_IOR] = address; - cpu_loop_exit_restore(cs, retaddr); -} -#else static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) { int i; @@ -392,4 +378,3 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr) hppa_tlb_entry *ent = hppa_find_tlb(env, vaddr); return ent ? ent->ar_type : -1; } -#endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/meson.build b/target/hppa/meson.build index 8a7ff82efc..021e42a2d0 100644 --- a/target/hppa/meson.build +++ b/target/hppa/meson.build @@ -7,13 +7,15 @@ hppa_ss.add(files( 'gdbstub.c', 'helper.c', 'int_helper.c', - 'mem_helper.c', 'op_helper.c', 'translate.c', )) hppa_softmmu_ss = ss.source_set() -hppa_softmmu_ss.add(files('machine.c')) +hppa_softmmu_ss.add(files( + 'machine.c', + 'mem_helper.c', +)) target_arch += {'hppa': hppa_ss} target_softmmu_arch += {'hppa': hppa_softmmu_ss} From patchwork Fri Oct 1 17:11:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515066 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1005779jaf; Fri, 1 Oct 2021 10:24:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzqjlovsQzdKuWAfQy9MFwCjbxU7r82CtD936tC5uBkGHJlUTvMhG/WvwBRjLhzXh3hJnPL X-Received: by 2002:ab0:7e8a:: with SMTP id j10mr7280643uax.58.1633109045153; Fri, 01 Oct 2021 10:24:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633109045; cv=none; d=google.com; s=arc-20160816; b=J4V9pRtspKiFORePUCRYNYRNBhjQnUuZILI5GJ3v2BnQPIgbSxdoXRlDVqnYwCuaQ6 6mg2Y2BMdZeU4KwdCKVyCnCXTmSPDwYwc6vjaicJqHfRZ0d47pJaNGJLbJlqwH1q/Jz3 PRL8LyxYWwriyTZt3nGCLdAvRJBzrZv/QrkGaw3jR7Te1+GuPFf7y1YISj8+TciIDBae 6OfZQ6nnwLdeIW6x+OyYx0pkqs2EG/j0u2HgdTDktQtflya9UaPn2QO7muJQ3FyAJgmk r27K2OHK2Ii9Drh1tpDqzuQIqNTKuNRdZWFpB7kA3Dyv6d4PvCsjGnTSs7Ga/gsJATYg gOMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Bcv7+vrfVWDaxhREKP7oW3QycojCjuZf0xWMtNuZYi8=; b=vNbFG0H53MbLl8T++GmmH18IYfVkQzZBIM7t32vW8Y8yJ/zD9mZIcLeF0KD+lQ84Ug eteKIBVI9S0JvAK1yS+vSdyQCFDJNHy4lr9Wx5qMn2J7Nch/nEGaN9CDlv9NAEfwRylg dwMeJnFvdBuhkDa6sk7xbmzhMotmd4uW6qdWF11U+tgIzYGgAl/SaAA9X8ZEALdmAoPz Cry8WNZO84yOdRSH1lMm8zA3khyxlGacGTti/eTDECRo1MwAZf+AtujPC1ANiN2hXSI3 gcy7QLe/xxCW/uaOzxZedd7uGT7342nyK3blUNU09+BHtmD/tNfW3a12VsOEiiQ/pKVj 2lMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cRH7O3PC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 27/41] target/i386: Implement x86_cpu_record_sigsegv Date: Fri, 1 Oct 2021 13:11:37 -0400 Message-Id: <20211001171151.1739472-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::733; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x733.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Record cr2, error_code, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. Use the maperr parameter to properly set PG_ERROR_P_MASK. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/i386/tcg/helper-tcg.h | 6 ++++++ target/i386/tcg/tcg-cpu.c | 3 ++- target/i386/tcg/user/excp_helper.c | 23 +++++++++++++++++------ 3 files changed, 25 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 60ca09e95e..0a4401e917 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -43,9 +43,15 @@ bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); #endif /* helper.c */ +#ifdef CONFIG_USER_ONLY +void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif void breakpoint_handler(CPUState *cs); diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 3ecfae34cb..6fdfdf9598 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -72,10 +72,11 @@ static const struct TCGCPUOps x86_tcg_ops = { .synchronize_from_tb = x86_cpu_synchronize_from_tb, .cpu_exec_enter = x86_cpu_exec_enter, .cpu_exec_exit = x86_cpu_exec_exit, - .tlb_fill = x86_cpu_tlb_fill, #ifdef CONFIG_USER_ONLY .fake_user_interrupt = x86_cpu_do_interrupt, + .record_sigsegv = x86_cpu_record_sigsegv, #else + .tlb_fill = x86_cpu_tlb_fill, .do_interrupt = x86_cpu_do_interrupt, .cpu_exec_interrupt = x86_cpu_exec_interrupt, .debug_excp_handler = breakpoint_handler, diff --git a/target/i386/tcg/user/excp_helper.c b/target/i386/tcg/user/excp_helper.c index a89b5228fd..cd507e2a1b 100644 --- a/target/i386/tcg/user/excp_helper.c +++ b/target/i386/tcg/user/excp_helper.c @@ -22,18 +22,29 @@ #include "exec/exec-all.h" #include "tcg/helper-tcg.h" -bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra) { X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; + /* + * The error_code that hw reports as part of the exception frame + * is copied to linux sigcontext.err. The exception_index is + * copied to linux sigcontext.trapno. Short of inventing a new + * place to store the trapno, we cannot let our caller raise the + * signal and set exception_index to EXCP_INTERRUPT. + */ env->cr[2] = addr; - env->error_code = (access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT; - env->error_code |= PG_ERROR_U_MASK; + env->error_code = ((access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT) + | (maperr ? 0 : PG_ERROR_P_MASK) + | PG_ERROR_U_MASK; cs->exception_index = EXCP0E_PAGE; + + /* Disable do_interrupt_user. */ env->exception_is_int = 0; env->exception_next_eip = -1; - cpu_loop_exit_restore(cs, retaddr); + + cpu_loop_exit_restore(cs, ra); } From patchwork Fri Oct 1 17:11:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515069 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1008438jaf; Fri, 1 Oct 2021 10:27:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyeMpBai79PLJxK/BSG9A3bP07v8muBcG54ChAYbzzB3KzNwJ51C2ZXCBynQbTkgoa7jJfD X-Received: by 2002:a37:a4cc:: with SMTP id n195mr10376906qke.86.1633109254763; Fri, 01 Oct 2021 10:27:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633109254; cv=none; d=google.com; s=arc-20160816; b=wxXdvKKRwHb0oimXoxVl/c+WW4eMlmCZcl7+FOg+34z8MuNx/B0VUFJIKHvIIaOxh0 FlpyZzqlIDKUkenee3Vo+gh7TZu7BFBNMqKQXuQGlad8tJWYGAdAizQ0rerztyILCYyv 2h3bTckjNYpUXchTrW2ui3ITekI27tfAydXY54/pTzNAo9T1jVD6h6e8xdUke2bkEBDg 6mioEKD2ZJFitl/JlJtw4b7vJkPDNLKr/RDDfjXvnL2Yo09YvSYRMbWz5/tZra0WC7Qh pgoJ9VoQVZi89Tj2SPdh+wTZmgIVwjT0kOx3b+TM95ui0XVjdYe234P6emqUObIIzfnf Up1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=G1HWedffqhycyxP8d2WDLOk4nPDaQm4JAuhJ0f230MI=; b=iF9VTORaqdXf2HxSXXEBJHQxNO5wgFci54NbKavYclY5DjA0YF96DnbaggDdvwUCX/ mT1csW0jID+O/akG4bzKEv+Ef7ByCO4H65GDkudNuJdq0Ua8vO5rPjUzmt79bxrp2W4g URQ2aX7c3EAdzt4j8vWET7LtSltsfkwXxGvRLnISt1QNwvUHfFgtMWd0qgR0tO7MQM0I +lxANCTdfAGeiUqMaDp/SiTMAiVDEqw0OzniIbMshGxiZ61MHxPGRATQHRy0LCIwvCA8 qWzFS5PzfggXvcUzcLCb8FwKRF7D8N0bl4qgyCZI7scVLWkt8WZCJj8LgxOpknzmvC7y lZJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vQnMVrMd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 28/41] target/m68k: Make m68k_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:38 -0400 Message-Id: <20211001171151.1739472-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2e; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for m68k-linux-user. Remove the code from cpu_loop that handled EXCP_ACCESS. Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 10 ---------- target/m68k/cpu.c | 2 +- target/m68k/helper.c | 6 +----- 3 files changed, 2 insertions(+), 16 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index ebf32be78f..790bd558c3 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -90,16 +90,6 @@ void cpu_loop(CPUM68KState *env) case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; - case EXCP_ACCESS: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->mmu.ar; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_DEBUG: info.si_signo = TARGET_SIGTRAP; info.si_errno = 0; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 66d22d1189..c7aeb7da9c 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -515,9 +515,9 @@ static const struct SysemuCPUOps m68k_sysemu_ops = { static const struct TCGCPUOps m68k_tcg_ops = { .initialize = m68k_tcg_init, - .tlb_fill = m68k_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = m68k_cpu_tlb_fill, .cpu_exec_interrupt = m68k_cpu_exec_interrupt, .do_interrupt = m68k_cpu_do_interrupt, .do_transaction_failed = m68k_cpu_transaction_failed, diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 137a3e1a3d..5728e48585 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -978,16 +978,12 @@ void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector) } } -#endif - bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType qemu_access_type, int mmu_idx, bool probe, uintptr_t retaddr) { M68kCPU *cpu = M68K_CPU(cs); CPUM68KState *env = &cpu->env; - -#ifndef CONFIG_USER_ONLY hwaddr physical; int prot; int access_type; @@ -1051,12 +1047,12 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (!(access_type & ACCESS_STORE)) { env->mmu.ssw |= M68K_RW_040; } -#endif cs->exception_index = EXCP_ACCESS; env->mmu.ar = address; cpu_loop_exit_restore(cs, retaddr); } +#endif /* !CONFIG_USER_ONLY */ uint32_t HELPER(bitrev)(uint32_t x) { From patchwork Fri Oct 1 17:11:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515073 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1011428jaf; Fri, 1 Oct 2021 10:31:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy8bAtgx3hn6NWBe3lmJQ75CBKY+36zQdYnoSuqjPAwXZzpxFChV4Hcq30EHbpWBv+HqiVd X-Received: by 2002:a67:f618:: with SMTP id k24mr5567425vso.48.1633109474670; Fri, 01 Oct 2021 10:31:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633109474; cv=none; d=google.com; s=arc-20160816; b=p2FYqGi+894XXrNfgrbdGRWVBTBrxBXEyBhkdtSmKKmSVz8nK3ic++04/dFyUB9hF2 nTphW/b4qDdgBPFzRSpNPSzaSdrCowoxyQLUWPRE9oShnSh4Sb9aVtcbYul8NSpJyj4k EgKNAQL/3AsKZVXI4YgfhBcfC5DfOt0EJvnNOj3BuiLSdDK05Wi//ILviFacMIAnvCjG SDjwAV1YcuWNv4/NqKDmqG+lGu0PChofkgz24KzbTrDpYY3NSfRWG4PfaztkhfVN5P6r FgUNyAudG0d5L2QMs64D7v89RDOvclB1gw0CfSkdke+RrCF6auhVKjdYLpxnENrAd+mC rt/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XFe/Vw3cr/4hcwv1jUnUaBVa+r7ZoPXYiTXFgPNQ9tk=; b=ntVJ8MuFF7GoUF3PxzwBn4jRTXe8YJrPplitSZg5qjOymeqsv6AuMP4hgCTHHRhJxA aPytED3Rr5MR9TkNLHKqeKRE8PFHn9C8BolKAifi6QOg7HG+fkHgoqyqMtFZ6z9O6LRh ektCIGsJ0Ocuh0yIwaK4SbwPpClnRFcnvC+rw65XfoUOh3t5JN5TfnAr8OCaaonTVDmp W/a7Vhml7FwPZjo2vAntVPIJtWJ966dH8juIo8dA1Ll6WAV7C2JGz+R2rMY6XQAlQI4g XJLVpxDj8JTodym9n6Edl6u1ioDQFAze53qt3+Dnq8vwjHxj0ZiBVpOdYeeXojA/uIIu uhAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hN0VzbmA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 29/41] target/microblaze: Make mb_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:39 -0400 Message-Id: <20211001171151.1739472-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2f; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for mb linux-user. Remove the code from cpu_loop that handled the unnamed 0xaa exception. Cc: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 8 ++++---- linux-user/microblaze/cpu_loop.c | 10 ---------- target/microblaze/cpu.c | 2 +- target/microblaze/helper.c | 13 +------------ 4 files changed, 6 insertions(+), 27 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b7a848bbae..e9cd0b88de 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -394,10 +394,6 @@ void mb_tcg_init(void); #define MMU_USER_IDX 2 /* See NB_MMU_MODES further up the file. */ -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); - typedef CPUMBState CPUArchState; typedef MicroBlazeCPU ArchCPU; @@ -415,6 +411,10 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, } #if !defined(CONFIG_USER_ONLY) +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index 52222eb93f..a94467dd2d 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -37,16 +37,6 @@ void cpu_loop(CPUMBState *env) process_queued_cpu_work(cs); switch (trapnr) { - case 0xaa: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = 0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 15db277925..b9c888b87e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -365,9 +365,9 @@ static const struct SysemuCPUOps mb_sysemu_ops = { static const struct TCGCPUOps mb_tcg_ops = { .initialize = mb_tcg_init, .synchronize_from_tb = mb_cpu_synchronize_from_tb, - .tlb_fill = mb_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = mb_cpu_tlb_fill, .cpu_exec_interrupt = mb_cpu_exec_interrupt, .do_interrupt = mb_cpu_do_interrupt, .do_transaction_failed = mb_cpu_transaction_failed, diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index dd2aecd1d5..a607fe68e5 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -24,18 +24,7 @@ #include "qemu/host-utils.h" #include "exec/log.h" -#if defined(CONFIG_USER_ONLY) - -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - cs->exception_index = 0xaa; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - +#ifndef CONFIG_USER_ONLY static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu, MMUAccessType access_type) { From patchwork Fri Oct 1 17:11:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515071 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1009183jaf; Fri, 1 Oct 2021 10:28:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzBJGw9928+5oYA7ubYWAw8WiY/GeDsJel+fYCGcqoJVepqcY0E9TiRaJV1tWEhw+YNqLQb X-Received: by 2002:ab0:5b03:: with SMTP id u3mr11370678uae.41.1633109316409; Fri, 01 Oct 2021 10:28:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633109316; cv=none; d=google.com; s=arc-20160816; b=jKswf3uZtnzr/tfkw6LKgNYbOg/zgD4fYycd9lVI8IDLhKxRybZwKCSLzp+rbKFhQW 9GkVSpOsbpnSOeJy6KtHgRz7bS8qQWVn3KHl7/vuEFH6nIItJP98Zp+BiT7kzhWxNqqt QlYcgYTTBG/O17Z+TgachQropMdDV4l64hlfMHxKa33d+pG/F0KzshwlBV3rL647sgAF sUTgYK3Hn01FiQlxGB1ut/YMy6ZgUnd70jTUPI3lBwO+w+P6NN8oO3PEcVrUC6oGH9Be 38iYtGzrW3aFDJVE5CjtiUuep0MV6fFRMHcO5s6tZpgrdr4e9o0rkN1E9Hu9mFwASBfU 3AnQ== ARC-Message-Signature: i=1; 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 30/41] target/mips: Make mips_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:40 -0400 Message-Id: <20211001171151.1739472-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for mips linux-user. This means we can remove tcg/user/tlb_helper.c entirely. Remove the code from cpu_loop that raised SIGSEGV. Signed-off-by: Richard Henderson --- target/mips/tcg/tcg-internal.h | 7 ++-- linux-user/mips/cpu_loop.c | 11 ------ target/mips/cpu.c | 2 +- target/mips/tcg/user/tlb_helper.c | 59 ------------------------------- target/mips/tcg/meson.build | 3 -- target/mips/tcg/user/meson.build | 3 -- 6 files changed, 5 insertions(+), 80 deletions(-) delete mode 100644 target/mips/tcg/user/tlb_helper.c delete mode 100644 target/mips/tcg/user/meson.build -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index bad3deb611..466768aec4 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -18,9 +18,6 @@ void mips_tcg_init(void); void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; @@ -60,6 +57,10 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, MemTxResult response, uintptr_t retaddr); void cpu_mips_tlb_flush(CPUMIPSState *env); +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + #endif /* !CONFIG_USER_ONLY */ #endif diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index cb03fb066b..b735c99a24 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -158,17 +158,6 @@ done_syscall: } env->active_tc.gpr[2] = ret; break; - case EXCP_TLBL: - case EXCP_TLBS: - case EXCP_AdEL: - case EXCP_AdES: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->CP0_BadVAddr; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_CpU: case EXCP_RI: info.si_signo = TARGET_SIGILL; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 00e0c55d0e..4aae23934b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -539,9 +539,9 @@ static const struct SysemuCPUOps mips_sysemu_ops = { static const struct TCGCPUOps mips_tcg_ops = { .initialize = mips_tcg_init, .synchronize_from_tb = mips_cpu_synchronize_from_tb, - .tlb_fill = mips_cpu_tlb_fill, #if !defined(CONFIG_USER_ONLY) + .tlb_fill = mips_cpu_tlb_fill, .cpu_exec_interrupt = mips_cpu_exec_interrupt, .do_interrupt = mips_cpu_do_interrupt, .do_transaction_failed = mips_cpu_do_transaction_failed, diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_helper.c deleted file mode 100644 index 210c6d529e..0000000000 --- a/target/mips/tcg/user/tlb_helper.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * MIPS TLB (Translation lookaside buffer) helpers. - * - * Copyright (c) 2004-2005 Jocelyn Mayer - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ -#include "qemu/osdep.h" - -#include "cpu.h" -#include "exec/exec-all.h" -#include "internal.h" - -static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type) -{ - CPUState *cs = env_cpu(env); - - env->error_code = 0; - if (access_type == MMU_INST_FETCH) { - env->error_code |= EXCP_INST_NOTAVAIL; - } - - /* Reference to kernel address from user mode or supervisor mode */ - /* Reference to supervisor address from user mode */ - if (access_type == MMU_DATA_STORE) { - cs->exception_index = EXCP_AdES; - } else { - cs->exception_index = EXCP_AdEL; - } - - /* Raise exception */ - if (!(env->hflags & MIPS_HFLAG_DM)) { - env->CP0_BadVAddr = address; - } -} - -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - - /* data access */ - raise_mmu_exception(env, address, access_type); - do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr); -} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 8f6f7508b6..98003779ae 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -28,9 +28,6 @@ mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'mxu_translate.c', )) -if have_user - subdir('user') -endif if have_system subdir('sysemu') endif diff --git a/target/mips/tcg/user/meson.build b/target/mips/tcg/user/meson.build deleted file mode 100644 index 79badcd321..0000000000 --- a/target/mips/tcg/user/meson.build +++ /dev/null @@ -1,3 +0,0 @@ -mips_user_ss.add(files( - 'tlb_helper.c', -)) From patchwork Fri Oct 1 17:11:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515103 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1030137jaf; Fri, 1 Oct 2021 10:55:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyFRb/b6dRprqcuhNXuHMBBAzLa8aj+Y/cFnCENBydYn2mPJMnwCvI/zCWbok3cmTspVag4 X-Received: by 2002:a92:300c:: with SMTP id x12mr9758657ile.230.1633110952523; Fri, 01 Oct 2021 10:55:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633110952; cv=none; d=google.com; s=arc-20160816; b=fnczqDpgqA6f8L5FHF7URkXsDSZe6hQ6ufhBe3Qh8Yt70/xhJMkBC4XMjefDBVowmJ 7WV84Uv6G7sG4eMvF1iKsAdKgroYm9t0Fk+L6HmMbdO6jeQx3zUPqSKAPf51a2tBKYpM fT3U5YVRse2MNDzimxpGOX0kYcIg0KfUKrBnNHKnJka+GFSpNjNqxWgYnMjLkhltMzMm fQy6LyxrkrwVhwntiYEYT/Uom3pm7d7TZT6ELhWk9srKMxfPyJxa6GXT99rEY7f8e6IW YAT5CVotBTnVZ7J3HB4zPGrR2DGFJ5AaHaKpS/5QN9J6v/91Rps/PY8LYcZGt7L9s2Dj GMiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=g+FO3WUb/++tC//nR4BBTKuJptT+iDAQAdjiSDu9yJ4=; b=HYNk4KHHJa6KYzvePtZHizKYB/jj664gkOOIwvJFN5GpTCbDqkSY8pDQFCgbBbnQG5 gzE7hRVYF6cdpx2h8pDkYMOwPm+WNlSxU54dwok2k6UnqtFaVjRaPNiXE+levy4LaEbR bPj12LzwK7SXrQysaXq/+1bGZSSBd+yeGkvkUEVBlpHsGSXsUQNX/jnuLaxFjjFvOznf LaFen5ykmg7AWYz1PgwTnYg0ELqXROAdSLz9HHC6f8SaVfWptyUV+a7Q2qpD1AUpIzGO +QntKmd/tDYSnFr/MqPvvUe97ndglF/yed6iLj1BgXgCN+iHoNEqXD1+9yGdhZnmxUKW kn9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=tNv6UJvR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 31/41] target/nios2: Implement nios2_cpu_record_sigsegv Date: Fri, 1 Oct 2021 13:11:41 -0400 Message-Id: <20211001171151.1739472-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82c; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because the linux-user kuser page handling is currently implemented by detecting magic addresses in the unnamed 0xaa trap, we cannot simply remove nios2_cpu_tlb_fill and rely on the fallback code. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 6 ++++++ target/nios2/cpu.c | 6 ++++-- target/nios2/helper.c | 7 ++++--- 3 files changed, 14 insertions(+), 5 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index a80587338a..1a69ed7a49 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -218,9 +218,15 @@ static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) MMU_SUPERVISOR_IDX; } +#ifdef CONFIG_USER_ONLY +void nios2_cpu_record_sigsegv(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif static inline int cpu_interrupts_enabled(CPUNios2State *env) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 947bb09bc1..421cad114a 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -220,9 +220,11 @@ static const struct SysemuCPUOps nios2_sysemu_ops = { static const struct TCGCPUOps nios2_tcg_ops = { .initialize = nios2_tcg_init, - .tlb_fill = nios2_cpu_tlb_fill, -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv = nios2_cpu_record_sigsegv, +#else + .tlb_fill = nios2_cpu_tlb_fill, .cpu_exec_interrupt = nios2_cpu_exec_interrupt, .do_interrupt = nios2_cpu_do_interrupt, .do_unaligned_access = nios2_cpu_do_unaligned_access, diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 53be8398e9..e5c98650e1 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -38,10 +38,11 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[R_EA] = env->regs[R_PC] + 4; } -bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { + /* FIXME: Disentangle kuser page from linux-user sigsegv handling. */ cs->exception_index = 0xaa; cpu_loop_exit_restore(cs, retaddr); } From patchwork Fri Oct 1 17:11:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515077 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1013912jaf; Fri, 1 Oct 2021 10:34:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx8kFZmbMYPyotvCjdMSGVFOU7BdJqXE5BPnZgSHD4eP1S26sKxMBY47IHc+v39svq8j8Re X-Received: by 2002:a67:f558:: with SMTP id z24mr5699504vsn.30.1633109653620; Fri, 01 Oct 2021 10:34:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633109653; cv=none; d=google.com; s=arc-20160816; b=P/eMl0vE7Mj3Tz2asu+Avk3+GIOJwQ4p7jLyCm8R42+wcE/BqXIUmzTZ6YAfsPqIQK ECM4zOMW+gMhguaJFF+lWRxjuo6ug0RbX9lHIAgtksrUhKHvgh8IXduganpuh4DY2xcE bKmb/BVbc83WM00EcntppFA5aJ8M9iMC1ghVyfiNQ1FIFCVpt/B4MftzH7JtpRT4/SS+ TQ5YvBs+TzQWiKJ5RYtHp9gpJj+fleEKM2MW2OJmnu+dGjjEWmMDw4RCKv/FY9GJJuPu palrnN5dqCa7B3aoP9K9RpdRP1VDOuC7jGLntK0eBBEqKxf4iripU7Xoa84sudS16XOc evKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cVCx2jHCPvPujkZ/wrXYdO47hYaVZq7kiqP/WMFmGDE=; b=Kt3jzuQe1v9JuWcYXX6eElKgvctQdBAgQRGVIlKyVBQvBGumd7xAeXLWbr/MYsYlvu 4DKMSYWwL71rUGlzLqkG4kDiYnpZZSReBKXLCNLz5GewMuP4zxLLRvn8npbmdqs46xxy xNfQ641cEr7viRIo4X59bME70wNX1d2PF3wJoTDFJSRIJEXgLWUoxuYaKAMLf6LebPzY LxKgsbVNypoByPxmZ2gfjFZUa9Nyz80UW76YAFsi9262O9wZ3dRtVio4K2ub9kbhidPy 4ALVomD13KAyfXUal9LAI++1MN8d+j42xg2sDLX/RAf54GeQxCQIju/VdjqZUdDoXiCr Qxtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="Aew/8u6Y"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 32/41] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE Date: Fri, 1 Oct 2021 13:11:42 -0400 Message-Id: <20211001171151.1739472-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2c; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2c.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The kernel vectors both of these through unhandled_exception, which results in force_sig(SIGSEGV). This isn't very useful for userland when enabling overflow traps or fpu traps, but c'est la vie. Cc: Stafford Horne Signed-off-by: Richard Henderson --- linux-user/openrisc/cpu_loop.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index f6360db47c..de5417a262 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -56,13 +56,17 @@ void cpu_loop(CPUOpenRISCState *env) break; case EXCP_DPF: case EXCP_IPF: - case EXCP_RANGE: info.si_signo = TARGET_SIGSEGV; info.si_errno = 0; info.si_code = TARGET_SEGV_MAPERR; info._sifields._sigfault._addr = env->pc; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; + case EXCP_RANGE: + case EXCP_FPE: + /* ??? The kernel vectors both of these to unhandled_exception. */ + force_sig(TARGET_SIGSEGV); + break; case EXCP_ALIGN: info.si_signo = TARGET_SIGBUS; info.si_errno = 0; @@ -77,13 +81,6 @@ void cpu_loop(CPUOpenRISCState *env) info._sifields._sigfault._addr = env->pc; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case EXCP_FPE: - info.si_signo = TARGET_SIGFPE; - info.si_errno = 0; - info.si_code = 0; - info._sifields._sigfault._addr = env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_INTERRUPT: /* We processed the pending cpu work above. */ break; From patchwork Fri Oct 1 17:11:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515080 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1016064jaf; Fri, 1 Oct 2021 10:36:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw/bimhEMt5Nj376s1V70wq+ICu68/ir9WqP1gYE7+g/iaE7mhvRuh9cUQ+U/XzZTdAQ+Nq X-Received: by 2002:ab0:3447:: with SMTP id a7mr11734465uaq.56.1633109808973; Fri, 01 Oct 2021 10:36:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633109808; cv=none; d=google.com; s=arc-20160816; b=UBWX8AgA1dI1RU1B0l9kFr1sF3rZ++IBFaCxpVZ1Sh5KAa4f7RPJAdMSSZXfVdnTQV HA6H/VFhEz2u0lNfregLx/9yMJ7Sfq9MXP4FGW1BgDBBYhHsAOsxz65KD2x5TZyhsIbt eipK5TWupBxMZPo3utgeE2D8lMAM5ZkyG3x3ZYWQi6QC2YXuhm9Xxwzs8XGwCJ6TIlGb yGEAKpM43UoJvBwJ+1MeTIseah5401BcChUGQKGmYWrijc4ypNJGpdiYxX0R6oDgMyZI CyLXGPJ6RljA27xzHLqnmlo8QlyfTY7QK1BqUXTqTqNddT41klFhUTnAbwoERGThOPiu y2XQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bhFTWYUd/DdGCKOIwhaKfMZGLTFXZbTF8Lut7J+0pC4=; b=qZ32as4L4GnpPSOhUK0ZHwvlAqqo/BbJuJCa+qKT3bkDmqxCcKRApEnGe3USaCVG0v xTiGjuQIc+196W4L1A+6U2HDwqQHeVp/pHUq0KaabUbWMPmgtKb8/GTrCAD/9ZC50o9F CABFeK65oPUz3FUwm/bF+a2oGRwCWr7gub9XC1px7VLhZRxUp/hsJ3H+Tnd5XwLnwNsI lq4KcJxCMiKDv3vGejNCSQf42ElEDW9ZTZbOWA76JsyPTreRK4Kbl/vb83xxw2jFawp/ 476HJxYpX4eD2UfWnTJS+wOBu8EyXB2gCnpx6rFthJCGeJ44FnXA0KGs/5EKoVJ1Hyc9 /IkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ms8cDPku; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 33/41] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:43 -0400 Message-Id: <20211001171151.1739472-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for openrisc. This makes all of the code in mmu.c sysemu only, so remove the ifdefs and move the file to openrisc_softmmu_ss. Remove the code from cpu_loop that handled EXCP_DPF. Cc: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 7 ++++--- linux-user/openrisc/cpu_loop.c | 8 -------- target/openrisc/cpu.c | 2 +- target/openrisc/mmu.c | 8 -------- target/openrisc/meson.build | 2 +- 5 files changed, 6 insertions(+), 21 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 187a4a114e..ee069b080c 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -317,14 +317,15 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); -bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); int print_insn_or1k(bfd_vma addr, disassemble_info *info); #define cpu_list cpu_openrisc_list #ifndef CONFIG_USER_ONLY +bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + extern const VMStateDescription vmstate_openrisc_cpu; void openrisc_cpu_do_interrupt(CPUState *cpu); diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index de5417a262..fb37fb7651 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -54,14 +54,6 @@ void cpu_loop(CPUOpenRISCState *env) cpu_set_gpr(env, 11, ret); } break; - case EXCP_DPF: - case EXCP_IPF: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_RANGE: case EXCP_FPE: /* ??? The kernel vectors both of these to unhandled_exception. */ diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 27cb04152f..dfbafc5236 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -186,9 +186,9 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { static const struct TCGCPUOps openrisc_tcg_ops = { .initialize = openrisc_translate_init, - .tlb_fill = openrisc_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = openrisc_cpu_tlb_fill, .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, .do_interrupt = openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 94df8c7bef..91cedf4125 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -23,11 +23,8 @@ #include "exec/exec-all.h" #include "exec/gdbstub.h" #include "qemu/host-utils.h" -#ifndef CONFIG_USER_ONLY #include "hw/loader.h" -#endif -#ifndef CONFIG_USER_ONLY static inline void get_phys_nommu(hwaddr *phys_addr, int *prot, target_ulong address) { @@ -94,7 +91,6 @@ static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot, return need & PAGE_EXEC ? EXCP_ITLBMISS : EXCP_DTLBMISS; } } -#endif static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, int exception) @@ -113,7 +109,6 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, OpenRISCCPU *cpu = OPENRISC_CPU(cs); int excp = EXCP_DPF; -#ifndef CONFIG_USER_ONLY int prot; hwaddr phys_addr; @@ -138,13 +133,11 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, if (probe) { return false; } -#endif raise_mmu_exception(cpu, addr, excp); cpu_loop_exit_restore(cs, retaddr); } -#ifndef CONFIG_USER_ONLY hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { OpenRISCCPU *cpu = OPENRISC_CPU(cs); @@ -177,4 +170,3 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } } -#endif diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build index e445dec4a0..84322086ec 100644 --- a/target/openrisc/meson.build +++ b/target/openrisc/meson.build @@ -10,7 +10,6 @@ openrisc_ss.add(files( 'fpu_helper.c', 'gdbstub.c', 'interrupt_helper.c', - 'mmu.c', 'sys_helper.c', 'translate.c', )) @@ -19,6 +18,7 @@ openrisc_softmmu_ss = ss.source_set() openrisc_softmmu_ss.add(files( 'interrupt.c', 'machine.c', + 'mmu.c', )) target_arch += {'openrisc': openrisc_ss} From patchwork Fri Oct 1 17:11:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515089 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1021049jaf; Fri, 1 Oct 2021 10:43:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyX2hLNTxAp60vlEzxmkcNK6cBfxuqstpJV3jvscj5SbsLHRbgmAdk+wIo0tDCxlVy+RNZP X-Received: by 2002:a05:6214:1342:: with SMTP id b2mr11919235qvw.16.1633110208891; Fri, 01 Oct 2021 10:43:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633110208; cv=none; d=google.com; s=arc-20160816; b=NIMgYryX33tugC8JgJ4pJs9JTCcOeY+KZjsXeKo/GsV43cRFz7S45Q1AmvXfiosoQH YkOnPKA+20we1cQmZMseuBHVpdvOjFHboGjEltq6I5zzYKuytf591e2NUxHUwtkp3/xs iK25bOT2DNbRqr12nOVbYCW6fW6YWxbclcPB/JzTFp0ptBIMDEI5bpm1ghybhVqr490r N1HKSo8r8FnjBw9+lLleyt2FXbO6ROh+nria/1jS5faiRJH4U990tPUs6VfmCpkV6rRy mP9pXauKERGobBM5Q3hYIIFr9F5R8PocTIyEVaNbDfJl3FwkMOTmZYcfx/N9VGzV7wSS /s6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=h+WX/Xz3j7uTzh8f9NwZfFO9w7icTNNLSs9RiVXjf3k=; b=QOnDSsiaOykRygE4ABR5Z9VpuZYkxDqf0/BuT5gi8fSbc03BiTU3ZnP/pfMC9IrDgu xumgeouEIMGDUJQ8yq1EhPCpY4s6TmhseqY+cjtgJG6mnMBgo79SrbwyiuKIDZfj7DW6 Z295MIIfyJ4V+eGh8ANvocJIFfOda/eTAPZ+soXfncTxtbObY8L83CEswUh51AD7fD8T Cd6/xthJJ2AGahIUqq0lZ2wz8eQvyEaNdx3k8rrjHF1bRAEjKUsRTS/MxSyEsdGG9Sbl N/oVVm4NIQZAw3dfsGNYw7QJvm2UEsabOQUXQApj82UbXQH6ko/gmwefkG0OMpvBdYeP ntaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mCrnYTJn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 34/41] target/ppc: Implement ppc_cpu_record_sigsegv Date: Fri, 1 Oct 2021 13:11:44 -0400 Message-Id: <20211001171151.1739472-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, alex.bennee@linaro.org, laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Record DAR, DSISR, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. This is exactly what the user-mode ppc_cpu_tlb_fill does, so simply rename it as ppc_cpu_record_sigsegv. Cc: qemu-ppc@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 3 --- target/ppc/internal.h | 9 +++++++++ target/ppc/cpu_init.c | 6 ++++-- target/ppc/user_only_helper.c | 15 +++++++++++---- 4 files changed, 24 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 01d3773bc7..60d1117845 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1278,9 +1278,6 @@ extern const VMStateDescription vmstate_ppc_cpu; /*****************************************************************************/ void ppc_translate_init(void); -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); #if !defined(CONFIG_USER_ONLY) void ppc_store_sdr1(CPUPPCState *env, target_ulong value); diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 55284369f5..339974b7d8 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -283,5 +283,14 @@ static inline void pte_invalidate(target_ulong *pte0) #define PTE_PTEM_MASK 0x7FFFFFBF #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) +#ifdef CONFIG_USER_ONLY +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#endif #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 6aad01d1d3..ec8da08f0b 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -9014,9 +9014,11 @@ static const struct SysemuCPUOps ppc_sysemu_ops = { static const struct TCGCPUOps ppc_tcg_ops = { .initialize = ppc_translate_init, - .tlb_fill = ppc_cpu_tlb_fill, -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv = ppc_cpu_record_sigsegv, +#else + .tlb_fill = ppc_cpu_tlb_fill, .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .do_interrupt = ppc_cpu_do_interrupt, .cpu_exec_enter = ppc_cpu_exec_enter, diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index aa3f867596..7ff76f7a06 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -21,16 +21,23 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "internal.h" - -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; int exception, error_code; + /* + * Both DSISR and the "trap number" (exception vector offset, + * looked up from exception_index) are present in the linux-user + * signal frame. + * FIXME: we don't actually populate the trap number properly. + * It would be easiest to fill in an env->trap value now. + */ if (access_type == MMU_INST_FETCH) { exception = POWERPC_EXCP_ISI; error_code = 0x40000000; From patchwork Fri Oct 1 17:11:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515093 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1024022jaf; Fri, 1 Oct 2021 10:47:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwjpNDoRScvNOPmLWcCKK3buedWISHmALKfi5TjKrix5C2nc9Js5s1QBIX4GHIevWnLastV X-Received: by 2002:a67:b208:: with SMTP id b8mr5600798vsf.53.1633110457798; Fri, 01 Oct 2021 10:47:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 35/41] target/riscv: Make riscv_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:45 -0400 Message-Id: <20211001171151.1739472-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2d; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for riscv. Remove the code from cpu_loop that raised SIGSEGV. Cc: qemu-riscv@nongnu.org Signed-off-by: Richard Henderson --- linux-user/riscv/cpu_loop.c | 7 ------- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 21 +-------------------- 3 files changed, 2 insertions(+), 28 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 9859a366e4..aef019b1c8 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -87,13 +87,6 @@ void cpu_loop(CPURISCVState *env) sigcode = TARGET_TRAP_BRKPT; sigaddr = env->pc; break; - case RISCV_EXCP_INST_PAGE_FAULT: - case RISCV_EXCP_LOAD_PAGE_FAULT: - case RISCV_EXCP_STORE_PAGE_FAULT: - signum = TARGET_SIGSEGV; - sigcode = TARGET_SEGV_MAPERR; - sigaddr = env->badaddr; - break; case RISCV_EXCP_SEMIHOST: env->gpr[xA0] = do_common_semihosting(cs); env->pc += 4; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7c626d89cd..0292a72feb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -675,9 +675,9 @@ static const struct SysemuCPUOps riscv_sysemu_ops = { static const struct TCGCPUOps riscv_tcg_ops = { .initialize = riscv_translate_init, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, - .tlb_fill = riscv_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = riscv_cpu_tlb_fill, .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .do_interrupt = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d41d5cd27c..b520d6fc78 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -748,7 +748,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, riscv_cpu_two_stage_lookup(mmu_idx); riscv_raise_exception(env, cs->exception_index, retaddr); } -#endif /* !CONFIG_USER_ONLY */ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -756,7 +755,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; -#ifndef CONFIG_USER_ONLY vaddr im_address; hwaddr pa = 0; int prot, prot2, prot_pmp; @@ -888,25 +886,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } return true; - -#else - switch (access_type) { - case MMU_INST_FETCH: - cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; - break; - case MMU_DATA_LOAD: - cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; - break; - case MMU_DATA_STORE: - cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; - break; - default: - g_assert_not_reached(); - } - env->badaddr = address; - cpu_loop_exit_restore(cs, retaddr); -#endif } +#endif /* !CONFIG_USER_ONLY */ /* * Handle Traps From patchwork Fri Oct 1 17:11:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515099 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1028348jaf; Fri, 1 Oct 2021 10:53:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxlhTmSIvi5sMrFPBNVXxrBoY2lahsI9dDYog7XWTg06+v19pnpaIQoU/SXFwfOguLjtJX3 X-Received: by 2002:a67:fe4f:: with SMTP id m15mr5606626vsr.2.1633110795241; Fri, 01 Oct 2021 10:53:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633110795; cv=none; d=google.com; s=arc-20160816; b=RT3nN/Ovy87EJ34pb2HvVtkKnhtVgZOBml3CM/iaLahudoIoBZa5NnzbJEXucdLscu FCbs8Lw42+4iByitwvzhR4TB6c439rWDGD89MRxM4ey74749KELVRSnHLBOjChdKCErA BeL6Bx3tdD96kjR9LKW4LmPNYIl1fVQaHK6bfe2esUpw7nQpc0H4qv5TUORJFHyGDeOD KwawBVQ5FihyPsgTrZJ7aj5R2f4+Lz+QFidoZvpX8zQmb5XZzUi80TchlNJ90BF5RkJQ pu7DTxV1TyH3C+zUrxBrABZxdlVNz/UzHzUbauGdu6meBYqcCxoFY670mQ1ymrV0Je9n r/YQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ed7k7oV00Ud53qqbt9Yos8IyOCfVvxLg7PyS2NKYTH0=; b=OJD+p1bhnnlAV5Po/y95uLbX07iXUt2yK84PemjXuDRjc7+zSypUjbWYA9qtnSqCQb OYd6+bcC6S9+jYAq1Kvkzz+dlD4Lm48P8YN3GoZYKCkeVvdlI9X9kFDQUdlZezUpIIHK mITW5pINThGarCOS9PeSuXRyZ+7m6+rKAxC6LeD2OGrn3Lfh69b+L2knR3YcDU+SQRMh 2Vc9dRta/vKJ+gdsUXjRKG4/QBbuUJ9IJUi6BQ8thD9CVSpopBLCWMeJ97FCfkOK8ARo YOwsfRQUGhIpF/R0srs1HWa5KC2cYjhyFlz48Pf8JWtYVLBLQrea/FaSt0kuj0yHVLMN UDIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YqPuSya7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 36/41] target/s390x: Use probe_access_flags in s390_probe_access Date: Fri, 1 Oct 2021 13:11:46 -0400 Message-Id: <20211001171151.1739472-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2e; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2e.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Not sure why the user-only code wasn't rewritten to use probe_access_flags at the same time that the sysemu code was converted. For the purpose of user-only, this is an exact replacement. Cc: qemu-s390x@nongnu.org Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 0bf775a37d..596270e45d 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -142,20 +142,12 @@ static int s390_probe_access(CPUArchState *env, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t ra) { +#if defined(CONFIG_USER_ONLY) + return probe_access_flags(env, addr, access_type, mmu_idx, + nonfault, phost, ra); +#else int flags; -#if defined(CONFIG_USER_ONLY) - flags = page_get_flags(addr); - if (!(flags & (access_type == MMU_DATA_LOAD ? PAGE_READ : PAGE_WRITE_ORG))) { - env->__excp_addr = addr; - flags = (flags & PAGE_VALID) ? PGM_PROTECTION : PGM_ADDRESSING; - if (nonfault) { - return flags; - } - tcg_s390_program_interrupt(env, flags, ra); - } - *phost = g2h(env_cpu(env), addr); -#else /* * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr==NULL * to detect if there was an exception during tlb_fill(). @@ -174,8 +166,8 @@ static int s390_probe_access(CPUArchState *env, target_ulong addr, int size, (access_type == MMU_DATA_STORE ? BP_MEM_WRITE : BP_MEM_READ), ra); } -#endif return 0; +#endif } static int access_prepare_nf(S390Access *access, CPUS390XState *env, From patchwork Fri Oct 1 17:11:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515104 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1032028jaf; Fri, 1 Oct 2021 10:58:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJygvUJiphZylmk7jB8F5Igf10h6bPBEL59C5GVluTQG2V+C6e4x6u+rENvS51ueqT+kXh8D X-Received: by 2002:a37:4656:: with SMTP id t83mr10684278qka.207.1633111113576; Fri, 01 Oct 2021 10:58:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633111113; cv=none; d=google.com; s=arc-20160816; b=B75vLJurTpjea5ECdI9hdMuclrGrwPyoFtGQsW8pOaqpKnqrXioKvzpBD9MYUwei7q JIUjLlcd+EsPOgkjob0RZtBCQtSb2SdZX5XMsa2vqFuNn/7y0ESza7G/9vGiHMQIyR1b PlKboc/jRmZxqPDg96c6QvE36vj/NiUqLCQQa9oeEpmLRgOZ1n3k/zFWN2Iqdl+t6g25 BLee63zzZO6QEeO/9eLYBBP6+XFmOmlA5VvSyMnSU2fV+TDaagnFPYkuW1NePSn6IcNL ggOBk7+J6QmX8q5YTLCdyvAZ9rLNrGEAPZWtAwIOwBDe8WVoDVhCmXsnSyN7HFZ5Fi/x wteg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jEmAGke+Q2SF6dInMRgXkKJGhuJtK6GWTLvXnPINEiA=; b=EYEjAYuXa4JmzZ0ea7wsdcHdxQIZy1hPqhSEuYjkl0OvCpYQe2ZR8Mpepka8+KiSxi ySixQa0gP3Ykc6ZDvpH5I4bujPGA816byNhDHNanT8Epb+mLv6g9zrrDl667wW8V6XCv F68q26RmW+7jqYqR7dusWJoF5DYxQnz/tSLZBqXqcnXDZfyX2KSmogyWaCJXpf/q+GFS a8oqcXqjQsfY29CdnieAXxnbawwKi+pqCn1dxMHFhfhm4MPwlObiEDo84P25xUS7d0t6 GLyF1RrBgNvP2p2upzuSA1CmWJjPjYb/G/65bWXbHHQfntagJ0cOHkKXXdtmvPIEJNIF I5JA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=g22jRRh5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 37/41] target/s390x: Implement s390_cpu_record_sigsegv Date: Fri, 1 Oct 2021 13:11:47 -0400 Message-Id: <20211001171151.1739472-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82e; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82e.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, alex.bennee@linaro.org, laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the masking of the address from cpu_loop into s390_cpu_record_sigsegv -- this is governed by hw, not linux. This does mean we have to raise our own exception, rather than return to the fallback. Use maperr to choose between PGM_PROTECTION and PGM_ADDRESSING. Use the appropriate si_code for each in cpu_loop. Cc: qemu-s390x@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/s390x-internal.h | 13 ++++++++++--- linux-user/s390x/cpu_loop.c | 13 ++++++------- target/s390x/cpu.c | 6 ++++-- target/s390x/tcg/excp_helper.c | 18 +++++++++++------- 4 files changed, 31 insertions(+), 19 deletions(-) -- 2.25.1 diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 27d4a03ca1..163aa4f94a 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -270,13 +270,20 @@ ObjectClass *s390_cpu_class_by_name(const char *name); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; +#ifdef CONFIG_USER_ONLY +void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr); +#else +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#endif + /* fpu_helper.c */ uint32_t set_cc_nz_f32(float32 v); diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c index 69b69981f6..d089c8417e 100644 --- a/linux-user/s390x/cpu_loop.c +++ b/linux-user/s390x/cpu_loop.c @@ -24,8 +24,6 @@ #include "cpu_loop-common.h" #include "signal-common.h" -/* s390x masks the fault address it reports in si_addr for SIGSEGV and SIGBUS */ -#define S390X_FAIL_ADDR_MASK -4096LL static int get_pgm_data_si_code(int dxc_code) { @@ -111,12 +109,13 @@ void cpu_loop(CPUS390XState *env) n = TARGET_ILL_ILLOPC; goto do_signal_pc; case PGM_PROTECTION: + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_ACCERR, + env->__excp_addr); + break; case PGM_ADDRESSING: - sig = TARGET_SIGSEGV; - /* XXX: check env->error_code */ - n = TARGET_SEGV_MAPERR; - addr = env->__excp_addr & S390X_FAIL_ADDR_MASK; - goto do_signal; + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, + env->__excp_addr); + break; case PGM_EXECUTE: case PGM_SPECIFICATION: case PGM_SPECIAL_OP: diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7b7b05f1d3..593dda75c4 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -266,9 +266,11 @@ static void s390_cpu_reset_full(DeviceState *dev) static const struct TCGCPUOps s390_tcg_ops = { .initialize = s390x_translate_init, - .tlb_fill = s390_cpu_tlb_fill, -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv = s390_cpu_record_sigsegv, +#else + .tlb_fill = s390_cpu_tlb_fill, .cpu_exec_interrupt = s390_cpu_exec_interrupt, .do_interrupt = s390_cpu_do_interrupt, .debug_excp_handler = s390x_cpu_debug_excp_handler, diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 3d6662a53c..b923d080fc 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -89,16 +89,20 @@ void s390_cpu_do_interrupt(CPUState *cs) cs->exception_index = -1; } -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { S390CPU *cpu = S390_CPU(cs); - trigger_pgm_exception(&cpu->env, PGM_ADDRESSING); - /* On real machines this value is dropped into LowMem. Since this - is userland, simply put this someplace that cpu_loop can find it. */ - cpu->env.__excp_addr = address; + trigger_pgm_exception(&cpu->env, maperr ? PGM_ADDRESSING : PGM_PROTECTION); + /* + * On real machines this value is dropped into LowMem. Since this + * is userland, simply put this someplace that cpu_loop can find it. + * S390 only gives the page of the fault, not the exact address. + * C.f. the construction of TEC in mmu_translate(). + */ + cpu->env.__excp_addr = address & TARGET_PAGE_MASK; cpu_loop_exit_restore(cs, retaddr); } From patchwork Fri Oct 1 17:11:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515091 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1023492jaf; Fri, 1 Oct 2021 10:46:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw2ER3FPyl2atkajpim62GL4X0KTydsYw7rw2hgXxTqONjpHhj6XaxvMfyN3/Wqeq5N957W X-Received: by 2002:a05:6102:f08:: with SMTP id v8mr5444793vss.60.1633110411773; Fri, 01 Oct 2021 10:46:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633110411; cv=none; d=google.com; s=arc-20160816; b=qtyNEHmsBymB8xh2nctWsQcjGj2yp6l9uj/EXc2MxNG216k4BYl8LJvMQ5XM80WGrI rpBK4KZYM89zyPtWsY6dW4nY1TFsCG7xiyvCZJRAc9uhx5MjMOmhDXyuSfBZnPdYs52w KkYtymQN5Q8KCv6EO8R4sxDrMRzQfj8gnLSYUOnWGOrkfSNxufEzaTCIHahSJBp7WVjV jcByEG0EiDJb7kLZGPzEDYXpBZt/C8kEjKBI2EY1jdVVWdIXvgQPUPuD3yMKiALT5eCo 09GTUcWXQMR7mWUNw++7WRPuORPFEAsvDL351zaKVjXMMrxNDmSz3NxxcPyXzZo9/9kd e64w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QnIuy+UNML3N+Vecxph501fC1v8l7RElAhe1SJhJNCk=; b=VBEYf1vrEEluoSgHN+j8/sdqe/IWN+4OzSe7uwh3ffurpCPupc4bv7F+9n1I5wjkiT PAYjpvOOQWvrNJRlN3CVF4SfrBZD0mg1oUcDAXrENyvN4Fhwr37zLM5Q9eZjvDgS6AAh Ou0lvlPJHk5wKpjU3FHzxy6YNKMF9abNCVJcMNzmfCgMtaRbbWV+a+WqMCysCN08cm6Y pB6oL/76dQX1d1SLf4L6DKxn2mXG0vJC84I0BoROL2eMMYCgAnQYIn3J6VUmbVskvdmt AI+a53sWWdXDrRuXppWuV+A8+CiQ8nKP2cnkqXgGUP0hGFYm+XZw8efdJzNdvEZJGUSe /vng== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rB07Vx0y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 38/41] target/sh4: Make sh4_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:48 -0400 Message-Id: <20211001171151.1739472-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2c; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, Yoshinori Sato Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for sh4. Remove the code from cpu_loop that raised SIGSEGV. Cc: Yoshinori Sato Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 6 +++--- linux-user/sh4/cpu_loop.c | 8 -------- target/sh4/cpu.c | 2 +- target/sh4/helper.c | 9 +-------- 4 files changed, 5 insertions(+), 20 deletions(-) -- 2.25.1 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index dc81406646..4cfb109f56 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -213,12 +213,12 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, uintptr_t retaddr) QEMU_NORETURN; void sh4_translate_init(void); +void sh4_cpu_list(void); + +#if !defined(CONFIG_USER_ONLY) bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); - -void sh4_cpu_list(void); -#if !defined(CONFIG_USER_ONLY) void superh_cpu_do_interrupt(CPUState *cpu); bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); void cpu_sh4_invalidate_tlb(CPUSH4State *s); diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c index 65b8972e3c..ac9b01840c 100644 --- a/linux-user/sh4/cpu_loop.c +++ b/linux-user/sh4/cpu_loop.c @@ -65,14 +65,6 @@ void cpu_loop(CPUSH4State *env) info.si_code = TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case 0xa0: - case 0xc0: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->tea; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); arch_interrupt = false; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 2047742d03..06b2691dc4 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -236,9 +236,9 @@ static const struct SysemuCPUOps sh4_sysemu_ops = { static const struct TCGCPUOps superh_tcg_ops = { .initialize = sh4_translate_init, .synchronize_from_tb = superh_cpu_synchronize_from_tb, - .tlb_fill = superh_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = superh_cpu_tlb_fill, .cpu_exec_interrupt = superh_cpu_exec_interrupt, .do_interrupt = superh_cpu_do_interrupt, .do_unaligned_access = superh_cpu_do_unaligned_access, diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 53cb9c3b63..6a620e36fc 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -796,8 +796,6 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } -#endif /* !CONFIG_USER_ONLY */ - bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -806,11 +804,6 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, CPUSH4State *env = &cpu->env; int ret; -#ifdef CONFIG_USER_ONLY - ret = (access_type == MMU_DATA_STORE ? MMU_DTLB_VIOLATION_WRITE : - access_type == MMU_INST_FETCH ? MMU_ITLB_VIOLATION : - MMU_DTLB_VIOLATION_READ); -#else target_ulong physical; int prot; @@ -829,7 +822,6 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) { env->pteh = (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_MASK); } -#endif env->tea = address; switch (ret) { @@ -868,3 +860,4 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } cpu_loop_exit_restore(cs, retaddr); } +#endif /* !CONFIG_USER_ONLY */ From patchwork Fri Oct 1 17:11:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515096 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1026197jaf; Fri, 1 Oct 2021 10:50:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxpmAfZI/yCErXUmR6BSH6ZMZH5GKt+DfI+eoZ0lbZURL6aAtP+f4qyrQyXYLWLFUtbuvuj X-Received: by 2002:a05:6102:21d0:: with SMTP id r16mr5615083vsg.39.1633110633209; Fri, 01 Oct 2021 10:50:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633110633; cv=none; d=google.com; s=arc-20160816; b=dkpAaBbGRBAhQJZYE+CPFr5+pFB7MOH9bh+e3lFs+ywjF34xI3ychUIs6whYsD0qWp 5h0fZKzTgqi59QcBdimEaVYwqXDO99Llyg9ZWIngkJxSFlgs5S+vXGUS49L82aVkWPbh vIZGzJEaT/GRYM/zKEJyn7BLrpZlJL+bPQ4zcFV2N74wFaHs82K2hukD0kSnKhpKvixQ DtPe1hlLZor+9k09t/NN3bjx24bZ3MQILegcWqRgmHlWg0RIsogQdd9iY7Tvr7ZvPRZs ApurHECUBLctBoe2/9kxIy4D4qaRkHyXspcK9HjO5QqMVPdYPKNb1loqEywVd0J8O+d1 bsig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Kxx36+JaRB0XOezqbrSvE6VIGRNmwbnwHPsqVvcTcY0=; b=gNhVYhSGHgHFnMwmEtkOKdechYwm9ZF74SyO0bLpo4oumKXBFJzX75JFKeBZJl3E5X mxmzl62GOUi/2SIRHmUBkBVDF+ReLy/fGFPzmz3HcaZbzvddiqIng98TG1hr4oqlP26z Gz5+0aX5PKkqmpdOqhynUc5M9GiaCplxEbFhU+PxcMWKqLfazYG+eLZiyLTOsKbUl1ZZ ZQZKBEtkXFQXit/JDzkylIa1ScnFwNnX/vwaZk6cm/sNxBpLyx0xhJCvpPoB4egeM+yg K9iuoaYcwNbgSWpPS4QoNbTgX0OG18GTKKh3w8xk1uMatfHFkMdLpnmYe6qnekiUXDn8 ejKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FGUKBeAU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id y15sm3557250qko.78.2021.10.01.10.12.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:12:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 39/41] target/sparc: Make sparc_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:49 -0400 Message-Id: <20211001171151.1739472-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::836; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x836.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for sparc. This makes all of the code in mmu_helper.c sysemu only, so remove the ifdefs and move the file to sparc_softmmu_ss. Remove the code from cpu_loop that handled TT_DFAULT and TT_TFAULT. Cc: Mark Cave-Ayland Signed-off-by: Richard Henderson --- linux-user/sparc/cpu_loop.c | 25 ------------------------- target/sparc/cpu.c | 2 +- target/sparc/mmu_helper.c | 25 ------------------------- target/sparc/meson.build | 2 +- 4 files changed, 2 insertions(+), 52 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index ad29b4eb6a..0ba65e431c 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -219,17 +219,6 @@ void cpu_loop (CPUSPARCState *env) case TT_WIN_UNF: /* window underflow */ restore_window(env); break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->mmuregs[4]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; #else case TT_SPILL: /* window overflow */ save_window(env); @@ -237,20 +226,6 @@ void cpu_loop (CPUSPARCState *env) case TT_FILL: /* window underflow */ restore_window(env); break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - if (trapnr == TT_DFAULT) - info._sifields._sigfault._addr = env->dmmu.mmuregs[4]; - else - info._sifields._sigfault._addr = cpu_tsptr(env)->tpc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; #ifndef TARGET_ABI32 case 0x16e: flush_windows(env); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 21dd27796d..55268ed2a1 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -865,9 +865,9 @@ static const struct SysemuCPUOps sparc_sysemu_ops = { static const struct TCGCPUOps sparc_tcg_ops = { .initialize = sparc_tcg_init, .synchronize_from_tb = sparc_cpu_synchronize_from_tb, - .tlb_fill = sparc_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = sparc_cpu_tlb_fill, .cpu_exec_interrupt = sparc_cpu_exec_interrupt, .do_interrupt = sparc_cpu_do_interrupt, .do_transaction_failed = sparc_cpu_do_transaction_failed, diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index a44473a1c7..2ad47391d0 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -25,30 +25,6 @@ /* Sparc MMU emulation */ -#if defined(CONFIG_USER_ONLY) - -bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - - if (access_type == MMU_INST_FETCH) { - cs->exception_index = TT_TFAULT; - } else { - cs->exception_index = TT_DFAULT; -#ifdef TARGET_SPARC64 - env->dmmu.mmuregs[4] = address; -#else - env->mmuregs[4] = address; -#endif - } - cpu_loop_exit_restore(cs, retaddr); -} - -#else - #ifndef TARGET_SPARC64 /* * Sparc V8 Reference MMU (SRMMU) @@ -926,4 +902,3 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } return phys_addr; } -#endif diff --git a/target/sparc/meson.build b/target/sparc/meson.build index a3638b9503..a801802ee2 100644 --- a/target/sparc/meson.build +++ b/target/sparc/meson.build @@ -6,7 +6,6 @@ sparc_ss.add(files( 'gdbstub.c', 'helper.c', 'ldst_helper.c', - 'mmu_helper.c', 'translate.c', 'win_helper.c', )) @@ -16,6 +15,7 @@ sparc_ss.add(when: 'TARGET_SPARC64', if_true: files('int64_helper.c', 'vis_helpe sparc_softmmu_ss = ss.source_set() sparc_softmmu_ss.add(files( 'machine.c', + 'mmu_helper.c', 'monitor.c', )) From patchwork Fri Oct 1 17:11:50 2021 Content-Type: text/plain; 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id l5sm3697516qtq.4.2021.10.01.10.15.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:15:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 40/41] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only Date: Fri, 1 Oct 2021 13:11:50 -0400 Message-Id: <20211001171151.1739472-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::833; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x833.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for xtensa. Remove the code from cpu_loop that raised SIGSEGV. Cc: Max Filippov Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 2 +- linux-user/xtensa/cpu_loop.c | 9 --------- target/xtensa/cpu.c | 2 +- target/xtensa/helper.c | 22 +--------------------- 4 files changed, 3 insertions(+), 32 deletions(-) -- 2.25.1 Acked-by: Max Filippov Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index f9a510ca46..02143f2f77 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -563,10 +563,10 @@ struct XtensaCPU { }; +#ifndef CONFIG_USER_ONLY bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c index 622afbcd34..a83490ab35 100644 --- a/linux-user/xtensa/cpu_loop.c +++ b/linux-user/xtensa/cpu_loop.c @@ -226,15 +226,6 @@ void cpu_loop(CPUXtensaState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case LOAD_PROHIBITED_CAUSE: - case STORE_PROHIBITED_CAUSE: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr = env->sregs[EXCVADDR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - default: fprintf(stderr, "exccause = %d\n", env->sregs[EXCCAUSE]); g_assert_not_reached(); diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c1cbd03595..224f723236 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -192,10 +192,10 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = { static const struct TCGCPUOps xtensa_tcg_ops = { .initialize = xtensa_translate_init, - .tlb_fill = xtensa_cpu_tlb_fill, .debug_excp_handler = xtensa_breakpoint_handler, #ifndef CONFIG_USER_ONLY + .tlb_fill = xtensa_cpu_tlb_fill, .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, .do_interrupt = xtensa_cpu_do_interrupt, .do_transaction_failed = xtensa_cpu_do_transaction_failed, diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f18ab383fd..29d216ec1b 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -242,27 +242,7 @@ void xtensa_cpu_list(void) } } -#ifdef CONFIG_USER_ONLY - -bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; - - qemu_log_mask(CPU_LOG_INT, - "%s: rw = %d, address = 0x%08" VADDR_PRIx ", size = %d\n", - __func__, access_type, address, size); - env->sregs[EXCVADDR] = address; - env->sregs[EXCCAUSE] = (access_type == MMU_DATA_STORE ? - STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE); - cs->exception_index = EXC_USER; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - +#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) From patchwork Fri Oct 1 17:11:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515101 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp1028892jaf; Fri, 1 Oct 2021 10:54:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwFPQFeZfo8HUcyV8xhDeK94nHOEW/O7ISizvAP1Uyhu2BE0Wbx3OIAlMAe/mbs2JC58JiV X-Received: by 2002:a67:e157:: with SMTP id o23mr947836vsl.25.1633110846950; Fri, 01 Oct 2021 10:54:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633110846; cv=none; d=google.com; s=arc-20160816; b=rXC7f6hyOgdqbYtCEohFcRwbK/yf8lX72UmJmUSGNxnXNhBSpyXvaT13BfivI21iii idwdZ1Uzt4mPNh0iXs1RixkOth8Inyv2Nzb/34ZnyATWXvjN4t6OY5tdGaNEJoDzB1FS WcpLlUdol+kpeebuq9if9fQorUXhC9bwksDbcB7ba5UI7VITERjCVhHyNzx0VbSvSz42 VJdo4qxAkR5O2wliBgUaqK0igLYpV1Rv6y/aIBnm6pOWezbtJPmVI8KTUkTekqd+ar8F lH8Omh/JYlnbFVungWoz45sJFMQxXudb4uD3sPir57CaMicV3bLMueJ+LVw34ey+o91G 84Pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iPL+UEtKoL8lJ1cyR3L2m8ieOZFTWfsG23UG08w8UQA=; b=k4iMm3KSLAXNaprlWikFhmMmVCLNzC4qsXV/P5KWiLO8n8mtqvASyWTqspsw2NOjlc l7fZlvxxWfK0F2Iixn1C+jXnq61wMVFWppuVFIMMo6WzAZDWdGrEAFRGqVfdnSKS6l1f y5+U9Ln7UntgFAf+lChhfn8fg8lQVYOT7oV0aJ4y9+4+nmb36pyWj70mlZ7oRyzGNmfh Rz4LbJCfTQEXqMKurzMt52B5OWzRFz8Z334Wbkt2FntfIuEjyl9rXlKpVamuFreMzo+x Uv11+tBfU1fwRWMA4A6KL7+i9smDPerUezwDCog5HDThPrTvN4/bM8E+WM9VEBz77clu Nh4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=lAPempVc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.174.166.185]) by smtp.gmail.com with ESMTPSA id l5sm3697516qtq.4.2021.10.01.10.15.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 10:15:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 41/41] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Date: Fri, 1 Oct 2021 13:11:51 -0400 Message-Id: <20211001171151.1739472-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org> References: <20211001171151.1739472-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x834.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have replaced tlb_fill with record_sigsegv for user mod. Move the declaration to restrict it to system emulation. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 22 ++++++++++------------ linux-user/signal.c | 3 --- 2 files changed, 10 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 41718b695b..8eadd404c8 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -35,18 +35,6 @@ struct TCGCPUOps { void (*cpu_exec_enter)(CPUState *cpu); /** @cpu_exec_exit: Callback for cpu_exec cleanup */ void (*cpu_exec_exit)(CPUState *cpu); - /** - * @tlb_fill: Handle a softmmu tlb miss or user-only address fault - * - * For system mode, if the access is valid, call tlb_set_page - * and return true; if the access is invalid, and probe is - * true, return false; otherwise raise an exception and do - * not return. For user-only mode, always raise an exception - * and do not return. - */ - bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); /** @debug_excp_handler: Callback for handling debug exceptions */ void (*debug_excp_handler)(CPUState *cpu); @@ -68,6 +56,16 @@ struct TCGCPUOps { #ifdef CONFIG_SOFTMMU /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** + * @tlb_fill: Handle a softmmu tlb miss + * + * If the access is valid, call tlb_set_page and return true; + * if the access is invalid and probe is true, return false; + * otherwise raise an exception and do not return. + */ + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); /** * @do_transaction_failed: Callback for handling failed memory transactions * (ie bus faults or external aborts; not MMU faults) diff --git a/linux-user/signal.c b/linux-user/signal.c index 8c22f711f1..d32bc5e1e5 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -694,9 +694,6 @@ void cpu_loop_exit_segv(CPUState *cpu, target_ulong addr, if (tcg_ops->record_sigsegv) { tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); - } else if (tcg_ops->tlb_fill) { - tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, ra); - g_assert_not_reached(); } force_sig_fault(TARGET_SIGSEGV,