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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id k6sm727416otf.80.2021.09.30.11.19.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 11:19:24 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Rob Herring , Frank Rowand Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Lew , Deepak Kumar Singh Subject: [PATCH v2 1/4] dt-bindings: sram: Document qcom,rpm-msg-ram Date: Thu, 30 Sep 2021 11:21:08 -0700 Message-Id: <20210930182111.57353-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210930182111.57353-1-bjorn.andersson@linaro.org> References: <20210930182111.57353-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Qualcomm SMEM binding always depended on a reference to a SRAM node of compatible "qcom,rpm-msg-ram", document this as part of the SRAM binding. The SRAM is consumed as a whole and not split up using subnodes, so properties related to this are not required. Signed-off-by: Bjorn Andersson --- Changes since v1: - New patch, to resolve issue with the existing qcom,smem example Documentation/devicetree/bindings/sram/sram.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.29.2 Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index 3eda5049d183..e3311b54db33 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -31,6 +31,7 @@ properties: - amlogic,meson-gxbb-sram - arm,juno-sram-ns - atmel,sama5d2-securam + - qcom,rpm-msg-ram - rockchip,rk3288-pmu-sram reg: @@ -135,7 +136,9 @@ if: properties: compatible: contains: - const: rockchip,rk3288-pmu-sram + enum: + - qcom,rpm-msg-ram + - rockchip,rk3288-pmu-sram else: required: From patchwork Thu Sep 30 18:21:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 514967 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp39417jaf; Thu, 30 Sep 2021 11:19:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxg16FCex/WRmzWgQLPf33XKt1c0YIUBr9nOPXwMvvm009MSBnlzO/i4QIRfTmkLPjerhxa X-Received: by 2002:a50:be8f:: with SMTP id b15mr8687450edk.200.1633025992725; Thu, 30 Sep 2021 11:19:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633025992; cv=none; d=google.com; s=arc-20160816; b=o6lu7UKOkFYoMJaC+gs8VVajWiIDa4DLn1xjmlSuZn6tOpeNdGal1dRPZfegA/xnN+ pHZvYM2nSsDagJ6o2YFFD8qHWqhggEkQS5Uzb1G+dupBqO3HR5eSCLeNV9YaU6x2Kn6J zo1q5kgSRmlTNnGSoVcCZCr1BYYuJnQ+RMdiyn79ESUtVaMW2SUG1e6GdUTf/zT998QB 3g9FS8NGEv8tE9c6MhvqmmiQ553aEBp8Ax3pzb0VnFQNX6V1pvDF6frOxlA/fe+nNcLe 4AK1fnQTY9cw568BgnZQXFWIAAifdFhR9Ncef3B5RyGhRguoWGR0UXkxpqXHcTdPJvJN Tisg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=I3QEbxt5uEHrOmXC8KCrrnLxWzCqzAmWjkibzCAclE4=; b=epWF6wZ5OBELs8T3R6d+ZCK9523Nt/Z1ynWPJSlunE2wWImXAHpte8yvRfLUtLUY9z j9E81aATp+Hb9EFa7QlE0U4cjrN6XGcbidNzvHeO6lDrbv3ZMYecgBjegK3h4ciCbZ4e /9p3hqh0tSvIVQCoENhWQfwzwurdZRgmyKXNdu4FKs5lz5HNxXKyI0t57czNgWiRHy72 rN3HvYABSdNKJgsE/V6bIz2jtD9a2LVhVEpmvl6S+DIXYi75Rh2ghtL8vIE7cn66XZ+R XJLvj5uumZY1TsVvvZiocObg7Vvjm3HikuhYGjoB2/fJZt5FXQhSkUcXxaAn9Nr1vFZN nv8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MXtkO4ZL; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id k6sm727416otf.80.2021.09.30.11.19.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 11:19:25 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Rob Herring , Frank Rowand Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Lew , Deepak Kumar Singh Subject: [PATCH v2 2/4] dt-bindings: soc: smem: Make indirection optional Date: Thu, 30 Sep 2021 11:21:09 -0700 Message-Id: <20210930182111.57353-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210930182111.57353-1-bjorn.andersson@linaro.org> References: <20210930182111.57353-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the olden days the Qualcomm shared memory (SMEM) region consisted of multiple chunks of memory, so SMEM was described as a standalone node with references to its various memory regions. But practically all modern Qualcomm platforms has a single reserved memory region used for SMEM. So rather than having to use two nodes to describe the one SMEM region, update the binding to allow the reserved-memory region alone to describe SMEM. The olden format is preserved as valid, as this is widely used already. Signed-off-by: Bjorn Andersson --- Changes since v1: - None .../bindings/soc/qcom/qcom,smem.yaml | 34 ++++++++++++++++--- 1 file changed, 30 insertions(+), 4 deletions(-) -- 2.29.2 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smem.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smem.yaml index f7e17713b3d8..4149cf2b66be 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smem.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smem.yaml @@ -10,14 +10,18 @@ maintainers: - Andy Gross - Bjorn Andersson -description: | - This binding describes the Qualcomm Shared Memory Manager, used to share data - between various subsystems and OSes in Qualcomm platforms. +description: + This binding describes the Qualcomm Shared Memory Manager, a region of + reserved-memory used to share data between various subsystems and OSes in + Qualcomm platforms. properties: compatible: const: qcom,smem + reg: + maxItems: 1 + memory-region: maxItems: 1 description: handle to memory reservation for main SMEM memory region. @@ -29,11 +33,19 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: handle to RPM message memory resource + no-map: true + required: - compatible - - memory-region - hwlocks +oneOf: + - required: + - reg + - no-map + - required: + - memory-region + additionalProperties: false examples: @@ -43,6 +55,20 @@ examples: #size-cells = <1>; ranges; + smem@fa00000 { + compatible = "qcom,smem"; + reg = <0xfa00000 0x200000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + }; + }; + - | + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + smem_region: smem@fa00000 { reg = <0xfa00000 0x200000>; no-map; From patchwork Thu Sep 30 18:21:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 514968 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp39518jaf; Thu, 30 Sep 2021 11:20:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzFbWUDTNc7SOHw7wuKKsSdzqvsCYNEon6cY8ZZedeWtD+ysQiWL+4IPP+nqJ1QUaVLXqIu X-Received: by 2002:a17:906:5a97:: with SMTP id l23mr738221ejq.541.1633026002344; Thu, 30 Sep 2021 11:20:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633026002; cv=none; d=google.com; s=arc-20160816; b=WS0lkolODvFpbdlwlSbOG5jnTdyj/6uhlpvdsUcYjryuOeK+uA7OT9KwMIPRmle5Dc 7/7HRP4e66PLzoYHC2b1KX64RUkMPSL0PpPGW76TPkce05E3As0L+AyM3u/id0o5VVoH 0j9tLE7CmlCkNemhB4PHsa51DdYKL0NZddDZOLQjiToVHMOndHmZn0bGdry0Nuhx87tt 9MxFjfPmlOujdxCDqm/+VmE3x2XnH3cB0xasCS3twQ/iFbuc4vzTGde97aothiVuh9Yk SrUCCxjv83iuJVljE45aJmdQVcUo4UoGS6Om8MLXsx3RYbOixvWbjVqm6UwB4XjGlCbC AqZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=aMZ/AgEZ1ehZjKbP09jYtyKIb6Gw+NFrOG75sO7xPMo=; b=obFSf4C8JoGhgkvAfz+fE/AyzCoeOji+5gRAM94Xj4hlWX7dPqljKM8dM4Ip3ApDXH Fk8tMwYrBHA6TwsCQAwQdUmBTNHE0T0ilvFjZN84I+XL/w/BvUGAN2HlikGAXTT+Hts+ MyzDvhfZvxrIhdeFozLbEXvD0d02vADnfbjOQ6UA+s1dbRAIvWDNnF5i3t1PsKfPhIop 0TZz0uQsDuWbSLP+r/szvwUxNSnUznIWpol7/5pQCxcZmUiXzb5Xeui8jjGcIm8Hj/rs tE+n9OuO6UC5lzyFgKOGZfqP/Jt+ObcQOoslFEYeK/mh4QXDdgghJgQKWp++Q0TXUi3Q 99YA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mUzV8g4W; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id k6sm727416otf.80.2021.09.30.11.19.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 11:19:25 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Rob Herring , Frank Rowand Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Lew , Deepak Kumar Singh Subject: [PATCH v2 3/4] soc: qcom: smem: Support reserved-memory description Date: Thu, 30 Sep 2021 11:21:10 -0700 Message-Id: <20210930182111.57353-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210930182111.57353-1-bjorn.andersson@linaro.org> References: <20210930182111.57353-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Practically all modern Qualcomm platforms has a single reserved-memory region for SMEM. So rather than having to describe SMEM in the form of a node with a reference to a reserved-memory node, allow the SMEM device to be instantiated directly from the reserved-memory node. The current means of falling back to dereferencing the "memory-region" is kept as a fallback, if it's determined that the SMEM node is a reserved-memory node. The "qcom,smem" compatible is added to the reserved_mem_matches list, to allow the reserved-memory device to be probed. In order to retain the readability of the code, the resolution of resources is split from the actual ioremapping. Signed-off-by: Bjorn Andersson --- Changes since v1: - None drivers/of/platform.c | 1 + drivers/soc/qcom/smem.c | 57 ++++++++++++++++++++++++++++------------- 2 files changed, 40 insertions(+), 18 deletions(-) -- 2.29.2 Acked-by: Rob Herring diff --git a/drivers/of/platform.c b/drivers/of/platform.c index 32d5ff8df747..07813fb1ef37 100644 --- a/drivers/of/platform.c +++ b/drivers/of/platform.c @@ -505,6 +505,7 @@ EXPORT_SYMBOL_GPL(of_platform_default_populate); static const struct of_device_id reserved_mem_matches[] = { { .compatible = "qcom,rmtfs-mem" }, { .compatible = "qcom,cmd-db" }, + { .compatible = "qcom,smem" }, { .compatible = "ramoops" }, { .compatible = "nvmem-rmem" }, {} diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 4fb5aeeb0843..c7e519bfdc8a 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -240,7 +241,7 @@ static const u8 SMEM_INFO_MAGIC[] = { 0x53, 0x49, 0x49, 0x49 }; /* SIII */ * @size: size of the memory region */ struct smem_region { - u32 aux_base; + phys_addr_t aux_base; void __iomem *virt_base; size_t size; }; @@ -499,7 +500,7 @@ static void *qcom_smem_get_global(struct qcom_smem *smem, for (i = 0; i < smem->num_regions; i++) { region = &smem->regions[i]; - if (region->aux_base == aux_base || !aux_base) { + if ((u32)region->aux_base == aux_base || !aux_base) { if (size != NULL) *size = le32_to_cpu(entry->size); return region->virt_base + le32_to_cpu(entry->offset); @@ -664,7 +665,7 @@ phys_addr_t qcom_smem_virt_to_phys(void *p) if (p < region->virt_base + region->size) { u64 offset = p - region->virt_base; - return (phys_addr_t)region->aux_base + offset; + return region->aux_base + offset; } } @@ -863,12 +864,12 @@ qcom_smem_enumerate_partitions(struct qcom_smem *smem, u16 local_host) return 0; } -static int qcom_smem_map_memory(struct qcom_smem *smem, struct device *dev, - const char *name, int i) +static int qcom_smem_resolve_mem(struct qcom_smem *smem, const char *name, + struct smem_region *region) { + struct device *dev = smem->dev; struct device_node *np; struct resource r; - resource_size_t size; int ret; np = of_parse_phandle(dev->of_node, name, 0); @@ -881,13 +882,9 @@ static int qcom_smem_map_memory(struct qcom_smem *smem, struct device *dev, of_node_put(np); if (ret) return ret; - size = resource_size(&r); - smem->regions[i].virt_base = devm_ioremap_wc(dev, r.start, size); - if (!smem->regions[i].virt_base) - return -ENOMEM; - smem->regions[i].aux_base = (u32)r.start; - smem->regions[i].size = size; + region->aux_base = r.start; + region->size = resource_size(&r); return 0; } @@ -895,12 +892,14 @@ static int qcom_smem_map_memory(struct qcom_smem *smem, struct device *dev, static int qcom_smem_probe(struct platform_device *pdev) { struct smem_header *header; + struct reserved_mem *rmem; struct qcom_smem *smem; size_t array_size; int num_regions; int hwlock_id; u32 version; int ret; + int i; num_regions = 1; if (of_find_property(pdev->dev.of_node, "qcom,rpm-msg-ram", NULL)) @@ -914,13 +913,35 @@ static int qcom_smem_probe(struct platform_device *pdev) smem->dev = &pdev->dev; smem->num_regions = num_regions; - ret = qcom_smem_map_memory(smem, &pdev->dev, "memory-region", 0); - if (ret) - return ret; + rmem = of_reserved_mem_lookup(pdev->dev.of_node); + if (rmem) { + smem->regions[0].aux_base = rmem->base; + smem->regions[0].size = rmem->size; + } else { + /* + * Fall back to the memory-region reference, if we're not a + * reserved-memory node. + */ + ret = qcom_smem_resolve_mem(smem, "memory-region", &smem->regions[0]); + if (ret) + return ret; + } - if (num_regions > 1 && (ret = qcom_smem_map_memory(smem, &pdev->dev, - "qcom,rpm-msg-ram", 1))) - return ret; + if (num_regions > 1) { + ret = qcom_smem_resolve_mem(smem, "qcom,rpm-msg-ram", &smem->regions[1]); + if (ret) + return ret; + } + + for (i = 0; i < num_regions; i++) { + smem->regions[i].virt_base = devm_ioremap_wc(&pdev->dev, + smem->regions[i].aux_base, + smem->regions[i].size); + if (!smem->regions[i].virt_base) { + dev_err(&pdev->dev, "failed to remap %pa\n", &smem->regions[i].aux_base); + return -ENOMEM; + } + } header = smem->regions[0].virt_base; if (le32_to_cpu(header->initialized) != 1 || From patchwork Thu Sep 30 18:21:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 514969 Delivered-To: patch@linaro.org Received: by 2002:a02:606e:0:0:0:0:0 with SMTP id d46csp39536jaf; Thu, 30 Sep 2021 11:20:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy9jLqYAsGJArJaqOUCAPXufQ6GeubbU3b9w/JEgQ+MqPI7L6LxCJ8eY9BMvJT9dMEEcSV5 X-Received: by 2002:a17:906:3ce2:: with SMTP id d2mr807455ejh.410.1633026003241; Thu, 30 Sep 2021 11:20:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633026003; cv=none; d=google.com; s=arc-20160816; b=oTlSIzt5HndGgcGZSMd5MHskZR2pwUUM737WcxFhYdnxaL9IESrA5QeoA/Kx8aqRGz 96UCf6tkG0Ws/ESHOwfb9816PYH5asWbj1CQFQNPeCjrIZDPvtGR/pEbFwbfZc22NFxk ymAF6N5iuaAb1PUNzAvA2vvG/VzLAMztY2oVEROfv8m8IjIq7i1lOkXVnrz900qDE3K+ X+3JcH2g1gD16rXqxG1sYqX8RQMma+nIQhFEiaTG2tF+93t8Rqc8V2rgo09xirGHJgLC Ho9wJgsivWX+dGa26seyO5qlItebgB6izPk7SNyLyl7ezbSEfDw7LdixxPxDRqT1Cm+K UyIg== ARC-Message-Signature: i=1; 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id k6sm727416otf.80.2021.09.30.11.19.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 11:19:26 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Rob Herring , Frank Rowand Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Lew , Deepak Kumar Singh Subject: [PATCH v2 4/4] arm64: dts: qcom: sdm845: Drop standalone smem node Date: Thu, 30 Sep 2021 11:21:11 -0700 Message-Id: <20210930182111.57353-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210930182111.57353-1-bjorn.andersson@linaro.org> References: <20210930182111.57353-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now that the SMEM binding and driver allows the SMEM node to be described in the reserved-memory region directly, move the compatible and hwlock properties to the reserved-memory node and drop the standadlone node. Signed-off-by: Bjorn Andersson --- Changes since v1: - Node name is changed to "smem", as "memory" is reserved for memory nodes. arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) -- 2.29.2 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index beee57087d05..64119d2efdcf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -99,9 +99,11 @@ aop_cmd_db_mem: memory@85fe0000 { no-map; }; - smem_mem: memory@86000000 { + smem@86000000 { + compatible = "qcom,smem"; reg = <0x0 0x86000000 0 0x200000>; no-map; + hwlocks = <&tcsr_mutex 3>; }; tz_mem: memory@86200000 { @@ -941,12 +943,6 @@ tcsr_mutex: hwlock { #hwlock-cells = <1>; }; - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>;