From patchwork Wed Sep 29 21:03:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 514863 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp418627jam; Wed, 29 Sep 2021 14:06:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwCF/BqW6qQw9IaFjNRqINeZd2I4MUoClfgW5H9nwcSz15izumfhzfzLjsbp+xWthNYZSp0 X-Received: by 2002:a17:906:5010:: with SMTP id s16mr2314406ejj.245.1632949619258; Wed, 29 Sep 2021 14:06:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632949619; cv=none; d=google.com; s=arc-20160816; b=ass8io1lW8gxamNw6kxVmpKHTVdskuSBrJrbPt2cjazBTbqDo/gokwjTOGTsXcdOLe JF3IrV+ANIZ2ZQpBLWT2UidTcK+hQUlj+EEqUCCdIToqRbxmbQ+5X26f2td3c6TWlGYR pmKqmdzykGUFMsFYgeApvxSdxjfyuh4nwyq/Uc7/A3czzlyNJyj8mV+jIsPuM3eIPRzd Jmq52L2QOoTN8Thb6mcZPpYisu0onx0iK39QTFc1yh6ueKt9ziZ1ZKcUOPBYsorAfLwQ jrjUfUd0PmtkjZH8xLOh4zKxOFPBvAkHeZOnM5EX8FiR5YOHmQGFCKpnL34qMqnW/kZ2 bm9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qWI4Ka7n0dQPnT0TU9YWQ06UE86yJzfw98UR0cjXhAs=; b=F/QbhCmA+h/R3zzQHnylF9mV1+z/GXEo6E370B2AbVl1NG25wDeLHdbLrTiTGzYlnZ wpeL08V4d4TwMh0FZqcCPeI3DkpebQcJMsyOS1YEJZzc60lAzPXTBIfIf48byuwrhbow FsRuvRxmiVwvwyb/HMNgUntqkDDHqWjc6paXuo0fIvMKfPXsOFNlLe5E+YMEFbon8Azg adpOX265laCL7u8S9lkQrsQohOM6IVUbSrX10G3N34moCumegoSCf3HDV/QjY7LqWGt0 msYpBaK/sOZ3TpB59irWWXRn8gIA7LJXxZLJB/SIPKwQ1NUAVHJy3Fiwi9XAaRTQ2dSj P1gg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sve1s1NY; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.34.204.253]) by smtp.gmail.com with ESMTPSA id s9sm112613lfp.291.2021.09.29.14.06.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Sep 2021 14:06:54 -0700 (PDT) From: Linus Walleij To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Jakub Kicinski Cc: netdev@vger.kernel.org, Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Mauri Sandberg , DENG Qingfang Subject: [PATCH net-next 1/4 v4] net: dsa: rtl8366rb: Support disabling learning Date: Wed, 29 Sep 2021 23:03:46 +0200 Message-Id: <20210929210349.130099-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210929210349.130099-1-linus.walleij@linaro.org> References: <20210929210349.130099-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The RTL8366RB hardware supports disabling learning per-port so let's make use of this feature. Rename some unfortunately named registers in the process. Suggested-by: Vladimir Oltean Cc: Alvin Šipraga Cc: Mauri Sandberg Cc: Florian Fainelli Cc: DENG Qingfang Signed-off-by: Linus Walleij --- ChangeLog v3->v4: - No changes, rebased on other patches. ChangeLog v2->v3: - Disable learning by default, learning will be turned on selectively using the callback. ChangeLog v1->v2: - New patch suggested by Vladimir. --- drivers/net/dsa/rtl8366rb.c | 50 ++++++++++++++++++++++++++++++++----- 1 file changed, 44 insertions(+), 6 deletions(-) -- 2.31.1 Reviewed-by: Vladimir Oltean diff --git a/drivers/net/dsa/rtl8366rb.c b/drivers/net/dsa/rtl8366rb.c index bb9d017c2f9f..b3056064b937 100644 --- a/drivers/net/dsa/rtl8366rb.c +++ b/drivers/net/dsa/rtl8366rb.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -42,9 +43,12 @@ /* Port Enable Control register */ #define RTL8366RB_PECR 0x0001 -/* Switch Security Control registers */ -#define RTL8366RB_SSCR0 0x0002 -#define RTL8366RB_SSCR1 0x0003 +/* Switch per-port learning disablement register */ +#define RTL8366RB_PORT_LEARNDIS_CTRL 0x0002 + +/* Security control, actually aging register */ +#define RTL8366RB_SECURITY_CTRL 0x0003 + #define RTL8366RB_SSCR2 0x0004 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0) @@ -927,13 +931,14 @@ static int rtl8366rb_setup(struct dsa_switch *ds) /* layer 2 size, see rtl8366rb_change_mtu() */ rb->max_mtu[i] = 1532; - /* Enable learning for all ports */ - ret = regmap_write(smi->map, RTL8366RB_SSCR0, 0); + /* Disable learning for all ports */ + ret = regmap_write(smi->map, RTL8366RB_PORT_LEARNDIS_CTRL, + RTL8366RB_PORT_ALL); if (ret) return ret; /* Enable auto ageing for all ports */ - ret = regmap_write(smi->map, RTL8366RB_SSCR1, 0); + ret = regmap_write(smi->map, RTL8366RB_SECURITY_CTRL, 0); if (ret) return ret; @@ -1272,6 +1277,37 @@ static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port, return ret; } +static int +rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack) +{ + /* We support enabling/disabling learning */ + if (flags.mask & ~(BR_LEARNING)) + return -EINVAL; + + return 0; +} + +static int +rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack) +{ + struct realtek_smi *smi = ds->priv; + int ret; + + if (flags.mask & BR_LEARNING) { + ret = regmap_update_bits(smi->map, RTL8366RB_PORT_LEARNDIS_CTRL, + BIT(port), + (flags.val & BR_LEARNING) ? 0 : BIT(port)); + if (ret) + return ret; + } + + return 0; +} + static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu) { struct realtek_smi *smi = ds->priv; @@ -1682,6 +1718,8 @@ static const struct dsa_switch_ops rtl8366rb_switch_ops = { .port_vlan_del = rtl8366_vlan_del, .port_enable = rtl8366rb_port_enable, .port_disable = rtl8366rb_port_disable, + .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags, + .port_bridge_flags = rtl8366rb_port_bridge_flags, .port_change_mtu = rtl8366rb_change_mtu, .port_max_mtu = rtl8366rb_max_mtu, }; From patchwork Wed Sep 29 21:03:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 514864 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp418687jam; Wed, 29 Sep 2021 14:07:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyLKu8iDtR1g9s3mOBkjwQr3NcNTNgoeUxeuKRoQKFRE+Eyll6YrZWVSyX5F4hrONSAQj11 X-Received: by 2002:a05:6402:19b5:: with SMTP id o21mr2550500edz.214.1632949623767; Wed, 29 Sep 2021 14:07:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632949623; cv=none; d=google.com; s=arc-20160816; b=rwCKxvqLK7pIxyCFwn700YU3sL/YTq7UmX3MZXVxAT1Ateu1qpQ0XIdGerIz6/VUVQ ZgTnsP0YJPhl7e8WR0R4K1sFJXRJpDe5h5qyA/Fi6i+be/TqsdhImK7Kk9KeXwg7suTe OOR01kJ+jYqXzzwqU+Y2i53T4R2B8RWlHcrQ4a9JUBHe8wPLiBVdll1OBn2Yhh01f9Rr tCZvSa6nXwqaOzy4HXPwzdYx2GYi0uX+XM1k2Atzy7GhX4dhx9Ujva5KC5e64dIeapeN NmM41GTnyAs0/AEV5Cal4aL+k0D8z2VMZrEpG6i5DUdZZPlagYR5VaSO+XvE5orjF/AF W5CQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=A16Q8X6j77E5oCaHJ/vqDItQyNAq42o/Cp5ylsoL1I4=; b=LLpsDqLRtTt8nIPEoUANekSXQxSXSw2moYUv8z7GOQSw32CINLb7mvCzZXxeqlvrXI qPkURFpRFDiuQHCKTA7Adj5yAN/NK0jocUsPpA7lwTs7xwJIrTghzzcEv+8d+qXlFVRu jCXoM4a/EZOlCEaipdxWFTKzvrzxuFmLu4b6XHS5kvRygBKr/gxlbWE6/n1OZVG16D7G fvNHiEYTf47JT7p+xHXnoEtmBWoENgYd/BadTaC3ildoLWZaIIyHXHo3/lU1dHTspC7o 4oBcABeSpRDtrITVooYtx7iRTKUhbG61KGlPy2GLO6ZZBONoMIEwpv/JDfC/naraXqEk DdHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="DeGSG/1v"; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.34.204.253]) by smtp.gmail.com with ESMTPSA id s9sm112613lfp.291.2021.09.29.14.06.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Sep 2021 14:06:56 -0700 (PDT) From: Linus Walleij To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Jakub Kicinski Cc: netdev@vger.kernel.org, Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Mauri Sandberg , DENG Qingfang Subject: [PATCH net-next 2/4 v4] net: dsa: rtl8366rb: Support flood control Date: Wed, 29 Sep 2021 23:03:47 +0200 Message-Id: <20210929210349.130099-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210929210349.130099-1-linus.walleij@linaro.org> References: <20210929210349.130099-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Now that we have implemented bridge flag handling we can easily support flood control as well so let's do it. Cc: Vladimir Oltean Cc: Alvin Šipraga Cc: Mauri Sandberg Cc: Florian Fainelli Cc: DENG Qingfang Signed-off-by: Linus Walleij --- ChangeLog v3->v4: - No changes, rebased on the other patches. ChangeLog v2->v3: - Move the UNMC under the multicast setting as it is related to multicast to unknown address. - Add some more registers from the API, unfortunately we don't know how to make use of them. - Use tabs for indentation in copypaste bug. - Since we don't know how to make the elaborate storm control work just mention flood control in the message. ChangeLog v1->v2: - New patch --- drivers/net/dsa/rtl8366rb.c | 55 +++++++++++++++++++++++++++++++++++-- 1 file changed, 53 insertions(+), 2 deletions(-) -- 2.31.1 diff --git a/drivers/net/dsa/rtl8366rb.c b/drivers/net/dsa/rtl8366rb.c index b3056064b937..52e750ea790e 100644 --- a/drivers/net/dsa/rtl8366rb.c +++ b/drivers/net/dsa/rtl8366rb.c @@ -164,6 +164,26 @@ */ #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f +/* Storm registers are for flood control + * + * 02e2 and 02e3 are defined in the header for the RTL8366RB API + * but there are no usage examples. The implementation only activates + * the filter per port in the CTRL registers. + */ +#define RTL8366RB_STORM_FILTERING_1_REG 0x02e2 +#define RTL8366RB_STORM_FILTERING_PERIOD_BIT BIT(0) +#define RTL8366RB_STORM_FILTERING_PERIOD_MSK GENMASK(1, 0) +#define RTL8366RB_STORM_FILTERING_COUNT_BIT BIT(1) +#define RTL8366RB_STORM_FILTERING_COUNT_MSK GENMASK(3, 2) +#define RTL8366RB_STORM_FILTERING_BC_BIT BIT(5) +#define RTL8366RB_STORM_FILTERING_2_REG 0x02e3 +#define RTL8366RB_STORM_FILTERING_MC_BIT BIT(0) +#define RTL8366RB_STORM_FILTERING_UNDA_BIT BIT(5) +#define RTL8366RB_STORM_BC_CTRL 0x03e0 +#define RTL8366RB_STORM_MC_CTRL 0x03e1 +#define RTL8366RB_STORM_UNDA_CTRL 0x03e2 +#define RTL8366RB_STORM_UNMC_CTRL 0x03e3 + /* LED control registers */ #define RTL8366RB_LED_BLINKRATE_REG 0x0430 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007 @@ -1282,8 +1302,8 @@ rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack) { - /* We support enabling/disabling learning */ - if (flags.mask & ~(BR_LEARNING)) + if (flags.mask & ~(BR_LEARNING | BR_BCAST_FLOOD | + BR_MCAST_FLOOD | BR_FLOOD)) return -EINVAL; return 0; @@ -1305,6 +1325,37 @@ rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port, return ret; } + if (flags.mask & BR_BCAST_FLOOD) { + ret = regmap_update_bits(smi->map, RTL8366RB_STORM_BC_CTRL, + BIT(port), + (flags.val & BR_BCAST_FLOOD) ? BIT(port) : 0); + if (ret) + return ret; + } + + if (flags.mask & BR_MCAST_FLOOD) { + ret = regmap_update_bits(smi->map, RTL8366RB_STORM_MC_CTRL, + BIT(port), + (flags.val & BR_MCAST_FLOOD) ? BIT(port) : 0); + if (ret) + return ret; + /* UNMC = Unknown multicast address */ + ret = regmap_update_bits(smi->map, RTL8366RB_STORM_UNMC_CTRL, + BIT(port), + (flags.val & BR_FLOOD) ? BIT(port) : 0); + if (ret) + return ret; + } + + if (flags.mask & BR_FLOOD) { + /* UNDA = Unknown destination address */ + ret = regmap_update_bits(smi->map, RTL8366RB_STORM_UNDA_CTRL, + BIT(port), + (flags.val & BR_FLOOD) ? BIT(port) : 0); + if (ret) + return ret; + } + return 0; } From patchwork Wed Sep 29 21:03:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 514865 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp418696jam; Wed, 29 Sep 2021 14:07:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxc546c0SuOSOyG+csEHh4qf3LRnuFvHp3yXGzUiohIRVlSfJIyGnjLlVFKGCOf2dYwfZ5y X-Received: by 2002:a17:906:1146:: with SMTP id i6mr2383405eja.12.1632949625263; Wed, 29 Sep 2021 14:07:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632949625; cv=none; d=google.com; s=arc-20160816; b=BMUvAZH1dGaEV5Yqd07pGRmmTTbxZ+jGbtL3XzI8PBG6kIH2mly/6e86mKXtmPX+bv X7MburTvxtEK8kpVyOSGiPFiAFxzMbd/zVzOfQvpVWJWaXaG0qfxGmQ4CNgRk5so4OMt jmh67HteBLoB+mjX+QdWqqnWmLFbxFvTSAoc20koGblwi+wywfXZva9TOVAGjFOXrpNJ NgSpNKBKUSmc+AodmLdCJ6/FSrHIT2zdzP3sxQ2sMvlOwJzT5cERewVtCY4FJmfQiJkD JBMHZ5r6jMROKUvR3LzjcGYWcheIO0RUhcEll2a6UJrxejBd8HMRTLx15lLyQmGlMwOo L3oA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5IQ8G0uxxR5Pb6926edFohGE/OhQAa2EdYE4PQBssMg=; b=zFDGA9KiOdKAkBhrKY0aGbAMexITkq5FsZpUGIuxv06SLVBkZt89Es7ePZu8QxmsZq fQbjez14K6haAb36emfft+3jDnSRY7ObkkNgr8Cl3tLvavGgd5N18Mrt6CMZNe/WG0HF bTmNMrQ4txiwoQstRKZwU7N/i13aRsS0zNzRiCeysql1Qp8sKUcaUQ7SFBqSrFJl78Sd +hvKe6iEhdE/HDIY8xkEeLEi/KxepfiNtMqXvkpp/vJ7LH0hVfXYlf1NqUKF68HnzDub 8AFN8Ri+S+0TJf2x/q+CLudDxegZnbpBuHJSr0jJocKhFx6LaouI8h2iEZvOwdTj+xcp 9gtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pyONePkp; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.34.204.253]) by smtp.gmail.com with ESMTPSA id s9sm112613lfp.291.2021.09.29.14.06.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Sep 2021 14:06:58 -0700 (PDT) From: Linus Walleij To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Jakub Kicinski Cc: netdev@vger.kernel.org, Linus Walleij , Mauri Sandberg , DENG Qingfang , =?utf-8?q?Alvin_=C5=A0ipraga?= Subject: [PATCH net-next 3/4 v4] net: dsa: rtl8366rb: Support fast aging Date: Wed, 29 Sep 2021 23:03:48 +0200 Message-Id: <20210929210349.130099-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210929210349.130099-1-linus.walleij@linaro.org> References: <20210929210349.130099-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This implements fast aging per-port using the special "security" register, which will flush any learned L2 LUT entries on a port. Suggested-by: Vladimir Oltean Cc: Mauri Sandberg Cc: DENG Qingfang Cc: Florian Fainelli Reviewed-by: Alvin Šipraga Signed-off-by: Linus Walleij --- ChangeLog v3->v4: - No changes, rebased on the other patches. ChangeLog v2->v3: - Underscore that this only affects learned L2 entries, not static ones. ChangeLog v1->v2: - New patch suggested by Vladimir. --- drivers/net/dsa/rtl8366rb.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.31.1 diff --git a/drivers/net/dsa/rtl8366rb.c b/drivers/net/dsa/rtl8366rb.c index 52e750ea790e..748f22ab9130 100644 --- a/drivers/net/dsa/rtl8366rb.c +++ b/drivers/net/dsa/rtl8366rb.c @@ -1359,6 +1359,19 @@ rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port, return 0; } +static void +rtl8366rb_port_fast_age(struct dsa_switch *ds, int port) +{ + struct realtek_smi *smi = ds->priv; + + /* This will age out any learned L2 entries */ + regmap_update_bits(smi->map, RTL8366RB_SECURITY_CTRL, + BIT(port), BIT(port)); + /* Restore the normal state of things */ + regmap_update_bits(smi->map, RTL8366RB_SECURITY_CTRL, + BIT(port), 0); +} + static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu) { struct realtek_smi *smi = ds->priv; @@ -1771,6 +1784,7 @@ static const struct dsa_switch_ops rtl8366rb_switch_ops = { .port_disable = rtl8366rb_port_disable, .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags, .port_bridge_flags = rtl8366rb_port_bridge_flags, + .port_fast_age = rtl8366rb_port_fast_age, .port_change_mtu = rtl8366rb_change_mtu, .port_max_mtu = rtl8366rb_max_mtu, }; From patchwork Wed Sep 29 21:03:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 514866 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp418729jam; Wed, 29 Sep 2021 14:07:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzMBdOr3WJMQ+kQhuX9pJKGX2RBc4ARh1LanHffLA9DkGHtMeAgCleqlYJyFFYz4vCRuvOJ X-Received: by 2002:aa7:c78f:: with SMTP id n15mr2604946eds.338.1632949627887; Wed, 29 Sep 2021 14:07:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632949627; cv=none; d=google.com; s=arc-20160816; b=sQB6gASFX8YnE3bMqaksm0NJcC+E5LizQhL4exWqb4FCIkvGlDkxD1v7+suEuC8Z+l OO7FIlZUVqI1cDkBhQm5JPULWUcm/Nuj/0d38mwIPNd+D7xF9swDgX+ho/Cew/bE0k0R 8hETA+s9P1n1L8TiJzifBeQPZ6+mhIqZezsROCHBD0orLh2UacqNuzc0uDfBTfTvaMm/ d1lxwLIKMUdaXukoG9sH+7IKtOheX/BEd+0RFCAF7zOMuMguAMlwXToJGcFeVVmFfFhM N8RsdrkGxEutdX66JGIufqIM5C2YCSobNU3DHqTRf217bZe1Lkjs06Q5ITi6P7EVATpl zdag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3KZeQ1UL+Qr6VrGAkVMnUDxIrRV+iTWbafHkEPoCs9g=; b=N6XuLjts0Ph+2dZnwifkX0QIeWh00A5PfTjMjUBACF/7E4sIFrvutXANDTRD6tWNMY KF1S0y+5/IN3N7Te/BI2G4224S5l8DvAFMN849VOsJjQIlez6TddGqQ+FC8Hrz8rMz98 AO0fUfO3HVE9ASepuorAAM492csG7ihPJFZtznhTvsfwEdJToJ/CWL8OjJoWhOm5zLXH fHx8/jaN7Isj26/cxiF66ndLCbbdnBb8Ja/BHVXYDK3a37CdQap7OZfiqAtP+IkH3x3V iXIxtcbgcdk0eRmFfRzfWXUQd06rTz45TORfie6h5ubomVcCJbwc0I4n1F7+MEO3Hora 9w1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M58hkh9S; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.34.204.253]) by smtp.gmail.com with ESMTPSA id s9sm112613lfp.291.2021.09.29.14.06.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Sep 2021 14:07:00 -0700 (PDT) From: Linus Walleij To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Jakub Kicinski Cc: netdev@vger.kernel.org, Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Mauri Sandberg , DENG Qingfang Subject: [PATCH net-next 4/4 v4] net: dsa: rtl8366rb: Support setting STP state Date: Wed, 29 Sep 2021 23:03:49 +0200 Message-Id: <20210929210349.130099-5-linus.walleij@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210929210349.130099-1-linus.walleij@linaro.org> References: <20210929210349.130099-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This adds support for setting the STP state to the RTL8366RB DSA switch. This rids the following message from the kernel on e.g. OpenWrt: DSA: failed to set STP state 3 (-95) Since the RTL8366RB has one STP state register per FID with two bit per port in each, we simply loop over all the FIDs and set the state on all of them. Cc: Vladimir Oltean Cc: Alvin Šipraga Cc: Mauri Sandberg Cc: DENG Qingfang Signed-off-by: Linus Walleij --- ChangeLog v1->v4: - New patch after discovering that we can do really nice bridge offloading with these bits. --- drivers/net/dsa/rtl8366rb.c | 47 +++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) -- 2.31.1 diff --git a/drivers/net/dsa/rtl8366rb.c b/drivers/net/dsa/rtl8366rb.c index 748f22ab9130..c143fdab4802 100644 --- a/drivers/net/dsa/rtl8366rb.c +++ b/drivers/net/dsa/rtl8366rb.c @@ -110,6 +110,14 @@ #define RTL8366RB_POWER_SAVING_REG 0x0021 +/* Spanning tree status (STP) control, two bits per port per FID */ +#define RTL8368S_SPT_STATE_BASE 0x0050 /* 0x0050..0x0057 */ +#define RTL8368S_SPT_STATE_MSK 0x3 +#define RTL8368S_SPT_STATE_DISABLED 0x0 +#define RTL8368S_SPT_STATE_BLOCKING 0x1 +#define RTL8368S_SPT_STATE_LEARNING 0x2 +#define RTL8368S_SPT_STATE_FORWARDING 0x3 + /* CPU port control reg */ #define RTL8368RB_CPU_CTRL_REG 0x0061 #define RTL8368RB_CPU_PORTS_MSK 0x00FF @@ -254,6 +262,7 @@ #define RTL8366RB_NUM_LEDGROUPS 4 #define RTL8366RB_NUM_VIDS 4096 #define RTL8366RB_PRIORITYMAX 7 +#define RTL8366RB_NUM_FIDS 8 #define RTL8366RB_FIDMAX 7 #define RTL8366RB_PORT_1 BIT(0) /* In userspace port 0 */ @@ -1359,6 +1368,43 @@ rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port, return 0; } +static void +rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) +{ + struct realtek_smi *smi = ds->priv; + u16 mask; + u32 val; + int i; + + switch (state) { + case BR_STATE_DISABLED: + val = RTL8368S_SPT_STATE_DISABLED; + break; + case BR_STATE_BLOCKING: + case BR_STATE_LISTENING: + val = RTL8368S_SPT_STATE_BLOCKING; + break; + case BR_STATE_LEARNING: + val = RTL8368S_SPT_STATE_LEARNING; + break; + case BR_STATE_FORWARDING: + val = RTL8368S_SPT_STATE_FORWARDING; + break; + default: + dev_err(smi->dev, "unknown bridge state requested\n"); + return; + }; + + mask = (RTL8368S_SPT_STATE_MSK << (port * 2)); + val <<= (port * 2); + + /* Set the same status for the port on all the FIDs */ + for (i = 0; i < RTL8366RB_NUM_FIDS; i++) { + regmap_update_bits(smi->map, RTL8368S_SPT_STATE_BASE + i, + mask, val); + } +} + static void rtl8366rb_port_fast_age(struct dsa_switch *ds, int port) { @@ -1784,6 +1830,7 @@ static const struct dsa_switch_ops rtl8366rb_switch_ops = { .port_disable = rtl8366rb_port_disable, .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags, .port_bridge_flags = rtl8366rb_port_bridge_flags, + .port_stp_state_set = rtl8366rb_port_stp_state_set, .port_fast_age = rtl8366rb_port_fast_age, .port_change_mtu = rtl8366rb_change_mtu, .port_max_mtu = rtl8366rb_max_mtu,