From patchwork Mon Sep 20 02:44:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514292 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1667915jao; Sun, 19 Sep 2021 19:47:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwRWXcU5O68xT65m9pPIdxBdnl9qIpyfTShL6GeUnOCXaouGgrtYEXDzc8V2l6v1G9P34P2 X-Received: by 2002:a05:6214:1444:: with SMTP id b4mr23013086qvy.33.1632106028045; Sun, 19 Sep 2021 19:47:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632106028; cv=none; d=google.com; s=arc-20160816; b=SdQfMCYUeH/kefuCV63Is0JdaH1K4VD9hUS7tEufqFM6uf+mDom1P3cdypo+n3PdeG 9JyVa/Um1lSjqH0a16WUvWidAl96X9E+bZKOP2XCb/XlG5NTqNliBzgJZnuUunVAu+EB P/ga7Kq0tuxm1hgwEOWTbvdSIesIji6Bmd/mP8muBtsnobtS77POVVVXvBgDzy5Ts/ke Dcjib9fmbEsUWw5Y4dmABtXnZgUvPAqwIQ110i03PKVbt9oYuX57ww2wF2MQ2SgbRd5x pf4hvD+iv7NbOzMEp5IdQylVvAhT3ffuqXW0SsuDe9J1SKM9T/R6D69dBKnKjkzxctVG yN9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CtQUY+VgkQT1rox5MwFOniOvDKV16giSUD56+x0u+Dc=; b=CHwN0ZoBekhz0mcKYVDF1dTCzT+QkW7qAihXN3s0M8RKH881Ngij1TLOEiTCZfsovu U3ZVmhjLQ00ZUQ5NhvPytrVcau0bCJ9QbpArBB9F+EUpVpNXSnxQ1n2frlgOcdS4Bu4o I0wTjlO4cXwxLGYW2H3TXvERn/IwVUi7YtohwasUdZf7DlZkGCArKE3MxYNNwJJcL3H7 /G6J9quAWO4gSSbDTfZGRrQw/X08k6QSALmzZ1h7xVoTzUHpOAUUYXb2sIGYyXWC7bKu P2lu8xnDjOlIoFit25e7hj5R2igwmP0M/0aRk8NCtNBTWDyxFdvlEH7003hhoOB2+Zjj BlDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jq+L2dnp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f16si8470094qko.262.2021.09.19.19.47.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 19 Sep 2021 19:47:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jq+L2dnp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40128 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mS9Kl-0005EO-IL for patch@linaro.org; Sun, 19 Sep 2021 22:47:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57442) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mS9Is-0005Cm-Ky for qemu-devel@nongnu.org; Sun, 19 Sep 2021 22:45:10 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:34576) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mS9Iq-0008Ca-NC for qemu-devel@nongnu.org; Sun, 19 Sep 2021 22:45:10 -0400 Received: by mail-pf1-x42c.google.com with SMTP id g14so14936718pfm.1 for ; Sun, 19 Sep 2021 19:45:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CtQUY+VgkQT1rox5MwFOniOvDKV16giSUD56+x0u+Dc=; b=jq+L2dnpHgrIK8wcRbWEzdX1zmYvJLjQfMVbUGR4wS88LLKplbSxzc4XWI6Aik9tJ1 PH/bvimKg1PX70MeUorumde1SLeQgR7AmRRIjDxFihVrgnsHDg/8dAZBzByqroPcPJa1 UH0cawgvVP3AUID2VAIcK0pAr7YYvzqyWu2cr9RDvTbmnE2Jench5Hur/ggt/6nnwExk 9qWnipQvfkI+Kd3/7cTvJUg96W/2a5PO0XW6oDio2+RWdWB/4EBLIHApSV6Z9kTWC5cO a1kRrEdzysZS11olOY8N4Hra8SKhE+Aqaz8RtOwKdrIzbubzRRC61W+16bf+racCXJHB sGhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CtQUY+VgkQT1rox5MwFOniOvDKV16giSUD56+x0u+Dc=; b=0u7O/08xkQlyGdP/uCUyLiyw3YGH0E0sTNc5Gfbt6marp3ajH7sl04Nbp1E1mbeqkN dMBnJ74YztKAlCEjVnSJntH1MZ4miLUEagCG0xhvfEUkrLrnmM/iUiuLCiakUoYuFe1K gWflzsnmwefz6yAYZB4NyJcjDVWg2NBxUR4sCgsBpRJTIeopkz0SR5Im+Onca++x5QMt hIXMByqjZPAFByfPwqGsJKc/wVt+tnMZxuz3d0GK0wx2trmJ6hqk1Zfvuel/YTgyOhHB uaIR1wkz4zbkGI7JJfsLPJ4LFvU/tzsLxZ06LlA8otwfpbXSXGKDExn0JYyq+6U4M1mG RvVg== X-Gm-Message-State: AOAM531FbhEsHkPqg1odLz8orMMyWl0CnMtRUySBuU5Son0FfATKjvkc xqpePgRr5Wwc0F3hyk5kN+HIPon1fKMMtw== X-Received: by 2002:a65:6487:: with SMTP id e7mr21295360pgv.27.1632105907014; Sun, 19 Sep 2021 19:45:07 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id fh3sm16164767pjb.8.2021.09.19.19.45.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Sep 2021 19:45:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 1/6] linux-user/aarch64: Handle EC_PCALIGNMENT Date: Sun, 19 Sep 2021 19:44:59 -0700 Message-Id: <20210920024504.625965-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210920024504.625965-1-richard.henderson@linaro.org> References: <20210920024504.625965-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will shortly be raised for execution with a misaligned pc. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 44 +++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 11e34cb100..6e03afb2bd 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -78,7 +78,7 @@ void cpu_loop(CPUARMState *env) { CPUState *cs = env_cpu(env); - int trapnr, ec, fsc, si_code; + int trapnr, ec, fsc, si_sig, si_code; abi_long ret; for (;;) { @@ -112,28 +112,38 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */ ec = syn_get_ec(env->exception.syndrome); - assert(ec == EC_DATAABORT || ec == EC_INSNABORT); - - /* Both EC have the same format for FSC, or close enough. */ - fsc = extract32(env->exception.syndrome, 0, 6); - switch (fsc) { - case 0x04 ... 0x07: /* Translation fault, level {0-3} */ - si_code = TARGET_SEGV_MAPERR; + switch (ec) { + case EC_DATAABORT: + case EC_INSNABORT: + /* Both EC have the same format for FSC, or close enough. */ + fsc = extract32(env->exception.syndrome, 0, 6); + switch (fsc) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + si_sig = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + si_sig = TARGET_SIGSEGV; + si_code = TARGET_SEGV_ACCERR; + break; + case 0x11: /* Synchronous Tag Check Fault */ + si_sig = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MTESERR; + break; + default: + g_assert_not_reached(); + } break; - case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ - case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ - si_code = TARGET_SEGV_ACCERR; - break; - case 0x11: /* Synchronous Tag Check Fault */ - si_code = TARGET_SEGV_MTESERR; + case EC_PCALIGNMENT: + si_sig = TARGET_SIGBUS; + si_code = TARGET_BUS_ADRALN; break; default: g_assert_not_reached(); } - - force_sig_fault(TARGET_SIGSEGV, si_code, env->exception.vaddress); + force_sig_fault(si_sig, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: From patchwork Mon Sep 20 02:45:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514293 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1667923jao; Sun, 19 Sep 2021 19:47:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz3y4Vln6GQashxu3Jhv9b3QKA2im4dIHCiLMJOPfhYSxAkdcwgd0F5jddUWnaZRzY/AZud X-Received: by 2002:ac8:7d84:: with SMTP id c4mr21062157qtd.254.1632106029041; Sun, 19 Sep 2021 19:47:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632106029; cv=none; d=google.com; s=arc-20160816; b=OzVy4b0iKrG8eCvGNdoqtnzkcE3XAiK/EjT65GPWRfQrIP1myJuhS+lVby1SygTG5M /xRlM2M/Fy6AzWosAeIpuoCUo3iUWmkSr60rvWXcttZIgDVa8cw+Nbt3YytyVU+mlxDj p5JXRvbBFZQ+6FNMuuo638XJiEw426/w3MwHnKl/Ol1c4R3N31789IonmZsCC+hwcB83 1qEA6FNBtiBeL/7GwGQtYxOnY+lX/qDeqlFWAMQqGU7XlxhYbeWlA6P5WZatFlcziH0y 121Vnp1c7x0Rr3p/77I4tg9V0wEujQdPr4rq/dhtzZnEQP0GVTskGRhOLlFvYffIlKfl kG4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6vZb5MWAv/fM2L9STadGzJOqVrgkaOYinJFwq93jV/c=; b=jTyK41osb5/YrI4ykT9oTd9UAyOlmibn0xPbBHqLkZjhAomkxobSS/qMegGv3+M/b8 nucmK5bNbWYBCLFij9JHAaQAOSa+TDAJa5/qyG3PMnpiskdXj8WMn3XxjTKpGBX1HYrR LlWAugaDBPLoXVW0tu4KkTkCHuNaYr6kQUT0zrRNknFLQzR9moBWSxAwhxHz6tgVY1D3 v3xfgRyzMJ1YoWqUKzcY1kIaoJ4p323VLn0gx89W3VDf0P9kr3EigWUqeaOztDztrdg6 NcX9ptbzNtZ2IZvQIDvfYafd7wheFGy9/h/GDRR8k6hP1YjgkTv+s/CTDmWnomnu0SVl FrHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=lKIx7rDq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/arm/cpu_loop.c | 39 ++++++++++++++++++++++++++++++++++----- 1 file changed, 34 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index d4b4f0c71f..1377a80620 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -24,6 +24,7 @@ #include "cpu_loop-common.h" #include "signal-common.h" #include "semihosting/common-semi.h" +#include "target/arm/syndrome.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -279,8 +280,8 @@ static bool emulate_arm_fpa11(CPUARMState *env, uint32_t opcode) void cpu_loop(CPUARMState *env) { CPUState *cs = env_cpu(env); - int trapnr; - unsigned int n, insn; + int trapnr, si_signo, si_code; + unsigned int n, insn, ec, fsc; abi_ulong ret; for(;;) { @@ -422,9 +423,37 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* XXX: check env->error_code */ - force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, - env->exception.vaddress); + /* + * For user-only we don't set TTBCR_EAE, so we always get + * short-form FSC, which then tells us to look at the FSR. + */ + ec = syn_get_ec(env->exception.syndrome); + assert(ec == EC_DATAABORT || ec == EC_INSNABORT); + fsc = extract32(env->exception.syndrome, 0, 6); + assert(fsc == 0x3f); + switch (env->exception.fsr & 0x1f) { + case 0x1: /* Alignment */ + si_signo = TARGET_SIGBUS; + si_code = TARGET_BUS_ADRALN; + break; + case 0x3: /* Access flag fault, level 1 */ + case 0x6: /* Access flag fault, level 2 */ + case 0x9: /* Domain fault, level 1 */ + case 0xb: /* Domain fault, level 2 */ + case 0xd: /* Permission fault, level 1 */ + case 0xf: /* Permission fault, level 2 */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_ACCERR; + break; + case 0x5: /* Translation fault, level 1 */ + case 0x7: /* Translation fault, level 2 */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MAPERR; + break; + default: + g_assert_not_reached(); + } + force_sig_fault(si_signo, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: From patchwork Mon Sep 20 02:45:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514294 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1667940jao; Sun, 19 Sep 2021 19:47:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxgxto0DZtEjG0FrVDbG2cZG2Rfm6B14ZB8smLXAgznydGf44wUvXkQCuTv28iw0aDzh2a2 X-Received: by 2002:a37:8906:: with SMTP id l6mr22279458qkd.210.1632106031388; Sun, 19 Sep 2021 19:47:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632106031; cv=none; d=google.com; s=arc-20160816; b=Jtd/33I99I+CslwmCa/KTBZsX07/a1gxK51xSsjapXOs5HHyNJK+APIbGMze8Ru1W5 IHV8MCTIqZEBywUnKGFM3BzbTwVGyIh+fKMAPCwikMtbSkdpKR5M8bwNmofrG2P+8uEg YbciEwkSyyibpSuh+LVBZMb0/qaaa3Hqgve5MdAKJO10NbpM72BDvgM6aLf+CbTCtGLK S2vRMS8TsSzoiiL1AGlqJCCJTCiHULSdoqEUJuc4Pm7hNZYOXx3SPm54zQwxc71cT+3E k6zbCBPAhE8qSaiYBVR1IhypraRkDV4kjRfWhZe7BC5WFRNbp6Dr3gHHJlYziWQWLMZR NGPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cOM7VdjppvOQio1FebUdQG/S4ihUXuMBVVoQ3T4V5Ts=; b=veCS2R/8A6/ac5DLRaDZCizAzEdhF4i4GytVQveGQ+eZkblD5UmGzgRzwd0icE/4YR AlTuJQIxoLpy33eK6HazK5fgRPu/BtCV661k7Zeb7B1MDvxRGXUkPLfxZfTi+7gLmONR 6stU/G4MpX7JJ1PLsuT0MsMfQ6atxC8bVN/hyoxr4BU5hWnxsgINAsLTGWQV4fHmqQ2H 0TDkydDcmXZRsr/Ir1AnMBEvC6scqOhrGobYphRl4pOAnOT71vYqjZUS9b5Ga9gws+jH BtgRlQwCHxD9EFFTcj+mluh42X7AP6ocutx9HIzVlKKMFJLXZmLgNOdxebLU/WGSRaNI s0xQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pHdUM4ky; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w25si8037367qtn.93.2021.09.19.19.47.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 19 Sep 2021 19:47:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pHdUM4ky; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40438 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mS9Ko-0005Tv-SV for patch@linaro.org; Sun, 19 Sep 2021 22:47:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57504) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mS9Iu-0005DC-Ur for qemu-devel@nongnu.org; Sun, 19 Sep 2021 22:45:14 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:36707) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mS9Ir-0008DI-RI for qemu-devel@nongnu.org; Sun, 19 Sep 2021 22:45:12 -0400 Received: by mail-pf1-x42a.google.com with SMTP id m26so14907846pff.3 for ; Sun, 19 Sep 2021 19:45:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cOM7VdjppvOQio1FebUdQG/S4ihUXuMBVVoQ3T4V5Ts=; b=pHdUM4kyoVpVHqV8W3Nx2y52gXeyp1b3385iG9og4GNlqIj5Ug9DacpXVoC/0nQzQ4 0RdsbQaXCuBXJ9Nhe9dlPC7gbQgzvNVWLGkUHQJ/xEiTkhPkksFvHSSs01SlVYZXlpd5 1yHWSa4oPE0t28OBQvxA2+utpqAPD4BO8FOaOYS7i0Oo58WwIV2UELrK3vvgEFwaEqiU /89V0YSsSJtv2Xj8eErHq52GeRQGTY/CPnCuxks6Ja5m+aSufx84TP+F4zALmwSAKubJ CPbdhOGiUMoqcRCQWrKlnFLqOzeWcJbcnPfij++VdMFwM77JbSmlRrkCtPVChpBep8t9 vjYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cOM7VdjppvOQio1FebUdQG/S4ihUXuMBVVoQ3T4V5Ts=; b=AAwHc5YY7CcSwDY8YSi/wvpichh8jMm0TrPG/NjZAsrqjVEBoQRJ81szPBaanVwEiV EcRnSliomIedoc7wkIE0rahd+iXCu2WGR1CmowH/cF4BT+jmkCQgENAYpi4lXnOhl5mE +bQoCJrnVLXgOu5rgr+Ufb1rewrKX+pUYPC8FvrIYsjIJMzod3kb81kDK5Jeau35uGhL Y7b0laGSgyzLxE7ayK+Pysxhgw7cNLCzRZreFzU79YVLF2Qo9/ipeT5kUt2o3XXCNwUo CBpv/eKv6o4efPlGbNFig2eq3g+VOHJKVxLc+DeuDg5Lok9kPo8DO62el/JRbGaRuShP 4j7g== X-Gm-Message-State: AOAM5301k9CYZlQfUdtBQX83If3+RcrRPs3GRzJEjOv0BoEy12nuQCYN PvASDnh9ghBoVDtnD20RhA0Jeavfn5UhpQ== X-Received: by 2002:a63:7405:: with SMTP id p5mr21257119pgc.426.1632105908468; Sun, 19 Sep 2021 19:45:08 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id fh3sm16164767pjb.8.2021.09.19.19.45.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Sep 2021 19:45:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 3/6] target/arm: Take an exception if PC is misaligned Date: Sun, 19 Sep 2021 19:45:01 -0700 Message-Id: <20210920024504.625965-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210920024504.625965-1-richard.henderson@linaro.org> References: <20210920024504.625965-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For A64, any input to an indirect branch can cause this. For A32, many indirect branch paths force the branch to be aligned, but BXWritePC does not. This includes the BX instruction but also other interworking changes to PC. Prior to v8, this case is UNDEFINED. With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an exception or force align the PC. We choose to raise an exception because we have the infrastructure, it makes the generated code for gen_bx simpler, and it has the possibility of catching more guest bugs. Signed-off-by: Richard Henderson --- target/arm/helper.h | 1 + target/arm/syndrome.h | 5 +++++ target/arm/tlb_helper.c | 24 +++++++++++++++++++++++ target/arm/translate-a64.c | 23 +++++++++++++++++++--- target/arm/translate.c | 39 +++++++++++++++++++++++++++++++------- 5 files changed, 82 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/target/arm/helper.h b/target/arm/helper.h index 448a86edfd..b463d9343b 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -47,6 +47,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, DEF_HELPER_2(exception_internal, void, env, i32) DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) DEF_HELPER_2(exception_bkpt_insn, void, env, i32) +DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_1(wfe, void, env) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index f30f4130a2..8cde8e7243 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -282,4 +282,9 @@ static inline uint32_t syn_illegalstate(void) return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; } +static inline uint32_t syn_pcalignment(void) +{ + return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + #endif /* TARGET_ARM_SYNDROME_H */ diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index dc5860180f..1a50927bd6 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -9,6 +9,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/helper-proto.h" static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, @@ -123,6 +124,29 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } +void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) +{ + int target_el = exception_target_el(env); + + if (target_el == 2 || arm_el_is_aa64(env, target_el)) { + /* + * To aarch64 and aarch32 el2, pc alignment has a + * special exception class. + */ + env->exception.vaddress = pc; + env->exception.fsr = 0; + raise_exception(env, EXCP_PREFETCH_ABORT, syn_pcalignment(), target_el); + } else { + /* + * To aarch32 el1, pc alignment is like data alignment + * except with a prefetch abort. + */ + ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; + arm_deliver_fault(env_archcpu(env), pc, MMU_INST_FETCH, + cpu_mmu_index(env, true), &fi); + } +} + #if !defined(CONFIG_USER_ONLY) /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ab6b346e35..8c72e37de3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14752,8 +14752,10 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *s = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; + uint64_t pc = s->base.pc_next; uint32_t insn; + /* Singlestep exceptions have the highest priority. */ if (s->ss_active && !s->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either @@ -14768,13 +14770,28 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) assert(s->base.num_insns == 1); gen_swstep_exception(s, 0, 0); s->base.is_jmp = DISAS_NORETURN; + s->base.pc_next = pc + 4; return; } - s->pc_curr = s->base.pc_next; - insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b); + if (pc & 3) { + /* + * PC alignment fault. This has priority over the instruction abort + * that we would receive from a translation fault via arm_ldl_code. + * This should only be possible after an indirect branch, at the + * start of the TB. + */ + assert(s->base.num_insns == 1); + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); + s->base.is_jmp = DISAS_NORETURN; + s->base.pc_next = QEMU_ALIGN_UP(pc, 4); + return; + } + + s->pc_curr = pc; + insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b); s->insn = insn; - s->base.pc_next += 4; + s->base.pc_next = pc + 4; s->fp_access_checked = false; s->sve_access_checked = false; diff --git a/target/arm/translate.c b/target/arm/translate.c index caefb1e1a1..62c396b880 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9497,7 +9497,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) dc->insn_start = tcg_last_op(); } -static bool arm_pre_translate_insn(DisasContext *dc) +static bool arm_check_kernelpage(DisasContext *dc) { #ifdef CONFIG_USER_ONLY /* Intercept jump to the magic kernel page. */ @@ -9509,7 +9509,11 @@ static bool arm_pre_translate_insn(DisasContext *dc) return true; } #endif + return false; +} +static bool arm_check_ss_active(DisasContext *dc) +{ if (dc->ss_active && !dc->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either @@ -9543,17 +9547,38 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; + uint32_t pc = dc->base.pc_next; unsigned int insn; - if (arm_pre_translate_insn(dc)) { - dc->base.pc_next += 4; + /* Singlestep exceptions have the highest priority. */ + if (arm_check_ss_active(dc)) { + dc->base.pc_next = pc + 4; return; } - dc->pc_curr = dc->base.pc_next; - insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); + if (pc & 3) { + /* + * PC alignment fault. This has priority over the instruction abort + * that we would receive from a translation fault via arm_ldl_code + * (or the execution of the kernelpage entrypoint). This should only + * be possible after an indirect branch, at the start of the TB. + */ + assert(dc->base.num_insns == 1); + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); + dc->base.is_jmp = DISAS_NORETURN; + dc->base.pc_next = QEMU_ALIGN_UP(pc, 4); + return; + } + + if (arm_check_kernelpage(dc)) { + dc->base.pc_next = pc + 4; + return; + } + + dc->pc_curr = pc; + insn = arm_ldl_code(env, &dc->base, pc, dc->sctlr_b); dc->insn = insn; - dc->base.pc_next += 4; + dc->base.pc_next = pc + 4; disas_arm_insn(dc, insn); arm_post_translate_insn(dc); @@ -9615,7 +9640,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint32_t insn; bool is_16bit; - if (arm_pre_translate_insn(dc)) { + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { dc->base.pc_next += 2; return; } From patchwork Mon Sep 20 02:45:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514298 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1670216jao; Sun, 19 Sep 2021 19:51:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw1RucZ/pLTaTzN3FSPbuIzYzsCDqp4rrMt0Kc9NXZLMYbvS7LyjqG4vN6nFBbw61GrLNt8 X-Received: by 2002:a37:6708:: with SMTP id b8mr1203246qkc.283.1632106282802; Sun, 19 Sep 2021 19:51:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632106282; cv=none; d=google.com; s=arc-20160816; b=hwvobod7SClhjwoE9hzk+QD9Csx1Tt8vdN27RYVv0DM9AyYmruwGukG3SaZZW/wF30 V1swtjepvZgw/e7jYPxrlfWsi8vbCvXHILmx3r3C/EWN7a/6O6V3YuQfflcFnOauXsVg fV1YHJbquK9SQukWcVjEIxU2gz4E6Q8qQz5RNE3RAD/Dn3CkKSzXN665viKYhg3TmEiD RAaF5Iz0MCNebc3K8maT2CtGyUHZ5BWtQ3AeHHN457Mnu918Xj4y5/8fmyzvkfZ1pH8Q XUay1Pw4jnSdSXOQqCotS4BSRp5z3HDFfiYluShBdjy6+fdWWQBH0LwMyVt6GHSXhFs2 +MxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=w3KUOion9XWWhoPS4rc4FuBN5MtiU2iUhO/KyBmkvEs=; b=PloP5yB1x6a8CmYXpd+IXWuGgvqlqR49ok/hLU9OmwD0vBlPgTj80vQKbGpe9llJGy 7ODywN3hM3trpOiCm1Jga/LUHjb8mDKGZEtEYE5TMgvNO4IUnnC6K7ToRd06MK9P30mQ YqOfPKhkS4Vy39DfUrNsDquxSaLVJmuOVjXA38eA9jE59c70eGgLX6/bmQiLzC9MH6WB Ikf8qvv6E30euGTWKirUiNrjkbUIcYTqBuW3MucaNJQ4sj6I/rn/wzAoNPxpbriEwOK9 5hk/qK9BINnj0jPlaDqAHNYibraowU2fIbU05pk0/Y3M8EFxJj46k6U2xcmOUzhpupcA hgTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=B4RMbwu5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m22si3957961qkn.389.2021.09.19.19.51.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 19 Sep 2021 19:51:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=B4RMbwu5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51158 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mS9Os-0004Be-8p for patch@linaro.org; Sun, 19 Sep 2021 22:51:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57526) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mS9Iv-0005DH-Gg for qemu-devel@nongnu.org; Sun, 19 Sep 2021 22:45:14 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:38539) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mS9Is-0008EV-En for qemu-devel@nongnu.org; Sun, 19 Sep 2021 22:45:13 -0400 Received: by mail-pg1-x532.google.com with SMTP id w8so15859960pgf.5 for ; Sun, 19 Sep 2021 19:45:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w3KUOion9XWWhoPS4rc4FuBN5MtiU2iUhO/KyBmkvEs=; b=B4RMbwu5TdKbTQfxAy9Ztzg1LgicdEVJqzCH6kQbUMxCIFJ0sEZ3WizoT8BRgbbel8 72jrCt96XbJAy6drqW4X1HZGIrnLuIszI86af6p1dxWFg7kdihpM43fIB3LczlqbS2rQ Nw1NFoKW67jHdoiWT6GPvHHQjEXe59jDnYbk7vYGhp2LKiFbvkr84neH3/1JavJRPSYc M5UXHDKe8/okjiDkWsJSsehybeagkpxVD1m8phS5MNC3vsa65NfGNz9yhjmM1EcWInlX CbwXedybl+rE7n96MWtbGvPOrRtLdX8f6yigjRhx84ShSBNpaL73c4sUh0aITOYWpDU6 w+wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w3KUOion9XWWhoPS4rc4FuBN5MtiU2iUhO/KyBmkvEs=; b=wAKZ7DYkZcoAzhXVQ4d+Gbd2EUo9x8LSLqW/Iwicq7aNcuY023p88BTIH2U5JtE+aQ QCNII0Ytsx8srvB1L4BArcH0i54TO6u7TtYXZuJNcq9Vt38ed/VHfQqm0JFmVZzlLr1r kCdFgpEf7JK7qGKMmhV6wGe/xrw6+D62DNrE5c0z1HPRtL50ZB6PcVopmJbk5hftKGRg 5BTmiqhV75XlHCN1WXlv8/g8QFlIPOE5NuzBMzlDFfqKV6bDGzh75MYrD0vn0gO9qUkl h31m3jgjjPvyKfMkZpl8ISiUvhKB/p95ihzpYr04+JIUTGtShyNHyBAAcw61nOJFFNUG 5teg== X-Gm-Message-State: AOAM530tqmuYopG2e2EgFErNd6lxpq3pS7Zae00hrBluEfIYR/jqqIC5 3sSZWJ+ZOhYNF2Y5j6D9j8P6hVdUZoT4Yg== X-Received: by 2002:a05:6a00:c81:b029:30e:21bf:4c15 with SMTP id a1-20020a056a000c81b029030e21bf4c15mr22361978pfv.70.1632105909096; Sun, 19 Sep 2021 19:45:09 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id fh3sm16164767pjb.8.2021.09.19.19.45.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Sep 2021 19:45:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 4/6] target/arm: Assert thumb pc is aligned Date: Sun, 19 Sep 2021 19:45:02 -0700 Message-Id: <20210920024504.625965-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210920024504.625965-1-richard.henderson@linaro.org> References: <20210920024504.625965-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Misaligned thumb PC is architecturally impossible. Assert is better than proceeding, in case we've missed something somewhere. Expand a comment about aligning the pc in gdbstub. Fail an incoming migrate if a thumb pc is misaligned. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/gdbstub.c | 9 +++++++-- target/arm/machine.c | 9 +++++++++ target/arm/translate.c | 3 +++ 3 files changed, 19 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 826601b341..a54b42418b 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -76,8 +76,13 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) tmp = ldl_p(mem_buf); - /* Mask out low bit of PC to workaround gdb bugs. This will probably - cause problems if we ever implement the Jazelle DBX extensions. */ + /* + * Mask out low bits of PC to workaround gdb bugs. + * This avoids an assert in thumb_tr_translate_insn, because it is + * architecturally impossible to misalign the pc. + * This will probably cause problems if we ever implement the + * Jazelle DBX extensions. + */ if (n == 15) { tmp &= ~1; } diff --git a/target/arm/machine.c b/target/arm/machine.c index 81e30de824..b5004a67e9 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -781,6 +781,15 @@ static int cpu_post_load(void *opaque, int version_id) hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); + /* + * Misaligned thumb pc is architecturally impossible. + * We have an assert in thumb_tr_translate_insn to verify this. + * Fail an incoming migrate to avoid this assert. + */ + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { + return -1; + } + if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } diff --git a/target/arm/translate.c b/target/arm/translate.c index 62c396b880..e522cd2fbe 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9640,6 +9640,9 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint32_t insn; bool is_16bit; + /* Misaligned thumb PC is architecturally impossible. */ + assert((dc->base.pc_next & 1) == 0); + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { dc->base.pc_next += 2; return; From patchwork Mon Sep 20 02:45:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514297 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1669888jao; Sun, 19 Sep 2021 19:50:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwSFfCJcW4pIdIKNhb1Ti/FvC0bh/PQQvYt1BBcI/jKqJw0HBoM64T+1x3h7ac+cDxL4t+y X-Received: by 2002:a05:6214:146d:: with SMTP id c13mr23108683qvy.46.1632106252712; Sun, 19 Sep 2021 19:50:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632106252; cv=none; d=google.com; s=arc-20160816; b=WYKrlGn7PoldtzM7lqAu334SVH21l1/BASfj6+i/wdTQjDDJA+qrlzDj15Rz2U/MbE +vJeSGj6oYi5FuVR9xs5q+Z4afcwIE8XV2eNelwK10zM/DRi/EjTPSyWs36aJWVbWWw7 f4qpu0fUJztf84Npqni1ai+1rg2CfvLaWYBaxKfOhCLMTWEuXA2b/5Zwo1QSaMNusZDi XmgZcCAvLJpdYhj8Su6jqN6olBzbuVOO6F36D9gmGiCYLRUD9LAoWWnCa26hrfakfb4y 4/X8X83qLcT9dBKGsSwRTLF/6jHoW+uoWHZU6IH5lXve1+Ya9PNNQlv0keB2xnOIzVMm Owjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1GwQXaikJPOnXJQIMQ/JzNg2jCKDE196b7cKL2erVtk=; b=htp8VhUV+atwFpZMDcfkSrq1QoXe/feC3axKhUQx9fVxC25/V+PmEa2Wd7Xxzc2z0f 67rB617RqcvCZb6rK2X8JTbXY9hhYbF6Gmjl2CGjiyesyOPd3GIaXFPTt0Jd5CQpgCSW 2xq/mYjwfI26ilzlq6+lOb1mDIrzxgGVSLytYdpdmVW1+Y2L7K42nLdVtpUmpCwQd2tI 9RKkUk0x497g9JbClOx9UGOrzvvLPJxXMDzOZhuK1p3oKW0AN7xXFeO1qDLggoeoTZTk KuYN2MCeibyJPGgMQZcbp8C1F9fVvg10AtfC1auIexidu7p22buSKXtVf/HXB4GTpBrC ou8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=b59t+xSI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id bm40si3690166qkb.51.2021.09.19.19.50.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 19 Sep 2021 19:50:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=b59t+xSI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49960 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mS9OO-0003OK-7G for patch@linaro.org; Sun, 19 Sep 2021 22:50:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57542) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mS9Iw-0005DK-Gs for qemu-devel@nongnu.org; Sun, 19 Sep 2021 22:45:14 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:33738) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mS9Iu-0008Fr-L1 for qemu-devel@nongnu.org; Sun, 19 Sep 2021 22:45:14 -0400 Received: by mail-pl1-x62b.google.com with SMTP id t4so10114338plo.0 for ; Sun, 19 Sep 2021 19:45:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1GwQXaikJPOnXJQIMQ/JzNg2jCKDE196b7cKL2erVtk=; b=b59t+xSIgNEcDZu1q+PD3N4Lxi2N0VDrWDmYJ6T3JxH+8+sSykxh7as3gGkZ5tSXo/ /hona2CR2Ecl8Pg3dh6TY2YfjGwPUv3NDWUDXX3/3baPw9hIlRwb59imAtzXyxO6W0ch 0AMMdPzJ5u/WhVnLK/lMi6ip1PkaAM9fhAk3z6TefBbeiRMEh31vKHKRPaXcgIkANHJf +b9Clk6ncLvPicZo5LxJS3kKdv4HPnNyKcfuXnE2Z/Mf1am0VPVf9bIxytG7qP3mft80 vvLCQgguUq5tv49qHxJMitnESN+bfNvCTfNHMf/VeFOEa0j0sQODWNY53vVIM9ta5KHj FZJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1GwQXaikJPOnXJQIMQ/JzNg2jCKDE196b7cKL2erVtk=; b=xAXIicPyu2UmOvdLiVEuzFh91+MJ+kmgrMWMIoMTuto3BZSMi/zObUvOwls27tLuKG XIHRXVUFR9Pxvi9jjmsHcCA5WsIM3kfFG16xmu8X0WzGUibGy4mughKtM5Eu5y8uZqn8 y0nqeyI8b6cVk60IrCWer/tnjl2tr5NPL29Hl/7oApHHI109HeXOu3hy9J3Ct6fHi0Uy RCCcJ8a3NHC492Dd8OUAgNkTQEyyColwGk/qFemLjCiKO6n17weYTmtBQ8S2FkdHnb45 ZFOoFd4D2MLtGylgdeC60ymhJWADxtbcajixe8bgaU9zqMjq7f27KtVc8OBkc2jmxJ4t jI9A== X-Gm-Message-State: AOAM532kRLcwz3sAP0cbO5T4kZZij/x58YhC50qH7ro+/+Jyij+NXAr3 GwVXP/hOVXgWhgemsu5HUZDOIf7qrCAkaQ== X-Received: by 2002:a17:90a:19d8:: with SMTP id 24mr26935696pjj.57.1632105909850; Sun, 19 Sep 2021 19:45:09 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id fh3sm16164767pjb.8.2021.09.19.19.45.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Sep 2021 19:45:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 5/6] target/arm: Suppress bp for exceptions with more priority Date: Sun, 19 Sep 2021 19:45:03 -0700 Message-Id: <20210920024504.625965-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210920024504.625965-1-richard.henderson@linaro.org> References: <20210920024504.625965-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Both single-step and pc alignment faults have priority over breakpoint exceptions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/debug_helper.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) -- 2.25.1 diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 2983e36dd3..32f3caec23 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -220,6 +220,7 @@ bool arm_debug_check_breakpoint(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; + target_ulong pc; int n; /* @@ -231,6 +232,28 @@ bool arm_debug_check_breakpoint(CPUState *cs) return false; } + /* + * Single-step exceptions have priority over breakpoint exceptions. + * If single-step state is active-pending, suppress the bp. + */ + if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) { + return false; + } + + /* + * PC alignment faults have priority over breakpoint exceptions. + */ + pc = is_a64(env) ? env->pc : env->regs[15]; + if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) { + return false; + } + + /* + * Instruction aborts have priority over breakpoint exceptions. + * TODO: We would need to look up the page for PC and verify that + * it is present and executable. + */ + for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { if (bp_wp_matches(cpu, n, false)) { return true; From patchwork Mon Sep 20 02:45:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514296 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1669177jao; Sun, 19 Sep 2021 19:49:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxuOxf9Wf7tBRoASdLmWJGzd0BoWAykcoGEsBb2jlLlIH+zfyZ9mbTqat2MCRG5Y0Drxo2Q X-Received: by 2002:ac8:7756:: with SMTP id g22mr8717073qtu.160.1632106176072; Sun, 19 Sep 2021 19:49:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632106176; cv=none; d=google.com; s=arc-20160816; b=BxfYFFt7wbUhw2SF9DuKZVtfT6BKMUk2dtV1Od/lJuGgcrrZyXQlMPs4WoBLn/xEr+ 8iqgOI/v2HMRuO5v7zhY0Z2dpqL6xegZIYGZlOUJc0IiqSuV1BKGND3yYMo+dhN4rg81 5iOHBNuDkvt9xBAe1+90wuTaBuMZ2pPYKXz5e6iI3fEfDqm6Cb0cDktgox8p20jVA6Mk 9eKYvDutWIjadL4eoVUMyxeTeS3fvzHFkO0sYoA5il1/45RFQJq3Ha03B9POhxbLawZ/ as+fX52KzF7QAK+2j2Wpya8PxCnOxmc2A3mV0tuQ+X4e860nKV4Pk0MjFJCIMukM0sMa epMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=j3xcIy2m2TMlH3aTyvVTXEM5j7IHz1QAadoWnnY7f2s=; b=rTadYYaPpIhUKhg14CDvm27+sdFbA063n0asBUVw5KzEsdz9mkvxAHSi3Oy+vRG+RO oQqsM0VNfepS2S8HmzBbPBLff1mB4GX4Pe/RLax2XkkZE2cK1o3h8old4NlwEUaMNqtU YlCxBkIc/H7MVavrBvzSFE4HrY8oMb/jNsJJbegyCtx1J3Ap0Wi74KD6mnzz8OUcKy8k dSOdg7RcKej/86FYauIQ3fwNa58g1kmUrK2v3HzpBSQqtM9zzEVkfKOLKVQ1wtN2cXbN rEvbZdVb32BZtBFG1591P5MlUgEwhxjBf4gh8GjBgMnOyr4HEL4Jg+ldAeJ7y5uOngMn 6ZOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="gQfk2n/a"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Sun, 19 Sep 2021 19:45:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 6/6] tests/tcg: Add arm and aarch64 pc alignment tests Date: Sun, 19 Sep 2021 19:45:04 -0700 Message-Id: <20210920024504.625965-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210920024504.625965-1-richard.henderson@linaro.org> References: <20210920024504.625965-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tests/tcg/aarch64/pcalign-a64.c | 37 +++++++++++++++++++++++++ tests/tcg/arm/pcalign-a32.c | 46 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 4 +-- tests/tcg/arm/Makefile.target | 4 +++ 4 files changed, 89 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/aarch64/pcalign-a64.c create mode 100644 tests/tcg/arm/pcalign-a32.c -- 2.25.1 diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a64.c new file mode 100644 index 0000000000..6b9277f919 --- /dev/null +++ b/tests/tcg/aarch64/pcalign-a64.c @@ -0,0 +1,37 @@ +/* Test PC misalignment exception */ + +#include +#include +#include +#include + +static void *expected; + +static void sigbus(int sig, siginfo_t *info, void *vuc) +{ + assert(info->si_code == BUS_ADRALN); + assert(info->si_addr == expected); + exit(EXIT_SUCCESS); +} + +int main() +{ + void *tmp; + + struct sigaction sa = { + .sa_sigaction = sigbus, + .sa_flags = SA_SIGINFO + }; + + if (sigaction(SIGBUS, &sa, NULL) < 0) { + perror("sigaction"); + return EXIT_FAILURE; + } + + asm volatile("adr %0, 1f + 1\n\t" + "str %0, %1\n\t" + "br %0\n" + "1:" + : "=&r"(tmp), "=m"(expected)); + abort(); +} diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c new file mode 100644 index 0000000000..3c9c8cc97b --- /dev/null +++ b/tests/tcg/arm/pcalign-a32.c @@ -0,0 +1,46 @@ +/* Test PC misalignment exception */ + +#ifdef __thumb__ +#error "This test must be compiled for ARM" +#endif + +#include +#include +#include +#include + +static void *expected; + +static void sigbus(int sig, siginfo_t *info, void *vuc) +{ + assert(info->si_code == BUS_ADRALN); + assert(info->si_addr == expected); + exit(EXIT_SUCCESS); +} + +int main() +{ + void *tmp; + + struct sigaction sa = { + .sa_sigaction = sigbus, + .sa_flags = SA_SIGINFO + }; + + if (sigaction(SIGBUS, &sa, NULL) < 0) { + perror("sigaction"); + return EXIT_FAILURE; + } + + asm volatile("adr %0, 1f + 2\n\t" + "str %0, %1\n\t" + "bx %0\n" + "1:" + : "=&r"(tmp), "=m"(expected)); + + /* + * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns + * the address or not. If so, we can legitimately fall through. + */ + return EXIT_SUCCESS; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 2c05c90d17..1d967901bd 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -8,8 +8,8 @@ VPATH += $(ARM_SRC) AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64 VPATH += $(AARCH64_SRC) -# Float-convert Tests -AARCH64_TESTS=fcvt +# Base architecture tests +AARCH64_TESTS=fcvt pcalign-a64 fcvt: LDFLAGS+=-lm diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target index 5ab59ed6ce..f509d823d4 100644 --- a/tests/tcg/arm/Makefile.target +++ b/tests/tcg/arm/Makefile.target @@ -29,6 +29,10 @@ run-fcvt: fcvt $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) +# PC alignment test +ARM_TESTS += pcalign-a32 +pcalign-a32: CFLAGS+=-marm + ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y) # Semihosting smoke test for linux-user