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[209.51.188.17]) by mx.google.com with ESMTPS id u28si5969471qtc.425.2021.09.18.11.47.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 11:47:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OfcFIhVa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35874 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfNV-0004yu-6r for patch@linaro.org; Sat, 18 Sep 2021 14:47:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54040) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLC-0004yO-RK for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:34 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:36538) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLA-0006gV-2V for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:34 -0400 Received: by mail-pj1-x1035.google.com with SMTP id u13-20020a17090abb0db0290177e1d9b3f7so12336326pjr.1 for ; Sat, 18 Sep 2021 11:45:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MwSLIpZg3SBDOkqorWI9RwSF0cto2aAplNrO4o3oH4g=; b=OfcFIhVaDEiEzOK/rX+3aeV5ZbEHksw7k5lRIrl80/Siq9JyTSHhmSvXnIZluCCKBu o5HB9T9YTynZqHWwmThHk3sgWmB72P9tWfiR+E/jotKGZ1xU8904lLqjZ+e6o8c58MA8 OIrnCss3CO/kbhUAkncFYf8Dmal0fuCiWOjlFkwK6quCut4B0irXv/q9KukwcX6dD6Nj 9Z4kYt9myZ9d9D9yH6qGaD3ZNLJVPZOzoCy1ywhyUu82/BbeZ7lU20TL6xKCL0kbN2AZ E6zz/jLMMR9y03KJ33pqLlo72LlxK9z4h2mgfIylYpCzq9G3s7Urim1yMyslfhOFI14/ Aznw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MwSLIpZg3SBDOkqorWI9RwSF0cto2aAplNrO4o3oH4g=; b=MoGkVLtURgss5tw5KNT0713C4AH8EH9YDfaD0m0cCk+Pa52yuYr4QFYHAELXTPL9fn GqVl434CPkGBJy+pLWq459Mwax4VLqdZsBk9UZNQo78r0YKLZeB8hPfwHd2KS7kcSXGr p1Uk7WcZuHlIEzpQ3D/Fb7GJyWKqbNoS98QEAE70eDaW82Yhhl6scVMzNczya2aaQARJ dMoWXBcnd+3jVAnKA0kXCNsJBC9+2ow2gbrwAfmbF8qrin+Kr5IH11LFvGxKY7YPj19+ kvi+rot45Eo0xu2joGz7idSUsQdhIDEODeuuzT+YDF7mMUowTJyf7t5QjYKopArU8gvh HcyA== X-Gm-Message-State: AOAM530Yr61kODscYa+5V2l7Hzkf1b4hT70Q3IOC8EoLRTpOOFkcmN/r aLWxAkUfoIfOQSBPyw+dFZCAFZbG380o7A== X-Received: by 2002:a17:90a:1d4c:: with SMTP id u12mr19050420pju.95.1631990730360; Sat, 18 Sep 2021 11:45:30 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 01/41] accel/tcg: Split out adjust_signal_pc Date: Sat, 18 Sep 2021 11:44:47 -0700 Message-Id: <20210918184527.408540-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out a function to adjust the raw signal pc into a value that could be passed to cpu_restore_state. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Adjust pc in place; return MMUAccessType. --- include/exec/exec-all.h | 10 ++++++++++ accel/tcg/user-exec.c | 41 +++++++++++++++++++++++++---------------- 2 files changed, 35 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 9d5987ba04..e54f8e5d65 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -663,6 +663,16 @@ static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, return addr; } +/** + * adjust_signal_pc: + * @pc: raw pc from the host signal ucontext_t. + * @is_write: host memory operation was write, or read-modify-write. + * + * Alter @pc as required for unwinding. Return the type of the + * guest memory access -- host reads may be for guest execution. + */ +MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); + /** * cpu_signal_handler * @signum: host signal number diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 8fed542622..cef025d001 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -57,18 +57,11 @@ static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu, cpu_loop_exit_noexc(cpu); } -/* 'pc' is the host PC at which the exception was raised. 'address' is - the effective address of the memory exception. 'is_write' is 1 if a - write caused the exception and otherwise 0'. 'old_set' is the - signal set which should be restored */ -static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, - int is_write, sigset_t *old_set) +/* + * Adjust the pc to pass to cpu_restore_state; return the memop type. + */ +MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write) { - CPUState *cpu = current_cpu; - CPUClass *cc; - unsigned long address = (unsigned long)info->si_addr; - MMUAccessType access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; - switch (helper_retaddr) { default: /* @@ -77,7 +70,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * pointer into the generated code that will unwind to the * correct guest pc. */ - pc = helper_retaddr; + *pc = helper_retaddr; break; case 0: @@ -97,7 +90,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * Therefore, adjust to compensate for what will be done later * by cpu_restore_state_from_tb. */ - pc += GETPC_ADJ; + *pc += GETPC_ADJ; break; case 1: @@ -113,12 +106,28 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * * Like tb_gen_code, release the memory lock before cpu_loop_exit. */ - pc = 0; - access_type = MMU_INST_FETCH; mmap_unlock(); - break; + *pc = 0; + return MMU_INST_FETCH; } + return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; +} + +/* + * 'pc' is the host PC at which the exception was raised. + * 'address' is the effective address of the memory exception. + * 'is_write' is 1 if a write caused the exception and otherwise 0. + * 'old_set' is the signal set which should be restored. + */ +static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, + int is_write, sigset_t *old_set) +{ + CPUState *cpu = current_cpu; + CPUClass *cc; + unsigned long address = (unsigned long)info->si_addr; + MMUAccessType access_type = adjust_signal_pc(&pc, is_write); + /* For synchronous signals we expect to be coming from the vCPU * thread (so current_cpu should be valid) and either from running * code or during translation which can fault as we cross pages. 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Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 3 ++- accel/tcg/user-exec.c | 2 -- 2 files changed, 2 insertions(+), 3 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5fd1ed3422..410588d08a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -451,6 +451,7 @@ void cpu_exec_step_atomic(CPUState *cpu) * memory. */ #ifndef CONFIG_SOFTMMU + clear_helper_retaddr(); tcg_debug_assert(!have_mmap_lock()); #endif if (qemu_mutex_iothread_locked()) { @@ -460,7 +461,6 @@ void cpu_exec_step_atomic(CPUState *cpu) qemu_plugin_disable_mem_helpers(cpu); } - /* * As we start the exclusive region before codegen we must still * be in the region if we longjump out of either the codegen or @@ -905,6 +905,7 @@ int cpu_exec(CPUState *cpu) #endif #ifndef CONFIG_SOFTMMU + clear_helper_retaddr(); tcg_debug_assert(!have_mmap_lock()); #endif if (qemu_mutex_iothread_locked()) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index cef025d001..e94f1fed00 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -175,7 +175,6 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * currently executing TB was modified and must be exited * immediately. Clear helper_retaddr for next execution. */ - clear_helper_retaddr(); cpu_exit_tb_from_sighandler(cpu, old_set); /* NORETURN */ @@ -193,7 +192,6 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * an exception. Undo signal and retaddr state prior to longjmp. */ sigprocmask(SIG_SETMASK, old_set, NULL); - clear_helper_retaddr(); cc = CPU_GET_CLASS(cpu); cc->tcg_ops->tlb_fill(cpu, address, 0, access_type, From patchwork Sat Sep 18 18:44:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514218 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp665744jao; Sat, 18 Sep 2021 11:47:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxBl4hdk0BLtm4qZGeoqiqh8sWdB5xL4MQIF63+TDotMBA3/YclMvRwANN8ct1b4FlhZ/sz X-Received: by 2002:a0c:aa8d:: with SMTP id f13mr17643932qvb.31.1631990879225; Sat, 18 Sep 2021 11:47:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631990879; cv=none; d=google.com; s=arc-20160816; b=l6PsZfi9R7zuEsC9BU+uFWuK042kilivBNAAmV8tzL7mhAkxk+gZr7dd4vwcWPnrjq 1tteW3u7iu3lfIMB+M6Ax2hlAZ03zfVZncWpc4Ii9mP41W4ku3wPlmAQ9xvJ/6VAoKUJ mdwRaXJHAonAwrHfJmOx4sab3jjYEDOM92iwJv2I8K0OcowRzl+W8xefxxyVxDW1NqeK jz5nDjtVIXp4BrNmR1XcbOb5P58DhqJeLD2WfKoYLBsfJFxc07allGLu6rYpJ+rfslgS D7RJWaNYnQr2EPQyeHiGttimltV+Pfva1joyOWnqRj8CuXtO9JuBQsT1tW1unuEh081k Nrxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=d0XAyTZlMLuZKO7GS2lQ57aRasECVtACHoF9DI2hSaY=; b=udDE8d4mlhKpxenhNT3Gb0R4H498TljHXD/ir1Tyn6EMYrqnS565LcHxd4TFNcGRL+ 8PvydEFF3M7OGAYH0NDAII9cMk+eUhV5EBQtS4Ag7PsK3gwrNyje0pDulTipLuxbZA/q VZ34i33N5JNee6C0fD045MPv9tNQbFoREiDtkwqQBhAevQeZwc1SY9eSoFXIOQDgojNz 8hK9UO73P5mbdlq32Eyg7Q6ymj/gqOJfY9nVJ9+oihTDGd9X2I4sj2/YVj4pPuUpXDwx 31eEbKL/F5OIk+i7V9NjfuUaG8xwq0doyu5eEJAPHP5XhdvbE9yKXN05K2p6aZulRsvT 9TuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XgZYrKNb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s12si2772397qta.72.2021.09.18.11.47.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 11:47:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XgZYrKNb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfNW-000507-Nt for patch@linaro.org; Sat, 18 Sep 2021 14:47:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54100) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLF-0004yc-9f for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:37 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:33284) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLC-0006iJ-DF for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:37 -0400 Received: by mail-pl1-x62f.google.com with SMTP id t4so8427277plo.0 for ; Sat, 18 Sep 2021 11:45:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d0XAyTZlMLuZKO7GS2lQ57aRasECVtACHoF9DI2hSaY=; b=XgZYrKNbCuJ25En3uFCieCBRkoENjIqeZk7KdwjA9HS0Um0PsAtaHD/KoqFdN9rkfd yH7PB8SfdzukttMDyyPOSTYqFg1q9v9nJOlYF5VB9Gt7tZeDGHgihnbKpB8YjQzPEL18 p+0dEy5Uwg/91VveahU8cXvlKfmB0B2sxKYb0FWTVo5VeaWg47XGbWm+yoxmrJmy/qSb d5TX4bDJTy9t/gKOKR74dldyu/EgN1xl255se+KJwuMoGmZE5BP+kdqtLDMwzlJ5Al+F b72eKoYRKA4to/wxE7gbXSKhRRPI+hedR7Gf9pw7TRBXVJFuNbiBNzB2gjm1mrviMf87 VNKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d0XAyTZlMLuZKO7GS2lQ57aRasECVtACHoF9DI2hSaY=; b=UvItkHpX+bDMkuO1UUP6fcLIpzryCU68CJ8WmjL12MSJsTiHbI4VVyBdHHAg48NFG7 pUwhfyvtyahhRilpbTPhhJyeczeVd4XUDb5i6ol3gir/2DM7y9mdjToY7zEdLzMGCMw/ tOkS6PBckhln/YldSlrjucXafVIxwIA/X3LQkUKzP2MCKaLAnZO5bDI8D3IRf6UdN6fm +5UHuG+bTOorkAFxKFTUJ6cH/ssyx4opi02jGP1QOigLqTVzrQWIOSEhOuYU9SRQ0tCB 4hkeejWPcmFLpE7O+9VZe6WmsAfxyAL1l+C/2eo2jWMbAIY34HoK6xf8/d/0sUKvDLPb jNyw== X-Gm-Message-State: AOAM530QFuI0OncgR6IvG6ZjpixBcEN1fGzt7sCacORJ9r1NNsLr8b3c OCnUDpKTEcGC7uhv1TE6tFBR1tyR3eWBFA== X-Received: by 2002:a17:90a:4b83:: with SMTP id i3mr19580389pjh.22.1631990731929; Sat, 18 Sep 2021 11:45:31 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 03/41] accel/tcg: Split out handle_sigsegv_accerr_write Date: Sat, 18 Sep 2021 11:44:49 -0700 Message-Id: <20210918184527.408540-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the major portion of handle_cpu_signal which is specific to tcg, handling the page protections for the translations. Most of the rest will migrate to linux-user/ shortly. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Pass guest address to handle_sigsegv_accerr_write. --- include/exec/exec-all.h | 12 +++++ accel/tcg/user-exec.c | 103 ++++++++++++++++++++++++---------------- 2 files changed, 74 insertions(+), 41 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index e54f8e5d65..5f94d799aa 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -673,6 +673,18 @@ static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, */ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); +/** + * handle_sigsegv_accerr_write: + * @cpu: the cpu context + * @old_set: the sigset_t from the signal ucontext_t + * @host_pc: the host pc, adjusted for the signal + * @host_addr: the host address of the fault + * + * Return true if the write fault has been handled, and should be re-tried. + */ +bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, + uintptr_t host_pc, abi_ptr guest_addr); + /** * cpu_signal_handler * @signum: host signal number diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e94f1fed00..6f4fc01b60 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -114,6 +114,54 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write) return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; } +/** + * handle_sigsegv_accerr_write: + * @cpu: the cpu context + * @old_set: the sigset_t from the signal ucontext_t + * @host_pc: the host pc, adjusted for the signal + * @guest_addr: the guest address of the fault + * + * Return true if the write fault has been handled, and should be re-tried. + * + * Note that it is important that we don't call page_unprotect() unless + * this is really a "write to nonwriteable page" fault, because + * page_unprotect() assumes that if it is called for an access to + * a page that's writeable this means we had two threads racing and + * another thread got there first and already made the page writeable; + * so we will retry the access. If we were to call page_unprotect() + * for some other kind of fault that should really be passed to the + * guest, we'd end up in an infinite loop of retrying the faulting access. + */ +bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, + uintptr_t host_pc, abi_ptr guest_addr) +{ + switch (page_unprotect(guest_addr, host_pc)) { + case 0: + /* + * Fault not caused by a page marked unwritable to protect + * cached translations, must be the guest binary's problem. + */ + return false; + case 1: + /* + * Fault caused by protection of cached translation; TBs + * invalidated, so resume execution. Retain helper_retaddr + * for a possible second fault. + */ + return true; + case 2: + /* + * Fault caused by protection of cached translation, and the + * currently executing TB was modified and must be exited + * immediately. Clear helper_retaddr for next execution. + */ + cpu_exit_tb_from_sighandler(cpu, old_set); + /* NORETURN */ + default: + g_assert_not_reached(); + } +} + /* * 'pc' is the host PC at which the exception was raised. * 'address' is the effective address of the memory exception. @@ -125,8 +173,9 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, { CPUState *cpu = current_cpu; CPUClass *cc; - unsigned long address = (unsigned long)info->si_addr; + unsigned long host_addr = (unsigned long)info->si_addr; MMUAccessType access_type = adjust_signal_pc(&pc, is_write); + abi_ptr guest_addr; /* For synchronous signals we expect to be coming from the vCPU * thread (so current_cpu should be valid) and either from running @@ -143,49 +192,21 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, #if defined(DEBUG_SIGNAL) printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", - pc, address, is_write, *(unsigned long *)old_set); + pc, host_addr, is_write, *(unsigned long *)old_set); #endif - /* XXX: locking issue */ - /* Note that it is important that we don't call page_unprotect() unless - * this is really a "write to nonwriteable page" fault, because - * page_unprotect() assumes that if it is called for an access to - * a page that's writeable this means we had two threads racing and - * another thread got there first and already made the page writeable; - * so we will retry the access. If we were to call page_unprotect() - * for some other kind of fault that should really be passed to the - * guest, we'd end up in an infinite loop of retrying the faulting - * access. - */ - if (is_write && info->si_signo == SIGSEGV && info->si_code == SEGV_ACCERR && - h2g_valid(address)) { - switch (page_unprotect(h2g(address), pc)) { - case 0: - /* Fault not caused by a page marked unwritable to protect - * cached translations, must be the guest binary's problem. - */ - break; - case 1: - /* Fault caused by protection of cached translation; TBs - * invalidated, so resume execution. Retain helper_retaddr - * for a possible second fault. - */ - return 1; - case 2: - /* Fault caused by protection of cached translation, and the - * currently executing TB was modified and must be exited - * immediately. Clear helper_retaddr for next execution. - */ - cpu_exit_tb_from_sighandler(cpu, old_set); - /* NORETURN */ - - default: - g_assert_not_reached(); - } - } /* Convert forcefully to guest address space, invalid addresses are still valid segv ones */ - address = h2g_nocheck(address); + guest_addr = h2g_nocheck(host_addr); + + /* XXX: locking issue */ + if (is_write && + info->si_signo == SIGSEGV && + info->si_code == SEGV_ACCERR && + h2g_valid(host_addr) && + handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) { + return 1; + } /* * There is no way the target can handle this other than raising @@ -194,7 +215,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, sigprocmask(SIG_SETMASK, old_set, NULL); cc = CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, address, 0, access_type, + cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, MMU_USER_IDX, false, pc); g_assert_not_reached(); } From patchwork Sat Sep 18 18:44:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514222 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp667548jao; Sat, 18 Sep 2021 11:51:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw2+DrhZhGlznbTGOwEqNpdJDuUqkdFdzuA/+YAX4jiJ2OY+g6sIyG5OLgwgXCwuQeCISdn X-Received: by 2002:a37:61c9:: with SMTP id v192mr4333718qkb.209.1631991082328; Sat, 18 Sep 2021 11:51:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631991082; cv=none; d=google.com; s=arc-20160816; b=m3s3ktaiKgCLwpu6nWc5z/033mTvZsLIPnVVDFdIPCPEVDDtXQk0dneYdy/9Xi7xTg aPu2Z5vm3UekTT3rJYiEmemky8AlWdGmeKpVVYTxLOd+3jB91nwlvt+MJCj+s7q8vlPY ErgkzfkZBu1LSPV87TRaEm86A3qE42A4QzmstGBXC38Y23B9Ocm74SfeH2eCrDi50QDN xK5f32N7S/yNCdJZZTPd3MUep+9uz0ysbjTOOrssPeBB0hf33WynSF3dbYHGilAN/0h7 h941juh45zIr1j91hUe/08jLmfSW77uUGa14+yLevWc1IUSox29Mr26tx6uy+h+n+ALf ypFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lQDDeP4KrE59xBXWzR54VwCb3z15HLMlRMki+IJBEEo=; b=jyifqb+dT7D9ZUcMAvAHjKmQ0yuVX5VpNONJkMt+F9xpbyHe9D6AXuSIY921WEAaXl 9HaBz01hItQzVxooXcoWGqt1zZuqxv7LKzdkRxHnefMnvYzMCTUs8j146ouhPJqCEFuQ /XhwoZ2qFbQNV5yQPHKbZv9w6E2XalvxF0tc4GSSzvrCdjREXrwna9iLZabdOdj0LTC3 L1aP2dF48Msqg/bUr8I5mG3IW5XWSqaP591n2+rQ+5c0FhUbAv9qVMK0WSI+0e1j63IS 69robZKxtcH6cHJ1sCNkp69ugfoppoN0N6EPBKg6VIrB9cIyEhV4Ipa0L4Tgg/BRc7HP Y5Bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KGm835s9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n6si6713570qtl.291.2021.09.18.11.51.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 11:51:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KGm835s9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44686 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfQn-0002VJ-Sj for patch@linaro.org; Sat, 18 Sep 2021 14:51:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLF-0004ye-K7 for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:38 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:35629) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLC-0006iN-DN for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:37 -0400 Received: by mail-pf1-x42b.google.com with SMTP id w14so1833654pfu.2 for ; Sat, 18 Sep 2021 11:45:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lQDDeP4KrE59xBXWzR54VwCb3z15HLMlRMki+IJBEEo=; b=KGm835s966tjMmfvd6b/RMcBfUGuOPVjiDmNrxjcG4KnP20QHjSauF2tdYiges49bA bGFnIfPlAqz3gcSx/62aK17PuEPc6nEcxXLTDkbcM/eEEAmkGHkr9haNMgDig+fl6Vl+ fPAqQqe6bWHshZ/Xfa69Anvo24HaewSTijOWWq4EEt07UzwKHkZ9FuzrrJCUWCpy1h4b LW1mouTDpCCqg9ha7NGmGV+RUTLHOyg2WJidaUTmKTmpCsoTwTdfM12Z0fnvsUI4Oxi9 oLszelP8s7nQJmGrimGBHSlZkpO9oeuF1G9JHezxEFlzRHlSU3qoR0l95W4nsr+jIatH bKBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lQDDeP4KrE59xBXWzR54VwCb3z15HLMlRMki+IJBEEo=; b=dbDbgBY2iPsNoQfyQ9a0VgzSQCjF+hfNDpYHlaMDh5CQ+4CLkSaRu6flk3/OIOf7OQ WBmnRPJnYbAT5H89zT5Y/ilqYMM/ZFGv3SUPT9pNhYUOYTODS+gUSK+d4GF8Jc9byuFr JtQqLZH8m+0zEg8g+Qfuj9Wl4VZ8Fi6TCExtbAQvASmWnKFDuOGE/8JS6y5Q5SvuTghF 8QSP0+l59suZG0mTvnH7VW52hFQhNoAksVNBsmxpARX7Ndkx/JMyzDye4a0Tvc6w4Olp xUpc5m1mfdzOdnx8IRrT+R5gdNVf6hHkM71wRg79CpFZuwU0+IdbSUwFJqrkuBW+tqXl XIoQ== X-Gm-Message-State: AOAM5309rH+mwDJaM/y5FYlxp1dKuS9BzPSYwbr22O30C/KoXVrAW5+l 8AEK37n0b/XDWTEqWmQ1glcUBYG3RuLRJA== X-Received: by 2002:a63:fe41:: with SMTP id x1mr15969970pgj.272.1631990732649; Sat, 18 Sep 2021 11:45:32 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 04/41] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Date: Sat, 18 Sep 2021 11:44:50 -0700 Message-Id: <20210918184527.408540-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the comment about siglongjmp. We do use sigsetjmp in the main cpu loop, but we do not save the signal mask as most exits from the cpu loop do not require them. Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 6f4fc01b60..de4565f13e 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -46,17 +46,6 @@ __thread uintptr_t helper_retaddr; //#define DEBUG_SIGNAL -/* exit the current TB from a signal handler. The host registers are - restored in a state compatible with the CPU emulator - */ -static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu, - sigset_t *old_set) -{ - /* XXX: use siglongjmp ? */ - sigprocmask(SIG_SETMASK, old_set, NULL); - cpu_loop_exit_noexc(cpu); -} - /* * Adjust the pc to pass to cpu_restore_state; return the memop type. */ @@ -155,7 +144,8 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, * currently executing TB was modified and must be exited * immediately. Clear helper_retaddr for next execution. */ - cpu_exit_tb_from_sighandler(cpu, old_set); + sigprocmask(SIG_SETMASK, old_set, NULL); + cpu_loop_exit_noexc(cpu); /* NORETURN */ default: g_assert_not_reached(); From patchwork Sat Sep 18 18:44:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514224 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp668515jao; Sat, 18 Sep 2021 11:53:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyJvQ+8mK4y56dK26z3emgm4FXiKMKF1m2WPAYENIAZoeX+VDNCAknGDd2CN+LCbKvO/bgC X-Received: by 2002:a0c:9c48:: with SMTP id w8mr17102297qve.65.1631991194335; Sat, 18 Sep 2021 11:53:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631991194; cv=none; d=google.com; s=arc-20160816; b=DfxpafxRkWJIKHPM385bVMSA5o0ZRM+VuVzRIPQpv8aO+mCaNgAY2Xqh81mf97Yiri mkzQJemFmtbGEzeOrdZdYRGGA2K5sB/ziXuYMzH0B+URhSx0GFTGY7NSCAxOo+XCrMT8 IEJEkHWbcBWsCaL9VX7iTGF0g31gaHb5pWP3GcBfCfDZZF9Vb9s9Sd5spY68c+9OmU2x PI8KufvM+h8Kw6ZVodXdy1QHu286ZskfcLV9gusVz0SazHLg+YN8t85YPrPwbuUD3T30 DAz9RFiZoy5P57oa6jnm3m618ylRMP4TCSTRlrg5hFIfINpJ21GOnXDEerAlhySbvyOi Q22Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jNytvLeKtUgPrmZI/TBw9N43J3yDkQk24XcXM4krLhk=; b=ijjSTYUBT81lpUshODyFWDafr1FdCjwbN0PF2XqgQse2U9CUa0zHTeUFoXMDBDqmhD 4lzYdTw7MLMx5Nt+wl5KKxZcHIebCeA2vW4Xj6mU0x6U9OMT+wkvZLaw/Ti/AZjWMRor MNMdO6Wv+Oj8FAlmySogJH7nAp1bo12yr88MzTzBem/oi09bEJLCiHxjKKUE++VFIpHX RZjcZup7epuK8i8UKs3RTohV6b9JLBG3F+zRs7DQXN9VM8NWRMTkr55+cAedV4keaJzf CSiycip3c68z5zWND4i9fXoxTyWEfaiWYyrMWvE3QaiUAOuGvyIeAoDeVyTLPu6O6sa1 dirg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xQ+e4HNf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x6si1696067qko.34.2021.09.18.11.53.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 11:53:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xQ+e4HNf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52904 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfSb-00082d-S5 for patch@linaro.org; Sat, 18 Sep 2021 14:53:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54096) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLF-0004yb-5y for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:37 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:35550) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLC-0006iW-Ph for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:36 -0400 Received: by mail-pj1-x1030.google.com with SMTP id f3-20020a17090a638300b00199097ddf1aso12370427pjj.0 for ; Sat, 18 Sep 2021 11:45:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jNytvLeKtUgPrmZI/TBw9N43J3yDkQk24XcXM4krLhk=; b=xQ+e4HNflx/kFwy7DlYyzkV0zwhlsRq2X9B94zZoYQUnj46+cXRIX9rD955pR2e4Yc /XDfFyNr4/QdC+Rhttsy7c2DG6DvjN5weSrF+aVah5ZXyxIjFIfuzcQb4hrX57EBQxDP ZAI8Qkrkuf9Tv1/+AMP8yMciqdhQpEEwlnB2L8prjECrkqgfGGRyY3J/ubGTCvYlRL3K HUGAOO5ZryGNpYTIvbJClA1/frftoKZzhzrhWg6pK+cEKK8WIrAYwOjz2JNRIexBc+wC +FPCweNcqLKza0n3u8UiZZznNM7U1UAq/2rl8nXbNgI88zfvvHYC2m/W2f8HiEHbRyuy 5nfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jNytvLeKtUgPrmZI/TBw9N43J3yDkQk24XcXM4krLhk=; b=eSR7KzaPrLZ2mC4uZQG+JANsyi/EFe493+Ap9L1NfeGBP9Pe8YEBKb8Rj04SgSkiIm 4p500jF7otEPulgn4EzXyfTPJWVIx83pk2c3x4LVhj2/9YyS+5PQIpDzBK1YGamsARZV 5M7jybSfMRmK7fjbepIloibFx+m7grlPCKhkarqNNqwgbwe5JOq05q1BA7gDf1aybFdG K31IorPtDMBUPF4do7mZ0Jra3qYEoUASi/+W57A2ATIpcCXACkQ+qUlVTmnsjPcQOUif OwUy9Ki6shFvKhLjMazYBd1XsfDwXxAAIrV7WKx7N/5aInNn7DnEp/VNg/m6Ld45qk0f kYHw== X-Gm-Message-State: AOAM530GjB04d8pmg8xSbHVMFrdw4g7lcP4B/lG6EbpRATzf/U0JgJfA ngvAXNXtHhJkcnWEnviP/5767M79MvTBOw== X-Received: by 2002:a17:90b:1d02:: with SMTP id on2mr28136937pjb.21.1631990733547; Sat, 18 Sep 2021 11:45:33 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 05/41] configure: Merge riscv32 and riscv64 host architectures Date: Sat, 18 Sep 2021 11:44:51 -0700 Message-Id: <20210918184527.408540-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The existing code for safe-syscall.inc.S will compile without change for riscv32 and riscv64. We may also drop the meson.build stanza that merges them for tcg/. Signed-off-by: Richard Henderson --- configure | 8 ++------ meson.build | 4 +--- linux-user/host/{riscv64 => riscv}/hostdep.h | 4 ++-- linux-user/host/riscv32/hostdep.h | 11 ----------- linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S | 0 5 files changed, 5 insertions(+), 22 deletions(-) rename linux-user/host/{riscv64 => riscv}/hostdep.h (94%) delete mode 100644 linux-user/host/riscv32/hostdep.h rename linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S (100%) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis diff --git a/configure b/configure index da2501489f..6ff037bac1 100755 --- a/configure +++ b/configure @@ -650,11 +650,7 @@ elif check_define __s390__ ; then cpu="s390" fi elif check_define __riscv ; then - if check_define _LP64 ; then - cpu="riscv64" - else - cpu="riscv32" - fi + cpu="riscv" elif check_define __arm__ ; then cpu="arm" elif check_define __aarch64__ ; then @@ -667,7 +663,7 @@ ARCH= # Normalise host CPU name and set ARCH. # Note that this case should only have supported host CPUs, not guests. case "$cpu" in - ppc|ppc64|s390x|sparc64|x32|riscv32|riscv64) + ppc|ppc64|s390x|sparc64|x32|riscv) ;; ppc64le) ARCH="ppc64" diff --git a/meson.build b/meson.build index 2711cbb789..c35a230bf0 100644 --- a/meson.build +++ b/meson.build @@ -56,7 +56,7 @@ have_block = have_system or have_tools python = import('python').find_installation() supported_oses = ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', 'sunos', 'linux'] -supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', 'x86_64', +supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64', 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] cpu = host_machine.cpu_family() @@ -271,8 +271,6 @@ if not get_option('tcg').disabled() tcg_arch = 'i386' elif config_host['ARCH'] == 'ppc64' tcg_arch = 'ppc' - elif config_host['ARCH'] in ['riscv32', 'riscv64'] - tcg_arch = 'riscv' endif add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' / tcg_arch, language: ['c', 'cpp', 'objc']) diff --git a/linux-user/host/riscv64/hostdep.h b/linux-user/host/riscv/hostdep.h similarity index 94% rename from linux-user/host/riscv64/hostdep.h rename to linux-user/host/riscv/hostdep.h index 865f0fb9ff..2ba07456ae 100644 --- a/linux-user/host/riscv64/hostdep.h +++ b/linux-user/host/riscv/hostdep.h @@ -5,8 +5,8 @@ * See the COPYING file in the top-level directory. */ -#ifndef RISCV64_HOSTDEP_H -#define RISCV64_HOSTDEP_H +#ifndef RISCV_HOSTDEP_H +#define RISCV_HOSTDEP_H /* We have a safe-syscall.inc.S */ #define HAVE_SAFE_SYSCALL diff --git a/linux-user/host/riscv32/hostdep.h b/linux-user/host/riscv32/hostdep.h deleted file mode 100644 index adf9edbf2d..0000000000 --- a/linux-user/host/riscv32/hostdep.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef RISCV32_HOSTDEP_H -#define RISCV32_HOSTDEP_H - -#endif diff --git a/linux-user/host/riscv64/safe-syscall.inc.S b/linux-user/host/riscv/safe-syscall.inc.S similarity index 100% rename from linux-user/host/riscv64/safe-syscall.inc.S rename to linux-user/host/riscv/safe-syscall.inc.S From patchwork Sat Sep 18 18:44:52 2021 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id o8si11847318ybu.78.2021.09.18.11.56.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 11:56:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CfhbSO8l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33370 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfW7-0005Le-4w for patch@linaro.org; Sat, 18 Sep 2021 14:56:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54156) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLJ-0004zy-As for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:41 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:33701) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLE-0006im-9B for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:40 -0400 Received: by mail-pg1-x531.google.com with SMTP id u18so13167733pgf.0 for ; Sat, 18 Sep 2021 11:45:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Augx9stmO3IWbkqJHhpPVeuGJjJAQUvm2M+qwyR3XuM=; b=CfhbSO8l9oF0LrOEatoJXmhnHcHCF8L5OXlC7qgKvHQcZtH38oKBthZuz1+9HhNl67 zfAQWZe5cZCiVRmD9pq005EBhsYJJrKKHv5VoYCYC2OxsNAXF1TNFmFm7Hi6BcvWKTSI 3pzA0AmcGZU8M8danxffrpZthPfGtkHBmhwGFSj5Ef24DPf7Cs0r4RcO15YqYS6qH65D FhkOa3Gx7MSxpM32cleqcVPDxnRooKLJrqINe1TTuyqFo46XjnapE9bv9fEqHlLFoiPY U5g0houf1pLi1gC3yufAQdgmaMFaZXCOCsGgAkLImVQpX+kxS4a+fVvb9ENeBTY4g5RG bj+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Augx9stmO3IWbkqJHhpPVeuGJjJAQUvm2M+qwyR3XuM=; b=zRdXIfrBGRO596nV/ugvywgKkXsbDjJ+GolKNx2SLV+vfqEQ7v3oM+D1NjgnVWqLUb MSd0UclXbX36BJC/7+5kJNXAspXKRdraWgd/V1MAawM0DUDa6VV9BpwOhdzfAEux7w13 0db2w1hShGXnM5xMD+btQpmYLrnqfqHW4mpfgrvW5Qpr4rVWKNIob5QzjPPhCHaG1FtP +ewW6mG8Sz89XOlHHMio8D0eGbIdIVlN+6ao2ZgLQp+rNnveoXqHff852mJWyUMaT3vt xg1uKSPT0H8c2nI6xBBy6lSwxdOPPbQkeJ39bXnZdSD5qJZc6v8TJ8z3BplwpsYyPZzf VQlA== X-Gm-Message-State: AOAM532enNkrIgEOuThTrxcqH1PGJuZR6Zk9ZBNlfOs5baqT/d5mh7RA OFJyW1nj4NObiCSlu9Xl4taJa/hA9MoGKw== X-Received: by 2002:a62:b615:0:b0:3f9:1c5a:2671 with SMTP id j21-20020a62b615000000b003f91c5a2671mr16904984pff.10.1631990734393; Sat, 18 Sep 2021 11:45:34 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 06/41] linux-user: Reorg handling for SIGSEGV Date: Sat, 18 Sep 2021 11:44:52 -0700 Message-Id: <20210918184527.408540-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add stub host-signal.h for all linux-user hosts. Add new code replacing cpu_signal_handler. Full migration will happen one host at a time. Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 1 + linux-user/host/arm/host-signal.h | 1 + linux-user/host/i386/host-signal.h | 1 + linux-user/host/mips/host-signal.h | 1 + linux-user/host/ppc/host-signal.h | 1 + linux-user/host/ppc64/host-signal.h | 1 + linux-user/host/riscv/host-signal.h | 1 + linux-user/host/s390/host-signal.h | 1 + linux-user/host/s390x/host-signal.h | 1 + linux-user/host/sparc/host-signal.h | 1 + linux-user/host/sparc64/host-signal.h | 1 + linux-user/host/x32/host-signal.h | 1 + linux-user/host/x86_64/host-signal.h | 1 + linux-user/signal.c | 109 ++++++++++++++++++++++---- 14 files changed, 106 insertions(+), 16 deletions(-) create mode 100644 linux-user/host/aarch64/host-signal.h create mode 100644 linux-user/host/arm/host-signal.h create mode 100644 linux-user/host/i386/host-signal.h create mode 100644 linux-user/host/mips/host-signal.h create mode 100644 linux-user/host/ppc/host-signal.h create mode 100644 linux-user/host/ppc64/host-signal.h create mode 100644 linux-user/host/riscv/host-signal.h create mode 100644 linux-user/host/s390/host-signal.h create mode 100644 linux-user/host/s390x/host-signal.h create mode 100644 linux-user/host/sparc/host-signal.h create mode 100644 linux-user/host/sparc64/host-signal.h create mode 100644 linux-user/host/x32/host-signal.h create mode 100644 linux-user/host/x86_64/host-signal.h -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Acked-by: Alistair Francis diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch64/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/aarch64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/arm/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/i386/host-signal.h b/linux-user/host/i386/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/i386/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/mips/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/ppc/host-signal.h b/linux-user/host/ppc/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/ppc/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/ppc64/host-signal.h b/linux-user/host/ppc64/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/ppc64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/riscv/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/s390/host-signal.h b/linux-user/host/s390/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/s390/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/s390x/host-signal.h b/linux-user/host/s390x/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/s390x/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/sparc/host-signal.h b/linux-user/host/sparc/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/sparc/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/sparc64/host-signal.h b/linux-user/host/sparc64/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/sparc64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/x32/host-signal.h b/linux-user/host/x32/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/x32/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/host/x86_64/host-signal.h b/linux-user/host/x86_64/host-signal.h new file mode 100644 index 0000000000..f4b4d65031 --- /dev/null +++ b/linux-user/host/x86_64/host-signal.h @@ -0,0 +1 @@ +#define HOST_SIGNAL_PLACEHOLDER diff --git a/linux-user/signal.c b/linux-user/signal.c index 5ea8e4584a..6f953f10d4 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -18,12 +18,15 @@ */ #include "qemu/osdep.h" #include "qemu/bitops.h" +#include "hw/core/tcg-cpu-ops.h" + #include #include #include "qemu.h" #include "trace.h" #include "signal-common.h" +#include "host-signal.h" static struct target_sigaction sigact_table[TARGET_NSIG]; @@ -761,41 +764,115 @@ static inline void rewind_if_in_safe_syscall(void *puc) } #endif -static void host_signal_handler(int host_signum, siginfo_t *info, - void *puc) +static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) { CPUArchState *env = thread_cpu->env_ptr; CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; - - int sig; target_siginfo_t tinfo; ucontext_t *uc = puc; struct emulated_sigtable *k; + int guest_sig; +#ifdef HOST_SIGNAL_PLACEHOLDER /* the CPU emulator uses some host signals to detect exceptions, we forward to it some signals */ - if ((host_signum == SIGSEGV || host_signum == SIGBUS) + if ((host_sig == SIGSEGV || host_sig == SIGBUS) && info->si_code > 0) { - if (cpu_signal_handler(host_signum, info, puc)) + if (cpu_signal_handler(host_sig, info, puc)) return; } +#else + uintptr_t pc = 0; + bool sync_sig = false; + + /* + * Non-spoofed SIGSEGV and SIGBUS are synchronous, and need special + * handling wrt signal blocking and unwinding. + */ + if ((host_sig == SIGSEGV || host_sig == SIGBUS) && info->si_code > 0) { + MMUAccessType access_type; + uintptr_t host_addr; + abi_ptr guest_addr; + bool is_write; + + host_addr = (uintptr_t)info->si_addr; + + /* + * Convert forcefully to guest address space: addresses outside + * reserved_va are still valid to report via SEGV_MAPERR. + */ + guest_addr = h2g_nocheck(host_addr); + + pc = host_signal_pc(uc); + is_write = host_signal_write(info, uc); + access_type = adjust_signal_pc(&pc, is_write); + + if (host_sig == SIGSEGV) { + const struct TCGCPUOps *tcg_ops; + + if (info->si_code == SEGV_ACCERR && h2g_valid(host_addr)) { + /* If this was a write to a TB protected page, restart. */ + if (is_write && + handle_sigsegv_accerr_write(cpu, &uc->uc_sigmask, + pc, guest_addr)) { + return; + } + + /* + * With reserved_va, the whole address space is PROT_NONE, + * which means that we may get ACCERR when we want MAPERR. + */ + if (page_get_flags(guest_addr) & PAGE_VALID) { + /* maperr = false; */ + } else { + info->si_code = SEGV_MAPERR; + } + } + + sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + + tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, + MMU_USER_IDX, false, pc); + g_assert_not_reached(); + } else { + sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); + } + + sync_sig = true; + } +#endif /* get target signal number */ - sig = host_to_target_signal(host_signum); - if (sig < 1 || sig > TARGET_NSIG) + guest_sig = host_to_target_signal(host_sig); + if (guest_sig < 1 || guest_sig > TARGET_NSIG) { return; - trace_user_host_signal(env, host_signum, sig); + } + trace_user_host_signal(env, host_sig, guest_sig); + + host_to_target_siginfo_noswap(&tinfo, info); + k = &ts->sigtab[guest_sig - 1]; + k->info = tinfo; + k->pending = guest_sig; + ts->signal_pending = 1; + +#ifndef HOST_SIGNAL_PLACEHOLDER + /* + * For synchronous signals, unwind the cpu state to the faulting + * insn and then exit back to the main loop so that the signal + * is delivered immediately. + */ + if (sync_sig) { + cpu->exception_index = EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, pc); + } +#endif rewind_if_in_safe_syscall(puc); - host_to_target_siginfo_noswap(&tinfo, info); - k = &ts->sigtab[sig - 1]; - k->info = tinfo; - k->pending = sig; - ts->signal_pending = 1; - - /* Block host signals until target signal handler entered. We + /* + * Block host signals until target signal handler entered. We * can't block SIGSEGV or SIGBUS while we're executing guest * code in case the guest code provokes one in the window between * now and it getting out to the main loop. Signals will be From patchwork Sat Sep 18 18:44:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514232 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp671669jao; Sat, 18 Sep 2021 11:59:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyGkeYDSpuMhP/KkQ1bKvnTid020uVpZVO//U5DDVJz+lcpJoh7NVUlb7Zu+6BNAxtqs493 X-Received: by 2002:a6b:7710:: with SMTP id n16mr13048232iom.101.1631991598747; Sat, 18 Sep 2021 11:59:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631991598; cv=none; d=google.com; s=arc-20160816; b=LDZiN9tCzRrJarMt5Wa99Gs+0ptl1FZWtpuCW8/qvzPOKktuLBIzC5xID1HE35MQRH zMV63QVp9ZWAu+HtMkM8la0qCooVQbBbVAtx7tFjHfUYfj4/Jpyj88kmsHD7WLVcyJOg FeYKXgyLhaGI8Y5TlwB5HkAz+G33544yV5GHU3XMGXfpVYHZODoseuMifpRDT+s93rRn U0Y6JkRCEqOVZeOeyOh6S4t5X4PwIMl0vlANX7qKqdu8mm9PqD88fSRLR6ljQK75j2om MAkjBK6iXHgOtrmDSOfmhTUPqokjRKiC3oSCfgKyqvrMWLf4OcgKTbRECex+/uQ7shMN EN8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=eo69a6qpbSWMyVxfRxEgkjHG9EovPVD2b2o16GmRH3A=; b=TZ3TVUg104wbPWOkeZCmW2Zd0AylyS5x4VGDLP4xXhlwX8Nz3wM1YBhV30a9tJkT4U k5NsmRRb92vVANEmwvyP3ztMb2hYegv1//yLriStVfsGRKPP1DxC40IU5YWmRX0I3CaV lse+ST2mR3MvIxQuiTMr2CFiL6SVLUHjm/0n+/wtZBgkYPTTtu6DcncgTZQLpswy7m1O l3rFi63fkLFvJq5ZZPWP+yOutl3x+IcPh7OR5xA0cbIERwUst6NjwiB7FpIjMiUeRUTX ub0BRuifODTnp5j/F2k5Zh81vvAka7b/pt/SZyGRwKACc6+ZCQFk3/7nG3LHtIJhmvtl 9oAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tz26dHUz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson --- linux-user/host/i386/host-signal.h | 25 ++++- linux-user/host/x32/host-signal.h | 2 +- linux-user/host/x86_64/host-signal.h | 25 ++++- accel/tcg/user-exec.c | 136 +-------------------------- 4 files changed, 50 insertions(+), 138 deletions(-) -- 2.25.1 diff --git a/linux-user/host/i386/host-signal.h b/linux-user/host/i386/host-signal.h index f4b4d65031..ccbbee5082 100644 --- a/linux-user/host/i386/host-signal.h +++ b/linux-user/host/i386/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef I386_HOST_SIGNAL_H +#define I386_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_EIP]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe + && (uc->uc_mcontext.gregs[REG_ERR] & 0x2); +} + +#endif diff --git a/linux-user/host/x32/host-signal.h b/linux-user/host/x32/host-signal.h index f4b4d65031..26800591d3 100644 --- a/linux-user/host/x32/host-signal.h +++ b/linux-user/host/x32/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../x86_64/host-signal.h" diff --git a/linux-user/host/x86_64/host-signal.h b/linux-user/host/x86_64/host-signal.h index f4b4d65031..883d2fcf65 100644 --- a/linux-user/host/x86_64/host-signal.h +++ b/linux-user/host/x86_64/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef X86_64_HOST_SIGNAL_H +#define X86_64_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_RIP]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe + && (uc->uc_mcontext.gregs[REG_ERR] & 0x2); +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index de4565f13e..b5d06183db 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -29,19 +29,6 @@ #include "trace/trace-root.h" #include "trace/mem.h" -#undef EAX -#undef ECX -#undef EDX -#undef EBX -#undef ESP -#undef EBP -#undef ESI -#undef EDI -#undef EIP -#ifdef __linux__ -#include -#endif - __thread uintptr_t helper_retaddr; //#define DEBUG_SIGNAL @@ -268,123 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__i386__) - -#if defined(__NetBSD__) -#include -#include - -#define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__FreeBSD__) || defined(__DragonFly__) -#include -#include - -#define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip)) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) -#define ERROR_sig(context) ((context)->uc_mcontext.mc_err) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__OpenBSD__) -#include -#define EIP_sig(context) ((context)->sc_eip) -#define TRAP_sig(context) ((context)->sc_trapno) -#define ERROR_sig(context) ((context)->sc_err) -#define MASK_sig(context) ((context)->sc_mask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#else -#define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP 0xe -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; -#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) - ucontext_t *uc = puc; -#elif defined(__OpenBSD__) - struct sigcontext *uc = puc; -#else - ucontext_t *uc = puc; -#endif - unsigned long pc; - int trapno; - -#ifndef REG_EIP -/* for glibc 2.1 */ -#define REG_EIP EIP -#define REG_ERR ERR -#define REG_TRAPNO TRAPNO -#endif - pc = EIP_sig(uc); - trapno = TRAP_sig(uc); - return handle_cpu_signal(pc, info, - trapno == PAGE_FAULT_TRAP ? - (ERROR_sig(uc) >> 1) & 1 : 0, - &MASK_sig(uc)); -} - -#elif defined(__x86_64__) - -#ifdef __NetBSD__ -#include -#define PC_sig(context) _UC_MACHINE_PC(context) -#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__OpenBSD__) -#include -#define PC_sig(context) ((context)->sc_rip) -#define TRAP_sig(context) ((context)->sc_trapno) -#define ERROR_sig(context) ((context)->sc_err) -#define MASK_sig(context) ((context)->sc_mask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#elif defined(__FreeBSD__) || defined(__DragonFly__) -#include -#include - -#define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip)) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) -#define ERROR_sig(context) ((context)->uc_mcontext.mc_err) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP T_PAGEFLT -#else -#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) -#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) -#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) -#define MASK_sig(context) ((context)->uc_sigmask) -#define PAGE_FAULT_TRAP 0xe -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - unsigned long pc; -#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) - ucontext_t *uc = puc; -#elif defined(__OpenBSD__) - struct sigcontext *uc = puc; -#else - ucontext_t *uc = puc; -#endif - - pc = PC_sig(uc); - return handle_cpu_signal(pc, info, - TRAP_sig(uc) == PAGE_FAULT_TRAP ? - (ERROR_sig(uc) >> 1) & 1 : 0, - &MASK_sig(uc)); -} - -#elif defined(_ARCH_PPC) +#if defined(_ARCH_PPC) /*********************************************************************** * signal context platform-specific definitions @@ -895,11 +766,6 @@ int cpu_signal_handler(int host_signum, void *pinfo, return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } - -#else - -#error host CPU specific signal handler needed - #endif /* The softmmu versions of these helpers are in cputlb.c. */ From patchwork Sat Sep 18 18:44:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514217 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp665734jao; Sat, 18 Sep 2021 11:47:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyNt8ClfHsl3GsQhOHtwD6oqCM0bWvBGhxwOTLpUXc6G7E90Iz5W24ljrZOmQhs5XM3ltYE X-Received: by 2002:ac8:7444:: with SMTP id h4mr16073994qtr.337.1631990877829; Sat, 18 Sep 2021 11:47:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631990877; cv=none; d=google.com; s=arc-20160816; b=SAp/nFL85ZG7oz/vOwL03Cy2f7jf9Fdi/Qi1jgF/soXYyh1ms2jAmokksDdXAny3iq SFxH7qquSNn67P59+kexBw5WfwtHQCh5RFKsMBaDpwzRhe0lRbmElFpZViNks7w6i0+B hoVGgPhxzzke9SZ1NkHfyjm2W1/VPeV54Z3Zn7ShC34XLrCL99t3Noso2SpveujWca01 K+tpVFu5fgMPV6Y2m08pfvpqhv4eotc74WJ62oy/a9r4YHxR15FvgYlc/qD7MkwDf6pZ gcExq5AO1RvoTvRxAfK7pbIawuDN7+3YNY6RKW2susG1Y/zzGpkdLwwvk2bDww+tNF1o 1HdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QHZIGAsKEZU6jgHWjM6GlNTI+lnbqqDGKIT8+9oO0ok=; b=hskcf2w23fT+QbsLGbCjTNZ8g/nGxApQj/pjk1Nd3ERexp4mzRCMZIraodaNEKQqN8 xnp0F5TGtpKB+f5fgZnDljH3a31qQXQT/h6jIRJDjYYJddVDl2ycxh7/E6Bp9GjqWmsr p9qFVaOfm+3lr/Rf+z9dU/+DB4hwPAZdHnktZgE4HqyRO5fkIEyHOIKjspiWfIePBggH M0YLErkxV71gfTHdUEUpfO51h29ThCoqC9UC4CHUhUDlH2pyQSMGEsWSEJ9bU8zcAbp8 iy/CCpZ+6Va36KkBw0bBkuNuNgO/1BLYhRg9j5x90nan9oltgF1hqU9FEdj2rosIo1gw gpGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ZM8Xb/Rp"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson --- linux-user/host/ppc/host-signal.h | 25 ++++++++- linux-user/host/ppc64/host-signal.h | 2 +- accel/tcg/user-exec.c | 79 +---------------------------- 3 files changed, 26 insertions(+), 80 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh diff --git a/linux-user/host/ppc/host-signal.h b/linux-user/host/ppc/host-signal.h index f4b4d65031..e09756c691 100644 --- a/linux-user/host/ppc/host-signal.h +++ b/linux-user/host/ppc/host-signal.h @@ -1 +1,24 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef PPC_HOST_SIGNAL_H +#define PPC_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.regs->nip; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + return uc->uc_mcontext.regs->trap != 0x400 + && (uc->uc_mcontext.regs->dsisr & 0x02000000); +} + +#endif diff --git a/linux-user/host/ppc64/host-signal.h b/linux-user/host/ppc64/host-signal.h index f4b4d65031..a353c22a90 100644 --- a/linux-user/host/ppc64/host-signal.h +++ b/linux-user/host/ppc64/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../ppc/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index b5d06183db..e9e530e2e1 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,84 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(_ARCH_PPC) - -/*********************************************************************** - * signal context platform-specific definitions - * From Wine - */ -#ifdef linux -/* All Registers access - only for local access */ -#define REG_sig(reg_name, context) \ - ((context)->uc_mcontext.regs->reg_name) -/* Gpr Registers access */ -#define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) -/* Program counter */ -#define IAR_sig(context) REG_sig(nip, context) -/* Machine State Register (Supervisor) */ -#define MSR_sig(context) REG_sig(msr, context) -/* Count register */ -#define CTR_sig(context) REG_sig(ctr, context) -/* User's integer exception register */ -#define XER_sig(context) REG_sig(xer, context) -/* Link register */ -#define LR_sig(context) REG_sig(link, context) -/* Condition register */ -#define CR_sig(context) REG_sig(ccr, context) - -/* Float Registers access */ -#define FLOAT_sig(reg_num, context) \ - (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num]) -#define FPSCR_sig(context) \ - (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4))) -/* Exception Registers access */ -#define DAR_sig(context) REG_sig(dar, context) -#define DSISR_sig(context) REG_sig(dsisr, context) -#define TRAP_sig(context) REG_sig(trap, context) -#endif /* linux */ - -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) -#include -#define IAR_sig(context) ((context)->uc_mcontext.mc_srr0) -#define MSR_sig(context) ((context)->uc_mcontext.mc_srr1) -#define CTR_sig(context) ((context)->uc_mcontext.mc_ctr) -#define XER_sig(context) ((context)->uc_mcontext.mc_xer) -#define LR_sig(context) ((context)->uc_mcontext.mc_lr) -#define CR_sig(context) ((context)->uc_mcontext.mc_cr) -/* Exception Registers access */ -#define DAR_sig(context) ((context)->uc_mcontext.mc_dar) -#define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr) -#define TRAP_sig(context) ((context)->uc_mcontext.mc_exc) -#endif /* __FreeBSD__|| __FreeBSD_kernel__ */ - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) - ucontext_t *uc = puc; -#else - ucontext_t *uc = puc; -#endif - unsigned long pc; - int is_write; - - pc = IAR_sig(uc); - is_write = 0; -#if 0 - /* ppc 4xx case */ - if (DSISR_sig(uc) & 0x00800000) { - is_write = 1; - } -#else - if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) { - is_write = 1; - } -#endif - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__alpha__) +#if defined(__alpha__) int cpu_signal_handler(int host_signum, void *pinfo, void *puc) From patchwork Sat Sep 18 18:44:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514219 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp665758jao; Sat, 18 Sep 2021 11:48:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxN3ONJIFw2zFxYCseEhTosiKjhWqBWFWN+ekSHkuAnSDTsNUWZF04VsQIoFvQcQT8I6BYY X-Received: by 2002:a0c:ac0d:: with SMTP id l13mr2622076qvb.36.1631990880253; Sat, 18 Sep 2021 11:48:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631990880; cv=none; d=google.com; s=arc-20160816; b=WjYJ4xRIuXJ47lWtUZ8yy+FelA6fFmUeauFVp34wBip77LpUNDs3mbwhx0f9L9iCvM HCUfcju39bs/EBnRbAmMdhPiQCsVXwBeP57PVRGSnyXt+272e1Kz8Ho5WX7OUzeT63gl pZwtzJFvtIThOC71dnKjHOLo1yNz1NxaeB5sv3ljIWu2/0IG3YphEJBo4rKM6Tastc9H 1eTQV/4Lp1PeuiMtQXG1rPI0eF5Z78yow43vFy0A0GhLu54faVRh1a5QP1bRrdLok5ar OdYimZ8YCtT+ceiFNhYahwWAQuSKRn3XpmGUKG8BaXoH0AOshSMFSv4Bm3T19uSjbd6G eXIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9mBw19ydcFw0MZKZsGTXe7n/L8er4q9+1e7zu/IzZgY=; b=UNl9rqg6Xnw9H2LOrXXhALJ40q2YF5Wpxlo1uc4x6MqnyvVjtb6D4GSlHI+Ww+apQT 0ZxPOX83LWC1oNcBshNDuXHbYJxaUd5W/nGS1yGIfCAzuAckSYZj1gqloVT+5oSDAGD1 unjYPu6+ucvlyF+wU/Vt3a6Rc0BQ9clKoHOf8zbpUPEz2ypOrlkqwmMfAK1RvlUHRUav XMV7R8+9luGLzm9+96ZqUzXtwCneModyueEp94k3MEid9dPwWau/B9DIUPo2MoJptQkG epu9IYTOt8sFsaO6Ky4PCB5haoG6nCYMKGRcwjQxyQvelYrtiVolXw4hCeNCz5BSJ0KK qgpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HpondtEe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- linux-user/host/alpha/host-signal.h | 41 +++++++++++++++++++++++++++++ accel/tcg/user-exec.c | 31 +--------------------- 2 files changed, 42 insertions(+), 30 deletions(-) create mode 100644 linux-user/host/alpha/host-signal.h -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/linux-user/host/alpha/host-signal.h b/linux-user/host/alpha/host-signal.h new file mode 100644 index 0000000000..b0b488e004 --- /dev/null +++ b/linux-user/host/alpha/host-signal.h @@ -0,0 +1,41 @@ +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef ALPHA_HOST_SIGNAL_H +#define ALPHA_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.sc_pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t *pc = uc->uc_mcontext.sc_pc; + uint32_t insn = *pc; + + /* XXX: need kernel patch to get write flag faster */ + switch (insn >> 26) { + case 0x0d: /* stw */ + case 0x0e: /* stb */ + case 0x0f: /* stq_u */ + case 0x24: /* stf */ + case 0x25: /* stg */ + case 0x26: /* sts */ + case 0x27: /* stt */ + case 0x2c: /* stl */ + case 0x2d: /* stq */ + case 0x2e: /* stl_c */ + case 0x2f: /* stq_c */ + return true; + } + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e9e530e2e1..b895b5c8bd 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,36 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__alpha__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - uint32_t *pc = uc->uc_mcontext.sc_pc; - uint32_t insn = *pc; - int is_write = 0; - - /* XXX: need kernel patch to get write flag faster */ - switch (insn >> 26) { - case 0x0d: /* stw */ - case 0x0e: /* stb */ - case 0x0f: /* stq_u */ - case 0x24: /* stf */ - case 0x25: /* stg */ - case 0x26: /* sts */ - case 0x27: /* stt */ - case 0x2c: /* stl */ - case 0x2d: /* stq */ - case 0x2e: /* stl_c */ - case 0x2f: /* stq_c */ - is_write = 1; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#elif defined(__sparc__) +#if defined(__sparc__) int cpu_signal_handler(int host_signum, void *pinfo, void *puc) From patchwork Sat Sep 18 18:44:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514228 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp670216jao; Sat, 18 Sep 2021 11:56:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxLx0BZXgPKq+Der5hHNhinWA4o138XMKJAq/weCHZTNmPUbAb8iVSj9Lb7C4uqcP558olF X-Received: by 2002:ae9:de06:: with SMTP id s6mr16946244qkf.489.1631991402295; Sat, 18 Sep 2021 11:56:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631991402; cv=none; d=google.com; s=arc-20160816; b=cF0mMI0Da4OdFfZOpfjASkxLIB/zI/iP3IpJsikJRNU/cJ5NhQoMmub4E2ML2rJwjT 0tzdZ3EHpLfn0YcEQ6p2b2KWPqu22pYnH0PHhqSx78gJEAbvWNZd/HdLZiKO75/+5UQZ UjfdBWIbKw46EQDkS7lkj7SeLSddBYx8Q4aPEiNpKtRfHTVDYNePePhSVV76a0zIfZ5X a9uaYZivPtilezkhniSDIJt+RbkMUkI2qCxr7S5SsSYR6j3p0l0pVqwUYln42hB+vutT 5cR0XjriQgp5y0qPCGg9jFEUpG0racAwYtrdaaA4JBA3WcA68IpJEzsZYOtRCTgwGSKV tqhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SHk0L4QVJKHbdhHw2ZILrKhqMEpfB7Y/GR3loPVJEL4=; b=dXN19TXYt87aCHF7DWWGdvuSHcLqdccg6AdHM230L/8BD8TSjCdNVdiCg3xbWw+bLz L1JfjsmNrs9SHXAUyCTxrMBFPyRl/Vb/7zkzEYRCCJTMkQYJAiYtmuFQoSEOgYDH09J3 kQcqQRYTKnZboKu5BrwpAdkUc4wo8slQAWdjIDm9kdzU/NoWlIdmtiOY5ndsupWwaco0 YdypKmxvYTON7wkhpornY3Dt5aDvJCId457UDAtKMMhxkQ6ckjmum2dnn3KaMW2v0Gkp YVXjNc0yxVc3FMKPtFTAaexIC2+V+8pziyjzO+wlmpo0ACEjzWEFi0IXxMQQ/uuG78KZ KLYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nTuFN6Ex; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Drop the *BSD code, to be re-created under bsd-user/ later. Drop the Solais code as completely unused. Signed-off-by: Richard Henderson --- linux-user/host/sparc/host-signal.h | 54 ++++++++++++++++++++++- linux-user/host/sparc64/host-signal.h | 2 +- accel/tcg/user-exec.c | 62 +-------------------------- 3 files changed, 55 insertions(+), 63 deletions(-) -- 2.25.1 diff --git a/linux-user/host/sparc/host-signal.h b/linux-user/host/sparc/host-signal.h index f4b4d65031..232943a1db 100644 --- a/linux-user/host/sparc/host-signal.h +++ b/linux-user/host/sparc/host-signal.h @@ -1 +1,53 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef SPARC_HOST_SIGNAL_H +#define SPARC_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ +#ifdef __arch64__ + return uc->uc_mcontext.mc_gregs[MC_PC]; +#else + return uc->uc_mcontext.gregs[REG_PC]; +#endif +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn = *(uint32_t *)host_signal_pc(uc); + + if ((insn >> 30) == 3) { + switch ((insn >> 19) & 0x3f) { + case 0x05: /* stb */ + case 0x15: /* stba */ + case 0x06: /* sth */ + case 0x16: /* stha */ + case 0x04: /* st */ + case 0x14: /* sta */ + case 0x07: /* std */ + case 0x17: /* stda */ + case 0x0e: /* stx */ + case 0x1e: /* stxa */ + case 0x24: /* stf */ + case 0x34: /* stfa */ + case 0x27: /* stdf */ + case 0x37: /* stdfa */ + case 0x26: /* stqf */ + case 0x36: /* stqfa */ + case 0x25: /* stfsr */ + case 0x3c: /* casa */ + case 0x3e: /* casxa */ + return true; + } + } + return false; +} + +#endif diff --git a/linux-user/host/sparc64/host-signal.h b/linux-user/host/sparc64/host-signal.h index f4b4d65031..1191fe2d40 100644 --- a/linux-user/host/sparc64/host-signal.h +++ b/linux-user/host/sparc64/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../sparc/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index b895b5c8bd..c7d083db92 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,67 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__sparc__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - int is_write; - uint32_t insn; -#if !defined(__arch64__) || defined(CONFIG_SOLARIS) - uint32_t *regs = (uint32_t *)(info + 1); - void *sigmask = (regs + 20); - /* XXX: is there a standard glibc define ? */ - unsigned long pc = regs[1]; -#else -#ifdef __linux__ - struct sigcontext *sc = puc; - unsigned long pc = sc->sigc_regs.tpc; - void *sigmask = (void *)sc->sigc_mask; -#elif defined(__OpenBSD__) - struct sigcontext *uc = puc; - unsigned long pc = uc->sc_pc; - void *sigmask = (void *)(long)uc->sc_mask; -#elif defined(__NetBSD__) - ucontext_t *uc = puc; - unsigned long pc = _UC_MACHINE_PC(uc); - void *sigmask = (void *)&uc->uc_sigmask; -#endif -#endif - - /* XXX: need kernel patch to get write flag faster */ - is_write = 0; - insn = *(uint32_t *)pc; - if ((insn >> 30) == 3) { - switch ((insn >> 19) & 0x3f) { - case 0x05: /* stb */ - case 0x15: /* stba */ - case 0x06: /* sth */ - case 0x16: /* stha */ - case 0x04: /* st */ - case 0x14: /* sta */ - case 0x07: /* std */ - case 0x17: /* stda */ - case 0x0e: /* stx */ - case 0x1e: /* stxa */ - case 0x24: /* stf */ - case 0x34: /* stfa */ - case 0x27: /* stdf */ - case 0x37: /* stdfa */ - case 0x26: /* stqf */ - case 0x36: /* stqfa */ - case 0x25: /* stfsr */ - case 0x3c: /* casa */ - case 0x3e: /* casxa */ - is_write = 1; - break; - } - } - return handle_cpu_signal(pc, info, is_write, sigmask); -} - -#elif defined(__arm__) +#if defined(__arm__) #if defined(__NetBSD__) #include From patchwork Sat Sep 18 18:44:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514233 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp671691jao; Sat, 18 Sep 2021 12:00:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwLK+3eE+P8bfmSfGq/gg5pQJo1+jZfk2gOXTWUcmQ1KSfVOFSILupxY1jeksZR1QoIQVO1 X-Received: by 2002:a25:d6cf:: with SMTP id n198mr20970496ybg.535.1631991600772; Sat, 18 Sep 2021 12:00:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631991600; cv=none; d=google.com; s=arc-20160816; b=b9cdXk3HN+/GppPXukXtDhSo0sJsaN4Jps0HIC+GaQtipbPf7YW/bh8Rts+PrkMxmJ v7K5qVyNkGzxIfHUbxV2n4d9S1BzqWBXryZXTthO+DFCgq7PdWQPLX7VT5eenzzB54Lo TUJlRdoj2PM72dJfX9v3Gm9XO2hvz+g6bMpU9BKI+mJIfwa5CDs1T6b+lbHtj6axMkwb jiKUXoTrAtV6VwloRuLy3lPI66MDJK7CoyjjDiqC43uAO7gzMlgesxC+XIqkYSKdLw0B xP0/wUOUBdUYC8izhheaXUZTGQ9K4zSCV3cZN9JTjtAT3J4OWfbflgjEprKkkuR5Xczp INkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=sCS25t/S/07LT/4q9hu7ybFQaqd9aKvTlaQnlQkDGSw=; b=sn0J91rEsN7Dc30ncesWnX/iQFjooMA1QqrFOAEe5fKje8x4W2sDmrUiY//4U3D+Ia QwuTwVFb/BlBFRoFUpSKq1rA57ucAyvaHQMwhjpv6V5AltsqwdSxV67kD09j/ug7Tn/j OJO3oAVAfddBxVlbMcNhisTp/mwyjrrx0+YVt6VgBp5eh2Dgr/YNiQJ4dundvPzRLU02 O3CVoXkEp40d60eACrtiTFgWcGg/hLWz7fJUIpDToBvi/uPVvZyx71aTUOi4UAnkSRtr BEKPwzdS10kjMczwbpzzmrLPWeTws7OdhokIY8GXmnjR30GzRov32XXCTOfm5rV7vIW5 f5Zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Vp2sGT18; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson --- linux-user/host/arm/host-signal.h | 30 ++++++++++++++++++++- accel/tcg/user-exec.c | 45 +------------------------------ 2 files changed, 30 insertions(+), 45 deletions(-) -- 2.25.1 diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-signal.h index f4b4d65031..6932224c1c 100644 --- a/linux-user/host/arm/host-signal.h +++ b/linux-user/host/arm/host-signal.h @@ -1 +1,29 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef ARM_HOST_SIGNAL_H +#define ARM_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.arm_pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + /* + * In the FSR, bit 11 is WnR, assuming a v6 or + * later processor. On v5 we will always report + * this as a read, which will fail later. + */ + uint32_t fsr = uc->uc_mcontext.error_code; + return extract32(fsr, 11, 1); +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index c7d083db92..e9c29f917d 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,50 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__arm__) - -#if defined(__NetBSD__) -#include -#include -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; -#if defined(__NetBSD__) - ucontext_t *uc = puc; - siginfo_t *si = pinfo; -#else - ucontext_t *uc = puc; -#endif - unsigned long pc; - uint32_t fsr; - int is_write; - -#if defined(__NetBSD__) - pc = uc->uc_mcontext.__gregs[_REG_R15]; -#elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) - pc = uc->uc_mcontext.gregs[R15]; -#else - pc = uc->uc_mcontext.arm_pc; -#endif - -#ifdef __NetBSD__ - fsr = si->si_trap; -#else - fsr = uc->uc_mcontext.error_code; -#endif - /* - * In the FSR, bit 11 is WnR, assuming a v6 or - * later processor. On v5 we will always report - * this as a read, which will fail later. - */ - is_write = extract32(fsr, 11, 1); - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__aarch64__) +#if defined(__aarch64__) #if defined(__NetBSD__) From patchwork Sat Sep 18 18:44:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514239 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp675921jao; Sat, 18 Sep 2021 12:06:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwoa4K+qH0bejwAMNgTQv1+E4yJZBadhW1zHsVg12aD9kWbuxH+YqRs/KiWc8ygQvWA+BU5 X-Received: by 2002:a05:6638:1e2:: with SMTP id t2mr4807042jaq.21.1631991997379; Sat, 18 Sep 2021 12:06:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631991997; cv=none; d=google.com; s=arc-20160816; b=qaPs+dvp0jwOUWVLp+vdk9OZmhLkGrLi/YVoLBnMSQjCB1STfxeog97fi4LVMnLDX8 Fw4ncmgKH7KdzvYnLrm+SDNVUT/SHIHo8qblj3hsDbNRpKm553xqFtWP7eYxwXzUyPc7 coNmFGDgtAlLK95w22NLx1eNYLROgaJK5NZHZmWVlllHSteHLXFazRUkhQJvygJm0Jrd WDtSb+5PHRoaOLLKD1qaYq2Z9peT8lvqHZMoVP/sC7OihMhierxGH53XZZ10mYnrZXkG CmRWjJO2tyxw88TXhr0zqPrXmElvwJQBaGqlRAJRDX2ASPhAxtYz7JjYMDtdH3w+MFPi BbQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xfI870gEd9IvWUORblCHYU3iuTigO27Yz4cJ6DbnRFo=; b=pxiK0zUxHuplqgTDzNh2Hf0C1NVArdAiAnbWoZUcG9XT74rTJ6nW/QH1jQUKa5Ku8Z t+DzU+wubbZYOS198jv3VeIRu8umrEVHmljzOqP26/c5vRhjVBLvSvK1MUlQ1hi8rSof ry2WNVIiChTUvtSadoYcaY3syIBocm24SbvimCIrPWnFK+1Bj+VCPcwVdD9q24nHfj1x obA+K1tuneB5qZYTq6VPqWTJEW1dBrF0Htr4WABsx832YtIddPsVZcsVfUys6hxVMGht gEfaO/bM6Nr8MHSCkCGe1xaDb5qBwKXEa3xrM2jsYn1qtJXxTkmNCE6Vt9Fa+eRHeL7N 0BIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="oUniL/9x"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d6si9808178ios.63.2021.09.18.12.06.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 12:06:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="oUniL/9x"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58004 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRffY-0005GY-Ps for patch@linaro.org; Sat, 18 Sep 2021 15:06:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54290) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLO-00057J-Fl for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:50 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:56305) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLK-0006nA-7q for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:46 -0400 Received: by mail-pj1-x102e.google.com with SMTP id t20so9164818pju.5 for ; Sat, 18 Sep 2021 11:45:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xfI870gEd9IvWUORblCHYU3iuTigO27Yz4cJ6DbnRFo=; b=oUniL/9xNl8w1wiEjPGH3yHmb+yEFsfqNTHjbsBhln7vY1kPdc+m6HHY2rCDJ5/rGr ckb2SG52iLsCAge8nGkOgzgdhKzwznme3/Ehury1VRnlWOf6yah9Q6i/2/CXiVE4C7Or aDdaJRmDBHVve3AdoXxuxZgI/h6mjrZ+Z9waCGmZNggwona6FGQreyi2fagM4OXMsoZS wBKabZ76qK2TclszQH0CIJ7mZWzrW17rNsXHf6DOOt+RQVr/c+4baZ2AGlwwKA3bA/6D IYdWYv5aYEE5yDD79IjWEGlOSH1F5Y9otJDz4Xy3VHEZG5EnvrGmYGugSAUhI/zKwYm5 Zn+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xfI870gEd9IvWUORblCHYU3iuTigO27Yz4cJ6DbnRFo=; b=Xo7dM66OMsf6maot+9/hRmQScy3XPkw8AH8acNUxONZPcNuPO4s89aRJAQZkMxR3Vb RLKFC3nk2OFwMtH0zU/HcHu/MtZZUFjBis9xbIoVfT/1Uaka/1lHCOVIEWwKtppxlFSG EkZneVwJtVXEM+Wb2cRQ0YkDXCZqtb1uwuxK2qo6BAkdfGqBL4lkpCiwg9N7jbfsnWqv uiAGvrMEtRI7s6djfWGze+mnwos4HQ8FlDkRFoSLZgxob2u4VDUkycEb3TqExMpeHRZ9 AQ77KqEKe0SeVTafEiOPz+25ZOTbxBEcOJyrueeJWP9wqHHyVfBDMdN3QPSxh8voYmjA /UwQ== X-Gm-Message-State: AOAM5326mvVbNZCGPUbafsYNg/tqJzznhWaEGyAZ+qISmxTedqmToo2N XDIGBHikcVLUkZGER03fLnrq+zqse5MgOA== X-Received: by 2002:a17:90a:bd08:: with SMTP id y8mr19553097pjr.123.1631990739313; Sat, 18 Sep 2021 11:45:39 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 12/41] linux-user/host/aarch64: Populate host_signal.h Date: Sat, 18 Sep 2021 11:44:58 -0700 Message-Id: <20210918184527.408540-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 74 ++++++++++++++++++++- accel/tcg/user-exec.c | 94 +-------------------------- 2 files changed, 74 insertions(+), 94 deletions(-) -- 2.25.1 diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch64/host-signal.h index f4b4d65031..02a55c3372 100644 --- a/linux-user/host/aarch64/host-signal.h +++ b/linux-user/host/aarch64/host-signal.h @@ -1 +1,73 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef AARCH64_HOST_SIGNAL_H +#define AARCH64_HOST_SIGNAL_H + +/* Pre-3.16 kernel headers don't have these, so provide fallback definitions */ +#ifndef ESR_MAGIC +#define ESR_MAGIC 0x45535201 +struct esr_context { + struct _aarch64_ctx head; + uint64_t esr; +}; +#endif + +static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) +{ + return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; +} + +static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) +{ + return (struct _aarch64_ctx *)((char *)hdr + hdr->size); +} + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + struct _aarch64_ctx *hdr; + uint32_t insn; + + /* Find the esr_context, which has the WnR bit in it */ + for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) { + if (hdr->magic == ESR_MAGIC) { + struct esr_context const *ec = (struct esr_context const *)hdr; + uint64_t esr = ec->esr; + + /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ + return extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; + } + } + + /* + * Fall back to parsing instructions; will only be needed + * for really ancient (pre-3.16) kernels. + */ + insn = *(uint32_t *)host_signal_pc(uc); + + return (insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ + || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ + || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ + || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ + || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ + || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ + || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ + /* Ignore bits 10, 11 & 21, controlling indexing. */ + || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */ + || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */ + /* Ignore bits 23 & 24, controlling indexing. */ + || (insn & 0x3a400000) == 0x28000000; /* C3.3.7,14-16 */ +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e9c29f917d..8f4e788304 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,99 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__aarch64__) - -#if defined(__NetBSD__) - -#include -#include - -int cpu_signal_handler(int host_signum, void *pinfo, void *puc) -{ - ucontext_t *uc = puc; - siginfo_t *si = pinfo; - unsigned long pc; - int is_write; - uint32_t esr; - - pc = uc->uc_mcontext.__gregs[_REG_PC]; - esr = si->si_trap; - - /* - * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC - * is 0b10010x: then bit 6 is the WnR bit - */ - is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; - return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask); -} - -#else - -#ifndef ESR_MAGIC -/* Pre-3.16 kernel headers don't have these, so provide fallback definitions */ -#define ESR_MAGIC 0x45535201 -struct esr_context { - struct _aarch64_ctx head; - uint64_t esr; -}; -#endif - -static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) -{ - return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; -} - -static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) -{ - return (struct _aarch64_ctx *)((char *)hdr + hdr->size); -} - -int cpu_signal_handler(int host_signum, void *pinfo, void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - uintptr_t pc = uc->uc_mcontext.pc; - bool is_write; - struct _aarch64_ctx *hdr; - struct esr_context const *esrctx = NULL; - - /* Find the esr_context, which has the WnR bit in it */ - for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) { - if (hdr->magic == ESR_MAGIC) { - esrctx = (struct esr_context const *)hdr; - break; - } - } - - if (esrctx) { - /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ - uint64_t esr = esrctx->esr; - is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; - } else { - /* - * Fall back to parsing instructions; will only be needed - * for really ancient (pre-3.16) kernels. - */ - uint32_t insn = *(uint32_t *)pc; - - is_write = ((insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ - || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ - || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ - || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ - || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ - || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ - || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ - /* Ignore bits 10, 11 & 21, controlling indexing. */ - || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */ - || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */ - /* Ignore bits 23 & 24, controlling indexing. */ - || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */ - } - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#endif - -#elif defined(__s390__) +#if defined(__s390__) int cpu_signal_handler(int host_signum, void *pinfo, void *puc) From patchwork Sat Sep 18 18:44:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514226 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp668609jao; Sat, 18 Sep 2021 11:53:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzjinx0yuNs70fFyCkTAHgPhpNVT6GnOspbwl9y2U1bfejRJkUFbJBXcpPhmItmyfxW2s6a X-Received: by 2002:a05:622a:1911:: with SMTP id w17mr16642863qtc.228.1631991204754; Sat, 18 Sep 2021 11:53:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631991204; cv=none; d=google.com; s=arc-20160816; b=fcu2NCYgc2KugGGrJgoQPkUHmPda4vaNYn0dowZNflKaK5s8mq54XMS0Z7wmw86L3m eR+1U4RBDxklicKfNIxXSIuiIZUfFXwl6xmBJYs5vPPyBpRHIHxB+RmSSBqo3wQtOcwJ Cz/DRMQSJfVHLPCwRGZ49m7hIICKQgrtUgcX2qLdxCncLwmTp1fBMo2qeZBgogEea6SZ 9V8q6feT7AgDtQj3EktbYMwFA1GQ4/ZnM/e+vYmp9O5YPoHO4ZSY/4sr69hbZCdhwOhB UyoQLkpjCHVRSJmvhd6mPts6kvpRNSbJ8Vc5ldV7iZzLV06dlCVG+X6H9Q3hyC0+k85j qoBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zsP+4M7jyqQgsIMdfJ1ZQMN2aE0h8mf2eX18qZMVb8g=; b=fc5r1uSFZ6ZWeRHyePZqXzhXPzVlzg5FD3FZl2xRGCz/J60g2Zo8xb6220PVUa90bF uJATJHann6BcDeBunS8w+tSSe1L+QgvFAPKAV5qGKigwEbqixVWXu/wga+A6OO6u6zQx nPXsXJd+6gu02GcGFlPAf/htWmgsGVtWGwK4MQCUn0QPr4grUpnembnDCf2wT1911YN3 PO+u4HSEQsQMQeT+4+h+sFo5UABtXz7aAYpapRqVf7UTwjQMdCwrN1IuKual9jxh8N/O 8zJB7ohQHrLixCAuvPiZKaxQZkkgyUwuR/4PYxdMtrvH1DrHaC9w4ZSySCYAxDUKbMhd Bv4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U5D26PN6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- linux-user/host/s390/host-signal.h | 93 ++++++++++++++++++++++++++++- linux-user/host/s390x/host-signal.h | 2 +- accel/tcg/user-exec.c | 88 +-------------------------- 3 files changed, 94 insertions(+), 89 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/linux-user/host/s390/host-signal.h b/linux-user/host/s390/host-signal.h index f4b4d65031..21f59b612a 100644 --- a/linux-user/host/s390/host-signal.h +++ b/linux-user/host/s390/host-signal.h @@ -1 +1,92 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef S390_HOST_SIGNAL_H +#define S390_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.psw.addr; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint16_t *pinsn = (uint16_t *)host_signal_pc(uc); + + /* + * ??? On linux, the non-rt signal handler has 4 (!) arguments instead + * of the normal 2 arguments. The 4th argument contains the "Translation- + * Exception Identification for DAT Exceptions" from the hardware (aka + * "int_parm_long"), which does in fact contain the is_write value. + * The rt signal handler, as far as I can tell, does not give this value + * at all. Not that we could get to it from here even if it were. + * So fall back to parsing instructions. Treat read-modify-write ones as + * writes, which is not fully correct, but for tracking self-modifying code + * this is better than treating them as reads. Checking si_addr page flags + * might be a viable improvement, albeit a racy one. + */ + /* ??? This is not even close to complete. */ + switch (pinsn[0] >> 8) { + case 0x50: /* ST */ + case 0x42: /* STC */ + case 0x40: /* STH */ + case 0xba: /* CS */ + case 0xbb: /* CDS */ + return true; + case 0xc4: /* RIL format insns */ + switch (pinsn[0] & 0xf) { + case 0xf: /* STRL */ + case 0xb: /* STGRL */ + case 0x7: /* STHRL */ + return true; + } + break; + case 0xc8: /* SSF format insns */ + switch (pinsn[0] & 0xf) { + case 0x2: /* CSST */ + return true; + } + break; + case 0xe3: /* RXY format insns */ + switch (pinsn[2] & 0xff) { + case 0x50: /* STY */ + case 0x24: /* STG */ + case 0x72: /* STCY */ + case 0x70: /* STHY */ + case 0x8e: /* STPQ */ + case 0x3f: /* STRVH */ + case 0x3e: /* STRV */ + case 0x2f: /* STRVG */ + return true; + } + break; + case 0xeb: /* RSY format insns */ + switch (pinsn[2] & 0xff) { + case 0x14: /* CSY */ + case 0x30: /* CSG */ + case 0x31: /* CDSY */ + case 0x3e: /* CDSG */ + case 0xe4: /* LANG */ + case 0xe6: /* LAOG */ + case 0xe7: /* LAXG */ + case 0xe8: /* LAAG */ + case 0xea: /* LAALG */ + case 0xf4: /* LAN */ + case 0xf6: /* LAO */ + case 0xf7: /* LAX */ + case 0xfa: /* LAAL */ + case 0xf8: /* LAA */ + return true; + } + break; + } + return false; +} + +#endif diff --git a/linux-user/host/s390x/host-signal.h b/linux-user/host/s390x/host-signal.h index f4b4d65031..0e83f9358d 100644 --- a/linux-user/host/s390x/host-signal.h +++ b/linux-user/host/s390x/host-signal.h @@ -1 +1 @@ -#define HOST_SIGNAL_PLACEHOLDER +#include "../s390/host-signal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 8f4e788304..0810b71ba0 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,93 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__s390__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - unsigned long pc; - uint16_t *pinsn; - int is_write = 0; - - pc = uc->uc_mcontext.psw.addr; - - /* - * ??? On linux, the non-rt signal handler has 4 (!) arguments instead - * of the normal 2 arguments. The 4th argument contains the "Translation- - * Exception Identification for DAT Exceptions" from the hardware (aka - * "int_parm_long"), which does in fact contain the is_write value. - * The rt signal handler, as far as I can tell, does not give this value - * at all. Not that we could get to it from here even if it were. - * So fall back to parsing instructions. Treat read-modify-write ones as - * writes, which is not fully correct, but for tracking self-modifying code - * this is better than treating them as reads. Checking si_addr page flags - * might be a viable improvement, albeit a racy one. - */ - /* ??? This is not even close to complete. */ - pinsn = (uint16_t *)pc; - switch (pinsn[0] >> 8) { - case 0x50: /* ST */ - case 0x42: /* STC */ - case 0x40: /* STH */ - case 0xba: /* CS */ - case 0xbb: /* CDS */ - is_write = 1; - break; - case 0xc4: /* RIL format insns */ - switch (pinsn[0] & 0xf) { - case 0xf: /* STRL */ - case 0xb: /* STGRL */ - case 0x7: /* STHRL */ - is_write = 1; - } - break; - case 0xc8: /* SSF format insns */ - switch (pinsn[0] & 0xf) { - case 0x2: /* CSST */ - is_write = 1; - } - break; - case 0xe3: /* RXY format insns */ - switch (pinsn[2] & 0xff) { - case 0x50: /* STY */ - case 0x24: /* STG */ - case 0x72: /* STCY */ - case 0x70: /* STHY */ - case 0x8e: /* STPQ */ - case 0x3f: /* STRVH */ - case 0x3e: /* STRV */ - case 0x2f: /* STRVG */ - is_write = 1; - } - break; - case 0xeb: /* RSY format insns */ - switch (pinsn[2] & 0xff) { - case 0x14: /* CSY */ - case 0x30: /* CSG */ - case 0x31: /* CDSY */ - case 0x3e: /* CDSG */ - case 0xe4: /* LANG */ - case 0xe6: /* LAOG */ - case 0xe7: /* LAXG */ - case 0xe8: /* LAAG */ - case 0xea: /* LAALG */ - case 0xf4: /* LAN */ - case 0xf6: /* LAO */ - case 0xf7: /* LAX */ - case 0xfa: /* LAAL */ - case 0xf8: /* LAA */ - is_write = 1; - } - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__mips__) +#if defined(__mips__) #if defined(__misp16) || defined(__mips_micromips) #error "Unsupported encoding" From patchwork Sat Sep 18 18:45:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514236 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp674419jao; Sat, 18 Sep 2021 12:04:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy7RQ0poZvzVkFWDFyC7x5FYI0VrR+zFIQFlqouOoYvICmneIPDY6sXaLDVFXc/LPbK+VTX X-Received: by 2002:a05:6e02:164b:: with SMTP id v11mr2647457ilu.224.1631991841533; Sat, 18 Sep 2021 12:04:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631991841; cv=none; d=google.com; s=arc-20160816; b=LPG2Z79Oxsrwa4kk14dIBg7pmiinLK5Y4TEMRzHWFqvGgo1BK0RTYywVBgn609VLqV qe13yTjGamRyH6nMG2WuNHGMe6sAxxq+75bEmdMPDwPcLR5kC9YGuCGCmHv52e5b9F6r IcGuYlAAbsqR/oy/FQbYfza/kyWMfSRLwZtMCkooY+JCEdWvXRsPio48KWb5j+eSPVdD gh+D0usVuFNSAxLEeQtyOD9iy75OMy10tVpjDF+609l8rNxHbBJXdWgpFRlyLUXxOQSe I7cvlX5z4FadGaFantktJwjlY8W5d5540jxpFBouFeZiP3bnW4KTIUuiDf5YVccZyseP +HPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Zyf5KeX485BwSvF4JRLk5yqw2oK9iCIE3vprdtELuiE=; b=CdcWa8aNrPsXIYo4J5LpWlQTPmycpUsEfQJkRi5GLCY+Kv1CSD8eVOHVthDAkOYF68 15iKJjfchEIPrnxcEb9wp1DIUzJAIExD1A1+PT5qFy3mud0XoEWviF8kooB9C5iZaCgB dwh/FdygQiK726XORlgVt7Ool8Bv6kh1yn1uFsfQ2kS08q/+Mlk1Pm8FS43YYLQj9TK8 /AyDr2eg2TQurFJHr1Mb9tmaVB2hHrCNqZrtR5oGLmBF/6dGzO388RdoeNAedYq/jOid qtXFAVV2OipjnT5Ye0Kcsq4czbroyBYYQm1tubkk6nPP4MtBYYUvgiC01x649Rv74XEB vKZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RsRs+0yN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- linux-user/host/mips/host-signal.h | 62 +++++++++++++++++++++++++++++- accel/tcg/user-exec.c | 52 +------------------------ 2 files changed, 62 insertions(+), 52 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host-signal.h index f4b4d65031..9c83e51130 100644 --- a/linux-user/host/mips/host-signal.h +++ b/linux-user/host/mips/host-signal.h @@ -1 +1,61 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef MIPS_HOST_SIGNAL_H +#define MIPS_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.pc; +} + +#if defined(__misp16) || defined(__mips_micromips) +#error "Unsupported encoding" +#endif + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn = *(uint32_t *)host_signal_pc(uc); + + /* Detect all store instructions at program counter. */ + switch ((insn >> 26) & 077) { + case 050: /* SB */ + case 051: /* SH */ + case 052: /* SWL */ + case 053: /* SW */ + case 054: /* SDL */ + case 055: /* SDR */ + case 056: /* SWR */ + case 070: /* SC */ + case 071: /* SWC1 */ + case 074: /* SCD */ + case 075: /* SDC1 */ + case 077: /* SD */ +#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 + case 072: /* SWC2 */ + case 076: /* SDC2 */ +#endif + return true; + case 023: /* COP1X */ + /* + * Required in all versions of MIPS64 since + * MIPS64r1 and subsequent versions of MIPS32r2. + */ + switch (insn & 077) { + case 010: /* SWXC1 */ + case 011: /* SDXC1 */ + case 015: /* SUXC1 */ + return true; + } + break; + } + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0810b71ba0..42d1ad189b 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,57 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__mips__) - -#if defined(__misp16) || defined(__mips_micromips) -#error "Unsupported encoding" -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - uintptr_t pc = uc->uc_mcontext.pc; - uint32_t insn = *(uint32_t *)pc; - int is_write = 0; - - /* Detect all store instructions at program counter. */ - switch((insn >> 26) & 077) { - case 050: /* SB */ - case 051: /* SH */ - case 052: /* SWL */ - case 053: /* SW */ - case 054: /* SDL */ - case 055: /* SDR */ - case 056: /* SWR */ - case 070: /* SC */ - case 071: /* SWC1 */ - case 074: /* SCD */ - case 075: /* SDC1 */ - case 077: /* SD */ -#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 - case 072: /* SWC2 */ - case 076: /* SDC2 */ -#endif - is_write = 1; - break; - case 023: /* COP1X */ - /* Required in all versions of MIPS64 since - MIPS64r1 and subsequent versions of MIPS32r2. */ - switch (insn & 077) { - case 010: /* SWXC1 */ - case 011: /* SDXC1 */ - case 015: /* SUXC1 */ - is_write = 1; - } - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__riscv) +#if defined(__riscv) int cpu_signal_handler(int host_signum, void *pinfo, void *puc) From patchwork Sat Sep 18 18:45:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514244 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp677106jao; Sat, 18 Sep 2021 12:08:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz2MRbPF3FDvQwTTI2QYNJ5qNAn57WOR7ir+ihes9oA/RjphMPW48ulVUcLNuwwZqsUPpSO X-Received: by 2002:a05:6e02:1c2c:: with SMTP id m12mr9201677ilh.114.1631992122766; Sat, 18 Sep 2021 12:08:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631992122; cv=none; d=google.com; s=arc-20160816; b=pTTgVI+jrKBJqLEIjehqM3ZdZfBtWJy8ATuqKuXFpyL7Q1dQz2x9O4ByV2LRijreEK EViMgS6U8rMGqANK9RM6QOoZUvmX+gm+mqQKGxmmMZW3xOyi+hYsj8Vw5owZnpmE4s1t T3+njgLcz5p9T6u9pMrDoQ7z8w7qEyGjGEwDdFJk1twvEcxQ0HjkfJatMCSkqj3M57lc 1I4ft5igrKv/SLobw02e1kIhMa1rKDSYd03CRoZdWxqqivhYqRUJVC3CowUFPeKuq2+N +gTlVx6kLk9jN5dwviBpUrA27bqpE1uXvfhCe7iFgV+ClOYEmZ1lII8/8+G/K0JywFMF H4AA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=b88MeJ0VB21CqXeC9kfaVd7KTqjTS4pXJD2Bd6nXvIA=; b=E6R+K63seeB75sqD/9Fid6rw+U2RwET2gGENkW+OA2unZFTmnWYRmGhEMaFnvvWOZ7 a5HRKFZcMOara9VdTgvkPEqrPWz/ikAIxzIK7ofBOwjbKgr4rc2x5nv0sec/o2tF3QNg e+vxU/SRcOqyOuE1ncI4G5GpZVOYyyEgadTfik5WEWfHN69+0MlHKc4QU54Yn1Yu2z3s Et+pv9QK8mf+ivKjncAMDmGaH1xH/aNjBWyfojJsvzQPvgkPsHJ6eu7bsgvVlQAfg71X qiYHYIJ2NZexJ6fu5sc1D/8AYbm4S2e6nDBKTlnkg96WmZihXKD574qZ/l68Bz0ERrbv Hqmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LdR2CNYF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 85 +++++++++++++++++- accel/tcg/user-exec.c | 134 ---------------------------- 2 files changed, 84 insertions(+), 135 deletions(-) -- 2.25.1 diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/host-signal.h index f4b4d65031..5860dce7d7 100644 --- a/linux-user/host/riscv/host-signal.h +++ b/linux-user/host/riscv/host-signal.h @@ -1 +1,84 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef RISCV_HOST_SIGNAL_H +#define RISCV_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.__gregs[REG_PC]; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn = *(uint32_t *)host_signal_pc(uc); + + /* + * Detect store by reading the instruction at the program + * counter. Note: we currently only generate 32-bit + * instructions so we thus only detect 32-bit stores + */ + switch (((insn >> 0) & 0b11)) { + case 3: + switch (((insn >> 2) & 0b11111)) { + case 8: + switch (((insn >> 12) & 0b111)) { + case 0: /* sb */ + case 1: /* sh */ + case 2: /* sw */ + case 3: /* sd */ + case 4: /* sq */ + return true; + default: + break; + } + break; + case 9: + switch (((insn >> 12) & 0b111)) { + case 2: /* fsw */ + case 3: /* fsd */ + case 4: /* fsq */ + return true; + default: + break; + } + break; + default: + break; + } + } + + /* Check for compressed instructions */ + switch (((insn >> 13) & 0b111)) { + case 7: + switch (insn & 0b11) { + case 0: /*c.sd */ + case 2: /* c.sdsp */ + return true; + default: + break; + } + break; + case 6: + switch (insn & 0b11) { + case 0: /* c.sw */ + case 3: /* c.swsp */ + return true; + default: + break; + } + break; + default: + break; + } + + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 42d1ad189b..01e7e69e7f 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -139,64 +139,6 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, } } -/* - * 'pc' is the host PC at which the exception was raised. - * 'address' is the effective address of the memory exception. - * 'is_write' is 1 if a write caused the exception and otherwise 0. - * 'old_set' is the signal set which should be restored. - */ -static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, - int is_write, sigset_t *old_set) -{ - CPUState *cpu = current_cpu; - CPUClass *cc; - unsigned long host_addr = (unsigned long)info->si_addr; - MMUAccessType access_type = adjust_signal_pc(&pc, is_write); - abi_ptr guest_addr; - - /* For synchronous signals we expect to be coming from the vCPU - * thread (so current_cpu should be valid) and either from running - * code or during translation which can fault as we cross pages. - * - * If neither is true then something has gone wrong and we should - * abort rather than try and restart the vCPU execution. - */ - if (!cpu || !cpu->running) { - printf("qemu:%s received signal outside vCPU context @ pc=0x%" - PRIxPTR "\n", __func__, pc); - abort(); - } - -#if defined(DEBUG_SIGNAL) - printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", - pc, host_addr, is_write, *(unsigned long *)old_set); -#endif - - /* Convert forcefully to guest address space, invalid addresses - are still valid segv ones */ - guest_addr = h2g_nocheck(host_addr); - - /* XXX: locking issue */ - if (is_write && - info->si_signo == SIGSEGV && - info->si_code == SEGV_ACCERR && - h2g_valid(host_addr) && - handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) { - return 1; - } - - /* - * There is no way the target can handle this other than raising - * an exception. Undo signal and retaddr state prior to longjmp. - */ - sigprocmask(SIG_SETMASK, old_set, NULL); - - cc = CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, - MMU_USER_IDX, false, pc); - g_assert_not_reached(); -} - static int probe_access_internal(CPUArchState *env, target_ulong addr, int fault_size, MMUAccessType access_type, bool nonfault, uintptr_t ra) @@ -255,82 +197,6 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__riscv) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - greg_t pc = uc->uc_mcontext.__gregs[REG_PC]; - uint32_t insn = *(uint32_t *)pc; - int is_write = 0; - - /* Detect store by reading the instruction at the program - counter. Note: we currently only generate 32-bit - instructions so we thus only detect 32-bit stores */ - switch (((insn >> 0) & 0b11)) { - case 3: - switch (((insn >> 2) & 0b11111)) { - case 8: - switch (((insn >> 12) & 0b111)) { - case 0: /* sb */ - case 1: /* sh */ - case 2: /* sw */ - case 3: /* sd */ - case 4: /* sq */ - is_write = 1; - break; - default: - break; - } - break; - case 9: - switch (((insn >> 12) & 0b111)) { - case 2: /* fsw */ - case 3: /* fsd */ - case 4: /* fsq */ - is_write = 1; - break; - default: - break; - } - break; - default: - break; - } - } - - /* Check for compressed instructions */ - switch (((insn >> 13) & 0b111)) { - case 7: - switch (insn & 0b11) { - case 0: /*c.sd */ - case 2: /* c.sdsp */ - is_write = 1; - break; - default: - break; - } - break; - case 6: - switch (insn & 0b11) { - case 0: /* c.sw */ - case 3: /* c.swsp */ - is_write = 1; - break; - default: - break; - } - break; - default: - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} -#endif - /* The softmmu versions of these helpers are in cputlb.c. */ uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) From patchwork Sat Sep 18 18:45:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514243 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp676994jao; Sat, 18 Sep 2021 12:08:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyoyCCqCoMssOmpagQUxhY5gds7N7fFZK5V/0RmKEQejCXr0R3bGjKmqQzFJqZvjydoYXcQ X-Received: by 2002:a5d:80cc:: with SMTP id h12mr341964ior.57.1631992112483; Sat, 18 Sep 2021 12:08:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631992112; cv=none; d=google.com; s=arc-20160816; b=HWedobPGhfQjmOy2vZd5Ue8nSaTihmHWVCXiKlepwW8QZtxeeEo7zDMlWVFeqX2OvA GOlYaxaCFR2AnJgOgEOfrZ9ufit4c++tF6JGzExJM0Vzu7EYQB0Q81JOlYGgElfmTIH5 mLusGGxBMeqsq/mdqBTJsjvSglZaq2QsEZS8vj01Gy5OMgosTQtMMw2BVdAFkspgtfhk VpxugmilDlL1Ka1BbckOgEsvvTk0GVJ9yFeUGpGuqpUqBCYVT1se7teqkzjcRWoBqGER Ad1Rod52HJ0mxnE/bqlRiNKew6cxAqVXpYDHUp+0ItlHH7QRPAHawXZYgMR88d+Rrn6X 2s6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+vyWXP6Fx9Nim2ldoxF0eSsJbEhC7OEjuYcEJUYRKoA=; b=NfWVk9MJULuSuT5xbWpDIrDlwmRuE1tkp/H9KBMUtwMOFWDq3Ep+lkdCCnhAH/KwYi /Bj4sFqwWsqswvBeO3jo9s5PPmnLxgfeQjv+7z9hL038ZD4o5/WoluBpajowjsA7taZe roMQratFoImKfwWDLpbP+hSd40K+bA0AcDwS/ZuSVtu1U0yq+dHR2hOunPUbbFhj1rZF n9xZQL+PcSg4df6CV6OmsDaX0hJ7nMtyKJafqvXxV9RlTrM/XREWnJ3yNRM8hEQJ0rcg hzehe2H+LcaornGwLkYN6N3VdlwxAj4eZXzl13cyQro28NYrGjdCV5MykjcChWhxtNwN Zurw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lSzfsfsC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v189si9260346iof.75.2021.09.18.12.08.32 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 12:08:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lSzfsfsC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38386 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfhP-0002dE-Tn for patch@linaro.org; Sat, 18 Sep 2021 15:08:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54330) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLQ-00057s-NE for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:53 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:52164) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLN-0006og-0K for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:47 -0400 Received: by mail-pj1-x102d.google.com with SMTP id dw14so9179761pjb.1 for ; Sat, 18 Sep 2021 11:45:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+vyWXP6Fx9Nim2ldoxF0eSsJbEhC7OEjuYcEJUYRKoA=; b=lSzfsfsCZSvKw/DRgMkbB3UFuKC3OC9O/n9STdBep8+NCfDHpq2SG4lRQTixcVHBaL gOrchSfrhmozVAylVdlcrRrS/VxcM54OTX2LCrTB35XOXWqk0dTmhqn8ShHO57A1t3YK Krxc21pdtuIMBfoutvTVLRUQzr2/aQR7equgmW4gLpEH3vYDCqW7NKCCnUDIRsIGg88T 9ut//V63ESvrPhTljEq48zSnRxsA4iF+IY8t9lB/3KL9kkLFqZV8JjuO/ELGc6a+oeUJ mR2R1ZXKe8MKeCzGswFi0QT2SLC9QP7svABPJPNQqwaa59vP++tbRPCmNptFH+hAnvOf kYqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+vyWXP6Fx9Nim2ldoxF0eSsJbEhC7OEjuYcEJUYRKoA=; b=q9wvsHfcK4M21vjoeM0aZ814He/lJ5iXQj43nCSt7Akec/ETyqqpTdS4hw9lFv79qc t2XF566OyEbcgR6jyJSjxG7V/WnDk29yAh7wB8cylXtsmsrHoDZB24r3abpBPwpCEJDC jRZtQLUIvc8xs7dGNDqnjEGDbZ0AhB1gPxxnj8wnalX3YLZqlSIrGXBfLwXLMeJU4uFg jFlCGOL9Sni133ITx1oca5r+sNwVuOv6S2nUToUSnquvq5OK6xPZvfbsOOhPHMeE7j3n aNnf1GRFZ/974SHayzOZdXIp/IRdUC88rAwuD3kNlA/tpWMHj4GqotPmN/bLLlfwUfyU doag== X-Gm-Message-State: AOAM530tj3Uj1Po99Jgw6tksuExCdEGMoH4YFxeZqdZTZJqNU1osAr1T /7+yyss7JQTfdm+AIw9Gn/ZwyXlYS1tfTQ== X-Received: by 2002:a17:90a:428e:: with SMTP id p14mr28718674pjg.92.1631990742570; Sat, 18 Sep 2021 11:45:42 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 16/41] target/arm: Fixup comment re handle_cpu_signal Date: Sat, 18 Sep 2021 11:45:02 -0700 Message-Id: <20210918184527.408540-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The named function no longer exists. Refer to host_signal_handler instead. Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index dab5f1d1cd..07be55b7e1 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -6118,7 +6118,7 @@ DO_LDN_2(4, dd, MO_64) * linux-user/ in its get_user/put_user macros. * * TODO: Construct some helpers, written in assembly, that interact with - * handle_cpu_signal to produce memory ops which can properly report errors + * host_signal_handler to produce memory ops which can properly report errors * without racing. */ From patchwork Sat Sep 18 18:45:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514223 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp667553jao; Sat, 18 Sep 2021 11:51:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxtTe3amG1aJNRSD9l076jpOyf96JcvC/rZSbLlXjlDORvfxEP7JkSv/m0ZO8PP/+hoHr61 X-Received: by 2002:ac8:7fcb:: with SMTP id b11mr15817339qtk.115.1631991082693; Sat, 18 Sep 2021 11:51:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631991082; cv=none; d=google.com; s=arc-20160816; b=iMG/QzhmbJe1t0Ki8nAIpI6k7hkGMz0mRshB9haAsE3f1zNUcbvO9jzVD2WQeqKCcX VVVwvKJmnxqIX4ChgjIuruDNhxPFddD5j+0D3uKcj1LhYAgq1KyMEJU7BbBL2EkLtHox cGCx/vO96odzKR7rpKUxFUFT/+SiwRtbNZSeDo8aaQzZZtjgGOummT/smgRipq+10hRD TbNgfinYNhJLSrfLTjwopW+oKrD4WO6QTiBN2AxqxkhyR5kdm9yjeFhXJN6UxwSr9fGs flx8j5HyEyxnjkE6uhYi8uDLsvsUbMkorFwxVF6Q1QE+TFRt3SEzQj3x9X1kknGQccqe SACg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nMBhe6wRyQJffJfKqR3e4B4BjhzuFHvBY7lYZ6XbL2k=; b=uVQ6PVLClRaMKZIKqEivaKiBkSYg49eayuW8w72Sk+ujTSX0bfgNt+r4kl/x/6y742 bSlVOCP2gRcPOutiOEs+i1/IgvVtjwClOSEnZToFquJd/0LRygh7dRtHYhh15BhiTC1+ VUXqfZhOFuvRePJCg38x0klJ0xlpkHoFcDhuWFqmfahxS6jvoMACPTmgVIQ/UDEIJV8I elqWfBi0gAnlNT2wpsW30/5hXKAhBnlGI10fcLrUwEHjvjllgCQn5Sz/Fn5sHgtNgml9 RQ5zAp8a/tHx+nGzyljSN02N4Qhz8+tHGlxvdCMwaF21hPt43cnndXgBpbmvE9fgJjHg +ZHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gMJHG5IG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n10si6338378qvl.159.2021.09.18.11.51.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 11:51:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gMJHG5IG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44602 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfQo-0002Sf-7n for patch@linaro.org; Sat, 18 Sep 2021 14:51:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54360) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLS-00057y-4V for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:54 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:34709) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLN-0006pp-2w for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:49 -0400 Received: by mail-pf1-x42b.google.com with SMTP id g14so12396080pfm.1 for ; Sat, 18 Sep 2021 11:45:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nMBhe6wRyQJffJfKqR3e4B4BjhzuFHvBY7lYZ6XbL2k=; b=gMJHG5IGY0Go92Rn8xQnpykiF+BXx9y5AoInPCg6RLWbaXuFJDSIfh4uu1YMBLHNdW fF/25L6w6/Vn9HajjwdyUsN26WysJxG/P4F3ZwyVUIuO7qano3f1Wl9zNWvHUFiqyh7q XC3gH0zOTxfWzMaoMeWnecv1yBxilgUSkZ368F0DGy1mrLX5NAjYNuCNguKY4/hwMaQ0 gAXQqqhdA9Ss9Lz+xVcXrgBtGB30fNY3e4Iw1d+w/bUKSdEQaDvknP/R60tvT/P9UIoJ B49GeUgOx8M1J6gwMNyQ2JJL+FcwaR+gAGp0rvhqz8SEYTfWNVBhTMcWgctVE79kQIlO Zv8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nMBhe6wRyQJffJfKqR3e4B4BjhzuFHvBY7lYZ6XbL2k=; b=LyR0p9JUhsqDt0mr6IAMxwf6BVVeoyEPzyQ2TuDd089UJ2b4IiWK9g9jvMKV/dbvF1 PtBTUiRiJ7uH2W+UT3QwujDWBQg0jr/qi7/dj97gVx1vToN88t4R/nQnjA7pRD9/ZaJO 1oHoKXCtSJSvuxWD+5U70Bt9gdk9+cD+/iRqy2qzlnYd7L1nptEA0mKslBIjp24tjQDk gK2BEMrxiiOc8ViGstB6Dqg3LvvkkFAWfJNo89SdUrhoKnqEY5NT4osVPsLoMKeqm144 sCuKGbfgSahz16WI43ZmhQhvYukFeRHaiLDoEOeZIQ2CQX46Oc/VaX1FX7oyIsENy1i5 X/TA== X-Gm-Message-State: AOAM5335xuIE0DJGQL5nC3XAdcoFV3af6i8zMy5sL0c3ylSOBdrNITj9 QgJCO1QvteWdbLAruDS3sqqg6/fXj+fonA== X-Received: by 2002:aa7:9094:0:b0:42a:ea30:5509 with SMTP id i20-20020aa79094000000b0042aea305509mr17464303pfa.30.1631990743400; Sat, 18 Sep 2021 11:45:43 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 17/41] linux-user/host/riscv: Improve host_signal_write Date: Sat, 18 Sep 2021 11:45:03 -0700 Message-Id: <20210918184527.408540-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not read 4 bytes before we determine the size of the insn. Simplify triple switches in favor of checking major opcodes. Include the missing cases of compact fsd and fsdsp. Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 83 ++++++++++------------------- 1 file changed, 28 insertions(+), 55 deletions(-) -- 2.25.1 diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/host-signal.h index 5860dce7d7..ab06d70964 100644 --- a/linux-user/host/riscv/host-signal.h +++ b/linux-user/host/riscv/host-signal.h @@ -17,65 +17,38 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) { - uint32_t insn = *(uint32_t *)host_signal_pc(uc); - /* - * Detect store by reading the instruction at the program - * counter. Note: we currently only generate 32-bit - * instructions so we thus only detect 32-bit stores + * Detect store by reading the instruction at the program counter. + * Do not read more than 16 bits, because we have not yet determined + * the size of the instruction. */ - switch (((insn >> 0) & 0b11)) { - case 3: - switch (((insn >> 2) & 0b11111)) { - case 8: - switch (((insn >> 12) & 0b111)) { - case 0: /* sb */ - case 1: /* sh */ - case 2: /* sw */ - case 3: /* sd */ - case 4: /* sq */ - return true; - default: - break; - } - break; - case 9: - switch (((insn >> 12) & 0b111)) { - case 2: /* fsw */ - case 3: /* fsd */ - case 4: /* fsq */ - return true; - default: - break; - } - break; - default: - break; - } + const uint16_t *pinsn = (const uint16_t *)host_signal_pc(uc); + uint16_t insn = pinsn[0]; + + /* 16-bit instructions */ + switch (insn & 0xe003) { + case 0xa000: /* c.fsd */ + case 0xc000: /* c.sw */ + case 0xe000: /* c.sd (rv64) / c.fsw (rv32) */ + case 0xa002: /* c.fsdsp */ + case 0xc002: /* c.swsp */ + case 0xe002: /* c.sdsp (rv64) / c.fswsp (rv32) */ + return true; } - /* Check for compressed instructions */ - switch (((insn >> 13) & 0b111)) { - case 7: - switch (insn & 0b11) { - case 0: /*c.sd */ - case 2: /* c.sdsp */ - return true; - default: - break; - } - break; - case 6: - switch (insn & 0b11) { - case 0: /* c.sw */ - case 3: /* c.swsp */ - return true; - default: - break; - } - break; - default: - break; + /* 32-bit instructions, major opcodes */ + switch (insn & 0x7f) { + case 0x23: /* store */ + case 0x27: /* store-fp */ + return true; + case 0x2f: /* amo */ + /* + * The AMO function code is in bits 25-31, unread as yet. + * The AMO functions are LR (read), SC (write), and the + * rest are all read-modify-write. + */ + insn = pinsn[1]; + return (insn >> 11) != 2; /* LR */ } return false; From patchwork Sat Sep 18 18:45:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514240 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp676035jao; Sat, 18 Sep 2021 12:06:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw20USJ+Uoc4G0AwMQRmR1rrZkWFN/WolgzhjGmhsWckBH4W7/r6saY8Dkc9bUkT6wM32fI X-Received: by 2002:a92:444e:: with SMTP id a14mr12700533ilm.152.1631992010113; Sat, 18 Sep 2021 12:06:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631992010; cv=none; d=google.com; s=arc-20160816; b=gJwN92/AalyiVRASYnmqdsO6LMuEdiNhorkl8PJktxZoKfWlgkrO67uJENgUnB3RbQ Q8FPuGM7Ukx4978GtG0Fv+pOMu3GFcwaZNb72805HZjZTx2r39kxYtEyytQnTfNpGdgK tH63V0ClT0alNwpac54mZyiY8zVevVKwMfq/Dzrnge2Iw0qZIf2cTYr5oTO7yfkhDNP8 CibuOl9Z4SUc4hag5AztIrnbEwFVJN9wWJ14jyC0c19UKwEhCaolRMZlW+xlpEFnTmjp wk+cX4FgrYpbPQDxXa8uBsklC32lGrEpkVa86zl70q8hK5ReR/UO2gNHO1z27w8+fm1c CJbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mkpDyQi3PMKrFdlMQCQLbDcKXDWO1ARW+CoOrVOZKpc=; b=KOk6EymXKoFuNW3olur9Fc0F/pKTqvR4nHff7TDgdZRgXIwUBW4R0ltOtBu9++Xgec p4fvhnZJXJ4ahLKwWFgsGIIINGnsA150GvL7/gPpOPj/k5yem97O/cpodLaIkkPW3XQ5 EM6WpDrxjIj0HHnDKRv/QddDgpr9fOHVIM04AuILNSZLzXo083EyebOfID48ARebWQDG ViYIlGPOmqrCqBBRJs8cm6fO/DztUYffr0hdx8aCIiSQFU2KsZ9n1hqwtJ3XD2rHaEVK ohyeYwjSyHf27bTR/zLCMSApMyiFg5jOhfuJh7yf48OU6JtJagqGD/BFkVbS/xx3Hz8R S24w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="C08oYr/s"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 13si10611955jan.43.2021.09.18.12.06.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 12:06:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="C08oYr/s"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRffl-0005iA-HK for patch@linaro.org; Sat, 18 Sep 2021 15:06:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54328) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLQ-00057r-MY for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:53 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:41768) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLN-0006qi-K6 for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:47 -0400 Received: by mail-pj1-x102d.google.com with SMTP id m21-20020a17090a859500b00197688449c4so9813119pjn.0 for ; Sat, 18 Sep 2021 11:45:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mkpDyQi3PMKrFdlMQCQLbDcKXDWO1ARW+CoOrVOZKpc=; b=C08oYr/sxbSpb6AQYxQFXBxty12fy9N81y/zC20rgTXkfzyDq6pluJnlOC4zwqp4+t BRxoJEsIezBPfIJewy5xd7cBRuI3Z+4r69YyFCmTZnniMC18f0T1zGQ0UF0piFaXRGXg sJR1VPKBrqGaH5OKnLXZ0N4wS4Ox3shTDn8CDzjz94Ple3dr0hPKH0+GG8tWvtR/+Q6B NH1ZgKGKRIWyw4w44dAV+fJgv0kD5+e+P827s0iGefr6mly+tQSEZQVP4dD7AP8JjvbK qaG0d9+vK1CnEEiO5SD0svIe22YnlgH+Z6dXocl8jPJQsVxw0u2lQkuWwyOFWW08i1nq BwWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mkpDyQi3PMKrFdlMQCQLbDcKXDWO1ARW+CoOrVOZKpc=; b=EBOk6dH244ygYcaUQTiclqCU5RmIvoUV7ppVLWUl0mp4vStNwFOI2oeV39T0hqq7b/ oiOrA/1LUU/50yjABYrJEnwgpBwDRB/Waj8UZIuVbuXHw/L6MSmYcSwct7DIO00JYm0s kP5btGS8k9pWKkUOVRTLzl2OuiwI531e5wCOSqjF7sClvdorppq3htiInyf9KgeX4Tx3 cmuN3s2BIViWlky4Vq2Lik5HjfIIXb1BCGUduChi6YQHmHQvNg476kcqlkA3BCZGGZhv DZIB8Mh5aF3+HI6nW0vM57U4jd2aNpCmJWggENxgnRBw4rw7kl4gSaAf3O6GcCcIgi5S OmPw== X-Gm-Message-State: AOAM531SSGPxJfQc7QT+simDFxbfhocarFmAO0KV6Z3Qp0XcDItmsszU s2NjuIOfAdNv1YN00NfQ7CMApwFDln428A== X-Received: by 2002:a17:90a:191a:: with SMTP id 26mr19997917pjg.79.1631990743992; Sat, 18 Sep 2021 11:45:43 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 18/41] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Date: Sat, 18 Sep 2021 11:45:04 -0700 Message-Id: <20210918184527.408540-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that all of the linux-user hosts have been converted to host-signal.h, drop the compatibility code. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 12 ------------ linux-user/signal.c | 13 ------------- 2 files changed, 25 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5f94d799aa..5dd663c153 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -685,18 +685,6 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, uintptr_t host_pc, abi_ptr guest_addr); -/** - * cpu_signal_handler - * @signum: host signal number - * @pinfo: host siginfo_t - * @puc: host ucontext_t - * - * To be called from the SIGBUS and SIGSEGV signal handler to inform the - * virtual cpu of exceptions. Returns true if the signal was handled by - * the virtual CPU. - */ -int cpu_signal_handler(int signum, void *pinfo, void *puc); - #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/linux-user/signal.c b/linux-user/signal.c index 6f953f10d4..e6531fdfa0 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -773,16 +773,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) ucontext_t *uc = puc; struct emulated_sigtable *k; int guest_sig; - -#ifdef HOST_SIGNAL_PLACEHOLDER - /* the CPU emulator uses some host signals to detect exceptions, - we forward to it some signals */ - if ((host_sig == SIGSEGV || host_sig == SIGBUS) - && info->si_code > 0) { - if (cpu_signal_handler(host_sig, info, puc)) - return; - } -#else uintptr_t pc = 0; bool sync_sig = false; @@ -842,7 +832,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) sync_sig = true; } -#endif /* get target signal number */ guest_sig = host_to_target_signal(host_sig); @@ -857,7 +846,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) k->pending = guest_sig; ts->signal_pending = 1; -#ifndef HOST_SIGNAL_PLACEHOLDER /* * For synchronous signals, unwind the cpu state to the faulting * insn and then exit back to the main loop so that the signal @@ -867,7 +855,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) cpu->exception_index = EXCP_INTERRUPT; cpu_loop_exit_restore(cpu, pc); } -#endif rewind_if_in_safe_syscall(puc); From patchwork Sat Sep 18 18:45:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514221 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp667547jao; Sat, 18 Sep 2021 11:51:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxCVqzhH3cBGMcesdNZhQE/OHr/EtEnna2k9gcPMhX2qdoyq41ZahZGH+qMgV7C3sg6zx8c X-Received: by 2002:a05:620a:5f7:: with SMTP id z23mr16305849qkg.449.1631991082216; Sat, 18 Sep 2021 11:51:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631991082; cv=none; d=google.com; s=arc-20160816; b=cM5xTOmagFqHqoBwNblgs8eLipAAXGHxAwZHApAloqj5vbuGHfyCIZe0A3uRgM1CLX 8v01DffwARoAk+repMBptbr8QQnY8MF3dJZRfWld3nS37FaLmvuWZS7ESTIWLWGRQqeG PTC6xVQ1c+ZyNRrowrA2WZ/WzvvcleWWE5iSVwCH6XU+4Ah/pR6m/ClxJThBM+K8OHmi hyFek7wsLNtRzz+evTBwoqXlbI+cK9kXRVMIwgzvizHSGNCqQdbUe+a7LgVvtljXb5ak tPnwoI/Rm/FxH+CknywNdKXnD6VgTAprkCdD3USMBPsdnMWBKAigPiaHPteFfzcarbHJ BVgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nrD8E65gnfBNS6+ihjsgMJcAs7qIa3jYuvmEwiwusrE=; b=DbNpU5na30KLdjX8WcvjbKsiVPSl5kLHBVCRyMxEawsCf2Pgkqxk2RJA6stsuhF68a khB5drcAENRBPWbSN+W3Qx4rA52bxn0qfAPyBabB8TOInkI+99RVxn1WLNzTq4IGWyN4 v5XUMS+LkAsnraox1E0dknSqy+rNWw33S7r38KMNqQOenz4/woNhTzlF/CGl6MVtRLrF CopJe7+OPI0E8bwxUzGoyxjSwVyryzBy44iw07gvJkTycO1wWs95TCt/BG7OKDqLgwwZ HNU/yzex0p9KyrrzY86aaH4wMk59oZ3znByS7OAKE+2/B+ItGHMpIMQh/eMDQLoQTpoc Zq8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xzQZf8q0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ib6si1667248qvb.93.2021.09.18.11.51.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 11:51:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xzQZf8q0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44572 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfQm-0002RN-My for patch@linaro.org; Sat, 18 Sep 2021 14:51:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54430) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLb-0005Bb-9q for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:00 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:40626) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLN-0006qv-Sf for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:53 -0400 Received: by mail-pg1-x529.google.com with SMTP id h3so13086393pgb.7 for ; Sat, 18 Sep 2021 11:45:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nrD8E65gnfBNS6+ihjsgMJcAs7qIa3jYuvmEwiwusrE=; b=xzQZf8q0aioXJDqYBn2Hva+H5t5SIO5qSkagItq/E7Yd5xot92n0AcOwyqJapGf1NU IH9gKiFNJEiS2aZvBEKPALKxiOdofYKkQHeMNkPOt5oHdNIxLObA3lldX47h94+zdH4q FozT686IM7OUdnRbb1pptcMqlh/xBw24DMD8abpbaEAwKliTN7LJogEtJv5xSL6lwC4+ 3qO3U11h7mGx93ODo2VAAWdpYAcgOoYHY2z5qBuca1yiw5LroE8gRW2QgzALQqd3643w /od4Wz7wmME3ImSL9PvNrmrvnU5rV/3XvlPT7nuEWbZ8r45+lPtGE3B9zEdwdKLBpM7E 3+9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nrD8E65gnfBNS6+ihjsgMJcAs7qIa3jYuvmEwiwusrE=; b=BRO/gz535i2rUhfL0xxk0vjvIZTJSk5NvRp8l5GhhJ3y1lj09Ol/5ZgKcpgS66nhhZ PsFXQmcNvxWlTNX7vbW/yTJTzflnoRELefFD/C9teXAjP15utp7OqMr+wIFYj8fgwtTb QgE11sM/NdsOMtvbhTILbOcGE3fhtGPByUCTvdY917QCmY7c+5yGWZrr7BPLPQSbA3b0 wiUkPLHEOFE+xfZdZFWPz9V5p+zvQ+RG6lS/EFU+Nq7As9a6RtA24VMgduKpg5Dle6nD W2xluMw58Lk7lY8dctbRNTWWDIJipUuM1UO0uM920VOL+8Tob0h6YKRYtikB2JBfFFgl f+oA== X-Gm-Message-State: AOAM530XxHvWODhaPFurMJZ4YVs47aGZYseBvzdFx3r4Bo5dOwiku5EC WestgpapKwaGY9j1iX89ht5HFFNJ40wvZA== X-Received: by 2002:a62:194a:0:b0:43d:f06e:4f4a with SMTP id 71-20020a62194a000000b0043df06e4f4amr17025444pfz.20.1631990744594; Sat, 18 Sep 2021 11:45:44 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 19/41] hw/core: Add TCGCPUOps.record_sigsegv Date: Sat, 18 Sep 2021 11:45:05 -0700 Message-Id: <20210918184527.408540-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a new user-only interface for updating cpu state before raising a signal. This will replace tlb_fill for user-only and should result in less boilerplate for each guest. Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 4a4c4053e3..e229a40772 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -114,6 +114,32 @@ struct TCGCPUOps { */ bool (*io_recompile_replay_branch)(CPUState *cpu, const TranslationBlock *tb); +#else + /** + * record_sigsegv: + * @cpu: cpu context + * @addr: faulting guest address + * @access_type: access was read/write/execute + * @maperr: true for invalid page, false for permission fault + * @ra: host pc for unwinding + * + * We are about to raise SIGSEGV with si_code set for @maperr, + * and si_addr set for @addr. Record anything further needed + * for the signal ucontext_t. + * + * If the emulated kernel does not provide anything to the signal + * handler with anything besides the user context registers, and + * the siginfo_t, then this hook need do nothing and may be omitted. + * Otherwise, record the data and return; the caller will raise + * the signal, unwind the cpu state, and return to the main loop. + * + * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided + * so that a "normal" cpu exception can be raised. In this case, + * the signal must be raised by the architecture cpu_loop. + */ + void (*record_sigsegv)(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); #endif /* CONFIG_SOFTMMU */ #endif /* NEED_CPU_H */ From patchwork Sat Sep 18 18:45:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514231 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp670438jao; Sat, 18 Sep 2021 11:57:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzR3Vn52J8OyuhC3o+lbPvBqsq9HPH8yOstJ9Xqe3qEuDD//YTbqIZKPWDr2MeP6VcPYnBh X-Received: by 2002:a25:2485:: with SMTP id k127mr13175428ybk.71.1631991430535; Sat, 18 Sep 2021 11:57:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631991430; cv=none; d=google.com; s=arc-20160816; b=1DNYPHY+qoLz+MCcYYw9u1nC+8slMG2VxOtiX4P+L+Wc0kBFgfTZ4ZnXf6R9+xIVdd ThHM2g/vE+Biy1RnkeTdCLMr+RpHP3xq1y1rvERGbtS82HKxI9QaSXW6G86nQ/yzAZJQ U0f46X6FEJLNiVQh+YuVjeHO5+Et3AzWZI2T1MXX4R7HJhOPzjrv6LHQFp5gNFz009yA Nrg5bNIWTBjYt/vmbbEdFmZwJ0eEhgOcrzYLT98OKL6U/3YkW3luby+cKZw9gs04cHsl zw1wWCFRYARz+sVseA+Av0lb8ST+vQDz0N04FmNRnSPdBgkzbQlKbHDelm2jP0cDxuKV ui0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bUABOOKdTsHd1I4YhOWD+WaOacOY2c/QLq79HLsoZBA=; b=Iv8mQ3I7pfpnaFUAd5oW+7ZGl6gBZRQoTf39KKPLsnMDXZ4T0dX9bc1P5l/puQ++7G z9fY70mmwDTow2/iKtW1U/YpwE/sYe025tEl1OHt2GPRBg75PFCX3Xe+tV3l1GtGsrww idXnft+HhVi/SiMatKZTkcD/GTkyfcV6psZ9xqzOOMBMGTEjVwjaIa97bsQfSdgrT4GZ an3QNFEp9IGpyT1hjtTb5ZVl9GhlzFSri7xE5PVN+cJLwWJiw3kfima6wXuo/szzzyHa +iJnRGoA/9zv1x/Cl3IBPgNW4mIju9RERnKvzGwF3HNu1iD7bOhG8jvx4Fv9Vjkya6aI HLvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xBJjH7Xq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g132si4891774ybb.122.2021.09.18.11.57.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 11:57:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xBJjH7Xq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33522 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfWP-0005Ru-T0 for patch@linaro.org; Sat, 18 Sep 2021 14:57:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54504) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLf-0005Cz-PF for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:04 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:41489) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLP-0006r8-LB for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:45:59 -0400 Received: by mail-pg1-x531.google.com with SMTP id k24so13081116pgh.8 for ; Sat, 18 Sep 2021 11:45:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bUABOOKdTsHd1I4YhOWD+WaOacOY2c/QLq79HLsoZBA=; b=xBJjH7Xq4e8UymD4tS49FIHDlu3ITrRgnX0MoCCaDJX9km+bpGD7H+nkVYJsyekaX3 5xXIVAnrVyP3vMQqDVSL8o/Rm+U81kpfLhVUUHT7SvG2p6AiV9mDjX9U4CWZu+ZgT/y5 1iCNIvK+jhn5nBadtwdUg0/rLrNiBTFlSbwOCQqx5j5JGxEMIZkfyQWqomZk62H1EwEl xGj7FO39MZBXoI3eRxnD3J8D3H6ky3HqFOAWE1DbB+2pmMCc+nTrS3+NPzi2UpH3CK27 loNxkt9tKZC4mrHrtwJ63X2QQseK+rcqqzSXyc4BblH9EBWkor1JTE+kdxJVMv2966DJ bpDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bUABOOKdTsHd1I4YhOWD+WaOacOY2c/QLq79HLsoZBA=; b=aoWYhbz5Kb2BOYyavEAFLHekDeLX4Kzb6vq7Ndxeme5o1lRNctOIoGfOA+6xQjcitW +i4LgHF1i0MxWeNGbqFmsFnPQ8h0EodNdBBhc++334M1UtC/JCU1zi30Y+oTb28Dlxuw qW0F1/5UN/RBppd71Gme1x6lI10ksZCbVwPz7T03BvIq683NUXOSiBWeux1pgKiAa1L2 q+OlOjtlnqgD9LftjbzbtXHIgHzF8Wn1wY21piSQ6DCotoTVS6gRZ0R30ERI5s+QfokP oUBDZpcZMtYB3FYXNRcpCY2mnCL58eAdSUvwE+rjYeun8wPX4BoaUCFd3t1N9rWSngsy JzIg== X-Gm-Message-State: AOAM533gLsd4PV2KGPDlFn/qTMpPtK34Vql9a8N1QZxCHrxG4HkZZkew 42vdaPLwEerjzKUwWq5h2FH105CchJJo8w== X-Received: by 2002:a62:2cd8:0:b0:43d:e6c0:1725 with SMTP id s207-20020a622cd8000000b0043de6c01725mr17193710pfs.55.1631990745424; Sat, 18 Sep 2021 11:45:45 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 20/41] linux-user: Add raise_sigsegv Date: Sat, 18 Sep 2021 11:45:06 -0700 Message-Id: <20210918184527.408540-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a new interface to be provided by the os emulator for raising SIGSEGV on fault. Use the new record_sigsegv target hook. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 15 +++++++++++++++ accel/tcg/user-exec.c | 33 ++++++++++++++++++--------------- linux-user/signal.c | 30 ++++++++++++++++++++++-------- 3 files changed, 55 insertions(+), 23 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5dd663c153..2091c1bf1a 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -685,6 +685,21 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, uintptr_t host_pc, abi_ptr guest_addr); +/** + * raise_sigsegv: + * @cpu: the cpu context + * @addr: the guest address of the fault + * @access_type: access was read/write/execute + * @maperr: true for invalid page, false for permission fault + * @ra: host pc for unwinding + * + * Use the TCGCPUOps hook to record cpu state, do guest operating system + * specific things to raise SIGSEGV, and jump to the main cpu loop. + */ +void QEMU_NORETURN raise_sigsegv(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); + #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 01e7e69e7f..ab9cc6686d 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -143,35 +143,38 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, int fault_size, MMUAccessType access_type, bool nonfault, uintptr_t ra) { - int flags; + bool maperr = true; + int acc_flag; switch (access_type) { case MMU_DATA_STORE: - flags = PAGE_WRITE; + acc_flag = PAGE_WRITE_ORG; break; case MMU_DATA_LOAD: - flags = PAGE_READ; + acc_flag = PAGE_READ; break; case MMU_INST_FETCH: - flags = PAGE_EXEC; + acc_flag = PAGE_EXEC; break; default: g_assert_not_reached(); } - if (!guest_addr_valid_untagged(addr) || - page_check_range(addr, 1, flags) < 0) { - if (nonfault) { - return TLB_INVALID_MASK; - } else { - CPUState *cpu = env_cpu(env); - CPUClass *cc = CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_type, - MMU_USER_IDX, false, ra); - g_assert_not_reached(); + if (guest_addr_valid_untagged(addr)) { + int page_flags = page_get_flags(addr); + if (page_flags & acc_flag) { + return 0; /* success */ + } + if (page_flags & PAGE_VALID) { + maperr = false; } } - return 0; + + if (nonfault) { + return TLB_INVALID_MASK; + } + + raise_sigsegv(env_cpu(env), addr, access_type, maperr, ra); } int probe_access_flags(CPUArchState *env, target_ulong addr, diff --git a/linux-user/signal.c b/linux-user/signal.c index e6531fdfa0..ae31b46be0 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -681,9 +681,27 @@ void force_sigsegv(int oldsig) } force_sig(TARGET_SIGSEGV); } - #endif +void raise_sigsegv(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, bool maperr, uintptr_t ra) +{ + const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + + if (tcg_ops->record_sigsegv) { + tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); + } else if (tcg_ops->tlb_fill) { + tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, ra); + g_assert_not_reached(); + } + + force_sig_fault(TARGET_SIGSEGV, + maperr ? TARGET_SEGV_MAPERR : TARGET_SEGV_ACCERR, + addr); + cpu->exception_index = EXCP_INTERRUPT; + cpu_loop_exit_restore(cpu, ra); +} + /* abort execution with signal */ static void QEMU_NORETURN dump_core_and_abort(int target_sig) { @@ -799,7 +817,7 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) access_type = adjust_signal_pc(&pc, is_write); if (host_sig == SIGSEGV) { - const struct TCGCPUOps *tcg_ops; + bool maperr = true; if (info->si_code == SEGV_ACCERR && h2g_valid(host_addr)) { /* If this was a write to a TB protected page, restart. */ @@ -814,18 +832,14 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) * which means that we may get ACCERR when we want MAPERR. */ if (page_get_flags(guest_addr) & PAGE_VALID) { - /* maperr = false; */ + maperr = false; } else { info->si_code = SEGV_MAPERR; } } sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); - - tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; - tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type, - MMU_USER_IDX, false, pc); - g_assert_not_reached(); + raise_sigsegv(cpu, guest_addr, access_type, maperr, pc); } else { sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); } From patchwork Sat Sep 18 18:45:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514227 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp668632jao; Sat, 18 Sep 2021 11:53:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJySkvZYoHbMPMgBkXECqPLHjA+xdEMO/4wS6Ko7E7ndghLHZA5xlHWc9wSczmxdSRaeoH1l X-Received: by 2002:ad4:45e7:: with SMTP id q7mr17402088qvu.23.1631991207600; Sat, 18 Sep 2021 11:53:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631991207; cv=none; d=google.com; s=arc-20160816; b=escUQgFTUGMSMja4HTEi4FTcWC92GL3hcbCvElHFyg2ztmCbmbnDIfzK5l8EhJ9Yrl 7O6m9BUfu5exzFz4c0PKTxQLi25qH6eZ8t0NKvakU8ZYt2Eytxiy6+3vbQXhkvO96S+O iHWW9RipOYLLQVIG7+LTf4YWPVuZ/NBO5P+l8i6W4bGCpqUEQAUtxKwwM3R3NwS/MB6C TV+VqdvQi7nl3ym0C5jwgG9e3809atnJK6/x6/SlhRnPthGjkoxXY4M9ScikkDH4ZhMn han1vKtFgUUAk1oWAxWJCztA0m1z2JSJpyjqrEBKjlvtEmub7X+2rGu9UKh2fSycgn4U 3Ohg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6Qr0OuX9QX9R8kKysHcFpFuFjKaNccsgQik+Lfl3HtE=; b=BIQ9SKoaQtD/vNFcIWxy0VALWaR0PSGByVfejRfXb2e66OwmeMok0O5hJWapQUGrdi Nl0nF8XiN3H25zSpPaBuRimU84tDU2PjT3acCuFcooMVU95nBmn1H1ePAvPH/ja6jqF9 xDL6yqsfRI5iDfvyl8ki9bJ7IdBjBr5jTvWQ60hMMF+KW4GDtqfPFV3kLbLgIlwvFz5C u7HGqNemSM1B/Ct27aKVRFPlQsYAhmXNcMophegxgNyaKai2FHnLJ8WZFh+SaH4pGh8q VpSvp+nac3PsPhL5fxn8rbFQvAcIFc+FqOWboMGq8y1JPgYgkmsuphI4KUN1IXwpFSBF uIyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FEtv63qd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Remove the code from cpu_loop that handled EXCP_MMFAULT. Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 7 ++++--- linux-user/alpha/cpu_loop.c | 8 -------- target/alpha/cpu.c | 2 +- target/alpha/helper.c | 13 +------------ 4 files changed, 6 insertions(+), 24 deletions(-) -- 2.25.1 diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index ce9ec32199..cbca4c369c 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -439,9 +439,6 @@ void alpha_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU void alpha_cpu_list(void); -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); @@ -449,12 +446,16 @@ uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env); void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val); uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg); void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val); + #ifndef CONFIG_USER_ONLY void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #endif static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc, diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 7ce2461a02..60b650a827 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -52,14 +52,6 @@ void cpu_loop(CPUAlphaState *env) fprintf(stderr, "External interrupt. Exit\n"); exit(EXIT_FAILURE); break; - case EXCP_MMFAULT: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID - ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); - info._sifields._sigfault._addr = env->trap_arg0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_UNALIGN: info.si_signo = TARGET_SIGBUS; info.si_errno = 0; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 1ca601cac5..83c201d86a 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -220,10 +220,10 @@ static const struct SysemuCPUOps alpha_sysemu_ops = { static const struct TCGCPUOps alpha_tcg_ops = { .initialize = alpha_translate_init, - .tlb_fill = alpha_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY .has_work = alpha_cpu_has_work, + .tlb_fill = alpha_cpu_tlb_fill, .cpu_exec_interrupt = alpha_cpu_exec_interrupt, .do_interrupt = alpha_cpu_do_interrupt, .do_transaction_failed = alpha_cpu_do_transaction_failed, diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 81550d9e2f..266d56ea73 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -119,18 +119,7 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val) *cpu_alpha_addr_gr(env, reg) = val; } -#if defined(CONFIG_USER_ONLY) -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - AlphaCPU *cpu = ALPHA_CPU(cs); - - cs->exception_index = EXCP_MMFAULT; - cpu->env.trap_arg0 = address; - cpu_loop_exit_restore(cs, retaddr); -} -#else +#ifndef CONFIG_USER_ONLY /* Returns the OSF/1 entMM failure indication, or -1 on success. */ static int get_physical_address(CPUAlphaState *env, target_ulong addr, int prot_need, int mmu_idx, From patchwork Sat Sep 18 18:45:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514230 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp670403jao; Sat, 18 Sep 2021 11:57:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwT0NJnNvTEi4lhGg31OSqCbl/swS8xolg9ta3vnCnG06fhfZ0Dxm7Sf91ZZ8bEOvgY8G3q X-Received: by 2002:a25:2cc2:: with SMTP id s185mr22236900ybs.196.1631991425121; Sat, 18 Sep 2021 11:57:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631991425; cv=none; d=google.com; s=arc-20160816; b=Vf3ESuaKZM2/Qiqgm315A15kNsgbQ40UrmKmAQFOOeXOweurw85cYUtmlBsxlVcFS9 q5ntwh5bZZ4sN9z958kJ8/fCr3K269Bpd/jlGkXALtGsDM7i/BDEZFNcCUMVKK2gPRKY hAvwkHAsk4N0biR6sqZqP2EHYmUDf63646BST4fGdAThl2ZYdNrbBynA4pBR+Vv1zHl9 8UHsKbreypaD/6WvWut+91J5HM4wdhVl4jGwNtN5jn+QUk5hPJRoqxdR9QO6VJhAnuCN Rgbnb/AkuNQinS3N5+MuyYh2bR7SRPMc6yZbwLzH4FzRiegrN7dUL5b84IEkuO0pfvUW bXMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DnPKZsYD4ZUYg+zokoIL0aqocBtGju8WD3IhYIaHRac=; b=YBTa/0gdCfGLLWafX56n6g6O/u+ky7aOah6Eq4mTYwaBrV46lR7/YgWRDt0K6m5elF Jlwenwcb6Hlrvnw9wuOd1iadKBiB9O1D3VSpqVtysDPZueaNvGWBf4K5ooRyCwS2eoHj PipVzZzhEVBZHtYlTf4W3xXasuB+zARxfsJoiMNCS9lV1eqXEGAdsMREowjRenfJM/Ie UebZ1SEcOC0HO5ZzfTIndj79ClsGVwrQCAeCw9HY0V3XrGpfKgx8TpzHMYaBnNIvtKFB omdIDHi/QObM+DWt8RvzLquXxVF5ZoWbkw4adS05lXbXj6IwRPWcpgRAtIhi9gtKWSOM HBog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="yffMT/Zj"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 724175210b..2575e65860 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -84,10 +84,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, uintptr_t index; if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE_ORG : PAGE_READ))) { - /* SIGSEGV */ - arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access, - ptr_mmu_idx, false, ra); - g_assert_not_reached(); + raise_sigsegv(env_cpu(env), ptr, ptr_access, + !(flags & PAGE_VALID), ra); } /* Require both MAP_ANON and PROT_MTE for the page. */ From patchwork Sat Sep 18 18:45:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514235 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp671837jao; Sat, 18 Sep 2021 12:00:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwnN49lDit5V3QDm7V3uKI2YfF/iEMR0Dbgj7PAM2SF7YMqmS2IrWV5q8xND5SzuJLjux1r X-Received: by 2002:a05:6638:1352:: with SMTP id u18mr13815603jad.147.1631991611384; Sat, 18 Sep 2021 12:00:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631991611; cv=none; d=google.com; s=arc-20160816; b=SUOtHhJBqs6CU3+jGf46zr3MaNnhDzVR6kZPYRf6317Bh2KkTlgAoQMPfgDTQB/Kl+ JUuHBfo48wXQAtkNG8QX315fgwXv2bIZLdNsM49kbcRy0hUiq07VrZ3t6OHpn233GK5q 2fDUvyIycrSDrnlo6uu46pbQD+ad4W3+/uPFmzBijGOac/pEiHTadTPVJllO9crxdZG+ BRoeXCWKHoZ/gNoOvrTmn0oOPZ/+ZcUCBZNm+AK02dCzNiAkoK4Dpa4EoBzSMUvuoq01 fw9ASV+OQjCpyHaBtxFr1YsRKMVZ1vCfnXdjJX93PcGZ+cmAL8FZeDPwWRzXVFINvJwd 6stg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+ACTRx2M3S4z/05kxGieMFxgHgCHNXfLhyJ3AhpLuew=; b=m5sm3XK0SbLEDQTO64tqkMxoJ2sU3S/AlFwV1QT4FqXjVc84Y87FzJHdN4qywOU3tY 5BGFkKd84mlG+nq8msCBwqhRF0p0BSZ+9zZzQQizA8YaCQvgKQhNK8p4RH6Fn06YtAfI wYLUFzxMt/rkCNkMHs21LZFwrPVy3eZbUiUwcfdfiPK93F3sYi+32qjjCNEaYI0zVFOa RaWZcYpE1wBE5Tu67wtmFiG+OXJRSvNs5tMgyOQhycfWLij9XdNxU8MB+Q/4VrM14FrB QF4jRlfSzkz6rwYo96dHZxC5WIqvg9cPqgCSNXTzRK+vl5Jm+682WWBbS83JnRreJ/WF jDbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xCdM6xjQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This means we cannot remove the code within cpu_loop that decodes EXCP_DATA_ABORT and EXCP_PREFETCH_ABORT. But using the new hook means that we don't have to do the page_get_flags check manually, and we'll be able to restrict the tlb_fill hook to sysemu later. Signed-off-by: Richard Henderson --- target/arm/internals.h | 6 ++++++ target/arm/cpu.c | 6 ++++-- target/arm/cpu_tcg.c | 6 ++++-- target/arm/tlb_helper.c | 36 +++++++++++++++++++----------------- 4 files changed, 33 insertions(+), 21 deletions(-) -- 2.25.1 diff --git a/target/arm/internals.h b/target/arm/internals.h index cd2ea8a388..480145b382 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -544,9 +544,15 @@ static inline bool arm_extabort_type(MemTxResult result) return result != MEMTX_DECODE_ERROR; } +#ifdef CONFIG_USER_ONLY +void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e11aa625a5..4fc01768ab 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2016,10 +2016,12 @@ static const struct SysemuCPUOps arm_sysemu_ops = { static const struct TCGCPUOps arm_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, - .tlb_fill = arm_cpu_tlb_fill, .debug_excp_handler = arm_debug_excp_handler, -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv = arm_cpu_record_sigsegv, +#else + .tlb_fill = arm_cpu_tlb_fill, .has_work = arm_cpu_has_work, .cpu_exec_interrupt = arm_cpu_exec_interrupt, .do_interrupt = arm_cpu_do_interrupt, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0d5adccf1a..7b3bea2fbb 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -898,10 +898,12 @@ static void pxa270c5_initfn(Object *obj) static const struct TCGCPUOps arm_v7m_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, - .tlb_fill = arm_cpu_tlb_fill, .debug_excp_handler = arm_debug_excp_handler, -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv = arm_cpu_record_sigsegv, +#else + .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, .do_interrupt = arm_v7m_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 3107f9823e..dc5860180f 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -147,28 +147,12 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } -#endif /* !defined(CONFIG_USER_ONLY) */ - bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { ARMCPU *cpu = ARM_CPU(cs); ARMMMUFaultInfo fi = {}; - -#ifdef CONFIG_USER_ONLY - int flags = page_get_flags(useronly_clean_ptr(address)); - if (flags & PAGE_VALID) { - fi.type = ARMFault_Permission; - } else { - fi.type = ARMFault_Translation; - } - fi.level = 3; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); -#else hwaddr phys_addr; target_ulong page_size; int prot, ret; @@ -210,5 +194,23 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_restore_state(cs, retaddr, true); arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); } -#endif } +#else +void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra) +{ + ARMMMUFaultInfo fi = { + .type = maperr ? ARMFault_Translation : ARMFault_Permission, + .level = 3, + }; + ARMCPU *cpu = ARM_CPU(cs); + + /* + * We report both ESR and FAR to signal handlers. + * For now, it's easiest to deliver the fault normally. + */ + cpu_restore_state(cs, ra, true); + arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi); +} +#endif /* !defined(CONFIG_USER_ONLY) */ From patchwork Sat Sep 18 18:45:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514247 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp679429jao; Sat, 18 Sep 2021 12:12:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzM9ziNf+0rwrqnLkUxqu0vxsPQjXnD69WnoCDO9JihIMopJYpPnedSoNnM3ZvnZBe0pp/M X-Received: by 2002:a25:5956:: with SMTP id n83mr20315880ybb.109.1631992343613; Sat, 18 Sep 2021 12:12:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631992343; cv=none; d=google.com; s=arc-20160816; b=GRdqMwGq9XNBCfOW3PLbS/tsYwQ5Ne+A37n92SP3ijMSlDB0KnQ/K3+ZKE4M2AmPAF vp/aUtb84m7thcZX0DNizn3H6104yo9ZDgqBuYL8iHD1KUh8yPY9sjtRWNIvKU3pvQDq j1Laww/pvrWt8QZ883CzdWUJz9iwB6Jxbl5sQDNzC1ryaMdLadQIlBqyGhIhOzOQMJiv YI0q1gZj5uEnQYTHGfqaWd5x2Gz4ouZCJEUbEQDt3pQ2Qd5Rx5CNEIfmlJFYr+dztGto JqkB498rswwaNQxO2TQw6sf/PAKyxg+1bileTqjPhI2q3pzRR3z0ZfSMdG+7ybcQYW78 H3Fw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yhN8ow8bafB9lvcE0BZaSXFoylrPitNEFmmVqtlA/N4=; b=i4rmcft8x5hbC3LjTqE3aUje5f+07yUxLdmK5niRW74Y8HgwbJ0AMxygh3F3mUtbvT sKn036V544vPDa6v/yWDRk4oZXO4YWKnkg/nz8qkGvBd7wuiP+qiJJ6cRIWuFaIXgO1z Yzmk1nAg+8x/vnTJWpf/j6zhC2AnkN2+3zf7cgmvEScm2T6FUQV6uP5Cak5CytyDJ4QU AK6LTftxxYrSAnzFNVa1tuQtX3rOij7wJeMaaUrDZwJAMZaE3PGiOhMPgL23lTbozRsX uFXxNc3DFhSCM9KFOpCuGMU1+p7SDUAWbEQQUVj739C9UykxEbvl3SgliYCd1LfYoSPN HFJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=t28LFLBB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u14si11426360ybp.265.2021.09.18.12.12.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 12:12:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=t28LFLBB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46990 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfl9-0008JH-0R for patch@linaro.org; Sat, 18 Sep 2021 15:12:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54506) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLf-0005D0-Q2 for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:04 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:37439) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLS-0006ts-Vi for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:00 -0400 Received: by mail-pg1-x536.google.com with SMTP id 17so13098847pgp.4 for ; Sat, 18 Sep 2021 11:45:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yhN8ow8bafB9lvcE0BZaSXFoylrPitNEFmmVqtlA/N4=; b=t28LFLBBoCwttS/Xsn/H8Z9+uNlnEzbRSDN3S0d9ZoOOEEi2AmnrupLxJTTYpyeG2q Rd6fCBIqZkbl15zwrzgNsB/kcvG1ytYlp/lpS2jDdh1A3s9uaaaSS5v7BZBMQEbrMdAM 7rl4sGMtQOOimiryyJ7aHmsHBDE8xJGwaNn19S5xBeflat+k0pGu7mEN3H2dvJPfWWTl /8idErSCwZ3w5K/Zs3EucKPtlKMD55ipH89m8u7nkasTX4+iVAVtVNvzuqpKh11y7UAz BuNyzNzMC9+1zWM6TMrMrUJ4Z07LoqcUkmQ+zXotlIEeX/7og/uPaZiDke/uiCodTNwz LJkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yhN8ow8bafB9lvcE0BZaSXFoylrPitNEFmmVqtlA/N4=; b=K0kkcaNKQEvfOQjdpUFg0xvDn07B/lC51sYUBIhCFkSAAOKctYU/Pbq04RWiNaofOL nfF/KilqLi9bpGN1amIzMPqsrMa9DWYUcLpVOReRAc+vl83E1aJVo6xJ5O17E1HyXLc1 7fOjoEwhX/Eled9fdIcYH/Gqmm23kjt6hFM8CnkiveBIv7CKXNT9YvfFu9hd6vjsJ/oq yXaI6bVvmX3IHgdq64sNqlJt/25w+sTG9B6TpduX8O8SV53O6Xb+gSOrfpcLyPhuPd17 NKl6G3iWrC214QiTKO84MN1dH73Slp04T1BYcZ3RxTMw6jMheWIk1bjH7J27NIxvcRt9 TQeA== X-Gm-Message-State: AOAM531P/R26LXymrPgMk2+nT1WcEnSkgGrw60VUbeb80Bw68JASnY3a M1ZDOmsWQD/u05Zgpu/IKjdQergBc1nwUQ== X-Received: by 2002:a05:6a00:1481:b0:43d:275b:7ba4 with SMTP id v1-20020a056a00148100b0043d275b7ba4mr17032200pfu.63.1631990748685; Sat, 18 Sep 2021 11:45:48 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 24/41] target/cris: Make cris_cpu_tlb_fill sysemu only Date: Sat, 18 Sep 2021 11:45:10 -0700 Message-Id: <20210918184527.408540-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for cris-linux-user. Remove the code from cpu_loop that handled the unnamed 0xaa exception. This makes all of the code in helper.c sysemu only, so remove the ifdefs and move the file to cris_softmmu_ss. Signed-off-by: Richard Henderson --- target/cris/cpu.h | 8 ++++---- linux-user/cris/cpu_loop.c | 10 ---------- target/cris/cpu.c | 4 ++-- target/cris/helper.c | 18 ------------------ target/cris/meson.build | 7 +++++-- 5 files changed, 11 insertions(+), 36 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 6603565f83..b445b194ea 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -189,6 +189,10 @@ extern const VMStateDescription vmstate_cris_cpu; void cris_cpu_do_interrupt(CPUState *cpu); void crisv10_cpu_do_interrupt(CPUState *cpu); bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req); + +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #endif void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags); @@ -251,10 +255,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) return !!(env->pregs[PR_CCS] & U_FLAG); } -bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); - /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0 diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index 334edddd1e..0de941c0b4 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -35,16 +35,6 @@ void cpu_loop(CPUCRISState *env) process_queued_cpu_work(cs); switch (trapnr) { - case 0xaa: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->pregs[PR_EDA]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index b9f30ba58f..b8ac1b9f25 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -207,10 +207,10 @@ static const struct SysemuCPUOps cris_sysemu_ops = { static const struct TCGCPUOps crisv10_tcg_ops = { .initialize = cris_initialize_crisv10_tcg, - .tlb_fill = cris_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY .has_work = cris_cpu_has_work, + .tlb_fill = cris_cpu_tlb_fill, .cpu_exec_interrupt = cris_cpu_exec_interrupt, .do_interrupt = crisv10_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ @@ -218,9 +218,9 @@ static const struct TCGCPUOps crisv10_tcg_ops = { static const struct TCGCPUOps crisv32_tcg_ops = { .initialize = cris_initialize_tcg, - .tlb_fill = cris_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = cris_cpu_tlb_fill, .cpu_exec_interrupt = cris_cpu_exec_interrupt, .do_interrupt = cris_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/cris/helper.c b/target/cris/helper.c index 36926faf32..a0d6ecdcd3 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -39,22 +39,6 @@ #define D_LOG(...) do { } while (0) #endif -#if defined(CONFIG_USER_ONLY) - -bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - CRISCPU *cpu = CRIS_CPU(cs); - - cs->exception_index = 0xaa; - cpu->env.pregs[PR_EDA] = address; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - - static void cris_shift_ccs(CPUCRISState *env) { uint32_t ccs; @@ -304,5 +288,3 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return ret; } - -#endif /* !CONFIG_USER_ONLY */ diff --git a/target/cris/meson.build b/target/cris/meson.build index 67c3793c85..c1e326d950 100644 --- a/target/cris/meson.build +++ b/target/cris/meson.build @@ -2,13 +2,16 @@ cris_ss = ss.source_set() cris_ss.add(files( 'cpu.c', 'gdbstub.c', - 'helper.c', 'op_helper.c', 'translate.c', )) cris_softmmu_ss = ss.source_set() -cris_softmmu_ss.add(files('mmu.c', 'machine.c')) +cris_softmmu_ss.add(files( + 'helper.c', + 'machine.c', + 'mmu.c', +)) target_arch += {'cris': cris_ss} target_softmmu_arch += {'cris': cris_softmmu_ss} From patchwork Sat Sep 18 18:45:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514234 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp671811jao; 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Remove the code from cpu_loop that raises SIGSEGV. Signed-off-by: Richard Henderson --- linux-user/hexagon/cpu_loop.c | 24 +----------------------- target/hexagon/cpu.c | 23 ----------------------- 2 files changed, 1 insertion(+), 46 deletions(-) -- 2.25.1 diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index bc34f5d7c3..244917e27f 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -26,8 +26,7 @@ void cpu_loop(CPUHexagonState *env) { CPUState *cs = env_cpu(env); - int trapnr, signum, sigcode; - target_ulong sigaddr; + int trapnr; target_ulong syscallnum; target_ulong ret; @@ -37,10 +36,6 @@ void cpu_loop(CPUHexagonState *env) cpu_exec_end(cs); process_queued_cpu_work(cs); - signum = 0; - sigcode = 0; - sigaddr = 0; - switch (trapnr) { case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ @@ -63,12 +58,6 @@ void cpu_loop(CPUHexagonState *env) env->gpr[0] = ret; } break; - case HEX_EXCP_FETCH_NO_UPAGE: - case HEX_EXCP_PRIV_NO_UREAD: - case HEX_EXCP_PRIV_NO_UWRITE: - signum = TARGET_SIGSEGV; - sigcode = TARGET_SEGV_MAPERR; - break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); break; @@ -77,17 +66,6 @@ void cpu_loop(CPUHexagonState *env) trapnr); exit(EXIT_FAILURE); } - - if (signum) { - target_siginfo_t info = { - .si_signo = signum, - .si_errno = 0, - .si_code = sigcode, - ._sifields._sigfault._addr = sigaddr - }; - queue_signal(env, info.si_signo, QEMU_SI_KILL, &info); - } - process_pending_signals(env); } } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index aa01974807..96cd7db170 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -240,34 +240,11 @@ static void hexagon_cpu_init(Object *obj) qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property); } -static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ -#ifdef CONFIG_USER_ONLY - switch (access_type) { - case MMU_INST_FETCH: - cs->exception_index = HEX_EXCP_FETCH_NO_UPAGE; - break; - case MMU_DATA_LOAD: - cs->exception_index = HEX_EXCP_PRIV_NO_UREAD; - break; - case MMU_DATA_STORE: - cs->exception_index = HEX_EXCP_PRIV_NO_UWRITE; - break; - } - cpu_loop_exit_restore(cs, retaddr); -#else -#error System mode not implemented for Hexagon -#endif -} - #include "hw/core/tcg-cpu-ops.h" static const struct TCGCPUOps hexagon_tcg_ops = { .initialize = hexagon_translate_init, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, - .tlb_fill = hexagon_tlb_fill, }; static void hexagon_cpu_class_init(ObjectClass *c, void *data) From patchwork Sat Sep 18 18:45:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514250 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp681869jao; Sat, 18 Sep 2021 12:17:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxoiHB3W/DEp+kfSlHTV40eZgvQrgXXk5R17Qw9VPeefYvizHqslTX6u0NX0GBGJ3KW1SMl X-Received: by 2002:a02:7b01:: with SMTP id q1mr13749704jac.81.1631992634391; Sat, 18 Sep 2021 12:17:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631992634; cv=none; d=google.com; s=arc-20160816; b=xmXa8to6gF8nR1+qbB3xBulBcANCs4OtnxQyf0K57G3qhRFpC0FdFX8sUJ5frg9jfb bAtbp+DOcu4tTBxfwvwQlxFXrO9PtFO0yhOc/1VDaBtCJtvph9OsscG+NLLo4v0ZfEAJ E3i2vZ18IjGopxL4+r+nJyM16K1CA4CKv0FoJsv9yUnIm35OTzB/QuWe8kVbQK487rBf 4TIdpJPLWigpyBwgZwK15LeaS1WjqvOMncfMrd+QQhyJHSYda1A9pZsTB3LasYhVVLge E2Z3I7BqD9Mo08zY7ZOfJx4k5t1BbNV4nECd+y1Hc9XS2C3aN7m/eRNDsyB12LWZxggI uL9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZeJrnrGXbns19Ke8zIFiDiL715TP9FXdW45pYc4kaZA=; b=02I02WvOue1LWu7ClC1YQsM4BUgZ/B1LbOkLNX8XkuYL/ua5/gfChZY6Cs2Job/hfS B0n5el7twQOlAAS5IflNKT7WFMka1YwoP/QoYgsHqTyhqbuLMNjfRLx853UI9yPQpY0b vMtQvzvhUwMXcO203+FReuad2Wal/41hkV6SFgAb551ipaz8ieFDmudPdcemVNRmv+VR HQTF9xelyt5hXWxwalgd3RuWVJxec470dpLQJ3bhz6hOX65l60DiV30BKNW77Rwtq0T1 EvG3Z69AIo9OVgDjC10tAYLPxhU8PRA6G1i28LWm/DpxviwKBfM4WusuoYV2jtLsHJBi QqPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=evgczxDM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r4si1224217ilb.106.2021.09.18.12.17.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 12:17:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=evgczxDM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60638 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfpp-0000e9-RD for patch@linaro.org; Sat, 18 Sep 2021 15:17:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54546) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLj-0005Ec-3r for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:08 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:56302) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLV-0006vh-Et for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:06 -0400 Received: by mail-pj1-x102a.google.com with SMTP id t20so9164991pju.5 for ; Sat, 18 Sep 2021 11:45:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZeJrnrGXbns19Ke8zIFiDiL715TP9FXdW45pYc4kaZA=; b=evgczxDMW6NoVmZJV9OG47gOO74RerBksVVmt67+5F78SCqFd8/NJpgPI6BuRv5ZQY eEW3/7AQuOFXsuKDGwLV7S48qmEmBLPXei3PWnq1XvEzuStvE0fs3fiU7GJwzOGUjmes smApN+o+qE+PVrDRInYhG/eUg1SKUNdkp7NhtD3r+Yg/QwsPb3KLKVwX4PR8xRYf1S4B DF3XO/30nBHrK87XTJD55w3GbKiEIeNUHDN/BQnccRfCP1H0abzplO2jYwrYUlMR/XwU 12jV/ihzpNCLMxQ9nm6dbf5XJujRxShnqXrVjGINHphpj1oHhdWOIAC16tja3jCAliJD SfOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZeJrnrGXbns19Ke8zIFiDiL715TP9FXdW45pYc4kaZA=; b=EJsbaBWb7Cyxk1dfGuynAUrf//3jFuCSkq2jbVH2YRAJA5k59LX4gM/fkNuBLFMere pJpeo67S0nIR3t8XcmfSc0ockojkD2YlK65RWjLd83T+i9eihm4L0IqF570wMAnii6z7 0HbLNi03Gjy9oTWuOG4NA4wuWEwyo9MT7S9BZDZY3US8+KX4Tm5gFdA76NVPSjE9usAs rTn6mC+sDxpqhZkWV6GQfIeuHETeIF+p1zRmZY0148JgwxucnJ44wYQMFV1OBhBhg8QI dVeJVTNsjAkqanLDG2AUV07QVPNvcBOJnCcBuTQg6QKnuNxSh1vEOB3+uET6tuCZB0Nd l9hQ== X-Gm-Message-State: AOAM530GV8+3h4XIiapaIir3Mmy54nGMQpc7hWYr3ywT5HfHQfXBEcff 3tlEsCFKZDBLJ+vy6dNp9SRrdLaI8omCIw== X-Received: by 2002:a17:903:31c2:b0:13c:9de8:d314 with SMTP id v2-20020a17090331c200b0013c9de8d314mr15212452ple.1.1631990750138; Sat, 18 Sep 2021 11:45:50 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 26/41] target/hppa: Make hppa_cpu_tlb_fill sysemu only Date: Sat, 18 Sep 2021 11:45:12 -0700 Message-Id: <20210918184527.408540-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for hppa-linux-user. Remove the code from cpu_loop that raised SIGSEGV. This makes all of the code in mem_helper.c sysemu only, so remove the ifdefs and move the file to hppa_softmmu_ss. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 +- linux-user/hppa/cpu_loop.c | 16 ---------------- target/hppa/cpu.c | 2 +- target/hppa/mem_helper.c | 15 --------------- target/hppa/meson.build | 6 ++++-- 5 files changed, 6 insertions(+), 35 deletions(-) -- 2.25.1 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index d3cb7a279f..294fd7297f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -323,10 +323,10 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); +#ifndef CONFIG_USER_ONLY bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -#ifndef CONFIG_USER_ONLY void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 82d8183821..a6122b3594 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -142,22 +142,6 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f = env->gr[31]; env->iaoq_b = env->gr[31] + 4; break; - case EXCP_ITLB_MISS: - case EXCP_DTLB_MISS: - case EXCP_NA_ITLB_MISS: - case EXCP_NA_DTLB_MISS: - case EXCP_IMP: - case EXCP_DMP: - case EXCP_DMB: - case EXCP_PAGE_REF: - case EXCP_DMAR: - case EXCP_DMPI: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr = env->cr[CR_IOR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_UNALIGN: info.si_signo = TARGET_SIGBUS; info.si_errno = 0; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index be940ae224..9b92e82af7 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -146,10 +146,10 @@ static const struct SysemuCPUOps hppa_sysemu_ops = { static const struct TCGCPUOps hppa_tcg_ops = { .initialize = hppa_translate_init, .synchronize_from_tb = hppa_cpu_synchronize_from_tb, - .tlb_fill = hppa_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY .has_work = hppa_cpu_has_work, + .tlb_fill = hppa_cpu_tlb_fill, .cpu_exec_interrupt = hppa_cpu_exec_interrupt, .do_interrupt = hppa_cpu_do_interrupt, .do_unaligned_access = hppa_cpu_do_unaligned_access, diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index afc5b56c3e..bf07445cd1 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -24,20 +24,6 @@ #include "hw/core/cpu.h" #include "trace.h" -#ifdef CONFIG_USER_ONLY -bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - HPPACPU *cpu = HPPA_CPU(cs); - - /* ??? Test between data page fault and data memory protection trap, - which would affect si_code. */ - cs->exception_index = EXCP_DMP; - cpu->env.cr[CR_IOR] = address; - cpu_loop_exit_restore(cs, retaddr); -} -#else static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) { int i; @@ -392,4 +378,3 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr) hppa_tlb_entry *ent = hppa_find_tlb(env, vaddr); return ent ? ent->ar_type : -1; } -#endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/meson.build b/target/hppa/meson.build index 8a7ff82efc..021e42a2d0 100644 --- a/target/hppa/meson.build +++ b/target/hppa/meson.build @@ -7,13 +7,15 @@ hppa_ss.add(files( 'gdbstub.c', 'helper.c', 'int_helper.c', - 'mem_helper.c', 'op_helper.c', 'translate.c', )) hppa_softmmu_ss = ss.source_set() -hppa_softmmu_ss.add(files('machine.c')) +hppa_softmmu_ss.add(files( + 'machine.c', + 'mem_helper.c', +)) target_arch += {'hppa': hppa_ss} target_softmmu_arch += {'hppa': hppa_softmmu_ss} From patchwork Sat Sep 18 18:45:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514241 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp676133jao; Sat, 18 Sep 2021 12:06:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxwj3SnB0GvstmBkyCOQywMO2ryo7k7G0s89T70dM4uhHyCJMHwyjfGLjQZprtpngsUdIJy X-Received: by 2002:a05:6638:1613:: with SMTP id x19mr13738156jas.77.1631992018046; Sat, 18 Sep 2021 12:06:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631992018; cv=none; d=google.com; s=arc-20160816; b=Cjh6EsFeRbJO2KCjTAVIEs0dp0Tgjh2U8yFbU5OyJJd8Ksm5QNZWVtk/e0lk7u8VJ7 /pUGM4yBHKznsniEibguEDRB2ZKnmXJxiHZkv6g4Bx6S0WYkZJmdiNs02Q9egcgKvm2R s66bbgt/89t3X/LatZ991vYs8yPMupMCAVeBS6v7zwfxq0VsFlefXX9VaPd4+++JWqFa yAux/i49NAmuGDXX7O3ZGYUjRAymcYf2YCv8+N/0JuDjRKuvbYxpM03rAsPH1W/8Y1yW BoZa7MMMH7tck8+vTfhRKy/Xo6hz0jwFhaBJGPdLZbm6YHkXE4/mc5UvFMJHZPZocD98 gSOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=K0fQfQv3eI9fj5VVYuJMrdPgUOCZpzNCV/amqlAI9NY=; b=h+S7CfeaWKZwhbty1rWiA4m/pMtAyNi/s1vDlG3CxR6y9t7z5ZpGcbC2Ls7oyEy5E8 pFuaIloiJJ55nTEKE417Uu8InZpwozv70tSro0dZ3EZsBbxNO7shwa10HogJcR1xo7bY AjLYC9PV+S05Lqk2XTmvN92OEP78lfjRB31aK8Gd2SlLjnQa1XsPXzoYSKPhUTd+RP+0 gcILs3vSQCiWLoL+IIOvdRizYPDaEp/weAwjt20Aj1BOKzhbZkcFb8tJao4yOx3jb91L Lafo9IL3QTiONbq7Fzk5ofXGWAwgDInJiOo1z062oYZTo0SHiHHxYI4AaLxIAKoZ88E4 GOAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="TNP/i4Dy"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c184si9978332iof.111.2021.09.18.12.06.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 12:06:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="TNP/i4Dy"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59170 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfft-00061L-Er for patch@linaro.org; Sat, 18 Sep 2021 15:06:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54628) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLm-0005Jr-TC for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:10 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:52167) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLb-0006vo-3l for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:10 -0400 Received: by mail-pj1-x1030.google.com with SMTP id dw14so9179892pjb.1 for ; Sat, 18 Sep 2021 11:45:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=K0fQfQv3eI9fj5VVYuJMrdPgUOCZpzNCV/amqlAI9NY=; b=TNP/i4DymDyMMlS/4Zyqpp0V5kP+7O7ZgtbEH2vMsgIoZRqRWb5ahcqE+ae+KRFDxS 4YIMOdKBliEuXx60c4aTanWoTw+blhcHhCSX1PwR5SSvbWyRZC6W7YODXMB4Ff65Ik2x AZfVO7V6VKhMXSIM/ApTJOpSzrKU8JLTB3jW3QXwOGhoaN/rdy9zYlYuJOPxG2Ql6ZJn 8USTbO0REzYu5JSeRLQTb6TPKkedu3BbTNv7XLNFN6961TW5/sN7ZPgjkTbN/JJu1/Qk oT6NTL3SmpZUqTL651qmZxRohhOq9Pdz11CWQEiC/d1FEi7E2UjnUuObwnPNyounVX87 m+AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K0fQfQv3eI9fj5VVYuJMrdPgUOCZpzNCV/amqlAI9NY=; b=0SQnb2hYwBqa7HX/yjrKmfg5g7CIuh41y9waFid754XHAqNw7KVOqpaCdXgyXC25DF BPUmVlTEJ9rrz+gz19DcucrDYO6Tqpa3Z2WgzzIejaB2f+YGKPipCoYLXAc27Jby6rFQ WDgKWyPKbGBX99YiWd3tXwKn45QB+kDszjZPwuA0HwHIHJnBLCzI8IEy7oYF/fZlWPw0 0Xz5BoY3cRZA4DEms74UyEoPHlRaOFaZvX7mftWqcW0qXsuxF5vQ6NbUZuJmN1HrIsTx bGGRTHgfvGtLX3I8g+8HTQqw7YnhlnpbAxBdTm06gnHzCRCxKuVXPvDZpPppvw9fdkMf Atkw== X-Gm-Message-State: AOAM533JxIhfoUNu3AkGE1d/08qRDKFnZoEOn/X9v01NlUsghjpaQ3er I7kT4NIydHBpQ70JJ5M+TNm3BkFTvD41Ow== X-Received: by 2002:a17:90b:1c92:: with SMTP id oo18mr28669688pjb.56.1631990751022; Sat, 18 Sep 2021 11:45:51 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 27/41] target/i386: Implement x86_cpu_record_sigsegv Date: Sat, 18 Sep 2021 11:45:13 -0700 Message-Id: <20210918184527.408540-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Record cr2, error_code, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. Use the maperr parameter to properly set PG_ERROR_P_MASK. Signed-off-by: Richard Henderson --- target/i386/tcg/helper-tcg.h | 6 ++++++ target/i386/tcg/tcg-cpu.c | 3 ++- target/i386/tcg/user/excp_helper.c | 23 +++++++++++++++++------ 3 files changed, 25 insertions(+), 7 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 60ca09e95e..0a4401e917 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -43,9 +43,15 @@ bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); #endif /* helper.c */ +#ifdef CONFIG_USER_ONLY +void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#endif void breakpoint_handler(CPUState *cs); diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index aef050d089..3fab3676b1 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -77,11 +77,12 @@ static const struct TCGCPUOps x86_tcg_ops = { .synchronize_from_tb = x86_cpu_synchronize_from_tb, .cpu_exec_enter = x86_cpu_exec_enter, .cpu_exec_exit = x86_cpu_exec_exit, - .tlb_fill = x86_cpu_tlb_fill, #ifdef CONFIG_USER_ONLY .fake_user_interrupt = x86_cpu_do_interrupt, + .record_sigsegv = x86_cpu_record_sigsegv, #else .has_work = x86_cpu_has_work, + .tlb_fill = x86_cpu_tlb_fill, .do_interrupt = x86_cpu_do_interrupt, .cpu_exec_interrupt = x86_cpu_exec_interrupt, .debug_excp_handler = breakpoint_handler, diff --git a/target/i386/tcg/user/excp_helper.c b/target/i386/tcg/user/excp_helper.c index a89b5228fd..cd507e2a1b 100644 --- a/target/i386/tcg/user/excp_helper.c +++ b/target/i386/tcg/user/excp_helper.c @@ -22,18 +22,29 @@ #include "exec/exec-all.h" #include "tcg/helper-tcg.h" -bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra) { X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; + /* + * The error_code that hw reports as part of the exception frame + * is copied to linux sigcontext.err. The exception_index is + * copied to linux sigcontext.trapno. Short of inventing a new + * place to store the trapno, we cannot let our caller raise the + * signal and set exception_index to EXCP_INTERRUPT. + */ env->cr[2] = addr; - env->error_code = (access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT; - env->error_code |= PG_ERROR_U_MASK; + env->error_code = ((access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT) + | (maperr ? 0 : PG_ERROR_P_MASK) + | PG_ERROR_U_MASK; cs->exception_index = EXCP0E_PAGE; + + /* Disable do_interrupt_user. */ env->exception_is_int = 0; env->exception_next_eip = -1; - cpu_loop_exit_restore(cs, retaddr); + + cpu_loop_exit_restore(cs, ra); } From patchwork Sat Sep 18 18:45:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514253 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp684296jao; Sat, 18 Sep 2021 12:21:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw431d2UusV+j8Ouhh+JkhcRA7SedaJ1jEvrcA/8cHGmYm3f35wAwIIKeU6i2HrfGedpJMp X-Received: by 2002:a25:428c:: with SMTP id p134mr21404371yba.60.1631992886379; Sat, 18 Sep 2021 12:21:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631992886; cv=none; d=google.com; s=arc-20160816; b=a/hxhavd9Ni0Ye7eXBk9Ivjm4PydMunOzhlna6qFdiqPR+U2wtyxCfoTBu0xiHucW8 uEWIMGYPGiS3Urhs/OCI8IyndG5QUAdpJZ0zrgkPvr4FngG3R7kw/vhIMz2y802XE6sJ nLFylO843ybXLOkJ4fO638ibLQ2v9b0rTK7waVIiOOR8ZnNKD202HlLCLXfFOMW9RZng Gwe39k5xknC9+EvyRGxN0qPJn6vCgO7QjOoY+PP3uaYYxWcY6ZfT5CARxAHn2u6hBYor P/Wl5Ws5Cm88Z1lbGY1ut4lFxgANi23rMo2r4bqkOdgBTIfWRJcT208BrhCGhUCUsYTz 9NVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=J7hXQMffuuyXWpRCyuYJCpC7YHlZqNroGTBaJ0dICLY=; b=Dt4WhngshH5D9bzWydNYpIPI+FfGnVzLdpoG0yV6IpvcIkf92bXPsvugiFBucNhI3K VlcjBKV/cvAybhugC642CJAfG2OBeT8UvsCMRKov/g/jxtMzf3tS0okNP1V8ZtSShEp/ 43dMQu5AKv6Q9DzQvXHqiLfaYVS3xvY0YBCbjdFCJyoruJuTL4oG4YaxXRs5JJofYLFS YkPh3D5/ZcPwPIieZ0Tj9CzZgEUIhNzaViMpoqjR6qhfr2DIqt9nTavmfS48pcltZTWB OSigycHEjddlxM7qUF78kaJxInS8IxeAqe3DQJP3cxiDqeslUV/jBKzbqAR4mlcBsO7G +geg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HmaQDaZ6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j4si9286353ybo.68.2021.09.18.12.21.26 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 12:21:26 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HmaQDaZ6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41216 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRftt-0006pg-Rl for patch@linaro.org; Sat, 18 Sep 2021 15:21:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54584) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLl-0005Go-GD for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:09 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:35388) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLW-0006wT-6h for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:09 -0400 Received: by mail-pl1-x630.google.com with SMTP id bb10so8391305plb.2 for ; Sat, 18 Sep 2021 11:45:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J7hXQMffuuyXWpRCyuYJCpC7YHlZqNroGTBaJ0dICLY=; b=HmaQDaZ6OpxXZdCaSbmOznChge+x9N6Xx4Q/cATmhLf92uiWRSMFIshPAK3oYfVpsJ 7froXKEsUXT9bPzbXW+GgSGNvWZsT952zmVytnRDYDj7roxKGZLjUUysiztrxdN4/MNW /J4sroFSVX7kqfEXfilTbR1Y0vaes7ouYvNtmGucusrjDdSnexZrazew60xEXvYydbUG Uq9cC3w+UFC3hu88L9YVNs3tYuiuluqUY+FhSyB2/t/99WkDuzet6ozl+R/1kwWhD4t3 MdeTmqW5znUkW/7tAmgm5DIF5rNEbgXT0Vu10+rlN/iT5n6ZvlxOkgvE0PQtCFdzQ5jX scyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J7hXQMffuuyXWpRCyuYJCpC7YHlZqNroGTBaJ0dICLY=; b=ohGms0BuY043sIapSLsuk7QEVern/lqsYRT4fsMjIR7s5KzqiZIFjAmWPq4Hh/mtET kvyd9jALiu7kPcnMf2K+uaqCORd02+VYl9gUTYhgYHt9xc/I0vWJUJEuxGwyeXz550on 4IexkMqMH2qN1GwJ4P4kDD0+gUEZ/++VGE0qz1M0CHwTYJg88hUuWPsNlr4JhOVc6UKR TfTUR7W0NX4Kuuo426REPPkyYrKBDIwRDiyb2Mc+IDwyQ6hjm96fZDKKRouEg9z3IYIl CD+ThcAH8hOVt2igDxNmCY8wdZG+LQ/Es7IdNP9RiEojqZ7/+RYmZXU+i6/+3lXTVuPV IR8A== X-Gm-Message-State: AOAM533IPe7mQJOHWQHQ3FjrBRhHXNgtXAHi3IeBgsPEfSs1vK95MAPc 2nLxQjiGk9VUAjSUol3ZT0t8Hay5HEXd9w== X-Received: by 2002:a17:90b:3e84:: with SMTP id rj4mr14300361pjb.208.1631990751974; Sat, 18 Sep 2021 11:45:51 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 28/41] target/m68k: Make m68k_cpu_tlb_fill sysemu only Date: Sat, 18 Sep 2021 11:45:14 -0700 Message-Id: <20210918184527.408540-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for m68k-linux-user. Remove the code from cpu_loop that handled EXCP_ACCESS. Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 10 ---------- target/m68k/cpu.c | 2 +- target/m68k/helper.c | 6 +----- 3 files changed, 2 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index c7a500b58c..7d106aa86e 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -88,16 +88,6 @@ void cpu_loop(CPUM68KState *env) case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; - case EXCP_ACCESS: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->mmu.ar; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_DEBUG: info.si_signo = TARGET_SIGTRAP; info.si_errno = 0; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index ad5d26b5c9..94b7fc90e8 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -517,10 +517,10 @@ static const struct SysemuCPUOps m68k_sysemu_ops = { static const struct TCGCPUOps m68k_tcg_ops = { .initialize = m68k_tcg_init, - .tlb_fill = m68k_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY .has_work = m68k_cpu_has_work, + .tlb_fill = m68k_cpu_tlb_fill, .cpu_exec_interrupt = m68k_cpu_exec_interrupt, .do_interrupt = m68k_cpu_do_interrupt, .do_transaction_failed = m68k_cpu_transaction_failed, diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 137a3e1a3d..5728e48585 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -978,16 +978,12 @@ void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector) } } -#endif - bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType qemu_access_type, int mmu_idx, bool probe, uintptr_t retaddr) { M68kCPU *cpu = M68K_CPU(cs); CPUM68KState *env = &cpu->env; - -#ifndef CONFIG_USER_ONLY hwaddr physical; int prot; int access_type; @@ -1051,12 +1047,12 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (!(access_type & ACCESS_STORE)) { env->mmu.ssw |= M68K_RW_040; } -#endif cs->exception_index = EXCP_ACCESS; env->mmu.ar = address; cpu_loop_exit_restore(cs, retaddr); } +#endif /* !CONFIG_USER_ONLY */ uint32_t HELPER(bitrev)(uint32_t x) { From patchwork Sat Sep 18 18:45:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514252 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp683205jao; Sat, 18 Sep 2021 12:19:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwDU4+SQdPs47GITjd7OFCKfoHAodMWYodnBrNqRlgFp69MW8oAExn7aTCpODjoeOJM8d3z X-Received: by 2002:a92:8702:: with SMTP id m2mr11966185ild.250.1631992774653; Sat, 18 Sep 2021 12:19:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631992774; cv=none; d=google.com; s=arc-20160816; b=v2XI2uFgBYKOJ8gEfS58oBew636/PojMi60E6Y7ixCvM35ZAcGM5ghGDBw3yAG3d2D 8EAAi7gNWyMks1gNzspppFk5mSmW/hcHB8WpnPeAhFO7L9C4IrZ/p+cFRcftlFWak2jP sYMqhZJ4ohRdUsUp2C3+J8WsEw9Uc0ZjP/NMp9dJgouTaY1yxHtD3It2U9gVQ5ExreW8 W6xLX3Opu/BJhm1/DNJVmLilNS7OhAJKxaPFdNAfu9jPm6BhD93mG37s3ppMUeP5Kmji hbEXW6mgM57lErmphGQOdeyqHGnP4rVren3pPe/agKPuO3u3VK8OKmE9lCU3tBp1HgZW Welw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vy3PmhKz8vrPuLguGAuScpJF3WUMXPHzvRxSKLuEp08=; b=t0qafazNAB+3HFZNWQJnG6aSebpX9NwyIziBbAg5RORXRJysDwWKjB/JHi0njyeExa u/KrGXpUlV9buiw4rwuJPw9XHKT1UYcGQ591U2h1rPvX85oBcGWlEBo6lhxz8PD0kEnw t3sUCPlxjpoj11PKI0xUUTQnUUQhOAIEw+OiVspw7JxOd9HJbVryeTs3ALiC7/YM5+ZF 6WHnpTCBjLzypzrpohT3GbqAOqe465/Rb/hu96v7Dnh67zYeLPIiOgXuRiIpfTu7w39n yMPDrXOxdfxCJemDJwZ4RxFEaoBH5sfCFVFpJDuRlIsaIl62Dn4avhE2Ex9l4WjckGy4 6rHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Z//66kk5"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Remove the code from cpu_loop that handled the unnamed 0xaa exception. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 8 ++++---- linux-user/microblaze/cpu_loop.c | 10 ---------- target/microblaze/cpu.c | 2 +- target/microblaze/helper.c | 13 +------------ 4 files changed, 6 insertions(+), 27 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 13ed3cd4dd..2f3075d902 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -394,10 +394,6 @@ void mb_tcg_init(void); #define MMU_USER_IDX 2 /* See NB_MMU_MODES further up the file. */ -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); - typedef CPUMBState CPUArchState; typedef MicroBlazeCPU ArchCPU; @@ -415,6 +411,10 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, } #if !defined(CONFIG_USER_ONLY) +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index c3396a6e09..0b889a04a7 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -35,16 +35,6 @@ void cpu_loop(CPUMBState *env) process_queued_cpu_work(cs); switch (trapnr) { - case 0xaa: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = 0; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 36e6e54048..67a3b80512 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -366,10 +366,10 @@ static const struct SysemuCPUOps mb_sysemu_ops = { static const struct TCGCPUOps mb_tcg_ops = { .initialize = mb_tcg_init, .synchronize_from_tb = mb_cpu_synchronize_from_tb, - .tlb_fill = mb_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY .has_work = mb_cpu_has_work, + .tlb_fill = mb_cpu_tlb_fill, .cpu_exec_interrupt = mb_cpu_exec_interrupt, .do_interrupt = mb_cpu_do_interrupt, .do_transaction_failed = mb_cpu_transaction_failed, diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index dd2aecd1d5..a607fe68e5 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -24,18 +24,7 @@ #include "qemu/host-utils.h" #include "exec/log.h" -#if defined(CONFIG_USER_ONLY) - -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - cs->exception_index = 0xaa; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - +#ifndef CONFIG_USER_ONLY static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu, MMUAccessType access_type) { From patchwork Sat Sep 18 18:45:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514248 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp679953jao; Sat, 18 Sep 2021 12:13:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwHQ2xR1UCCbEoevME35HpSq2u++m00z7z4ns802hLNOoOxcxRSx6MHoMDGpsdwRsEiRYG0 X-Received: by 2002:a25:ad1f:: with SMTP id y31mr20303835ybi.437.1631992411591; Sat, 18 Sep 2021 12:13:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631992411; cv=none; d=google.com; s=arc-20160816; b=bYu37/RWzYdmJnbEYaO/WOE56fUTePKvBV1XOR+BkpsMvvQ+o/LBNvsd989nFpi4/Y 9SvDBCK5TSJmgeCA0aK2qoDj8tdWQVscaTqUIIfxYYJhPewsOSm/oPR2L7crnIUGzEAX SrFd5bNu3UthaRNr9oWSr4LMIjyf24tdxeDYqVX8121cTq+sdz+AZ9rG/NnC9vFnfZDF yPXch4psm3G2ra37WS+Oxb9QaFsrOKrGoDKHU4+2nijINEQZFWBGqkooOGH94fNP+n/U 4HWjljPtPwB3nUqdIVE9RHs/QjB8xbJebAcCR23IH2aKaxPbAJdj4JsmcuW5lT8WjBhu 9/NQ== ARC-Message-Signature: i=1; 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This means we can remove tcg/user/tlb_helper.c entirely. Remove the code from cpu_loop that raised SIGSEGV. Signed-off-by: Richard Henderson --- target/mips/tcg/tcg-internal.h | 7 ++-- linux-user/mips/cpu_loop.c | 11 ------ target/mips/cpu.c | 2 +- target/mips/tcg/user/tlb_helper.c | 59 ------------------------------- target/mips/tcg/meson.build | 3 -- target/mips/tcg/user/meson.build | 3 -- 6 files changed, 5 insertions(+), 80 deletions(-) delete mode 100644 target/mips/tcg/user/tlb_helper.c delete mode 100644 target/mips/tcg/user/meson.build -- 2.25.1 diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index c7a77ddccd..8ba36a8ef8 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -18,9 +18,6 @@ void mips_tcg_init(void); void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); @@ -60,6 +57,10 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, MemTxResult response, uintptr_t retaddr); void cpu_mips_tlb_flush(CPUMIPSState *env); +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + #endif /* !CONFIG_USER_ONLY */ #endif diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 9d813ece4e..40825ca566 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -156,17 +156,6 @@ done_syscall: } env->active_tc.gpr[2] = ret; break; - case EXCP_TLBL: - case EXCP_TLBS: - case EXCP_AdEL: - case EXCP_AdES: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->CP0_BadVAddr; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_CpU: case EXCP_RI: info.si_signo = TARGET_SIGILL; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 3639c03f8e..439b2f1635 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -541,10 +541,10 @@ static const struct SysemuCPUOps mips_sysemu_ops = { static const struct TCGCPUOps mips_tcg_ops = { .initialize = mips_tcg_init, .synchronize_from_tb = mips_cpu_synchronize_from_tb, - .tlb_fill = mips_cpu_tlb_fill, #if !defined(CONFIG_USER_ONLY) .has_work = mips_cpu_has_work, + .tlb_fill = mips_cpu_tlb_fill, .cpu_exec_interrupt = mips_cpu_exec_interrupt, .do_interrupt = mips_cpu_do_interrupt, .do_transaction_failed = mips_cpu_do_transaction_failed, diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_helper.c deleted file mode 100644 index 210c6d529e..0000000000 --- a/target/mips/tcg/user/tlb_helper.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * MIPS TLB (Translation lookaside buffer) helpers. - * - * Copyright (c) 2004-2005 Jocelyn Mayer - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ -#include "qemu/osdep.h" - -#include "cpu.h" -#include "exec/exec-all.h" -#include "internal.h" - -static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type) -{ - CPUState *cs = env_cpu(env); - - env->error_code = 0; - if (access_type == MMU_INST_FETCH) { - env->error_code |= EXCP_INST_NOTAVAIL; - } - - /* Reference to kernel address from user mode or supervisor mode */ - /* Reference to supervisor address from user mode */ - if (access_type == MMU_DATA_STORE) { - cs->exception_index = EXCP_AdES; - } else { - cs->exception_index = EXCP_AdEL; - } - - /* Raise exception */ - if (!(env->hflags & MIPS_HFLAG_DM)) { - env->CP0_BadVAddr = address; - } -} - -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - - /* data access */ - raise_mmu_exception(env, address, access_type); - do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr); -} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 8f6f7508b6..98003779ae 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -28,9 +28,6 @@ mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'mxu_translate.c', )) -if have_user - subdir('user') -endif if have_system subdir('sysemu') endif diff --git a/target/mips/tcg/user/meson.build b/target/mips/tcg/user/meson.build deleted file mode 100644 index 79badcd321..0000000000 --- a/target/mips/tcg/user/meson.build +++ /dev/null @@ -1,3 +0,0 @@ -mips_user_ss.add(files( - 'tlb_helper.c', -)) From patchwork Sat Sep 18 18:45:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514246 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp677273jao; Sat, 18 Sep 2021 12:08:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJya6Ld7rhH4j/xepYzxwWh89jzWZiK8I/J/i0Tq7jGyCW49WfbHt2oDkMvxBgTpSNDjxeP8 X-Received: by 2002:a92:cdad:: with SMTP id g13mr1429137ild.149.1631992137258; Sat, 18 Sep 2021 12:08:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631992137; cv=none; d=google.com; s=arc-20160816; b=A2NWZUIsbko+3VH4Q/dOTKjhYig6LR76j7kGv0T+6ytuAeBAOvpTYY9f5g9xHRHwU+ MWm2Ete96KHp1/LOiPF7bsUQSfS6JOFlxOW3Tr7IBMaFa/Ug58HpxPW/sc5ygiNCQsK+ tSOVNIncKMSfDpxrAvj4A9qpnp49rTTVBjw0Hci3ruJJI8uqc0CfYHnxBMscj2A9ioXG TheIUNXAL8qoVeH99J/vIj/079Rq6HmyTUMZsdjKht5WQ4fvjI4nIWBu6QW2fh0YJ+Xd G5JA3job7Ke2vFwcR9Cdu/fRgKxmpp9btbvZIbT2RF8OfWOGtPVq0gmc1/zq4snbsqLS 9j0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Hpn06mvL6ETEhh8XWYQF5SUad5wpeFGzI3BM48espBU=; b=yFrPiyFB2UkHoVEYHD73HLQ1ysHzu1vXyWBCHbc0uHA+6Jj9OenrWXupbVr0IXibgE j56IdMnK6TRVgemn0Hdkx95d0cd5WmSXdipccHYmGqsVMJYQiFkvQns0ZCk7lWAPlKrl U+JLFPkhtXjyftMr2rMOcXid5MZjtlqLAa51P8ZnXObG//SqHjpZ3Psh7wxqOhuPZGaa U6IvRAUThEiJGh5kE36IFmSFP/JUC/nUTNrEbynQM52jyaY69guPtLjIYyo7WexCnzru Dc5AT3N3Xkd/AUnN+yRf2wMYrB4QjqvporVvRebzUYFz+/4ZNbNBsz1jN8ftzqJAqwC9 beDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ln0D7kH7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n2si11256065jaj.42.2021.09.18.12.08.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 12:08:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ln0D7kH7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39782 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfho-0003XC-Ph for patch@linaro.org; Sat, 18 Sep 2021 15:08:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54662) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLp-0005O5-63 for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:16 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:46857) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLb-0006wq-5V for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:12 -0400 Received: by mail-pl1-x632.google.com with SMTP id bg1so8343715plb.13 for ; Sat, 18 Sep 2021 11:45:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Hpn06mvL6ETEhh8XWYQF5SUad5wpeFGzI3BM48espBU=; b=Ln0D7kH7ZPEIRygcBy0ufx233wWlLEFZYKaNcSGT21GIaUc8JLD7D3FR8tj+jkmVoF qReb+fWeDR4jpnGRbRZ1IsWLnPyJxGgNUj5EVBO1HTmeph0IER+VzG1OnOE5SaH8aqPc S4vJbYU1tgYFQ8ummN6ZchCxYrEq8iPVMqt2NhLVAPmxs71gEKtLHaQce8TtQFgpt0QJ xeepViE2yL6aB/wM4079mM2tRft2Ie/IZSTSIPUFU74aZq6mhbLHatbqYyYmjR51n90a Ni5OJzSRw0WGQ2XM2UMqfU2tkXAGie/RMdE7QC7Y38Mi0Bn43a/I8ip6JscbB7niYcNL +qrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Hpn06mvL6ETEhh8XWYQF5SUad5wpeFGzI3BM48espBU=; b=kVVXcjJ3P1nggdmynwRuCt3SwDO4rVQGpbeFdngsoS3BQMcECqnCu/X2rn76/7oFFu ZmsdIHzoMLQemGWn5Ll0vI150R+QKfwZ6q4l9+tqTXdbhWUuKuJ8/2EvKDVAWtXTTj3g HBDMezfN4eSgTyUBk9pcX6sfYrlKBH7HJvOVHsAqhupubTWE4VHwtS0/RLkWnbBSUPDa kEuA0riW6tp3j1Z/OxJsZgBGiofhWSDN4NwbBkfZgJ3RXyyvse53jY17aTh2KLWiNlx6 E3sTfcezCk1C+j3aBkHhFdH4sPujS8ayETgT2yw5UGnG8/evxwwHcYH0n0V8MVVVOgVV Lrng== X-Gm-Message-State: AOAM531sCcmvGEYFbB52X9NSxtjkkQa+wPrXO1W0jtXxIP47UPpu/Yy3 k/3K2tkNahX84XPfGE4oQ1XYcxws1WwFiw== X-Received: by 2002:a17:902:9a04:b0:13a:1ae3:add2 with SMTP id v4-20020a1709029a0400b0013a1ae3add2mr15222515plp.28.1631990754444; Sat, 18 Sep 2021 11:45:54 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 31/41] target/nios2: Make nios2_cpu_tlb_fill sysemu only Date: Sat, 18 Sep 2021 11:45:17 -0700 Message-Id: <20210918184527.408540-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for nios2. Remove the code from cpu_loop that handled the unnamed 0xaa exception. Signed-off-by: Richard Henderson --- linux-user/nios2/cpu_loop.c | 10 ---------- target/nios2/cpu.c | 2 +- target/nios2/helper.c | 8 -------- 3 files changed, 1 insertion(+), 19 deletions(-) -- 2.25.1 diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index fd3f853ac2..c06fb6fabd 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -106,16 +106,6 @@ void cpu_loop(CPUNios2State *env) info.si_code = TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case 0xaa: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* TODO: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->regs[R_PC]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; default: EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n", trapnr); diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 9938d7c291..b9f79b1bb2 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -222,10 +222,10 @@ static const struct SysemuCPUOps nios2_sysemu_ops = { static const struct TCGCPUOps nios2_tcg_ops = { .initialize = nios2_tcg_init, - .tlb_fill = nios2_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY .has_work = nios2_cpu_has_work, + .tlb_fill = nios2_cpu_tlb_fill, .cpu_exec_interrupt = nios2_cpu_exec_interrupt, .do_interrupt = nios2_cpu_do_interrupt, .do_unaligned_access = nios2_cpu_do_unaligned_access, diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 53be8398e9..8b9b55ec67 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -38,14 +38,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[R_EA] = env->regs[R_PC] + 4; } -bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - cs->exception_index = 0xaa; - cpu_loop_exit_restore(cs, retaddr); -} - #else /* !CONFIG_USER_ONLY */ void nios2_cpu_do_interrupt(CPUState *cs) From patchwork Sat Sep 18 18:45:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514237 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp674528jao; Sat, 18 Sep 2021 12:04:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwTp02ldNnpAF+S5H20UO2n4/PRYljmHiW+AQ2XZauRwBxCrwPrSDS7gOvuuj0AFRuDo+t8 X-Received: by 2002:a05:6e02:1d87:: with SMTP id h7mr12396139ila.92.1631991849935; Sat, 18 Sep 2021 12:04:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631991849; cv=none; d=google.com; s=arc-20160816; b=UySShRvo4il6goMp8yJHGNJ+jzZ+EXpxdpy4Aqb+cYjblDxCv85/Da7nRrPpDT7AVb jmDqDuKCrrKf3sR50jCV8aweMjF0Lou828rYW8qcAn+koaCZptt+ME0a3lH25dRh9Xdo di4bDCCxFarIcjJZf7MgacyXs5ybVgKj4x6qxY8VMSMVqM2mNhI2rHM47/ljFuEMeJqL BkVYlnc9IOx0DQpeSPQQj6OLuFfeR1QzosZcUTXyDzpRDRt001MXfcKBRZ/ExqXgB/4R i08dhP/NzWDKD4tReoMkzYG/pF2YGUrLgzOkdpdn35SLPI4X9m9FAZwiTWfPA06gCPot 1gzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MPeEJcgZH7TojaDG8K8aivb2xJIScpaxZoFZXE7a5sY=; b=nqxQXGZwU/qOUdz0mrTgMrHRqwFo3s9TF+fc48bp31z1DHybaywOui9bQuBEv6t17Q ixcbSwEPFyU1Q9OJHaoQj8rRryWBoX7MI857nWClva74sJcGczYCx/DxeUovQ3bQdFKg Rc76jYiEvFW7uLTORv8r7sB7JtXJENcES8ngkvvYpg+sWwgsPmMBT/UnEI1wR8Q/ISH4 YWgwo2r6tHxgPLtXrd+KC8gZ23n8IJFOjeEB9W5B0p1QeUl5c//yc3yvOJx6zYgUsOhi 10OJZtvB++BgeqQ7CmShtVazEBUhGuZ3HQIebPKsol/HAuDVd0YH7t056R4/M57x1yrn /1CQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S4JY2mSt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a13si6992803ilv.48.2021.09.18.12.04.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 12:04:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S4JY2mSt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfdB-0000LQ-Dn for patch@linaro.org; Sat, 18 Sep 2021 15:04:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54618) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLm-0005Ia-Dh for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:10 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:47089) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLb-0006ww-5H for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:10 -0400 Received: by mail-pg1-x52c.google.com with SMTP id m21so3884870pgu.13 for ; Sat, 18 Sep 2021 11:45:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MPeEJcgZH7TojaDG8K8aivb2xJIScpaxZoFZXE7a5sY=; b=S4JY2mStgSg8363Sq0kvbXKwnb2NR5+QabwRXj+5WKssNRzbI6i67hkzp6rDgWwvvc nzLXluddeGG+Y341TyCdea0z7DrY67mMI+ALF15VTgoYmb6az90n0u5GYoDC0lNMGH07 mbm7Cq4kp2Z82bCxfbVx2cjO9hoKyHdSSZPckA0CCuBZAQN+zh8MNFNdAhHPbHwJ42Uw 8RAB4POzXDyJvTpyt5uVD/yPzLwqxQn9rzTwfTIJc+F4S+Jv2T8HCvqR56++wj7i0gej T5a89iD8FvkqnQ69n9o+zUz5Vrb88fpaVb2qZbx5C+P4UkWZgHBHJ9Yn994NBGIrjtqf H0Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MPeEJcgZH7TojaDG8K8aivb2xJIScpaxZoFZXE7a5sY=; b=RGQ+Skg5mmfJwN3mDCMyJROUSym8FGKHALObH7vrrTVunq2K1/JHBZi4q+CzK+Nvqk xetaohYe7AAroKGvyDcnNts0ToEo87kCTt6DvZ94wc+aqDYj90n9JKFrf08CvG3Qvayu wVphmljKU/+vaZaHt3GsEZDf/17boUR7X7lexBD/mtEMuqR28Vhc2W8y6oSJOgcaK53w DLb9LYgmFC31LChyJjb0lm/zFi4a+f+052I2aWbA2WCNP9SyRZC422SrrwgqTZ6TAlxc lA5pXZ20NE4xvLBByujqnYZjaCQma3jswfDv2lyvjNG3L1ny9/ptetilDKdeV4UfdVq7 XKNw== X-Gm-Message-State: AOAM533kixa2dr1bhzKefqTbASNBLqayH294eyaC4lLJiDRj9GysuIsh zuIf9B/SgVXiSfBRv+f7+EF8WY6vcmjZvA== X-Received: by 2002:a63:4d20:: with SMTP id a32mr15733094pgb.247.1631990755291; Sat, 18 Sep 2021 11:45:55 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 32/41] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE Date: Sat, 18 Sep 2021 11:45:18 -0700 Message-Id: <20210918184527.408540-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The kernel vectors both of these through unhandled_exception, which results in force_sig(SIGSEGV). This isn't very useful for userland when enabling overflow traps or fpu traps, but c'est la vie. Signed-off-by: Richard Henderson --- linux-user/openrisc/cpu_loop.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index b33fa77718..314e7fba1e 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -21,6 +21,7 @@ #include "qemu-common.h" #include "qemu.h" #include "cpu_loop-common.h" +#include "signal-common.h" void cpu_loop(CPUOpenRISCState *env) { @@ -54,13 +55,17 @@ void cpu_loop(CPUOpenRISCState *env) break; case EXCP_DPF: case EXCP_IPF: - case EXCP_RANGE: info.si_signo = TARGET_SIGSEGV; info.si_errno = 0; info.si_code = TARGET_SEGV_MAPERR; info._sifields._sigfault._addr = env->pc; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; + case EXCP_RANGE: + case EXCP_FPE: + /* ??? The kernel vectors both of these to unhandled_exception. */ + force_sig(TARGET_SIGSEGV); + break; case EXCP_ALIGN: info.si_signo = TARGET_SIGBUS; info.si_errno = 0; @@ -75,13 +80,6 @@ void cpu_loop(CPUOpenRISCState *env) info._sifields._sigfault._addr = env->pc; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case EXCP_FPE: - info.si_signo = TARGET_SIGFPE; - info.si_errno = 0; - info.si_code = 0; - info._sifields._sigfault._addr = env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_INTERRUPT: /* We processed the pending cpu work above. */ break; From patchwork Sat Sep 18 18:45:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514242 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp676173jao; Sat, 18 Sep 2021 12:07:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwQ7MqqaqFjjR6QVYkmwIxfR5otqpT1pSty3iiMybv0Yrrb6Yu1sALi9xASro2dZNLQsGNv X-Received: by 2002:a6b:5d19:: with SMTP id r25mr8896565iob.11.1631992022707; Sat, 18 Sep 2021 12:07:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631992022; cv=none; d=google.com; s=arc-20160816; b=yp6uFCnC05qZvAYRUsXi4QveuTDPdfmbHTT9PdSlP8eTBgBLLcC3trS1ybbGvxmwak QPyDc2U5s5tQZKAfPlw9rrYDkvcpZIqTwDODA33w4i4tbBWo3Vv43VytGp7siU83fjEb AJdDUqidFq0KH1+FZiiEhV7No5yjoWUN0ySnZCAvJZXFsSIATSQHPhvDV7sBd713M+Ay tM95fr1pKRLJIMEPNFtr7AAhHQHRwMu5XWG5WiotP7d2nl2Q2f4owGs+y1bIJW11iknD U5lkMIPM+Anv12HM4fXxBYFUUVUhi702Ew9ziSmptMhAormoGiC0T5ujiqbEwlGXrbKP YtAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=b8i+4Ubm77XbfHdsRyJB5Dlng3rJ0jGxHde2wGc/RXc=; b=sqec8zB0s/17PjHP5f9LGQ/x723TVuG9YwI8SzgQZ8XPKs/BsPndI5fDfvTk0cOnee T28IfRM9U1CYRfToM3LsDdSakAkmDHjN/RdHG6G0xn3E4hd3ju3BXwgiWr8h63XdLnEP pGam616Y1bd5vZxAqLvTeP5lyTMMeKorkSvLZv9ae+SkjEqu2CcuK8FDQ7m4pFxvPlEN XV4EujE2/9RRh67Nv1N+VcVFMh9DkXbKTvMHicksfhZYOBqbN/rgIbUPX0uE++EGNdDw LItc0vx4lTS9MckmZ4EPScDq78XsbMTUoN9aNwtPmGFB/n7mJ8b1pjXMdiF4Tw1cvqje TEZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cFFXdP3k; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n6si4604430jac.111.2021.09.18.12.07.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 12:07:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cFFXdP3k; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59350 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRffy-00068t-3a for patch@linaro.org; Sat, 18 Sep 2021 15:07:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54640) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLn-0005Lj-FH for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:11 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:35636) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLb-0006x0-3j for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:11 -0400 Received: by mail-pf1-x431.google.com with SMTP id w14so1834208pfu.2 for ; Sat, 18 Sep 2021 11:45:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b8i+4Ubm77XbfHdsRyJB5Dlng3rJ0jGxHde2wGc/RXc=; b=cFFXdP3kMGcgUkPMjkjvATamv+a9RM5y7Xk85Ul6//YBwxwZOzp+cmR9PMOWgxR+Z7 nC5qz6Mqj9zZk6q20aeMIXbbShQ/Ovsb1JuGcvyDOsszNO2F5UvhqbDFbpVn7SsztP9A 6b6Q1hF6guf7MH4fz4z8hqNjHxkSd1uIIcnTZnBF2cJcOBWHySiyjoAsdXoqqn88xCi8 6fZqQmFE/42jBkviCuq9dlGH0npgRGOAnJZohDrfnidMEFfP8CaNJdeH4Vq0lhpo0x+P jx4Sz+T8wgVmUAZQ62lg8IcIeFZy1NFajZFw/xjOwtTLFw/6ZEQKEikmonHSkqIiE3ds quWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b8i+4Ubm77XbfHdsRyJB5Dlng3rJ0jGxHde2wGc/RXc=; b=mvxkuAsiK35hqZfFknJ55FyCwa9j9K/4mVarLJynGVPVDEIj82bFfXOstvXblTZWFW +LA1IOSegQe1oAJ+V1sK0QbUCdGO9u8XSQDbtYhU2KWbA035L+4nvpDBnqHJ6CMBqf+4 ebMz8vIRPhSJYn8vSVlEk0UqaNpk1un4HykG4wk0f4A8GstkAt55pKeaEpNSYZXFuOmy edad33Fwyb3a2INgEXhS2XAOa9cVxmk9y4AVvldVFP27nrlrKQh7XizoMrYCVXTvyPFX 4jlwAynOCsBoWezQxAYXWKhnmGf0vmlgjU3IOw2Y5s9AvhD8kcOs2USLQ41MlziagPLm w6Iw== X-Gm-Message-State: AOAM5305/VRx0OOSesluJnDT0fiOXvGrExDkFLl9SZ77lChKJg26dCta g7/CDDC5nIU6AtcZRwugB5WsmuyLXqbLXQ== X-Received: by 2002:a62:7d45:0:b0:445:545b:4d0e with SMTP id y66-20020a627d45000000b00445545b4d0emr7615686pfc.1.1631990755883; Sat, 18 Sep 2021 11:45:55 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 33/41] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Date: Sat, 18 Sep 2021 11:45:19 -0700 Message-Id: <20210918184527.408540-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for openrisc. This makes all of the code in mmu.c sysemu only, so remove the ifdefs and move the file to openrisc_softmmu_ss. Remove the code from cpu_loop that handled EXCP_DPF. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 7 ++++--- linux-user/openrisc/cpu_loop.c | 8 -------- target/openrisc/cpu.c | 2 +- target/openrisc/mmu.c | 8 -------- target/openrisc/meson.build | 2 +- 5 files changed, 6 insertions(+), 21 deletions(-) -- 2.25.1 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 187a4a114e..ee069b080c 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -317,14 +317,15 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); -bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); int print_insn_or1k(bfd_vma addr, disassemble_info *info); #define cpu_list cpu_openrisc_list #ifndef CONFIG_USER_ONLY +bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + extern const VMStateDescription vmstate_openrisc_cpu; void openrisc_cpu_do_interrupt(CPUState *cpu); diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index 314e7fba1e..5e50c0d743 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -53,14 +53,6 @@ void cpu_loop(CPUOpenRISCState *env) cpu_set_gpr(env, 11, ret); } break; - case EXCP_DPF: - case EXCP_IPF: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_RANGE: case EXCP_FPE: /* ??? The kernel vectors both of these to unhandled_exception. */ diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 3c368a1bde..0092fc161d 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -188,10 +188,10 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { static const struct TCGCPUOps openrisc_tcg_ops = { .initialize = openrisc_translate_init, - .tlb_fill = openrisc_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY .has_work = openrisc_cpu_has_work, + .tlb_fill = openrisc_cpu_tlb_fill, .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, .do_interrupt = openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 94df8c7bef..91cedf4125 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -23,11 +23,8 @@ #include "exec/exec-all.h" #include "exec/gdbstub.h" #include "qemu/host-utils.h" -#ifndef CONFIG_USER_ONLY #include "hw/loader.h" -#endif -#ifndef CONFIG_USER_ONLY static inline void get_phys_nommu(hwaddr *phys_addr, int *prot, target_ulong address) { @@ -94,7 +91,6 @@ static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot, return need & PAGE_EXEC ? EXCP_ITLBMISS : EXCP_DTLBMISS; } } -#endif static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, int exception) @@ -113,7 +109,6 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, OpenRISCCPU *cpu = OPENRISC_CPU(cs); int excp = EXCP_DPF; -#ifndef CONFIG_USER_ONLY int prot; hwaddr phys_addr; @@ -138,13 +133,11 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, if (probe) { return false; } -#endif raise_mmu_exception(cpu, addr, excp); cpu_loop_exit_restore(cs, retaddr); } -#ifndef CONFIG_USER_ONLY hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { OpenRISCCPU *cpu = OPENRISC_CPU(cs); @@ -177,4 +170,3 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } } -#endif diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build index e445dec4a0..84322086ec 100644 --- a/target/openrisc/meson.build +++ b/target/openrisc/meson.build @@ -10,7 +10,6 @@ openrisc_ss.add(files( 'fpu_helper.c', 'gdbstub.c', 'interrupt_helper.c', - 'mmu.c', 'sys_helper.c', 'translate.c', )) @@ -19,6 +18,7 @@ openrisc_softmmu_ss = ss.source_set() openrisc_softmmu_ss.add(files( 'interrupt.c', 'machine.c', + 'mmu.c', )) target_arch += {'openrisc': openrisc_ss} From patchwork Sat Sep 18 18:45:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514254 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp684969jao; Sat, 18 Sep 2021 12:22:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwmZtWyVSKIG3u47odEltJ0MgjmMsExuLghmDAgq3baU1gbwrbUxpcR9VkaWI5ayXlJ8ls3 X-Received: by 2002:a05:6e02:e53:: with SMTP id l19mr12546531ilk.217.1631992962060; Sat, 18 Sep 2021 12:22:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631992962; cv=none; d=google.com; s=arc-20160816; b=l93JMNO7vKqJOfc3TMoFZfjyolSVvA7mQkEvXJ/Y89z+xEufISsuYHWB5uP9PejvOj j8zMLhqXSXcXtZZ5K8LkNbdawOGrNn+Cey87DYAg4uR6ud+wrwtSp0Pfe2uYwMDFvJJK rdrNFKwhlqC8+1JobGQyDniM6qXrFxT71s0/EyFfTjn2Ly6vpO8asJic6ri/30DepVvN xRRxFdWhLVcNpPytYAnQNC9uv64S2TB9YUBsc+2/gItRUyhY9B1japd0VoDODIloOtR/ 6JpeBM8NgVgs3+8FZQAVr0CFkksHrYTRgWahyu5SYMIDdPp1UE9V3h5nKos8bTkhYxfG EoVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Sn+LIrzqj+yUnZFtGLsVKMxQIhFnl26SyubeCGE6DkU=; b=Y83YK8oHk+KsYG+JOeLLbQ3FD9dm7hfsWCa4AhMCZjHGjJgI9hNvpi3wXgJYixAvSl efYumnVbw5j3FCZt6PRdceisDtiLi572HSsbb/4kAYg6N3wZZhyULSAAVQPLicKI1TiX hO1/75bNm99blXebQVJWi7cH94Z2XxIfu9gRVXJSi7dEfAxNbqoCAlwJFfF7KM9se+tx muMRxUe4b1ZPUztWBrpvH0lZ6xPlMqFY+GiNjgrJ9PKc/mOp0xBKeOnPjfhvlZqj/xi0 sJ/HGyMFVsueBxZ4sy/R0JRgE7RIQYT8s1BQIc9G3gOxE6UFvk6eJO6xYqBZTBForwWS EkNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B6MspZYA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 3 --- target/ppc/internal.h | 9 +++++++++ target/ppc/cpu_init.c | 6 ++++-- target/ppc/user_only_helper.c | 15 +++++++++++---- 4 files changed, 24 insertions(+), 9 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 01d3773bc7..60d1117845 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1278,9 +1278,6 @@ extern const VMStateDescription vmstate_ppc_cpu; /*****************************************************************************/ void ppc_translate_init(void); -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); #if !defined(CONFIG_USER_ONLY) void ppc_store_sdr1(CPUPPCState *env, target_ulong value); diff --git a/target/ppc/internal.h b/target/ppc/internal.h index b71406fa46..f3e5aa8fbc 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -283,5 +283,14 @@ static inline void pte_invalidate(target_ulong *pte0) #define PTE_PTEM_MASK 0x7FFFFFBF #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) +#ifdef CONFIG_USER_ONLY +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); +#else +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#endif #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 5c134adeea..d56fde1215 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -9028,10 +9028,12 @@ static const struct SysemuCPUOps ppc_sysemu_ops = { static const struct TCGCPUOps ppc_tcg_ops = { .initialize = ppc_translate_init, - .tlb_fill = ppc_cpu_tlb_fill, -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .record_sigsegv = ppc_cpu_record_sigsegv, +#else .has_work = ppc_cpu_has_work, + .tlb_fill = ppc_cpu_tlb_fill, .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .do_interrupt = ppc_cpu_do_interrupt, .cpu_exec_enter = ppc_cpu_exec_enter, diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index aa3f867596..7ff76f7a06 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -21,16 +21,23 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "internal.h" - -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; int exception, error_code; + /* + * Both DSISR and the "trap number" (exception vector offset, + * looked up from exception_index) are present in the linux-user + * signal frame. + * FIXME: we don't actually populate the trap number properly. + * It would be easiest to fill in an env->trap value now. + */ if (access_type == MMU_INST_FETCH) { exception = POWERPC_EXCP_ISI; error_code = 0x40000000; From patchwork Sat Sep 18 18:45:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514238 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp674536jao; Sat, 18 Sep 2021 12:04:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwBLSafcQqEwXfsWta++LTduhkaBLHwUo9PG1o1KJu1Thh0JIOkCDG7eaBfS3lUxPTRvnTy X-Received: by 2002:a92:cb0b:: with SMTP id s11mr13086360ilo.210.1631991850825; Sat, 18 Sep 2021 12:04:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; 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[209.51.188.17]) by mx.google.com with ESMTPS id i12si8973961jac.26.2021.09.18.12.04.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 12:04:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WmdVLLhx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfdC-0000RE-9j for patch@linaro.org; Sat, 18 Sep 2021 15:04:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54610) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLm-0005IP-7F for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:10 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:35507) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLb-0006xA-3o for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:09 -0400 Received: by mail-pg1-x533.google.com with SMTP id e7so13099560pgk.2 for ; Sat, 18 Sep 2021 11:45:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yZsRnAbPNXmk9r6jQwi13vxXn5d80YjT3gRS7kzZYQg=; b=WmdVLLhxYmNfMaOGZHrEbsyNamF2DTSk/3y7jEKEvkeBqNWTBChMbaEnxeL/LG31Q4 kzSNkf0u2De/SXZovJwB3v9pRE1xPhRxIIpL3G3g3KGX+vXDd/OfzOqtR3BgR4NgqGEz OoJavbt3MbN+Pe+WCbpmxPs8s+U7VI2JIPLoFQf3Z/PISohBNJ+XD+ipVYK7MheaERit SMFGnUsKCnMx+1Fyq7VH/jjHGCAnSjLM9hDzbirgNi5nANlsXz2q01PplWmHwZF0s6+p q3Us/53glIJAnMXrDxd6twD7rBR9lVUlP7tjlEwQSEj/Br/hlsx6Tz7KIJ+LjNEMbvlq bl4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yZsRnAbPNXmk9r6jQwi13vxXn5d80YjT3gRS7kzZYQg=; b=zdVlJ8k/TKMoJUFn4jcZ7jT9tPyeV59C82k47VkDcqnu76CQZlnXIUoS6Z0F0gguGG N3rc9Htc2lFp3g9uaOL571BvqlVmqyKiahdLpJyMx3tjZ+JzQvmy8XH6gUxxNKkqnmYQ CFrCfVjBWCav1wWwvOOL43aiQEpKEBkw6GAtDzWRMos6382BihRLIf6a0OkW2wBr83cX JbgtEcS+7YLLDJIaJqcPHjwIoH6/UfYq0rK+xvvZSKBE9MVpVFrNBkIJ3L5IMrmfxlnj t5Vg9hqgp8r3IL2LP03+HaWRdryV1xKkQ6ExSxZPdvpqVdkzFXnP/13t/nxHTYaw8H61 UhQg== X-Gm-Message-State: AOAM531SIcFFki/EpXecStC4vUhAEOoCelwac0tkRKnP+D2QQorqxR/Q +9FYR6sBxWqgBLFgH0rOX9OhR4AaXMFZ4w== X-Received: by 2002:a62:1683:0:b0:3f3:814f:4367 with SMTP id 125-20020a621683000000b003f3814f4367mr17481629pfw.68.1631990757698; Sat, 18 Sep 2021 11:45:57 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 35/41] target/riscv: Make riscv_cpu_tlb_fill sysemu only Date: Sat, 18 Sep 2021 11:45:21 -0700 Message-Id: <20210918184527.408540-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for riscv. Remove the code from cpu_loop that raised SIGSEGV. Signed-off-by: Richard Henderson --- linux-user/riscv/cpu_loop.c | 7 ------- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 21 +-------------------- 3 files changed, 2 insertions(+), 28 deletions(-) -- 2.25.1 diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 74a9628dc9..49fa2209a7 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -85,13 +85,6 @@ void cpu_loop(CPURISCVState *env) sigcode = TARGET_TRAP_BRKPT; sigaddr = env->pc; break; - case RISCV_EXCP_INST_PAGE_FAULT: - case RISCV_EXCP_LOAD_PAGE_FAULT: - case RISCV_EXCP_STORE_PAGE_FAULT: - signum = TARGET_SIGSEGV; - sigcode = TARGET_SEGV_MAPERR; - sigaddr = env->badaddr; - break; case RISCV_EXCP_SEMIHOST: env->gpr[xA0] = do_common_semihosting(cs); env->pc += 4; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index abb555a8bd..830e5b568f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -642,10 +642,10 @@ static const struct SysemuCPUOps riscv_sysemu_ops = { static const struct TCGCPUOps riscv_tcg_ops = { .initialize = riscv_translate_init, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, - .tlb_fill = riscv_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY .has_work = riscv_cpu_has_work, + .tlb_fill = riscv_cpu_tlb_fill, .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .do_interrupt = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 701858d670..2260f95c79 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -747,7 +747,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, riscv_cpu_two_stage_lookup(mmu_idx); riscv_raise_exception(env, cs->exception_index, retaddr); } -#endif /* !CONFIG_USER_ONLY */ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -755,7 +754,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; -#ifndef CONFIG_USER_ONLY vaddr im_address; hwaddr pa = 0; int prot, prot2, prot_pmp; @@ -887,25 +885,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } return true; - -#else - switch (access_type) { - case MMU_INST_FETCH: - cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; - break; - case MMU_DATA_LOAD: - cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; - break; - case MMU_DATA_STORE: - cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; - break; - default: - g_assert_not_reached(); - } - env->badaddr = address; - cpu_loop_exit_restore(cs, retaddr); -#endif } +#endif /* !CONFIG_USER_ONLY */ /* * Handle Traps From patchwork Sat Sep 18 18:45:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514249 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp680447jao; Sat, 18 Sep 2021 12:14:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwCflXdPZMbt5phEygnpHqBgzVe/Q4UaWnwgpSbALOnTNewZMYh2ZvOPst8Xjv6CdoeZNJ+ X-Received: by 2002:a25:bb08:: with SMTP id z8mr22099045ybg.306.1631992475675; Sat, 18 Sep 2021 12:14:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631992475; cv=none; d=google.com; s=arc-20160816; b=dOZDv/ExoC7PkJJaKipbLf/ePnyT+vj2LZ/6P171j5R5pV7qPjoW4Ip8+DK6yc8U9I BV7f12I5fEc2EEgWre/A0nv9F974HT0E4IPYPIL0FWcfTdGA3mgZhTaW8JHX6fj5/M6z pqzscAroOEN6UDwLt5GOQ8rzguwgIpPX0PqRQMGc1fJwK6phzr9j6g39uywYBiSiezPW BD+wk7W/6DJ9C+z7CWSOahvqVVtYn1i+xDJ2XnmNQp06F4syG5s0RJD8zEZqdgsRngCy 2+zncurgLYqpnJP9TPtdvm8btL54J3MwKbJ6+uKeZu9KeM2uBCa2KjZZR2wk59F/PZVW pnNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gDQMWHvEjv12594lnZ03zCrTOpjiJ4+Ocs7aFLjDJuU=; b=wzjFzvDM+j3OfCtfGFMEODjMVuUqcPP1cKbfRPfYen1gRfP75lwp2udl6n9O5c9gTT Bs51MqT7qa/EJ/5apIBMRNfAQZirhQFr8NdJ/WdX50hfPWvPA7aYMlPG3akm6YAu7+vS 4PTRi9eymNP6nQldWkQAIvuCWiKGOPlEA+DEHJeD9fnhnIB0eswB6D/bcNJKSyP6c8QX anGhxTSqjMkS33OudF01Kgrbenmhj6czhaHCl3Zq/SHoho0aMuA983Wc/zb0tCgGEEBW Ydyzlky07fivssUkF8tj6iUik7fYRNkDQloXhvPCmMGBQYmyXc1TGwrFqMtW3/dSm5a0 SbvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="r/2ntDRm"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 10si9596635ybs.391.2021.09.18.12.14.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 12:14:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="r/2ntDRm"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55946 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfnH-0005ue-5z for patch@linaro.org; Sat, 18 Sep 2021 15:14:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54642) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLn-0005Lp-GJ for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:11 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:37432) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLe-0006xF-Qy for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:11 -0400 Received: by mail-pg1-x52d.google.com with SMTP id 17so13099119pgp.4 for ; Sat, 18 Sep 2021 11:45:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gDQMWHvEjv12594lnZ03zCrTOpjiJ4+Ocs7aFLjDJuU=; b=r/2ntDRmBf5TGJNkoiPoWGAY9oJHnDO2yFUuRzcsxKqv9RDdACsKbbAZf0/vsRkTkC 85X9A7uzR35wTz2CMUF69pj7skYSM0mhOK8IHl+bHzSUEiOGmoBGJGFw7y30f2GVXK9E kBjucLi0ya/Xn8jKiegkleqaXmTKOJtlDXTLnU96SWJprMcwYjTiOxW0j+oZu4VJigma wqdNUJlv+Kb5wHbbInnj+oBDtSgPqhG0RErG/RLpmcXz3Srnt2jKeSTancrH6rjqw88p gg9If+1RCp2MwViBCxe+C3EN+nZPx6ThPFzrlhL2mcUTU+VLSPEaBTeQVOH7aVCPNbVt ouVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gDQMWHvEjv12594lnZ03zCrTOpjiJ4+Ocs7aFLjDJuU=; b=HQzR0uN5f8nBwoq7IX1fq71JMDExeKWwx8eJ7Avz8zisjAQ1ycQVrAodfULu4963pM iMKN4oSebclKwBfFyVHEKDHXKkVOCtaSaCoZG6RgQnMSTC7oLbGTzsjtfPpbMjp+x/9d NiW17QBl450Oo+I7f6uFKGQCZ/zry4Fii0LPTYU1SOKAs4kAaUkBSaIA5bFUym8zbxeA oJEypVSfVJvGJb600KvAMG+YpbDi3clp5DlXaLpLOJucO3DePzDiYheKbzX1db86Ky/n FgI9QHxLuPCy6itts56NdmLlDQqdRquePUaOcQHreezVrrpZE1bUt5SW0k27mCCQ9+Ur 9B1g== X-Gm-Message-State: AOAM533A/7WSjIYh1ZFQxIWtmiLQRyodYi6An7bM7NqWWEmdjsw7kcmM jsWtB/j1EGyPjfajqkSzvejfBMdSuDJZcA== X-Received: by 2002:a63:ea44:: with SMTP id l4mr15721455pgk.210.1631990758546; Sat, 18 Sep 2021 11:45:58 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 36/41] target/s390x: Use probe_access_flags in s390_probe_access Date: Sat, 18 Sep 2021 11:45:22 -0700 Message-Id: <20210918184527.408540-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Not sure why the user-only code wasn't rewritten to use probe_access_flags at the same time that the sysemu code was converted. For the purpose of user-only, this is an exact replacement. Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 0bf775a37d..596270e45d 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -142,20 +142,12 @@ static int s390_probe_access(CPUArchState *env, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t ra) { +#if defined(CONFIG_USER_ONLY) + return probe_access_flags(env, addr, access_type, mmu_idx, + nonfault, phost, ra); +#else int flags; -#if defined(CONFIG_USER_ONLY) - flags = page_get_flags(addr); - if (!(flags & (access_type == MMU_DATA_LOAD ? PAGE_READ : PAGE_WRITE_ORG))) { - env->__excp_addr = addr; - flags = (flags & PAGE_VALID) ? PGM_PROTECTION : PGM_ADDRESSING; - if (nonfault) { - return flags; - } - tcg_s390_program_interrupt(env, flags, ra); - } - *phost = g2h(env_cpu(env), addr); -#else /* * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr==NULL * to detect if there was an exception during tlb_fill(). @@ -174,8 +166,8 @@ static int s390_probe_access(CPUArchState *env, target_ulong addr, int size, (access_type == MMU_DATA_STORE ? BP_MEM_WRITE : BP_MEM_READ), ra); } -#endif return 0; +#endif } static int access_prepare_nf(S390Access *access, CPUS390XState *env, From patchwork Sat Sep 18 18:45:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514255 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp685840jao; Sat, 18 Sep 2021 12:24:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxuDJRqQcej4CT2OPRpFsNDvdqRKEjOIVDSPSzJbLwEacdMIq2hZJuoOFd7t2mLmw8iXrF+ X-Received: by 2002:a05:6102:2158:: with SMTP id h24mr12336896vsg.15.1631993047629; Sat, 18 Sep 2021 12:24:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631993047; cv=none; d=google.com; s=arc-20160816; b=aTAF6aDMmdJ54rOOCqCOwjN+hD84mPHcquEU51aghCo+MnrOFgcm7pb5Yzjp6fEc/R nTA5XgtsLCjJdIqJBc1zn71v/XqfuPsiNbuPb9MwU9zIV+O2Q4cI+7X69zLjmWbFTq/1 DOefiTrDs+DF34bBo4VTI8DuldCYr36U33qoSmwMqQRuDuXuVefWzvymKvYJj6kQoD5k pRnDOVBJzH+FC28kSQy8F8fdkS/Zx/ZlHnqJ2A5VaYiD2vg6mCyeSUFv1VhUJY7GR4/z 4Z14iNdiK6fXWpE4gYgVPs+oFU4dfp1iSiEDYYbXj3T8F65ZMflXX7kPcUhVbHxXfVnd ITag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ONHPGv0AvpF9KQATDBu+SfMWLuLooluHmc8c/gF2z5A=; b=VbDtuCl4FktB1SXi5a4/28bH5VFfb5wPXpuh0Hds3NYf/PjmOR5HH9XzvrjjEjvOg+ 3Eoa+36VPWl7LWAEw++7JxFINemXl/NuocqxBhdzWaO50CcXjoizeJHpg3Iun77CzuGT gbmy63DI7XsLcUtn+POuIJ9UYOw/URT2HAwxsL3rLmH8lH4r2NDDmJMqL9jVP0eztY+q zEwHqa31h3Xa9fAsfVb4LoniImNoHaI0SDT+jWDuXuByraajZdIPFd7HiOb5fT03cAcA IbP/+meFEELvvhWN73hKy+ScSXlqMdyuJeSkhRGsF6UE2yRUG1KZtsgZtmZg2j2ExqGw PxJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=c3DuABvM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c26si443588vsk.158.2021.09.18.12.24.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 12:24:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=c3DuABvM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46250 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfwV-0001tk-3J for patch@linaro.org; Sat, 18 Sep 2021 15:24:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54654) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLo-0005Nj-1q for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:12 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:39821) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLi-0006xc-3r for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:11 -0400 Received: by mail-pg1-x530.google.com with SMTP id g184so13086196pgc.6 for ; Sat, 18 Sep 2021 11:46:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ONHPGv0AvpF9KQATDBu+SfMWLuLooluHmc8c/gF2z5A=; b=c3DuABvMfWVFlJI6cwA3gmYr1DibOy/mj7gDlt0ge4O5y0piUKcR5vapFJhlg20g71 8qO4KVrkDJejclFl7kfoQtyJzVG+NNd4vJYM8UdhO3GWu8fzxJ0SACM0lq7yDWjgFMk2 WPRWPdWVhWS9gm1jNx0y4wsxcSFtzSYpSrzEDGP13QiHbkYxsew8skyhziioI819vkIG OYnLx/JBVOyIOIG5JlWr6YPiXDYM88AQ+lFlyjVHUGr4borXEh6Kd1alEtiZWIDfHOvE DnUcVnYOSR3f9/LfrHUI2orV9EoCFZjugGJXKq8LNssWttLkJLVsnD8tYQMBHZ67o2Zv ggdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ONHPGv0AvpF9KQATDBu+SfMWLuLooluHmc8c/gF2z5A=; b=Q2+J9ApHXmedH4NrhUUTBWxdp776JHkIkiJyiMayLru0mRsyGJXk9ZBgJles5OSy69 k92w9+OQBV6sezJ9Tl1f4atuwHcW3U0YNCsWyCr2z1OMBQNEbQ7lUxavq5Xh5167S2S3 SelXFFDsZrqLvJgmhuvxOsUvDxQXXg2ueG4DvIxob2QTKgGLDqbxM2pNifBJHKzUiZl1 V454pV3VcEEuTe+RoAiFkwdxhFegHolkKjIZwwKKMLudMW57sSnnn2ojRm6zFV1NW3eD IZ00D8zQXl9zuKI3xQ9T0pw6+H3YBphvJPFabTybotONWVjRLTvKFcsDKSSlcOUB0jO4 z/TQ== X-Gm-Message-State: AOAM5328PieuobR52vyzhg+GcZz0x7/TOmggSLQrICXpNlTeXNg4HpmX 46ayJs5++WjrLqU8FcfhJDhen65wdUDU5Q== X-Received: by 2002:a62:a11b:0:b0:444:64df:9f2 with SMTP id b27-20020a62a11b000000b0044464df09f2mr11759144pff.31.1631990759348; Sat, 18 Sep 2021 11:45:59 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 37/41] target/s390x: Implement s390_cpu_record_sigsegv Date: Sat, 18 Sep 2021 11:45:23 -0700 Message-Id: <20210918184527.408540-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the masking of the address from cpu_loop into s390_cpu_record_sigsegv -- this is governed by hw, not linux. This does mean we have to raise our own exception, rather than return to the fallback. Use maperr to choose between PGM_PROTECTION and PGM_ADDRESSING. Use the appropriate si_code for each in cpu_loop. Signed-off-by: Richard Henderson --- target/s390x/s390x-internal.h | 13 ++++++++++--- linux-user/s390x/cpu_loop.c | 14 +++++++------- target/s390x/cpu.c | 6 ++++-- target/s390x/tcg/excp_helper.c | 18 +++++++++++------- 4 files changed, 32 insertions(+), 19 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 7a6aa4dacc..2b6791a3a2 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -270,13 +270,20 @@ ObjectClass *s390_cpu_class_by_name(const char *name); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); +#ifdef CONFIG_USER_ONLY +void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr); +#else +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#endif + /* fpu_helper.c */ uint32_t set_cc_nz_f32(float32 v); diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c index 6a69a6dd26..7a1d032227 100644 --- a/linux-user/s390x/cpu_loop.c +++ b/linux-user/s390x/cpu_loop.c @@ -21,9 +21,8 @@ #include "qemu-common.h" #include "qemu.h" #include "cpu_loop-common.h" +#include "signal-common.h" -/* s390x masks the fault address it reports in si_addr for SIGSEGV and SIGBUS */ -#define S390X_FAIL_ADDR_MASK -4096LL static int get_pgm_data_si_code(int dxc_code) { @@ -109,12 +108,13 @@ void cpu_loop(CPUS390XState *env) n = TARGET_ILL_ILLOPC; goto do_signal_pc; case PGM_PROTECTION: + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_ACCERR, + env->__excp_addr); + break; case PGM_ADDRESSING: - sig = TARGET_SIGSEGV; - /* XXX: check env->error_code */ - n = TARGET_SEGV_MAPERR; - addr = env->__excp_addr & S390X_FAIL_ADDR_MASK; - goto do_signal; + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, + env->__excp_addr); + break; case PGM_EXECUTE: case PGM_SPECIFICATION: case PGM_SPECIAL_OP: diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index df8ade9021..fa999d586d 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -268,10 +268,12 @@ static void s390_cpu_reset_full(DeviceState *dev) static const struct TCGCPUOps s390_tcg_ops = { .initialize = s390x_translate_init, - .tlb_fill = s390_cpu_tlb_fill, -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + .record_sigsegv = s390_cpu_record_sigsegv, +#else .has_work = s390_cpu_has_work, + .tlb_fill = s390_cpu_tlb_fill, .cpu_exec_interrupt = s390_cpu_exec_interrupt, .do_interrupt = s390_cpu_do_interrupt, .debug_excp_handler = s390x_cpu_debug_excp_handler, diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 3d6662a53c..b923d080fc 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -89,16 +89,20 @@ void s390_cpu_do_interrupt(CPUState *cs) cs->exception_index = -1; } -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +void s390_cpu_record_sigsegv(CPUState *cs, vaddr address, + MMUAccessType access_type, + bool maperr, uintptr_t retaddr) { S390CPU *cpu = S390_CPU(cs); - trigger_pgm_exception(&cpu->env, PGM_ADDRESSING); - /* On real machines this value is dropped into LowMem. Since this - is userland, simply put this someplace that cpu_loop can find it. */ - cpu->env.__excp_addr = address; + trigger_pgm_exception(&cpu->env, maperr ? PGM_ADDRESSING : PGM_PROTECTION); + /* + * On real machines this value is dropped into LowMem. Since this + * is userland, simply put this someplace that cpu_loop can find it. + * S390 only gives the page of the fault, not the exact address. + * C.f. the construction of TEC in mmu_translate(). + */ + cpu->env.__excp_addr = address & TARGET_PAGE_MASK; cpu_loop_exit_restore(cs, retaddr); } From patchwork Sat Sep 18 18:45:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514257 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp687569jao; Sat, 18 Sep 2021 12:27:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzSbKTMpbkhzlXqCvtmJonbCXYlyEnP+ksvyJI16b/3+7qX7MirkjcPdoDjriwptHnF39DM X-Received: by 2002:a92:4a10:: with SMTP id m16mr12678471ilf.91.1631993241683; Sat, 18 Sep 2021 12:27:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631993241; cv=none; d=google.com; s=arc-20160816; b=mmh6DkMrJJxcT3RGUjUMKSoamKYa/5772wP4sM/RjBYXQ8cTN+q0XaGKUR/ifSAWYI uFpe3E58hK2yskG23mmLqzUa0w0sq3oeOgxlhnC7qecyOzbzb9R0xe8PhgvFezi99GdV pSarLP15ISAP9mPbl0buFQOqyBIMDjvXnld/ZNiJIbh8oje6O8SWvI3s0CjAq1B67GWl jDWiEnrC6CVfaUA/w3WgXsb6ioynyiA1RfcxKkikSlJLCBBAEw/4wKsX0LjJR2qTDIom E5Hgl8Vl20oudWhfXGiLpJUmvHxyze2utEijMIVL1NrrcaDs3mMjqLFyGRZFYceA+w5Y lH/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gr1Yuwax54Nh89kDqsASWK4djVgjs7rSxRSreX+dYpg=; b=FUJcZjAYZ+UmGKc8kAx290PAouSePIwg3Ac1X3tiwlfNMvlRdHDq4kiIVhaFHPIadk Gc+G2dMq2npKSkDjCce3tM23iUY80MLmQAYoCWaN9S5ZBquXjjpzTUS3EIHk8v/4iuQ9 lCaww8PRdZtIqyqMVtdFRHemlLuNnKXsHfjqEjmclbHc0FtUdVJQz6IQBMYO3gwRUrRA U/EFfjb8OIZfu2WsIdPTMFQOoqN3L2z4IVr6R2lSBBI8Ynt5Gc9Z+4wMwKZALTSrIFs7 Jc2S5eAa8TvbtRj5c/gi48geZj0ygSFsmsnyUwTih9nIupzYlVyXFhyTmZzf7QyHDvaN kQrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kUeshxtZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s18si8989047ilj.28.2021.09.18.12.27.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 12:27:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kUeshxtZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50682 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfzd-000503-1Y for patch@linaro.org; Sat, 18 Sep 2021 15:27:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54664) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLp-0005O8-Qt for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:16 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:42813) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLi-0006ya-RG for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:13 -0400 Received: by mail-pj1-x1032.google.com with SMTP id p12-20020a17090adf8c00b0019c959bc795so4165128pjv.1 for ; Sat, 18 Sep 2021 11:46:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gr1Yuwax54Nh89kDqsASWK4djVgjs7rSxRSreX+dYpg=; b=kUeshxtZGZYrHMuYDZiehg4SmI4nXrIGdmK4B2c6hyJEYt9Spr5IDDHmyzACWH9Lyx 6QbH2g+7VMZrWXcZXSl5iNcnKD2edHrZEex0MREXodzXcp1wUJVyR8lfhc6murxotSRu 9ZkWbxHTiojkj6pBbVXkZl52yeEOt4Qo67kdYnJE65+A94/0gNJZDRw7pJpRW6DX+tc+ /oxZ/e82SgEKkOnFn8VQ5gqLDmz1RiXeKFRdX162ICjRA2jrhikrmxTQPFzAgfU9Z2Ie uo13NFIC4ZaX+DRSqBdjqkZNdHOYY9dRecbfGyBAfg1lPaRscR6GH8yZJLUKFqhgGB/5 JXEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gr1Yuwax54Nh89kDqsASWK4djVgjs7rSxRSreX+dYpg=; b=pROxxZ2yPpqw0MPHL8uHkayi/6sKETlFkFAAzXbe0ADi22Ps8xzYoWIzSfs1ZHUe2h W1CTw9LUzzoOiFElKipo9wa1ve+Gc3UtkTrs4URPLTutRY9vhP3CEE5gQVwdoop8Qp0V NRFkfJD5/A3jJqyzQyYBjPZ7dNuPO69VN0/TvypQ5sqtN8QtzDPKo9w7OTFSS/4aClr1 TPOp9dg6MXcOenFLz4vmn9VzguKt6xk2GMpkEoxRbhYmXr2/Ru3i+PwUbeb1WorBsgJ1 6f7bH4EFERuI37LtXlXUyg0EUTFXFOBoJTFBGrFvkR3WSrAfv8RJA22iAy6Hy6SUVyA/ YLEQ== X-Gm-Message-State: AOAM531q1mCXPf8t08o1uUO7/UQVm7tlmgmo4yPLG9fBitYi2i0NcMLe 8XvAJ/0vJ+1wHCYbVS+NbUsit72yXEcQAQ== X-Received: by 2002:a17:90a:d686:: with SMTP id x6mr19597660pju.227.1631990760060; Sat, 18 Sep 2021 11:46:00 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.45.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:45:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 38/41] target/sh4: Make sh4_cpu_tlb_fill sysemu only Date: Sat, 18 Sep 2021 11:45:24 -0700 Message-Id: <20210918184527.408540-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for sh4. Remove the code from cpu_loop that raised SIGSEGV. Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 6 +++--- linux-user/sh4/cpu_loop.c | 8 -------- target/sh4/cpu.c | 2 +- target/sh4/helper.c | 9 +-------- 4 files changed, 5 insertions(+), 20 deletions(-) -- 2.25.1 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 56f7c32df9..17458587a5 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -213,12 +213,12 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, int mmu_idx, uintptr_t retaddr); void sh4_translate_init(void); +void sh4_cpu_list(void); + +#if !defined(CONFIG_USER_ONLY) bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); - -void sh4_cpu_list(void); -#if !defined(CONFIG_USER_ONLY) void superh_cpu_do_interrupt(CPUState *cpu); bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); void cpu_sh4_invalidate_tlb(CPUSH4State *s); diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c index 222ed1c670..8408d0c42d 100644 --- a/linux-user/sh4/cpu_loop.c +++ b/linux-user/sh4/cpu_loop.c @@ -63,14 +63,6 @@ void cpu_loop(CPUSH4State *env) info.si_code = TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case 0xa0: - case 0xc0: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->tea; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); arch_interrupt = false; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index fb2116dc52..0cc1542681 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -237,10 +237,10 @@ static const struct SysemuCPUOps sh4_sysemu_ops = { static const struct TCGCPUOps superh_tcg_ops = { .initialize = sh4_translate_init, .synchronize_from_tb = superh_cpu_synchronize_from_tb, - .tlb_fill = superh_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY .has_work = superh_cpu_has_work, + .tlb_fill = superh_cpu_tlb_fill, .cpu_exec_interrupt = superh_cpu_exec_interrupt, .do_interrupt = superh_cpu_do_interrupt, .do_unaligned_access = superh_cpu_do_unaligned_access, diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 53cb9c3b63..6a620e36fc 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -796,8 +796,6 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } -#endif /* !CONFIG_USER_ONLY */ - bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -806,11 +804,6 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, CPUSH4State *env = &cpu->env; int ret; -#ifdef CONFIG_USER_ONLY - ret = (access_type == MMU_DATA_STORE ? MMU_DTLB_VIOLATION_WRITE : - access_type == MMU_INST_FETCH ? MMU_ITLB_VIOLATION : - MMU_DTLB_VIOLATION_READ); -#else target_ulong physical; int prot; @@ -829,7 +822,6 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) { env->pteh = (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_MASK); } -#endif env->tea = address; switch (ret) { @@ -868,3 +860,4 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } cpu_loop_exit_restore(cs, retaddr); } +#endif /* !CONFIG_USER_ONLY */ From patchwork Sat Sep 18 18:45:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514256 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp686707jao; Sat, 18 Sep 2021 12:25:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwi+WRhpGKVvWkDngF+h2H0WVZN1QSNseE6bMoWDDEG1fjq8YROJJC1SQENCA9mAswHNhiJ X-Received: by 2002:a05:620a:228c:: with SMTP id o12mr16319301qkh.367.1631993134737; Sat, 18 Sep 2021 12:25:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631993134; cv=none; d=google.com; s=arc-20160816; b=iuXRtiw0GHWY1ckreedCDjvvOWg0+V0XeO/x7BqxfbPcQZx+EBSSK9/zk0OLf3lyjP xos63vaFJFYm77xgNxpgGW6pK0hAmEusUQpbwX4evrUk1672XaXFPy7OdIrkSM0YTIXR Cu5zI1NGWfMzrpIScGTnT0n6cdFE+TqziVuyO/eRZSzVMyRnnGN5mt78SBet4UmiY+A7 J8XZWX62T8GDmeSnijcESpFiyrJp8bokikO7mP+SxX9YjoQ/2DW7dzH0+kMQ/Nq8AQLZ sMv2QC64zic09kqDWmn2Mdd3Wma122/ZlMBXdEzm/vSckt/MZBsNoZcqehXIvR0EmWqp LYoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mkkzYJUY8Ap6SXnhYvTgrVEh2l0oObcUDiO/BLDBzw0=; b=nnh/2ZThXO3IvTnVkz20buGEJxqFlxaAhqU0nGXZ2fuSG42Bc0aXap8XVj8ne/dLBr JpIMrb6ZoqkCToI+zNu7XlSAxfSRXzSVE/IZ3cD1vKp9GWkHleDFCVMzpAiwWEafZ8eI X1AMPj3IFxrbWrMUlZAnaTp9bNv8yey69yJ+P48Rox8HI3rhx7liDN51Wm/EGbpSy4RN Bj/PmZQq0C5+taz3J4PvLZyk71GFXRFLHn4CjJHyIVmPXJu4XXx+ClrQNsWs2OLDyZ9t EDGQtcxzHJ11aECG8a4J04r1gc5ShFgz0wdNgIlkllPR/nsujl0mcpT991l4o+wLukT4 1ZBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nlbammJF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h1si5901706qvx.123.2021.09.18.12.25.34 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 12:25:34 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nlbammJF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48382 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfxs-0003KM-Ky for patch@linaro.org; Sat, 18 Sep 2021 15:25:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54660) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfLo-0005O4-F2 for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:16 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:34415) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfLg-0006zV-Jr for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:46:12 -0400 Received: by mail-pl1-x629.google.com with SMTP id o8so8402702pll.1 for ; Sat, 18 Sep 2021 11:46:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mkkzYJUY8Ap6SXnhYvTgrVEh2l0oObcUDiO/BLDBzw0=; b=nlbammJFqlm9eVNMRbYzb5TJ20C9Zx4h/Jpcs4TWAs/rEUoqAPkVPH0F/ib/M0Rd1e MGIhFOqew9kS0LlIHY2gGl0THVmmdhdDRRsGLDizpQ1IN3/WVLILQnoTzzoZxJi8KzIM Gt7X0Pud1H7KyYpG4wJrf61PQBDSEsII4nhNcNGX21LEGSHrVJE/8FQ3hlZMUKQyZm9M h5PrzN71jqgNwyntA289XMIWu9BLkDP3lTDEasEhf4PEvdFKn2oe8Mk3pzptF+x1LcEN yjZPgTWphxgyAotJ8v6/ZpIw8CHMgDU8MawJTblHNHlVlGqGIxU+4HmnfzQRxr98r/Dj ftrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mkkzYJUY8Ap6SXnhYvTgrVEh2l0oObcUDiO/BLDBzw0=; b=BFssp2a40WqZwBvJYUqOvumFDE5FJB4kr7xQugKOr3r2QR9NVRO6tFCwY4jgBEt5sp 5Fo7+K3W2wTl2Jw4Ygbdh0C9k/YlbAoVNAHRyKwxLEK5fVHbC/iVoEFSW2RlYxpKoOra TvcikcD/pjtfKKge8zNxUv7rXV2TpKfTPfaMxW7jtWOTGlMXZj7jCraJGqLhQ9vwEMts CbRwbWicq1kBgh9GzbyctZGIRaeW8Caa787Lqg3UMpqKDNbncHH5FoiZ+tUElT6rrO0P LiAiTMICU2DCDVOKyM4b71TBv5NRn+Aca+jNxh1T0MCr/27u9g32t11s/REZd3CXCrCi adWQ== X-Gm-Message-State: AOAM530E7m370Lj0b/AWHhn8s3RplVHvXajHBBXqTmM2Ru/enNUIqAJN N7PCp3Nk1NGb1s+dkPrakF+Nl2V94n4w9Q== X-Received: by 2002:a17:90a:e2cb:: with SMTP id fr11mr20336548pjb.1.1631990761058; Sat, 18 Sep 2021 11:46:01 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id y26sm9555858pfe.69.2021.09.18.11.46.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:46:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 39/41] target/sparc: Make sparc_cpu_tlb_fill sysemu only Date: Sat, 18 Sep 2021 11:45:25 -0700 Message-Id: <20210918184527.408540-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for sparc. This makes all of the code in mmu_helper.c sysemu only, so remove the ifdefs and move the file to sparc_softmmu_ss. Remove the code from cpu_loop that handled TT_DFAULT and TT_TFAULT. Signed-off-by: Richard Henderson --- linux-user/sparc/cpu_loop.c | 25 ------------------------- target/sparc/cpu.c | 2 +- target/sparc/mmu_helper.c | 25 ------------------------- target/sparc/meson.build | 2 +- 4 files changed, 2 insertions(+), 52 deletions(-) -- 2.25.1 diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index 02532f198d..f5e0de7eaf 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -217,17 +217,6 @@ void cpu_loop (CPUSPARCState *env) case TT_WIN_UNF: /* window underflow */ restore_window(env); break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->mmuregs[4]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; #else case TT_SPILL: /* window overflow */ save_window(env); @@ -235,20 +224,6 @@ void cpu_loop (CPUSPARCState *env) case TT_FILL: /* window underflow */ restore_window(env); break; - case TT_TFAULT: - case TT_DFAULT: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - if (trapnr == TT_DFAULT) - info._sifields._sigfault._addr = env->dmmu.mmuregs[4]; - else - info._sifields._sigfault._addr = cpu_tsptr(env)->tpc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; #ifndef TARGET_ABI32 case 0x16e: flush_windows(env); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 4a63ed1264..c068ef98e3 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -866,10 +866,10 @@ static const struct SysemuCPUOps sparc_sysemu_ops = { static const struct TCGCPUOps sparc_tcg_ops = { .initialize = sparc_tcg_init, .synchronize_from_tb = sparc_cpu_synchronize_from_tb, - .tlb_fill = sparc_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY .has_work = sparc_cpu_has_work, + .tlb_fill = sparc_cpu_tlb_fill, .cpu_exec_interrupt = sparc_cpu_exec_interrupt, .do_interrupt = sparc_cpu_do_interrupt, .do_transaction_failed = sparc_cpu_do_transaction_failed, diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index a44473a1c7..2ad47391d0 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -25,30 +25,6 @@ /* Sparc MMU emulation */ -#if defined(CONFIG_USER_ONLY) - -bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - - if (access_type == MMU_INST_FETCH) { - cs->exception_index = TT_TFAULT; - } else { - cs->exception_index = TT_DFAULT; -#ifdef TARGET_SPARC64 - env->dmmu.mmuregs[4] = address; -#else - env->mmuregs[4] = address; -#endif - } - cpu_loop_exit_restore(cs, retaddr); -} - -#else - #ifndef TARGET_SPARC64 /* * Sparc V8 Reference MMU (SRMMU) @@ -926,4 +902,3 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } return phys_addr; } -#endif diff --git a/target/sparc/meson.build b/target/sparc/meson.build index a3638b9503..a801802ee2 100644 --- a/target/sparc/meson.build +++ b/target/sparc/meson.build @@ -6,7 +6,6 @@ sparc_ss.add(files( 'gdbstub.c', 'helper.c', 'ldst_helper.c', - 'mmu_helper.c', 'translate.c', 'win_helper.c', )) @@ -16,6 +15,7 @@ sparc_ss.add(when: 'TARGET_SPARC64', if_true: files('int64_helper.c', 'vis_helpe sparc_softmmu_ss = ss.source_set() sparc_softmmu_ss.add(files( 'machine.c', + 'mmu_helper.c', 'monitor.c', )) From patchwork Sat Sep 18 18:45:26 2021 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id h199si9014276iof.50.2021.09.18.12.18.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 12:18:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yd1OrPle; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34146 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfqq-0001vo-C0 for patch@linaro.org; Sat, 18 Sep 2021 15:18:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55114) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfOb-00026a-Kq for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:49:05 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:43776) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfOZ-0000Y1-Ti for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:49:05 -0400 Received: by mail-pg1-x535.google.com with SMTP id r2so13090825pgl.10 for ; Sat, 18 Sep 2021 11:49:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=evwYpaYtIeusJUHkEEt0rDRSAZ60QDEAx/EDgh8MFt8=; b=yd1OrPle+GMfowzsFnb2GpLny3itCxb1b1Fjs50fC6JIyetlNtQQBRGb7Y8cWGrEor 7T8KpI5djlt8zaJPhYx//iQRhi9wLLT+rZKLyFz047ytIAstoOttuU5fvAAfsig19ASY HlTpDWTjQZa4WstMWOyhriNUWg0gL0MBHgporCCnsngkjxkgP6Al5XYAVe3jPpwEBOr5 P3GhZQ1xurjtFpKCQJbCgjekW6Ob0F4VkKU8EGHLXnMcppYXB1CtCXlun7QDONrocJbT v0O6flus8sX2zWFHaPDFV/sQ2GOyVs0zS3tK09um/wh657iGvOTYMHsG9ZLgMHEzjaqs RnsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=evwYpaYtIeusJUHkEEt0rDRSAZ60QDEAx/EDgh8MFt8=; b=dtezWKDbN0PczRsaWLi4VUCp444NOM/DM6UMlyHQm5CXcdoKj1SJF2v17ccvoPoco4 mmZ7M8Q70jBldMQodygVKAg/MgtvhlRvmyimNJIcnlMZcWi2LzC+qtjbh7FUZI4HIbbb rwxmJEHDOKMl8nEpQjJTe0N2//YHd77ZhJkYLLFIMfoWJjSpsufb1p8NtB2pm1qsmaFH 4Bj05XH+dvslVB4ocT9sT8a6jKUzxiFIf/3qW6G7UwOHoxmDQMMGu3wmuZ59g6ukVEl/ BW1pPARLAp6AOXaJ+zzMdYu+8X7eJBSCfxnrYRfme/wjkpLLGWcajcuufg2BoyJNulA4 y53A== X-Gm-Message-State: AOAM530xkBwovwNBlLHOU1pWDcG8TlsEUq8QI3B59G56/ud1o9LDFtMf HmYMw1ABoGLmjedxlFtncAc+PMAVIApPLA== X-Received: by 2002:a63:1914:: with SMTP id z20mr15963906pgl.87.1631990942447; Sat, 18 Sep 2021 11:49:02 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id p30sm9916522pfh.116.2021.09.18.11.49.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:49:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 40/41] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only Date: Sat, 18 Sep 2021 11:45:26 -0700 Message-Id: <20210918184527.408540-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in raise_sigsegv is sufficient for xtensa. Remove the code from cpu_loop that raised SIGSEGV. Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 2 +- linux-user/xtensa/cpu_loop.c | 9 --------- target/xtensa/cpu.c | 2 +- target/xtensa/helper.c | 22 +--------------------- 4 files changed, 3 insertions(+), 32 deletions(-) -- 2.25.1 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 646965f379..cf0fffbd26 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -563,10 +563,10 @@ struct XtensaCPU { }; +#ifndef CONFIG_USER_ONLY bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c index 64831c9199..b48781c6e8 100644 --- a/linux-user/xtensa/cpu_loop.c +++ b/linux-user/xtensa/cpu_loop.c @@ -224,15 +224,6 @@ void cpu_loop(CPUXtensaState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case LOAD_PROHIBITED_CAUSE: - case STORE_PROHIBITED_CAUSE: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr = env->sregs[EXCVADDR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - default: fprintf(stderr, "exccause = %d\n", env->sregs[EXCCAUSE]); g_assert_not_reached(); diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 5cb19a8881..c289c4e679 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -192,11 +192,11 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = { static const struct TCGCPUOps xtensa_tcg_ops = { .initialize = xtensa_translate_init, - .tlb_fill = xtensa_cpu_tlb_fill, .debug_excp_handler = xtensa_breakpoint_handler, #ifndef CONFIG_USER_ONLY .has_work = xtensa_cpu_has_work, + .tlb_fill = xtensa_cpu_tlb_fill, .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, .do_interrupt = xtensa_cpu_do_interrupt, .do_transaction_failed = xtensa_cpu_do_transaction_failed, diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f18ab383fd..29d216ec1b 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -242,27 +242,7 @@ void xtensa_cpu_list(void) } } -#ifdef CONFIG_USER_ONLY - -bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; - - qemu_log_mask(CPU_LOG_INT, - "%s: rw = %d, address = 0x%08" VADDR_PRIx ", size = %d\n", - __func__, access_type, address, size); - env->sregs[EXCVADDR] = address; - env->sregs[EXCCAUSE] = (access_type == MMU_DATA_STORE ? - STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE); - cs->exception_index = EXC_USER; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - +#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) From patchwork Sat Sep 18 18:45:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 514245 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp677161jao; Sat, 18 Sep 2021 12:08:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJztnhzj2m1MI1dpAzuhM8bIuRtfoo7g3q/UEolazY2g1COzWOvOqJ0FQD9uMNoKdRmz0dYR X-Received: by 2002:a5e:d80a:: with SMTP id l10mr12998127iok.36.1631992127725; Sat, 18 Sep 2021 12:08:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631992127; cv=none; d=google.com; s=arc-20160816; b=VSADIKqFv34vEd/vLQ11aYdB7K65xanqcHw3W8Z4k1R6kbI9kdOKbbF4/2hNkjW0u5 Qb+eQttvG6nQTVJmYx4dQmTHhGPa4o6LuIx3+og0YU1HxLXWPkwZ+Ddc6FFkEevgR32W wompBDAcISQ1FzJEiiLRZUFXqApZxU//pgkOT29g+pltD4lj8AdQg/eEHCXrTYGwEsmZ uXXhW2SDR+9esjERSZ933tS/cBwPM2fKPzoyeIZm5lAkL/m8Y8YVGW1jbV9yO5nxMycJ KcTQ2nMn6vY0a51x102HKz8IaZuOEp481vCQwIIiYimIeHF2Od2Cg2kiGwAWz3VW1TGQ 05JA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=loPJ4fwu9tGHXBjISnsRpqTsfoBC8LJntmjmF4lGwE8=; b=hd0nyuz1VZX6uMOE4yZHTDdSUaSYzQDGV5hydvQ9OpMyFHR875vxaapO1BiBozy49V KQy9vYc6jm8bfjNB23asVST/LwKUbDYYB9zPrIBFK0oDBgE7+11CVEAUxlOQdESwFQpM WgCzFKj8DeX8ZBrRnXZOEA+yhuwKBlqNOkaEwD62tV/qIRMpiM7h0FUs21qiF9tydCKr aR6GL6pIj8qpCfL5GQj5dMVjiXER27zbbq+8QRDig3LbHZPzGdfMy/D+HnpDoE1uYoh8 b759ap2DkaCnDTdadP2Wx0r6oQ8CoeheJruTHWfZWEON/qA+4WRCk6j1QFqfrb0OyOOw 3IFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aL+gt94V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n9si3626950ilj.15.2021.09.18.12.08.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Sep 2021 12:08:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aL+gt94V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39294 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mRfhf-0003E0-78 for patch@linaro.org; Sat, 18 Sep 2021 15:08:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mRfOc-00028c-9P for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:49:07 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:42817) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mRfOa-0000YN-Ne for qemu-devel@nongnu.org; Sat, 18 Sep 2021 14:49:06 -0400 Received: by mail-pg1-x52b.google.com with SMTP id q68so13076548pga.9 for ; Sat, 18 Sep 2021 11:49:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=loPJ4fwu9tGHXBjISnsRpqTsfoBC8LJntmjmF4lGwE8=; b=aL+gt94Vb9+9BwTUJRN2W4P+jro2wkEzdTYq9+TQLx7wtNcNgWhS0iNngGjXeI+Xug 8IKjz7apG76IJeacSUXnBwD5Q7cpv/FbA5jg/qXXDtIA6lXJlI4gYCvar93xbdBjJHUZ vJssrWihnSveyxIquwJU8NzToYShdqUroHDAqzYxYK2+OxmZS2pPpCCVy4Ru5poEbHH7 lNJb48+EqiSSh5sZFgfpdXTAkb7CYX5wTBYbkK0A5U2sT3cVEjaGHCRgydsFWAH8xz8+ fOt1Q05rCJWdBOWfTgfuYsVK14P/E6OKeeeH9EcEbA/5X3c/bd4r7uh9YuLTVmhWDXj+ K9wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=loPJ4fwu9tGHXBjISnsRpqTsfoBC8LJntmjmF4lGwE8=; b=r2no62dWd6IL/ZnBV5AKWGfI+Ii6Xspv2z181qcyfNEFwcjckRv6kx3uEefUwT9mAL nHJpC03LQ1IqTi9Ossxc5/O4ZZqxA00DKDAteg4NkpIRBwTvxiL1btPRwypxGeAiN0+O 36cJOTo/uaeL2TVvBaI8QQW//nzCc7DChYWQqjiKrKzOJO/yTqdFODxSUBs91de3Yx1h tDAyD1sBYe4XNeX8IHN1tENOdFCU/rZmWvHxjyxd3SwN542MmtgZufFJl3LD+wZ80UPq EASg0SfjERFv/hRYQ+wDzk8c6KqRJNktaUjAL7qwznBEGrV4quJ2McIZFqNh6FXMEQt3 yJZw== X-Gm-Message-State: AOAM532PPYyd6+dEYQu/SMaMyHkaKXAV4bgGEh9kJ8zhTsc/piziuquc 8cwzofa44p1lX/nsKfqiAVFbHzJs5DxfQw== X-Received: by 2002:aa7:9823:0:b0:43c:6454:92b0 with SMTP id q3-20020aa79823000000b0043c645492b0mr17021396pfl.68.1631990943309; Sat, 18 Sep 2021 11:49:03 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id p30sm9916522pfh.116.2021.09.18.11.49.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 11:49:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 41/41] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Date: Sat, 18 Sep 2021 11:45:27 -0700 Message-Id: <20210918184527.408540-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210918184527.408540-1-richard.henderson@linaro.org> References: <20210918184527.408540-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have replaced tlb_fill with record_sigsegv for user mod. Move the declaration to restrict it to system emulation. Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 22 ++++++++++------------ linux-user/signal.c | 3 --- 2 files changed, 10 insertions(+), 15 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index e229a40772..988561e8d4 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -35,18 +35,6 @@ struct TCGCPUOps { void (*cpu_exec_enter)(CPUState *cpu); /** @cpu_exec_exit: Callback for cpu_exec cleanup */ void (*cpu_exec_exit)(CPUState *cpu); - /** - * @tlb_fill: Handle a softmmu tlb miss or user-only address fault - * - * For system mode, if the access is valid, call tlb_set_page - * and return true; if the access is invalid, and probe is - * true, return false; otherwise raise an exception and do - * not return. For user-only mode, always raise an exception - * and do not return. - */ - bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); /** @debug_excp_handler: Callback for handling debug exceptions */ void (*debug_excp_handler)(CPUState *cpu); @@ -72,6 +60,16 @@ struct TCGCPUOps { bool (*has_work)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** + * @tlb_fill: Handle a softmmu tlb miss + * + * If the access is valid, call tlb_set_page and return true; + * if the access is invalid and probe is true, return false; + * otherwise raise an exception and do not return. + */ + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); /** * @do_transaction_failed: Callback for handling failed memory transactions * (ie bus faults or external aborts; not MMU faults) diff --git a/linux-user/signal.c b/linux-user/signal.c index ae31b46be0..4f4c919b23 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -690,9 +690,6 @@ void raise_sigsegv(CPUState *cpu, target_ulong addr, if (tcg_ops->record_sigsegv) { tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); - } else if (tcg_ops->tlb_fill) { - tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, ra); - g_assert_not_reached(); } force_sig_fault(TARGET_SIGSEGV,