From patchwork Wed Sep 15 07:48:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 513275 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3D58C4332F for ; Wed, 15 Sep 2021 07:49:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9E72F60FC0 for ; Wed, 15 Sep 2021 07:49:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236687AbhIOHuU (ORCPT ); Wed, 15 Sep 2021 03:50:20 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:58937 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236674AbhIOHuL (ORCPT ); Wed, 15 Sep 2021 03:50:11 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1631692133; x=1663228133; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DrUrIkN919I36jDniIebt0/1keT56bFRv5l7cFRP50c=; b=CdK2PdLW8c7NpStNEhQa/2Ga2nIY14TzqviZu7K6rwuNllACywvJRxl9 SQUDw73MGyv7sEtI77sPOy5gct9lY0XCV/Nm19BbeCpIYYmZeoea+3ryH g1vejo3yJ/5zu3uesUTL4hpbP8F+jmmtap8/HrgzgnUezjPK6jQbPbufP /nYbeqreA8+ZsY+oOrAXJ/Yk+C9jJcRLqi5/ZcLHt0pvnD7i/dp0J7bso 7UbrtpKVgN2hB0uDYmoW4gcYUWhpkuJsVvRD2zprqVGfsW5ALjIDjulFb zZopEY3Re7pPzz6ykJuJ0FO00eGo1h13oLvAbnJ6v2LtVbS1oob+6lRBi g==; IronPort-SDR: hTqNy8gN3y3yGDih/uevQ8T9UegiWMz0bhkLV9JWstVcQIaoJg1gfHOj6SeQ+HQIWn4mJsPeJv emSVQI9hnO4o7R7tOvLC/AKf3BZq3KdZdeJT2Gw10jA95nZGHvsHmgiRu7DgOVLcB8z+df/kGm gE4vwjGbSA7L2VV+NawOjg9DumILCsUaz9ggPs6LEAqYJi+O8JooL8/cn58a3S0R7AsZK28EBf tX2k2njpCy3d0dRsaWvomEN6GxYZsNmDB5oTkxrfFwpW0X/Eaw1/GK685rYq2x/c0op5xdzJRF iA+IRzZadoUzbn605AvxD7ZO X-IronPort-AV: E=Sophos;i="5.85,294,1624345200"; d="scan'208";a="131883930" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 15 Sep 2021 00:48:52 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Wed, 15 Sep 2021 00:48:52 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Wed, 15 Sep 2021 00:48:50 -0700 From: Claudiu Beznea To: , , , CC: , , , Claudiu Beznea Subject: [PATCH 1/2] ARM: dts: at91: sama7g5ek: use proper slew-rate settings for GMACs Date: Wed, 15 Sep 2021 10:48:35 +0300 Message-ID: <20210915074836.6574-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210915074836.6574-1-claudiu.beznea@microchip.com> References: <20210915074836.6574-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Datasheet chapter "EMAC Timings" specifies that while in 3.3V domain GMAC's MDIO pins should be configured with slew-rate enabled, while the data + signaling pins should be configured with slew-rate disabled when GMAC works in RGMII or RMII modes. The pin controller for SAMA7G5 sets the slew-rate as enabled for all pins. Adapt the device tree to comply with these. Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/at91-sama7g5ek.dts | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts index 8b13b031a167..0bed8207d498 100644 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts @@ -353,7 +353,10 @@ &gmac0 { #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>; + pinctrl-0 = <&pinctrl_gmac0_default + &pinctrl_gmac0_mdio_default + &pinctrl_gmac0_txck_default + &pinctrl_gmac0_phy_irq>; phy-mode = "rgmii-id"; status = "okay"; @@ -368,7 +371,9 @@ &gmac1 { #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>; + pinctrl-0 = <&pinctrl_gmac1_default + &pinctrl_gmac1_mdio_default + &pinctrl_gmac1_phy_irq>; phy-mode = "rmii"; status = "okay"; @@ -423,14 +428,20 @@ pinctrl_gmac0_default: gmac0_default { , , , - , - , ; + slew-rate = <0>; + bias-disable; + }; + + pinctrl_gmac0_mdio_default: gmac0_mdio_default { + pinmux = , + ; bias-disable; }; pinctrl_gmac0_txck_default: gmac0_txck_default { pinmux = ; + slew-rate = <0>; bias-pull-up; }; @@ -447,8 +458,13 @@ pinctrl_gmac1_default: gmac1_default { , , , - , - , + ; + slew-rate = <0>; + bias-disable; + }; + + pinctrl_gmac1_mdio_default: gmac1_mdio_default { + pinmux = , ; bias-disable; }; From patchwork Wed Sep 15 07:48:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 513274 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29824C433FE for ; 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IronPort-SDR: 1BpRbL4QaNW4NAHdpfeyOpWDhIBjBEO0tem4jpljT2iaHgPsfBsBa9VZ8zQcSlgBpsHBTypOa+ PTjTFVn5QX9QckV9SRNrogiQtDFa937XzP88cOPOjZfxZ/JT0qbyAlu2cpqs+oSaTbEZBAl4P9 awOOpx0nye2SZOWGoJiiAI5SgDrlg8sn7AEa8mds0smW6AtSwFYpPsO+kp5dnKUxyPds5LHzY6 4KeYjvx8wVzI23gPeRfDgV+WGZqWD2xRxvLYDhx3SofdLLjiWqguBiI9wldK+Ds/yJoe4027cD MEYtZtZgJ9gA559sTO/4YKn2 X-IronPort-AV: E=Sophos;i="5.85,294,1624345200"; d="scan'208";a="136600228" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 15 Sep 2021 00:48:54 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Wed, 15 Sep 2021 00:48:54 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Wed, 15 Sep 2021 00:48:52 -0700 From: Claudiu Beznea To: , , , CC: , , , Claudiu Beznea Subject: [PATCH 2/2] ARM: dts: at91: sama7g5ek: to not touch slew-rate for SDMMC pins Date: Wed, 15 Sep 2021 10:48:36 +0300 Message-ID: <20210915074836.6574-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210915074836.6574-1-claudiu.beznea@microchip.com> References: <20210915074836.6574-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org With commit c709135e576b ("pinctrl: at91-pio4: add support for slew-rate") and commit cbde6c823bfa ("pinctrl: at91-pio4: Fix slew rate disablement") the slew-rate is enabled by default for each configured pin. The datasheet specifies at chapter "Output Driver AC Characteristics" that HSIO drivers (use in SDMMCx and QSPI0 peripherals), don't have a slewrate setting but are rather calibrated against an external 1% resistor mounted on the SDMMCx_CAL or QSPI0_CAL pins. Depending on the target signal frequency and the external load, it is possible to adjust their target output impedance. Thus set slew-rate = <0> for SDMMC (QSPI is not enabled at the moment in device tree). Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/at91-sama7g5ek.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts index 0bed8207d498..624162fec223 100644 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts @@ -556,6 +556,7 @@ cmd_data { , , ; + slew-rate = <0>; bias-pull-up; }; @@ -563,6 +564,7 @@ ck_cd_rstn_vddsel { pinmux = , , ; + slew-rate = <0>; bias-pull-up; }; }; @@ -574,6 +576,7 @@ cmd_data { , , ; + slew-rate = <0>; bias-pull-up; }; @@ -582,6 +585,7 @@ ck_cd_rstn_vddsel { , , ; + slew-rate = <0>; bias-pull-up; }; }; @@ -593,11 +597,13 @@ cmd_data { , , ; + slew-rate = <0>; bias-pull-up; }; ck { pinmux = ; + slew-rate = <0>; bias-pull-up; }; };