From patchwork Wed Sep 15 12:02:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 512406 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE3C8C433F5 for ; Wed, 15 Sep 2021 12:03:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D19576128B for ; Wed, 15 Sep 2021 12:03:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237675AbhIOMET (ORCPT ); Wed, 15 Sep 2021 08:04:19 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:55142 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237623AbhIOMEO (ORCPT ); Wed, 15 Sep 2021 08:04:14 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 18FC2ofe085397; Wed, 15 Sep 2021 07:02:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1631707370; bh=zJ/G+uhDKnKmBBBqmYU+RVWsZ4psvl76j+mA50Q1hn4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SfRBDjtL47GoCRgRMD1wy/5we2Fz4K6DaNrxpcXDS439lW5vqg1Yddz5/t8jliRW8 OuVgbSD93+KhAJjGj5Dv5kR5CauztAYSgV+Rd08XkNBsDBNON5yizVHhPejJwW1bdJ g+hJfANMSZW7MdjXjN/NEkIrobLLY3IK2Yl1bHlI= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 18FC2ovX068123 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 15 Sep 2021 07:02:50 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Wed, 15 Sep 2021 07:02:49 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 15 Sep 2021 07:02:49 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 18FC2fD2019246; Wed, 15 Sep 2021 07:02:46 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab CC: Pratyush Yadav , Laurent Pinchart , Nikhil Devshatwar , Tomi Valkeinen , Vignesh Raghavendra , Benoit Parrot , Maxime Ripard , Rob Herring , Sakari Ailus , =?utf-8?q?Niklas_S=C3=B6derlund?= , , , Subject: [PATCH v4 01/11] media: cadence: csi2rx: Unregister v4l2 async notifier Date: Wed, 15 Sep 2021 17:32:30 +0530 Message-ID: <20210915120240.21572-2-p.yadav@ti.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210915120240.21572-1-p.yadav@ti.com> References: <20210915120240.21572-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The notifier is added to the global notifier list when registered. When the module is removed, the struct csi2rx_priv in which the notifier is embedded, is destroyed. As a result the notifier list has a reference to a notifier that no longer exists. This causes invalid memory accesses when the list is iterated over. Similar for when the probe fails. Unregister and clean up the notifier to avoid this. Fixes: 1fc3b37f34f6 ("media: v4l: cadence: Add Cadence MIPI-CSI2 RX driver") Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart --- (no changes since v3) Changes in v3: - New in v3. drivers/media/platform/cadence/cdns-csi2rx.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index 7b44ab2b8c9a..d60975f905d6 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -469,6 +469,7 @@ static int csi2rx_probe(struct platform_device *pdev) return 0; err_cleanup: + v4l2_async_nf_unregister(&csi2rx->notifier); v4l2_async_nf_cleanup(&csi2rx->notifier); err_free_priv: kfree(csi2rx); @@ -479,6 +480,8 @@ static int csi2rx_remove(struct platform_device *pdev) { struct csi2rx_priv *csi2rx = platform_get_drvdata(pdev); + v4l2_async_nf_unregister(&csi2rx->notifier); + v4l2_async_nf_cleanup(&csi2rx->notifier); v4l2_async_unregister_subdev(&csi2rx->subdev); kfree(csi2rx); From patchwork Wed Sep 15 12:02:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 513266 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6386C4332F for ; Wed, 15 Sep 2021 12:03:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8963561357 for ; Wed, 15 Sep 2021 12:03:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237680AbhIOMEU (ORCPT ); Wed, 15 Sep 2021 08:04:20 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:55154 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237651AbhIOMER (ORCPT ); Wed, 15 Sep 2021 08:04:17 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 18FC2sp5085408; Wed, 15 Sep 2021 07:02:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1631707374; bh=l3ZcaCZppqvViDJsA+qmLFC+hXXiwwkwwQuFXOjal3k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZiAeYJ7P6l/HL8h+nF2AGweHXZh6cB0ekQJiHAKmyRWJC6MWBQsIc8nU37YlK1sx+ otus1uTI4o06voeUyvDfU0UISO9s3uamTuE3uDZHtK6KQHkqLkMHZJbwH0k+AxwMY1 X0qwde6bMauQGJ4nBOIy/CdmKmrVjgg2+e9/6rVQ= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 18FC2skP120079 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 15 Sep 2021 07:02:54 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Wed, 15 Sep 2021 07:02:53 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 15 Sep 2021 07:02:53 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 18FC2fD3019246; Wed, 15 Sep 2021 07:02:50 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab CC: Pratyush Yadav , Laurent Pinchart , Nikhil Devshatwar , Tomi Valkeinen , Vignesh Raghavendra , Benoit Parrot , Maxime Ripard , Rob Herring , Sakari Ailus , =?utf-8?q?Niklas_S=C3=B6derlund?= , , , Subject: [PATCH v4 02/11] media: cadence: csi2rx: Add external DPHY support Date: Wed, 15 Sep 2021 17:32:31 +0530 Message-ID: <20210915120240.21572-3-p.yadav@ti.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210915120240.21572-1-p.yadav@ti.com> References: <20210915120240.21572-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some platforms like TI's J721E can have the CSI2RX paired with an external DPHY. Add support to enable and configure the DPHY using the generic PHY framework. Get the pixel rate and bpp from the subdev and pass them on to the DPHY along with the number of lanes. All other settings are left to their default values. Signed-off-by: Pratyush Yadav --- Changes in v4: - Drop the call to set PHY submode. It is now being done via compatible on the DPHY side. Changes in v3: - Use v4l2_get_link_freq() to calculate pixel clock. Changes in v2: - Use phy_pm_runtime_get_sync() and phy_pm_runtime_put() before making calls to set PHY mode, etc. to make sure it is ready. drivers/media/platform/cadence/cdns-csi2rx.c | 143 +++++++++++++++++-- 1 file changed, 133 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index d60975f905d6..c06e039a1aa8 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -30,6 +30,12 @@ #define CSI2RX_STATIC_CFG_DLANE_MAP(llane, plane) ((plane) << (16 + (llane) * 4)) #define CSI2RX_STATIC_CFG_LANES_MASK GENMASK(11, 8) +#define CSI2RX_DPHY_LANE_CTRL_REG 0x40 +#define CSI2RX_DPHY_CL_RST BIT(16) +#define CSI2RX_DPHY_DL_RST(i) BIT((i) + 12) +#define CSI2RX_DPHY_CL_EN BIT(4) +#define CSI2RX_DPHY_DL_EN(i) BIT(i) + #define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100) #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) @@ -54,6 +60,11 @@ enum csi2rx_pads { CSI2RX_PAD_MAX, }; +struct csi2rx_fmt { + u32 code; + u8 bpp; +}; + struct csi2rx_priv { struct device *dev; unsigned int count; @@ -85,6 +96,37 @@ struct csi2rx_priv { int source_pad; }; +static const struct csi2rx_fmt formats[] = { + { + .code = MEDIA_BUS_FMT_YUYV8_2X8, + .bpp = 16, + }, + { + .code = MEDIA_BUS_FMT_UYVY8_2X8, + .bpp = 16, + }, + { + .code = MEDIA_BUS_FMT_YVYU8_2X8, + .bpp = 16, + }, + { + .code = MEDIA_BUS_FMT_VYUY8_2X8, + .bpp = 16, + }, +}; + +static u8 csi2rx_get_bpp(u32 code) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(formats); i++) { + if (formats[i].code == code) + return formats[i].bpp; + } + + return 0; +} + static inline struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev) { @@ -101,6 +143,66 @@ static void csi2rx_reset(struct csi2rx_priv *csi2rx) writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); } +static int csi2rx_configure_external_dphy(struct csi2rx_priv *csi2rx) +{ + union phy_configure_opts opts = { }; + struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy; + struct v4l2_subdev_format sd_fmt; + s64 pixel_clock; + int ret; + u8 bpp; + bool got_pm = true; + + sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; + sd_fmt.pad = 0; + + ret = v4l2_subdev_call(csi2rx->source_subdev, pad, get_fmt, NULL, + &sd_fmt); + if (ret) + return ret; + + bpp = csi2rx_get_bpp(sd_fmt.format.code); + if (!bpp) + return -EINVAL; + + /* + * Do not divide by the number of lanes here. That will be done by + * phy_mipi_dphy_get_default_config(). + */ + pixel_clock = v4l2_get_link_freq(csi2rx->source_subdev->ctrl_handler, + 1, 2); + if (pixel_clock < 0) + return pixel_clock; + + ret = phy_mipi_dphy_get_default_config(pixel_clock, bpp, + csi2rx->num_lanes, cfg); + if (ret) + return ret; + + ret = phy_pm_runtime_get_sync(csi2rx->dphy); + if (ret == -ENOTSUPP) + got_pm = false; + else if (ret) + return ret; + + ret = phy_power_on(csi2rx->dphy); + if (ret) + goto out; + + ret = phy_configure(csi2rx->dphy, &opts); + if (ret) { + /* Can't do anything if it fails. Ignore the return value. */ + phy_power_off(csi2rx->dphy); + goto out; + } + +out: + if (got_pm) + phy_pm_runtime_put(csi2rx->dphy); + + return ret; +} + static int csi2rx_start(struct csi2rx_priv *csi2rx) { unsigned int i; @@ -139,6 +241,17 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) if (ret) goto err_disable_pclk; + /* Enable DPHY clk and data lanes. */ + if (csi2rx->dphy) { + reg = CSI2RX_DPHY_CL_EN | CSI2RX_DPHY_CL_RST; + for (i = 0; i < csi2rx->num_lanes; i++) { + reg |= CSI2RX_DPHY_DL_EN(csi2rx->lanes[i] - 1); + reg |= CSI2RX_DPHY_DL_RST(csi2rx->lanes[i] - 1); + } + + writel(reg, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); + } + /* * Create a static mapping between the CSI virtual channels * and the output stream. @@ -169,10 +282,21 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) if (ret) goto err_disable_pixclk; + if (csi2rx->dphy) { + ret = csi2rx_configure_external_dphy(csi2rx); + if (ret) { + dev_err(csi2rx->dev, + "Failed to configure external DPHY: %d\n", ret); + goto err_disable_sysclk; + } + } + clk_disable_unprepare(csi2rx->p_clk); return 0; +err_disable_sysclk: + clk_disable_unprepare(csi2rx->sys_clk); err_disable_pixclk: for (; i > 0; i--) clk_disable_unprepare(csi2rx->pixel_clk[i - 1]); @@ -200,6 +324,13 @@ static void csi2rx_stop(struct csi2rx_priv *csi2rx) if (v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, false)) dev_warn(csi2rx->dev, "Couldn't disable our subdev\n"); + + if (csi2rx->dphy) { + writel(0, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); + + if (phy_power_off(csi2rx->dphy)) + dev_warn(csi2rx->dev, "Couldn't power off DPHY\n"); + } } static int csi2rx_s_stream(struct v4l2_subdev *subdev, int enable) @@ -307,15 +438,6 @@ static int csi2rx_get_resources(struct csi2rx_priv *csi2rx, return PTR_ERR(csi2rx->dphy); } - /* - * FIXME: Once we'll have external D-PHY support, the check - * will need to be removed. - */ - if (csi2rx->dphy) { - dev_err(&pdev->dev, "External D-PHY not supported yet\n"); - return -EINVAL; - } - ret = clk_prepare_enable(csi2rx->p_clk); if (ret) { dev_err(&pdev->dev, "Couldn't prepare and enable P clock\n"); @@ -345,7 +467,7 @@ static int csi2rx_get_resources(struct csi2rx_priv *csi2rx, * FIXME: Once we'll have internal D-PHY support, the check * will need to be removed. */ - if (csi2rx->has_internal_dphy) { + if (!csi2rx->dphy && csi2rx->has_internal_dphy) { dev_err(&pdev->dev, "Internal D-PHY not supported yet\n"); return -EINVAL; } @@ -464,6 +586,7 @@ static int csi2rx_probe(struct platform_device *pdev) dev_info(&pdev->dev, "Probed CSI2RX with %u/%u lanes, %u streams, %s D-PHY\n", csi2rx->num_lanes, csi2rx->max_lanes, csi2rx->max_streams, + csi2rx->dphy ? "external" : csi2rx->has_internal_dphy ? "internal" : "no"); return 0; From patchwork Wed Sep 15 12:02:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 512405 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C578CC433FE for ; Wed, 15 Sep 2021 12:03:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B30CC6135F for ; Wed, 15 Sep 2021 12:03:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237707AbhIOMEW (ORCPT ); Wed, 15 Sep 2021 08:04:22 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:46650 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237623AbhIOMEV (ORCPT ); Wed, 15 Sep 2021 08:04:21 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 18FC2w3C066363; Wed, 15 Sep 2021 07:02:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1631707378; bh=F2b9rMetRvmE4f/oZbkFR/Hv9TZEmqltYgboOVvrHGU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=sA7bFm+NCUxBs2mKGZE17qsx0lU6kWiqvy2x2pTM8MtDSHGulryqJ3TXFKai4WcH+ wmWtKRqMdbN4YYnO/f/eYycXGAvSWJoNWkZrc5139KjmXb2zXkkyzB/9g1DM3iU0vT D3ZkB7c+gcSojQQPHpWjiFjpdY8Bi3WBp7PE2sLM= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 18FC2wQi048334 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 15 Sep 2021 07:02:58 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Wed, 15 Sep 2021 07:02:58 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 15 Sep 2021 07:02:57 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 18FC2fD4019246; Wed, 15 Sep 2021 07:02:54 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab CC: Pratyush Yadav , Laurent Pinchart , Nikhil Devshatwar , Tomi Valkeinen , Vignesh Raghavendra , Benoit Parrot , Maxime Ripard , Rob Herring , Sakari Ailus , =?utf-8?q?Niklas_S=C3=B6derlund?= , , , Subject: [PATCH v4 03/11] media: cadence: csi2rx: Soft reset the streams before starting capture Date: Wed, 15 Sep 2021 17:32:32 +0530 Message-ID: <20210915120240.21572-4-p.yadav@ti.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210915120240.21572-1-p.yadav@ti.com> References: <20210915120240.21572-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This resets the stream state machines and FIFOs, giving them a clean slate. On J721E if the streams are not reset before starting the capture, the captured frame gets wrapped around vertically on every run after the first. Signed-off-by: Pratyush Yadav --- (no changes since v1) drivers/media/platform/cadence/cdns-csi2rx.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index c06e039a1aa8..e05d76394cd6 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -39,6 +39,7 @@ #define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100) #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) +#define CSI2RX_STREAM_CTRL_SOFT_RST BIT(4) #define CSI2RX_STREAM_CTRL_START BIT(0) #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) @@ -135,12 +136,22 @@ struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev) static void csi2rx_reset(struct csi2rx_priv *csi2rx) { + int i; + writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT, csi2rx->base + CSI2RX_SOFT_RESET_REG); udelay(10); writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); + + /* Reset individual streams. */ + for (i = 0; i < csi2rx->max_streams; i++) { + writel(CSI2RX_STREAM_CTRL_SOFT_RST, + csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + usleep_range(10, 20); + writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + } } static int csi2rx_configure_external_dphy(struct csi2rx_priv *csi2rx) From patchwork Wed Sep 15 12:02:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 513265 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C46B1C433EF for ; Wed, 15 Sep 2021 12:03:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AEA8361247 for ; Wed, 15 Sep 2021 12:03:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237390AbhIOMEc (ORCPT ); Wed, 15 Sep 2021 08:04:32 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:46670 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237623AbhIOMEZ (ORCPT ); Wed, 15 Sep 2021 08:04:25 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 18FC33AP066401; Wed, 15 Sep 2021 07:03:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1631707383; bh=Rcjrh9xOmMchJURusioQgCOfJy0HVk9mnr1C8fCqldI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=razq60FeYEqOworD9v6UQ8H/kzFqnwHtUFuITKdxy9tQcvoj4lkIFufutXLLxgn7S C0hY5iY1eGU43KZ325HysQZTewnjUO2vhlzoWEHb3VGGqauHeJ1vrL6tqwa0JSyNoS H4EmGp/mVA37DOamchTiRx7dtP4ueseWKm1AwlYY= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 18FC32BZ120210 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 15 Sep 2021 07:03:03 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Wed, 15 Sep 2021 07:03:02 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 15 Sep 2021 07:03:01 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 18FC2fD5019246; Wed, 15 Sep 2021 07:02:58 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab CC: Pratyush Yadav , Laurent Pinchart , Nikhil Devshatwar , Tomi Valkeinen , Vignesh Raghavendra , Benoit Parrot , Maxime Ripard , Rob Herring , Sakari Ailus , =?utf-8?q?Niklas_S=C3=B6derlund?= , , , Subject: [PATCH v4 04/11] media: cadence: csi2rx: Set the STOP bit when stopping a stream Date: Wed, 15 Sep 2021 17:32:33 +0530 Message-ID: <20210915120240.21572-5-p.yadav@ti.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210915120240.21572-1-p.yadav@ti.com> References: <20210915120240.21572-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The stream stop procedure says that the STOP bit should be set when the stream is to be stopped, and then the ready bit in stream status register polled to make sure the STOP operation is finished. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart --- (no changes since v1) drivers/media/platform/cadence/cdns-csi2rx.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index e05d76394cd6..3730e8beee48 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -40,8 +41,12 @@ #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) #define CSI2RX_STREAM_CTRL_SOFT_RST BIT(4) +#define CSI2RX_STREAM_CTRL_STOP BIT(1) #define CSI2RX_STREAM_CTRL_START BIT(0) +#define CSI2RX_STREAM_STATUS_REG(n) (CSI2RX_STREAM_BASE(n) + 0x004) +#define CSI2RX_STREAM_STATUS_RDY BIT(31) + #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) #define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT BIT(31) #define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n) BIT((n) + 16) @@ -321,12 +326,23 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) static void csi2rx_stop(struct csi2rx_priv *csi2rx) { unsigned int i; + u32 val; + int ret; clk_prepare_enable(csi2rx->p_clk); clk_disable_unprepare(csi2rx->sys_clk); for (i = 0; i < csi2rx->max_streams; i++) { - writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + writel(CSI2RX_STREAM_CTRL_STOP, + csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + + ret = readl_relaxed_poll_timeout(csi2rx->base + + CSI2RX_STREAM_STATUS_REG(i), + val, + (val & CSI2RX_STREAM_STATUS_RDY), + 10, 10000); + if (ret) + dev_warn(csi2rx->dev, "Failed to stop stream%d\n", i); clk_disable_unprepare(csi2rx->pixel_clk[i]); } From patchwork Wed Sep 15 12:02:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 512403 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0798FC433F5 for ; Wed, 15 Sep 2021 12:03:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E638B61353 for ; Wed, 15 Sep 2021 12:03:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237792AbhIOMEh (ORCPT ); Wed, 15 Sep 2021 08:04:37 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:55208 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237741AbhIOMEe (ORCPT ); Wed, 15 Sep 2021 08:04:34 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 18FC36p1085464; Wed, 15 Sep 2021 07:03:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1631707386; bh=1EbfquFBKlFE7F+bpSOI+/LXMEkFHo8R0YoztebJ0/Q=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TAgSH8GD9LQDejUi3BP3R7/fPQc8anW1UMdZSt6Lts034I//C38B84GMcsxEYEyUM FdEWL31uVkQP+OqK5MYwYcGt8Bphhdgm6nx4zi8SCJMaPUInF135g6OxAGq1Vibil0 HcjFsxPcy1LpNgAiqWDC9Z98vGBmnI94rrpkEUIo= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 18FC36Br121053 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 15 Sep 2021 07:03:06 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Wed, 15 Sep 2021 07:03:06 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 15 Sep 2021 07:03:06 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 18FC2fD6019246; Wed, 15 Sep 2021 07:03:02 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab CC: Pratyush Yadav , Laurent Pinchart , Nikhil Devshatwar , Tomi Valkeinen , Vignesh Raghavendra , Benoit Parrot , Maxime Ripard , Rob Herring , Sakari Ailus , =?utf-8?q?Niklas_S=C3=B6derlund?= , , , Subject: [PATCH v4 05/11] media: cadence: csi2rx: Fix stream data configuration Date: Wed, 15 Sep 2021 17:32:34 +0530 Message-ID: <20210915120240.21572-6-p.yadav@ti.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210915120240.21572-1-p.yadav@ti.com> References: <20210915120240.21572-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Firstly, there is no VC_EN bit present in the STREAM_DATA_CFG register. Bit 31 is part of the VL_SELECT field. Remove it completely. Secondly, it makes little sense to enable ith virtual channel for ith stream. Sure, there might be a use-case that demands it. But there might also be a use case that demands all streams to use the 0th virtual channel. Prefer this case over the former because it is less arbitrary and also makes it very clear what the limitations of the current driver is instead of giving a false impression that multiple virtual channels are supported. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart --- (no changes since v1) drivers/media/platform/cadence/cdns-csi2rx.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index 3730e8beee48..edd56c5f2e89 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -48,7 +48,6 @@ #define CSI2RX_STREAM_STATUS_RDY BIT(31) #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) -#define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT BIT(31) #define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n) BIT((n) + 16) #define CSI2RX_STREAM_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x00c) @@ -286,8 +285,11 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF, csi2rx->base + CSI2RX_STREAM_CFG_REG(i)); - writel(CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT | - CSI2RX_STREAM_DATA_CFG_VC_SELECT(i), + /* + * Enable one virtual channel. When multiple virtual channels + * are supported this will have to be changed. + */ + writel(CSI2RX_STREAM_DATA_CFG_VC_SELECT(0), csi2rx->base + CSI2RX_STREAM_DATA_CFG_REG(i)); writel(CSI2RX_STREAM_CTRL_START, From patchwork Wed Sep 15 12:02:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 513264 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0234CC4332F for ; Wed, 15 Sep 2021 12:03:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E1DB561355 for ; Wed, 15 Sep 2021 12:03:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237785AbhIOMEf (ORCPT ); Wed, 15 Sep 2021 08:04:35 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:55202 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237772AbhIOMEd (ORCPT ); Wed, 15 Sep 2021 08:04:33 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 18FC3AlY085483; Wed, 15 Sep 2021 07:03:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1631707390; bh=kT+jpdgHUgB8WmXpX4IK0Fq/UD51pryiZLI1p3AwL4s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pq/klfE0Nviq3z3e3+xMhqSQ+Gdx0kdUI/1WICeXTkUTGPUC8BTpEC1CjuSkTqYLz nzZuyVLcfsGLnOKJ9PgpOyzBFB9ob7f06GhFKOK7ra4JtLk/k66GRMgykyFSNGDkGt JUPuE/jDmA24jpXWNzJXuvr19+P+npWox8Qyjeso= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 18FC3AhA048962 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 15 Sep 2021 07:03:10 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Wed, 15 Sep 2021 07:03:10 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 15 Sep 2021 07:03:10 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 18FC2fD7019246; Wed, 15 Sep 2021 07:03:06 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab CC: Pratyush Yadav , Laurent Pinchart , Nikhil Devshatwar , Tomi Valkeinen , Vignesh Raghavendra , Benoit Parrot , Maxime Ripard , Rob Herring , Sakari Ailus , =?utf-8?q?Niklas_S=C3=B6derlund?= , , , Subject: [PATCH v4 06/11] media: cadence: csi2rx: Populate subdev devnode Date: Wed, 15 Sep 2021 17:32:35 +0530 Message-ID: <20210915120240.21572-7-p.yadav@ti.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210915120240.21572-1-p.yadav@ti.com> References: <20210915120240.21572-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The devnode can be used by media-ctl and other userspace tools to perform configurations on the subdev. Without it, media-ctl returns ENOENT when setting format on the sensor subdev. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart --- (no changes since v2) Changes in v2: - New in v2. drivers/media/platform/cadence/cdns-csi2rx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index edd56c5f2e89..7c3183069db0 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -602,6 +602,7 @@ static int csi2rx_probe(struct platform_device *pdev) csi2rx->pads[CSI2RX_PAD_SINK].flags = MEDIA_PAD_FL_SINK; for (i = CSI2RX_PAD_SOURCE_STREAM0; i < CSI2RX_PAD_MAX; i++) csi2rx->pads[i].flags = MEDIA_PAD_FL_SOURCE; + csi2rx->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; ret = media_entity_pads_init(&csi2rx->subdev.entity, CSI2RX_PAD_MAX, csi2rx->pads); From patchwork Wed Sep 15 12:02:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 513263 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5381BC433EF for ; Wed, 15 Sep 2021 12:03:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 40E8361247 for ; Wed, 15 Sep 2021 12:03:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232906AbhIOMEp (ORCPT ); Wed, 15 Sep 2021 08:04:45 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:55216 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237735AbhIOMEh (ORCPT ); Wed, 15 Sep 2021 08:04:37 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 18FC3Eh4085502; Wed, 15 Sep 2021 07:03:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1631707394; bh=qGqqKeOzBHe5XEzH1nw3griRZuYm6K1QDfOlq3ycjxA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=AGoAeWRqjm0EVDMFUedVtFm+ugWyUgYbgo8+l4ADnhPB1i9E8HPw0Mjr3at/rmvaq 3fUhXF04iY6vs4eYRe8JCNW0L2Wo/diaBHkd5uuFuLVomlF7UXwvgti0n+rkmQEscm kFNS5iLFmt7FYA2ilryxotAW21ShUNqJ2RQCRbdk= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 18FC3E3v100222 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 15 Sep 2021 07:03:14 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Wed, 15 Sep 2021 07:03:14 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 15 Sep 2021 07:03:14 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 18FC2fD8019246; Wed, 15 Sep 2021 07:03:10 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab CC: Pratyush Yadav , Laurent Pinchart , Nikhil Devshatwar , Tomi Valkeinen , Vignesh Raghavendra , Benoit Parrot , Maxime Ripard , Rob Herring , Sakari Ailus , =?utf-8?q?Niklas_S=C3=B6derlund?= , , , Subject: [PATCH v4 07/11] media: Re-structure TI platform drivers Date: Wed, 15 Sep 2021 17:32:36 +0530 Message-ID: <20210915120240.21572-8-p.yadav@ti.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210915120240.21572-1-p.yadav@ti.com> References: <20210915120240.21572-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ti-vpe/ sub-directory does not only contain the VPE-specific things. It also contains the CAL driver, which is a completely different subsystem. This is also not a good place to add new drivers for other TI platforms since they will all get mixed up. Separate the VPE and CAL parts into different sub-directories and rename the ti-vpe/ sub-directory to ti/. This is now the place where new TI platform drivers can be added. Signed-off-by: Pratyush Yadav Reviewed-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart --- Compile tested only. There should be no functional change. (no changes since v3) Changes in v3: - Add Tomi's R-by. Changes in v2: - New in v2. MAINTAINERS | 3 ++- drivers/media/platform/Makefile | 2 +- drivers/media/platform/ti/Makefile | 3 +++ drivers/media/platform/ti/cal/Makefile | 3 +++ drivers/media/platform/{ti-vpe => ti/cal}/cal-camerarx.c | 0 drivers/media/platform/{ti-vpe => ti/cal}/cal-video.c | 0 drivers/media/platform/{ti-vpe => ti/cal}/cal.c | 0 drivers/media/platform/{ti-vpe => ti/cal}/cal.h | 0 drivers/media/platform/{ti-vpe => ti/cal}/cal_regs.h | 0 drivers/media/platform/{ti-vpe => ti/vpe}/Makefile | 4 ---- drivers/media/platform/{ti-vpe => ti/vpe}/csc.c | 0 drivers/media/platform/{ti-vpe => ti/vpe}/csc.h | 0 drivers/media/platform/{ti-vpe => ti/vpe}/sc.c | 0 drivers/media/platform/{ti-vpe => ti/vpe}/sc.h | 0 drivers/media/platform/{ti-vpe => ti/vpe}/sc_coeff.h | 0 drivers/media/platform/{ti-vpe => ti/vpe}/vpdma.c | 0 drivers/media/platform/{ti-vpe => ti/vpe}/vpdma.h | 0 drivers/media/platform/{ti-vpe => ti/vpe}/vpdma_priv.h | 0 drivers/media/platform/{ti-vpe => ti/vpe}/vpe.c | 0 drivers/media/platform/{ti-vpe => ti/vpe}/vpe_regs.h | 0 20 files changed, 9 insertions(+), 6 deletions(-) create mode 100644 drivers/media/platform/ti/Makefile create mode 100644 drivers/media/platform/ti/cal/Makefile rename drivers/media/platform/{ti-vpe => ti/cal}/cal-camerarx.c (100%) rename drivers/media/platform/{ti-vpe => ti/cal}/cal-video.c (100%) rename drivers/media/platform/{ti-vpe => ti/cal}/cal.c (100%) rename drivers/media/platform/{ti-vpe => ti/cal}/cal.h (100%) rename drivers/media/platform/{ti-vpe => ti/cal}/cal_regs.h (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/Makefile (78%) rename drivers/media/platform/{ti-vpe => ti/vpe}/csc.c (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/csc.h (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/sc.c (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/sc.h (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/sc_coeff.h (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/vpdma.c (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/vpdma.h (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/vpdma_priv.h (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/vpe.c (100%) rename drivers/media/platform/{ti-vpe => ti/vpe}/vpe_regs.h (100%) diff --git a/MAINTAINERS b/MAINTAINERS index cad1289793db..62bc4a949ae1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18829,7 +18829,8 @@ W: http://linuxtv.org/ Q: http://patchwork.linuxtv.org/project/linux-media/list/ F: Documentation/devicetree/bindings/media/ti,cal.yaml F: Documentation/devicetree/bindings/media/ti,vpe.yaml -F: drivers/media/platform/ti-vpe/ +F: drivers/media/platform/ti/cal/ +F: drivers/media/platform/ti/vpe/ TI WILINK WIRELESS DRIVERS L: linux-wireless@vger.kernel.org diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index 73ce083c2fc6..26d15b377a79 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -15,7 +15,7 @@ obj-$(CONFIG_VIDEO_PXA27x) += pxa_camera.o obj-$(CONFIG_VIDEO_VIU) += fsl-viu.o -obj-y += ti-vpe/ +obj-y += ti/ obj-$(CONFIG_VIDEO_MX2_EMMAPRP) += mx2_emmaprp.o obj-$(CONFIG_VIDEO_CODA) += coda/ diff --git a/drivers/media/platform/ti/Makefile b/drivers/media/platform/ti/Makefile new file mode 100644 index 000000000000..bbc737ccbbea --- /dev/null +++ b/drivers/media/platform/ti/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-y += cal/ +obj-y += vpe/ diff --git a/drivers/media/platform/ti/cal/Makefile b/drivers/media/platform/ti/cal/Makefile new file mode 100644 index 000000000000..45ac35585f0b --- /dev/null +++ b/drivers/media/platform/ti/cal/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_VIDEO_TI_CAL) += ti-cal.o +ti-cal-y := cal.o cal-camerarx.o cal-video.o diff --git a/drivers/media/platform/ti-vpe/cal-camerarx.c b/drivers/media/platform/ti/cal/cal-camerarx.c similarity index 100% rename from drivers/media/platform/ti-vpe/cal-camerarx.c rename to drivers/media/platform/ti/cal/cal-camerarx.c diff --git a/drivers/media/platform/ti-vpe/cal-video.c b/drivers/media/platform/ti/cal/cal-video.c similarity index 100% rename from drivers/media/platform/ti-vpe/cal-video.c rename to drivers/media/platform/ti/cal/cal-video.c diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti/cal/cal.c similarity index 100% rename from drivers/media/platform/ti-vpe/cal.c rename to drivers/media/platform/ti/cal/cal.c diff --git a/drivers/media/platform/ti-vpe/cal.h b/drivers/media/platform/ti/cal/cal.h similarity index 100% rename from drivers/media/platform/ti-vpe/cal.h rename to drivers/media/platform/ti/cal/cal.h diff --git a/drivers/media/platform/ti-vpe/cal_regs.h b/drivers/media/platform/ti/cal/cal_regs.h similarity index 100% rename from drivers/media/platform/ti-vpe/cal_regs.h rename to drivers/media/platform/ti/cal/cal_regs.h diff --git a/drivers/media/platform/ti-vpe/Makefile b/drivers/media/platform/ti/vpe/Makefile similarity index 78% rename from drivers/media/platform/ti-vpe/Makefile rename to drivers/media/platform/ti/vpe/Makefile index ad624056e039..3fadfe084f87 100644 --- a/drivers/media/platform/ti-vpe/Makefile +++ b/drivers/media/platform/ti/vpe/Makefile @@ -10,7 +10,3 @@ ti-sc-y := sc.o ti-csc-y := csc.o ccflags-$(CONFIG_VIDEO_TI_VPE_DEBUG) += -DDEBUG - -obj-$(CONFIG_VIDEO_TI_CAL) += ti-cal.o - -ti-cal-y := cal.o cal-camerarx.o cal-video.o diff --git a/drivers/media/platform/ti-vpe/csc.c b/drivers/media/platform/ti/vpe/csc.c similarity index 100% rename from drivers/media/platform/ti-vpe/csc.c rename to drivers/media/platform/ti/vpe/csc.c diff --git a/drivers/media/platform/ti-vpe/csc.h b/drivers/media/platform/ti/vpe/csc.h similarity index 100% rename from drivers/media/platform/ti-vpe/csc.h rename to drivers/media/platform/ti/vpe/csc.h diff --git a/drivers/media/platform/ti-vpe/sc.c b/drivers/media/platform/ti/vpe/sc.c similarity index 100% rename from drivers/media/platform/ti-vpe/sc.c rename to drivers/media/platform/ti/vpe/sc.c diff --git a/drivers/media/platform/ti-vpe/sc.h b/drivers/media/platform/ti/vpe/sc.h similarity index 100% rename from drivers/media/platform/ti-vpe/sc.h rename to drivers/media/platform/ti/vpe/sc.h diff --git a/drivers/media/platform/ti-vpe/sc_coeff.h b/drivers/media/platform/ti/vpe/sc_coeff.h similarity index 100% rename from drivers/media/platform/ti-vpe/sc_coeff.h rename to drivers/media/platform/ti/vpe/sc_coeff.h diff --git a/drivers/media/platform/ti-vpe/vpdma.c b/drivers/media/platform/ti/vpe/vpdma.c similarity index 100% rename from drivers/media/platform/ti-vpe/vpdma.c rename to drivers/media/platform/ti/vpe/vpdma.c diff --git a/drivers/media/platform/ti-vpe/vpdma.h b/drivers/media/platform/ti/vpe/vpdma.h similarity index 100% rename from drivers/media/platform/ti-vpe/vpdma.h rename to drivers/media/platform/ti/vpe/vpdma.h diff --git a/drivers/media/platform/ti-vpe/vpdma_priv.h b/drivers/media/platform/ti/vpe/vpdma_priv.h similarity index 100% rename from drivers/media/platform/ti-vpe/vpdma_priv.h rename to drivers/media/platform/ti/vpe/vpdma_priv.h diff --git a/drivers/media/platform/ti-vpe/vpe.c b/drivers/media/platform/ti/vpe/vpe.c similarity index 100% rename from drivers/media/platform/ti-vpe/vpe.c rename to drivers/media/platform/ti/vpe/vpe.c diff --git a/drivers/media/platform/ti-vpe/vpe_regs.h b/drivers/media/platform/ti/vpe/vpe_regs.h similarity index 100% rename from drivers/media/platform/ti-vpe/vpe_regs.h rename to drivers/media/platform/ti/vpe/vpe_regs.h From patchwork Wed Sep 15 12:02:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 512402 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38533C433F5 for ; Wed, 15 Sep 2021 12:03:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 239566128B for ; Wed, 15 Sep 2021 12:03:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237816AbhIOMEs (ORCPT ); Wed, 15 Sep 2021 08:04:48 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:55230 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237834AbhIOMEm (ORCPT ); Wed, 15 Sep 2021 08:04:42 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 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(version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 15 Sep 2021 07:03:18 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 18FC2fD9019246; Wed, 15 Sep 2021 07:03:14 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab CC: Pratyush Yadav , Laurent Pinchart , Nikhil Devshatwar , Tomi Valkeinen , Vignesh Raghavendra , Benoit Parrot , Maxime Ripard , Rob Herring , Sakari Ailus , =?utf-8?q?Niklas_S=C3=B6derlund?= , , , Subject: [PATCH v4 08/11] media: ti: Add CSI2RX support for J721E Date: Wed, 15 Sep 2021 17:32:37 +0530 Message-ID: <20210915120240.21572-9-p.yadav@ti.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210915120240.21572-1-p.yadav@ti.com> References: <20210915120240.21572-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate capture over a CSI-2 bus. The Cadence CSI2RX IP acts as a bridge between the TI specific parts and the CSI-2 protocol parts. TI then has a wrapper on top of this bridge called the SHIM layer. It takes in data from stream 0, repacks it, and sends it to memory over PSI-L DMA. This driver acts as the "front end" to V4L2 client applications. It implements the required ioctls and buffer operations, passes the necessary calls on to the bridge, programs the SHIM layer, and performs DMA via the dmaengine API to finally return the data to a buffer supplied by the application. Signed-off-by: Pratyush Yadav --- Changes in v4: - Acquire the media device's graph_mutex before starting the graph walk. - Call media_graph_walk_init() and media_graph_walk_cleanup() when starting and ending the graph walk respectively. - Reduce max frame height and width in enum_framesizes. Currently they are set to UINT_MAX but they must be a multiple of step_width, so they need to be rounded down. Also, these values are absurdly large which causes some userspace applications like gstreamer to trip up. While it is not generally right to change the kernel for an application bug, it is not such a big deal here. This change is replacing one set of absurdly large arbitrary values with another set of smaller but still absurdly large arbitrary values. Both limits are unlikely to be hit in practice. Changes in v3: - Move DMA related fields in struct ti_csi2rx_dma. - Protect DMA buffer queue with a spinlock to make sure the queue buffer and DMA callback don't race on it. - Track the current DMA state. It might go idle because of a lack of buffers. This state can be used to restart it if needed. - Do not include the current buffer in the pending queue. It is slightly better modelling than leaving it at the head of the pending queue. - Use the buffer as the callback argument, and add a reference to csi in it. - If queueing a buffer to DMA fails, the buffer gets leaked and DMA gets stalled with. Instead, report the error to vb2 and queue the next buffer in the pending queue. - DMA gets stalled if we run out of buffers since the callback is the only one that fires subsequent transfers and it is no longer being called. Check for that when queueing buffers and restart DMA if needed. - Do not put of node until we are done using the fwnode. - Set inital format to UYVY 640x480. Changes in v2: - Use dmaengine_get_dma_device() instead of directly accessing dma->device->dev. - Do not set dst_addr_width when configuring slave DMA. - Move to a separate subdir and rename to j721e-csi2rx.c - Convert compatible to ti,j721e-csi2rx. - Move to use Media Controller centric APIs. - Improve cleanup in probe when one of the steps fails. - Add colorspace to formats database. - Set hw_revision on media_device. - Move video device initialization to probe time instead of register time. MAINTAINERS | 6 + drivers/media/platform/Kconfig | 12 + drivers/media/platform/ti/Makefile | 1 + .../media/platform/ti/j721e-csi2rx/Makefile | 2 + .../platform/ti/j721e-csi2rx/j721e-csi2rx.c | 1008 +++++++++++++++++ 5 files changed, 1029 insertions(+) create mode 100644 drivers/media/platform/ti/j721e-csi2rx/Makefile create mode 100644 drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c diff --git a/MAINTAINERS b/MAINTAINERS index 62bc4a949ae1..7ee236cbd016 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18712,6 +18712,12 @@ S: Odd Fixes F: drivers/clk/ti/ F: include/linux/clk/ti.h +TI J721E CSI2RX DRIVER +M: Pratyush Yadav +L: linux-media@vger.kernel.org +S: Supported +F: drivers/media/platform/ti/j721e-csi2rx/ + TI DAVINCI MACHINE SUPPORT M: Sekhar Nori R: Bartosz Golaszewski diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index aa277a19e275..85caf3e03146 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -200,6 +200,18 @@ config VIDEO_TI_CAL_MC endif # VIDEO_TI_CAL +config VIDEO_TI_J721E_CSI2RX + tristate "TI J721E CSI2RX wrapper layer driver" + depends on VIDEO_DEV && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API + depends on MEDIA_SUPPORT && MEDIA_CONTROLLER + depends on PHY_CADENCE_DPHY && VIDEO_CADENCE_CSI2RX + depends on ARCH_K3 || COMPILE_TEST + select VIDEOBUF2_DMA_CONTIG + select V4L2_FWNODE + help + Support for TI CSI2RX wrapper layer. This just enables the wrapper driver. + The Cadence CSI2RX bridge driver needs to be enabled separately. + endif # V4L_PLATFORM_DRIVERS menuconfig V4L_MEM2MEM_DRIVERS diff --git a/drivers/media/platform/ti/Makefile b/drivers/media/platform/ti/Makefile index bbc737ccbbea..17c9cfb74f66 100644 --- a/drivers/media/platform/ti/Makefile +++ b/drivers/media/platform/ti/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-y += cal/ obj-y += vpe/ +obj-y += j721e-csi2rx/ diff --git a/drivers/media/platform/ti/j721e-csi2rx/Makefile b/drivers/media/platform/ti/j721e-csi2rx/Makefile new file mode 100644 index 000000000000..377afc1d6280 --- /dev/null +++ b/drivers/media/platform/ti/j721e-csi2rx/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_VIDEO_TI_J721E_CSI2RX) += j721e-csi2rx.o diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c new file mode 100644 index 000000000000..333718c92c41 --- /dev/null +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -0,0 +1,1008 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * TI CSI2 RX driver. + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * + * Author: Pratyush Yadav + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#define TI_CSI2RX_MODULE_NAME "j721e-csi2rx" + +#define SHIM_CNTL 0x10 +#define SHIM_CNTL_PIX_RST BIT(0) + +#define SHIM_DMACNTX 0x20 +#define SHIM_DMACNTX_EN BIT(31) +#define SHIM_DMACNTX_YUV422 GENMASK(27, 26) +#define SHIM_DMACNTX_FMT GENMASK(5, 0) +#define SHIM_DMACNTX_UYVY 0 +#define SHIM_DMACNTX_VYUY 1 +#define SHIM_DMACNTX_YUYV 2 +#define SHIM_DMACNTX_YVYU 3 + +#define SHIM_PSI_CFG0 0x24 +#define SHIM_PSI_CFG0_SRC_TAG GENMASK(15, 0) +#define SHIM_PSI_CFG0_DST_TAG GENMASK(31, 15) + +#define CSI_DF_YUV420 0x18 +#define CSI_DF_YUV422 0x1e +#define CSI_DF_RGB444 0x20 +#define CSI_DF_RGB888 0x24 + +#define PSIL_WORD_SIZE_BYTES 16 +/* + * There are no hard limits on the width or height. The DMA engine can handle + * all sizes. The max width and height are arbitrary numbers for this driver. + * Use 16M * 16M as the arbitrary limit. It is large enough that it is unlikely + * the limit will be hit in practice. + */ +#define MAX_WIDTH_BYTES SZ_16M +#define MAX_HEIGHT_BYTES SZ_16M + +struct ti_csi2rx_fmt { + u32 fourcc; /* Four character code. */ + u32 code; /* Mbus code. */ + enum v4l2_colorspace colorspace; + u32 csi_df; /* CSI Data format. */ + u8 bpp; /* Bits per pixel. */ +}; + +struct ti_csi2rx_buffer { + /* Common v4l2 buffer. Must be first. */ + struct vb2_v4l2_buffer vb; + struct list_head list; + struct ti_csi2rx_dev *csi; +}; + +enum ti_csi2rx_dma_state { + TI_CSI2RX_DMA_STOPPED, /* Streaming not started yet. */ + TI_CSI2RX_DMA_IDLE, /* Streaming but no pending DMA operation. */ + TI_CSI2RX_DMA_ACTIVE, /* Streaming and pending DMA operation. */ +}; + +struct ti_csi2rx_dma { + /* Protects all fields in this struct. */ + spinlock_t lock; + struct dma_chan *chan; + /* Buffers queued to the driver, waiting to be processed by DMA. */ + struct list_head queue; + enum ti_csi2rx_dma_state state; + /* + * Current buffer being processed by DMA. NULL if no buffer is being + * processed. + */ + struct ti_csi2rx_buffer *curr; +}; + +struct ti_csi2rx_dev { + struct device *dev; + void __iomem *shim; + struct v4l2_device v4l2_dev; + struct video_device vdev; + struct media_device mdev; + struct media_pipeline pipe; + struct media_pad pad; + struct v4l2_async_notifier notifier; + struct v4l2_subdev *subdev; + struct vb2_queue vidq; + struct mutex mutex; /* To serialize ioctls. */ + struct v4l2_format v_fmt; + struct ti_csi2rx_dma dma; + u32 sequence; +}; + +static const struct ti_csi2rx_fmt formats[] = { + { + .fourcc = V4L2_PIX_FMT_YUYV, + .code = MEDIA_BUS_FMT_YUYV8_2X8, + .colorspace = V4L2_COLORSPACE_SRGB, + .csi_df = CSI_DF_YUV422, + .bpp = 16, + }, { + .fourcc = V4L2_PIX_FMT_UYVY, + .code = MEDIA_BUS_FMT_UYVY8_2X8, + .colorspace = V4L2_COLORSPACE_SRGB, + .csi_df = CSI_DF_YUV422, + .bpp = 16, + }, { + .fourcc = V4L2_PIX_FMT_YVYU, + .code = MEDIA_BUS_FMT_YVYU8_2X8, + .colorspace = V4L2_COLORSPACE_SRGB, + .csi_df = CSI_DF_YUV422, + .bpp = 16, + }, { + .fourcc = V4L2_PIX_FMT_VYUY, + .code = MEDIA_BUS_FMT_VYUY8_2X8, + .colorspace = V4L2_COLORSPACE_SRGB, + .csi_df = CSI_DF_YUV422, + .bpp = 16, + }, + + /* More formats can be supported but they are not listed for now. */ +}; + +static const unsigned int num_formats = ARRAY_SIZE(formats); + +/* Forward declaration needed by ti_csi2rx_dma_callback. */ +static int ti_csi2rx_start_dma(struct ti_csi2rx_dev *csi, + struct ti_csi2rx_buffer *buf); + +static const struct ti_csi2rx_fmt *find_format_by_pix(u32 pixelformat) +{ + unsigned int i; + + for (i = 0; i < num_formats; i++) { + if (formats[i].fourcc == pixelformat) + return &formats[i]; + } + + return NULL; +} + +static void ti_csi2rx_fill_fmt(const struct ti_csi2rx_fmt *csi_fmt, + struct v4l2_format *v4l2_fmt) +{ + struct v4l2_pix_format *pix = &v4l2_fmt->fmt.pix; + u32 bpl; + + v4l2_fmt->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + pix->pixelformat = csi_fmt->fourcc; + pix->colorspace = csi_fmt->colorspace; + pix->sizeimage = pix->height * pix->width * (csi_fmt->bpp / 8); + + bpl = (pix->width * ALIGN(csi_fmt->bpp, 8)) >> 3; + pix->bytesperline = ALIGN(bpl, 16); +} + +static int ti_csi2rx_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + struct ti_csi2rx_dev *csi = video_drvdata(file); + + strscpy(cap->driver, TI_CSI2RX_MODULE_NAME, sizeof(cap->driver)); + strscpy(cap->card, TI_CSI2RX_MODULE_NAME, sizeof(cap->card)); + + snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", + dev_name(csi->dev)); + + return 0; +} + +static int ti_csi2rx_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + if (f->index >= num_formats) + return -EINVAL; + + memset(f->reserved, 0, sizeof(f->reserved)); + f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + f->pixelformat = formats[f->index].fourcc; + + return 0; +} + +static int ti_csi2rx_g_fmt_vid_cap(struct file *file, void *prov, + struct v4l2_format *f) +{ + struct ti_csi2rx_dev *csi = video_drvdata(file); + + *f = csi->v_fmt; + + return 0; +} + +static int ti_csi2rx_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + const struct ti_csi2rx_fmt *fmt; + + /* + * Default to the first format if the requested pixel format code isn't + * supported. + */ + fmt = find_format_by_pix(f->fmt.pix.pixelformat); + if (!fmt) + fmt = &formats[0]; + + if (f->fmt.pix.field == V4L2_FIELD_ANY) + f->fmt.pix.field = V4L2_FIELD_NONE; + + if (f->fmt.pix.field != V4L2_FIELD_NONE) + return -EINVAL; + + ti_csi2rx_fill_fmt(fmt, f); + + return 0; +} + +static int ti_csi2rx_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct ti_csi2rx_dev *csi = video_drvdata(file); + struct vb2_queue *q = &csi->vidq; + int ret; + + if (vb2_is_busy(q)) + return -EBUSY; + + ret = ti_csi2rx_try_fmt_vid_cap(file, priv, f); + if (ret < 0) + return ret; + + csi->v_fmt = *f; + + return 0; +} + +static int ti_csi2rx_enum_framesizes(struct file *file, void *fh, + struct v4l2_frmsizeenum *fsize) +{ + const struct ti_csi2rx_fmt *fmt; + unsigned int pixels_in_word; + u8 bpp; + + fmt = find_format_by_pix(fsize->pixel_format); + if (!fmt) + return -EINVAL; + + bpp = ALIGN(fmt->bpp, 8); + + /* + * Number of pixels in one PSI-L word. The transfer happens in multiples + * of PSI-L word sizes. + */ + pixels_in_word = PSIL_WORD_SIZE_BYTES * 8 / bpp; + + fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; + fsize->stepwise.min_width = pixels_in_word; + fsize->stepwise.max_width = rounddown(MAX_WIDTH_BYTES, pixels_in_word); + fsize->stepwise.step_width = pixels_in_word; + fsize->stepwise.min_height = 1; + fsize->stepwise.max_height = MAX_HEIGHT_BYTES; + fsize->stepwise.step_height = 1; + + return 0; +} + +static const struct v4l2_ioctl_ops csi_ioctl_ops = { + .vidioc_querycap = ti_csi2rx_querycap, + .vidioc_enum_fmt_vid_cap = ti_csi2rx_enum_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = ti_csi2rx_try_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = ti_csi2rx_g_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = ti_csi2rx_s_fmt_vid_cap, + .vidioc_enum_framesizes = ti_csi2rx_enum_framesizes, + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_create_bufs = vb2_ioctl_create_bufs, + .vidioc_prepare_buf = vb2_ioctl_prepare_buf, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, + .vidioc_expbuf = vb2_ioctl_expbuf, + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, +}; + +static const struct v4l2_file_operations csi_fops = { + .owner = THIS_MODULE, + .open = v4l2_fh_open, + .release = vb2_fop_release, + .read = vb2_fop_read, + .poll = vb2_fop_poll, + .unlocked_ioctl = video_ioctl2, + .mmap = vb2_fop_mmap, +}; + +static int ti_csi2rx_video_register(struct ti_csi2rx_dev *csi) +{ + struct video_device *vdev = &csi->vdev; + int ret, src_pad; + + ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); + if (ret) + return ret; + + src_pad = media_entity_get_fwnode_pad(&csi->subdev->entity, + csi->subdev->fwnode, + MEDIA_PAD_FL_SOURCE); + if (src_pad < 0) { + dev_err(csi->dev, "Couldn't find source pad for subdev\n"); + return src_pad; + } + + ret = media_create_pad_link(&csi->subdev->entity, src_pad, + &vdev->entity, 0, + MEDIA_LNK_FL_IMMUTABLE | + MEDIA_LNK_FL_ENABLED); + if (ret) { + video_unregister_device(vdev); + return ret; + } + + return 0; +} + +static int csi_async_notifier_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *subdev, + struct v4l2_async_subdev *asd) +{ + struct ti_csi2rx_dev *csi = dev_get_drvdata(notifier->v4l2_dev->dev); + + csi->subdev = subdev; + + return 0; +} + +static int csi_async_notifier_complete(struct v4l2_async_notifier *notifier) +{ + struct ti_csi2rx_dev *csi = dev_get_drvdata(notifier->v4l2_dev->dev); + int ret; + + ret = ti_csi2rx_video_register(csi); + if (ret) + return ret; + + return v4l2_device_register_subdev_nodes(&csi->v4l2_dev); +} + +static const struct v4l2_async_notifier_operations csi_async_notifier_ops = { + .bound = csi_async_notifier_bound, + .complete = csi_async_notifier_complete, +}; + +static int ti_csi2rx_init_subdev(struct ti_csi2rx_dev *csi) +{ + struct fwnode_handle *fwnode; + struct v4l2_async_subdev *asd; + struct device_node *node; + int ret; + + node = of_get_child_by_name(csi->dev->of_node, "csi-bridge"); + if (!node) + return -EINVAL; + + fwnode = of_fwnode_handle(node); + if (!fwnode) { + of_node_put(node); + return -EINVAL; + } + + v4l2_async_nf_init(&csi->notifier); + csi->notifier.ops = &csi_async_notifier_ops; + + asd = v4l2_async_nf_add_fwnode(&csi->notifier, fwnode, + struct v4l2_async_subdev); + of_node_put(node); + if (IS_ERR(asd)) { + v4l2_async_nf_cleanup(&csi->notifier); + return PTR_ERR(asd); + } + + ret = v4l2_async_nf_register(&csi->v4l2_dev, &csi->notifier); + if (ret) { + v4l2_async_nf_cleanup(&csi->notifier); + return ret; + } + + return 0; +} + +static void ti_csi2rx_setup_shim(struct ti_csi2rx_dev *csi) +{ + const struct ti_csi2rx_fmt *fmt; + unsigned int reg; + + fmt = find_format_by_pix(csi->v_fmt.fmt.pix.pixelformat); + if (!fmt) { + dev_err(csi->dev, "Unknown format\n"); + return; + } + + /* De-assert the pixel interface reset. */ + reg = SHIM_CNTL_PIX_RST; + writel(reg, csi->shim + SHIM_CNTL); + + reg = SHIM_DMACNTX_EN; + reg |= FIELD_PREP(SHIM_DMACNTX_FMT, fmt->csi_df); + + /* + * Using the values from the documentation gives incorrect ordering for + * the luma and chroma components. In practice, the "reverse" format + * gives the correct image. So for example, if the image is in UYVY, the + * reverse would be YVYU. + */ + switch (fmt->fourcc) { + case V4L2_PIX_FMT_UYVY: + reg |= FIELD_PREP(SHIM_DMACNTX_YUV422, + SHIM_DMACNTX_YVYU); + break; + case V4L2_PIX_FMT_VYUY: + reg |= FIELD_PREP(SHIM_DMACNTX_YUV422, + SHIM_DMACNTX_YUYV); + break; + case V4L2_PIX_FMT_YUYV: + reg |= FIELD_PREP(SHIM_DMACNTX_YUV422, + SHIM_DMACNTX_VYUY); + break; + case V4L2_PIX_FMT_YVYU: + reg |= FIELD_PREP(SHIM_DMACNTX_YUV422, + SHIM_DMACNTX_UYVY); + break; + default: + /* Ignore if not YUV 4:2:2 */ + break; + } + + writel(reg, csi->shim + SHIM_DMACNTX); + + reg = FIELD_PREP(SHIM_PSI_CFG0_SRC_TAG, 0) | + FIELD_PREP(SHIM_PSI_CFG0_DST_TAG, 1); + writel(reg, csi->shim + SHIM_PSI_CFG0); +} + +static void ti_csi2rx_dma_callback(void *param) +{ + struct ti_csi2rx_buffer *buf = param; + struct ti_csi2rx_dev *csi = buf->csi; + struct ti_csi2rx_dma *dma = &csi->dma; + unsigned long flags = 0; + + buf->vb.vb2_buf.timestamp = ktime_get_ns(); + buf->vb.sequence = csi->sequence++; + + spin_lock_irqsave(&dma->lock, flags); + + WARN_ON(dma->curr != buf); + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + + /* If there are more buffers to process then start their transfer. */ + dma->curr = NULL; + while (!list_empty(&dma->queue)) { + buf = list_entry(dma->queue.next, struct ti_csi2rx_buffer, list); + list_del(&buf->list); + + if (ti_csi2rx_start_dma(csi, buf)) { + dev_err(csi->dev, "Failed to queue the next buffer for DMA\n"); + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + } else { + dma->curr = buf; + break; + } + } + + if (!dma->curr) + dma->state = TI_CSI2RX_DMA_IDLE; + + spin_unlock_irqrestore(&dma->lock, flags); +} + +static int ti_csi2rx_start_dma(struct ti_csi2rx_dev *csi, + struct ti_csi2rx_buffer *buf) +{ + unsigned long addr; + struct dma_async_tx_descriptor *desc; + size_t len = csi->v_fmt.fmt.pix.sizeimage; + dma_cookie_t cookie; + int ret = 0; + + addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); + desc = dmaengine_prep_slave_single(csi->dma.chan, addr, len, + DMA_DEV_TO_MEM, + DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + if (!desc) + return -EIO; + + desc->callback = ti_csi2rx_dma_callback; + desc->callback_param = buf; + + cookie = dmaengine_submit(desc); + ret = dma_submit_error(cookie); + if (ret) + return ret; + + dma_async_issue_pending(csi->dma.chan); + + return 0; +} + +static int ti_csi2rx_queue_setup(struct vb2_queue *q, unsigned int *nbuffers, + unsigned int *nplanes, unsigned int sizes[], + struct device *alloc_devs[]) +{ + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(q); + unsigned int size = csi->v_fmt.fmt.pix.sizeimage; + + if (*nplanes) { + if (sizes[0] < size) + return -EINVAL; + size = sizes[0]; + } + + *nplanes = 1; + sizes[0] = size; + + return 0; +} + +static int ti_csi2rx_buffer_prepare(struct vb2_buffer *vb) +{ + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vb->vb2_queue); + unsigned long size = csi->v_fmt.fmt.pix.sizeimage; + + if (vb2_plane_size(vb, 0) < size) { + dev_err(csi->dev, "Data will not fit into plane\n"); + return -EINVAL; + } + + vb2_set_plane_payload(vb, 0, size); + return 0; +} + +static void ti_csi2rx_buffer_queue(struct vb2_buffer *vb) +{ + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vb->vb2_queue); + struct ti_csi2rx_buffer *buf; + struct ti_csi2rx_dma *dma = &csi->dma; + unsigned long flags = 0; + int ret; + + buf = container_of(vb, struct ti_csi2rx_buffer, vb.vb2_buf); + buf->csi = csi; + + spin_lock_irqsave(&dma->lock, flags); + /* + * Usually the DMA callback takes care of queueing the pending buffers. + * But if DMA has stalled due to lack of buffers, restart it now. + */ + if (dma->state == TI_CSI2RX_DMA_IDLE) { + ret = ti_csi2rx_start_dma(csi, buf); + if (ret) { + dev_err(csi->dev, "Failed to start DMA: %d\n", ret); + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); + goto unlock; + } + + dma->curr = buf; + dma->state = TI_CSI2RX_DMA_ACTIVE; + } else { + list_add_tail(&buf->list, &dma->queue); + } + +unlock: + spin_unlock_irqrestore(&dma->lock, flags); +} + +/* + * Find the input format. This is done by finding the first device in the + * pipeline which can tell us the current format. This could be the sensor, or + * this could be another device in the middle which is capable of format + * conversions. + */ +static int ti_csi2rx_validate_pipeline(struct ti_csi2rx_dev *csi) +{ + struct media_pipeline *pipe = &csi->pipe; + struct media_entity *entity; + struct v4l2_subdev *sd; + struct v4l2_subdev_format fmt; + struct v4l2_pix_format *pix = &csi->v_fmt.fmt.pix; + struct media_device *mdev = &csi->mdev; + const struct ti_csi2rx_fmt *ti_fmt; + int ret; + + mutex_lock(&mdev->graph_mutex); + ret = media_graph_walk_init(&pipe->graph, mdev); + if (ret) { + mutex_unlock(&mdev->graph_mutex); + return ret; + } + + media_graph_walk_start(&pipe->graph, &csi->vdev.entity); + + while ((entity = media_graph_walk_next(&pipe->graph))) { + if (!is_media_entity_v4l2_subdev(entity)) + continue; + + sd = media_entity_to_v4l2_subdev(entity); + + fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; + fmt.pad = media_get_pad_index(entity, 0, PAD_SIGNAL_DEFAULT); + + ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt); + if (ret && ret != -ENOIOCTLCMD) { + media_graph_walk_cleanup(&pipe->graph); + mutex_unlock(&mdev->graph_mutex); + return ret; + } + + if (!ret) + break; + } + + media_graph_walk_cleanup(&pipe->graph); + mutex_unlock(&mdev->graph_mutex); + + /* Could not find input format. */ + if (!entity) + return -EPIPE; + + if (fmt.format.width != pix->width) + return -EPIPE; + if (fmt.format.height != pix->height) + return -EPIPE; + + ti_fmt = find_format_by_pix(pix->pixelformat); + if (WARN_ON(!ti_fmt)) + return -EINVAL; + + if (fmt.format.code == MEDIA_BUS_FMT_YUYV8_2X8 || + fmt.format.code == MEDIA_BUS_FMT_VYUY8_2X8 || + fmt.format.code == MEDIA_BUS_FMT_YVYU8_2X8) { + dev_err(csi->dev, + "Only UYVY input allowed for YUV422 8-bit. Output format can be configured.\n"); + return -EPIPE; + } + + if (fmt.format.code == MEDIA_BUS_FMT_UYVY8_2X8) { + /* Format conversion between YUV422 formats can be done. */ + if (ti_fmt->code != MEDIA_BUS_FMT_UYVY8_2X8 && + ti_fmt->code != MEDIA_BUS_FMT_YUYV8_2X8 && + ti_fmt->code != MEDIA_BUS_FMT_VYUY8_2X8 && + ti_fmt->code != MEDIA_BUS_FMT_YVYU8_2X8) + return -EPIPE; + } else if (fmt.format.code != ti_fmt->code) { + return -EPIPE; + } + + if (fmt.format.field != V4L2_FIELD_NONE && + fmt.format.field != V4L2_FIELD_ANY) + return -EPIPE; + + return 0; +} + +static int ti_csi2rx_start_streaming(struct vb2_queue *vq, unsigned int count) +{ + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vq); + struct ti_csi2rx_dma *dma = &csi->dma; + struct ti_csi2rx_buffer *buf, *tmp; + unsigned long flags = 0; + int ret = 0; + + spin_lock_irqsave(&dma->lock, flags); + if (list_empty(&dma->queue)) + ret = -EIO; + spin_unlock_irqrestore(&dma->lock, flags); + if (ret) + return ret; + + ret = media_pipeline_start(&csi->vdev.entity, &csi->pipe); + if (ret) + return ret; + + ret = ti_csi2rx_validate_pipeline(csi); + if (ret) { + dev_err(csi->dev, + "Format mismatch between source and video node\n"); + goto err; + } + + ti_csi2rx_setup_shim(csi); + + ret = v4l2_subdev_call(csi->subdev, video, s_stream, 1); + if (ret) + goto err; + + csi->sequence = 0; + + spin_lock_irqsave(&dma->lock, flags); + buf = list_entry(dma->queue.next, struct ti_csi2rx_buffer, list); + list_del(&buf->list); + dma->state = TI_CSI2RX_DMA_ACTIVE; + + ret = ti_csi2rx_start_dma(csi, buf); + if (ret) { + dev_err(csi->dev, "Failed to start DMA: %d\n", ret); + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); + spin_unlock_irqrestore(&dma->lock, flags); + goto err_stream; + } + + dma->curr = buf; + spin_unlock_irqrestore(&dma->lock, flags); + + return 0; + +err_stream: + v4l2_subdev_call(csi->subdev, video, s_stream, 0); +err: + media_pipeline_stop(&csi->vdev.entity); + + spin_lock_irqsave(&dma->lock, flags); + list_for_each_entry_safe(buf, tmp, &dma->queue, list) { + list_del(&buf->list); + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); + } + csi->dma.state = TI_CSI2RX_DMA_STOPPED; + spin_unlock_irqrestore(&dma->lock, flags); + + return ret; +} + +static void ti_csi2rx_stop_streaming(struct vb2_queue *vq) +{ + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vq); + struct ti_csi2rx_buffer *buf = NULL, *tmp; + struct ti_csi2rx_dma *dma = &csi->dma; + unsigned long flags = 0; + int ret; + + media_pipeline_stop(&csi->vdev.entity); + + ret = v4l2_subdev_call(csi->subdev, video, s_stream, 0); + if (ret) + dev_err(csi->dev, "Failed to stop subdev stream\n"); + + writel(0, csi->shim + SHIM_CNTL); + + ret = dmaengine_terminate_sync(csi->dma.chan); + if (ret) + dev_err(csi->dev, "Failed to stop DMA\n"); + + writel(0, csi->shim + SHIM_DMACNTX); + + spin_lock_irqsave(&dma->lock, flags); + list_for_each_entry_safe(buf, tmp, &csi->dma.queue, list) { + list_del(&buf->list); + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + } + + if (dma->curr) + vb2_buffer_done(&dma->curr->vb.vb2_buf, VB2_BUF_STATE_ERROR); + + dma->curr = NULL; + dma->state = TI_CSI2RX_DMA_STOPPED; + spin_unlock_irqrestore(&dma->lock, flags); +} + +static const struct vb2_ops csi_vb2_qops = { + .queue_setup = ti_csi2rx_queue_setup, + .buf_prepare = ti_csi2rx_buffer_prepare, + .buf_queue = ti_csi2rx_buffer_queue, + .start_streaming = ti_csi2rx_start_streaming, + .stop_streaming = ti_csi2rx_stop_streaming, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, +}; + +static int ti_csi2rx_init_vb2q(struct ti_csi2rx_dev *csi) +{ + struct vb2_queue *q = &csi->vidq; + int ret; + + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ; + q->drv_priv = csi; + q->buf_struct_size = sizeof(struct ti_csi2rx_buffer); + q->ops = &csi_vb2_qops; + q->mem_ops = &vb2_dma_contig_memops; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->dev = dmaengine_get_dma_device(csi->dma.chan); + q->lock = &csi->mutex; + + ret = vb2_queue_init(q); + if (ret) + return ret; + + csi->vdev.queue = q; + + return 0; +} + +static int ti_csi2rx_init_dma(struct ti_csi2rx_dev *csi) +{ + struct dma_slave_config cfg; + int ret; + + INIT_LIST_HEAD(&csi->dma.queue); + spin_lock_init(&csi->dma.lock); + + csi->dma.state = TI_CSI2RX_DMA_STOPPED; + + csi->dma.chan = dma_request_chan(csi->dev, "rx0"); + if (IS_ERR(csi->dma.chan)) + return PTR_ERR(csi->dma.chan); + + memset(&cfg, 0, sizeof(cfg)); + + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_16_BYTES; + + ret = dmaengine_slave_config(csi->dma.chan, &cfg); + if (ret) + return ret; + + return 0; +} + +static int ti_csi2rx_v4l2_init(struct ti_csi2rx_dev *csi) +{ + struct media_device *mdev = &csi->mdev; + struct video_device *vdev = &csi->vdev; + const struct ti_csi2rx_fmt *fmt; + struct v4l2_pix_format *pix_fmt = &csi->v_fmt.fmt.pix; + int ret; + + fmt = find_format_by_pix(V4L2_PIX_FMT_UYVY); + if (!fmt) + return -EINVAL; + + pix_fmt->width = 640; + pix_fmt->height = 480; + + ti_csi2rx_fill_fmt(fmt, &csi->v_fmt); + + mdev->dev = csi->dev; + mdev->hw_revision = 1; + strscpy(mdev->model, "TI-CSI2RX", sizeof(mdev->model)); + snprintf(mdev->bus_info, sizeof(mdev->bus_info), "platform:%s", + dev_name(mdev->dev)); + + media_device_init(mdev); + + strscpy(vdev->name, TI_CSI2RX_MODULE_NAME, sizeof(vdev->name)); + vdev->v4l2_dev = &csi->v4l2_dev; + vdev->vfl_dir = VFL_DIR_RX; + vdev->fops = &csi_fops; + vdev->ioctl_ops = &csi_ioctl_ops; + vdev->release = video_device_release_empty; + vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | + V4L2_CAP_STREAMING | V4L2_CAP_IO_MC; + vdev->lock = &csi->mutex; + video_set_drvdata(vdev, csi); + + csi->pad.flags = MEDIA_PAD_FL_SINK; + ret = media_entity_pads_init(&csi->vdev.entity, 1, &csi->pad); + if (ret) + return ret; + + csi->v4l2_dev.mdev = mdev; + + ret = v4l2_device_register(csi->dev, &csi->v4l2_dev); + if (ret) + return ret; + + ret = media_device_register(mdev); + if (ret) { + v4l2_device_unregister(&csi->v4l2_dev); + media_device_cleanup(mdev); + return ret; + } + + return 0; +} + +static void ti_csi2rx_cleanup_dma(struct ti_csi2rx_dev *csi) +{ + dma_release_channel(csi->dma.chan); +} + +static void ti_csi2rx_cleanup_v4l2(struct ti_csi2rx_dev *csi) +{ + media_device_unregister(&csi->mdev); + v4l2_device_unregister(&csi->v4l2_dev); + media_device_cleanup(&csi->mdev); +} + +static void ti_csi2rx_cleanup_subdev(struct ti_csi2rx_dev *csi) +{ + v4l2_async_nf_unregister(&csi->notifier); + v4l2_async_nf_cleanup(&csi->notifier); +} + +static void ti_csi2rx_cleanup_vb2q(struct ti_csi2rx_dev *csi) +{ + vb2_queue_release(&csi->vidq); +} + +static int ti_csi2rx_probe(struct platform_device *pdev) +{ + struct ti_csi2rx_dev *csi; + struct resource *res; + int ret; + + csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL); + if (!csi) + return -ENOMEM; + + csi->dev = &pdev->dev; + platform_set_drvdata(pdev, csi); + + mutex_init(&csi->mutex); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + csi->shim = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(csi->shim)) + return PTR_ERR(csi->shim); + + ret = ti_csi2rx_init_dma(csi); + if (ret) + return ret; + + ret = ti_csi2rx_v4l2_init(csi); + if (ret) + goto err_dma; + + ret = ti_csi2rx_init_vb2q(csi); + if (ret) + goto err_v4l2; + + ret = ti_csi2rx_init_subdev(csi); + if (ret) + goto err_vb2q; + + ret = of_platform_populate(csi->dev->of_node, NULL, NULL, csi->dev); + if (ret) { + dev_err(csi->dev, "Failed to create children: %d\n", ret); + goto err_subdev; + } + + return 0; + +err_subdev: + ti_csi2rx_cleanup_subdev(csi); +err_vb2q: + ti_csi2rx_cleanup_vb2q(csi); +err_v4l2: + ti_csi2rx_cleanup_v4l2(csi); +err_dma: + ti_csi2rx_cleanup_dma(csi); + return ret; +} + +static int ti_csi2rx_remove(struct platform_device *pdev) +{ + struct ti_csi2rx_dev *csi = platform_get_drvdata(pdev); + + if (vb2_is_busy(&csi->vidq)) + return -EBUSY; + + video_unregister_device(&csi->vdev); + + ti_csi2rx_cleanup_vb2q(csi); + ti_csi2rx_cleanup_subdev(csi); + ti_csi2rx_cleanup_v4l2(csi); + ti_csi2rx_cleanup_dma(csi); + + return 0; +} + +static const struct of_device_id ti_csi2rx_of_match[] = { + { .compatible = "ti,j721e-csi2rx", }, + { }, +}; +MODULE_DEVICE_TABLE(of, ti_csi2rx_of_match); + +static struct platform_driver ti_csi2rx_pdrv = { + .probe = ti_csi2rx_probe, + .remove = ti_csi2rx_remove, + .driver = { + .name = TI_CSI2RX_MODULE_NAME, + .of_match_table = ti_csi2rx_of_match, + }, +}; + +module_platform_driver(ti_csi2rx_pdrv); + +MODULE_DESCRIPTION("TI J721E CSI2 RX Driver"); +MODULE_AUTHOR("Pratyush Yadav "); +MODULE_LICENSE("GPL v2"); +MODULE_VERSION("1.0"); From patchwork Wed Sep 15 12:02:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 513262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2065C433EF for ; Wed, 15 Sep 2021 12:03:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8344061354 for ; Wed, 15 Sep 2021 12:03:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232930AbhIOMFJ (ORCPT ); Wed, 15 Sep 2021 08:05:09 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:46724 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232887AbhIOMEq (ORCPT ); Wed, 15 Sep 2021 08:04:46 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 18FC3NVb066482; Wed, 15 Sep 2021 07:03:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1631707403; bh=hN5uE93XZj37Xv7//FNslH6f7yJkUpIZe1Xe3lzSGGU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JDXcaJcIN3GGrEijxcvEaiD8qfWLokuzCrokB7zEdVH6xG9LOp/DGYsssAy9lAAPq acD5d9sl6AwqxLQu9f81MUdGM1nz1+suVii57VPTMi5UdRcnlvo0Wq2kq54TQzB4Q4 C/NEm+QQ87zG7uWrS7vHc/Z0BCU1FqqimcW/L9Oo= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 18FC3MUL049157 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 15 Sep 2021 07:03:22 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Wed, 15 Sep 2021 07:03:22 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 15 Sep 2021 07:03:22 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 18FC2fDA019246; Wed, 15 Sep 2021 07:03:19 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab CC: Pratyush Yadav , Laurent Pinchart , Nikhil Devshatwar , Tomi Valkeinen , Vignesh Raghavendra , Benoit Parrot , Maxime Ripard , Rob Herring , Sakari Ailus , =?utf-8?q?Niklas_S=C3=B6derlund?= , , , Subject: [PATCH v4 09/11] media: dt-bindings: Make sure items in data-lanes are unique Date: Wed, 15 Sep 2021 17:32:38 +0530 Message-ID: <20210915120240.21572-10-p.yadav@ti.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210915120240.21572-1-p.yadav@ti.com> References: <20210915120240.21572-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The data-lanes property maps the logical lane numbers to the physical lane numbers. The position of an entry is the logical lane number and its value is the physical lane number. Since one physical lane can only map to one logical lane, no number in the list should repeat. Add the uniqueItems constraint on the property to enforce this. Signed-off-by: Pratyush Yadav Acked-by: Rob Herring Reviewed-by: Laurent Pinchart --- Changes in v4: - New in v4. Documentation/devicetree/bindings/media/video-interfaces.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/media/video-interfaces.yaml b/Documentation/devicetree/bindings/media/video-interfaces.yaml index 4391dce2caee..4bce93efae5f 100644 --- a/Documentation/devicetree/bindings/media/video-interfaces.yaml +++ b/Documentation/devicetree/bindings/media/video-interfaces.yaml @@ -158,6 +158,7 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 maxItems: 8 + uniqueItems: true items: # Assume up to 9 physical lane indices maximum: 8 From patchwork Wed Sep 15 12:02:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 512401 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD20BC433EF for ; Wed, 15 Sep 2021 12:03:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A4F9261356 for ; Wed, 15 Sep 2021 12:03:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237812AbhIOMFM (ORCPT ); Wed, 15 Sep 2021 08:05:12 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:46772 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237834AbhIOMEv (ORCPT ); Wed, 15 Sep 2021 08:04:51 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 18FC3R5w066510; Wed, 15 Sep 2021 07:03:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1631707407; bh=vTvtlpflSxIHLgiIUmQ7qVkhakZbTnWnNKgslc6WBI8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=l46h7pRx4pXZzGMty2wRkPhvh+ls5KzESCm04oTiJi8NgA2S+H666Fr/siz1zJs0l LmvswBCP+4rEqjF/iULEQ3GYQWtkOPSws6GCrh3oMgza3QkG1jXj2uiQOTUorSuiv7 ZxtX3D/R+jMr7kw+smUmaJ/qN70EemsTVMXNb/vU= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 18FC3R2B100415 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 15 Sep 2021 07:03:27 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Wed, 15 Sep 2021 07:03:26 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 15 Sep 2021 07:03:26 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 18FC2fDB019246; Wed, 15 Sep 2021 07:03:23 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab CC: Pratyush Yadav , Laurent Pinchart , Nikhil Devshatwar , Tomi Valkeinen , Vignesh Raghavendra , Benoit Parrot , Maxime Ripard , Rob Herring , Sakari Ailus , =?utf-8?q?Niklas_S=C3=B6derlund?= , , , Subject: [PATCH v4 10/11] media: dt-bindings: Add DT bindings for TI J721E CSI2RX driver Date: Wed, 15 Sep 2021 17:32:39 +0530 Message-ID: <20210915120240.21572-11-p.yadav@ti.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210915120240.21572-1-p.yadav@ti.com> References: <20210915120240.21572-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate capture over a CSI-2 bus. The TI CSI2RX platform driver glues all the parts together. Signed-off-by: Pratyush Yadav Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart --- (no changes since v2) Changes in v2: - Rename to ti,j721e-csi2rx.yaml - Add an entry in MAINTAINERS. - Add a description for the binding. - Change compatible to ti,j721e-csi2rx to make it SoC specific. - Remove description from dmas, reg, power-domains. - Remove a limit of 2 from #address-cells and #size-cells. - Fix add ^ to csi-bridge subnode regex. - Make ranges mandatory. - Add unit address in example. - Add a reference to cdns,csi2rx in csi-bridge subnode. - Expand the example to include the csi-bridge subnode as well. - Re-order subject prefixes. .../bindings/media/ti,j721e-csi2rx.yaml | 101 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 102 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml diff --git a/Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml new file mode 100644 index 000000000000..db87cfd65bed --- /dev/null +++ b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/ti,j721e-csi2rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI J721E CSI2RX Wrapper Device Tree Bindings + +description: | + The TI J721E CSI2RX Wrapper is a wrapper around Cadence CSI2RX bridge that + enables sending captured frames to memory over PSI-L DMA. In the J721E + Technical Reference Manual (SPRUIL1B) it is referred to as "SHIM" under the + CSI_RX_IF section. + +maintainers: + - Pratyush Yadav + +properties: + compatible: + items: + - const: ti,j721e-csi2rx + + dmas: + maxItems: 1 + + dma-names: + items: + - const: rx0 + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + ranges: true + + "#address-cells": true + + "#size-cells": true + +patternProperties: + "^csi-bridge@": + type: object + description: CSI2 bridge node. + $ref: cdns,csi2rx.yaml# + +required: + - compatible + - reg + - dmas + - dma-names + - power-domains + - ranges + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx"; + dmas = <&main_udmap 0x4940>; + dma-names = "rx0"; + reg = <0x4500000 0x1000>; + power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cdns_csi2rx: csi-bridge@4504000 { + compatible = "cdns,csi2rx"; + reg = <0x4504000 0x1000>; + clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, + <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + + reg = <0>; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 7ee236cbd016..7b3e557c9d3b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18716,6 +18716,7 @@ TI J721E CSI2RX DRIVER M: Pratyush Yadav L: linux-media@vger.kernel.org S: Supported +F: Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml F: drivers/media/platform/ti/j721e-csi2rx/ TI DAVINCI MACHINE SUPPORT From patchwork Wed Sep 15 12:02:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 513261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9883BC433F5 for ; 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Wed, 15 Sep 2021 07:03:31 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Wed, 15 Sep 2021 07:03:30 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 15 Sep 2021 07:03:30 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 18FC2fDC019246; Wed, 15 Sep 2021 07:03:27 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab CC: Pratyush Yadav , Laurent Pinchart , Nikhil Devshatwar , Tomi Valkeinen , Vignesh Raghavendra , Benoit Parrot , Maxime Ripard , Rob Herring , Sakari Ailus , =?utf-8?q?Niklas_S=C3=B6derlund?= , , , Subject: [PATCH v4 11/11] media: dt-bindings: Convert Cadence CSI2RX binding to YAML Date: Wed, 15 Sep 2021 17:32:40 +0530 Message-ID: <20210915120240.21572-12-p.yadav@ti.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210915120240.21572-1-p.yadav@ti.com> References: <20210915120240.21572-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Cadence CSI2RX binding to use YAML schema. Signed-off-by: Pratyush Yadav Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart --- Changes in v4: - Add power-domains property. - Drop maxItems from clock-names. - Drop the type for data-lanes. - Drop uniqueItems from data-lanes. Move it to video-interfaces.yaml instead. Changes in v3: - Add compatible: contains: const: cdns,csi2rx to allow SoC specific compatible. - Add more constraints for data-lanes property. Changes in v2: - New in v2. .../devicetree/bindings/media/cdns,csi2rx.txt | 100 ----------- .../bindings/media/cdns,csi2rx.yaml | 169 ++++++++++++++++++ 2 files changed, 169 insertions(+), 100 deletions(-) delete mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.txt create mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.yaml diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt b/Documentation/devicetree/bindings/media/cdns,csi2rx.txt deleted file mode 100644 index 6b02a0657ad9..000000000000 --- a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt +++ /dev/null @@ -1,100 +0,0 @@ -Cadence MIPI-CSI2 RX controller -=============================== - -The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI -lanes in input, and 4 different pixel streams in output. - -Required properties: - - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible - - reg: base address and size of the memory mapped region - - clocks: phandles to the clocks driving the controller - - clock-names: must contain: - * sys_clk: main clock - * p_clk: register bank clock - * pixel_if[0-3]_clk: pixel stream output clock, one for each stream - implemented in hardware, between 0 and 3 - -Optional properties: - - phys: phandle to the external D-PHY, phy-names must be provided - - phy-names: must contain "dphy", if the implementation uses an - external D-PHY - -Required subnodes: - - ports: A ports node with one port child node per device input and output - port, in accordance with the video interface bindings defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - port nodes are numbered as follows: - - Port Description - ----------------------------- - 0 CSI-2 input - 1 Stream 0 output - 2 Stream 1 output - 3 Stream 2 output - 4 Stream 3 output - - The stream output port nodes are optional if they are not - connected to anything at the hardware level or implemented - in the design.Since there is only one endpoint per port, - the endpoints are not numbered. - - -Example: - -csi2rx: csi-bridge@0d060000 { - compatible = "cdns,csi2rx"; - reg = <0x0d060000 0x1000>; - clocks = <&byteclock>, <&byteclock> - <&coreclock>, <&coreclock>, - <&coreclock>, <&coreclock>; - clock-names = "sys_clk", "p_clk", - "pixel_if0_clk", "pixel_if1_clk", - "pixel_if2_clk", "pixel_if3_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - csi2rx_in_sensor: endpoint { - remote-endpoint = <&sensor_out_csi2rx>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - - csi2rx_out_grabber0: endpoint { - remote-endpoint = <&grabber0_in_csi2rx>; - }; - }; - - port@2 { - reg = <2>; - - csi2rx_out_grabber1: endpoint { - remote-endpoint = <&grabber1_in_csi2rx>; - }; - }; - - port@3 { - reg = <3>; - - csi2rx_out_grabber2: endpoint { - remote-endpoint = <&grabber2_in_csi2rx>; - }; - }; - - port@4 { - reg = <4>; - - csi2rx_out_grabber3: endpoint { - remote-endpoint = <&grabber3_in_csi2rx>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml new file mode 100644 index 000000000000..fbd7f0503832 --- /dev/null +++ b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/cdns,csi2rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence MIPI-CSI2 RX controller + +description: | + The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI + lanes in input, and 4 different pixel streams in output. + +maintainers: + - Pratyush Yadav + +properties: + compatible: + contains: + const: cdns,csi2rx + + reg: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 6 + + clock-names: + minItems: 3 + items: + - const: sys_clk # main clock + - const: p_clk # register bank clock + - const: pixel_if0_clk # pixel stream 0 output clock + - const: pixel_if1_clk # pixel stream 1 output clock + - const: pixel_if2_clk # pixel stream 2 output clock + - const: pixel_if3_clk # pixel stream 3 output clock + + phys: + maxItems: 1 + description: phandle to the external D-PHY + + phy-names: + items: + - const: dphy + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI-2 input + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + items: + maximum: 4 + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 0 output + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 1 output + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 2 output + + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 3 output + + required: + - port@0 + + +dependencies: + phys: [ 'phy-names' ] + phy-names: [ 'phys' ] + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + csi2rx: csi-bridge@d060000 { + compatible = "cdns,csi2rx"; + reg = <0x0d060000 0x1000>; + clocks = <&byteclock>, <&byteclock>, + <&coreclock>, <&coreclock>, + <&coreclock>, <&coreclock>; + clock-names = "sys_clk", "p_clk", + "pixel_if0_clk", "pixel_if1_clk", + "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi2rx_in_sensor: endpoint { + remote-endpoint = <&sensor_out_csi2rx>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + + csi2rx_out_grabber0: endpoint { + remote-endpoint = <&grabber0_in_csi2rx>; + }; + }; + + port@2 { + reg = <2>; + + csi2rx_out_grabber1: endpoint { + remote-endpoint = <&grabber1_in_csi2rx>; + }; + }; + + port@3 { + reg = <3>; + + csi2rx_out_grabber2: endpoint { + remote-endpoint = <&grabber2_in_csi2rx>; + }; + }; + + port@4 { + reg = <4>; + + csi2rx_out_grabber3: endpoint { + remote-endpoint = <&grabber3_in_csi2rx>; + }; + }; + }; + };