From patchwork Tue Sep 14 12:34:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fengquan Chen X-Patchwork-Id: 511438 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59773C433F5 for ; Tue, 14 Sep 2021 12:35:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 43A8660FED for ; Tue, 14 Sep 2021 12:35:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232836AbhINMg1 (ORCPT ); Tue, 14 Sep 2021 08:36:27 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:40486 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232801AbhINMgV (ORCPT ); Tue, 14 Sep 2021 08:36:21 -0400 X-UUID: 77751c7b44d8426493af619b85db3633-20210914 X-UUID: 77751c7b44d8426493af619b85db3633-20210914 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 900585629; Tue, 14 Sep 2021 20:35:01 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Tue, 14 Sep 2021 20:35:00 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 14 Sep 2021 20:34:59 +0800 From: Fengquan Chen To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Matthias Brugger , , , , , CC: , , , , , , Subject: [v3,2/2] watchdog: mtk: add disable_wdt_extrst support Date: Tue, 14 Sep 2021 20:34:54 +0800 Message-ID: <20210914123454.32603-3-Fengquan.Chen@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914123454.32603-1-Fengquan.Chen@mediatek.com> References: <20210914123454.32603-1-Fengquan.Chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org In some cases, we may need watchdog just to trigger an internal soc reset without sending any output signal. Provide a disable_wdt_extrst parameter for configuration. We can disable or enable it just by configuring dts. Signed-off-by: Fengquan Chen Reviewed-by: Guenter Roeck --- drivers/watchdog/mtk_wdt.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 796fbb048cbe..ceb57ea627cd 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -65,6 +65,7 @@ struct mtk_wdt_dev { void __iomem *wdt_base; spinlock_t lock; /* protects WDT_SWSYSRST reg */ struct reset_controller_dev rcdev; + bool disable_wdt_extrst; }; struct mtk_wdt_data { @@ -256,6 +257,8 @@ static int mtk_wdt_start(struct watchdog_device *wdt_dev) reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); else reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); + if (mtk_wdt->disable_wdt_extrst) + reg &= ~WDT_MODE_EXRST_EN; reg |= (WDT_MODE_EN | WDT_MODE_KEY); iowrite32(reg, wdt_base + WDT_MODE); @@ -381,6 +384,10 @@ static int mtk_wdt_probe(struct platform_device *pdev) if (err) return err; } + + mtk_wdt->disable_wdt_extrst = + of_property_read_bool(dev->of_node, "mediatek,disable-extrst"); + return 0; }