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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id r13sm9622654pgl.90.2021.09.13.19.56.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 19:56:03 -0700 (PDT) From: Shawn Guo To: Stephen Boyd Cc: Rob Herring , Bjorn Andersson , Loic Poulain , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 1/3] clk: qcom: smd-rpm: Add rate hooks for clk_smd_rpm_branch_ops Date: Tue, 14 Sep 2021 10:55:52 +0800 Message-Id: <20210914025554.5686-2-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210914025554.5686-1-shawn.guo@linaro.org> References: <20210914025554.5686-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On QCM2290 platform, the clock xo_board runs at 38400000, while the child clock bi_tcxo needs to run at 19200000. That said, clk_smd_rpm_branch_ops needs the capability of setting rate. Add rate hooks into clk_smd_rpm_branch_ops to make it possible. Signed-off-by: Shawn Guo --- drivers/clk/qcom/clk-smd-rpm.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 Signed-off-by: Shawn Guo diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 66d7807ee38e..2380e45b6247 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -416,6 +416,9 @@ static const struct clk_ops clk_smd_rpm_ops = { static const struct clk_ops clk_smd_rpm_branch_ops = { .prepare = clk_smd_rpm_prepare, .unprepare = clk_smd_rpm_unprepare, + .set_rate = clk_smd_rpm_set_rate, + .round_rate = clk_smd_rpm_round_rate, + .recalc_rate = clk_smd_rpm_recalc_rate, }; DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); From patchwork Tue Sep 14 02:55:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 510909 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1137266jao; Mon, 13 Sep 2021 19:56:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwhakyZkJ0OjzLo3NQF0SnMoaPHQrB/nPHOJpgWFmOIciErYGmXMG6JUA7C3zJkEIN3YvTl X-Received: by 2002:a92:d0d2:: with SMTP id y18mr6580763ila.80.1631588173781; Mon, 13 Sep 2021 19:56:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631588173; cv=none; d=google.com; s=arc-20160816; b=ohecYE2jAzj9RK3TtGX7Z3IwXSZgaBm6JDO//HmJ04xm4nA5sYbneAQqZK+OEBAINd GvJoGpV+BXo1YfrkiD+7tPC5CXggTJqa+YB3leU15H7bwflUyOvpfBbyrWMjO8knHrJJ 3nEG15D+w8C9GWEgONUMVgJo7RxhsKmlsFs524HaiKf3wKS2kAver57K1kftCSK6e160 oWwg7qEuGB8TY9seKIdY9HIQAQljWaBJTbobKAPRjPuqt7ZdzT6PYU2XAqW0brLIc4Cr mMy0fAQqxvnrNao+rDs8fVh1XMsBLxAB/wtpxWRHRXV6WwySa4hsrJriBvM84EfMxcd6 wkrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=x7aZTfIyIwGJxBeqjp2VS+8QxWVwQJBhJBrFL9IwQ/I=; b=BRIf6DeL2Z/ulWGpJTRi+dBccz6WX7OIIO9ZqzCvMOKxcAr7nIXIU9eBGdM/ob+5YC 3arT+KWURrJH7N0cnZ42rx3tMYV/yjBofkT1WkLMHF2wlKYTS8OdvKoyYsbwMhPmVmap kFu59idMFYYqh3vTr2D1zRJmrLgwEApk6st2p2THcFBFSrOokJDkiqo2+0QFEycsyjsA Q7vdjejMqnbpP+nJTSP4ZLne5SrV2x/+PeZFdm47DU9TTovaTz7AWLKD3knmELuHel8C XJhaLb7PLpBug7+/iucCIrHgPR4TyYEM5IzAYS7Q0TBjbeUUC2dxcbSbJlyeD1I0dqOc 58og== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SMh8M7i+; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id r13sm9622654pgl.90.2021.09.13.19.56.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 19:56:06 -0700 (PDT) From: Shawn Guo To: Stephen Boyd Cc: Rob Herring , Bjorn Andersson , Loic Poulain , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 2/3] dt-bindings: clk: qcom, rpmcc: Document QCM2290 compatible Date: Tue, 14 Sep 2021 10:55:53 +0800 Message-Id: <20210914025554.5686-3-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210914025554.5686-1-shawn.guo@linaro.org> References: <20210914025554.5686-1-shawn.guo@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add compatible for the RPM Clock Controller on the QCM2290 SoC. Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/clock/qcom,rpmcc.txt | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt index a4877881f1d8..da295c3c004b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt @@ -25,6 +25,7 @@ Required properties : "qcom,rpmcc-msm8994",ยท"qcom,rpmcc" "qcom,rpmcc-msm8996", "qcom,rpmcc" "qcom,rpmcc-msm8998", "qcom,rpmcc" + "qcom,rpmcc-qcm2290", "qcom,rpmcc" "qcom,rpmcc-qcs404", "qcom,rpmcc" "qcom,rpmcc-sdm660", "qcom,rpmcc" "qcom,rpmcc-sm6115", "qcom,rpmcc" From patchwork Tue Sep 14 02:55:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 510910 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1137293jao; Mon, 13 Sep 2021 19:56:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx7fnQ0hC63+vvyRkDq1COzfoM+MuOMaLj2I6iUVrg3G6U0gAzT+RbIajDg+5ISq5cvwqAd X-Received: by 2002:a05:6e02:1aa6:: with SMTP id l6mr10565105ilv.14.1631588177460; Mon, 13 Sep 2021 19:56:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631588177; cv=none; d=google.com; s=arc-20160816; b=wAQIOfHbtng4kAHK1SdYEx0ke2m2HYXo0yMq7+l+CZdmPGmsBz2TFN3u3MSq/guZgc o+xwdFZ1EGxQgKmUWVy8sbols0TdEtrDb1roqjQXBOmPql3YNmy8t49wbPvhGGC6NTYc RhzzmcahyeAGgkz7bYMMT3MS4n4oOJwzFM5hE+2Nh9iFfa+hIWshG/haGfgKEgpwrk+B Mn7WKJqAm2bnMSktk1ZRtOUBLdpzqvBZ4xgF6hRiOIGM9QAOJ2HDnSVZzTftnivbWXQ5 3whq1tVgWAgPof+IjpO69udjVUIrvoM/HTJ5556EPGNqv+/DahQXIVIMxSJKJ0iOVfGf SLTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=6z4EVDIxvmSYs4cCpIBDRML2cVV3ycANQaXgrnvaHVA=; b=LNGcsjV6h0owqeK4yEYowF8vBc8+4QBsO0MdaeGazGqd/STS5r8uPi5rgF6Yvfcgpc VUa1PS4XqXAcj+aaf72ZyM4U0+1WXLB6wnSBHJGNYJIGs/RgUHx8VRmQlvJ3v8We8hhj XFD3vAERFFiDlY3TmHGVP3f1QHD5/Fi35zOTrMF7GQncZnsJFfTWp7F8AjRO4ADGIWx4 etJ5jpmV9kbCAu2EAqAe4Rj4wlt/cy7ZgFPI69Aw1rq3nQ6Mo262zHSNvczu4bo5OLUR XW0k74P8lN4Wg8ptGoy6ZOHqrNcZcg+7G/vkfVMq0gEx82gQLKwzC8sWMj+k6rYFcABt Nwaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=n8Mu9j7b; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id r13sm9622654pgl.90.2021.09.13.19.56.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 19:56:09 -0700 (PDT) From: Shawn Guo To: Stephen Boyd Cc: Rob Herring , Bjorn Andersson , Loic Poulain , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 3/3] clk: qcom: smd-rpm: Add QCM2290 RPM clock support Date: Tue, 14 Sep 2021 10:55:54 +0800 Message-Id: <20210914025554.5686-4-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210914025554.5686-1-shawn.guo@linaro.org> References: <20210914025554.5686-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for RPM-managed clocks on the QCM2290 platform. Signed-off-by: Shawn Guo --- drivers/clk/qcom/clk-smd-rpm.c | 59 ++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,rpmcc.h | 6 +++ include/linux/soc/qcom/smd-rpm.h | 2 + 3 files changed, 67 insertions(+) -- 2.17.1 diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 2380e45b6247..428830d800f6 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -1070,6 +1070,64 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { .num_clks = ARRAY_SIZE(sm6115_clks), }; +/* QCM2290 */ +DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, ln_bb_clk2, ln_bb_clk2_a, 0x2); +DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, rf_clk3_a, 6); + +DEFINE_CLK_SMD_RPM(qcm2290, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); +DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0); +DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0); +DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc_clk, cpuss_gnoc_a_clk, + QCOM_SMD_RPM_MEM_CLK, 1); +DEFINE_CLK_SMD_RPM(qcm2290, bimc_gpu_clk, bimc_gpu_a_clk, + QCOM_SMD_RPM_MEM_CLK, 2); + +static struct clk_smd_rpm *qcm2290_clks[] = { + [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, + [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk, + [RPM_SMD_LN_BB_CLK2] = &qcm2290_ln_bb_clk2, + [RPM_SMD_LN_BB_CLK2_A] = &qcm2290_ln_bb_clk2_a, + [RPM_SMD_RF_CLK3] = &qcm2290_rf_clk3, + [RPM_SMD_RF_CLK3_A] = &qcm2290_rf_clk3_a, + [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk, + [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, + [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, + [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk, + [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk, + [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, + [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, + [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, + [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk, + [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk, + [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk, + [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk, + [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, + [RPM_SMD_QPIC_CLK] = &qcm2290_qpic_clk, + [RPM_SMD_QPIC_CLK_A] = &qcm2290_qpic_a_clk, + [RPM_SMD_HWKM_CLK] = &qcm2290_hwkm_clk, + [RPM_SMD_HWKM_A_CLK] = &qcm2290_hwkm_a_clk, + [RPM_SMD_PKA_CLK] = &qcm2290_pka_clk, + [RPM_SMD_PKA_A_CLK] = &qcm2290_pka_a_clk, + [RPM_SMD_BIMC_GPU_CLK] = &qcm2290_bimc_gpu_clk, + [RPM_SMD_BIMC_GPU_A_CLK] = &qcm2290_bimc_gpu_a_clk, + [RPM_SMD_CPUSS_GNOC_CLK] = &qcm2290_cpuss_gnoc_clk, + [RPM_SMD_CPUSS_GNOC_A_CLK] = &qcm2290_cpuss_gnoc_a_clk, +}; + +static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = { + .clks = qcm2290_clks, + .num_clks = ARRAY_SIZE(qcm2290_clks), +}; + static const struct of_device_id rpm_smd_clk_match_table[] = { { .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 }, { .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 }, @@ -1082,6 +1140,7 @@ static const struct of_device_id rpm_smd_clk_match_table[] = { { .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 }, { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 }, { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 }, + { .compatible = "qcom,rpmcc-qcm2290", .data = &rpm_clk_qcm2290 }, { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 }, { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 }, { .compatible = "qcom,rpmcc-sm6115", .data = &rpm_clk_sm6115 }, diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index aa834d516234..fb624ff39273 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -159,5 +159,11 @@ #define RPM_SMD_SNOC_PERIPH_A_CLK 113 #define RPM_SMD_SNOC_LPASS_CLK 114 #define RPM_SMD_SNOC_LPASS_A_CLK 115 +#define RPM_SMD_HWKM_CLK 116 +#define RPM_SMD_HWKM_A_CLK 117 +#define RPM_SMD_PKA_CLK 118 +#define RPM_SMD_PKA_A_CLK 119 +#define RPM_SMD_CPUSS_GNOC_CLK 120 +#define RPM_SMD_CPUSS_GNOC_A_CLK 121 #endif diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h index 60e66fc9b6bf..860dd8cdf9f3 100644 --- a/include/linux/soc/qcom/smd-rpm.h +++ b/include/linux/soc/qcom/smd-rpm.h @@ -38,6 +38,8 @@ struct qcom_smd_rpm; #define QCOM_SMD_RPM_IPA_CLK 0x617069 #define QCOM_SMD_RPM_CE_CLK 0x6563 #define QCOM_SMD_RPM_AGGR_CLK 0x72676761 +#define QCOM_SMD_RPM_HWKM_CLK 0x6d6b7768 +#define QCOM_SMD_RPM_PKA_CLK 0x616b70 int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm, int state,