From patchwork Thu May 25 12:04:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100483 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp717729qge; Thu, 25 May 2017 04:34:46 -0700 (PDT) X-Received: by 10.98.65.26 with SMTP id o26mr44180801pfa.228.1495712086810; Thu, 25 May 2017 04:34:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495712086; cv=none; d=google.com; s=arc-20160816; b=W0nUdkVCASwifntb4OlcfydusIy6kIaHkAgBEoYYA/4Tmk80PTYrphHSIT/ZroiubP bEFa9iF6Vr/1D4biuRukwE8BE7BkBwtgA2npD/aXmkFs2spwMNu16e4Xn903iLBEzzHA cdcukPZeHnhaEfn3WwuAatxkaWPSwR+mOXN8NL6CJw8MLxjMFp+Mh532BBD3CLjPzSm/ yF9MZAAozOteAhOBsMsgjf+Bt+I7Jix7JLXN4U1XtB93z8jCWs2TCjDl+PlcACaftuhc 1nAYL0euioD3/8ffMBUnFa05SiQ7LVVPoAy1EcJ+PN1iwkO9/kdnozLDiFj3pY4CPH28 gQ2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=4Pep7ZyeMDlfuhXLRMkurEwtLRDkHm0fkdfkuIG7hMc=; b=z1EhkSlNVinEukZv04eZfOzw7Ms06ZOnYaO1jOy89Ody8Txpa52+w2IQTwi9KupDp9 Ml8Ao8Xs+MRIE1MsLt04bvAvKKri46CX+qrHQYOcNXBic5drvAk9+gDYADYFSXQVWMPC pmu/6GsjUdHzO700r/+FMpLQhZe++fyyOQ81uQ5pW5kWyXAmvLjIj7OUWwQzQguSD3dF GqZCBxu837UdZuNdE6ItXxAEPVFGnzs4VizCaLtynS8jJcg2oEQaTtNgMv51wF3sNVdd V/2eDgBXBSZ7VtboVkS7DC4PzbCV+reT4Bzs9AxI65Abi06qj4XralhDUu6iTIsN1Ey2 busg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g4si27543109pln.281.2017.05.25.04.34.46; Thu, 25 May 2017 04:34:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1764400AbdEYLem (ORCPT + 25 others); Thu, 25 May 2017 07:34:42 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:7260 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763563AbdEYLec (ORCPT ); Thu, 25 May 2017 07:34:32 -0400 Received: from 172.30.72.55 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APE94327; Thu, 25 May 2017 19:34:30 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:17 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH v2 01/22] scsi: hisi_sas: fix timeout check in hisi_sas_internal_task_abort() Date: Thu, 25 May 2017 20:04:50 +0800 Message-ID: <1495713911-80476-2-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.5926C146.0267, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: f44f105fc96f3e3f76e8a275d8deff0e Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen We need to check for timeout before task status, or the task will be mistook as completed internal abort command. Also add protection for sas_task.task_state_flags in hisi_sas_tmf_timedout(). Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_main.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index f720d3c..3605d28 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -691,8 +691,13 @@ static void hisi_sas_task_done(struct sas_task *task) static void hisi_sas_tmf_timedout(unsigned long data) { struct sas_task *task = (struct sas_task *)data; + unsigned long flags; + + spin_lock_irqsave(&task->task_state_lock, flags); + if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) + task->task_state_flags |= SAS_TASK_STATE_ABORTED; + spin_unlock_irqrestore(&task->task_state_lock, flags); - task->task_state_flags |= SAS_TASK_STATE_ABORTED; complete(&task->slow_task->completion); } @@ -1247,6 +1252,17 @@ static int hisi_sas_query_task(struct sas_task *task) wait_for_completion(&task->slow_task->completion); res = TMF_RESP_FUNC_FAILED; + /* Internal abort timed out */ + if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) { + if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) { + struct hisi_sas_slot *slot = task->lldd_task; + + if (slot) + slot->task = NULL; + dev_err(dev, "internal task abort: timeout.\n"); + } + } + if (task->task_status.resp == SAS_TASK_COMPLETE && task->task_status.stat == TMF_RESP_FUNC_COMPLETE) { res = TMF_RESP_FUNC_COMPLETE; @@ -1259,13 +1275,6 @@ static int hisi_sas_query_task(struct sas_task *task) goto exit; } - /* Internal abort timed out */ - if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) { - if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) { - dev_err(dev, "internal task abort: timeout.\n"); - } - } - exit: dev_dbg(dev, "internal task abort: task to dev %016llx task=%p " "resp: 0x%x sts 0x%x\n", From patchwork Thu May 25 12:04:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100506 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp720103qge; Thu, 25 May 2017 04:41:57 -0700 (PDT) X-Received: by 10.99.155.17 with SMTP id r17mr44623370pgd.193.1495712517662; Thu, 25 May 2017 04:41:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495712517; cv=none; d=google.com; s=arc-20160816; b=0jwGokmbxVJL3BIO0T97FEtRDKWg6oUUofuEZrl1W9MIqV8PNh6TkaPU02pDiGuEnt BgFd4VvvDN0CCe4sprTHo/nbTIuZaPeA6Flj04SIlYorFlE/ZLR2iErvV88npv93rN/f Nj/xIqAS6jmc9b+GZSrUCQWxl+nb9yrffhigyMMjed3nl9fx6LbIka6HVBRMmS4OTr1y yWpQq3lDBUzz0vBbwc2ss0xmu7HpjpOnpq6uTdMlO3i8rMRs/Jo/TSsHfWJMhC6IDUO/ exT5iL+4X1atpuR8BuL+zhiLYIH+DRImkvOYbluwk3fR3eBQtaP+qntTRNl4d6k+eNxc LYlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=2/t6d89rj5pDjfi4xUZmW46hyQ54nrNFZVnyXICVXPQ=; b=V8wsdDvh/VdCSvFGE1mM/AjMc1Dw5libt5E/+WMNfrvP3dpGACfcRp/GVs+/ik3+oS LGwGqIh/w4jhKPNjYClDII/pTPop2fRu01NiApq2y/OnZ4w4rIKtHhqElfDRR035+419 dKxxy7pmCXQDhigwsD25R0sEV2RkYe4WZ5aj6wHwQBP0Ej+NXGVnxdjPT+3WWphi+WYQ DraWjr7xofLA+jZTwcVPCjoPEL3hcWal8jtNxpKqzcLcco3xRMvAc9Bs5OOS39dDXTsZ kAbgEuPVzJtzpDBma1VKdazs06baosxwG3CT3p5UCkbOzL10cn4IxUn8swlNAmLSq+Ok kYeA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t128si28984295pgt.337.2017.05.25.04.41.57; Thu, 25 May 2017 04:41:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S968884AbdEYLlp (ORCPT + 25 others); Thu, 25 May 2017 07:41:45 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:7261 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763670AbdEYLed (ORCPT ); Thu, 25 May 2017 07:34:33 -0400 Received: from 172.30.72.55 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APE94328; Thu, 25 May 2017 19:34:30 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:17 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH v2 02/22] scsi: hisi_sas: optimise the usage of hisi_hba.lock Date: Thu, 25 May 2017 20:04:51 +0800 Message-ID: <1495713911-80476-3-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.5926C147.009E, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 85e64c748b790d2f64584209c6addc87 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Currently hisi_hba.lock is locked to deliver and receive a command to/from any hw queue. This causes much contention at high data-rates. To boost performance, lock on a per queue basis for sending and receiving commands to/from hw. Certain critical regions still need to be locked in the delivery and completion stages with hisi_hba.lock. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 8 ++--- drivers/scsi/hisi_sas/hisi_sas_main.c | 59 ++++++++++++++++++++++------------ drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 23 +++++-------- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 30 ++++++++--------- 4 files changed, 64 insertions(+), 56 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 4e28f32..88f06be 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -102,8 +102,10 @@ struct hisi_sas_cq { struct hisi_sas_dq { struct hisi_hba *hisi_hba; + spinlock_t lock; int wr_point; int id; + struct hisi_sas_slot *slot_prep; }; struct hisi_sas_device { @@ -154,9 +156,8 @@ struct hisi_sas_hw { struct domain_device *device); struct hisi_sas_device *(*alloc_dev)(struct domain_device *device); void (*sl_notify)(struct hisi_hba *hisi_hba, int phy_no); - int (*get_free_slot)(struct hisi_hba *hisi_hba, u32 dev_id, - int *q, int *s); - void (*start_delivery)(struct hisi_hba *hisi_hba); + int (*get_free_slot)(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq); + void (*start_delivery)(struct hisi_sas_dq *dq); int (*prep_ssp)(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot, int is_tmf, struct hisi_sas_tmf_task *tmf); @@ -217,7 +218,6 @@ struct hisi_hba { struct hisi_sas_port port[HISI_SAS_MAX_PHYS]; int queue_count; - struct hisi_sas_slot *slot_prep; struct dma_pool *sge_page_pool; struct hisi_sas_device devices[HISI_SAS_MAX_DEVICES]; diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 3605d28..d1b7dbf 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -179,10 +179,11 @@ static void hisi_sas_slot_abort(struct work_struct *work) task->task_done(task); } -static int hisi_sas_task_prep(struct sas_task *task, struct hisi_hba *hisi_hba, - int is_tmf, struct hisi_sas_tmf_task *tmf, - int *pass) +static int hisi_sas_task_prep(struct sas_task *task, struct hisi_sas_dq + *dq, int is_tmf, struct hisi_sas_tmf_task *tmf, + int *pass) { + struct hisi_hba *hisi_hba = dq->hisi_hba; struct domain_device *device = task->dev; struct hisi_sas_device *sas_dev = device->lldd_dev; struct hisi_sas_port *port; @@ -240,18 +241,24 @@ static int hisi_sas_task_prep(struct sas_task *task, struct hisi_hba *hisi_hba, } else n_elem = task->num_scatter; + spin_lock_irqsave(&hisi_hba->lock, flags); if (hisi_hba->hw->slot_index_alloc) rc = hisi_hba->hw->slot_index_alloc(hisi_hba, &slot_idx, device); else rc = hisi_sas_slot_index_alloc(hisi_hba, &slot_idx); - if (rc) + if (rc) { + spin_unlock_irqrestore(&hisi_hba->lock, flags); goto err_out; - rc = hisi_hba->hw->get_free_slot(hisi_hba, sas_dev->device_id, - &dlvry_queue, &dlvry_queue_slot); + } + spin_unlock_irqrestore(&hisi_hba->lock, flags); + + rc = hisi_hba->hw->get_free_slot(hisi_hba, dq); if (rc) goto err_out_tag; + dlvry_queue = dq->id; + dlvry_queue_slot = dq->wr_point; slot = &hisi_hba->slot_info[slot_idx]; memset(slot, 0, sizeof(struct hisi_sas_slot)); @@ -316,7 +323,7 @@ static int hisi_sas_task_prep(struct sas_task *task, struct hisi_hba *hisi_hba, task->task_state_flags |= SAS_TASK_AT_INITIATOR; spin_unlock_irqrestore(&task->task_state_lock, flags); - hisi_hba->slot_prep = slot; + dq->slot_prep = slot; atomic64_inc(&sas_dev->running_req); ++(*pass); @@ -354,19 +361,23 @@ static int hisi_sas_task_exec(struct sas_task *task, gfp_t gfp_flags, unsigned long flags; struct hisi_hba *hisi_hba = dev_to_hisi_hba(task->dev); struct device *dev = &hisi_hba->pdev->dev; + struct domain_device *device = task->dev; + struct hisi_sas_device *sas_dev = device->lldd_dev; + int queue_id = sas_dev->device_id % hisi_hba->queue_count; + struct hisi_sas_dq *dq = &hisi_hba->dq[queue_id]; if (unlikely(test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))) return -EINVAL; /* protect task_prep and start_delivery sequence */ - spin_lock_irqsave(&hisi_hba->lock, flags); - rc = hisi_sas_task_prep(task, hisi_hba, is_tmf, tmf, &pass); + spin_lock_irqsave(&dq->lock, flags); + rc = hisi_sas_task_prep(task, dq, is_tmf, tmf, &pass); if (rc) dev_err(dev, "task exec: failed[%d]!\n", rc); if (likely(pass)) - hisi_hba->hw->start_delivery(hisi_hba); - spin_unlock_irqrestore(&hisi_hba->lock, flags); + hisi_hba->hw->start_delivery(dq); + spin_unlock_irqrestore(&dq->lock, flags); return rc; } @@ -1142,6 +1153,8 @@ static int hisi_sas_query_task(struct sas_task *task) struct hisi_sas_cmd_hdr *cmd_hdr_base; int dlvry_queue_slot, dlvry_queue, n_elem = 0, rc, slot_idx; unsigned long flags; + int queue_id = sas_dev->device_id % hisi_hba->queue_count; + struct hisi_sas_dq *dq = &hisi_hba->dq[queue_id]; if (unlikely(test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))) return -EINVAL; @@ -1152,14 +1165,22 @@ static int hisi_sas_query_task(struct sas_task *task) port = to_hisi_sas_port(sas_port); /* simply get a slot and send abort command */ + spin_lock_irqsave(&hisi_hba->lock, flags); rc = hisi_sas_slot_index_alloc(hisi_hba, &slot_idx); - if (rc) + if (rc) { + spin_unlock_irqrestore(&hisi_hba->lock, flags); goto err_out; - rc = hisi_hba->hw->get_free_slot(hisi_hba, sas_dev->device_id, - &dlvry_queue, &dlvry_queue_slot); + } + spin_unlock_irqrestore(&hisi_hba->lock, flags); + + spin_lock_irqsave(&dq->lock, flags); + rc = hisi_hba->hw->get_free_slot(hisi_hba, dq); if (rc) goto err_out_tag; + dlvry_queue = dq->id; + dlvry_queue_slot = dq->wr_point; + slot = &hisi_hba->slot_info[slot_idx]; memset(slot, 0, sizeof(struct hisi_sas_slot)); @@ -1186,18 +1207,20 @@ static int hisi_sas_query_task(struct sas_task *task) task->task_state_flags |= SAS_TASK_AT_INITIATOR; spin_unlock_irqrestore(&task->task_state_lock, flags); - hisi_hba->slot_prep = slot; + dq->slot_prep = slot; atomic64_inc(&sas_dev->running_req); /* send abort command to our chip */ - hisi_hba->hw->start_delivery(hisi_hba); + hisi_hba->hw->start_delivery(dq); + spin_unlock_irqrestore(&dq->lock, flags); return 0; err_out_tag: hisi_sas_slot_index_free(hisi_hba, slot_idx); err_out: + spin_unlock_irqrestore(&dq->lock, flags); dev_err(dev, "internal abort task prep: failed[%d]!\n", rc); return rc; @@ -1221,7 +1244,6 @@ static int hisi_sas_query_task(struct sas_task *task) struct hisi_sas_device *sas_dev = device->lldd_dev; struct device *dev = &hisi_hba->pdev->dev; int res; - unsigned long flags; if (!hisi_hba->hw->prep_abort) return -EOPNOTSUPP; @@ -1238,11 +1260,8 @@ static int hisi_sas_query_task(struct sas_task *task) task->slow_task->timer.expires = jiffies + msecs_to_jiffies(110); add_timer(&task->slow_task->timer); - /* Lock as we are alloc'ing a slot, which cannot be interrupted */ - spin_lock_irqsave(&hisi_hba->lock, flags); res = hisi_sas_internal_abort_task_exec(hisi_hba, sas_dev->device_id, task, abort_flag, tag); - spin_unlock_irqrestore(&hisi_hba->lock, flags); if (res) { del_timer(&task->slow_task->timer); dev_err(dev, "internal task abort: executing internal task failed: %d\n", diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c index fc1c1b2..7d7d2a7 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c @@ -900,22 +900,17 @@ static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id) return bitmap; } -/** - * This function allocates across all queues to load balance. - * Slots are allocated from queues in a round-robin fashion. - * +/* * The callpath to this function and upto writing the write * queue pointer should be safe from interruption. */ -static int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, u32 dev_id, - int *q, int *s) +static int +get_free_slot_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) { struct device *dev = &hisi_hba->pdev->dev; - struct hisi_sas_dq *dq; + int queue = dq->id; u32 r, w; - int queue = dev_id % hisi_hba->queue_count; - dq = &hisi_hba->dq[queue]; w = dq->wr_point; r = hisi_sas_read32_relaxed(hisi_hba, DLVRY_Q_0_RD_PTR + (queue * 0x14)); @@ -924,16 +919,14 @@ static int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, u32 dev_id, return -EAGAIN; } - *q = queue; - *s = w; return 0; } -static void start_delivery_v1_hw(struct hisi_hba *hisi_hba) +static void start_delivery_v1_hw(struct hisi_sas_dq *dq) { - int dlvry_queue = hisi_hba->slot_prep->dlvry_queue; - int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot; - struct hisi_sas_dq *dq = &hisi_hba->dq[dlvry_queue]; + struct hisi_hba *hisi_hba = dq->hisi_hba; + int dlvry_queue = dq->slot_prep->dlvry_queue; + int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot; dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS; hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index e241921..193cc43 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -1454,22 +1454,17 @@ static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id) return bitmap; } -/** - * This function allocates across all queues to load balance. - * Slots are allocated from queues in a round-robin fashion. - * +/* * The callpath to this function and upto writing the write * queue pointer should be safe from interruption. */ -static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, u32 dev_id, - int *q, int *s) +static int +get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) { struct device *dev = &hisi_hba->pdev->dev; - struct hisi_sas_dq *dq; + int queue = dq->id; u32 r, w; - int queue = dev_id % hisi_hba->queue_count; - dq = &hisi_hba->dq[queue]; w = dq->wr_point; r = hisi_sas_read32_relaxed(hisi_hba, DLVRY_Q_0_RD_PTR + (queue * 0x14)); @@ -1479,16 +1474,14 @@ static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, u32 dev_id, return -EAGAIN; } - *q = queue; - *s = w; return 0; } -static void start_delivery_v2_hw(struct hisi_hba *hisi_hba) +static void start_delivery_v2_hw(struct hisi_sas_dq *dq) { - int dlvry_queue = hisi_hba->slot_prep->dlvry_queue; - int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot; - struct hisi_sas_dq *dq = &hisi_hba->dq[dlvry_queue]; + struct hisi_hba *hisi_hba = dq->hisi_hba; + int dlvry_queue = dq->slot_prep->dlvry_queue; + int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot; dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS; hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), @@ -2344,7 +2337,9 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba, spin_lock_irqsave(&task->task_state_lock, flags); task->task_state_flags |= SAS_TASK_STATE_DONE; spin_unlock_irqrestore(&task->task_state_lock, flags); + spin_lock_irqsave(&hisi_hba->lock, flags); hisi_sas_slot_task_free(hisi_hba, task, slot); + spin_unlock_irqrestore(&hisi_hba->lock, flags); sts = ts->stat; if (task->task_done) @@ -3162,13 +3157,14 @@ static void cq_tasklet_v2_hw(unsigned long val) struct hisi_sas_complete_v2_hdr *complete_queue; u32 rd_point = cq->rd_point, wr_point, dev_id; int queue = cq->id; + struct hisi_sas_dq *dq = &hisi_hba->dq[queue]; if (unlikely(hisi_hba->reject_stp_links_msk)) phys_try_accept_stp_links_v2_hw(hisi_hba); complete_queue = hisi_hba->complete_hdr[queue]; - spin_lock(&hisi_hba->lock); + spin_lock(&dq->lock); wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + (0x14 * queue)); @@ -3218,7 +3214,7 @@ static void cq_tasklet_v2_hw(unsigned long val) /* update rd_point */ cq->rd_point = rd_point; hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); - spin_unlock(&hisi_hba->lock); + spin_unlock(&dq->lock); } static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p) From patchwork Thu May 25 12:04:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100485 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp717826qge; Thu, 25 May 2017 04:35:01 -0700 (PDT) X-Received: by 10.99.134.194 with SMTP id x185mr24609052pgd.174.1495712101618; Thu, 25 May 2017 04:35:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495712101; cv=none; d=google.com; s=arc-20160816; b=cYzwZoBbwQVjS2z7P1Iy+w5l4t9EbnxgcMSDPmi+/L2rYeS4tc1pdoj93feMpwR3hV u+TwSRmEztvobcQG7XUB8kjq6T8OffYCkDxJEcNyNiiPSjFr54rvsp25cA6wetUS+N10 yCd85pk2YW1W1tsvibSvFzzfgbcOpUiduDjvv9tHRiLctC/K+6GS5c5jpNZPdb6/+jG2 utIqe4UdPcnIg8nA020rbJrG8n4gSsKdYKxnN8C9cton1xeGLVjTyK6z9uGorl0hkGgs kaXLrvenKmCSJbLlQlDvO/nr0NrqCgeR2eQgFdvAu8oJLPfjuxRzz1X1NqRqSUXJjEGX BK4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[209.132.180.67]) by mx.google.com with ESMTP id n34si27636953pld.268.2017.05.25.04.35.01; Thu, 25 May 2017 04:35:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965463AbdEYLes (ORCPT + 25 others); Thu, 25 May 2017 07:34:48 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:7258 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763521AbdEYLec (ORCPT ); Thu, 25 May 2017 07:34:32 -0400 Received: from 172.30.72.55 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APE94325; Thu, 25 May 2017 19:34:30 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:18 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH v2 03/22] scsi: hisi_sas: relocate get_ata_protocol() Date: Thu, 25 May 2017 20:04:52 +0800 Message-ID: <1495713911-80476-4-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.5926C146.016F, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 8f91f2b263003f71ae5547d7f94e2b0f Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Relocate get_ata_protocol() to a common location, as future hw versions will require it. Also rename with "hisi_sas_" prefix for consistency. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 1 + drivers/scsi/hisi_sas/hisi_sas_main.c | 65 +++++++++++++++++++++++++++++++++ drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 67 +--------------------------------- 3 files changed, 68 insertions(+), 65 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 88f06be..02ec10b 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -355,6 +355,7 @@ struct hisi_sas_command_table_ssp { struct hisi_sas_command_table_stp stp; }; +extern u8 hisi_sas_get_ata_protocol(u8 cmd, int direction); extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port); extern int hisi_sas_probe(struct platform_device *pdev, const struct hisi_sas_hw *ops); diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index d1b7dbf..8fce20b 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -15,6 +15,12 @@ #define DEV_IS_GONE(dev) \ ((!dev) || (dev->dev_type == SAS_PHY_UNUSED)) +#define SATA_PROTOCOL_NONDATA 0x1 +#define SATA_PROTOCOL_PIO 0x2 +#define SATA_PROTOCOL_DMA 0x4 +#define SATA_PROTOCOL_FPDMA 0x8 +#define SATA_PROTOCOL_ATAPI 0x10 + static int hisi_sas_debug_issue_ssp_tmf(struct domain_device *device, u8 *lun, struct hisi_sas_tmf_task *tmf); static int @@ -23,6 +29,65 @@ static int hisi_sas_debug_issue_ssp_tmf(struct domain_device *device, int abort_flag, int tag); static int hisi_sas_softreset_ata_disk(struct domain_device *device); +u8 hisi_sas_get_ata_protocol(u8 cmd, int direction) +{ + switch (cmd) { + case ATA_CMD_FPDMA_WRITE: + case ATA_CMD_FPDMA_READ: + case ATA_CMD_FPDMA_RECV: + case ATA_CMD_FPDMA_SEND: + case ATA_CMD_NCQ_NON_DATA: + return SATA_PROTOCOL_FPDMA; + + case ATA_CMD_DOWNLOAD_MICRO: + case ATA_CMD_ID_ATA: + case ATA_CMD_PMP_READ: + case ATA_CMD_READ_LOG_EXT: + case ATA_CMD_PIO_READ: + case ATA_CMD_PIO_READ_EXT: + case ATA_CMD_PMP_WRITE: + case ATA_CMD_WRITE_LOG_EXT: + case ATA_CMD_PIO_WRITE: + case ATA_CMD_PIO_WRITE_EXT: + return SATA_PROTOCOL_PIO; + + case ATA_CMD_DSM: + case ATA_CMD_DOWNLOAD_MICRO_DMA: + case ATA_CMD_PMP_READ_DMA: + case ATA_CMD_PMP_WRITE_DMA: + case ATA_CMD_READ: + case ATA_CMD_READ_EXT: + case ATA_CMD_READ_LOG_DMA_EXT: + case ATA_CMD_READ_STREAM_DMA_EXT: + case ATA_CMD_TRUSTED_RCV_DMA: + case ATA_CMD_TRUSTED_SND_DMA: + case ATA_CMD_WRITE: + case ATA_CMD_WRITE_EXT: + case ATA_CMD_WRITE_FUA_EXT: + case ATA_CMD_WRITE_QUEUED: + case ATA_CMD_WRITE_LOG_DMA_EXT: + case ATA_CMD_WRITE_STREAM_DMA_EXT: + return SATA_PROTOCOL_DMA; + + case ATA_CMD_CHK_POWER: + case ATA_CMD_DEV_RESET: + case ATA_CMD_EDD: + case ATA_CMD_FLUSH: + case ATA_CMD_FLUSH_EXT: + case ATA_CMD_VERIFY: + case ATA_CMD_VERIFY_EXT: + case ATA_CMD_SET_FEATURES: + case ATA_CMD_STANDBY: + case ATA_CMD_STANDBYNOW1: + return SATA_PROTOCOL_NONDATA; + default: + if (direction == DMA_NONE) + return SATA_PROTOCOL_NONDATA; + return SATA_PROTOCOL_PIO; + } +} +EXPORT_SYMBOL_GPL(hisi_sas_get_ata_protocol); + static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device) { return device->port->ha->lldd_ha; diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 193cc43..397f01e 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -554,12 +554,6 @@ enum { #define DIR_TO_DEVICE 2 #define DIR_RESERVED 3 -#define SATA_PROTOCOL_NONDATA 0x1 -#define SATA_PROTOCOL_PIO 0x2 -#define SATA_PROTOCOL_DMA 0x4 -#define SATA_PROTOCOL_FPDMA 0x8 -#define SATA_PROTOCOL_ATAPI 0x10 - #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \ err_phase == 0x4 || err_phase == 0x8 ||\ err_phase == 0x6 || err_phase == 0xa) @@ -2348,64 +2342,6 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba, return sts; } -static u8 get_ata_protocol(u8 cmd, int direction) -{ - switch (cmd) { - case ATA_CMD_FPDMA_WRITE: - case ATA_CMD_FPDMA_READ: - case ATA_CMD_FPDMA_RECV: - case ATA_CMD_FPDMA_SEND: - case ATA_CMD_NCQ_NON_DATA: - return SATA_PROTOCOL_FPDMA; - - case ATA_CMD_DOWNLOAD_MICRO: - case ATA_CMD_ID_ATA: - case ATA_CMD_PMP_READ: - case ATA_CMD_READ_LOG_EXT: - case ATA_CMD_PIO_READ: - case ATA_CMD_PIO_READ_EXT: - case ATA_CMD_PMP_WRITE: - case ATA_CMD_WRITE_LOG_EXT: - case ATA_CMD_PIO_WRITE: - case ATA_CMD_PIO_WRITE_EXT: - return SATA_PROTOCOL_PIO; - - case ATA_CMD_DSM: - case ATA_CMD_DOWNLOAD_MICRO_DMA: - case ATA_CMD_PMP_READ_DMA: - case ATA_CMD_PMP_WRITE_DMA: - case ATA_CMD_READ: - case ATA_CMD_READ_EXT: - case ATA_CMD_READ_LOG_DMA_EXT: - case ATA_CMD_READ_STREAM_DMA_EXT: - case ATA_CMD_TRUSTED_RCV_DMA: - case ATA_CMD_TRUSTED_SND_DMA: - case ATA_CMD_WRITE: - case ATA_CMD_WRITE_EXT: - case ATA_CMD_WRITE_FUA_EXT: - case ATA_CMD_WRITE_QUEUED: - case ATA_CMD_WRITE_LOG_DMA_EXT: - case ATA_CMD_WRITE_STREAM_DMA_EXT: - return SATA_PROTOCOL_DMA; - - case ATA_CMD_CHK_POWER: - case ATA_CMD_DEV_RESET: - case ATA_CMD_EDD: - case ATA_CMD_FLUSH: - case ATA_CMD_FLUSH_EXT: - case ATA_CMD_VERIFY: - case ATA_CMD_VERIFY_EXT: - case ATA_CMD_SET_FEATURES: - case ATA_CMD_STANDBY: - case ATA_CMD_STANDBYNOW1: - return SATA_PROTOCOL_NONDATA; - default: - if (direction == DMA_NONE) - return SATA_PROTOCOL_NONDATA; - return SATA_PROTOCOL_PIO; - } -} - static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag) { struct ata_queued_cmd *qc = task->uldd_task; @@ -2460,7 +2396,8 @@ static int prep_ata_v2_hw(struct hisi_hba *hisi_hba, (task->ata_task.fis.control & ATA_SRST)) dw1 |= 1 << CMD_HDR_RESET_OFF; - dw1 |= (get_ata_protocol(task->ata_task.fis.command, task->data_dir)) + dw1 |= (hisi_sas_get_ata_protocol( + task->ata_task.fis.command, task->data_dir)) << CMD_HDR_FRAME_TYPE_OFF; dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; hdr->dw1 = cpu_to_le32(dw1); From patchwork Thu May 25 12:04:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100484 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp717817qge; 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[209.132.180.67]) by mx.google.com with ESMTP id n34si27636953pld.268.2017.05.25.04.35.00; Thu, 25 May 2017 04:35:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1764535AbdEYLeq (ORCPT + 25 others); Thu, 25 May 2017 07:34:46 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:6820 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763503AbdEYLec (ORCPT ); Thu, 25 May 2017 07:34:32 -0400 Received: from 172.30.72.55 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APE94319; Thu, 25 May 2017 19:34:28 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:18 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH v2 04/22] scsi: hisi_sas: relocate sata_done_v2_hw() Date: Thu, 25 May 2017 20:04:53 +0800 Message-ID: <1495713911-80476-5-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.5926C145.00C1, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 55070718844c03292957b06bdac53e6f Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Relocate get_ata_protocol() to a common location, as future hw versions will require it. Also rename with "hisi_sas_" prefix for consistency. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 2 ++ drivers/scsi/hisi_sas/hisi_sas_main.c | 15 +++++++++++++++ drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 18 ++---------------- 3 files changed, 19 insertions(+), 16 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 02ec10b..d0c0844 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -357,6 +357,8 @@ struct hisi_sas_command_table_ssp { extern u8 hisi_sas_get_ata_protocol(u8 cmd, int direction); extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port); +extern void hisi_sas_sata_done(struct sas_task *task, + struct hisi_sas_slot *slot); extern int hisi_sas_probe(struct platform_device *pdev, const struct hisi_sas_hw *ops); extern int hisi_sas_remove(struct platform_device *pdev); diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 8fce20b..3f2bb8e 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -88,6 +88,21 @@ u8 hisi_sas_get_ata_protocol(u8 cmd, int direction) } EXPORT_SYMBOL_GPL(hisi_sas_get_ata_protocol); +void hisi_sas_sata_done(struct sas_task *task, + struct hisi_sas_slot *slot) +{ + struct task_status_struct *ts = &task->task_status; + struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf; + struct dev_to_host_fis *d2h = slot->status_buffer + + sizeof(struct hisi_sas_err_record); + + resp->frame_len = sizeof(struct dev_to_host_fis); + memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis)); + + ts->buf_valid_size = sizeof(*resp); +} +EXPORT_SYMBOL_GPL(hisi_sas_sata_done); + static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device) { return device->port->ha->lldd_ha; diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 397f01e..51140dc 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -1679,20 +1679,6 @@ static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba, return 0; } -static void sata_done_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task, - struct hisi_sas_slot *slot) -{ - struct task_status_struct *ts = &task->task_status; - struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf; - struct dev_to_host_fis *d2h = slot->status_buffer + - sizeof(struct hisi_sas_err_record); - - resp->frame_len = sizeof(struct dev_to_host_fis); - memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis)); - - ts->buf_valid_size = sizeof(*resp); -} - #define TRANS_TX_ERR 0 #define TRANS_RX_ERR 1 #define DMA_TX_ERR 2 @@ -2185,7 +2171,7 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba, break; } } - sata_done_v2_hw(hisi_hba, task, slot); + hisi_sas_sata_done(task, slot); } break; default: @@ -2313,7 +2299,7 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba, case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: { ts->stat = SAM_STAT_GOOD; - sata_done_v2_hw(hisi_hba, task, slot); + hisi_sas_sata_done(task, slot); break; } default: From patchwork Thu May 25 12:04:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100510 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp720301qge; Thu, 25 May 2017 04:42:31 -0700 (PDT) X-Received: by 10.99.142.75 with SMTP id k72mr15850148pge.99.1495712551834; Thu, 25 May 2017 04:42:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495712551; cv=none; d=google.com; s=arc-20160816; b=kksv63/+/ufsMyHChjtKXcpLOhlETRZOfEDvqwUWbiwtyRj1rEQ5NiEu9fwkK5tdKg P1nEzc7L46FOsJf2MC3qkWV6tabRF82UNaOvlkGZRL5Po30wYtSjPTkCLsyduWMvGGde XSIrqN/K/TiE9ygxa2OG1bapaILiwDeKYvyCKKRaT9bGKMcRywijcWLQ/76vAkzsQIUO mV6sep7j5SIEmLdK6GptG6qtaCmDVk1Hx+StIJx3GJz17oq9YQldV+uR9yMF2IKmuxgz zA0kaSKk7TuXn8t0rZFv4dX8rgN7dlAnTcEZ8ww3Z2Wf1I7YmFL/rngCgUwv/kCKMIrE xHrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=fARftZx47N6bN4XxK9IK6BpmqI6294PHyXvaInfp3/E=; b=lORYkAXOpZqfuBGRhHKMvHb7aJAX0Zh+3WqMFlMOpwxhYbjMLRAHpG5hrYNcg4yWKa 8Bu8SsX7AFknhiel6q4ZNH+MSW6RNtSVrhniy3JhhTzkKa2TjoQ8BYkfKMPt5jKAfyWP xlZOzrEyb/sg6+LsQJ8hYCEQMpc/1l9oMkBqxeqkUO9zXQmxOxT7FefxtBYCl2oKXVot uaA6CqEjPr6ZigDVuHnh6EN8nbwL68lGTh+QF/Mdux0w6Uzxwj7zW7zkpZHfSbzZ3kyz A+p0Vn2XjLsz1ENDVbUpR3NVEgmzFU4l8pwheafrajoEC6nhq/4eG/ArL/2TJlRx+6jp NZDw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y63si27769704pfd.154.2017.05.25.04.42.31; Thu, 25 May 2017 04:42:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S968908AbdEYLlt (ORCPT + 25 others); Thu, 25 May 2017 07:41:49 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:7263 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763802AbdEYLed (ORCPT ); Thu, 25 May 2017 07:34:33 -0400 Received: from 172.30.72.55 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APE94332; Thu, 25 May 2017 19:34:31 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:18 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH v2 05/22] scsi: hisi_sas: relocate get_ncq_tag_v2_hw() Date: Thu, 25 May 2017 20:04:54 +0800 Message-ID: <1495713911-80476-6-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.5926C147.01F2, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 52f9b20acd31130a62aae5ada88992c0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Relocate get_ncq_tag_v2_hw() to a common location, as future hw versions will require it. Also rename with "hisi_sas_" prefix for consistency. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 1 + drivers/scsi/hisi_sas/hisi_sas_main.c | 15 +++++++++++++++ drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 16 +--------------- 3 files changed, 17 insertions(+), 15 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index d0c0844..210daec 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -359,6 +359,7 @@ struct hisi_sas_command_table_ssp { extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port); extern void hisi_sas_sata_done(struct sas_task *task, struct hisi_sas_slot *slot); +extern int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag); extern int hisi_sas_probe(struct platform_device *pdev, const struct hisi_sas_hw *ops); extern int hisi_sas_remove(struct platform_device *pdev); diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 3f2bb8e..aaa7f5d 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -103,6 +103,21 @@ void hisi_sas_sata_done(struct sas_task *task, } EXPORT_SYMBOL_GPL(hisi_sas_sata_done); +int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag) +{ + struct ata_queued_cmd *qc = task->uldd_task; + + if (qc) { + if (qc->tf.command == ATA_CMD_FPDMA_WRITE || + qc->tf.command == ATA_CMD_FPDMA_READ) { + *tag = qc->tag; + return 1; + } + } + return 0; +} +EXPORT_SYMBOL_GPL(hisi_sas_get_ncq_tag); + static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device) { return device->port->ha->lldd_ha; diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 51140dc..e64047c 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -2328,20 +2328,6 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba, return sts; } -static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag) -{ - struct ata_queued_cmd *qc = task->uldd_task; - - if (qc) { - if (qc->tf.command == ATA_CMD_FPDMA_WRITE || - qc->tf.command == ATA_CMD_FPDMA_READ) { - *tag = qc->tag; - return 1; - } - } - return 0; -} - static int prep_ata_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) { @@ -2389,7 +2375,7 @@ static int prep_ata_v2_hw(struct hisi_hba *hisi_hba, hdr->dw1 = cpu_to_le32(dw1); /* dw2 */ - if (task->ata_task.use_ncq && get_ncq_tag_v2_hw(task, &hdr_tag)) { + if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) { task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; } From patchwork Thu May 25 12:04:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100509 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp720232qge; Thu, 25 May 2017 04:42:20 -0700 (PDT) X-Received: by 10.99.95.79 with SMTP id t76mr44505501pgb.82.1495712540013; Thu, 25 May 2017 04:42:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495712540; cv=none; d=google.com; s=arc-20160816; b=tod3O5FwmxyuSGZGytsqbvHrP2uEuHOlbAFgWUE+Cyb7omnFM/OoPsCLSltn2j0UQT 4ioPfn9WuhADWaTDm+ATlZuK2b72luE46XLo08U23vnjtqAQhxmWqJdj9y735qiowLWX plz0+KNVIO0oKxZ2elTQ09xNY76OvLmJIUkO+gfbsyFjlBlt3I+Wv/OSQGv05RHYY07I 48sAOvkx0XfeQFHvMkTPw1kV3C3yx9Bl82qMzRR66roySSmfOLaED6u0nz7I3wRtANdy MFsCOyf8ewXWWFvjoVU48mkhmBz4WAbzBD4GrEJr1AcsJB9KnX8Nq5MAwkc07NJXsq4N Gclw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=acUKNTXJcICsQYx9nn5yJArVTG5wUD1YvdopB3diZ7k=; b=AendMKn9Nd5nqPeSlyeHhstYNZUevNYzcdOtGduRemUBgB8ahyYKpCSxRnwJLYfMFT L2zUaY4lFaod8cqOacb/1neVw8S/RqDpKUhBd7AZf5t/C6tCotmrNx41Ave3yICFzozW KjglPsil9pCZ5kUYpzjWseiwRdsR9gWIJa0drEdLNIYy/YHNqyVjaoPStEcWpj8Pyz/b k1seKqn44PH4hyW4rEr588dKmkkOi9dvpQamnkMXFhTKo2efVU4FdlGeNiPLvXeZhJet hegnZlnKtPkmjkPXvd96cdP4Xg7Y8nQ0q8aSLqiPNJDL5h3CVoBTJ1gGIGv/K81Ws8tV rXlA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y63si27769704pfd.154.2017.05.25.04.42.19; Thu, 25 May 2017 04:42:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423907AbdEYLlv (ORCPT + 25 others); Thu, 25 May 2017 07:41:51 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:7259 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763532AbdEYLed (ORCPT ); Thu, 25 May 2017 07:34:33 -0400 Received: from 172.30.72.55 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APE94324; Thu, 25 May 2017 19:34:29 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:19 +0800 From: John Garry To: , CC: , , , , , John Garry , Xiang Chen Subject: [PATCH v2 06/22] scsi: hisi_sas: add pci_dev in hisi_hba struct Date: Thu, 25 May 2017 20:04:55 +0800 Message-ID: <1495713911-80476-7-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.5926C146.00F1, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 1749447ae835378c0d98b1c03d226b51 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since hip08 SAS controller is based on pci device, add hisi_hba.pci_dev for hip08 (will be v3), and also rename hisi_hba.pdev to .platform_dev for clarity. In addition, for common code which wants to reference the controller device struct, add hisi_hba.dev, and change the common code to use it. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas.h | 6 ++++- drivers/scsi/hisi_sas/hisi_sas_main.c | 36 ++++++++++++++-------------- drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 28 +++++++++++----------- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 44 +++++++++++++++++----------------- 4 files changed, 59 insertions(+), 55 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 210daec..18044b7 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -189,7 +190,10 @@ struct hisi_hba { /* This must be the first element, used by SHOST_TO_SAS_HA */ struct sas_ha_struct *p; - struct platform_device *pdev; + struct platform_device *platform_dev; + struct pci_dev *pci_dev; + struct device *dev; + void __iomem *regs; struct regmap *ctrl; u32 ctrl_reset_reg; diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index aaa7f5d..d4809cf 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -174,7 +174,7 @@ void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba, struct sas_task *task, { if (task) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct domain_device *device = task->dev; struct hisi_sas_device *sas_dev = device->lldd_dev; @@ -251,7 +251,7 @@ static void hisi_sas_slot_abort(struct work_struct *work) struct scsi_cmnd *cmnd = task->uldd_task; struct hisi_sas_tmf_task tmf_task; struct scsi_lun lun; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int tag = abort_slot->idx; unsigned long flags; @@ -285,7 +285,7 @@ static int hisi_sas_task_prep(struct sas_task *task, struct hisi_sas_dq struct hisi_sas_slot *slot; struct hisi_sas_cmd_hdr *cmd_hdr_base; struct asd_sas_port *sas_port = device->port; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int dlvry_queue_slot, dlvry_queue, n_elem = 0, rc, slot_idx; unsigned long flags; @@ -455,7 +455,7 @@ static int hisi_sas_task_exec(struct sas_task *task, gfp_t gfp_flags, u32 pass = 0; unsigned long flags; struct hisi_hba *hisi_hba = dev_to_hisi_hba(task->dev); - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct domain_device *device = task->dev; struct hisi_sas_device *sas_dev = device->lldd_dev; int queue_id = sas_dev->device_id % hisi_hba->queue_count; @@ -547,7 +547,7 @@ static int hisi_sas_dev_found(struct domain_device *device) struct hisi_hba *hisi_hba = dev_to_hisi_hba(device); struct domain_device *parent_dev = device->parent; struct hisi_sas_device *sas_dev; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; if (hisi_hba->hw->alloc_dev) sas_dev = hisi_hba->hw->alloc_dev(device); @@ -732,7 +732,7 @@ static void hisi_sas_dev_gone(struct domain_device *device) { struct hisi_sas_device *sas_dev = device->lldd_dev; struct hisi_hba *hisi_hba = dev_to_hisi_hba(device); - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u64 dev_id = sas_dev->device_id; dev_info(dev, "found dev[%lld:%x] is gone\n", @@ -815,7 +815,7 @@ static int hisi_sas_exec_internal_tmf_task(struct domain_device *device, { struct hisi_sas_device *sas_dev = device->lldd_dev; struct hisi_hba *hisi_hba = sas_dev->hisi_hba; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct sas_task *task; int res, retry; @@ -932,7 +932,7 @@ static int hisi_sas_softreset_ata_disk(struct domain_device *device) struct ata_link *link; int rc = TMF_RESP_FUNC_FAILED; struct hisi_hba *hisi_hba = dev_to_hisi_hba(device); - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int s = sizeof(struct host_to_dev_fis); unsigned long flags; @@ -990,7 +990,7 @@ static int hisi_sas_controller_reset(struct hisi_hba *hisi_hba) return -1; if (!test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct sas_ha_struct *sas_ha = &hisi_hba->sha; unsigned long flags; @@ -1023,7 +1023,7 @@ static int hisi_sas_abort_task(struct sas_task *task) struct domain_device *device = task->dev; struct hisi_sas_device *sas_dev = device->lldd_dev; struct hisi_hba *hisi_hba = dev_to_hisi_hba(task->dev); - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int rc = TMF_RESP_FUNC_FAILED; unsigned long flags; @@ -1152,7 +1152,7 @@ static int hisi_sas_lu_reset(struct domain_device *device, u8 *lun) { struct hisi_sas_device *sas_dev = device->lldd_dev; struct hisi_hba *hisi_hba = dev_to_hisi_hba(device); - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; unsigned long flags; int rc = TMF_RESP_FUNC_FAILED; @@ -1241,7 +1241,7 @@ static int hisi_sas_query_task(struct sas_task *task) { struct domain_device *device = task->dev; struct hisi_sas_device *sas_dev = device->lldd_dev; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct hisi_sas_port *port; struct hisi_sas_slot *slot; struct asd_sas_port *sas_port = device->port; @@ -1337,7 +1337,7 @@ static int hisi_sas_query_task(struct sas_task *task) { struct sas_task *task; struct hisi_sas_device *sas_dev = device->lldd_dev; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int res; if (!hisi_hba->hw->prep_abort) @@ -1547,8 +1547,7 @@ void hisi_sas_init_mem(struct hisi_hba *hisi_hba) static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost) { - struct platform_device *pdev = hisi_hba->pdev; - struct device *dev = &pdev->dev; + struct device *dev = hisi_hba->dev; int i, s, max_command_entries = hisi_hba->hw->max_command_entries; spin_lock_init(&hisi_hba->lock); @@ -1668,7 +1667,7 @@ static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost) static void hisi_sas_free(struct hisi_hba *hisi_hba) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int i, s, max_command_entries = hisi_hba->hw->max_command_entries; for (i = 0; i < hisi_hba->queue_count; i++) { @@ -1749,7 +1748,8 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev, INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); hisi_hba->hw = hw; - hisi_hba->pdev = pdev; + hisi_hba->platform_dev = pdev; + hisi_hba->dev = dev; hisi_hba->shost = shost; SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; @@ -1866,7 +1866,7 @@ int hisi_sas_probe(struct platform_device *pdev, shost->cmd_per_lun = hisi_hba->hw->max_command_entries; sha->sas_ha_name = DRV_NAME; - sha->dev = &hisi_hba->pdev->dev; + sha->dev = hisi_hba->dev; sha->lldd_module = THIS_MODULE; sha->sas_addr = &hisi_hba->sas_addr[0]; sha->num_phys = hisi_hba->n_phy; diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c index 7d7d2a7..afa87d4 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c @@ -505,7 +505,7 @@ static void setup_itct_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_device *sas_dev) { struct domain_device *device = sas_dev->sas_device; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u64 qw0, device_id = sas_dev->device_id; struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; struct asd_sas_port *sas_port = device->port; @@ -571,7 +571,7 @@ static int reset_hw_v1_hw(struct hisi_hba *hisi_hba) int i; unsigned long end_time; u32 val; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; for (i = 0; i < hisi_hba->n_phy; i++) { u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL); @@ -756,7 +756,7 @@ static void init_reg_v1_hw(struct hisi_hba *hisi_hba) static int hw_init_v1_hw(struct hisi_hba *hisi_hba) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int rc; rc = reset_hw_v1_hw(hisi_hba); @@ -907,7 +907,7 @@ static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id) static int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int queue = dq->id; u32 r, w; @@ -939,7 +939,7 @@ static int prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba, struct scatterlist *scatter, int n_elem) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct scatterlist *sg; int i; @@ -976,7 +976,7 @@ static int prep_smp_v1_hw(struct hisi_hba *hisi_hba, struct sas_task *task = slot->task; struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; struct domain_device *device = task->dev; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct hisi_sas_port *port = slot->port; struct scatterlist *sg_req, *sg_resp; struct hisi_sas_device *sas_dev = device->lldd_dev; @@ -1148,7 +1148,7 @@ static void slot_err_v1_hw(struct hisi_hba *hisi_hba, { struct task_status_struct *ts = &task->task_status; struct hisi_sas_err_record_v1 *err_record = slot->status_buffer; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; switch (task->task_proto) { case SAS_PROTOCOL_SSP: @@ -1274,7 +1274,7 @@ static int slot_complete_v1_hw(struct hisi_hba *hisi_hba, { struct sas_task *task = slot->task; struct hisi_sas_device *sas_dev; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct task_status_struct *ts; struct domain_device *device; enum exec_status sts; @@ -1423,7 +1423,7 @@ static irqreturn_t int_phyup_v1_hw(int irq_no, void *p) { struct hisi_sas_phy *phy = p; struct hisi_hba *hisi_hba = phy->hisi_hba; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct asd_sas_phy *sas_phy = &phy->sas_phy; int i, phy_no = sas_phy->id; u32 irq_value, context, port_id, link_rate; @@ -1504,7 +1504,7 @@ static irqreturn_t int_bcast_v1_hw(int irq, void *p) struct hisi_hba *hisi_hba = phy->hisi_hba; struct asd_sas_phy *sas_phy = &phy->sas_phy; struct sas_ha_struct *sha = &hisi_hba->sha; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int phy_no = sas_phy->id; u32 irq_value; irqreturn_t res = IRQ_HANDLED; @@ -1531,7 +1531,7 @@ static irqreturn_t int_abnormal_v1_hw(int irq, void *p) { struct hisi_sas_phy *phy = p; struct hisi_hba *hisi_hba = phy->hisi_hba; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct asd_sas_phy *sas_phy = &phy->sas_phy; u32 irq_value, irq_mask_old; int phy_no = sas_phy->id; @@ -1634,7 +1634,7 @@ static irqreturn_t cq_interrupt_v1_hw(int irq, void *p) static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p) { struct hisi_hba *hisi_hba = p; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR); if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) { @@ -1693,7 +1693,7 @@ static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p) static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p) { struct hisi_hba *hisi_hba = p; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2); u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO); @@ -1731,7 +1731,7 @@ static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p) static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba) { - struct platform_device *pdev = hisi_hba->pdev; + struct platform_device *pdev = hisi_hba->platform_dev; struct device *dev = &pdev->dev; int i, j, irq, rc, idx; diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index e64047c..e4cd86a 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -653,7 +653,7 @@ static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx) { unsigned int index; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; void *bitmap = hisi_hba->sata_dev_bitmap; index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW); @@ -750,7 +750,7 @@ static void setup_itct_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_device *sas_dev) { struct domain_device *device = sas_dev->sas_device; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u64 qw0, device_id = sas_dev->device_id; struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; struct domain_device *parent_dev = device->parent; @@ -803,7 +803,7 @@ static void free_device_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_device *sas_dev) { u64 dev_id = sas_dev->device_id; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); int i; @@ -847,7 +847,7 @@ static int reset_hw_v2_hw(struct hisi_hba *hisi_hba) int i, reset_val; u32 val; unsigned long end_time; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; /* The mask needs to be set depending on the number of phys */ if (hisi_hba->n_phy == 9) @@ -983,7 +983,7 @@ static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba) static void init_reg_v2_hw(struct hisi_hba *hisi_hba) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int i; /* Global registers init */ @@ -1164,7 +1164,7 @@ static void set_link_timer_quirk(struct hisi_hba *hisi_hba) static int hw_init_v2_hw(struct hisi_hba *hisi_hba) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int rc; rc = reset_hw_v2_hw(hisi_hba); @@ -1213,7 +1213,7 @@ static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no) static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { int i, max_loop = 1000; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u32 status, axi_status, dfx_val, dfx_tx_val; for (i = 0; i < max_loop; i++) { @@ -1239,7 +1239,7 @@ static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no) static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { int i, max_loop = 1000; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u32 status, tx_dfx0; for (i = 0; i < max_loop; i++) { @@ -1277,7 +1277,7 @@ static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { u32 cfg, axi_val, dfx0_val, txid_auto; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; /* Close axi bus. */ axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + @@ -1455,7 +1455,7 @@ static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id) static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int queue = dq->id; u32 r, w; @@ -1488,7 +1488,7 @@ static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba, struct scatterlist *scatter, int n_elem) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct scatterlist *sg; int i; @@ -1525,7 +1525,7 @@ static int prep_smp_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task = slot->task; struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; struct domain_device *device = task->dev; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct hisi_sas_port *port = slot->port; struct scatterlist *sg_req, *sg_resp; struct hisi_sas_device *sas_dev = device->lldd_dev; @@ -2184,7 +2184,7 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba, { struct sas_task *task = slot->task; struct hisi_sas_device *sas_dev; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct task_status_struct *ts; struct domain_device *device; enum exec_status sts; @@ -2482,7 +2482,7 @@ static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba) u32 port_id, link_rate, hard_phy_linkrate; struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; struct asd_sas_phy *sas_phy = &phy->sas_phy; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd; @@ -2669,7 +2669,7 @@ static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba) static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p) { struct hisi_hba *hisi_hba = p; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u32 ent_msk, ent_tmp, irq_msk; int phy_no = 0; @@ -2729,7 +2729,7 @@ static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p) static void one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u32 reg_val; if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF)) { @@ -2818,7 +2818,7 @@ static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value) { u32 reg_val; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF)) { reg_val = hisi_sas_read32(hisi_hba, HGC_DQE_ECC_ADDR); @@ -2968,7 +2968,7 @@ static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p) { struct hisi_hba *hisi_hba = p; u32 irq_value, irq_msk, err_value; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe); @@ -3144,7 +3144,7 @@ static irqreturn_t sata_int_v2_hw(int irq_no, void *p) struct hisi_sas_phy *phy = p; struct hisi_hba *hisi_hba = phy->hisi_hba; struct asd_sas_phy *sas_phy = &phy->sas_phy; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct hisi_sas_initial_fis *initial_fis; struct dev_to_host_fis *fis; u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate; @@ -3246,7 +3246,7 @@ static irqreturn_t sata_int_v2_hw(int irq_no, void *p) */ static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba) { - struct platform_device *pdev = hisi_hba->pdev; + struct platform_device *pdev = hisi_hba->platform_dev; struct device *dev = &pdev->dev; int i, irq, rc, irq_map[128]; @@ -3360,7 +3360,7 @@ static int hisi_sas_v2_init(struct hisi_hba *hisi_hba) static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba) { - struct platform_device *pdev = hisi_hba->pdev; + struct platform_device *pdev = hisi_hba->platform_dev; int i; for (i = 0; i < hisi_hba->queue_count; i++) @@ -3382,7 +3382,7 @@ static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba) static int soft_reset_v2_hw(struct hisi_hba *hisi_hba) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u32 old_state, state; int rc, cnt; int phy_no; From patchwork Thu May 25 12:04:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100482 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp717699qge; Thu, 25 May 2017 04:34:41 -0700 (PDT) X-Received: by 10.98.7.68 with SMTP id b65mr44811269pfd.123.1495712081693; Thu, 25 May 2017 04:34:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495712081; cv=none; d=google.com; s=arc-20160816; b=s3UIkqesZzVwxXog/NHCpR5ULsSxcwsCu4nrKCErSBgxW+uqJ2oKxqXiAp1yrAzCz1 W+YHads2y4Ud6ETBvTPMlxKcv5h+tcSoIVMxkZRZU2i5CPeutEYh0JKvXoL/ZQ+d787I 2CAykLIzqZNI1YmqxqO1ySfJgLxjuhmAj2WdecY1nKxu54yCwVas4iClsPygfiqT5uBw 1RTqyfVBe1sulWUJtkd2MPhF8dLkBTVqORfxHV0PKRv9jNQ2+0aGoNNa0dd7JZ/BTfl/ 4eo0e9a5HVMrQJifUHqZqhn0ZjGGnqEEemzNwgKyhfTPNZ3crV4rMQWodf8m3Lhu3X+T H7Tg== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id v4si28122544pfi.95.2017.05.25.04.34.41; Thu, 25 May 2017 04:34:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1764281AbdEYLei (ORCPT + 25 others); Thu, 25 May 2017 07:34:38 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:7257 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763519AbdEYLec (ORCPT ); Thu, 25 May 2017 07:34:32 -0400 Received: from 172.30.72.55 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APE94323; Thu, 25 May 2017 19:34:29 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:19 +0800 From: John Garry To: , CC: , , , , , John Garry Subject: [PATCH v2 07/22] scsi: hisi_sas: create hisi_sas_get_fw_info() Date: Thu, 25 May 2017 20:04:56 +0800 Message-ID: <1495713911-80476-8-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.5926C145.02DD, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: fc4c588253f5b366b44f8aad6ad76626 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Move the functionality to retrieve the fw info into a dedicated device type-agnostic function, hisi_sas_get_fw_info(). The reasoning is that this function will be required for future pci-based platforms. Also add some debug prints for failure. Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 1 + drivers/scsi/hisi_sas/hisi_sas_main.c | 103 ++++++++++++++++++++++------------ 2 files changed, 67 insertions(+), 37 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 18044b7..d029aba 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -364,6 +364,7 @@ struct hisi_sas_command_table_ssp { extern void hisi_sas_sata_done(struct sas_task *task, struct hisi_sas_slot *slot); extern int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag); +extern int hisi_sas_get_fw_info(struct hisi_hba *hisi_hba); extern int hisi_sas_probe(struct platform_device *pdev, const struct hisi_sas_hw *ops); extern int hisi_sas_remove(struct platform_device *pdev); diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index d4809cf..58c6cf0 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -1729,66 +1729,95 @@ static void hisi_sas_rst_work_handler(struct work_struct *work) hisi_sas_controller_reset(hisi_hba); } -static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev, - const struct hisi_sas_hw *hw) +int hisi_sas_get_fw_info(struct hisi_hba *hisi_hba) { - struct resource *res; - struct Scsi_Host *shost; - struct hisi_hba *hisi_hba; - struct device *dev = &pdev->dev; - struct device_node *np = pdev->dev.of_node; + struct device *dev = hisi_hba->dev; + struct platform_device *pdev = hisi_hba->platform_dev; + struct device_node *np = pdev ? pdev->dev.of_node : NULL; struct clk *refclk; - shost = scsi_host_alloc(&hisi_sas_sht, sizeof(*hisi_hba)); - if (!shost) { - dev_err(dev, "scsi host alloc failed\n"); - return NULL; - } - hisi_hba = shost_priv(shost); - - INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); - hisi_hba->hw = hw; - hisi_hba->platform_dev = pdev; - hisi_hba->dev = dev; - hisi_hba->shost = shost; - SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; - - init_timer(&hisi_hba->timer); - if (device_property_read_u8_array(dev, "sas-addr", hisi_hba->sas_addr, - SAS_ADDR_SIZE)) - goto err_out; + SAS_ADDR_SIZE)) { + dev_err(dev, "could not get property sas-addr\n"); + return -ENOENT; + } if (np) { hisi_hba->ctrl = syscon_regmap_lookup_by_phandle(np, "hisilicon,sas-syscon"); - if (IS_ERR(hisi_hba->ctrl)) - goto err_out; + if (IS_ERR(hisi_hba->ctrl)) { + dev_err(dev, "could not get syscon\n"); + return -ENOENT; + } if (device_property_read_u32(dev, "ctrl-reset-reg", - &hisi_hba->ctrl_reset_reg)) - goto err_out; + &hisi_hba->ctrl_reset_reg)) { + dev_err(dev, + "could not get property ctrl-reset-reg\n"); + return -ENOENT; + } if (device_property_read_u32(dev, "ctrl-reset-sts-reg", - &hisi_hba->ctrl_reset_sts_reg)) - goto err_out; + &hisi_hba->ctrl_reset_sts_reg)) { + dev_err(dev, + "could not get property ctrl-reset-sts-reg\n"); + return -ENOENT; + } if (device_property_read_u32(dev, "ctrl-clock-ena-reg", - &hisi_hba->ctrl_clock_ena_reg)) - goto err_out; + &hisi_hba->ctrl_clock_ena_reg)) { + dev_err(dev, + "could not get property ctrl-clock-ena-reg\n"); + return -ENOENT; + } } - refclk = devm_clk_get(&pdev->dev, NULL); + refclk = devm_clk_get(dev, NULL); if (IS_ERR(refclk)) dev_dbg(dev, "no ref clk property\n"); else hisi_hba->refclk_frequency_mhz = clk_get_rate(refclk) / 1000000; - if (device_property_read_u32(dev, "phy-count", &hisi_hba->n_phy)) - goto err_out; + if (device_property_read_u32(dev, "phy-count", &hisi_hba->n_phy)) { + dev_err(dev, "could not get property phy-count\n"); + return -ENOENT; + } if (device_property_read_u32(dev, "queue-count", - &hisi_hba->queue_count)) + &hisi_hba->queue_count)) { + dev_err(dev, "could not get property queue-count\n"); + return -ENOENT; + } + + return 0; +} +EXPORT_SYMBOL_GPL(hisi_sas_get_fw_info); + +static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev, + const struct hisi_sas_hw *hw) +{ + struct resource *res; + struct Scsi_Host *shost; + struct hisi_hba *hisi_hba; + struct device *dev = &pdev->dev; + + shost = scsi_host_alloc(&hisi_sas_sht, sizeof(*hisi_hba)); + if (!shost) { + dev_err(dev, "scsi host alloc failed\n"); + return NULL; + } + hisi_hba = shost_priv(shost); + + INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); + hisi_hba->hw = hw; + hisi_hba->dev = dev; + hisi_hba->platform_dev = pdev; + hisi_hba->shost = shost; + SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; + + init_timer(&hisi_hba->timer); + + if (hisi_sas_get_fw_info(hisi_hba) < 0) goto err_out; if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) && From patchwork Thu May 25 12:04:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100504 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp720023qge; Thu, 25 May 2017 04:41:44 -0700 (PDT) X-Received: by 10.99.163.67 with SMTP id v3mr46654359pgn.210.1495712504363; Thu, 25 May 2017 04:41:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495712504; cv=none; d=google.com; s=arc-20160816; b=F/k5HPWKAz0TkL32ETFBmY0goSxrgxeRNvK04LcsnZ7k3nDUaktZiVP2axeAOLoUau c+u2hSkaUtg9IziszV3pbFwuZNhZMCY651mnpkjBejId1RhSVzNX3guBlKAR8hby1M7c GabWTvEo2SU2tNFwIZtnwTs3for8b9zt1bPfTPrQNk+G/7XvGbknk1aGlQ5oJEHxWR44 9cv2I/XvGSExsCFfkGXR/r/MluSLQ+hWUJ4EMMTgdg+O2Kha7+QwbTYRyLD0ivV1sSLT 6qBDQ0LnzgxJalPFv2sAJFNEOb7UWn5PFiOFMx2wp1scUtidg6o8Re7MUtNrMRTd/wv7 ko0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=NBkuFmQMaN5YGvA7azc839YyXP8p5u0BOr61aqCkgP0=; b=nez2N40GroX5bzG1movkqNGPT0egOxRtHmr8pRR6bLF2p42lJ1iLThKR1IYxHgFBCm 5C1iB73JuExhcl2ayu4pPI82SJskRaGy5WR8gV9kuDit+sD/JSuVoFeb924lCNhpTkGJ JzGcvO/dwaLbEvBFlFuZZxd+clN5VHTKl3ViooXfSSF4igvEY2WYiGm9jBjFoIsXz1Q8 4j0e4SLs4KiOXeUaQ3DKeghr4q1x5tA1AN/r75e5Gp6jGygCEA1AOjW+D32eFHFhSQJp XxNSzCj9SaqicoqpVmZ/72aOU+lhyLvGj3GIBEZ6QS9t8Hpl3evKpIJQhNfiWom076jp chdA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s131si22633369pgs.324.2017.05.25.04.41.44; Thu, 25 May 2017 04:41:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965733AbdEYLlk (ORCPT + 25 others); Thu, 25 May 2017 07:41:40 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:7265 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763815AbdEYLed (ORCPT ); Thu, 25 May 2017 07:34:33 -0400 Received: from 172.30.72.55 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APE94334; Thu, 25 May 2017 19:34:31 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:19 +0800 From: John Garry To: , CC: , , , , , John Garry , Xiang Chen Subject: [PATCH v2 08/22] scsi: hisi_sas: add skeleton v3 hw driver Date: Thu, 25 May 2017 20:04:57 +0800 Message-ID: <1495713911-80476-9-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.5926C148.000D, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 4ccfb442903aa2a299e5722f7e671c10 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add skeleton driver for v3 hw in hisi_sas_v3_hw.c File hisi_sas_v3_hw.c will serve 2 purposes: - probing and initialisation of the controller based on pci device - hw layer for v3-based controllers The controller design is quite similar to v2 hw in hip07. However key differences include: -All v2 hw bugs are fixed (hopefully), so workarounds are not required -support for device deregistration -some interrupt modifications -configurable max device support Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/Kconfig | 10 +++++++- drivers/scsi/hisi_sas/Makefile | 1 + drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 47 ++++++++++++++++++++++++++++++++++ 3 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/Kconfig b/drivers/scsi/hisi_sas/Kconfig index 374a329..d42f29a 100644 --- a/drivers/scsi/hisi_sas/Kconfig +++ b/drivers/scsi/hisi_sas/Kconfig @@ -6,4 +6,12 @@ config SCSI_HISI_SAS select BLK_DEV_INTEGRITY depends on ATA help - This driver supports HiSilicon's SAS HBA + This driver supports HiSilicon's SAS HBA, including support based + on platform device + +config SCSI_HISI_SAS_PCI + tristate "HiSilicon SAS on PCI bus" + depends on SCSI_HISI_SAS + depends on PCI + help + This driver supports HiSilicon's SAS HBA based on PCI device diff --git a/drivers/scsi/hisi_sas/Makefile b/drivers/scsi/hisi_sas/Makefile index c6d3a1b..24623f2 100644 --- a/drivers/scsi/hisi_sas/Makefile +++ b/drivers/scsi/hisi_sas/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas_main.o obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas_v1_hw.o hisi_sas_v2_hw.o +obj-$(CONFIG_SCSI_HISI_SAS_PCI) += hisi_sas_v3_hw.o diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c new file mode 100644 index 0000000..cf72577 --- /dev/null +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2017 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include "hisi_sas.h" +#define DRV_NAME "hisi_sas_v3_hw" + +static int +hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + return 0; +} + +static void hisi_sas_v3_remove(struct pci_dev *pdev) +{ +} + +enum { + /* instances of the controller */ + hip08, +}; + +static const struct pci_device_id sas_v3_pci_table[] = { + { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, + {} +}; + +static struct pci_driver sas_v3_pci_driver = { + .name = DRV_NAME, + .id_table = sas_v3_pci_table, + .probe = hisi_sas_v3_probe, + .remove = hisi_sas_v3_remove, +}; + +module_pci_driver(sas_v3_pci_driver); + +MODULE_VERSION(DRV_VERSION); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("John Garry "); +MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); +MODULE_ALIAS("platform:" DRV_NAME); From patchwork Thu May 25 12:04:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100507 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp720196qge; Thu, 25 May 2017 04:42:14 -0700 (PDT) X-Received: by 10.98.75.6 with SMTP id y6mr45066183pfa.157.1495712534486; Thu, 25 May 2017 04:42:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495712534; cv=none; d=google.com; s=arc-20160816; b=Rqn6134gKayt5lMpBANTqqLRjFhMFo++9xkj6Rtf/Tk5K2fjlH5PWV66OcnmEo9LaD X9tdV/JrVusXF6yNuA1X77Umt6cVkTcGyyZxqzm1lYZmlNQEeiB7yfN1pSIKexb8ekVm VzXRa0R3dlaDOlXXzK7QkmOfjgM6M8PxE9kNdOUbnh8bRmXpsoJAOUKe0RlB1QQIqiyg TzXfJFeLsg8+DsA7sgUxOy+XQwvx00oKLx1ca7iSL2u84h6gnI+dklinKeeU+KtSKaOK WvJF+niFH+auZ236U3QAV2TVDE7nwVwMOAsDs72qCgu5iT3y5NHtV5ezHfVsTlVriY2C pVVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=YijZ6jr56BXnYiBuP5TcA1zzk9f0Mnw3+/a/lRfb1rA=; b=Y1J+ySgA/0LdtZAXsh4GdNZk/wuu3hZYGbstXjVbiUSGAOezI2y6yf2ykdw38yU5zT nCDyJO/ky4a3wORPmU6knVJaXLLBrfGPkKNtgXX3YrPXD1T2RnmGy7dhVCvGqwYKTOAP CxFEM//QDvRwlrU8yvTsHf7IU0OUIXovFHRlsm+ayiyCZxyA5fGcqX5VBYM11EdwmucX vVPlBl74+bgbkkhwwdrI3LiphuPxxS9uIWxe4Ebant6cDSiYLUoSYriINSpYeA8RHku9 /R4kbPOjK2tCayqMCcT4JPMd16NcpweW+dNSYAAG63Qv109upKVmFxC6rwC9rumnEhKU nUxg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 2si13096779pfk.47.2017.05.25.04.42.14; Thu, 25 May 2017 04:42:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S937955AbdEYLly (ORCPT + 25 others); Thu, 25 May 2017 07:41:54 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:6821 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763513AbdEYLed (ORCPT ); Thu, 25 May 2017 07:34:33 -0400 Received: from 172.30.72.55 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APE94320; Thu, 25 May 2017 19:34:28 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:20 +0800 From: John Garry To: , CC: , , , , , John Garry , Xiang Chen Subject: [PATCH v2 09/22] scsi: hisi_sas: add initialisation for v3 pci-based controller Date: Thu, 25 May 2017 20:04:58 +0800 Message-ID: <1495713911-80476-10-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.5926C145.0189, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 80340e08c2cc308a0ad28db17fc4094f Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the code to initialise the controller which is based on pci device in hisi_sas_v3_hw.c The core controller routines are still in hisi_sas_main.c; some common initialisation functions are also exported from hisi_sas_main.c For pci-based controller, the device properties, like phy count and sas address are read from the firmware, same as platform device-based controller. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas.h | 6 ++ drivers/scsi/hisi_sas/hisi_sas_main.c | 18 ++-- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 157 +++++++++++++++++++++++++++++++++ 3 files changed, 175 insertions(+), 6 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index d029aba..ce2666b 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -359,6 +359,12 @@ struct hisi_sas_command_table_ssp { struct hisi_sas_command_table_stp stp; }; +extern struct scsi_transport_template *hisi_sas_stt; +extern struct scsi_host_template *hisi_sas_sht; + +extern void hisi_sas_init_add(struct hisi_hba *hisi_hba); +extern int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost); +extern void hisi_sas_free(struct hisi_hba *hisi_hba); extern u8 hisi_sas_get_ata_protocol(u8 cmd, int direction); extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port); extern void hisi_sas_sata_done(struct sas_task *task, diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 58c6cf0..fba06fb 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -1476,9 +1476,10 @@ void hisi_sas_rescan_topology(struct hisi_hba *hisi_hba, u32 old_state, } EXPORT_SYMBOL_GPL(hisi_sas_rescan_topology); -static struct scsi_transport_template *hisi_sas_stt; +struct scsi_transport_template *hisi_sas_stt; +EXPORT_SYMBOL_GPL(hisi_sas_stt); -static struct scsi_host_template hisi_sas_sht = { +static struct scsi_host_template _hisi_sas_sht = { .module = THIS_MODULE, .name = DRV_NAME, .queuecommand = sas_queuecommand, @@ -1498,6 +1499,8 @@ void hisi_sas_rescan_topology(struct hisi_hba *hisi_hba, u32 old_state, .target_destroy = sas_target_destroy, .ioctl = sas_ioctl, }; +struct scsi_host_template *hisi_sas_sht = &_hisi_sas_sht; +EXPORT_SYMBOL_GPL(hisi_sas_sht); static struct sas_domain_function_template hisi_sas_transport_ops = { .lldd_dev_found = hisi_sas_dev_found, @@ -1545,7 +1548,7 @@ void hisi_sas_init_mem(struct hisi_hba *hisi_hba) } EXPORT_SYMBOL_GPL(hisi_sas_init_mem); -static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost) +int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost) { struct device *dev = hisi_hba->dev; int i, s, max_command_entries = hisi_hba->hw->max_command_entries; @@ -1664,8 +1667,9 @@ static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost) err_out: return -ENOMEM; } +EXPORT_SYMBOL_GPL(hisi_sas_alloc); -static void hisi_sas_free(struct hisi_hba *hisi_hba) +void hisi_sas_free(struct hisi_hba *hisi_hba) { struct device *dev = hisi_hba->dev; int i, s, max_command_entries = hisi_hba->hw->max_command_entries; @@ -1720,6 +1724,7 @@ static void hisi_sas_free(struct hisi_hba *hisi_hba) if (hisi_hba->wq) destroy_workqueue(hisi_hba->wq); } +EXPORT_SYMBOL_GPL(hisi_sas_free); static void hisi_sas_rst_work_handler(struct work_struct *work) { @@ -1801,7 +1806,7 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev, struct hisi_hba *hisi_hba; struct device *dev = &pdev->dev; - shost = scsi_host_alloc(&hisi_sas_sht, sizeof(*hisi_hba)); + shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba)); if (!shost) { dev_err(dev, "scsi host alloc failed\n"); return NULL; @@ -1843,7 +1848,7 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev, return NULL; } -static void hisi_sas_init_add(struct hisi_hba *hisi_hba) +void hisi_sas_init_add(struct hisi_hba *hisi_hba) { int i; @@ -1852,6 +1857,7 @@ static void hisi_sas_init_add(struct hisi_hba *hisi_hba) hisi_hba->sas_addr, SAS_ADDR_SIZE); } +EXPORT_SYMBOL_GPL(hisi_sas_init_add); int hisi_sas_probe(struct platform_device *pdev, const struct hisi_sas_hw *hw) diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index cf72577..05976db 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -11,16 +11,173 @@ #include "hisi_sas.h" #define DRV_NAME "hisi_sas_v3_hw" +static const struct hisi_sas_hw hisi_sas_v3_hw; + +static struct Scsi_Host * +hisi_sas_shost_alloc_pci(struct pci_dev *pdev) +{ + struct Scsi_Host *shost; + struct hisi_hba *hisi_hba; + struct device *dev = &pdev->dev; + + shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba)); + if (!shost) + goto err_out; + hisi_hba = shost_priv(shost); + + hisi_hba->hw = &hisi_sas_v3_hw; + hisi_hba->pci_dev = pdev; + hisi_hba->dev = dev; + hisi_hba->shost = shost; + SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; + + init_timer(&hisi_hba->timer); + + if (hisi_sas_get_fw_info(hisi_hba) < 0) + goto err_out; + + if (hisi_sas_alloc(hisi_hba, shost)) { + hisi_sas_free(hisi_hba); + goto err_out; + } + + return shost; +err_out: + dev_err(dev, "shost alloc failed\n"); + return NULL; +} + static int hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) { + struct Scsi_Host *shost; + struct hisi_hba *hisi_hba; + struct device *dev = &pdev->dev; + struct asd_sas_phy **arr_phy; + struct asd_sas_port **arr_port; + struct sas_ha_struct *sha; + int rc, phy_nr, port_nr, i; + + rc = pci_enable_device(pdev); + if (rc) + goto err_out; + + pci_set_master(pdev); + + rc = pci_request_regions(pdev, DRV_NAME); + if (rc) + goto err_out_disable_device; + + if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) || + (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) { + if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) || + (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) { + dev_err(dev, "No usable DMA addressing method\n"); + rc = -EIO; + goto err_out_regions; + } + } + + shost = hisi_sas_shost_alloc_pci(pdev); + if (!shost) { + rc = -ENOMEM; + goto err_out_regions; + } + + sha = SHOST_TO_SAS_HA(shost); + hisi_hba = shost_priv(shost); + dev_set_drvdata(dev, sha); + + hisi_hba->regs = pcim_iomap(pdev, 5, 0); + if (!hisi_hba->regs) { + dev_err(dev, "cannot map register.\n"); + rc = -ENOMEM; + goto err_out_ha; + } + + phy_nr = port_nr = hisi_hba->n_phy; + + arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); + arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); + if (!arr_phy || !arr_port) { + rc = -ENOMEM; + goto err_out_ha; + } + + sha->sas_phy = arr_phy; + sha->sas_port = arr_port; + sha->core.shost = shost; + sha->lldd_ha = hisi_hba; + + shost->transportt = hisi_sas_stt; + shost->max_id = HISI_SAS_MAX_DEVICES; + shost->max_lun = ~0; + shost->max_channel = 1; + shost->max_cmd_len = 16; + shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT); + shost->can_queue = hisi_hba->hw->max_command_entries; + shost->cmd_per_lun = hisi_hba->hw->max_command_entries; + + sha->sas_ha_name = DRV_NAME; + sha->dev = dev; + sha->lldd_module = THIS_MODULE; + sha->sas_addr = &hisi_hba->sas_addr[0]; + sha->num_phys = hisi_hba->n_phy; + sha->core.shost = hisi_hba->shost; + + for (i = 0; i < hisi_hba->n_phy; i++) { + sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; + sha->sas_port[i] = &hisi_hba->port[i].sas_port; + } + + hisi_sas_init_add(hisi_hba); + + rc = scsi_add_host(shost, dev); + if (rc) + goto err_out_ha; + + rc = sas_register_ha(sha); + if (rc) + goto err_out_register_ha; + + rc = hisi_hba->hw->hw_init(hisi_hba); + if (rc) + goto err_out_register_ha; + + scsi_scan_host(shost); + return 0; + +err_out_register_ha: + scsi_remove_host(shost); +err_out_ha: + kfree(shost); +err_out_regions: + pci_release_regions(pdev); +err_out_disable_device: + pci_disable_device(pdev); +err_out: + return rc; } static void hisi_sas_v3_remove(struct pci_dev *pdev) { + struct device *dev = &pdev->dev; + struct sas_ha_struct *sha = dev_get_drvdata(dev); + struct hisi_hba *hisi_hba = sha->lldd_ha; + + scsi_remove_host(sha->core.shost); + sas_unregister_ha(sha); + sas_remove_host(sha->core.shost); + + hisi_sas_free(hisi_hba); + pci_release_regions(pdev); + pci_disable_device(pdev); } +static const struct hisi_sas_hw hisi_sas_v3_hw = { +}; + enum { /* instances of the controller */ hip08, From patchwork Thu May 25 12:05:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100505 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp720101qge; 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[209.132.180.67]) by mx.google.com with ESMTP id t128si28984295pgt.337.2017.05.25.04.41.56; Thu, 25 May 2017 04:41:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965974AbdEYLln (ORCPT + 25 others); Thu, 25 May 2017 07:41:43 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:7262 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763735AbdEYLed (ORCPT ); Thu, 25 May 2017 07:34:33 -0400 Received: from 172.30.72.55 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APE94329; Thu, 25 May 2017 19:34:30 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:20 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH v2 11/22] scsi: hisi_sas: add v3 hw PHY init Date: Thu, 25 May 2017 20:05:00 +0800 Message-ID: <1495713911-80476-12-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.5926C147.01A7, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 0e5332aa35c975e2c81b349b43fbb6b2 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add code to configure PHYs for v3 hw. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 126 +++++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 316938a..e3e3734 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -19,6 +19,10 @@ #define ITCT_BASE_ADDR_HI 0x14 #define IO_BROKEN_MSG_ADDR_LO 0x18 #define IO_BROKEN_MSG_ADDR_HI 0x1c +#define PHY_CONTEXT 0x20 +#define PHY_STATE 0x24 +#define PHY_PORT_NUM_MA 0x28 +#define PHY_CONN_RATE 0x30 #define AXI_AHB_CLK_CFG 0x3c #define AXI_USER1 0x48 #define AXI_USER2 0x4c @@ -42,6 +46,7 @@ #define CFG_SET_ABORTED_IPTT_OFF 0 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) #define CFG_1US_TIMER_TRSH 0xcc +#define CHNL_INT_STATUS 0x148 #define INT_COAL_EN 0x19c #define OQ_INT_COAL_TIME 0x1a0 #define OQ_INT_COAL_CNT 0x1a4 @@ -68,9 +73,11 @@ #define ENT_INT_SRC_MSK1 0x1c4 #define ENT_INT_SRC_MSK2 0x1c8 #define ENT_INT_SRC_MSK3 0x1cc +#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 #define CHNL_ENT_INT_MSK 0x1d4 #define HGC_COM_INT_MSK 0x1d8 +#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) #define SAS_ECC_INTR 0x1e8 #define SAS_ECC_INTR_MSK 0x1ec #define HGC_ERR_STAT_EN 0x238 @@ -91,11 +98,33 @@ /* phy registers requiring init */ #define PORT_BASE (0x2000) +#define PHY_CFG (PORT_BASE + 0x0) +#define HARD_PHY_LINKRATE (PORT_BASE + 0x4) +#define PHY_CFG_ENA_OFF 0 +#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) +#define PHY_CFG_DC_OPT_OFF 2 +#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) #define PHY_CTRL (PORT_BASE + 0x14) #define PHY_CTRL_RESET_OFF 0 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) #define SL_CFG (PORT_BASE + 0x84) +#define SL_CONTROL (PORT_BASE + 0x94) +#define SL_CONTROL_NOTIFY_EN_OFF 0 +#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) +#define SL_CTA_OFF 17 +#define SL_CTA_MSK (0x1 << SL_CTA_OFF) +#define TX_ID_DWORD0 (PORT_BASE + 0x9c) +#define TX_ID_DWORD1 (PORT_BASE + 0xa0) +#define TX_ID_DWORD2 (PORT_BASE + 0xa4) +#define TX_ID_DWORD3 (PORT_BASE + 0xa8) +#define TX_ID_DWORD4 (PORT_BASE + 0xaC) +#define TX_ID_DWORD5 (PORT_BASE + 0xb0) +#define TX_ID_DWORD6 (PORT_BASE + 0xb4) +#define TXID_AUTO (PORT_BASE + 0xb8) +#define CT3_OFF 1 +#define CT3_MSK (0x1 << CT3_OFF) +#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) @@ -136,6 +165,13 @@ struct hisi_sas_complete_v3_hdr { }; #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 +#define HISI_SAS_MSI_COUNT_V3_HW 32 + +enum { + HISI_SAS_PHY_PHY_UPDOWN, + HISI_SAS_PHY_CHNL_INT, + HISI_SAS_PHY_INT_NR +}; static const struct hisi_sas_hw hisi_sas_v3_hw; @@ -154,6 +190,14 @@ static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, writel(val, regs); } +static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, + int phy_no, u32 off) +{ + void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; + + return readl(regs); +} + static void init_reg_v3_hw(struct hisi_hba *hisi_hba) { int i; @@ -268,6 +312,45 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) upper_32_bits(hisi_hba->initial_fis_dma)); } +static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); + + cfg &= ~PHY_CFG_DC_OPT_MSK; + cfg |= 1 << PHY_CFG_DC_OPT_OFF; + hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); +} + +static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + struct sas_identify_frame identify_frame; + u32 *identify_buffer; + + memset(&identify_frame, 0, sizeof(identify_frame)); + identify_frame.dev_type = SAS_END_DEVICE; + identify_frame.frame_type = 0; + identify_frame._un1 = 1; + identify_frame.initiator_bits = SAS_PROTOCOL_ALL; + identify_frame.target_bits = SAS_PROTOCOL_NONE; + memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); + memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); + identify_frame.phy_id = phy_no; + identify_buffer = (u32 *)(&identify_frame); + + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, + __swab32(identify_buffer[0])); + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, + __swab32(identify_buffer[1])); + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, + __swab32(identify_buffer[2])); + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, + __swab32(identify_buffer[3])); + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, + __swab32(identify_buffer[4])); + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, + __swab32(identify_buffer[5])); +} + static int hw_init_v3_hw(struct hisi_hba *hisi_hba) { init_reg_v3_hw(hisi_hba); @@ -275,6 +358,47 @@ static int hw_init_v3_hw(struct hisi_hba *hisi_hba) return 0; } +static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); + + cfg |= PHY_CFG_ENA_MSK; + hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); +} + +static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + config_id_frame_v3_hw(hisi_hba, phy_no); + config_phy_opt_mode_v3_hw(hisi_hba, phy_no); + enable_phy_v3_hw(hisi_hba, phy_no); +} + +static void start_phys_v3_hw(struct hisi_hba *hisi_hba) +{ + int i; + + for (i = 0; i < hisi_hba->n_phy; i++) + start_phy_v3_hw(hisi_hba, i); +} + +static void phys_init_v3_hw(struct hisi_hba *hisi_hba) +{ + start_phys_v3_hw(hisi_hba); +} + +static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + u32 sl_control; + + sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); + sl_control |= SL_CONTROL_NOTIFY_EN_MSK; + hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); + msleep(1); + sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); + sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; + hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); +} + static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) { int rc; @@ -451,7 +575,9 @@ static void hisi_sas_v3_remove(struct pci_dev *pdev) static const struct hisi_sas_hw hisi_sas_v3_hw = { .hw_init = hisi_sas_v3_init, .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, + .sl_notify = sl_notify_v3_hw, .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), + .phys_init = phys_init_v3_hw, }; enum { From patchwork Thu May 25 12:05:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100508 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp720200qge; Thu, 25 May 2017 04:42:15 -0700 (PDT) X-Received: by 10.98.71.214 with SMTP id p83mr43792267pfi.236.1495712535024; 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[209.132.180.67]) by mx.google.com with ESMTP id 2si13096779pfk.47.2017.05.25.04.42.14; Thu, 25 May 2017 04:42:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1765510AbdEYLl5 (ORCPT + 25 others); Thu, 25 May 2017 07:41:57 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:7256 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751882AbdEYLed (ORCPT ); Thu, 25 May 2017 07:34:33 -0400 Received: from 172.30.72.55 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APE94321; Thu, 25 May 2017 19:34:29 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:21 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH v2 12/22] scsi: hisi_sas: add phy up/down/bcast and channel ISR Date: Thu, 25 May 2017 20:05:01 +0800 Message-ID: <1495713911-80476-13-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.5926C145.0225, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 0a7b3ce56123e3509cf2040bf770ab55 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add code to initialise interrupts and add some interrupt handlers. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 282 +++++++++++++++++++++++++++++++++ 1 file changed, 282 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index e3e3734..e9fdedd 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -173,8 +173,16 @@ enum { HISI_SAS_PHY_INT_NR }; + static const struct hisi_sas_hw hisi_sas_v3_hw; +static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) +{ + void __iomem *regs = hisi_hba->regs + off; + + return readl(regs); +} + static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) { void __iomem *regs = hisi_hba->regs + off; @@ -399,6 +407,276 @@ static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no) hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); } +static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) +{ + int i, res = 0; + u32 context, port_id, link_rate, hard_phy_linkrate; + struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; + struct asd_sas_phy *sas_phy = &phy->sas_phy; + struct device *dev = hisi_hba->dev; + + hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); + + port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); + port_id = (port_id >> (4 * phy_no)) & 0xf; + link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); + link_rate = (link_rate >> (phy_no * 4)) & 0xf; + + if (port_id == 0xf) { + dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); + res = IRQ_NONE; + goto end; + } + sas_phy->linkrate = link_rate; + hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no, + HARD_PHY_LINKRATE); + phy->maximum_linkrate = hard_phy_linkrate & 0xf; + phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf; + phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); + + /* Check for SATA dev */ + context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); + if (context & (1 << phy_no)) { + struct hisi_sas_initial_fis *initial_fis; + struct dev_to_host_fis *fis; + u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; + + dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); + initial_fis = &hisi_hba->initial_fis[phy_no]; + fis = &initial_fis->fis; + sas_phy->oob_mode = SATA_OOB_MODE; + attached_sas_addr[0] = 0x50; + attached_sas_addr[7] = phy_no; + memcpy(sas_phy->attached_sas_addr, + attached_sas_addr, + SAS_ADDR_SIZE); + memcpy(sas_phy->frame_rcvd, fis, + sizeof(struct dev_to_host_fis)); + phy->phy_type |= PORT_TYPE_SATA; + phy->identify.device_type = SAS_SATA_DEV; + phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); + phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; + } else { + u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; + struct sas_identify_frame *id = + (struct sas_identify_frame *)frame_rcvd; + + dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); + for (i = 0; i < 6; i++) { + u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, + RX_IDAF_DWORD0 + (i * 4)); + frame_rcvd[i] = __swab32(idaf); + } + sas_phy->oob_mode = SAS_OOB_MODE; + memcpy(sas_phy->attached_sas_addr, + &id->sas_addr, + SAS_ADDR_SIZE); + phy->phy_type |= PORT_TYPE_SAS; + phy->identify.device_type = id->dev_type; + phy->frame_rcvd_size = sizeof(struct sas_identify_frame); + if (phy->identify.device_type == SAS_END_DEVICE) + phy->identify.target_port_protocols = + SAS_PROTOCOL_SSP; + else if (phy->identify.device_type != SAS_PHY_UNUSED) + phy->identify.target_port_protocols = + SAS_PROTOCOL_SMP; + } + + phy->port_id = port_id; + phy->phy_attached = 1; + queue_work(hisi_hba->wq, &phy->phyup_ws); + +end: + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, + CHL_INT0_SL_PHY_ENABLE_MSK); + hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); + + return res; +} + +static int phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) +{ + int res = 0; + u32 phy_state, sl_ctrl, txid_auto; + struct device *dev = hisi_hba->dev; + + hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); + + phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); + dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); + hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); + + sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); + hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, + sl_ctrl&(~SL_CTA_MSK)); + + txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); + hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, + txid_auto | CT3_MSK); + + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); + hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); + + return res; +} + +static void phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) +{ + struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; + struct asd_sas_phy *sas_phy = &phy->sas_phy; + struct sas_ha_struct *sas_ha = &hisi_hba->sha; + + hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); + sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, + CHL_INT0_SL_RX_BCST_ACK_MSK); + hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); +} + +static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) +{ + struct hisi_hba *hisi_hba = p; + u32 irq_msk; + int phy_no = 0; + irqreturn_t res = IRQ_NONE; + + irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) + & 0x11111111; + while (irq_msk) { + if (irq_msk & 1) { + u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, + CHL_INT0); + u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); + int rdy = phy_state & (1 << phy_no); + + if (rdy) { + if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) + /* phy up */ + if (phy_up_v3_hw(phy_no, hisi_hba) + == IRQ_HANDLED) + res = IRQ_HANDLED; + if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) + /* phy bcast */ + phy_bcast_v3_hw(phy_no, hisi_hba); + } else { + if (irq_value & CHL_INT0_NOT_RDY_MSK) + /* phy down */ + if (phy_down_v3_hw(phy_no, hisi_hba) + == IRQ_HANDLED) + res = IRQ_HANDLED; + } + } + irq_msk >>= 4; + phy_no++; + } + + return res; +} + +static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) +{ + struct hisi_hba *hisi_hba = p; + struct device *dev = hisi_hba->dev; + u32 ent_msk, ent_tmp, irq_msk; + int phy_no = 0; + + ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); + ent_tmp = ent_msk; + ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK; + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk); + + irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) + & 0xeeeeeeee; + + while (irq_msk) { + u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, + CHL_INT0); + u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no, + CHL_INT1); + u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no, + CHL_INT2); + + if ((irq_msk & (4 << (phy_no * 4))) && + irq_value1) { + if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK | + CHL_INT1_DMAC_TX_ECC_ERR_MSK)) + panic("%s: DMAC RX/TX ecc bad error! (0x%x)", + dev_name(dev), irq_value1); + + hisi_sas_phy_write32(hisi_hba, phy_no, + CHL_INT1, irq_value1); + } + + if (irq_msk & (8 << (phy_no * 4)) && irq_value2) + hisi_sas_phy_write32(hisi_hba, phy_no, + CHL_INT2, irq_value2); + + + if (irq_msk & (2 << (phy_no * 4)) && irq_value0) { + hisi_sas_phy_write32(hisi_hba, phy_no, + CHL_INT0, irq_value0 + & (~CHL_INT0_HOTPLUG_TOUT_MSK) + & (~CHL_INT0_SL_PHY_ENABLE_MSK) + & (~CHL_INT0_NOT_RDY_MSK)); + } + irq_msk &= ~(0xe << (phy_no * 4)); + phy_no++; + } + + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp); + + return IRQ_HANDLED; +} + +static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = { + int_phy_up_down_bcast_v3_hw, + int_chnl_int_v3_hw, +}; + +static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) +{ + struct device *dev = hisi_hba->dev; + struct pci_dev *pdev = hisi_hba->pci_dev; + int vectors, i, irq, rc; + int max_msi = HISI_SAS_MSI_COUNT_V3_HW; + int msi_vectors[HISI_SAS_MSI_COUNT_V3_HW]; + + if (pdev->msi_enabled) + pci_disable_msi(pdev); + + vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1, + max_msi, PCI_IRQ_MSI); + if (vectors < max_msi) { + dev_err(dev, "could not allocate all msi (%d)\n", vectors); + return -ENOENT; + } + + for (i = 0; i < vectors; i++) + msi_vectors[i] = pdev->irq + i; + + for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) { + int idx = i; + + irq = msi_vectors[idx + 1]; /* Phy up/down/bcast is irq1 */ + if (!irq) { + dev_err(dev, "irq init: failed to map PHY interrupt %d\n", + idx); + return -ENOENT; + } + + rc = devm_request_irq(dev, irq, phy_interrupts[i], 0, + DRV_NAME " phy", hisi_hba); + if (rc) { + dev_err(dev, "irq init: could not request " + "phy interrupt %d, rc=%d\n", + irq, rc); + return -ENOENT; + } + } + + return 0; +} + static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) { int rc; @@ -407,6 +685,10 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) if (rc) return rc; + rc = interrupt_init_v3_hw(hisi_hba); + if (rc) + return rc; + return 0; } From patchwork Thu May 25 12:05:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100486 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp718072qge; Thu, 25 May 2017 04:35:42 -0700 (PDT) X-Received: by 10.98.75.157 with SMTP id d29mr43945673pfj.135.1495712142006; Thu, 25 May 2017 04:35:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495712141; cv=none; d=google.com; s=arc-20160816; b=HpfBceiPnlcuMHShVQ+V8+TjlZH6jnKyMNYOQx0ooUmHHz12jm5YEh5sgkyZS5QFCW Dr/+77x+1e5EOBcAdqYlmId82ZfF/N+TxHwGueP2cQa++ssevE8olo+EUWfEcQcczonq EPDeYC86FzR6sYQQvawqMGZWGFsHd4kzq5HQjFuGKQ12JQ2kzqxonSOGnAFCz4EaPP3U 51F2drpuwhdy+TlriXsKPRrwfqnDzl/aWnJwkhExViHbXQh0Tv2UBAuDHE1NKro4dEnX SFY17Rdvz2Rg0JaeSGDPceewWgxdqi3jYvk9Ol4apK/drgSfGRXs/QkcPdmGyH9EwsxL cevQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=LLm86wCS+UDkcXGUd9nlidQoqcaQ6jWna+32f71pq4c=; b=0T4mrj8/KxQJtoXeH5KVBG8ghyrmstnjy+a/4wBsSesvta2aathi7N2TARjYZi9snM ChzA+LiHQ2G1ah87+DWygtZKjj6NAe5XBenfKW7YEtMaQQps0gPSZ+fzQHpVJN0Virbu 143AtDZeT1E3xmcZBp/4KtUw6f1X3d2XPa/wz8jRv5rwnINZVsnyRO/6Lo8HVwKi/e12 vDT3K5axnzNGtFk+96zrZTMSesTvjMr3vE/lQQusl8804ydLGfhcwSbsRmDgDNaLH/DT OgGQrQyE7yx5F4QuqWO7klBWS/kDmK8aDyUivJa+omImt69B8qyZwU/vmMNE7ijt3nE6 ihoA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y2si5444651pgo.217.2017.05.25.04.35.41; Thu, 25 May 2017 04:35:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423870AbdEYLf2 (ORCPT + 25 others); Thu, 25 May 2017 07:35:28 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6383 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1761559AbdEYLel (ORCPT ); Thu, 25 May 2017 07:34:41 -0400 Received: from 172.30.72.53 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOF01640; Thu, 25 May 2017 19:34:34 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:22 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH v2 13/22] scsi: hisi_sas: add v3 cq interrupt handler Date: Thu, 25 May 2017 20:05:02 +0800 Message-ID: <1495713911-80476-14-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020204.5926C14A.00B2, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: ca9d85ed589e952e7591ccedf20d811b Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add v3 cq interrupt handler slot_complete_v2_hw(). Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas.h | 1 + drivers/scsi/hisi_sas/hisi_sas_main.c | 32 ++++ drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 331 +++++++++++++++++++++++++++++++++ 3 files changed, 364 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index ce2666b..2315102 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -371,6 +371,7 @@ extern void hisi_sas_sata_done(struct sas_task *task, struct hisi_sas_slot *slot); extern int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag); extern int hisi_sas_get_fw_info(struct hisi_hba *hisi_hba); +extern bool hisi_sas_is_rw_cmd(struct sas_task *task); extern int hisi_sas_probe(struct platform_device *pdev, const struct hisi_sas_hw *ops); extern int hisi_sas_remove(struct platform_device *pdev); diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index fba06fb..a6d0bf8 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -118,6 +118,38 @@ int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag) } EXPORT_SYMBOL_GPL(hisi_sas_get_ncq_tag); +bool hisi_sas_is_rw_cmd(struct sas_task *task) +{ + switch (task->task_proto) { + case SAS_PROTOCOL_SSP: + { + unsigned char op = task->ssp_task.cmd->cmnd[0]; + + if (op == READ_6 || op == WRITE_6 || + op == READ_10 || op == WRITE_10 || + op == READ_12 || op == WRITE_12 || + op == READ_16 || op == WRITE_16) + return true; + break; + } + case SAS_PROTOCOL_SATA: + case SAS_PROTOCOL_STP: + case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: + { + u32 cmd_proto = hisi_sas_get_ata_protocol( + task->ata_task.fis.command, + task->data_dir); + if (cmd_proto != SATA_PROTOCOL_NONDATA) + return true; + break; + } + default: + break; + } + return false; +} +EXPORT_SYMBOL_GPL(hisi_sas_is_rw_cmd); + static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device) { return device->port->ha->lldd_ha; diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index e9fdedd..f8ac239 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -157,6 +157,32 @@ #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) +/* Completion header */ +/* dw0 */ +#define CMPLT_HDR_CMPLT_OFF 0 +#define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) +#define CMPLT_HDR_ERROR_PHASE_OFF 2 +#define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) +#define CMPLT_HDR_RSPNS_XFRD_OFF 10 +#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) +#define CMPLT_HDR_ERX_OFF 12 +#define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) +#define CMPLT_HDR_ABORT_STAT_OFF 13 +#define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) +/* abort_stat */ +#define STAT_IO_NOT_VALID 0x1 +#define STAT_IO_NO_DEVICE 0x2 +#define STAT_IO_COMPLETE 0x3 +#define STAT_IO_ABORTED 0x4 +/* dw1 */ +#define CMPLT_HDR_IPTT_OFF 0 +#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) +#define CMPLT_HDR_DEV_ID_OFF 16 +#define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) +/* dw3 */ +#define CMPLT_HDR_IO_IN_TARGET_OFF 17 +#define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) + struct hisi_sas_complete_v3_hdr { __le32 dw0; __le32 dw1; @@ -164,6 +190,8 @@ struct hisi_sas_complete_v3_hdr { __le32 dw3; }; +#define IO_RX_DATA_LEN_UNDERFLOW_OFF 6 +#define IO_RX_DATA_LEN_UNDERFLOW_MSK (1 << IO_RX_DATA_LEN_UNDERFLOW_OFF) #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 #define HISI_SAS_MSI_COUNT_V3_HW 32 @@ -628,6 +656,286 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) return IRQ_HANDLED; } +static void slot_err_v3_hw(struct hisi_hba *hisi_hba, + struct sas_task *task, + struct hisi_sas_slot *slot) +{ + struct task_status_struct *ts = &task->task_status; + struct hisi_sas_complete_v3_hdr *complete_queue = + hisi_hba->complete_hdr[slot->cmplt_queue]; + struct hisi_sas_complete_v3_hdr *complete_hdr = + &complete_queue[slot->cmplt_queue_slot]; + + switch (task->task_proto) { + case SAS_PROTOCOL_SSP: + { + if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { + ts->stat = SAS_QUEUE_FULL; + slot->abort = 1; + } else { + ts->stat = SAS_OPEN_REJECT; + ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; + } + } + break; + case SAS_PROTOCOL_SATA: + case SAS_PROTOCOL_STP: + case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: + { + if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { + ts->stat = SAS_PHY_DOWN; + slot->abort = 1; + } else { + ts->stat = SAS_OPEN_REJECT; + ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; + } + hisi_sas_sata_done(task, slot); + } + break; + case SAS_PROTOCOL_SMP: + ts->stat = SAM_STAT_CHECK_CONDITION; + break; + default: + break; + } +} + +static int +slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) +{ + struct sas_task *task = slot->task; + struct hisi_sas_device *sas_dev; + struct device *dev = hisi_hba->dev; + struct task_status_struct *ts; + struct domain_device *device; + enum exec_status sts; + u32 *error_info = slot->status_buffer; + struct hisi_sas_complete_v3_hdr *complete_queue = + hisi_hba->complete_hdr[slot->cmplt_queue]; + struct hisi_sas_complete_v3_hdr *complete_hdr = + &complete_queue[slot->cmplt_queue_slot]; + int aborted; + unsigned long flags; + + if (unlikely(!task || !task->lldd_task || !task->dev)) + return -EINVAL; + + ts = &task->task_status; + device = task->dev; + sas_dev = device->lldd_dev; + + spin_lock_irqsave(&task->task_state_lock, flags); + aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED; + task->task_state_flags &= + ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); + spin_unlock_irqrestore(&task->task_state_lock, flags); + + memset(ts, 0, sizeof(*ts)); + ts->resp = SAS_TASK_COMPLETE; + if (unlikely(aborted)) { + ts->stat = SAS_ABORTED_TASK; + hisi_sas_slot_task_free(hisi_hba, task, slot); + return -1; + } + + if (unlikely(!sas_dev)) { + dev_dbg(dev, "slot complete: port has not device\n"); + ts->stat = SAS_PHY_DOWN; + goto out; + } + + /* + * Use SAS+TMF status codes + */ + switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK) + >> CMPLT_HDR_ABORT_STAT_OFF) { + case STAT_IO_ABORTED: + /* this IO has been aborted by abort command */ + ts->stat = SAS_ABORTED_TASK; + goto out; + case STAT_IO_COMPLETE: + /* internal abort command complete */ + ts->stat = TMF_RESP_FUNC_SUCC; + goto out; + case STAT_IO_NO_DEVICE: + ts->stat = TMF_RESP_FUNC_COMPLETE; + goto out; + case STAT_IO_NOT_VALID: + /* + * abort single IO, the controller can't find the IO + */ + ts->stat = TMF_RESP_FUNC_FAILED; + goto out; + default: + break; + } + + if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3 && + (!(error_info[3] & + IO_RX_DATA_LEN_UNDERFLOW_MSK) || + hisi_sas_is_rw_cmd(task))) { + if ((complete_hdr->dw0 & + CMPLT_HDR_ERROR_PHASE_MSK) == 0x1) { + /* error happens on parse DQ entry */ + dev_dbg(dev, "Error happens on parse DQ entry!\n"); + } else if ((complete_hdr->dw0 & + CMPLT_HDR_ERROR_PHASE_MSK) == 0x80) { + /* error happens on ITCT or IOST configuration */ + dev_dbg(dev, "Error happens on ITCT or IOST configuration!\n"); + } else { + /* error info is recorded in memory*/ + dev_dbg(dev, "Error info: 0x%x, 0x%x, 0x%x, 0x%x\n", + error_info[0], error_info[1], + error_info[2], error_info[3]); + } + + slot_err_v3_hw(hisi_hba, task, slot); + if (unlikely(slot->abort)) + return ts->stat; + goto out; + } + + switch (task->task_proto) { + case SAS_PROTOCOL_SSP: + { + struct ssp_response_iu *iu = slot->status_buffer + + sizeof(struct hisi_sas_err_record); + + sas_ssp_task_response(dev, task, iu); + break; + } + case SAS_PROTOCOL_SMP: + { + struct scatterlist *sg_resp = &task->smp_task.smp_resp; + void *to; + + ts->stat = SAM_STAT_GOOD; + to = kmap_atomic(sg_page(sg_resp)); + + dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, + DMA_FROM_DEVICE); + dma_unmap_sg(dev, &task->smp_task.smp_req, 1, + DMA_TO_DEVICE); + memcpy(to + sg_resp->offset, + slot->status_buffer + + sizeof(struct hisi_sas_err_record), + sg_dma_len(sg_resp)); + kunmap_atomic(to); + break; + } + case SAS_PROTOCOL_SATA: + case SAS_PROTOCOL_STP: + case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: + { + ts->stat = SAM_STAT_GOOD; + hisi_sas_sata_done(task, slot); + break; + } + default: + ts->stat = SAM_STAT_CHECK_CONDITION; + break; + } + + if (!slot->port->port_attached) { + dev_err(dev, "slot complete: port %d has removed\n", + slot->port->sas_port.id); + ts->stat = SAS_PHY_DOWN; + } + +out: + spin_lock_irqsave(&task->task_state_lock, flags); + task->task_state_flags |= SAS_TASK_STATE_DONE; + spin_unlock_irqrestore(&task->task_state_lock, flags); + spin_lock_irqsave(&hisi_hba->lock, flags); + hisi_sas_slot_task_free(hisi_hba, task, slot); + spin_unlock_irqrestore(&hisi_hba->lock, flags); + sts = ts->stat; + + if (task->task_done) + task->task_done(task); + + return sts; +} + +static void cq_tasklet_v3_hw(unsigned long val) +{ + struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; + struct hisi_hba *hisi_hba = cq->hisi_hba; + struct hisi_sas_slot *slot; + struct hisi_sas_itct *itct; + struct hisi_sas_complete_v3_hdr *complete_queue; + u32 rd_point = cq->rd_point, wr_point, dev_id; + int queue = cq->id; + struct hisi_sas_dq *dq = &hisi_hba->dq[queue]; + + complete_queue = hisi_hba->complete_hdr[queue]; + + spin_lock(&dq->lock); + wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + + (0x14 * queue)); + + while (rd_point != wr_point) { + struct hisi_sas_complete_v3_hdr *complete_hdr; + int iptt; + + complete_hdr = &complete_queue[rd_point]; + + /* Check for NCQ completion */ + if (complete_hdr->act) { + u32 act_tmp = complete_hdr->act; + int ncq_tag_count = ffs(act_tmp); + + dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >> + CMPLT_HDR_DEV_ID_OFF; + itct = &hisi_hba->itct[dev_id]; + + /* The NCQ tags are held in the itct header */ + while (ncq_tag_count) { + __le64 *ncq_tag = &itct->qw4_15[0]; + + ncq_tag_count -= 1; + iptt = (ncq_tag[ncq_tag_count / 5] + >> (ncq_tag_count % 5) * 12) & 0xfff; + + slot = &hisi_hba->slot_info[iptt]; + slot->cmplt_queue_slot = rd_point; + slot->cmplt_queue = queue; + slot_complete_v3_hw(hisi_hba, slot); + + act_tmp &= ~(1 << ncq_tag_count); + ncq_tag_count = ffs(act_tmp); + } + } else { + iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK; + slot = &hisi_hba->slot_info[iptt]; + slot->cmplt_queue_slot = rd_point; + slot->cmplt_queue = queue; + slot_complete_v3_hw(hisi_hba, slot); + } + + if (++rd_point >= HISI_SAS_QUEUE_SLOTS) + rd_point = 0; + } + + /* update rd_point */ + cq->rd_point = rd_point; + hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); + spin_unlock(&dq->lock); +} + +static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) +{ + struct hisi_sas_cq *cq = p; + struct hisi_hba *hisi_hba = cq->hisi_hba; + int queue = cq->id; + + hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); + + tasklet_schedule(&cq->tasklet); + + return IRQ_HANDLED; +} + static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = { int_phy_up_down_bcast_v3_hw, int_chnl_int_v3_hw, @@ -674,6 +982,29 @@ static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) } } + for (i = 0; i < hisi_hba->queue_count; i++) { + int idx = i + 16; /* First cq interrupt is irq16 */ + struct hisi_sas_cq *cq = &hisi_hba->cq[i]; + struct tasklet_struct *t = &cq->tasklet; + + irq = msi_vectors[idx]; + if (!irq) { + dev_err(dev, + "irq init: could not map cq interrupt %d\n", + idx); + return -ENOENT; + } + rc = devm_request_irq(dev, irq, cq_interrupt_v3_hw, 0, + DRV_NAME " cq", &hisi_hba->cq[i]); + if (rc) { + dev_err(dev, + "irq init: could not request cq interrupt %d, rc=%d\n", + irq, rc); + return -ENOENT; + } + tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); + } + return 0; } From patchwork Thu May 25 12:05:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100490 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp718514qge; Thu, 25 May 2017 04:37:04 -0700 (PDT) X-Received: by 10.98.58.195 with SMTP id v64mr43706211pfj.237.1495712224811; Thu, 25 May 2017 04:37:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495712224; cv=none; d=google.com; s=arc-20160816; b=sIf2+MoUJ2XPTwOX45+e3z7ddbUovU+J9Bw26u2+ptvghJd7A4Xy8AXrUO7YVyenXj 7S795TMZ+hXgUgz9IF7NbItxpt3UbE2NFqkUfa2NFZ41L8Pg5UNaujsxeE3BqaU3SPex fECeXTegJUVPRxqmd2PsZfeSwCs8DKcHuA3GqMKyjEJ8bYQ0rdvlVDgJ5hfynOSByCRY M8pANyzjW1XueRSXm39aYcjr137gnBkumEZqfzT3lAqFSExj1yCr/l412oW+maCRCzXk 5YovnVFSC1l04nSXBATAzYueYyW3e3PMcUSI7kWRCO8t7Z67F1wVla4kFLIL5yvjl+jw nRNw== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id t188si27566804pgc.259.2017.05.25.04.37.04; Thu, 25 May 2017 04:37:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423889AbdEYLgq (ORCPT + 25 others); Thu, 25 May 2017 07:36:46 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6823 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1764170AbdEYLei (ORCPT ); Thu, 25 May 2017 07:34:38 -0400 Received: from 172.30.72.53 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOF01647; Thu, 25 May 2017 19:34:35 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:22 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH v2 14/22] scsi: hisi_sas: add v3 code to send SSP frame Date: Thu, 25 May 2017 20:05:03 +0800 Message-ID: <1495713911-80476-15-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.5926C14C.0069, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 42c719135f52ee463fbed9c702a05902 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add code to prepare SSP frame and deliver it to hardware. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 209 ++++++++++++++++++++++++++++++++- 1 file changed, 208 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index f8ac239..7dd4804 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -157,6 +157,41 @@ #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) +/* HW dma structures */ +/* Delivery queue header */ +/* dw0 */ +#define CMD_HDR_RESP_REPORT_OFF 5 +#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) +#define CMD_HDR_TLR_CTRL_OFF 6 +#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) +#define CMD_HDR_PORT_OFF 18 +#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) +#define CMD_HDR_PRIORITY_OFF 27 +#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) +#define CMD_HDR_CMD_OFF 29 +#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) +/* dw1 */ +#define CMD_HDR_DIR_OFF 5 +#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) +#define CMD_HDR_VDTL_OFF 10 +#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) +#define CMD_HDR_FRAME_TYPE_OFF 11 +#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) +#define CMD_HDR_DEV_ID_OFF 16 +#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) +/* dw2 */ +#define CMD_HDR_CFL_OFF 0 +#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) +#define CMD_HDR_MRFL_OFF 15 +#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) +#define CMD_HDR_SG_MOD_OFF 24 +#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) +/* dw6 */ +#define CMD_HDR_DIF_SGL_LEN_OFF 0 +#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) +#define CMD_HDR_DATA_SGL_LEN_OFF 16 +#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) + /* Completion header */ /* dw0 */ #define CMPLT_HDR_CMPLT_OFF 0 @@ -201,9 +236,13 @@ enum { HISI_SAS_PHY_INT_NR }; - static const struct hisi_sas_hw hisi_sas_v3_hw; +#define DIR_NO_DATA 0 +#define DIR_TO_INI 1 +#define DIR_TO_DEVICE 2 +#define DIR_RESERVED 3 + static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) { void __iomem *regs = hisi_hba->regs + off; @@ -211,6 +250,13 @@ static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) return readl(regs); } +static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) +{ + void __iomem *regs = hisi_hba->regs + off; + + return readl_relaxed(regs); +} + static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) { void __iomem *regs = hisi_hba->regs + off; @@ -435,6 +481,163 @@ static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no) hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); } +/** + * The callpath to this function and upto writing the write + * queue pointer should be safe from interruption. + */ +static int +get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) +{ + struct device *dev = hisi_hba->dev; + int queue = dq->id; + u32 r, w; + + w = dq->wr_point; + r = hisi_sas_read32_relaxed(hisi_hba, + DLVRY_Q_0_RD_PTR + (queue * 0x14)); + if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { + dev_warn(dev, "full queue=%d r=%d w=%d\n\n", + queue, r, w); + return -EAGAIN; + } + + return 0; +} + +static void start_delivery_v3_hw(struct hisi_sas_dq *dq) +{ + struct hisi_hba *hisi_hba = dq->hisi_hba; + int dlvry_queue = dq->slot_prep->dlvry_queue; + int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot; + + dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS; + hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), + dq->wr_point); +} + +static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_slot *slot, + struct hisi_sas_cmd_hdr *hdr, + struct scatterlist *scatter, + int n_elem) +{ + struct device *dev = hisi_hba->dev; + struct scatterlist *sg; + int i; + + if (n_elem > HISI_SAS_SGE_PAGE_CNT) { + dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT", + n_elem); + return -EINVAL; + } + + slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC, + &slot->sge_page_dma); + if (!slot->sge_page) + return -ENOMEM; + + for_each_sg(scatter, sg, n_elem, i) { + struct hisi_sas_sge *entry = &slot->sge_page->sge[i]; + + entry->addr = cpu_to_le64(sg_dma_address(sg)); + entry->page_ctrl_0 = entry->page_ctrl_1 = 0; + entry->data_len = cpu_to_le32(sg_dma_len(sg)); + entry->data_off = 0; + } + + hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma); + hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); + + return 0; +} + +static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_slot *slot, int is_tmf, + struct hisi_sas_tmf_task *tmf) +{ + struct sas_task *task = slot->task; + struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; + struct domain_device *device = task->dev; + struct hisi_sas_device *sas_dev = device->lldd_dev; + struct hisi_sas_port *port = slot->port; + struct sas_ssp_task *ssp_task = &task->ssp_task; + struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; + int has_data = 0, rc, priority = is_tmf; + u8 *buf_cmd; + u32 dw1 = 0, dw2 = 0; + + hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | + (2 << CMD_HDR_TLR_CTRL_OFF) | + (port->id << CMD_HDR_PORT_OFF) | + (priority << CMD_HDR_PRIORITY_OFF) | + (1 << CMD_HDR_CMD_OFF)); /* ssp */ + + dw1 = 1 << CMD_HDR_VDTL_OFF; + if (is_tmf) { + dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; + dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; + } else { + dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; + switch (scsi_cmnd->sc_data_direction) { + case DMA_TO_DEVICE: + has_data = 1; + dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; + break; + case DMA_FROM_DEVICE: + has_data = 1; + dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; + break; + default: + dw1 &= ~CMD_HDR_DIR_MSK; + } + } + + /* map itct entry */ + dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; + hdr->dw1 = cpu_to_le32(dw1); + + dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) + + 3) / 4) << CMD_HDR_CFL_OFF) | + ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | + (2 << CMD_HDR_SG_MOD_OFF); + hdr->dw2 = cpu_to_le32(dw2); + hdr->transfer_tags = cpu_to_le32(slot->idx); + + if (has_data) { + rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, + slot->n_elem); + if (rc) + return rc; + } + + hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); + hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma); + hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); + + buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr); + memcpy(buf_cmd, ssp_task->LUN, 8); + + if (!is_tmf) { + buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); + memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); + } else { + buf_cmd[10] = tmf->tmf; + switch (tmf->tmf) { + case TMF_ABORT_TASK: + case TMF_QUERY_TASK: + buf_cmd[12] = + (tmf->tag_of_task_to_be_managed >> 8) & 0xff; + buf_cmd[13] = + tmf->tag_of_task_to_be_managed & 0xff; + break; + default: + break; + } + } + + return 0; +} + static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) { int i, res = 0; @@ -1190,6 +1393,10 @@ static void hisi_sas_v3_remove(struct pci_dev *pdev) .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, .sl_notify = sl_notify_v3_hw, .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), + .prep_ssp = prep_ssp_v3_hw, + .get_free_slot = get_free_slot_v3_hw, + .start_delivery = start_delivery_v3_hw, + .slot_complete = slot_complete_v3_hw, .phys_init = phys_init_v3_hw, }; From patchwork Thu May 25 12:05:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100495 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp719088qge; Thu, 25 May 2017 04:38:53 -0700 (PDT) X-Received: by 10.98.217.154 with SMTP id b26mr43732267pfl.136.1495712333324; Thu, 25 May 2017 04:38:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495712333; cv=none; d=google.com; s=arc-20160816; b=c8rSLFIsaQNdz0Sz61LutV9c697ht+6fCrlHq8ukLwQUUyA230Mx8dgMIro63stOVb L4fwP8GrNifi/66CyHA0GP39LHc+/tLVtEqHKo8VC9h7AWI7UeTW6iIMbrzSeyHub6RW hLKiuXuojVLUAvKg3hnlleaVpwEHCSE5Y2Q9vjwsLgoYZOGZPkJlR/sxySqfOPzFA21C 8iButpaJhVxxS6uKkFHp+FRWgYbNgGOmQvOxix2ygj2l+gh4EWP+iln5M5vmCOMUsXYX r13bmJ9r27aObx1U/xdlSES2m45DmaqhbIzByKlPfqacwBHC5bje5Q09Rus1EclNaIm/ CMug== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id p23si27778007pli.56.2017.05.25.04.38.52; Thu, 25 May 2017 04:38:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936229AbdEYLir (ORCPT + 25 others); Thu, 25 May 2017 07:38:47 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6382 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763887AbdEYLeg (ORCPT ); Thu, 25 May 2017 07:34:36 -0400 Received: from 172.30.72.53 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOF01637; Thu, 25 May 2017 19:34:33 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:23 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH v2 15/22] scsi: hisi_sas: add v3 code to send SMP frame Date: Thu, 25 May 2017 20:05:04 +0800 Message-ID: <1495713911-80476-16-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020204.5926C14A.0010, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 65357bf79e33ff7e81fa248b34ef0289 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add code to prepare SMP frame. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 74 ++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 7dd4804..5de4738 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -186,6 +186,9 @@ #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) #define CMD_HDR_SG_MOD_OFF 24 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) +/* dw3 */ +#define CMD_HDR_IPTT_OFF 0 +#define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) /* dw6 */ #define CMD_HDR_DIF_SGL_LEN_OFF 0 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) @@ -638,6 +641,76 @@ static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba, return 0; } +static int prep_smp_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_slot *slot) +{ + struct sas_task *task = slot->task; + struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; + struct domain_device *device = task->dev; + struct device *dev = hisi_hba->dev; + struct hisi_sas_port *port = slot->port; + struct scatterlist *sg_req, *sg_resp; + struct hisi_sas_device *sas_dev = device->lldd_dev; + dma_addr_t req_dma_addr; + unsigned int req_len, resp_len; + int elem, rc; + + /* + * DMA-map SMP request, response buffers + */ + /* req */ + sg_req = &task->smp_task.smp_req; + elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE); + if (!elem) + return -ENOMEM; + req_len = sg_dma_len(sg_req); + req_dma_addr = sg_dma_address(sg_req); + + /* resp */ + sg_resp = &task->smp_task.smp_resp; + elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE); + if (!elem) { + rc = -ENOMEM; + goto err_out_req; + } + resp_len = sg_dma_len(sg_resp); + if ((req_len & 0x3) || (resp_len & 0x3)) { + rc = -EINVAL; + goto err_out_resp; + } + + /* create header */ + /* dw0 */ + hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | + (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ + (2 << CMD_HDR_CMD_OFF)); /* smp */ + + /* map itct entry */ + hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | + (1 << CMD_HDR_FRAME_TYPE_OFF) | + (DIR_NO_DATA << CMD_HDR_DIR_OFF)); + + /* dw2 */ + hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | + (HISI_SAS_MAX_SMP_RESP_SZ / 4 << + CMD_HDR_MRFL_OFF)); + + hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); + + hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); + hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); + + return 0; + +err_out_resp: + dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1, + DMA_FROM_DEVICE); +err_out_req: + dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1, + DMA_TO_DEVICE); + return rc; +} + static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) { int i, res = 0; @@ -1394,6 +1467,7 @@ static void hisi_sas_v3_remove(struct pci_dev *pdev) .sl_notify = sl_notify_v3_hw, .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), .prep_ssp = prep_ssp_v3_hw, + .prep_smp = prep_smp_v3_hw, .get_free_slot = get_free_slot_v3_hw, .start_delivery = start_delivery_v3_hw, .slot_complete = slot_complete_v3_hw, From patchwork Thu May 25 12:05:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100487 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp718075qge; Thu, 25 May 2017 04:35:42 -0700 (PDT) X-Received: by 10.84.232.141 with SMTP id i13mr49588272plk.143.1495712142563; Thu, 25 May 2017 04:35:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495712142; cv=none; d=google.com; s=arc-20160816; b=OVkoR49ql/qMvruWFfvjZWCGICZzYGurZeRvDR0P+WoV7+MXbOCpGckdwkr4l5nVr7 gYRdvErnzNVNl/w9B4MWD7dT85e0W45jedscfs1Zm520YjezQcxWlVpZ5PPbKnShF4Jh oMIBK6QIJrI0nCT/fGL/8FssDX/UAkQXWIhrH31YYsyUm13QC5lbIRljXnOPpmrTueH/ SyxQu+TxqYXqY812uvQpHTINXP6hEKAGQyrDgwHdbyHoLr+tNyy8k925gQR7yO01ffnM BoKmHT96I6wspntt7f5jP8ZA9/0AriMwnHlE80cQ0SA3TclMK8gOSkqyt5Cp3O63geju dw6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=VrkR66IGNwqDqoNg3wsmlI1ZTno9BeAEeTIQldom7D4=; b=U5DSNbdvLqLbCCTbyMM1k6kH6bdroNr22u7bvZXdNNDL5EbePAWFw2KrmX1GYDS3XX hr3mbLKmHeXMhWqTkEGWnRCHFt7N2AqFPWvl+2h5lshEdBwtrTwwfmCKcybEOJRsT1PY bdusA17RXpmXAvtCnv7yhlv8lsgyyXZhf6sG5IJlPuBe1PjVLvjhvDz69jAFMAIRHwZr 7UggWeqfDysmcmPOfGGKni6+wsdN1hnEoZU8EHOpvkVUbjLonxYI/DSqZrHiOuWBzqsz ZEjNdsuAcg8gjnIga8UhqRKrXfFAZR7oZk+RQfTg5ML7e6TTDKGsx6ZUd8YabooHYRc2 HLCg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y2si5444651pgo.217.2017.05.25.04.35.42; Thu, 25 May 2017 04:35:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1764720AbdEYLfc (ORCPT + 25 others); Thu, 25 May 2017 07:35:32 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6381 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1764287AbdEYLel (ORCPT ); Thu, 25 May 2017 07:34:41 -0400 Received: from 172.30.72.53 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOF01634; Thu, 25 May 2017 19:34:33 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:23 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH v2 16/22] scsi: hisi_sas: add v3 code to send ATA frame Date: Thu, 25 May 2017 20:05:05 +0800 Message-ID: <1495713911-80476-17-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020204.5926C149.0164, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 5ade427ce96aef7a86f686d09cc22bb5 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add code to prepare ATA frame for v3 hw Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 106 +++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 5de4738..e682ad7 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -171,8 +171,11 @@ #define CMD_HDR_CMD_OFF 29 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) /* dw1 */ +#define CMD_HDR_UNCON_CMD_OFF 3 #define CMD_HDR_DIR_OFF 5 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) +#define CMD_HDR_RESET_OFF 7 +#define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) #define CMD_HDR_VDTL_OFF 10 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) #define CMD_HDR_FRAME_TYPE_OFF 11 @@ -182,6 +185,8 @@ /* dw2 */ #define CMD_HDR_CFL_OFF 0 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) +#define CMD_HDR_NCQ_TAG_OFF 10 +#define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) #define CMD_HDR_MRFL_OFF 15 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) #define CMD_HDR_SG_MOD_OFF 24 @@ -246,6 +251,11 @@ enum { #define DIR_TO_DEVICE 2 #define DIR_RESERVED 3 +#define CMD_IS_UNCONSTRAINT(cmd) \ + ((cmd == ATA_CMD_READ_LOG_EXT) || \ + (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \ + (cmd == ATA_CMD_DEV_RESET)) + static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) { void __iomem *regs = hisi_hba->regs + off; @@ -711,6 +721,101 @@ static int prep_smp_v3_hw(struct hisi_hba *hisi_hba, return rc; } +static int get_ncq_tag_v3_hw(struct sas_task *task, u32 *tag) +{ + struct ata_queued_cmd *qc = task->uldd_task; + + if (qc) { + if (qc->tf.command == ATA_CMD_FPDMA_WRITE || + qc->tf.command == ATA_CMD_FPDMA_READ) { + *tag = qc->tag; + return 1; + } + } + return 0; +} + +static int prep_ata_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_slot *slot) +{ + struct sas_task *task = slot->task; + struct domain_device *device = task->dev; + struct domain_device *parent_dev = device->parent; + struct hisi_sas_device *sas_dev = device->lldd_dev; + struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; + struct asd_sas_port *sas_port = device->port; + struct hisi_sas_port *port = to_hisi_sas_port(sas_port); + u8 *buf_cmd; + int has_data = 0, rc = 0, hdr_tag = 0; + u32 dw1 = 0, dw2 = 0; + + hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); + if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) + hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); + else + hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); + + switch (task->data_dir) { + case DMA_TO_DEVICE: + has_data = 1; + dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; + break; + case DMA_FROM_DEVICE: + has_data = 1; + dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; + break; + default: + dw1 &= ~CMD_HDR_DIR_MSK; + } + + if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && + (task->ata_task.fis.control & ATA_SRST)) + dw1 |= 1 << CMD_HDR_RESET_OFF; + + dw1 |= (hisi_sas_get_ata_protocol( + task->ata_task.fis.command, task->data_dir)) + << CMD_HDR_FRAME_TYPE_OFF; + dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; + + if (CMD_IS_UNCONSTRAINT(task->ata_task.fis.command)) + dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; + + hdr->dw1 = cpu_to_le32(dw1); + + /* dw2 */ + if (task->ata_task.use_ncq && get_ncq_tag_v3_hw(task, &hdr_tag)) { + task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); + dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; + } + + dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | + 2 << CMD_HDR_SG_MOD_OFF; + hdr->dw2 = cpu_to_le32(dw2); + + /* dw3 */ + hdr->transfer_tags = cpu_to_le32(slot->idx); + + if (has_data) { + rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, + slot->n_elem); + if (rc) + return rc; + } + + hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); + hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma); + hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); + + buf_cmd = slot->command_table; + + if (likely(!task->ata_task.device_control_reg_update)) + task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ + /* fill in command FIS */ + memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); + + return 0; +} + static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) { int i, res = 0; @@ -1468,6 +1573,7 @@ static void hisi_sas_v3_remove(struct pci_dev *pdev) .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), .prep_ssp = prep_ssp_v3_hw, .prep_smp = prep_smp_v3_hw, + .prep_stp = prep_ata_v3_hw, .get_free_slot = get_free_slot_v3_hw, .start_delivery = start_delivery_v3_hw, .slot_complete = slot_complete_v3_hw, From patchwork Thu May 25 12:05:06 2017 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id t188si27566804pgc.259.2017.05.25.04.37.04; Thu, 25 May 2017 04:37:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1765194AbdEYLgs (ORCPT + 25 others); Thu, 25 May 2017 07:36:48 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6822 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1764064AbdEYLei (ORCPT ); Thu, 25 May 2017 07:34:38 -0400 Received: from 172.30.72.53 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOF01646; Thu, 25 May 2017 19:34:35 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:23 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH v2 17/22] scsi: hisi_sas: add v3 code for itct setup and free Date: Thu, 25 May 2017 20:05:06 +0800 Message-ID: <1495713911-80476-18-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.5926C14B.01B7, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 60ed5bb8a285d1eb060217695b3a048e Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add code to itct setup and free for v3 hw. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 115 +++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index e682ad7..c8b6997 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -24,6 +24,11 @@ #define PHY_PORT_NUM_MA 0x28 #define PHY_CONN_RATE 0x30 #define AXI_AHB_CLK_CFG 0x3c +#define ITCT_CLR 0x44 +#define ITCT_CLR_EN_OFF 16 +#define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) +#define ITCT_DEV_OFF 0 +#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) #define AXI_USER1 0x48 #define AXI_USER2 0x4c #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 @@ -226,6 +231,27 @@ #define CMPLT_HDR_IO_IN_TARGET_OFF 17 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) +/* ITCT header */ +/* qw0 */ +#define ITCT_HDR_DEV_TYPE_OFF 0 +#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) +#define ITCT_HDR_VALID_OFF 2 +#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) +#define ITCT_HDR_MCR_OFF 5 +#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) +#define ITCT_HDR_VLN_OFF 9 +#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) +#define ITCT_HDR_SMP_TIMEOUT_OFF 16 +#define ITCT_HDR_AWT_CONTINUE_OFF 25 +#define ITCT_HDR_PORT_ID_OFF 28 +#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) +/* qw2 */ +#define ITCT_HDR_INLT_OFF 0 +#define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) +#define ITCT_HDR_RTOLT_OFF 48 +#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) + + struct hisi_sas_complete_v3_hdr { __le32 dw0; __le32 dw1; @@ -446,6 +472,93 @@ static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) __swab32(identify_buffer[5])); } +static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_device *sas_dev) +{ + struct domain_device *device = sas_dev->sas_device; + struct device *dev = hisi_hba->dev; + u64 qw0, device_id = sas_dev->device_id; + struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; + struct domain_device *parent_dev = device->parent; + struct asd_sas_port *sas_port = device->port; + struct hisi_sas_port *port = to_hisi_sas_port(sas_port); + + memset(itct, 0, sizeof(*itct)); + + /* qw0 */ + qw0 = 0; + switch (sas_dev->dev_type) { + case SAS_END_DEVICE: + case SAS_EDGE_EXPANDER_DEVICE: + case SAS_FANOUT_EXPANDER_DEVICE: + qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; + break; + case SAS_SATA_DEV: + case SAS_SATA_PENDING: + if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) + qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; + else + qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; + break; + default: + dev_warn(dev, "setup itct: unsupported dev type (%d)\n", + sas_dev->dev_type); + } + + qw0 |= ((1 << ITCT_HDR_VALID_OFF) | + (device->linkrate << ITCT_HDR_MCR_OFF) | + (1 << ITCT_HDR_VLN_OFF) | + (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | + (1 << ITCT_HDR_AWT_CONTINUE_OFF) | + (port->id << ITCT_HDR_PORT_ID_OFF)); + itct->qw0 = cpu_to_le64(qw0); + + /* qw1 */ + memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE); + itct->sas_addr = __swab64(itct->sas_addr); + + /* qw2 */ + if (!dev_is_sata(device)) + itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | + (0x1ULL << ITCT_HDR_RTOLT_OFF)); +} + +static void free_device_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_device *sas_dev) +{ + u64 dev_id = sas_dev->device_id; + struct device *dev = hisi_hba->dev; + struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; + u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); + + /* clear the itct interrupt state */ + if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) + hisi_sas_write32(hisi_hba, ENT_INT_SRC3, + ENT_INT_SRC3_ITC_INT_MSK); + + /* clear the itct table*/ + reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); + reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); + hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); + + udelay(10); + reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); + if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) { + dev_dbg(dev, "got clear ITCT done interrupt\n"); + + /* invalid the itct state*/ + memset(itct, 0, sizeof(struct hisi_sas_itct)); + hisi_sas_write32(hisi_hba, ENT_INT_SRC3, + ENT_INT_SRC3_ITC_INT_MSK); + hisi_hba->devices[dev_id].dev_type = SAS_PHY_UNUSED; + hisi_hba->devices[dev_id].dev_status = HISI_SAS_DEV_NORMAL; + + /* clear the itct */ + hisi_sas_write32(hisi_hba, ITCT_CLR, 0); + dev_dbg(dev, "clear ITCT ok\n"); + } +} + static int hw_init_v3_hw(struct hisi_hba *hisi_hba) { init_reg_v3_hw(hisi_hba); @@ -1568,9 +1681,11 @@ static void hisi_sas_v3_remove(struct pci_dev *pdev) static const struct hisi_sas_hw hisi_sas_v3_hw = { .hw_init = hisi_sas_v3_init, + .setup_itct = setup_itct_v3_hw, .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, .sl_notify = sl_notify_v3_hw, .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), + .free_device = free_device_v3_hw, .prep_ssp = prep_ssp_v3_hw, .prep_smp = prep_smp_v3_hw, .prep_stp = prep_ata_v3_hw, From patchwork Thu May 25 12:05:07 2017 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id d29si28384947plj.192.2017.05.25.04.36.05; Thu, 25 May 2017 04:36:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423852AbdEYLf0 (ORCPT + 25 others); Thu, 25 May 2017 07:35:26 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6384 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1764365AbdEYLem (ORCPT ); Thu, 25 May 2017 07:34:42 -0400 Received: from 172.30.72.53 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOF01641; Thu, 25 May 2017 19:34:34 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:23 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH v2 18/22] scsi: hisi_sas: add v3 code to send internal abort command Date: Thu, 25 May 2017 20:05:07 +0800 Message-ID: <1495713911-80476-19-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.5926C14A.0163, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d61670bde157b0d1bc700b0008cc603a Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add code to prepare internal abort command. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 38 ++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index c8b6997..6273368 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -165,6 +165,10 @@ /* HW dma structures */ /* Delivery queue header */ /* dw0 */ +#define CMD_HDR_ABORT_FLAG_OFF 0 +#define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) +#define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 +#define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) #define CMD_HDR_RESP_REPORT_OFF 5 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) #define CMD_HDR_TLR_CTRL_OFF 6 @@ -204,6 +208,11 @@ #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) #define CMD_HDR_DATA_SGL_LEN_OFF 16 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) +/* dw7 */ +#define CMD_HDR_ADDR_MODE_SEL_OFF 15 +#define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) +#define CMD_HDR_ABORT_IPTT_OFF 16 +#define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) /* Completion header */ /* dw0 */ @@ -929,6 +938,34 @@ static int prep_ata_v3_hw(struct hisi_hba *hisi_hba, return 0; } +static int prep_abort_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_slot *slot, + int device_id, int abort_flag, int tag_to_abort) +{ + struct sas_task *task = slot->task; + struct domain_device *dev = task->dev; + struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; + struct hisi_sas_port *port = slot->port; + + /* dw0 */ + hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ + (port->id << CMD_HDR_PORT_OFF) | + ((dev_is_sata(dev) ? 1:0) + << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | + (abort_flag + << CMD_HDR_ABORT_FLAG_OFF)); + + /* dw1 */ + hdr->dw1 = cpu_to_le32(device_id + << CMD_HDR_DEV_ID_OFF); + + /* dw7 */ + hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); + hdr->transfer_tags = cpu_to_le32(slot->idx); + + return 0; +} + static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) { int i, res = 0; @@ -1689,6 +1726,7 @@ static void hisi_sas_v3_remove(struct pci_dev *pdev) .prep_ssp = prep_ssp_v3_hw, .prep_smp = prep_smp_v3_hw, .prep_stp = prep_ata_v3_hw, + .prep_abort = prep_abort_v3_hw, .get_free_slot = get_free_slot_v3_hw, .start_delivery = start_delivery_v3_hw, .slot_complete = slot_complete_v3_hw, From patchwork Thu May 25 12:05:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100493 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp718697qge; Thu, 25 May 2017 04:37:40 -0700 (PDT) X-Received: by 10.98.40.198 with SMTP id o189mr45094741pfo.238.1495712259949; Thu, 25 May 2017 04:37:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495712259; cv=none; d=google.com; s=arc-20160816; b=YXvk/mvrp7GutBsKVcOAt4mbS2F6NKhTY4tJD7v/62NRs2o4/1VyFPwnvhreREv+Sa uzOoSCXu1ytprOxsGmov/GKCCgLpX4WVKdwTuQ/wXCcm0/5U3mILoncxB9W5K50wrUX5 Xbb2rs8Dlf6//ilf5Q42ztCa1z3lxPe3t6R67itfqADsGYY2YzPYseAMfZTRsT0lZ0Ed xLGNYnGF8oxFSMCU6FnsAMoeghpvODadhlDx5jK5Jzq3E9/ZhMqloe8XphicAlUisEvI pgTzxGwIvVwgM3As1G9pUuagkJc4ipb5SP9U+xaLWGNB2Z1LUqMgl4OUNfuMIURjwAQu wgsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=PPLlerIP6UmES6xpXu0jJRxqNoh46zVhJD39tOGwhvE=; b=L/vLxYy8ECA/Fk593g8UE2GSjTahuw+mzjBV/3r+NFRLfkyZx0CcG6ckLmkzoL7X+d pRTcKZyEdxE1ozyxCT3FbLFk5++ihW+oYMHjb+JGjoAy8WFLcVKGuNMUl4Me/SrPWKY/ zuNWoQHqwTMI6tShjHe5lOkSk8BpXSFq/zcGyRpzz6gKuu4HvmyBZpeDfymsd8ZLTRyL vvQoO/mILPcykNLhrZydITsHbmibjxgzr6y/SKqL4RMZB6VSNLaVLtro/PjS8BE7cJAb DPJXjCq8jwaij6wFy6tWvCzeaPZDgkLJYVg2OEQ9O+mdM46iAQvtcCS0UxB2KRnA/HP7 Pc3w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l62si2211170pge.309.2017.05.25.04.37.39; Thu, 25 May 2017 04:37:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423939AbdEYLh0 (ORCPT + 25 others); Thu, 25 May 2017 07:37:26 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6385 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763946AbdEYLeh (ORCPT ); Thu, 25 May 2017 07:34:37 -0400 Received: from 172.30.72.53 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOF01642; Thu, 25 May 2017 19:34:34 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:24 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH v2 19/22] scsi: hisi_sas: add get_wideport_bitmap_v3_hw() Date: Thu, 25 May 2017 20:05:08 +0800 Message-ID: <1495713911-80476-20-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.5926C14B.001C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 6ec8f0d8ecabf5a01886f362295cd183 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add code for interface get_wide_port_bitmap_v3_hw(). Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 6273368..4169e6a 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -616,6 +616,18 @@ static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no) hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); } +static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) +{ + int i, bitmap = 0; + u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); + + for (i = 0; i < hisi_hba->n_phy; i++) + if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) + bitmap |= 1 << i; + + return bitmap; +} + /** * The callpath to this function and upto writing the write * queue pointer should be safe from interruption. @@ -1721,6 +1733,7 @@ static void hisi_sas_v3_remove(struct pci_dev *pdev) .setup_itct = setup_itct_v3_hw, .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, .sl_notify = sl_notify_v3_hw, + .get_wideport_bitmap = get_wideport_bitmap_v3_hw, .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), .free_device = free_device_v3_hw, .prep_ssp = prep_ssp_v3_hw, From patchwork Thu May 25 12:05:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100489 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp718343qge; Thu, 25 May 2017 04:36:34 -0700 (PDT) X-Received: by 10.98.209.22 with SMTP id z22mr42787502pfg.95.1495712194522; Thu, 25 May 2017 04:36:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495712194; cv=none; d=google.com; s=arc-20160816; b=tG/Lf0NZAA0PbzWaOCLxDmcg5WxkAa9VGPJnXv872L5dGfE4L2vlVRZnMcfbt03iDn CehSESFnqBiuNrxRk3FSZnjQBOEMV0QKhAeUxJ9oLGMhdswhWLOBL4VOsP4lUnXp9jZ0 Cw3fTWU+BC38VXxeeTHyTZwtWqoEQMyeytfiDm9G5AEW9UeejFWeoT96op/8TecYblyI ZzQeofgrl5LCoMknfqceLAiXtB1gABWUNxCr+tCpkfT9gXhyxDmsxy1qsFRDwrYaBMz4 IGtHRIEtdredwnus0c6O+ARZhL6PXNaFpish58vagwYzfgfS2Nr3Nj8nCoTR2mc0DIg0 Xb9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=p/V+3Gw32qoKZKRv26t+BOP6fwfdtj8XEGY5h2wYk8w=; b=Tb5ChbyZveCIG0NKGgvHZ4f+/Q2wgTGxjClxLPG/48jzLNvYRy6XvMHr8cNupgWJWY s+OHICDmtiT8idsWjWpSqkBvrl22FLaBYEKR6S7eLD/V2f0zxgKxCLxSfkbkCPwi2zcx LRJ9Sth5q5/fOxpePlzNsbrYSJA9M8nHJV850TK7cpMRbDKhitXWk3JuHpA7FqaQf39d wGbl5mKdYBIkct8+X3M9GZJHPSNPdA/gzwlxXThgEdhlz16wMjxO/huQJRS667CQ2rcB 6a+IhX3fkqo0xj2XJvNLMk0vFq9tHm+0gYk1W2ZjzZByQN7luYSo3qQ7SVE0Uf4fwQY6 GKQw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 6si10541465pfe.109.2017.05.25.04.36.34; Thu, 25 May 2017 04:36:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1765078AbdEYLgP (ORCPT + 25 others); Thu, 25 May 2017 07:36:15 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6824 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1764216AbdEYLej (ORCPT ); Thu, 25 May 2017 07:34:39 -0400 Received: from 172.30.72.53 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOF01648; Thu, 25 May 2017 19:34:35 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:24 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH v2 20/22] scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error Date: Thu, 25 May 2017 20:05:09 +0800 Message-ID: <1495713911-80476-21-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.5926C14C.0170, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 7ce77de5ef3016851b07c3f8ff768a9c Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen For ECC 1bit error, logic can recover it, so we only print a warning. For ECC multi-bit and AXI bus fatal error, we panic. Note: once v3 hw controller reset support is added, the panic will be replaced by a controller reset, like v2 hw. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 401 ++++++++++++++++++++++++++++++++- 1 file changed, 399 insertions(+), 2 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 4169e6a..9add347 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -51,7 +51,39 @@ #define CFG_SET_ABORTED_IPTT_OFF 0 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) #define CFG_1US_TIMER_TRSH 0xcc +#define HGC_LM_DFX_STATUS2 0x128 +#define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0 +#define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff <<\ + HGC_LM_DFX_STATUS2_IOSTLIST_OFF) +#define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12 +#define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff <<\ + HGC_LM_DFX_STATUS2_ITCTLIST_OFF) +#define HGC_CQE_ECC_ADDR 0x13c +#define HGC_CQE_ECC_1B_ADDR_OFF 0 +#define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF) +#define HGC_CQE_ECC_MB_ADDR_OFF 8 +#define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF) +#define HGC_IOST_ECC_ADDR 0x140 +#define HGC_IOST_ECC_1B_ADDR_OFF 0 +#define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF) +#define HGC_IOST_ECC_MB_ADDR_OFF 16 +#define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF) +#define HGC_DQE_ECC_ADDR 0x144 +#define HGC_DQE_ECC_1B_ADDR_OFF 0 +#define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF) +#define HGC_DQE_ECC_MB_ADDR_OFF 16 +#define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF) #define CHNL_INT_STATUS 0x148 +#define HGC_ITCT_ECC_ADDR 0x150 +#define HGC_ITCT_ECC_1B_ADDR_OFF 0 +#define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << HGC_ITCT_ECC_1B_ADDR_OFF) +#define HGC_ITCT_ECC_MB_ADDR_OFF 16 +#define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << HGC_ITCT_ECC_MB_ADDR_OFF) +#define HGC_AXI_FIFO_ERR_INFO 0x154 +#define AXI_ERR_INFO_OFF 0 +#define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) +#define FIFO_ERR_INFO_OFF 8 +#define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) #define INT_COAL_EN 0x19c #define OQ_INT_COAL_TIME 0x1a0 #define OQ_INT_COAL_CNT 0x1a4 @@ -85,6 +117,26 @@ #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) #define SAS_ECC_INTR 0x1e8 #define SAS_ECC_INTR_MSK 0x1ec +#define SAS_ECC_INTR_DQE_ECC_1B_OFF 0 +#define SAS_ECC_INTR_DQE_ECC_MB_OFF 1 +#define SAS_ECC_INTR_IOST_ECC_1B_OFF 2 +#define SAS_ECC_INTR_IOST_ECC_MB_OFF 3 +#define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4 +#define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5 +#define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6 +#define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7 +#define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 8 +#define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 9 +#define SAS_ECC_INTR_CQE_ECC_1B_OFF 10 +#define SAS_ECC_INTR_CQE_ECC_MB_OFF 11 +#define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12 +#define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13 +#define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14 +#define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15 +#define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16 +#define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17 +#define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18 +#define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19 #define HGC_ERR_STAT_EN 0x238 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 @@ -98,6 +150,20 @@ #define COMPL_Q_0_DEPTH 0x4e8 #define COMPL_Q_0_WR_PTR 0x4ec #define COMPL_Q_0_RD_PTR 0x4f0 +#define HGC_RXM_DFX_STATUS14 0xae8 +#define HGC_RXM_DFX_STATUS14_MEM0_OFF 0 +#define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff <<\ + HGC_RXM_DFX_STATUS14_MEM0_OFF) +#define HGC_RXM_DFX_STATUS14_MEM1_OFF 9 +#define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff <<\ + HGC_RXM_DFX_STATUS14_MEM1_OFF) +#define HGC_RXM_DFX_STATUS14_MEM2_OFF 18 +#define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff <<\ + HGC_RXM_DFX_STATUS14_MEM2_OFF) +#define HGC_RXM_DFX_STATUS15 0xaec +#define HGC_RXM_DFX_STATUS15_MEM3_OFF 0 +#define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff <<\ + HGC_RXM_DFX_STATUS15_MEM3_OFF) #define AWQOS_AWCACHE_CFG 0xc84 #define ARQOS_ARCACHE_CFG 0xc88 @@ -260,6 +326,7 @@ #define ITCT_HDR_RTOLT_OFF 48 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) +#define HISI_SAS_FATAL_INT_NR 2 struct hisi_sas_complete_v3_hdr { __le32 dw0; @@ -1171,8 +1238,9 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) irq_value1) { if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK | CHL_INT1_DMAC_TX_ECC_ERR_MSK)) - panic("%s: DMAC RX/TX ecc bad error! (0x%x)", - dev_name(dev), irq_value1); + panic("%s: DMAC RX/TX ecc bad error!" + " (0x%x)", + dev_name(dev), irq_value1); hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value1); @@ -1199,6 +1267,320 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) return IRQ_HANDLED; } +static void one_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba, + u32 irq_value) +{ + struct device *dev = hisi_hba->dev; + u32 reg_val; + + if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_DQE_ECC_ADDR); + dev_info(dev, "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n", + (reg_val & HGC_DQE_ECC_1B_ADDR_MSK) + >> HGC_DQE_ECC_1B_ADDR_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR); + dev_info(dev, "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n", + (reg_val & HGC_IOST_ECC_1B_ADDR_MSK) + >> HGC_IOST_ECC_1B_ADDR_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR); + dev_info(dev, "hgc_itct_acc1b_intr found: Ram address is 0x%08X\n", + (reg_val & HGC_ITCT_ECC_1B_ADDR_MSK) + >> HGC_ITCT_ECC_1B_ADDR_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2); + dev_info(dev, "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n", + (reg_val & HGC_LM_DFX_STATUS2_IOSTLIST_MSK) + >> HGC_LM_DFX_STATUS2_IOSTLIST_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2); + dev_info(dev, "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n", + (reg_val & HGC_LM_DFX_STATUS2_ITCTLIST_MSK) + >> HGC_LM_DFX_STATUS2_ITCTLIST_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_CQE_ECC_ADDR); + dev_info(dev, "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n", + (reg_val & HGC_CQE_ECC_1B_ADDR_MSK) + >> HGC_CQE_ECC_1B_ADDR_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14); + dev_info(dev, "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n", + (reg_val & HGC_RXM_DFX_STATUS14_MEM0_MSK) + >> HGC_RXM_DFX_STATUS14_MEM0_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14); + dev_info(dev, "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n", + (reg_val & HGC_RXM_DFX_STATUS14_MEM1_MSK) + >> HGC_RXM_DFX_STATUS14_MEM1_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14); + dev_info(dev, "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n", + (reg_val & HGC_RXM_DFX_STATUS14_MEM2_MSK) + >> HGC_RXM_DFX_STATUS14_MEM2_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS15); + dev_info(dev, "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n", + (reg_val & HGC_RXM_DFX_STATUS15_MEM3_MSK) + >> HGC_RXM_DFX_STATUS15_MEM3_OFF); + } + +} + +static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba, + u32 irq_value) +{ + u32 reg_val; + struct device *dev = hisi_hba->dev; + + if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_DQE_ECC_ADDR); + panic("%s: hgc_dqe_accbad_intr (0x%x) found:" + " Ram address is 0x%08X\n", + dev_name(dev), irq_value, + (reg_val & HGC_DQE_ECC_MB_ADDR_MSK) + >> HGC_DQE_ECC_MB_ADDR_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR); + panic("%s: hgc_iost_accbad_intr (0x%x) found:" + " Ram address is 0x%08X\n", + dev_name(dev), irq_value, + (reg_val & HGC_IOST_ECC_MB_ADDR_MSK) + >> HGC_IOST_ECC_MB_ADDR_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR); + panic("%s: hgc_itct_accbad_intr (0x%x) found:" + " Ram address is 0x%08X\n", + dev_name(dev), irq_value, + (reg_val & HGC_ITCT_ECC_MB_ADDR_MSK) + >> HGC_ITCT_ECC_MB_ADDR_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2); + panic("%s: hgc_iostl_accbad_intr (0x%x) found:" + " memory address is 0x%08X\n", + dev_name(dev), irq_value, + (reg_val & HGC_LM_DFX_STATUS2_IOSTLIST_MSK) + >> HGC_LM_DFX_STATUS2_IOSTLIST_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2); + panic("%s: hgc_itctl_accbad_intr (0x%x) found:" + " memory address is 0x%08X\n", + dev_name(dev), irq_value, + (reg_val & HGC_LM_DFX_STATUS2_ITCTLIST_MSK) + >> HGC_LM_DFX_STATUS2_ITCTLIST_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_CQE_ECC_ADDR); + panic("%s: hgc_cqe_accbad_intr (0x%x) found:" + " Ram address is 0x%08X\n", + dev_name(dev), irq_value, + (reg_val & HGC_CQE_ECC_MB_ADDR_MSK) + >> HGC_CQE_ECC_MB_ADDR_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14); + panic("%s: rxm_mem0_accbad_intr (0x%x) found:" + "memory address is 0x%08X\n", + dev_name(dev), irq_value, + (reg_val & HGC_RXM_DFX_STATUS14_MEM0_MSK) + >> HGC_RXM_DFX_STATUS14_MEM0_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14); + panic("%s: rxm_mem1_accbad_intr (0x%x) found:" + " memory address is 0x%08X\n", + dev_name(dev), irq_value, + (reg_val & HGC_RXM_DFX_STATUS14_MEM1_MSK) + >> HGC_RXM_DFX_STATUS14_MEM1_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14); + panic("%s: rxm_mem2_accbad_intr (0x%x) found:" + " memory address is 0x%08X\n", + dev_name(dev), irq_value, + (reg_val & HGC_RXM_DFX_STATUS14_MEM2_MSK) + >> HGC_RXM_DFX_STATUS14_MEM2_OFF); + } + + if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF)) { + reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS15); + panic("%s: rxm_mem3_accbad_intr (0x%x) found:" + " memory address is 0x%08X\n", + dev_name(dev), irq_value, + (reg_val & HGC_RXM_DFX_STATUS15_MEM3_MSK) + >> HGC_RXM_DFX_STATUS15_MEM3_OFF); + } + +} + +static irqreturn_t fatal_ecc_int_v3_hw(int irq_no, struct hisi_hba *hisi_hba) +{ + u32 irq_value, irq_msk; + + irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK); + hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff); + + irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR); + if (irq_value) { + multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value); + one_bit_ecc_error_process_v3_hw(hisi_hba, irq_value); + } + + hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value); + hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk); + + return IRQ_HANDLED; +} + +#define AXI_ERR_NR 8 +static const char axi_err_info[AXI_ERR_NR][32] = { + "IOST_AXI_W_ERR", + "IOST_AXI_R_ERR", + "ITCT_AXI_W_ERR", + "ITCT_AXI_R_ERR", + "SATA_AXI_W_ERR", + "SATA_AXI_R_ERR", + "DQE_AXI_R_ERR", + "CQE_AXI_W_ERR" +}; + +#define FIFO_ERR_NR 5 +static const char fifo_err_info[FIFO_ERR_NR][32] = { + "CQE_WINFO_FIFO", + "CQE_MSG_FIFIO", + "GETDQE_FIFO", + "CMDP_FIFO", + "AWTCTRL_FIFO" +}; + +static irqreturn_t fatal_axi_int_v3_hw(int irq_no, struct hisi_hba *hisi_hba) +{ + u32 irq_value, irq_msk, err_value; + struct device *dev = hisi_hba->dev; + + irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe); + + irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); + if (irq_value) { + if (irq_value & BIT(ENT_INT_SRC3_WP_DEPTH_OFF)) { + hisi_sas_write32(hisi_hba, ENT_INT_SRC3, + 1 << ENT_INT_SRC3_WP_DEPTH_OFF); + panic("%s: write pointer and depth error (0x%x) found!\n", + dev_name(dev), irq_value); + } + + if (irq_value & BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF)) { + hisi_sas_write32(hisi_hba, ENT_INT_SRC3, + 1 << ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF); + panic("%s: iptt no match slot error (0x%x) found!\n", + dev_name(dev), irq_value); + } + + if (irq_value & BIT(ENT_INT_SRC3_RP_DEPTH_OFF)) + panic("%s: read pointer and depth error (0x%x) found!\n", + dev_name(dev), irq_value); + + if (irq_value & BIT(ENT_INT_SRC3_AXI_OFF)) { + int i; + + hisi_sas_write32(hisi_hba, ENT_INT_SRC3, + 1 << ENT_INT_SRC3_AXI_OFF); + err_value = hisi_sas_read32(hisi_hba, + HGC_AXI_FIFO_ERR_INFO); + + for (i = 0; i < AXI_ERR_NR; i++) { + if (err_value & BIT(i)) + panic("%s: %s (0x%x) found!\n", + dev_name(dev), + axi_err_info[i], irq_value); + } + } + + if (irq_value & BIT(ENT_INT_SRC3_FIFO_OFF)) { + int i; + + hisi_sas_write32(hisi_hba, ENT_INT_SRC3, + 1 << ENT_INT_SRC3_FIFO_OFF); + err_value = hisi_sas_read32(hisi_hba, + HGC_AXI_FIFO_ERR_INFO); + + for (i = 0; i < FIFO_ERR_NR; i++) { + if (err_value & BIT(AXI_ERR_NR + i)) + panic("%s: %s (0x%x) found!\n", + dev_name(dev), + fifo_err_info[i], irq_value); + } + + } + + if (irq_value & BIT(ENT_INT_SRC3_LM_OFF)) { + hisi_sas_write32(hisi_hba, ENT_INT_SRC3, + 1 << ENT_INT_SRC3_LM_OFF); + panic("%s: LM add/fetch list error (0x%x) found!\n", + dev_name(dev), irq_value); + } + + if (irq_value & BIT(ENT_INT_SRC3_ABT_OFF)) { + hisi_sas_write32(hisi_hba, ENT_INT_SRC3, + 1 << ENT_INT_SRC3_ABT_OFF); + panic("%s: SAS_HGC_ABT fetch LM list error (0x%x) found!\n", + dev_name(dev), irq_value); + } + } + + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); + + return IRQ_HANDLED; +} + +static irqreturn_t fatal_interrupt_v3_hw(int irq_no, void *p) +{ + struct hisi_hba *hisi_hba = p; + u32 irq_value1, irq_value2; + + irq_value1 = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); + irq_value2 = hisi_sas_read32(hisi_hba, SAS_ECC_INTR); + + if (irq_value1) + return fatal_axi_int_v3_hw(irq_no, hisi_hba); + + if (irq_value2) + return fatal_ecc_int_v3_hw(irq_no, hisi_hba); + + return IRQ_NONE; +} + static void slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, struct hisi_sas_slot *slot) @@ -1525,6 +1907,21 @@ static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) } } + irq = msi_vectors[11]; + if (!irq) { + dev_err(dev, "irq init: fail map fatal interrupt 11\n"); + return -ENOENT; + } + + rc = devm_request_irq(dev, irq, fatal_interrupt_v3_hw, 0, + DRV_NAME " fatal", hisi_hba); + if (rc) { + dev_err(dev, + "irq init: could not request fatal interrupt 11, rc=%d\n", + rc); + return -ENOENT; + } + for (i = 0; i < hisi_hba->queue_count; i++) { int idx = i + 16; /* First cq interrupt is irq16 */ struct hisi_sas_cq *cq = &hisi_hba->cq[i]; From patchwork Thu May 25 12:05:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100494 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp718853qge; Thu, 25 May 2017 04:38:05 -0700 (PDT) X-Received: by 10.99.171.65 with SMTP id k1mr14537824pgp.150.1495712285113; Thu, 25 May 2017 04:38:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495712285; cv=none; d=google.com; s=arc-20160816; b=BhZW9leBmYuBPDvWy3FLiy6xubZTmfvb5FrLTkenIP/eN8ldcf5xFyrFmiS3Ealvex ITjhYdjPkBZnq6QFFP2NzqNpKjbh//jpnBTpIh95WNrWeJgX6+kBFWleurtIqZ8fW1RD 3gGxwnQQQyaH3Wn7H5ZDbEjSaOYGxln2XbBH1zEHz7rzlcGLslQ339kCVmCJC+Tl1MDf shki3PN4l93EyvGYZUw4gwvXVTf+Ndha5yWXhuw1X1ybQ7TRCuNx3qEF8qNVm5OwY8VQ +fCMUuEEhLCFfIUUFgTyDW0QBRfY2jOMhcVt4VCyMISKN4mF/oN9JebdnFDRhksFIvo3 C8eg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[209.132.180.67]) by mx.google.com with ESMTP id l62si2211170pge.309.2017.05.25.04.38.04; Thu, 25 May 2017 04:38:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423902AbdEYLhS (ORCPT + 25 others); Thu, 25 May 2017 07:37:18 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6387 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763982AbdEYLeh (ORCPT ); Thu, 25 May 2017 07:34:37 -0400 Received: from 172.30.72.53 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOF01645; Thu, 25 May 2017 19:34:35 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Thu, 25 May 2017 19:34:25 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH v2 22/22] scsi: hisi_sas: modify internal abort dev flow for v3 hw Date: Thu, 25 May 2017 20:05:11 +0800 Message-ID: <1495713911-80476-23-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495713911-80476-1-git-send-email-john.garry@huawei.com> References: <1495713911-80476-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.5926C14B.0138, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 21d01d17b2638b8704b89844527b25c2 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen There is a change for abort dev for v3 hw: add registers to configure unaborted iptt for a device, and then inform this to logic. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 2 ++ drivers/scsi/hisi_sas/hisi_sas_main.c | 15 +++++++++++++++ drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 2315102..c465aab 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -181,6 +181,8 @@ struct hisi_sas_hw { void (*free_device)(struct hisi_hba *hisi_hba, struct hisi_sas_device *dev); int (*get_wideport_bitmap)(struct hisi_hba *hisi_hba, int port_id); + void (*dereg_device)(struct hisi_hba *hisi_hba, + struct domain_device *device); int (*soft_reset)(struct hisi_hba *hisi_hba); int max_command_entries; int complete_hdr_size; diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index a6d0bf8..1803374 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -760,6 +760,13 @@ static void hisi_sas_release_tasks(struct hisi_hba *hisi_hba) } } +static void hisi_sas_dereg_device(struct hisi_hba *hisi_hba, + struct domain_device *device) +{ + if (hisi_hba->hw->dereg_device) + hisi_hba->hw->dereg_device(hisi_hba, device); +} + static void hisi_sas_dev_gone(struct domain_device *device) { struct hisi_sas_device *sas_dev = device->lldd_dev; @@ -773,6 +780,8 @@ static void hisi_sas_dev_gone(struct domain_device *device) hisi_sas_internal_task_abort(hisi_hba, device, HISI_SAS_INT_ABT_DEV, 0); + hisi_sas_dereg_device(hisi_hba, device); + hisi_hba->hw->free_device(hisi_hba, sas_dev); device->lldd_dev = NULL; memset(sas_dev, 0, sizeof(*sas_dev)); @@ -1104,6 +1113,7 @@ static int hisi_sas_abort_task(struct sas_task *task) if (task->dev->dev_type == SAS_SATA_DEV) { hisi_sas_internal_task_abort(hisi_hba, device, HISI_SAS_INT_ABT_DEV, 0); + hisi_sas_dereg_device(hisi_hba, device); rc = hisi_sas_softreset_ata_disk(device); } } else if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SMP) { @@ -1170,6 +1180,10 @@ static int hisi_sas_I_T_nexus_reset(struct domain_device *device) return TMF_RESP_FUNC_FAILED; sas_dev->dev_status = HISI_SAS_DEV_NORMAL; + hisi_sas_internal_task_abort(hisi_hba, device, + HISI_SAS_INT_ABT_DEV, 0); + hisi_sas_dereg_device(hisi_hba, device); + rc = hisi_sas_debug_I_T_nexus_reset(device); if (rc == TMF_RESP_FUNC_COMPLETE) { @@ -1197,6 +1211,7 @@ static int hisi_sas_lu_reset(struct domain_device *device, u8 *lun) HISI_SAS_INT_ABT_DEV, 0); if (rc == TMF_RESP_FUNC_FAILED) goto out; + hisi_sas_dereg_device(hisi_hba, device); phy = sas_get_local_phy(device); diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 4a6f5c7..c1db7bc 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -50,6 +50,10 @@ #define CFG_ABT_SET_QUERY_IPTT 0xd4 #define CFG_SET_ABORTED_IPTT_OFF 0 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) +#define CFG_SET_ABORTED_EN_OFF 12 +#define CFG_ABT_SET_IPTT_DONE 0xd8 +#define CFG_ABT_SET_IPTT_DONE_OFF 0 +#define HGC_IOMB_PROC1_STATUS 0x104 #define CFG_1US_TIMER_TRSH 0xcc #define HGC_LM_DFX_STATUS2 0x128 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0 @@ -637,6 +641,29 @@ static void free_device_v3_hw(struct hisi_hba *hisi_hba, } } +static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, + struct domain_device *device) +{ + struct hisi_sas_slot *slot, *slot2; + struct hisi_sas_device *sas_dev = device->lldd_dev; + u32 cfg_abt_set_query_iptt; + + cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, + CFG_ABT_SET_QUERY_IPTT); + list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { + cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; + cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | + (slot->idx << CFG_SET_ABORTED_IPTT_OFF); + hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, + cfg_abt_set_query_iptt); + } + cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); + hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, + cfg_abt_set_query_iptt); + hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, + 1 << CFG_ABT_SET_IPTT_DONE_OFF); +} + static int hw_init_v3_hw(struct hisi_hba *hisi_hba) { init_reg_v3_hw(hisi_hba); @@ -2180,6 +2207,7 @@ static void hisi_sas_v3_remove(struct pci_dev *pdev) .phy_disable = disable_phy_v3_hw, .phy_hard_reset = phy_hard_reset_v3_hw, .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, + .dereg_device = dereg_device_v3_hw, }; enum {