From patchwork Mon Sep 13 19:28:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 511160 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57C0AC433EF for ; Mon, 13 Sep 2021 19:28:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4241861103 for ; Mon, 13 Sep 2021 19:28:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243404AbhIMT3i (ORCPT ); Mon, 13 Sep 2021 15:29:38 -0400 Received: from mail-ot1-f42.google.com ([209.85.210.42]:33602 "EHLO mail-ot1-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242460AbhIMT3h (ORCPT ); Mon, 13 Sep 2021 15:29:37 -0400 Received: by mail-ot1-f42.google.com with SMTP id c42-20020a05683034aa00b0051f4b99c40cso14920011otu.0; Mon, 13 Sep 2021 12:28:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bo3Y3YQ371Z883tMU4VrZy4L5Q9VAxUq7LbWOjVoWos=; b=Vxk9k7iY6UFpiF5H1Shaq3aHPwyc6dvR0/5F8MAMHQWpqq9KvkoxPnlmwnCQTlbEsr vmgSxCYobQTbLzdLrzU4I9vHyWENMdrlTSEa/e/tXbtrHdXwE1CWhDQP6fUAOlEsU1iK LJGrWXFF6TPC8TTXNCjD4+zNbGclR9e0/y7qkQHaDJ0pD0ezRetzU+QNIrfbg+9qu8ve c3eXK+WZThUamTUdo2FZ5d21PZxF9Hfb0fZ+/wAXmGw9PxFxPOiLalfbgPI+4z54npJZ nmRrAt2Zkg65mxwhWQeFRGHYz/MWktj0eMZM4laqEhnBiKYatF2LU5gqcF8w2HPSAmti JvGA== X-Gm-Message-State: AOAM5333AJ2l5RjA1xekSo6izySCYFgM0cMD0RnrCUT7wp4KSOE9DfwC 1mV9WM6Dcqku91XR6sJhpw== X-Google-Smtp-Source: ABdhPJy6jaYywW1V07gad8tmv5Sw6LtKfCn4pRXceEdBmalCy8UAA3XdyeV0WbWobplmHwvk1MAUew== X-Received: by 2002:a9d:410:: with SMTP id 16mr11271688otc.83.1631561300488; Mon, 13 Sep 2021 12:28:20 -0700 (PDT) Received: from xps15.herring.priv (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.googlemail.com with ESMTPSA id m24sm1907838oie.50.2021.09.13.12.28.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 12:28:19 -0700 (PDT) From: Rob Herring To: Linus Walleij , Stephen Boyd , Pavel Machek Cc: Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-leds@vger.kernel.org Subject: [PATCH v2 1/8] dt-bindings: leds: Convert register-bit-led binding to DT schema Date: Mon, 13 Sep 2021 14:28:09 -0500 Message-Id: <20210913192816.1225025-2-robh@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210913192816.1225025-1-robh@kernel.org> References: <20210913192816.1225025-1-robh@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the register-bit-led binding to DT schema format. As the example just repeats nearly identical nodes, trim it down to a few nodes and use some documented values for 'linux,default-trigger'. Cc: Linus Walleij Cc: Pavel Machek Cc: linux-leds@vger.kernel.org Signed-off-by: Rob Herring --- v2: - Drop undocumented linux,default-trigger values --- .../bindings/leds/register-bit-led.txt | 94 ------------------- .../bindings/leds/register-bit-led.yaml | 78 +++++++++++++++ 2 files changed, 78 insertions(+), 94 deletions(-) delete mode 100644 Documentation/devicetree/bindings/leds/register-bit-led.txt create mode 100644 Documentation/devicetree/bindings/leds/register-bit-led.yaml diff --git a/Documentation/devicetree/bindings/leds/register-bit-led.txt b/Documentation/devicetree/bindings/leds/register-bit-led.txt deleted file mode 100644 index c7af6f70a97b..000000000000 --- a/Documentation/devicetree/bindings/leds/register-bit-led.txt +++ /dev/null @@ -1,94 +0,0 @@ -Device Tree Bindings for Register Bit LEDs - -Register bit leds are used with syscon multifunctional devices -where single bits in a certain register can turn on/off a -single LED. The register bit LEDs appear as children to the -syscon device, with the proper compatible string. For the -syscon bindings see: -Documentation/devicetree/bindings/mfd/syscon.yaml - -Each LED is represented as a sub-node of the syscon device. Each -node's name represents the name of the corresponding LED. - -LED sub-node properties: - -Required properties: -- compatible : must be "register-bit-led" -- offset : register offset to the register controlling this LED -- mask : bit mask for the bit controlling this LED in the register - typically 0x01, 0x02, 0x04 ... - -Optional properties: -- label : (optional) - see Documentation/devicetree/bindings/leds/common.txt -- linux,default-trigger : (optional) - see Documentation/devicetree/bindings/leds/common.txt -- default-state: (optional) The initial state of the LED - see Documentation/devicetree/bindings/leds/common.txt - -Example: - -syscon: syscon@10000000 { - compatible = "arm,realview-pb1176-syscon", "syscon"; - reg = <0x10000000 0x1000>; - - led@8.0 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@8.1 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@8.2 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@8.3 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - default-state = "off"; - }; - led@8.4 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - default-state = "off"; - }; - led@8.5 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - default-state = "off"; - }; - led@8.6 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@8.7 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/register-bit-led.yaml b/Documentation/devicetree/bindings/leds/register-bit-led.yaml new file mode 100644 index 000000000000..77ba0b824c15 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/register-bit-led.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/register-bit-led.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Device Tree Bindings for Register Bit LEDs + +maintainers: + - Linus Walleij + +description: |+ + Register bit leds are used with syscon multifunctional devices where single + bits in a certain register can turn on/off a single LED. The register bit LEDs + appear as children to the syscon device, with the proper compatible string. + For the syscon bindings see: + Documentation/devicetree/bindings/mfd/syscon.yaml + +allOf: + - $ref: /schemas/leds/common.yaml# + +properties: + compatible: + const: register-bit-led + + mask: + description: + bit mask for the bit controlling this LED in the register + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + [ 0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80, 0x100, 0x200, 0x400, 0x800, + 0x1000, 0x2000, 0x4000, 0x8000, 0x10000, 0x20000, 0x40000, 0x80000, + 0x100000, 0x200000, 0x400000, 0x800000, 0x1000000, 0x2000000, 0x4000000, + 0x8000000, 0x10000000, 0x20000000, 0x40000000, 0x80000000 ] + + offset: + description: + register offset to the register controlling this LED + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - mask + - offset + +unevaluatedProperties: false + +examples: + - | + + syscon@10000000 { + compatible = "arm,realview-pb1176-syscon", "syscon"; + reg = <0x10000000 0x1000>; + + led@8.0 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x01>; + label = "versatile:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + led@8.1 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x02>; + label = "versatile:1"; + default-state = "off"; + }; + led@8.2 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x04>; + label = "versatile:2"; + default-state = "off"; + }; + }; +... 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[66.90.148.213]) by smtp.googlemail.com with ESMTPSA id m24sm1907838oie.50.2021.09.13.12.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 12:28:21 -0700 (PDT) From: Rob Herring To: Linus Walleij , Stephen Boyd , Pavel Machek Cc: Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-leds@vger.kernel.org Subject: [PATCH v2 2/8] dt-bindings: leds: register-bit-led: Use 'reg' instead of 'offset' Date: Mon, 13 Sep 2021 14:28:10 -0500 Message-Id: <20210913192816.1225025-3-robh@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210913192816.1225025-1-robh@kernel.org> References: <20210913192816.1225025-1-robh@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 'reg' is the standard property for defining register banks/addresses. Add it to use for the register address and deprecate 'offset'. This also allows for using standard node names with unit-addresses. However, since it is quite possible to have multiple nodes at the same register address, allow for the unit-address to optionally have the bit offset. The unit-address format is '@[,]'. This matches the format recently added for nvmem binding which has the same issue. Cc: Pavel Machek Cc: Linus Walleij Cc: linux-leds@vger.kernel.org Signed-off-by: Rob Herring --- .../bindings/leds/register-bit-led.yaml | 25 ++++++++++++++++--- 1 file changed, 21 insertions(+), 4 deletions(-) -- 2.30.2 diff --git a/Documentation/devicetree/bindings/leds/register-bit-led.yaml b/Documentation/devicetree/bindings/leds/register-bit-led.yaml index 77ba0b824c15..79b8fc0f9d23 100644 --- a/Documentation/devicetree/bindings/leds/register-bit-led.yaml +++ b/Documentation/devicetree/bindings/leds/register-bit-led.yaml @@ -20,9 +20,19 @@ allOf: - $ref: /schemas/leds/common.yaml# properties: + $nodename: + description: + The unit-address is in the form of @, + pattern: '^led@[0-9a-f]+,[0-9a-f]{1,2}$' + compatible: const: register-bit-led + reg: + description: + The register address and size + maxItems: 1 + mask: description: bit mask for the bit controlling this LED in the register @@ -37,11 +47,12 @@ properties: description: register offset to the register controlling this LED $ref: /schemas/types.yaml#/definitions/uint32 + deprecated: true required: - compatible - mask - - offset + - reg unevaluatedProperties: false @@ -51,24 +62,30 @@ examples: syscon@10000000 { compatible = "arm,realview-pb1176-syscon", "syscon"; reg = <0x10000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000000 0x1000>; - led@8.0 { + led@8,0 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x01>; label = "versatile:0"; linux,default-trigger = "heartbeat"; default-state = "on"; }; - led@8.1 { + led@8,1 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x02>; label = "versatile:1"; default-state = "off"; }; - led@8.2 { + led@8,2 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x04>; label = "versatile:2"; From patchwork Mon Sep 13 19:28:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 509889 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC281C4332F for ; Mon, 13 Sep 2021 19:28:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C0B8761106 for ; Mon, 13 Sep 2021 19:28:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345319AbhIMT3k (ORCPT ); Mon, 13 Sep 2021 15:29:40 -0400 Received: from mail-ot1-f51.google.com ([209.85.210.51]:33616 "EHLO mail-ot1-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242654AbhIMT3j (ORCPT ); Mon, 13 Sep 2021 15:29:39 -0400 Received: by mail-ot1-f51.google.com with SMTP id c42-20020a05683034aa00b0051f4b99c40cso14920184otu.0; Mon, 13 Sep 2021 12:28:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9BBmBTBD/+iBwMGuU2DXqDGCFrO8u6bMOR8Z4+lnQAM=; b=gEhwHwRGwgiYY1oGqfPZvqT8cK3myKdwQlmjZ9czAYtZcnWdt8UhIZsLPXOK3RW9mm IQf7aJzwfHsscZ0ypbkFI9lPz3jFQIo6inm8+T1K3jZZGBCkeMhB4S98N9ykQYcuFmqt Smcnu6zIvgamZz0UtglFUbGdlkSjpNSUuYa3d0K/BfWrO1kokFMULSMRW6rJp7I/+rjn eWneghx/flmkuCw8W24gabeYWJJkX7a+Q12IZJDNiuCTCffIRT4ZNm1cb3oKSFQklXW7 usMoVEtQAR+QJyHoJULuLv/j+1R46SeDtZgScrmVa4KvAf5EoY5eshUq3UgeJGQ7Lfzh wmKA== X-Gm-Message-State: AOAM533hVqPH+sjMjaJ71SDlfu6frYO8HViNNAIeeGXTqFSpKGPjBq1x UrQGindqrw/rLu0fgRl08w== X-Google-Smtp-Source: ABdhPJwNuV74wCE+mYLB952ZYFLvACBXFmA+SnALVyiBkwoiZk8W4pI+AwyMyZErj9nIyrrw86d6Ag== X-Received: by 2002:a05:6830:349c:: with SMTP id c28mr11349403otu.35.1631561302950; Mon, 13 Sep 2021 12:28:22 -0700 (PDT) Received: from xps15.herring.priv (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.googlemail.com with ESMTPSA id m24sm1907838oie.50.2021.09.13.12.28.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 12:28:22 -0700 (PDT) From: Rob Herring To: Linus Walleij , Stephen Boyd , Pavel Machek Cc: Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-leds@vger.kernel.org Subject: [PATCH v2 3/8] leds: syscon: Support 'reg' in addition to 'offset' for register address Date: Mon, 13 Sep 2021 14:28:11 -0500 Message-Id: <20210913192816.1225025-4-robh@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210913192816.1225025-1-robh@kernel.org> References: <20210913192816.1225025-1-robh@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The register-bit-led binding now also supports 'reg' in addition to 'offset' for the register address. Add support to the driver to get the address from 'reg'. Cc: Linus Walleij Cc: Pavel Machek Cc: linux-leds@vger.kernel.org Signed-off-by: Rob Herring --- drivers/leds/leds-syscon.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/leds/leds-syscon.c b/drivers/leds/leds-syscon.c index 7eddb8ecb44e..44e79cdf5c39 100644 --- a/drivers/leds/leds-syscon.c +++ b/drivers/leds/leds-syscon.c @@ -81,7 +81,8 @@ static int syscon_led_probe(struct platform_device *pdev) sled->map = map; - if (of_property_read_u32(np, "offset", &sled->offset)) + if (of_property_read_u32(np, "reg", &sled->offset) && + of_property_read_u32(np, "offset", &sled->offset)) return -EINVAL; if (of_property_read_u32(np, "mask", &sled->mask)) return -EINVAL; From patchwork Mon Sep 13 19:28:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 509834 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp851237jao; Mon, 13 Sep 2021 12:28:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzCPuW+tE5ugr48ItMLASmOgNPy99XiQd/4iLHm9TOAf2UN5GT3OfuQhlrG1vh3Uq2hUDlP X-Received: by 2002:a92:c5c9:: with SMTP id s9mr9459377ilt.56.1631561308391; Mon, 13 Sep 2021 12:28:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631561308; cv=none; d=google.com; s=arc-20160816; b=sWDdIOUphSbFtuOYjamFSRSubeH4z5ItEl5dEEpTVWsC0vbYxmev+i8VTvqZt6Ze86 0MvOHLBomphmRNKCRrFsXiNgNWlrZIOs7ZPSokqOiwMzpUkJkmLMtb+TdFURyzE7advt lwyoZ084GsyEYx6eu+zjrdI40YP9xnUYli6bHEb0eBoagIuSfTNzDVswEXj+gIsKCevh CuCNl/uvrDZrnjSePcUlx+hqobR6Gd5gBdi1h77kPVkkLXs+XLyBa/Emc2PiPnVyOTMs G3HhN/NXrvZynn5DZkcxvp2T68zV2fFmLAV6Yj8cfK7wPvhRfA29uZqqK1PhfMbw7/Pj 9wuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=zgiY/jAX2so3Eo3P0Fr/TYfuN0OCzOoGgLVFkTmAlds=; b=R26xoFVRUMBp3UhrPv8N5uxrzq3Cinwj2PoxQ4zwq2bjGvBh8fWlc9CGsAlqshB404 PJgSYpjOS++kJjKVXQd+oy8PW5dGgTQ3k0ZHAdesSRrmvr7ir5Icd0p6v4D2OkQCmr9n 9mG7ZmM6d0tXs5QKny6hdfUk3f598wHXltTZ+ks5nkyQVAjtnGQx8sKxK5S8J1wBkUJ4 MLPZlZlCyB+NPhLA9DxRWVLnLfWvVb2DWiUv7pWAYFC9XcQTKjixX2xtafmOC/BQGTHT /anBtUF213mPj9nqcAk+BAe3BhoKnYBj3UYbZMA/tVNfXE35sCrB9SyK3acwmKEcHhvY yi1w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[66.90.148.213]) by smtp.googlemail.com with ESMTPSA id m24sm1907838oie.50.2021.09.13.12.28.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 12:28:23 -0700 (PDT) From: Rob Herring To: Linus Walleij , Stephen Boyd , Pavel Machek Cc: Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-leds@vger.kernel.org, Michael Turquette Subject: [PATCH v2 4/8] dt-bindings: clock: arm, syscon-icst: Use 'reg' instead of 'vco-offset' for VCO register address Date: Mon, 13 Sep 2021 14:28:12 -0500 Message-Id: <20210913192816.1225025-5-robh@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210913192816.1225025-1-robh@kernel.org> References: <20210913192816.1225025-1-robh@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 'reg' is the standard property for defining register banks/addresses. Add it to use for the VCO register address and deprecate 'vco-offset'. This will also allow for using standard node names with unit-addresses. Cc: Linus Walleij Cc: Stephen Boyd Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org Cc: Michael Turquette Signed-off-by: Rob Herring --- v2: - Fix 'deprecated' --- Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml | 5 +++++ 1 file changed, 5 insertions(+) -- 2.30.2 Reviewed-by: Stephen Boyd diff --git a/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml b/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml index 118c5543e037..90eadf6869b2 100644 --- a/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml +++ b/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml @@ -69,6 +69,10 @@ properties: - arm,impd1-vco1 - arm,impd1-vco2 + reg: + maxItems: 1 + description: The VCO register + clocks: description: Parent clock for the ICST VCO maxItems: 1 @@ -83,6 +87,7 @@ properties: vco-offset: $ref: '/schemas/types.yaml#/definitions/uint32' description: Offset to the VCO register for the oscillator + deprecated: true required: - "#clock-cells" From patchwork Mon Sep 13 19:28:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 511158 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DCF0C433F5 for ; Mon, 13 Sep 2021 19:28:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 18D25610FE for ; Mon, 13 Sep 2021 19:28:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346423AbhIMT3o (ORCPT ); Mon, 13 Sep 2021 15:29:44 -0400 Received: from mail-oi1-f175.google.com ([209.85.167.175]:34504 "EHLO mail-oi1-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242460AbhIMT3m (ORCPT ); Mon, 13 Sep 2021 15:29:42 -0400 Received: by mail-oi1-f175.google.com with SMTP id p2so15560670oif.1; Mon, 13 Sep 2021 12:28:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S09DONJ4lcwRKCzXlF4Hu+KGIQds8gxD/iFwoouakjk=; b=SwRGmBL8x3XGgcxo0tnnQBmBKLlPnZte4RFxcW9bj7+/RebcQfjsLBcIpiLewm2g3Q ihnXdQBZiJsTS0/UJYvPz87Kdg2eOB+SEAzqI2nVCvU/uplANlKgBGO+lK2r3eWtyOyr q62aiumqm1MhBVYbeajKMbgsZEi2dtarR7jdxlIRKZK9Y5hiaOvnjYkqwVj8yELOs1F8 X1MBzQY42mXLnsEbv9FXpVKky8jT83os4xmLsMKNjG2uvAxlOkTt21WYwPn9IfEYrcqe gautZ+lVEu7kWywg0WGI8qvJYu0RVfhqQKl1kudWc0mS8y9zrq8EMfNXmrpAAWLazp/7 310Q== X-Gm-Message-State: AOAM531QKMf3duZ7vSb9/m6i2+2mXZ6AtQusTkzRanqmanmiu6CyR7Bz jpy66XBhbo1sDD/CF5hfjw== X-Google-Smtp-Source: ABdhPJxDqvjVXbnm3PAJ2C419RCGcLNFWtXAKZoTaaa1/P86XWuVMFHQFon2e3+PMaqQ0PbZ6PLHPA== X-Received: by 2002:aca:4b85:: with SMTP id y127mr9060394oia.169.1631561306234; Mon, 13 Sep 2021 12:28:26 -0700 (PDT) Received: from xps15.herring.priv (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.googlemail.com with ESMTPSA id m24sm1907838oie.50.2021.09.13.12.28.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 12:28:24 -0700 (PDT) From: Rob Herring To: Linus Walleij , Stephen Boyd , Pavel Machek Cc: Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-leds@vger.kernel.org Subject: [PATCH v2 5/8] clk: versatile: clk-icst: Support 'reg' in addition to 'vco-offset' for register address Date: Mon, 13 Sep 2021 14:28:13 -0500 Message-Id: <20210913192816.1225025-6-robh@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210913192816.1225025-1-robh@kernel.org> References: <20210913192816.1225025-1-robh@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ICST binding now also supports 'reg' in addition to 'vco-offset' for the VCO register address. Add support to the driver to get the VCO address from 'reg'. Cc: Linus Walleij Cc: Stephen Boyd Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org Signed-off-by: Rob Herring --- drivers/clk/versatile/clk-icst.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/versatile/clk-icst.c b/drivers/clk/versatile/clk-icst.c index fdd6aa3cb1fc..77fd0ecaf155 100644 --- a/drivers/clk/versatile/clk-icst.c +++ b/drivers/clk/versatile/clk-icst.c @@ -501,7 +501,8 @@ static void __init of_syscon_icst_setup(struct device_node *np) return; } - if (of_property_read_u32(np, "vco-offset", &icst_desc.vco_offset)) { + if (of_property_read_u32(np, "reg", &icst_desc.vco_offset) && + of_property_read_u32(np, "vco-offset", &icst_desc.vco_offset)) { pr_err("no VCO register offset for ICST clock\n"); return; } From patchwork Mon Sep 13 19:28:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 509888 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CD67C4167B for ; Mon, 13 Sep 2021 19:28:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 75D1B61108 for ; Mon, 13 Sep 2021 19:28:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347375AbhIMT3p (ORCPT ); Mon, 13 Sep 2021 15:29:45 -0400 Received: from mail-oi1-f174.google.com ([209.85.167.174]:40524 "EHLO mail-oi1-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345862AbhIMT3o (ORCPT ); Mon, 13 Sep 2021 15:29:44 -0400 Received: by mail-oi1-f174.google.com with SMTP id h133so15525110oib.7; Mon, 13 Sep 2021 12:28:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cqIeqU65iovt1/KVYn/OKZzsq19Zz/ArZBTPcmVHg2A=; b=Zhs6mODZRKpOiZ8ixXFybJdLt24iQRFDZZgWd63FoX7yjpps5QI3UJ1b4UnWFQHK8m c39rR/in5S+hLFb4xEf29neXf2FkPrfTA4W74a7fg12b3zMS1hdxodwvKsFwmKDFA3W2 1a6uHMJ9/ctf77minD7pa1CUyt/CNRP0zj/EvdxCoR82Ydru31duPx1fU6W2AvGgYO0L tIJicx0VUGjbCLGKe1eRsRYpWInI9YHoe+D2L239euZwwrJc19MinHg8Qqjsgz/GUdpH iedDN3mB5tQSRbN7V55Rn5/Z/udAH4JcheK/7Cy3Nw4yZ7cybMLGZ9yj9gIAe0XGUlwo B0Gw== X-Gm-Message-State: AOAM533/6O6zZVN6hESIR78nYp8oYWmWD1EFm3SS6nzDYzrFprlHun+s EoNqKPFo+upML2QeQHU3Vg== X-Google-Smtp-Source: ABdhPJxxMUFZr8rTTazRvS3urBG1WavS0XnJcYlP4pL7Z7c0ieM/UZs96dJlrUtLSwb6c5AANKAQZw== X-Received: by 2002:aca:3bc2:: with SMTP id i185mr8636420oia.67.1631561307489; Mon, 13 Sep 2021 12:28:27 -0700 (PDT) Received: from xps15.herring.priv (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.googlemail.com with ESMTPSA id m24sm1907838oie.50.2021.09.13.12.28.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 12:28:26 -0700 (PDT) From: Rob Herring To: Linus Walleij , Stephen Boyd , Pavel Machek Cc: Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-leds@vger.kernel.org Subject: [PATCH v2 6/8] ARM: dts: arm: Update register-bit-led nodes 'reg' and node names Date: Mon, 13 Sep 2021 14:28:14 -0500 Message-Id: <20210913192816.1225025-7-robh@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210913192816.1225025-1-robh@kernel.org> References: <20210913192816.1225025-1-robh@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a 'reg' entry for register-bit-led nodes on the Arm Ltd platforms. The 'reg' entry is the LED control register address. With this, the node name can be updated to use a generic node name, 'led', and a unit-address. Cc: Linus Walleij Cc: Liviu Dudau Cc: Sudeep Holla Cc: Lorenzo Pieralisi Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- arch/arm/boot/dts/arm-realview-eb.dtsi | 27 +++++++++++++------ arch/arm/boot/dts/arm-realview-pb1176.dts | 27 +++++++++++++------ arch/arm/boot/dts/arm-realview-pb11mp.dts | 27 +++++++++++++------ arch/arm/boot/dts/arm-realview-pbx.dtsi | 27 +++++++++++++------ arch/arm/boot/dts/integrator.dtsi | 23 +++++++++++----- arch/arm/boot/dts/mps2.dtsi | 10 +++++-- arch/arm/boot/dts/versatile-ab-ib2.dts | 6 ++++- arch/arm/boot/dts/versatile-ab.dts | 27 +++++++++++++------ arch/arm64/boot/dts/arm/juno-motherboard.dtsi | 27 +++++++++++++------ 9 files changed, 144 insertions(+), 57 deletions(-) diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi index 04e8a27ba1eb..56441ef08a55 100644 --- a/arch/arm/boot/dts/arm-realview-eb.dtsi +++ b/arch/arm/boot/dts/arm-realview-eb.dtsi @@ -198,61 +198,72 @@ fpga { syscon: syscon@10000000 { compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd"; reg = <0x10000000 0x1000>; + ranges = <0x0 0x10000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; - led@08.0 { + led@8,0 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x01>; label = "versatile:0"; linux,default-trigger = "heartbeat"; default-state = "on"; }; - led@08.1 { + led@8,1 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x02>; label = "versatile:1"; linux,default-trigger = "mmc0"; default-state = "off"; }; - led@08.2 { + led@8,2 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x04>; label = "versatile:2"; linux,default-trigger = "cpu0"; default-state = "off"; }; - led@08.3 { + led@8,3 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x08>; label = "versatile:3"; default-state = "off"; }; - led@08.4 { + led@8,4 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x10>; label = "versatile:4"; default-state = "off"; }; - led@08.5 { + led@8,5 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x20>; label = "versatile:5"; default-state = "off"; }; - led@08.6 { + led@8,6 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x40>; label = "versatile:6"; default-state = "off"; }; - led@08.7 { + led@8,7 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x80>; label = "versatile:7"; diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts index 366687fb1ee3..df71ee27294d 100644 --- a/arch/arm/boot/dts/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm-realview-pb1176.dts @@ -216,61 +216,72 @@ soc { syscon: syscon@10000000 { compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd"; reg = <0x10000000 0x1000>; + ranges = <0x0 0x10000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; - led@08.0 { + led@8,0 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x01>; label = "versatile:0"; linux,default-trigger = "heartbeat"; default-state = "on"; }; - led@08.1 { + led@8,1 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x02>; label = "versatile:1"; linux,default-trigger = "mmc0"; default-state = "off"; }; - led@08.2 { + led@8,2 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x04>; label = "versatile:2"; linux,default-trigger = "cpu0"; default-state = "off"; }; - led@08.3 { + led@8,3 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x08>; label = "versatile:3"; default-state = "off"; }; - led@08.4 { + led@8,4 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x10>; label = "versatile:4"; default-state = "off"; }; - led@08.5 { + led@8,5 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x20>; label = "versatile:5"; default-state = "off"; }; - led@08.6 { + led@8,6 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x40>; label = "versatile:6"; default-state = "off"; }; - led@08.7 { + led@8,7 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x80>; label = "versatile:7"; diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts index 228a51a38f95..54d4cbd10bdf 100644 --- a/arch/arm/boot/dts/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts @@ -303,64 +303,75 @@ soc { pb11mp_syscon: syscon@10000000 { compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd"; reg = <0x10000000 0x1000>; + ranges = <0x0 0x10000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; - led@08.0 { + led@8,0 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x01>; label = "versatile:0"; linux,default-trigger = "heartbeat"; default-state = "on"; }; - led@08.1 { + led@8,1 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x02>; label = "versatile:1"; linux,default-trigger = "mmc0"; default-state = "off"; }; - led@08.2 { + led@8,2 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x04>; label = "versatile:2"; linux,default-trigger = "cpu0"; default-state = "off"; }; - led@08.3 { + led@8,3 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x08>; label = "versatile:3"; linux,default-trigger = "cpu1"; default-state = "off"; }; - led@08.4 { + led@8,4 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x10>; label = "versatile:4"; linux,default-trigger = "cpu2"; default-state = "off"; }; - led@08.5 { + led@8,5 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x20>; label = "versatile:5"; linux,default-trigger = "cpu3"; default-state = "off"; }; - led@08.6 { + led@8,6 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x40>; label = "versatile:6"; default-state = "off"; }; - led@08.7 { + led@8,7 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x80>; label = "versatile:7"; diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi index ccf6f756b6ed..9366fecc699b 100644 --- a/arch/arm/boot/dts/arm-realview-pbx.dtsi +++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi @@ -220,61 +220,72 @@ soc: soc { syscon: syscon@10000000 { compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd"; reg = <0x10000000 0x1000>; + ranges = <0x0 0x10000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; - led@08.0 { + led@8,0 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x01>; label = "versatile:0"; linux,default-trigger = "heartbeat"; default-state = "on"; }; - led@08.1 { + led@8,1 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x02>; label = "versatile:1"; linux,default-trigger = "mmc0"; default-state = "off"; }; - led@08.2 { + led@8,2 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x04>; label = "versatile:2"; linux,default-trigger = "cpu0"; default-state = "off"; }; - led@08.3 { + led@8,3 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x08>; label = "versatile:3"; default-state = "off"; }; - led@08.4 { + led@8,4 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x10>; label = "versatile:4"; default-state = "off"; }; - led@08.5 { + led@8,5 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x20>; label = "versatile:5"; default-state = "off"; }; - led@08.6 { + led@8,6 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x40>; label = "versatile:6"; default-state = "off"; }; - led@08.7 { + led@8,7 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x80>; label = "versatile:7"; diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi index 602f74d2c758..ad868cfebc94 100644 --- a/arch/arm/boot/dts/integrator.dtsi +++ b/arch/arm/boot/dts/integrator.dtsi @@ -15,10 +15,14 @@ memory { core-module@10000000 { compatible = "arm,core-module-integrator", "syscon", "simple-mfd"; reg = <0x10000000 0x200>; + ranges = <0x0 0x10000000 0x200>; + #address-cells = <1>; + #size-cells = <1>; /* Use core module LED to indicate CPU load */ - led@c.0 { + led@c,0 { compatible = "register-bit-led"; + reg = <0x0c 0x04>; offset = <0x0c>; mask = <0x01>; label = "integrator:core_module"; @@ -104,35 +108,42 @@ kmi@19000000 { interrupts = <4>; }; - syscon { + syscon@1a000000 { /* Debug registers mapped as syscon */ compatible = "syscon", "simple-mfd"; reg = <0x1a000000 0x10>; + ranges = <0x0 0x1a000000 0x10>; + #address-cells = <1>; + #size-cells = <1>; - led@4.0 { + led@4,0 { compatible = "register-bit-led"; + reg = <0x04 0x04>; offset = <0x04>; mask = <0x01>; label = "integrator:green0"; linux,default-trigger = "heartbeat"; default-state = "on"; }; - led@4.1 { + led@4,1 { compatible = "register-bit-led"; + reg = <0x04 0x04>; offset = <0x04>; mask = <0x02>; label = "integrator:yellow"; default-state = "off"; }; - led@4.2 { + led@4,2 { compatible = "register-bit-led"; + reg = <0x04 0x04>; offset = <0x04>; mask = <0x04>; label = "integrator:red"; default-state = "off"; }; - led@4.3 { + led@4,3 { compatible = "register-bit-led"; + reg = <0x04 0x04>; offset = <0x04>; mask = <0x08>; label = "integrator:green1"; diff --git a/arch/arm/boot/dts/mps2.dtsi b/arch/arm/boot/dts/mps2.dtsi index 37f5023f529c..b99577d411b1 100644 --- a/arch/arm/boot/dts/mps2.dtsi +++ b/arch/arm/boot/dts/mps2.dtsi @@ -216,8 +216,13 @@ fpgaio@8000 { compatible = "syscon", "simple-mfd"; reg = <0x8000 0x10>; - led0 { + ranges = <0x0 0x8000 0x10>; + #address-cells = <1>; + #size-cells = <1>; + + led@0,0 { compatible = "register-bit-led"; + reg = <0x00 0x04>; offset = <0x0>; mask = <0x01>; label = "userled:0"; @@ -225,8 +230,9 @@ led0 { default-state = "on"; }; - led1 { + led@0,1 { compatible = "register-bit-led"; + reg = <0x00 0x04>; offset = <0x0>; mask = <0x02>; label = "userled:1"; diff --git a/arch/arm/boot/dts/versatile-ab-ib2.dts b/arch/arm/boot/dts/versatile-ab-ib2.dts index c577ff4bb4be..7ebb0dfd0467 100644 --- a/arch/arm/boot/dts/versatile-ab-ib2.dts +++ b/arch/arm/boot/dts/versatile-ab-ib2.dts @@ -13,9 +13,13 @@ / { syscon@27000000 { compatible = "arm,versatile-ib2-syscon", "syscon", "simple-mfd"; reg = <0x27000000 0x4>; + ranges = <0x0 0x27000000 0x4>; + #address-cells = <1>; + #size-cells = <1>; - led@00.4 { + led@0,4 { compatible = "register-bit-led"; + reg = <0x00 0x04>; offset = <0x00>; mask = <0x10>; label = "versatile-ib2:0"; diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts index 151c0220047d..79f7cc241282 100644 --- a/arch/arm/boot/dts/versatile-ab.dts +++ b/arch/arm/boot/dts/versatile-ab.dts @@ -70,61 +70,72 @@ vga_con_in: endpoint { core-module@10000000 { compatible = "arm,core-module-versatile", "syscon", "simple-mfd"; reg = <0x10000000 0x200>; + ranges = <0x0 0x10000000 0x200>; + #address-cells = <1>; + #size-cells = <1>; - led@08.0 { + led@8,0 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x01>; label = "versatile:0"; linux,default-trigger = "heartbeat"; default-state = "on"; }; - led@08.1 { + led@8,1 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x02>; label = "versatile:1"; linux,default-trigger = "mmc0"; default-state = "off"; }; - led@08.2 { + led@8,2 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x04>; label = "versatile:2"; linux,default-trigger = "cpu0"; default-state = "off"; }; - led@08.3 { + led@8,3 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x08>; label = "versatile:3"; default-state = "off"; }; - led@08.4 { + led@8,4 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x10>; label = "versatile:4"; default-state = "off"; }; - led@08.5 { + led@8,5 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x20>; label = "versatile:5"; default-state = "off"; }; - led@08.6 { + led@8,6 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x40>; label = "versatile:6"; default-state = "off"; }; - led@08.7 { + led@8,7 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x80>; label = "versatile:7"; diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi index 40d95c58b55e..f7afb8faf5de 100644 --- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi @@ -153,64 +153,75 @@ v2m_sysctl: sysctl@20000 { apbregs@10000 { compatible = "syscon", "simple-mfd"; reg = <0x010000 0x1000>; + ranges = <0x0 0x10000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; - led0 { + led@8,0 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x01>; label = "vexpress:0"; linux,default-trigger = "heartbeat"; default-state = "on"; }; - led1 { + led@8,1 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x02>; label = "vexpress:1"; linux,default-trigger = "mmc0"; default-state = "off"; }; - led2 { + led@8,2 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x04>; label = "vexpress:2"; linux,default-trigger = "cpu0"; default-state = "off"; }; - led3 { + led@8,3 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x08>; label = "vexpress:3"; linux,default-trigger = "cpu1"; default-state = "off"; }; - led4 { + led@8,4 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x10>; label = "vexpress:4"; linux,default-trigger = "cpu2"; default-state = "off"; }; - led5 { + led@8,5 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x20>; label = "vexpress:5"; linux,default-trigger = "cpu3"; default-state = "off"; }; - led6 { + led@8,6 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x40>; label = "vexpress:6"; default-state = "off"; }; - led7 { + led@8,7 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x80>; label = "vexpress:7"; From patchwork Mon Sep 13 19:28:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 509837 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp851326jao; 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[66.90.148.213]) by smtp.googlemail.com with ESMTPSA id m24sm1907838oie.50.2021.09.13.12.28.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 12:28:28 -0700 (PDT) From: Rob Herring To: Linus Walleij , Stephen Boyd , Pavel Machek Cc: Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-leds@vger.kernel.org Subject: [PATCH v2 7/8] ARM: dts: arm: Update ICST clock nodes 'reg' and node names Date: Mon, 13 Sep 2021 14:28:15 -0500 Message-Id: <20210913192816.1225025-8-robh@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210913192816.1225025-1-robh@kernel.org> References: <20210913192816.1225025-1-robh@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a 'reg' entry for ICST clock nodes on the Arm Ltd platforms. The 'reg' entry is the VCO register address. With this, the node name can be updated to use a generic node name, 'clock-controller', and a unit-address. Cc: Linus Walleij Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- arch/arm/boot/dts/arm-realview-eb.dtsi | 15 ++++++++++----- arch/arm/boot/dts/arm-realview-pb1176.dts | 15 ++++++++++----- arch/arm/boot/dts/arm-realview-pb11mp.dts | 21 ++++++++++++++------- arch/arm/boot/dts/arm-realview-pbx.dtsi | 15 ++++++++++----- arch/arm/boot/dts/integratorap-im-pd1.dts | 9 +++++++-- arch/arm/boot/dts/integratorap.dts | 15 +++++++++++---- arch/arm/boot/dts/integratorcp.dts | 9 ++++++--- 7 files changed, 68 insertions(+), 31 deletions(-) -- 2.30.2 diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi index 56441ef08a55..2dfb32bf9d48 100644 --- a/arch/arm/boot/dts/arm-realview-eb.dtsi +++ b/arch/arm/boot/dts/arm-realview-eb.dtsi @@ -269,36 +269,41 @@ led@8,7 { label = "versatile:7"; default-state = "off"; }; - oscclk0: osc0@0c { + oscclk0: clock-controller@c { compatible = "arm,syscon-icst307"; + reg = <0x0c 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x0C>; clocks = <&xtal24mhz>; }; - oscclk1: osc1@10 { + oscclk1: clock-controller@10 { compatible = "arm,syscon-icst307"; + reg = <0x10 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x10>; clocks = <&xtal24mhz>; }; - oscclk2: osc2@14 { + oscclk2: clock-controller@14 { compatible = "arm,syscon-icst307"; + reg = <0x14 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x14>; clocks = <&xtal24mhz>; }; - oscclk3: osc3@18 { + oscclk3: clock-controller@18 { compatible = "arm,syscon-icst307"; + reg = <0x18 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x18>; clocks = <&xtal24mhz>; }; - oscclk4: osc4@1c { + oscclk4: clock-controller@1c { compatible = "arm,syscon-icst307"; + reg = <0x1c 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x1c>; diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts index df71ee27294d..06b8723b09eb 100644 --- a/arch/arm/boot/dts/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm-realview-pb1176.dts @@ -287,36 +287,41 @@ led@8,7 { label = "versatile:7"; default-state = "off"; }; - oscclk0: osc0@0c { + oscclk0: clock-controller@c { compatible = "arm,syscon-icst307"; + reg = <0x0c 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x0C>; clocks = <&xtal24mhz>; }; - oscclk1: osc1@10 { + oscclk1: clock-controller@10 { compatible = "arm,syscon-icst307"; + reg = <0x10 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x10>; clocks = <&xtal24mhz>; }; - oscclk2: osc2@14 { + oscclk2: clock-controller@14 { compatible = "arm,syscon-icst307"; + reg = <0x14 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x14>; clocks = <&xtal24mhz>; }; - oscclk3: osc3@18 { + oscclk3: clock-controller@18 { compatible = "arm,syscon-icst307"; + reg = <0x18 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x18>; clocks = <&xtal24mhz>; }; - oscclk4: osc4@1c { + oscclk4: clock-controller@1c { compatible = "arm,syscon-icst307"; + reg = <0x1c 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x1c>; diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts index 54d4cbd10bdf..295aef448123 100644 --- a/arch/arm/boot/dts/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts @@ -378,50 +378,57 @@ led@8,7 { default-state = "off"; }; - oscclk0: osc0@0c { + oscclk0: clock-controller@c { compatible = "arm,syscon-icst307"; + reg = <0x0c 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x0C>; clocks = <&xtal24mhz>; }; - oscclk1: osc1@10 { + oscclk1: clock-controller@10 { compatible = "arm,syscon-icst307"; + reg = <0x10 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x10>; clocks = <&xtal24mhz>; }; - oscclk2: osc2@14 { + oscclk2: clock-controller@14 { compatible = "arm,syscon-icst307"; + reg = <0x14 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x14>; clocks = <&xtal24mhz>; }; - oscclk3: osc3@18 { + oscclk3: clock-controller@18 { compatible = "arm,syscon-icst307"; + reg = <0x18 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x18>; clocks = <&xtal24mhz>; }; - oscclk4: osc4@1c { + oscclk4: clock-controller@1c { compatible = "arm,syscon-icst307"; + reg = <0x1c 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x1c>; clocks = <&xtal24mhz>; }; - oscclk5: osc5@d4 { + oscclk5: clock-controller@d4 { compatible = "arm,syscon-icst307"; + reg = <0xd4 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0xd4>; clocks = <&xtal24mhz>; }; - oscclk6: osc6@d8 { + oscclk6: clock-controller@d8 { compatible = "arm,syscon-icst307"; + reg = <0xd8 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0xd8>; diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi index 9366fecc699b..6f61f968d689 100644 --- a/arch/arm/boot/dts/arm-realview-pbx.dtsi +++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi @@ -291,36 +291,41 @@ led@8,7 { label = "versatile:7"; default-state = "off"; }; - oscclk0: osc0@0c { + oscclk0: clock-controller@c { compatible = "arm,syscon-icst307"; + reg = <0x0c 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x0C>; clocks = <&xtal24mhz>; }; - oscclk1: osc1@10 { + oscclk1: clock-controller@10 { compatible = "arm,syscon-icst307"; + reg = <0x10 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x10>; clocks = <&xtal24mhz>; }; - oscclk2: osc2@14 { + oscclk2: clock-controller@14 { compatible = "arm,syscon-icst307"; + reg = <0x14 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x14>; clocks = <&xtal24mhz>; }; - oscclk3: osc3@18 { + oscclk3: clock-controller@18 { compatible = "arm,syscon-icst307"; + reg = <0x18 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x18>; clocks = <&xtal24mhz>; }; - oscclk4: osc4@1c { + oscclk4: clock-controller@1c { compatible = "arm,syscon-icst307"; + reg = <0x1c 0x04>; #clock-cells = <0>; lock-offset = <0x20>; vco-offset = <0x1c>; diff --git a/arch/arm/boot/dts/integratorap-im-pd1.dts b/arch/arm/boot/dts/integratorap-im-pd1.dts index 0614f82b808e..d47bfb66d069 100644 --- a/arch/arm/boot/dts/integratorap-im-pd1.dts +++ b/arch/arm/boot/dts/integratorap-im-pd1.dts @@ -28,9 +28,13 @@ &lm0 { syscon@0 { compatible = "arm,im-pd1-syscon", "syscon"; reg = <0x00000000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; - vco1: vco1-clock { + vco1: clock-controller@0 { compatible = "arm,impd1-vco1"; + reg = <0x00 0x04>; #clock-cells = <0>; lock-offset = <0x08>; vco-offset = <0x00>; @@ -38,8 +42,9 @@ vco1: vco1-clock { clock-output-names = "IM-PD1-VCO1"; }; - vco2: vco2-clock { + vco2: clock-controller@4 { compatible = "arm,impd1-vco2"; + reg = <0x04 0x04>; #clock-cells = <0>; lock-offset = <0x08>; vco-offset = <0x04>; diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index 67d1f9b24a52..9b652cc27b14 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -88,8 +88,9 @@ cm24mhz: cm24mhz@24M { }; /* Oscillator on the core module, clocks the CPU core */ - cmosc: cmosc@24M { + cmosc: clock-controller@8 { compatible = "arm,syscon-icst525-integratorap-cm"; + reg = <0x08 0x04>; #clock-cells = <0>; lock-offset = <0x14>; vco-offset = <0x08>; @@ -97,8 +98,9 @@ cmosc: cmosc@24M { }; /* Auxilary oscillator on the core module, 32.369MHz at boot */ - auxosc: auxosc@24M { + auxosc: clock-controller@1c { compatible = "arm,syscon-icst525"; + reg = <0x1c 0x04>; #clock-cells = <0>; lock-offset = <0x14>; vco-offset = <0x1c>; @@ -109,13 +111,17 @@ auxosc: auxosc@24M { syscon { compatible = "arm,integrator-ap-syscon", "syscon"; reg = <0x11000000 0x100>; + ranges = <0x0 0x11000000 0x100>; + #size-cells = <1>; + #address-cells = <1>; /* * SYSCLK clocks PCIv3 bridge, system controller and the * logic modules. */ - sysclk: apsys@24M { + sysclk: clock-controller@4 { compatible = "arm,syscon-icst525-integratorap-sys"; + reg = <0x04 0x04>; #clock-cells = <0>; lock-offset = <0x1c>; vco-offset = <0x04>; @@ -123,8 +129,9 @@ sysclk: apsys@24M { }; /* One-bit control for the PCI bus clock (33 or 25 MHz) */ - pciclk: pciclk@24M { + pciclk: clock-controller@4,8 { compatible = "arm,syscon-icst525-integratorap-pci"; + reg = <0x04 0x04>; #clock-cells = <0>; lock-offset = <0x1c>; vco-offset = <0x04>; diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts index 01fa229e1bd0..38fc7e81bdb6 100644 --- a/arch/arm/boot/dts/integratorcp.dts +++ b/arch/arm/boot/dts/integratorcp.dts @@ -92,8 +92,9 @@ cm24mhz: cm24mhz@24M { }; /* Oscillator on the core module, clocks the CPU core */ - cmcore: cmosc@24M { + cmcore: clock-controller@8 { compatible = "arm,syscon-icst525-integratorcp-cm-core"; + reg = <0x08 0x04>; #clock-cells = <0>; lock-offset = <0x14>; vco-offset = <0x08>; @@ -101,8 +102,9 @@ cmcore: cmosc@24M { }; /* Oscillator on the core module, clocks the memory bus */ - cmmem: cmosc@24M { + cmmem: clock-controller@8,12 { compatible = "arm,syscon-icst525-integratorcp-cm-mem"; + reg = <0x08 0x04>; #clock-cells = <0>; lock-offset = <0x14>; vco-offset = <0x08>; @@ -110,8 +112,9 @@ cmmem: cmosc@24M { }; /* Auxilary oscillator on the core module, clocks the CLCD */ - auxosc: auxosc@24M { + auxosc: clock-controller@1c { compatible = "arm,syscon-icst525"; + reg = <0x1c 0x04>; #clock-cells = <0>; lock-offset = <0x14>; vco-offset = <0x1c>; From patchwork Mon Sep 13 19:28:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 509838 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp851396jao; 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[66.90.148.213]) by smtp.googlemail.com with ESMTPSA id m24sm1907838oie.50.2021.09.13.12.28.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 12:28:29 -0700 (PDT) From: Rob Herring To: Linus Walleij , Stephen Boyd , Pavel Machek Cc: Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-leds@vger.kernel.org, Michal Marek , Nick Desaulniers , linux-kbuild@vger.kernel.org, Masahiro Yamada Subject: [PATCH v2 8/8] kbuild: Enable dtc 'unit_address_format' warning by default Date: Mon, 13 Sep 2021 14:28:16 -0500 Message-Id: <20210913192816.1225025-9-robh@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210913192816.1225025-1-robh@kernel.org> References: <20210913192816.1225025-1-robh@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org With all the 'unit_address_format' warnings fixed, enable the warning by default. Cc: Michal Marek Cc: Nick Desaulniers Cc: linux-kbuild@vger.kernel.org Acked-by: Masahiro Yamada Signed-off-by: Rob Herring --- scripts/Makefile.lib | 1 - 1 file changed, 1 deletion(-) -- 2.30.2 Acked-by: Nick Desaulniers diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 54582673fc1a..56d50eb0cd80 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -310,7 +310,6 @@ DTC_FLAGS += -Wno-interrupt_provider # Disable noisy checks by default ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),) DTC_FLAGS += -Wno-unit_address_vs_reg \ - -Wno-unit_address_format \ -Wno-avoid_unnecessary_addr_size \ -Wno-alias_paths \ -Wno-graph_child_address \