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envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ilya Leoshkevich Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Ilya Leoshkevich Signed-off-by: Ilya Leoshkevich [rth: Split out of a larger patch.] Signed-off-by: Richard Henderson --- include/exec/translator.h | 9 +++++---- target/arm/arm_ldst.h | 12 ++++++------ target/alpha/translate.c | 2 +- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 9 +++++---- target/hexagon/translate.c | 3 ++- target/hppa/translate.c | 2 +- target/i386/tcg/translate.c | 10 +++++----- target/m68k/translate.c | 2 +- target/mips/tcg/translate.c | 8 ++++---- target/openrisc/translate.c | 2 +- target/ppc/translate.c | 5 +++-- target/riscv/translate.c | 5 +++-- target/s390x/tcg/translate.c | 16 +++++++++------- target/sh4/translate.c | 4 ++-- target/sparc/translate.c | 2 +- target/xtensa/translate.c | 5 +++-- target/mips/tcg/micromips_translate.c.inc | 2 +- target/mips/tcg/mips16e_translate.c.inc | 4 ++-- target/mips/tcg/nanomips_translate.c.inc | 4 ++-- 20 files changed, 58 insertions(+), 50 deletions(-) -- 2.25.1 diff --git a/include/exec/translator.h b/include/exec/translator.h index d318803267..6c054e8d05 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -157,7 +157,8 @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest); #define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \ static inline type \ - fullname ## _swap(CPUArchState *env, abi_ptr pc, bool do_swap) \ + fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \ + abi_ptr pc, bool do_swap) \ { \ type ret = load_fn(env, pc); \ if (do_swap) { \ @@ -166,10 +167,10 @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest); plugin_insn_append(&ret, sizeof(ret)); \ return ret; \ } \ - \ - static inline type fullname(CPUArchState *env, abi_ptr pc) \ + static inline type fullname(CPUArchState *env, \ + DisasContextBase *dcbase, abi_ptr pc) \ { \ - return fullname ## _swap(env, pc, false); \ + return fullname ## _swap(env, dcbase, pc, false); \ } GEN_TRANSLATOR_LD(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */) diff --git a/target/arm/arm_ldst.h b/target/arm/arm_ldst.h index 057160e8da..cee0548a1c 100644 --- a/target/arm/arm_ldst.h +++ b/target/arm/arm_ldst.h @@ -24,15 +24,15 @@ #include "qemu/bswap.h" /* Load an instruction and return it in the standard little-endian order */ -static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr, - bool sctlr_b) +static inline uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s, + target_ulong addr, bool sctlr_b) { - return translator_ldl_swap(env, addr, bswap_code(sctlr_b)); + return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b)); } /* Ditto, for a halfword (Thumb) instruction */ -static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr, - bool sctlr_b) +static inline uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s, + target_ulong addr, bool sctlr_b) { #ifndef CONFIG_USER_ONLY /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped @@ -41,7 +41,7 @@ static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr, addr ^= 2; } #endif - return translator_lduw_swap(env, addr, bswap_code(sctlr_b)); + return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b)); } #endif diff --git a/target/alpha/translate.c b/target/alpha/translate.c index de6c0a8439..b034206688 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2971,7 +2971,7 @@ static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *ctx = container_of(dcbase, DisasContext, base); CPUAlphaState *env = cpu->env_ptr; - uint32_t insn = translator_ldl(env, ctx->base.pc_next); + uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next); ctx->base.pc_next += 4; ctx->base.is_jmp = translate_one(ctx, insn); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 422e2ac0c9..a52949b1f3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14655,7 +14655,7 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) uint32_t insn; s->pc_curr = s->base.pc_next; - insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b); + insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b); s->insn = insn; s->base.pc_next += 4; diff --git a/target/arm/translate.c b/target/arm/translate.c index 24b7f49d76..422fca353d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9302,7 +9302,7 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s) * boundary, so we cross the page if the first 16 bits indicate * that this is a 32 bit insn. */ - uint16_t insn = arm_lduw_code(env, s->base.pc_next, s->sctlr_b); + uint16_t insn = arm_lduw_code(env, &s->base, s->base.pc_next, s->sctlr_b); return !thumb_insn_is_16bit(s, s->base.pc_next, insn); } @@ -9540,7 +9540,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) } dc->pc_curr = dc->base.pc_next; - insn = arm_ldl_code(env, dc->base.pc_next, dc->sctlr_b); + insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); dc->insn = insn; dc->base.pc_next += 4; disas_arm_insn(dc, insn); @@ -9610,11 +9610,12 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) } dc->pc_curr = dc->base.pc_next; - insn = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b); + insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn); dc->base.pc_next += 2; if (!is_16bit) { - uint32_t insn2 = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b); + uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next, + dc->sctlr_b); insn = insn << 16 | insn2; dc->base.pc_next += 2; diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 54fdcaa5e8..6fb4e6853c 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -112,7 +112,8 @@ static int read_packet_words(CPUHexagonState *env, DisasContext *ctx, memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t)); for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { words[nwords] = - translator_ldl(env, ctx->base.pc_next + nwords * sizeof(uint32_t)); + translator_ldl(env, &ctx->base, + ctx->base.pc_next + nwords * sizeof(uint32_t)); found_end = is_packet_end(words[nwords]); } if (!found_end) { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b18150ef8d..3ce22cdd09 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4177,7 +4177,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { /* Always fetch the insn, even if nullified, so that we check the page permissions for execute. */ - uint32_t insn = translator_ldl(env, ctx->base.pc_next); + uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next); /* Set up the IA queue for the next insn. This will be overwritten by a branch. */ diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index aacb605eee..a46be75b00 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2028,28 +2028,28 @@ static uint64_t advance_pc(CPUX86State *env, DisasContext *s, int num_bytes) static inline uint8_t x86_ldub_code(CPUX86State *env, DisasContext *s) { - return translator_ldub(env, advance_pc(env, s, 1)); + return translator_ldub(env, &s->base, advance_pc(env, s, 1)); } static inline int16_t x86_ldsw_code(CPUX86State *env, DisasContext *s) { - return translator_ldsw(env, advance_pc(env, s, 2)); + return translator_ldsw(env, &s->base, advance_pc(env, s, 2)); } static inline uint16_t x86_lduw_code(CPUX86State *env, DisasContext *s) { - return translator_lduw(env, advance_pc(env, s, 2)); + return translator_lduw(env, &s->base, advance_pc(env, s, 2)); } static inline uint32_t x86_ldl_code(CPUX86State *env, DisasContext *s) { - return translator_ldl(env, advance_pc(env, s, 4)); + return translator_ldl(env, &s->base, advance_pc(env, s, 4)); } #ifdef TARGET_X86_64 static inline uint64_t x86_ldq_code(CPUX86State *env, DisasContext *s) { - return translator_ldq(env, advance_pc(env, s, 8)); + return translator_ldq(env, &s->base, advance_pc(env, s, 8)); } #endif diff --git a/target/m68k/translate.c b/target/m68k/translate.c index c34d9aed61..50a55f949c 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -415,7 +415,7 @@ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val, static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s) { uint16_t im; - im = translator_lduw(env, s->pc); + im = translator_lduw(env, &s->base, s->pc); s->pc += 2; return im; } diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 6f4a9a839c..148afec9dc 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -16041,17 +16041,17 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) is_slot = ctx->hflags & MIPS_HFLAG_BMASK; if (ctx->insn_flags & ISA_NANOMIPS32) { - ctx->opcode = translator_lduw(env, ctx->base.pc_next); + ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); insn_bytes = decode_isa_nanomips(env, ctx); } else if (!(ctx->hflags & MIPS_HFLAG_M16)) { - ctx->opcode = translator_ldl(env, ctx->base.pc_next); + ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next); insn_bytes = 4; decode_opc(env, ctx); } else if (ctx->insn_flags & ASE_MICROMIPS) { - ctx->opcode = translator_lduw(env, ctx->base.pc_next); + ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); insn_bytes = decode_isa_micromips(env, ctx); } else if (ctx->insn_flags & ASE_MIPS16) { - ctx->opcode = translator_lduw(env, ctx->base.pc_next); + ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); insn_bytes = decode_ase_mips16e(env, ctx); } else { gen_reserved_instruction(ctx); diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index d6ea536744..5f3d430245 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1613,7 +1613,7 @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); OpenRISCCPU *cpu = OPENRISC_CPU(cs); - uint32_t insn = translator_ldl(&cpu->env, dc->base.pc_next); + uint32_t insn = translator_ldl(&cpu->env, &dc->base, dc->base.pc_next); if (!decode(dc, insn)) { gen_illegal_exception(dc); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 171b216e17..5d8b06bd80 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -8585,7 +8585,7 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); ctx->cia = pc = ctx->base.pc_next; - insn = translator_ldl_swap(env, pc, need_byteswap(ctx)); + insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); ctx->base.pc_next = pc += 4; if (!is_prefix_insn(ctx, insn)) { @@ -8600,7 +8600,8 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); ok = true; } else { - uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx)); + uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, + need_byteswap(ctx)); ctx->base.pc_next = pc += 4; ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e356fc6c46..74b33fa3c9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -500,7 +500,8 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) } else { uint32_t opcode32 = opcode; opcode32 = deposit32(opcode32, 16, 16, - translator_lduw(env, ctx->base.pc_next + 2)); + translator_lduw(env, &ctx->base, + ctx->base.pc_next + 2)); ctx->pc_succ_insn = ctx->base.pc_next + 4; if (!decode_insn32(ctx, opcode32)) { gen_exception_illegal(ctx); @@ -561,7 +562,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *ctx = container_of(dcbase, DisasContext, base); CPURISCVState *env = cpu->env_ptr; - uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next); + uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); decode_opc(env, ctx, opcode16); ctx->base.pc_next = ctx->pc_succ_insn; diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 0632b0374b..f284870cd2 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -388,14 +388,16 @@ static void update_cc_op(DisasContext *s) } } -static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc) +static inline uint64_t ld_code2(CPUS390XState *env, DisasContext *s, + uint64_t pc) { - return (uint64_t)cpu_lduw_code(env, pc); + return (uint64_t)translator_lduw(env, &s->base, pc); } -static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc) +static inline uint64_t ld_code4(CPUS390XState *env, DisasContext *s, + uint64_t pc) { - return (uint64_t)(uint32_t)cpu_ldl_code(env, pc); + return (uint64_t)(uint32_t)translator_ldl(env, &s->base, pc); } static int get_mem_index(DisasContext *s) @@ -6273,7 +6275,7 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s) ilen = s->ex_value & 0xf; op = insn >> 56; } else { - insn = ld_code2(env, pc); + insn = ld_code2(env, s, pc); op = (insn >> 8) & 0xff; ilen = get_ilen(op); switch (ilen) { @@ -6281,10 +6283,10 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s) insn = insn << 48; break; case 4: - insn = ld_code4(env, pc) << 32; + insn = ld_code4(env, s, pc) << 32; break; case 6: - insn = (insn << 48) | (ld_code4(env, pc + 2) << 16); + insn = (insn << 48) | (ld_code4(env, s, pc + 2) << 16); break; default: g_assert_not_reached(); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 8704fea1ca..cf5fe9243d 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1907,7 +1907,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env) /* Read all of the insns for the region. */ for (i = 0; i < max_insns; ++i) { - insns[i] = translator_lduw(env, pc + i * 2); + insns[i] = translator_lduw(env, &ctx->base, pc + i * 2); } ld_adr = ld_dst = ld_mop = -1; @@ -2307,7 +2307,7 @@ static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) } #endif - ctx->opcode = translator_lduw(env, ctx->base.pc_next); + ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); decode_opc(ctx); ctx->base.pc_next += 2; } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index bb70ba17de..fdb8bbe5dc 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5855,7 +5855,7 @@ static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) CPUSPARCState *env = cs->env_ptr; unsigned int insn; - insn = translator_ldl(env, dc->pc); + insn = translator_ldl(env, &dc->base, dc->pc); dc->base.pc_next += 4; disas_sparc_insn(dc, insn); diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 20399d6a04..dcf6b500ef 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -882,7 +882,8 @@ static int arg_copy_compare(const void *a, const void *b) static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) { xtensa_isa isa = dc->config->isa; - unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, dc->pc)}; + unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, &dc->base, + dc->pc)}; unsigned len = xtensa_op0_insn_len(dc, b[0]); xtensa_format fmt; int slot, slots; @@ -907,7 +908,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) dc->base.pc_next = dc->pc + len; for (i = 1; i < len; ++i) { - b[i] = translator_ldub(env, dc->pc + i); + b[i] = translator_ldub(env, &dc->base, dc->pc + i); } xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len); fmt = xtensa_format_decode(isa, dc->insnbuf); diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index 5e95f47854..0da4c802a3 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -1627,7 +1627,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) uint32_t op, minor, minor2, mips32_op; uint32_t cond, fmt, cc; - insn = translator_lduw(env, ctx->base.pc_next + 2); + insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); ctx->opcode = (ctx->opcode << 16) | insn; rt = (ctx->opcode >> 21) & 0x1f; diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc index 54071813f1..84d816603a 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -455,7 +455,7 @@ static void decode_i64_mips16(DisasContext *ctx, static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) { - int extend = translator_lduw(env, ctx->base.pc_next + 2); + int extend = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); int op, rx, ry, funct, sa; int16_t imm, offset; @@ -688,7 +688,7 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx) /* No delay slot, so just process as a normal instruction */ break; case M16_OPC_JAL: - offset = translator_lduw(env, ctx->base.pc_next + 2); + offset = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); offset = (((ctx->opcode & 0x1f) << 21) | ((ctx->opcode >> 5) & 0x1f) << 16 | offset) << 2; diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index a66ae26796..ccbcecad09 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -3656,7 +3656,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) int offset; int imm; - insn = translator_lduw(env, ctx->base.pc_next + 2); + insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); ctx->opcode = (ctx->opcode << 16) | insn; rt = extract32(ctx->opcode, 21, 5); @@ -3775,7 +3775,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) break; case NM_P48I: { - insn = translator_lduw(env, ctx->base.pc_next + 4); + insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 4); target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16; switch (extract32(ctx->opcode, 16, 5)) { case NM_LI48: From patchwork Sun Sep 12 15:58:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 509499 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp3096710jai; Sun, 12 Sep 2021 09:03:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwd/s6BSdVUMhc5UceUIqJ0QzAABPetsiLuI5hJevxz+Ee3WHeafR8IK+yu5o3FQPaTLv0c X-Received: by 2002:adf:9e49:: with SMTP id v9mr8133303wre.39.1631462616134; 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[209.51.188.17]) by mx.google.com with ESMTPS id 184si3783128wmz.1.2021.09.12.09.03.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 12 Sep 2021 09:03:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="vsT/ctD0"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47788 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPRx8-0008FQ-Ou for patch@linaro.org; Sun, 12 Sep 2021 12:03:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40106) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPRs1-0002MQ-JW for qemu-devel@nongnu.org; Sun, 12 Sep 2021 11:58:17 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:40809) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPRrx-0003uh-J4 for qemu-devel@nongnu.org; Sun, 12 Sep 2021 11:58:15 -0400 Received: by mail-pl1-x629.google.com with SMTP id n18so4256513plp.7 for ; Sun, 12 Sep 2021 08:58:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eLHG44jCWPrfG7hZcGkKiwrmgjxf0GnrOvDF2kTb5Z0=; b=vsT/ctD0xCdETlcGMvZbdQZ/CPHhfv78Zi01bjvsE8BKT3GE6oeYmXBcZNdSLYmUkO Nng1Qa3k3fP5TA9XZqAxbVvfsBN6sZH0XUT/QSbKOHLsC3vHhX8xjvznyx6ZvNhJSFm2 Vkf7GS+SphUkdVnhS3IcOmBXzSqIg17BkbuUZcRVHuRWGDfqjhQoYn+pVOYRCxchyKjj f0hwmLE/ico8/jZLHTJTdG1HrB9WX1E+6sgazTbdkJuIDOKuQjd7k6yP2dI5271r+ZqJ zWl3ocQ6ONCvanQWiuxSsoDA8jAIPNnpDjks21a8amcx8lw7FqGy8xy/I0BrscOy+3QO IDmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eLHG44jCWPrfG7hZcGkKiwrmgjxf0GnrOvDF2kTb5Z0=; b=5ixwIY/ZCkLmL8lcwPFcuXIKepAECOAfMY3a1niND7hujHB1XiIYHuPMPys/ZfrJ1r l9D09cgjG/WAYr5PZ0SwhecpclquIv9CkTxV680dovIVG0KkI6Prn4PtXCQc+vF4Eg93 SvCeLHJ/xqqZXfBDaLbMTmesbGnlWO5m2LnE2zopzYPXbewpiWGS29ljLNlwXy413Xke cMx4ctnarXQ2Zc5NBoNvKguT2Tz+okfG8un/T2/ZZAk0EvMiVQA0oLpu5iFh4qsGeRLn kIGDJEOVxaqZcOzsMUd6dPYhFsO3Uhn0bU+DrslAGAYDifYRj4VFP+7lxMuUpKkle7Jl xWxw== X-Gm-Message-State: AOAM532g4IUKwSTAQqZBxLiQPLQtw+itTA850yr9tvGy6he/fNkafwTp SoWBnFOZGMes+I4nMt/xXulMTZU11bQ2Jw== X-Received: by 2002:a17:90a:bc8d:: with SMTP id x13mr8059546pjr.9.1631462292179; Sun, 12 Sep 2021 08:58:12 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id v13sm4439415pfm.16.2021.09.12.08.58.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Sep 2021 08:58:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 2/9] accel/tcg: Clear PAGE_WRITE before translation Date: Sun, 12 Sep 2021 08:58:02 -0700 Message-Id: <20210912155809.196236-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210912155809.196236-1-richard.henderson@linaro.org> References: <20210912155809.196236-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ilya Leoshkevich Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Ilya Leoshkevich translate_insn() implementations fetch instruction bytes piecemeal, which can cause qemu-user to generate inconsistent translations if another thread modifies them concurrently [1]. Fix by making pages containing translated instruction non-writable right before loading instruction bytes from them. [1] https://lists.nongnu.org/archive/html/qemu-devel/2021-08/msg00644.html Signed-off-by: Ilya Leoshkevich Message-Id: <20210805204835.158918-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- include/exec/translate-all.h | 1 + include/exec/translator.h | 39 ++++++++++++++---------- accel/tcg/translate-all.c | 59 +++++++++++++++++++++--------------- accel/tcg/translator.c | 39 ++++++++++++++++++++++++ 4 files changed, 97 insertions(+), 41 deletions(-) -- 2.25.1 diff --git a/include/exec/translate-all.h b/include/exec/translate-all.h index a557b4e2bb..9f646389af 100644 --- a/include/exec/translate-all.h +++ b/include/exec/translate-all.h @@ -33,6 +33,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end); void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); #ifdef CONFIG_USER_ONLY +void page_protect(tb_page_addr_t page_addr); int page_unprotect(target_ulong address, uintptr_t pc); #endif diff --git a/include/exec/translator.h b/include/exec/translator.h index 6c054e8d05..9bc46eda59 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/plugin-gen.h" +#include "exec/translate-all.h" #include "tcg/tcg.h" @@ -74,6 +75,17 @@ typedef struct DisasContextBase { int num_insns; int max_insns; bool singlestep_enabled; +#ifdef CONFIG_USER_ONLY + /* + * Guest address of the last byte of the last protected page. + * + * Pages containing the translated instructions are made non-writable in + * order to achieve consistency in case another thread is modifying the + * code while translate_insn() fetches the instruction bytes piecemeal. + * Such writer threads are blocked on mmap_lock() in page_unprotect(). + */ + target_ulong page_protect_end; +#endif } DisasContextBase; /** @@ -156,28 +168,23 @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest); */ #define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \ - static inline type \ - fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \ - abi_ptr pc, bool do_swap) \ - { \ - type ret = load_fn(env, pc); \ - if (do_swap) { \ - ret = swap_fn(ret); \ - } \ - plugin_insn_append(&ret, sizeof(ret)); \ - return ret; \ - } \ + type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \ + abi_ptr pc, bool do_swap); \ static inline type fullname(CPUArchState *env, \ DisasContextBase *dcbase, abi_ptr pc) \ { \ return fullname ## _swap(env, dcbase, pc, false); \ } -GEN_TRANSLATOR_LD(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */) -GEN_TRANSLATOR_LD(translator_ldsw, int16_t, cpu_ldsw_code, bswap16) -GEN_TRANSLATOR_LD(translator_lduw, uint16_t, cpu_lduw_code, bswap16) -GEN_TRANSLATOR_LD(translator_ldl, uint32_t, cpu_ldl_code, bswap32) -GEN_TRANSLATOR_LD(translator_ldq, uint64_t, cpu_ldq_code, bswap64) +#define FOR_EACH_TRANSLATOR_LD(F) \ + F(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */) \ + F(translator_ldsw, int16_t, cpu_ldsw_code, bswap16) \ + F(translator_lduw, uint16_t, cpu_lduw_code, bswap16) \ + F(translator_ldl, uint32_t, cpu_ldl_code, bswap32) \ + F(translator_ldq, uint64_t, cpu_ldq_code, bswap64) + +FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD) + #undef GEN_TRANSLATOR_LD #endif /* EXEC__TRANSLATOR_H */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bbfcfb698c..fb9ebfad9e 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1297,31 +1297,8 @@ static inline void tb_page_add(PageDesc *p, TranslationBlock *tb, invalidate_page_bitmap(p); #if defined(CONFIG_USER_ONLY) - if (p->flags & PAGE_WRITE) { - target_ulong addr; - PageDesc *p2; - int prot; - - /* force the host page as non writable (writes will have a - page fault + mprotect overhead) */ - page_addr &= qemu_host_page_mask; - prot = 0; - for (addr = page_addr; addr < page_addr + qemu_host_page_size; - addr += TARGET_PAGE_SIZE) { - - p2 = page_find(addr >> TARGET_PAGE_BITS); - if (!p2) { - continue; - } - prot |= p2->flags; - p2->flags &= ~PAGE_WRITE; - } - mprotect(g2h_untagged(page_addr), qemu_host_page_size, - (prot & PAGE_BITS) & ~PAGE_WRITE); - if (DEBUG_TB_INVALIDATE_GATE) { - printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr); - } - } + /* translator_loop() must have made all TB pages non-writable */ + assert(!(p->flags & PAGE_WRITE)); #else /* if some code is already present, then the pages are already protected. So we handle the case where only the first TB is @@ -2394,6 +2371,38 @@ int page_check_range(target_ulong start, target_ulong len, int flags) return 0; } +void page_protect(tb_page_addr_t page_addr) +{ + target_ulong addr; + PageDesc *p; + int prot; + + p = page_find(page_addr >> TARGET_PAGE_BITS); + if (p && (p->flags & PAGE_WRITE)) { + /* + * Force the host page as non writable (writes will have a page fault + + * mprotect overhead). + */ + page_addr &= qemu_host_page_mask; + prot = 0; + for (addr = page_addr; addr < page_addr + qemu_host_page_size; + addr += TARGET_PAGE_SIZE) { + + p = page_find(addr >> TARGET_PAGE_BITS); + if (!p) { + continue; + } + prot |= p->flags; + p->flags &= ~PAGE_WRITE; + } + mprotect(g2h_untagged(page_addr), qemu_host_page_size, + (prot & PAGE_BITS) & ~PAGE_WRITE); + if (DEBUG_TB_INVALIDATE_GATE) { + printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr); + } + } +} + /* called from signal handler: invalidate the code and unprotect the * page. Return 0 if the fault was not handled, 1 if it was handled, * and 2 if it was handled but the caller must cause the TB to be diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index c53a7f8e44..390bd9db0a 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -42,6 +42,15 @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest) return ((db->pc_first ^ dest) & TARGET_PAGE_MASK) == 0; } +static inline void translator_page_protect(DisasContextBase *dcbase, + target_ulong pc) +{ +#ifdef CONFIG_USER_ONLY + dcbase->page_protect_end = pc | ~TARGET_PAGE_MASK; + page_protect(pc); +#endif +} + void translator_loop(const TranslatorOps *ops, DisasContextBase *db, CPUState *cpu, TranslationBlock *tb, int max_insns) { @@ -56,6 +65,7 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db, db->num_insns = 0; db->max_insns = max_insns; db->singlestep_enabled = cflags & CF_SINGLE_STEP; + translator_page_protect(db, db->pc_next); ops->init_disas_context(db, cpu); tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */ @@ -137,3 +147,32 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db, } #endif } + +static inline void translator_maybe_page_protect(DisasContextBase *dcbase, + target_ulong pc, size_t len) +{ +#ifdef CONFIG_USER_ONLY + target_ulong end = pc + len - 1; + + if (end > dcbase->page_protect_end) { + translator_page_protect(dcbase, end); + } +#endif +} + +#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \ + type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \ + abi_ptr pc, bool do_swap) \ + { \ + translator_maybe_page_protect(dcbase, pc, sizeof(type)); \ + type ret = load_fn(env, pc); \ + if (do_swap) { \ + ret = swap_fn(ret); \ + } \ + plugin_insn_append(&ret, sizeof(ret)); \ + return ret; \ + } + +FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD) + +#undef GEN_TRANSLATOR_LD From patchwork Sun Sep 12 15:58:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 509494 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp3093886jai; Sun, 12 Sep 2021 08:59:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyUY3gC1aLTerpIVCU7rFEazLe8txMTZZjCmrx2M64MzmN1quh+OfSkQbvORR81Cm4STk+E X-Received: by 2002:a02:2204:: with SMTP id o4mr5876772jao.145.1631462399874; Sun, 12 Sep 2021 08:59:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631462399; cv=none; d=google.com; s=arc-20160816; b=b4LqwrfoH3teH6tQBghNjyGVEVyjtKjdkSxYcGVZAnUyO34obV2WGVJ0Zikug0Ovo4 IsyrvEXsA5F9IW0IUeSc1Hf7+0V16eO7WvYwAvn6x2ftM3FlXth6/zAeTcHEDzVXabrj uZ5F6DaiVvIXyxijn3OIC/hYEmlYlLjXAVa+w4ujbUO0yYTQolml7kGaouWF4wI5uhmW Kl18ZmTLmDtZ/EK0L41VSG+we4HosunlsxOxfHsacMynxwl7tI+t7vjeHfb0G5h8g6L+ ICrSJLXkDQPwWJmsx/BH2KS9ClQNYBoCaaE5eoswu+IbhqPaZzetr4kl+5SRMb1ljeaV hLYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xTIxcHhgBqxY5Qqs3Qm50I0S2odWSXBe4kNBC/XEBq0=; b=aGkGR9NPJQKdAlMHS7i6ld41c2ZpJ4UNO4wxuD2NRBLdcRMyJGw7yJ/US+orRSRybS jC3uEhAQIqNe9nb5uiWPmT0H+pfPB0IdUbyWs6scykdcI4GCUP/GTkFpUhgQ0xBAZcbW TTDak1Bq7RB4/OSAIm0vDjtvwhG7J0K+GT7K13VS/ECsj9qJupC5fC18bsbBwTuMxLPD DjuP3w6tJ15xPopQR4cfzLTdN90d4xQ0sazkoL34R3bT+ueAUGUqjSAnY2VpLGshc+O/ 7TKJz9ifDfZ6Mq5aTX2NJMwsvtB4TboQxW4kG/0UUNMnBOONSmegtlA4qISdtrgAq0Fn 5xjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EQowP4au; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z23si5355137jas.40.2021.09.12.08.59.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 12 Sep 2021 08:59:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EQowP4au; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39322 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPRtf-0002SU-BX for patch@linaro.org; Sun, 12 Sep 2021 11:59:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40120) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPRs2-0002NE-4J for qemu-devel@nongnu.org; Sun, 12 Sep 2021 11:58:18 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:39804) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPRry-0003uo-8P for qemu-devel@nongnu.org; Sun, 12 Sep 2021 11:58:17 -0400 Received: by mail-pl1-x62b.google.com with SMTP id c4so2713629pls.6 for ; Sun, 12 Sep 2021 08:58:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xTIxcHhgBqxY5Qqs3Qm50I0S2odWSXBe4kNBC/XEBq0=; b=EQowP4aujitLFXTmAcp/FAajb9HJX5SmJnDuCUdnBmM3X7cjDInr2VGP7BNfOffbMI /K1QrbpbZtPJ9E+97eBIelpSibmgiyyr3nF4+mXILfS0k0WZRQSD3If4Alb8ZTJIxfJD 5oCWK7eAjrjxz195oOcZ3TNfk93OZRIVAd2MxPwBn93+4NGF+YEr6vZwJqyopVO0+jBV PPqySojcklmP/nI4SE/JQRd25LeEHHrqUKhlXBWiJnJNLEkmFeK1L1JMCWeG2161xSsX JLB4csmHtsTK5roOTillanCOrHRzjFl+ruyj3q8T8eUDSNi07MG0Dq/aRDA+a1zOtuJX evRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xTIxcHhgBqxY5Qqs3Qm50I0S2odWSXBe4kNBC/XEBq0=; b=eVGunGAPzMAG9hV9sVUNJgGxUsVE1wNxxhFVVmRVo+1wNupVhQeMRaZ3OYwfR9x5nS ezH5l0F/kXD4Moz5cNyC+R2D4Upv4COvQXrt5XHrokb0+QtMQh0NmutuWSzsKL1GI7UA uOrl7zEuqp7cOBlcPPWVOj0LbVndJ8xNcFDUPzNlE1bue48k46/2j7toc4cHQJyvqRCo FQZMwmM4ZOpMGoRTV434X34HWkluQyr0klLpMHB7zdpjue8j3t+H2zUHV/OoBXcv35Ab wEWLeNGUftCRFIawNRmkWLAER2PnGoBUVaeldl2I2UiBP83ThqLDJ4ltzgRLoaovnr5T av9Q== X-Gm-Message-State: AOAM533KlXsMlObOqQ74rw2N4YrO4YiupcmJopnLcJSuWiy2DEZFKWkM UB6c2PhNF79k16qucVIggL7KVDV7hUY5BA== X-Received: by 2002:a17:90a:a23:: with SMTP id o32mr264815pjo.172.1631462292987; Sun, 12 Sep 2021 08:58:12 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id v13sm4439415pfm.16.2021.09.12.08.58.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Sep 2021 08:58:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 3/9] tcg/i386: Split P_VEXW from P_REXW Date: Sun, 12 Sep 2021 08:58:03 -0700 Message-Id: <20210912155809.196236-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210912155809.196236-1-richard.henderson@linaro.org> References: <20210912155809.196236-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We need to be able to represent VEX.W on a 32-bit host, where REX.W will always be zero. Fixes the encoding for VPSLLVQ and VPSRLVQ. Fixes: a2ce146a068 ("tcg/i386: Support vector variable shift opcodes") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/385 Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 98d924b91a..997510109d 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -241,8 +241,9 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) #define P_EXT 0x100 /* 0x0f opcode prefix */ #define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ #define P_DATA16 0x400 /* 0x66 opcode prefix */ +#define P_VEXW 0x1000 /* Set VEX.W = 1 */ #if TCG_TARGET_REG_BITS == 64 -# define P_REXW 0x1000 /* Set REX.W = 1 */ +# define P_REXW P_VEXW /* Set REX.W = 1; match VEXW */ # define P_REXB_R 0x2000 /* REG field as byte register */ # define P_REXB_RM 0x4000 /* R/M field as byte register */ # define P_GS 0x8000 /* gs segment override */ @@ -410,13 +411,13 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) #define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16) #define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16) #define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16) -#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_REXW) +#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW) #define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) #define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16) -#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_REXW) +#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW) #define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16) #define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16) -#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_REXW) +#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW) #define OPC_VZEROUPPER (0x77 | P_EXT) #define OPC_XCHG_ax_r32 (0x90) @@ -576,7 +577,7 @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v, /* Use the two byte form if possible, which cannot encode VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */ - if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_REXW)) == P_EXT + if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_VEXW)) == P_EXT && ((rm | index) & 8) == 0) { /* Two byte VEX prefix. */ tcg_out8(s, 0xc5); @@ -601,7 +602,7 @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v, tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */ tcg_out8(s, tmp); - tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */ + tmp = (opc & P_VEXW ? 0x80 : 0); /* VEX.W */ } tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */ From patchwork Sun Sep 12 15:58:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 509497 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp3096610jai; Sun, 12 Sep 2021 09:03:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxpfL3lzhv6ptqSb3SCcYCoNbRDlmxwHkwKVVdfclAET/RCQ57UrTVCA1oGN7qJiYyUDLxq X-Received: by 2002:a1c:4b09:: with SMTP id y9mr3567971wma.45.1631462608876; Sun, 12 Sep 2021 09:03:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631462608; cv=none; d=google.com; s=arc-20160816; b=Y/vkNSXPHXsLRkhcR1jtIlHLJKZenLiX8SpzE95rt09FrnDnfdhhiTvJySBQJd5EXc xCA5TY7dep7PJF0FzzJt00zddErnszrPKWwxiUWUeOOF9uzOhar7m2ogy4EWIRbHOnPv PQydccCT7SbyIjNtcT42MJF4BVggl8vf60zfL5UiustheGgOQLbNIrlqit5gP8K9bC32 5dsiFjwuTtdM3ZMi4m886Z4eJMY1QR9q5DBXGkI44upeJaIGh93vn1OXIbz7HXoLSJgo REOY7bg62ES8QZUyfH+4hRWQhFm0ymmNQNibKQd1MINfIbm2BIkU+7Q3VaJgMwzxsZMO 10hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4qLOJ7aAC4BizQd/i02xX0hEQglVCR9hQiC8rfWR7Us=; b=rcXIF6dBiOLretRCrlmYmEKtr4NXoi1KQVFRZ8kXudJX7/oRdXLVhgo+FmOgjY7WNv xxJqwR5HnWVjNfnHLwyb0hO0QF2dvLOeumLaTrAemy7A4fEzq0durpHn3ZrmIHm1iz+B 310RgOrvjcdMhTUf2KFM4thKhzlGlUhCHbHIh7ZfYhjj9wPPhx8jc4zFuS3DY7aYTp71 lmzx9uZJhEPyws0unPVpriziIREysg+CvQKkRzxPY7hHjhmhTSYKyD4wxApdg18Dq4xP 70ZazJjbmqN5+Le1sSAPbGwRd41QjpUJkKkzoubaRTqpaMw9etKnTuH3aH3x3sSUAkQX CEvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J7B4eDwf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h6si1407057wml.83.2021.09.12.09.03.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 12 Sep 2021 09:03:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J7B4eDwf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47396 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPRx1-0007zp-VC for patch@linaro.org; Sun, 12 Sep 2021 12:03:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40108) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPRs1-0002MR-Kx for qemu-devel@nongnu.org; Sun, 12 Sep 2021 11:58:17 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:42931) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPRrz-0003vQ-4q for qemu-devel@nongnu.org; Sun, 12 Sep 2021 11:58:17 -0400 Received: by mail-pl1-x635.google.com with SMTP id n4so4249549plh.9 for ; Sun, 12 Sep 2021 08:58:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4qLOJ7aAC4BizQd/i02xX0hEQglVCR9hQiC8rfWR7Us=; b=J7B4eDwfWuTdlCqBUcS077j1KftDXaNKG2WBXRsA6Sgc/ikWItxTG5F00+4lOjYM48 q0DU1ytuRlWDrnryc25ccjcJzVoSAbozidI5MZj981xAdbAfIkgPClF7WQvEQCo3BJs/ bje0Wdu512RVsx6j33IMsK0VH1VzVaPZ5sBQnC5IJ98QiRimcCUqs/tCxZEceMlLdXM4 lg0GoIB4aB7UbPgqwtbJCMrUNH+Nn6FIygpIxOcS5sUfOW0Uk5pP4jXU1xMQFpESgpXL HWIQMjySe0npcVgDWn3aIvhDmiCdujqFoHMPqcKvQIFKXCLLwlkca/xrgbGjYAlgxEPZ G+FQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4qLOJ7aAC4BizQd/i02xX0hEQglVCR9hQiC8rfWR7Us=; b=012UX7vGYWYuwUTQbPmUPyERSfCa4r/yFINXC0hnT98IJAWU2AAAnOx7cBN7bkGMZW jKUNJ7N3lbAPoenz7YWJzjan1sNYvegtNaNpufANGlPJM4vu+uK++3s9bstv4Kh/BeW+ AASXs4g0tMaAWArx7S6EOsLSwpbs4OLkZNNX3sCOC6dgnh1CCmp4oaj5V7UPBN6Axreg kC2qFU3nyZB3NWocDquSUFH0uMFy2jQH+3l2avZxoFPvpae+EwK6Okq4li2yGoMHpW/5 U/2NdjS3oTJJmUsFG6C8Zrlx3+2OUviGYMMuoSnviPCvMgNs96sPnA07Ndf30mYJOp3i Mp1g== X-Gm-Message-State: AOAM5326DID52jG1Z/3zKks94NzFMFpuzBbcqrBqAVWTlbXxMJTq8Dme mkj71pvdo5ZP85kiZuEU0KSMX4ObrIH2Lg== X-Received: by 2002:a17:90b:4904:: with SMTP id kr4mr8417715pjb.50.1631462293808; Sun, 12 Sep 2021 08:58:13 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id v13sm4439415pfm.16.2021.09.12.08.58.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Sep 2021 08:58:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 4/9] accel/tcg: remove redundant TCG_KICK_PERIOD define Date: Sun, 12 Sep 2021 08:58:04 -0700 Message-Id: <20210912155809.196236-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210912155809.196236-1-richard.henderson@linaro.org> References: <20210912155809.196236-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Luc Michel , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel The TCG_KICK_PERIOD macro is already defined in tcg-accel-ops-rr.h. Remove it from tcg-accel-ops-rr.c. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210811141229.12470-1-lmichel@kalray.eu> Signed-off-by: Richard Henderson --- accel/tcg/tcg-accel-ops-rr.c | 2 -- 1 file changed, 2 deletions(-) -- 2.25.1 diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index c02c061ecb..a5fd26190e 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -60,8 +60,6 @@ void rr_kick_vcpu_thread(CPUState *unused) static QEMUTimer *rr_kick_vcpu_timer; static CPUState *rr_current_cpu; -#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10) - static inline int64_t rr_next_kick_time(void) { return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD; From patchwork Sun Sep 12 15:58:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 509501 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp3099344jai; Sun, 12 Sep 2021 09:06:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxQ1OQXdDich3u4TyDDJq9BxbNvCeNxFEAIflJRxWa+q3YSJdnpYLtB18C4YU1fKMMcdVPX X-Received: by 2002:a05:600c:3b26:: with SMTP id m38mr7080105wms.155.1631462805981; Sun, 12 Sep 2021 09:06:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631462805; cv=none; d=google.com; s=arc-20160816; b=ZVYKLttNe8QTRaKQCyM2JswdGZzs3KFtpIRLFaBAtzNUGvxfxEqJNySFc7FSg6juEI AOj23/fHDM3bWL1B1KbRRP2JW6OwnGverDRunGwhdH6u3UZmDdznNV2QXR35bWyy+sBw rwFutiZeo2Q2pTdOwVyBVW8Z8mbu9KbHhA8BAmG7GSiKgwTJjLRcNCwNI+dxauPWFlEQ gIS9gg1Tq+uTBg0lgbqbDXdegI02t01fX26Hz2Aa+g5HES1tw7vISYhf5hVhO/G6dwIQ YyFg70TkKOAxLYWBBYSjacmxQf3QD5Y5j0yz0d5P9cUWz4Ml2U01sifYnoZsJloXT5sz kLOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mo8bAa/Ep14lrVyCCKLWc2/qVNIgW8fWICNcTlyJnEo=; b=ixyU2S6+nt/hc9R2UOr1gseL9rBHTclXdIBzZjlBaLIct9nNH41laNBRP+fnqUrp1O HSVl99Iz49DDQcX5PnqH9bBVcqKayXrjWbdnqDsICmiRDnbpbAbv2lJ3cEtxNQ8hR0Mr ot3yjHFFZzq6dGY1kW3OQMxoKPPd3/SU1mZ1zlP2ZX5P8tQgrYWLpube+ipqDAACiX+E R9XeYDA0h/ieouLCQOJqxyXH0nGN30QI1ZNtiDEkY6wPjj9ScdF0ae6EMNgLowb0g2eM MhDcWvSa2Q7foW2yfQyVoosckygifI7Z+r50xGtNArkEnrCpUoRCG7JRPq9QXtgcaqx9 7uog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yHyodcA8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j18si4639218wrh.52.2021.09.12.09.06.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 12 Sep 2021 09:06:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yHyodcA8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57188 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPS0B-00061Q-75 for patch@linaro.org; Sun, 12 Sep 2021 12:06:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40156) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPRs4-0002QE-Gm for qemu-devel@nongnu.org; Sun, 12 Sep 2021 11:58:21 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:36831) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPRrz-0003wJ-T8 for qemu-devel@nongnu.org; Sun, 12 Sep 2021 11:58:20 -0400 Received: by mail-pg1-x52d.google.com with SMTP id t1so7037044pgv.3 for ; Sun, 12 Sep 2021 08:58:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mo8bAa/Ep14lrVyCCKLWc2/qVNIgW8fWICNcTlyJnEo=; b=yHyodcA8fcQjjJC1ke3hNEXdLnjKF7cvxhUXPAnlushiIKz2AKMdOluu4G6gRRae3P +aFTYaaK/MM9emNCy5ronvq/43H8RI5NEeMW6sM+gdtijCVXhXrdknFI1H6m1jokh4Yh 7/nbReNmXqLwfIl4VI2rIHDcX0KoLSe4scVeHPdg3L5Q7zBbCczHFC2jjsk5RTIJCJVK Ffp4aGrhGhyZ5hoxl5SqNwG0v+EESNa5l0q+QxAan3TayEWp1W92+ACOXKCvJVqmLIkl 0cKnreb3UcUuyxVth65jrK31/7/cn85vlWdrSyUwUb8aM6v2v4mM3pNVBv8aUL/KvdEC owAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mo8bAa/Ep14lrVyCCKLWc2/qVNIgW8fWICNcTlyJnEo=; b=16NoIC0OtTTW+sSbtDlaI4hKnuycjkhzPOHg9gl/+IYLo5yNcLXzMwrBKvDwNKtcyI wOlOqhloh3AMyqrwMh2ODGtmJZsgWff/B2voNGZ5ik9wu4/BxB9II6wSW7IrnKBnFa35 PewGQeuESbEVdTz3ZzICds5sJMjUZzUEXdjBpvYGbfl9eZyfbMvpK4kjNLUiPb6PpkLD wKcohqpE43DksrIITvyW00QAQ/y3qG0F9aIKFb+KhZ/p4BdhxiY/NcU1lD5VBJeG+Ag0 BDFf45wC/VDWQoV99+oI2+EgCCFladpFpXKAZ+ngmCh11WteP4/3MRvQIphLrBcisQ5d oIdA== X-Gm-Message-State: AOAM5330YYUwi8ZO56/Dj6NBdE2wHAjKelvvUVYFAqMjEmE1jGvAt8zs yhE+uuwfbMyOpo3Etegw8dKFK/AYUIR+4g== X-Received: by 2002:a63:e510:: with SMTP id r16mr7232349pgh.34.1631462294650; Sun, 12 Sep 2021 08:58:14 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id v13sm4439415pfm.16.2021.09.12.08.58.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Sep 2021 08:58:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 5/9] tcg: Remove tcg_global_reg_new defines Date: Sun, 12 Sep 2021 08:58:05 -0700 Message-Id: <20210912155809.196236-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210912155809.196236-1-richard.henderson@linaro.org> References: <20210912155809.196236-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Bin Meng , =?utf-8?q?Phi?= =?utf-8?q?lippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Since commit 1c2adb958fc0 ("tcg: Initialize cpu_env generically"), these tcg_global_reg_new_ macros are not used anywhere. Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210816143507.11200-1-bmeng.cn@gmail.com> Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 2 -- target/hppa/translate.c | 3 --- 2 files changed, 5 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 2a654f350c..0545a6224c 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -843,7 +843,6 @@ static inline void tcg_gen_plugin_cb_end(void) #if TARGET_LONG_BITS == 32 #define tcg_temp_new() tcg_temp_new_i32() -#define tcg_global_reg_new tcg_global_reg_new_i32 #define tcg_global_mem_new tcg_global_mem_new_i32 #define tcg_temp_local_new() tcg_temp_local_new_i32() #define tcg_temp_free tcg_temp_free_i32 @@ -851,7 +850,6 @@ static inline void tcg_gen_plugin_cb_end(void) #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 #else #define tcg_temp_new() tcg_temp_new_i64() -#define tcg_global_reg_new tcg_global_reg_new_i64 #define tcg_global_mem_new tcg_global_mem_new_i64 #define tcg_temp_local_new() tcg_temp_local_new_i64() #define tcg_temp_free tcg_temp_free_i64 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3ce22cdd09..c3698cf067 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -34,7 +34,6 @@ #undef TCGv #undef tcg_temp_new -#undef tcg_global_reg_new #undef tcg_global_mem_new #undef tcg_temp_local_new #undef tcg_temp_free @@ -59,7 +58,6 @@ #define TCGv_reg TCGv_i64 #define tcg_temp_new tcg_temp_new_i64 -#define tcg_global_reg_new tcg_global_reg_new_i64 #define tcg_global_mem_new tcg_global_mem_new_i64 #define tcg_temp_local_new tcg_temp_local_new_i64 #define tcg_temp_free tcg_temp_free_i64 @@ -155,7 +153,6 @@ #else #define TCGv_reg TCGv_i32 #define tcg_temp_new tcg_temp_new_i32 -#define tcg_global_reg_new tcg_global_reg_new_i32 #define tcg_global_mem_new tcg_global_mem_new_i32 #define tcg_temp_local_new tcg_temp_local_new_i32 #define tcg_temp_free tcg_temp_free_i32 From patchwork Sun Sep 12 15:58:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 509496 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp3093889jai; Sun, 12 Sep 2021 09:00:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx7iYsCAWvLAnO6BRbNgzCTLI2AcSuEofnqUvYoYOhbRqXGJJTIKO6u5LP/AwJ/O/huA77S X-Received: by 2002:a6b:14f:: with SMTP id 76mr5600110iob.211.1631462400072; Sun, 12 Sep 2021 09:00:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631462400; cv=none; d=google.com; s=arc-20160816; b=z+KlWm/rls6h+ae+hE675RbsoEx7nasiORThqa+ZS3jjtvVI7rwC050X75cjgTzgOr HZW3HB4PVFI5ScR+DrsagGEuTraaz9f0/CKO82CoucbD/bMVHq+EGiw8TS7IiqsTOxLc pM82IJZ891IbPuyOISXWT5Mf3N9B6KQ/hCePLrKZDNkA1hfSkqAvVfA3IGg5UbZPga4S /UdtuNC76x8QwbqND/eZ2MtMePA0noI4JzGj/tc3Fkj0LSlY/D0VxcKARwio+LsMG3vh UHqW0K53idrGbQg0aXm6yMF/yf9m5zuAnIRBCnm3dmfVOhWyedVoiq1r4TwxiTctNnL/ EtIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WQDuqbSrDr+qw7KrlgTnp7QFi56WX9RoG9PJ3coNJeg=; b=USlnq4e84w6eU5J1wl/4Z9pl2IWmYLSP3jbpxOESMTylnz8+uVin73Haby5tXfg3gi ZcE/rMjMPewhueRzmijfjdGJ9zEcF+GmyOo8rwLVGE3IE7dXaFcZytLuhKsUxaOn3Q6x ep0ROp55+hkY7PXNVL147p988KntZwB3fpGMpm8MQCtiirOxllGUv0yaYzfYs8Vh0Bxo YYYWoMs0ckHcfy8GELKAobu+K32J3oo6tA1n10VmG3kwZRxAxobBMydC0TJnfnoa80qn V6iXJ3V8ehJ43N2nIyGrGbgit7PqjGaDKwgVtevazpW62L6fRTRoVOz0ZFuOIpJzyOAN 2/Gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GlXybQsW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g14si4988257jat.122.2021.09.12.09.00.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 12 Sep 2021 09:00:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GlXybQsW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39274 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPRtf-0002R7-G8 for patch@linaro.org; Sun, 12 Sep 2021 11:59:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40152) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPRs4-0002Pn-9o for qemu-devel@nongnu.org; Sun, 12 Sep 2021 11:58:20 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:44544) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPRs1-0003wo-C1 for qemu-devel@nongnu.org; Sun, 12 Sep 2021 11:58:20 -0400 Received: by mail-pj1-x1029.google.com with SMTP id gp20-20020a17090adf1400b00196b761920aso4760145pjb.3 for ; Sun, 12 Sep 2021 08:58:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WQDuqbSrDr+qw7KrlgTnp7QFi56WX9RoG9PJ3coNJeg=; b=GlXybQsWe+pPyo3VjOdYKrJ932JM7RquMO0mH4xIUVMqZMdN04C8Dhzv8t/pn6PYMB VrIfBPdpcNLdLtgcyOPtgYZ/XRbURu2xBhlrX6aEwZeiNKRil4omWQyQ4uMjT+wFObx3 fd2C3P/ZYKT4o+KNqL1SOnQyJC1WOkTvK1lkMeaWMriw3+8Vn2HfnpXYWPwIYUhjts7u JtI9NFiSeQjej/C7bTl1rIywVue8pHGxEogO7/1wc2vZOJjygOQnmp91Iol+sRgPF7qr teQBVozIi4GB3weGBOmSzBJWmjXeMb6ctHAUmPvcEWNrJTvrfsnARqaw43VOvKhmF2z9 lNUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WQDuqbSrDr+qw7KrlgTnp7QFi56WX9RoG9PJ3coNJeg=; b=hBlx18+Z87oviCWyEwjKzONjr8nXnAiv0LcRYtEUDvwMs1OSIbB6Sc3o8eh2LHnG+J mpCF087bil6jexRprfqTyxJALGngqwTAbuEVTXTgu1Ntpk8IYGXf3pJi6T08Qjj0ZAsy IP0JrtiCgdy8CzoiJvHHgPyHt7BKC64fXTJBZUV5sRqsHmkcdm6NPT//FFt7e1l+EoQI Kg0WbYK1r6ngiHlv8neazr+oSWvKe5PBjpYflraWI6hKnqr+T5HFRAN2QqFrYbnCrlrf tHxm4tZdJNCFYkdpk/ae+XAa8ZP6s0PnXmEMgdPxLj51X9czWjQp54mj84zd3FIJqiU0 oPJg== X-Gm-Message-State: AOAM532qObi9BODcEFBDrTVyIk+tpJ/4TsCjNVD6+XiP7bd/RShKOaUK cI1OzZ0wR73zdOxsgi8jY6wCQI2TDH3pow== X-Received: by 2002:a17:902:7d8f:b0:13a:79e7:5bf0 with SMTP id a15-20020a1709027d8f00b0013a79e75bf0mr6666987plm.27.1631462295407; Sun, 12 Sep 2021 08:58:15 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id v13sm4439415pfm.16.2021.09.12.08.58.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Sep 2021 08:58:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 6/9] include/qemu: Use builtins for bswap Date: Sun, 12 Sep 2021 08:58:06 -0700 Message-Id: <20210912155809.196236-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210912155809.196236-1-richard.henderson@linaro.org> References: <20210912155809.196236-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All supported compilers have builtins for this. Drop all of the complicated system detection stuff. Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210708181743.750220-1-richard.henderson@linaro.org> Signed-off-by: Richard Henderson --- meson.build | 6 ----- include/qemu/bswap.h | 53 +++----------------------------------------- 2 files changed, 3 insertions(+), 56 deletions(-) -- 2.25.1 diff --git a/meson.build b/meson.build index 9a64d16943..306797c604 100644 --- a/meson.build +++ b/meson.build @@ -1332,8 +1332,6 @@ config_host_data.set('HAVE_STRCHRNUL', cc.has_function('strchrnul')) config_host_data.set('HAVE_SYSTEM_FUNCTION', cc.has_function('system', prefix: '#include ')) # has_header_symbol -config_host_data.set('CONFIG_BYTESWAP_H', - cc.has_header_symbol('byteswap.h', 'bswap_32')) config_host_data.set('CONFIG_EPOLL_CREATE1', cc.has_header_symbol('sys/epoll.h', 'epoll_create1')) config_host_data.set('CONFIG_HAS_ENVIRON', @@ -1353,10 +1351,6 @@ config_host_data.set('CONFIG_INOTIFY', cc.has_header_symbol('sys/inotify.h', 'inotify_init')) config_host_data.set('CONFIG_INOTIFY1', cc.has_header_symbol('sys/inotify.h', 'inotify_init1')) -config_host_data.set('CONFIG_MACHINE_BSWAP_H', - cc.has_header_symbol('machine/bswap.h', 'bswap32', - prefix: '''#include - #include ''')) config_host_data.set('CONFIG_PRCTL_PR_SET_TIMERSLACK', cc.has_header_symbol('sys/prctl.h', 'PR_SET_TIMERSLACK')) config_host_data.set('CONFIG_RTNETLINK', diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h index 2d3bb8bbed..9e12bd8073 100644 --- a/include/qemu/bswap.h +++ b/include/qemu/bswap.h @@ -1,73 +1,26 @@ #ifndef BSWAP_H #define BSWAP_H -#ifdef CONFIG_MACHINE_BSWAP_H -# include -# include -#elif defined(__FreeBSD__) -# include -#elif defined(__HAIKU__) -# include -#elif defined(CONFIG_BYTESWAP_H) -# include -#define BSWAP_FROM_BYTESWAP -# else -#define BSWAP_FROM_FALLBACKS -#endif /* ! CONFIG_MACHINE_BSWAP_H */ - #ifdef __cplusplus extern "C" { #endif #include "fpu/softfloat-types.h" -#ifdef BSWAP_FROM_BYTESWAP static inline uint16_t bswap16(uint16_t x) { - return bswap_16(x); + return __builtin_bswap16(x); } static inline uint32_t bswap32(uint32_t x) { - return bswap_32(x); + return __builtin_bswap32(x); } static inline uint64_t bswap64(uint64_t x) { - return bswap_64(x); + return __builtin_bswap64(x); } -#endif - -#ifdef BSWAP_FROM_FALLBACKS -static inline uint16_t bswap16(uint16_t x) -{ - return (((x & 0x00ff) << 8) | - ((x & 0xff00) >> 8)); -} - -static inline uint32_t bswap32(uint32_t x) -{ - return (((x & 0x000000ffU) << 24) | - ((x & 0x0000ff00U) << 8) | - ((x & 0x00ff0000U) >> 8) | - ((x & 0xff000000U) >> 24)); -} - -static inline uint64_t bswap64(uint64_t x) -{ - return (((x & 0x00000000000000ffULL) << 56) | - ((x & 0x000000000000ff00ULL) << 40) | - ((x & 0x0000000000ff0000ULL) << 24) | - ((x & 0x00000000ff000000ULL) << 8) | - ((x & 0x000000ff00000000ULL) >> 8) | - ((x & 0x0000ff0000000000ULL) >> 24) | - ((x & 0x00ff000000000000ULL) >> 40) | - ((x & 0xff00000000000000ULL) >> 56)); -} -#endif - -#undef BSWAP_FROM_BYTESWAP -#undef BSWAP_FROM_FALLBACKS static inline void bswap16s(uint16_t *s) { From patchwork Sun Sep 12 15:58:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 509500 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp3098831jai; Sun, 12 Sep 2021 09:06:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxeOkoRPakCqf1WKMg4LxGLiXYBByMJ0J8RWBt20XmqXNf55CsbYCfglQuFJNeO/vfOTxZ/ X-Received: by 2002:adf:f183:: with SMTP id h3mr2905262wro.32.1631462770535; Sun, 12 Sep 2021 09:06:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631462770; cv=none; d=google.com; s=arc-20160816; b=NMnHhtyzJENWVH/s8QJcoICSMx0XGfCZckBRelM9EZe3vSnn1x9mNhTQPLc3CXyfJn zushJiSlIQNGhloNDfI/TKxvoHvUS6ZT8bkZWjov/no9/VNUwa7dtHNxg1EcSOfipINN q44oDxIN9q8ElkP8IlFu7a9fvrA+zuN22mvbQFlgV6Y9qhOFOn9LB295Ukd6xUtazY/t PR90udyQgKby0UMBK57YJwUrRy4xdFYChkYsSEGz9TvEZcUWVAop5AKnMiPGyAI9t+ei ZqGqCI+IEYz/CqN8ab4yicXVR4ay9bbJ0+2tOFUBzk4Zj+gfZWts8aK02t6vEkdQmhqT Scww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=m7emFn9ZXxGGMcBZFosB1EnmF9R96t2zGLMZbzq44mc=; b=dp7TtXo003lJaXXSNUxOXq2gRn6LRBq333gp+HqkHfNPhpnrWHYoDpc4ZRg83QWrd9 VOTmU3Vvi9xnrDPRDt+kXnjiFwjYUFq5R6Ddd5iYxRHnzCpVLb2xsyhJvT8peFSrx6Ox y9mrRvSBgUfnDAhcL+7UEMRia683lqY7m8QfVMeV3dLmc4sEPY2T/Cbt3Q+S2EPCsZ9e PHmXA9m1gYd7UD4vkYv6UaeYvzfaTL9OyAk6v1rT0FWXwrD2nC6IvTHcGfMlvpBPgynB vr/pS87x+kcbDC/A3hkmmDrZPNeyg/S0a20agIvny9/NZG/WOWVOPkysbXCvEI5rmqxa FAoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X1HK1FUm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i2si4796459wrm.110.2021.09.12.09.06.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 12 Sep 2021 09:06:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X1HK1FUm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPRzd-0004ms-IC for patch@linaro.org; Sun, 12 Sep 2021 12:06:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40158) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPRs4-0002QN-OU for qemu-devel@nongnu.org; Sun, 12 Sep 2021 11:58:21 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:37719) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPRs1-0003xF-CI for qemu-devel@nongnu.org; Sun, 12 Sep 2021 11:58:19 -0400 Received: by mail-pl1-x630.google.com with SMTP id f21so2021864plb.4 for ; Sun, 12 Sep 2021 08:58:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m7emFn9ZXxGGMcBZFosB1EnmF9R96t2zGLMZbzq44mc=; b=X1HK1FUm3HBpdWLlIShTQXfxDBn3QbTNqlzrS2uIb2MVZ+Vq/9RTQYFdj9FZQNuW1H PfenExM/qaeu4FWMFX2+c2yfYBeH3t1Vp+zCXFJA5DY/ZicbtpVS//vvUPDuV3c+fxLS 7KQg+W+JAV5oTG4qoGrIhP/R05GTJ84iPRtBnyHtXht/rbP241blCqTjdOpjjDfTiVRK K0tL3rchaTRfAVkPeq6xAces2OKPG55W09SXvoMbMOBDcp17VeE7x97gpmGv+T48Hf0x /GSKLz2J+mBWMoWveB24N85WYIz1bzznN9rpQOfsDtsmt5kbJKvmoQLLffjqtpt5GMhT r36A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m7emFn9ZXxGGMcBZFosB1EnmF9R96t2zGLMZbzq44mc=; b=YlN+9i2cuYuguezfVc9ZM4cTX/aqVAi+fMMybfEtC48HLvtNXQRxsWFKtLePW8FSlF JbVaUtWa0jveMrDsEnY+1eGw/T1DCPX+1vp3GtcBwqbMSBn2fAbQFrPMSvpn9X1aAvVr 1LKLi9R/FEygkpzPo9RXgloBd6Jn1zsEbd9Evtt1EdiXb9lM/xO0esI1BGZxg5NueO3J XRTLTZnEwKzN7REBQAgrxOWMDjW4lWl52CC1FGyoTHwDnodYo/SmTc/gaCjBK3sTevs8 oKBtrYwPOB1wH2BhQE3JFbh+0ZDVCIPDeks4p4riRofuxLaqBv8uyF0d1BsO7nnOAOe7 o7hA== X-Gm-Message-State: AOAM530RWN7SuOqJQzqSKOn7kzS/Pm9Db596HlB99PrEyPG9i4ezTzjm /6EgkQRn78lxyGGyyZSNjvBL6EPw7HCVAw== X-Received: by 2002:a17:90b:814:: with SMTP id bk20mr8255580pjb.108.1631462295989; Sun, 12 Sep 2021 08:58:15 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id v13sm4439415pfm.16.2021.09.12.08.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Sep 2021 08:58:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 7/9] tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN Date: Sun, 12 Sep 2021 08:58:07 -0700 Message-Id: <20210912155809.196236-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210912155809.196236-1-richard.henderson@linaro.org> References: <20210912155809.196236-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" If __APPLE__, ensure that _CALL_DARWIN is set, then remove our local TCG_TARGET_CALL_DARWIN. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index e0f4665213..2202ce017e 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -25,8 +25,8 @@ #include "elf.h" #include "../tcg-pool.c.inc" -#if defined _CALL_DARWIN || defined __APPLE__ -#define TCG_TARGET_CALL_DARWIN +#if !defined _CALL_DARWIN && defined __APPLE__ +#define _CALL_DARWIN 1 #endif #ifdef _CALL_SYSV # define TCG_TARGET_CALL_ALIGN_ARGS 1 @@ -169,7 +169,7 @@ static const int tcg_target_call_oarg_regs[] = { }; static const int tcg_target_callee_save_regs[] = { -#ifdef TCG_TARGET_CALL_DARWIN +#ifdef _CALL_DARWIN TCG_REG_R11, #endif TCG_REG_R14, @@ -2372,7 +2372,7 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count) # define LINK_AREA_SIZE (6 * SZR) # define LR_OFFSET (1 * SZR) # define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR) -#elif defined(TCG_TARGET_CALL_DARWIN) +#elif defined(_CALL_DARWIN) # define LINK_AREA_SIZE (6 * SZR) # define LR_OFFSET (2 * SZR) #elif TCG_TARGET_REG_BITS == 64 From patchwork Sun Sep 12 15:58:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 509502 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp3101027jai; Sun, 12 Sep 2021 09:09:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJznYcTwXzKB3gw/D/FZnpnNNOGZezHUmL/COSN0vtvpeK1i9cIE/8xq4DWH2QN8mwPD2BMu X-Received: by 2002:a9f:3e4c:: with SMTP id c12mr3031117uaj.75.1631462949805; Sun, 12 Sep 2021 09:09:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631462949; cv=none; d=google.com; s=arc-20160816; b=MNEkuT0Da2B3HXmBNMsQZMxj/EK3RGNG4oFvlEdMG9K+/kIR5gHroIKLeXXzFaEroy XjYOuxrGbc4dWtzjOgfzRFhbezc8O9gTupMaQ0sB54CCUWtmg+E+XR5jH3Rby1jwWkkp vwgYJAii6unMxYtPDreKa8adDbxI3497QVHP/57q4uhuaPTysuMxgTI7/KDIAVgJAjlq qVg5/WKxyjcwr1Q5Y1LfBTtcmJW4w7p63xs5ypH7YKByXSZ+WHkqloSMthefdq2WgNNR R2EGOlU1ZL4UKWJZmUDq6+eVMc+Wwvr80qxNzWu55I10S22dlxQXpVMHxXj1jGfdwxMD xCTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0lgwAN4JLa+eJyUWPeSpGCyCJ0/V+S2YWU/Kqpi1gBQ=; b=efovJs++mTqvDj/v1z/jQbWbDfS+sboDFcs6hswgA8n1IVKTDxJPdmwuXKfN2gdcsN Z+ptGioktvoor0k2JAgQFafbnjqNyoP2l4ZbYSpJ0nXLiubVXgRCFxgphbMgG/hHvdKk 6T8Xt3oQwjJvTjJlpELjfHFZBveZxPo9M55Fx2Dn8n/rwEjw1S6yvaufYuTFy1Nn6xAt scQT5z7YS5yuPalrbWau2ivR954SfsVkWnecygfFusjUcSYI/43wknwZsgWXvK0vxFrG uQNzCYhJDYXFAn45ikGsGsCeSSgTzyyChqP6zbIY3lJSAj1AtD3QzitvHBfFniBG7CFe Vung== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yP51pHcw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 73si1068181uan.50.2021.09.12.09.09.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 12 Sep 2021 09:09:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yP51pHcw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35636 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mPS2X-000285-6X for patch@linaro.org; Sun, 12 Sep 2021 12:09:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40170) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mPRs8-0002ST-2r for qemu-devel@nongnu.org; Sun, 12 Sep 2021 11:58:25 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:33286) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mPRs1-0003xc-TD for qemu-devel@nongnu.org; Sun, 12 Sep 2021 11:58:23 -0400 Received: by mail-pj1-x1029.google.com with SMTP id mi6-20020a17090b4b4600b00199280a31cbso3735332pjb.0 for ; Sun, 12 Sep 2021 08:58:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0lgwAN4JLa+eJyUWPeSpGCyCJ0/V+S2YWU/Kqpi1gBQ=; b=yP51pHcwrmx2oxBxaPl9XGJ8pj+i76hA6At+8sZWguIVn2hF/x9/PWxkAh6URyuZCt fb9Q9Wh1FNC58ihi8vnShAPgORQQz6uCbelqTLte4IasOFpI9fi8d5V33ieVUOQCkXdP 1iSIXq8t3f3augEBnz9q1YAavXG/jzn1Cb2bZKgZu1qPEWEJYLUAOOM10KC8Ht0YiERB 84QmhCA89vOLUVZvE6arskHQjhH9E7nxr90a6ijDYer6vackcZw60k8j7OmHn9LBxSwu 18hFt9+yqUKB2PI1JeBsG8BoWsOu84eDifX0gXHnXxIhn6GZYpv8XFGzff5HTrpTDeE+ 7elg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0lgwAN4JLa+eJyUWPeSpGCyCJ0/V+S2YWU/Kqpi1gBQ=; b=JeU+DNz+MK+Lqf7WYW9HDzD3uoN0Hh/iPTWB+M73I1FldY9rK/lO0zYsf/vKYu2MHg 3ww4aYFt7wd7GxWLMD+JHNI0A37tVpe5/Ft7fGgacr5c9vjTQ2SHZlMNZ+pz2ltjpm9J SHi/AU1YA4tumjwQwlerFSToaHaSh75m6HoEpELzohITwIRL3D1lK/BrZyyGKkZMzGZh o7mOFAC3b6MOnmaOaI6aEVxq1iyTqsGMmZZOXSRSxl3ilPm9wBBPR3Otg32QavKHu/rW /tO55nmOd2oB3Z8t/QhTWltteqUngbPkniZDOd1OX2TD2ltyJgzzvB9kOpKWNt6KuVsP 4+Gw== X-Gm-Message-State: AOAM533K6DWSBASvXoXPNreTIbgrXlrMW7OIPeZw8W3eHPq+lha1g2Fk J1Fr4UMip1GMmqlC5KIirI7UpqIrW9xw1w== X-Received: by 2002:a17:90b:1102:: with SMTP id gi2mr8195486pjb.43.1631462296624; Sun, 12 Sep 2021 08:58:16 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id v13sm4439415pfm.16.2021.09.12.08.58.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Sep 2021 08:58:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 8/9] tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF Date: Sun, 12 Sep 2021 08:58:08 -0700 Message-Id: <20210912155809.196236-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210912155809.196236-1-richard.henderson@linaro.org> References: <20210912155809.196236-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Brad Smith Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Clang only sets _CALL_ELF for ppc64, and nothing at all to specify the ABI for ppc32. Make a good guess based on other symbols. Reported-by: Brad Smith Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 2202ce017e..5e1fac914a 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -25,9 +25,24 @@ #include "elf.h" #include "../tcg-pool.c.inc" -#if !defined _CALL_DARWIN && defined __APPLE__ -#define _CALL_DARWIN 1 -#endif +/* + * Standardize on the _CALL_FOO symbols used by GCC: + * Apple XCode does not define _CALL_DARWIN. + * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV (32-bit). + */ +#if !defined(_CALL_SYSV) && \ + !defined(_CALL_DARWIN) && \ + !defined(_CALL_AIX) && \ + !defined(_CALL_ELF) +# if defined(__APPLE__) +# define _CALL_DARWIN +# elif defined(__ELF__) && TCG_TARGET_REG_BITS == 32 +# define _CALL_SYSV +# else +# error "Unknown ABI" +# endif +#endif + #ifdef _CALL_SYSV # define TCG_TARGET_CALL_ALIGN_ARGS 1 #endif From patchwork Sun Sep 12 15:58:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 509498 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp3096697jai; Sun, 12 Sep 2021 09:03:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwWlEHPKUEKP+jD38cUncbpVSW/GFEszRE+DhFzeZyOZ83e2sLhkbf0ZcGNXc3SHBeovTTp X-Received: by 2002:a1c:4c14:: with SMTP id z20mr7253532wmf.82.1631462615506; Sun, 12 Sep 2021 09:03:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631462615; cv=none; d=google.com; s=arc-20160816; b=R0o3SMYvtniC0miFFf3ESRghDZpxUkHC+q81wA0oGml+8WDBv6AjdLMIp65tSzyRi9 XpJW5tv5oNMzkKnNIaC+MPiycz5mxZF7IT26b+z9gg2EGmRFzxaUcLe6L5NW60Fr4y3C tAVcflY1BlZxpvPOX1rFOwTpYBOcbw7UqERpmwRGqMrAwmENeUwpi3nXCmyAPoL1VhwV brrmoHwVu3OYNLyl4Xjp2h+AmEBW8bw9qNgK2UurstJsYd0FjZnICKsBs/wfI8+1VU9C VxVy3xpNHjNlIsHSkCUukERwLSaHw1V10rqmvZaGuUUR1eWlyCd+efgdO/KX/YLPqP4D bruw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Zk1Xc7v798/v3MVPLkwWlC7sy9W9XT/J+dwHkhEwhvw=; b=vM+hkSnnHUEluWxr+dOg5ItRiW9PGeP9jBif0x/jxPX/S3j8pAC7VfDn5/w4ONkuUd 4myfuyR5ufCLn7jR5ASkYey/OEnjJtYg1tbODksMLUKaW+NKU1p3a/hiN7bj2X1lPJqd u74NSG6+/5BANLpUx1aZyqFCGhygMBsaKyIKv4E0SmMMgapbQdRa5xEV/1zQmNbT0KIq gsJKD2hULHZuqx7pF8E4HAEXfvaBv57ZqTA0zGS5R1hviDulMx9AwtC7+hkOp9H91Jr7 4SWleM/JguobumgZbid1AYp50vl2OeRv4z9IGw/pE1zNVq8VEC/p8ymlRQg1hle/Il7+ gSVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nKS8ugSA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Ziviani" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Jose R. Ziviani" Commit 5e8892db93 fixed several function signatures but tcg_out_vec_op for arm is missing. It causes a build error on armv6 and armv7: tcg-target.c.inc:2718:42: error: argument 5 of type 'const TCGArg *' {aka 'const unsigned int *'} declared as a pointer [-Werror=array-parameter=] const TCGArg *args, const int *const_args) ~~~~~~~~~~~~~~^~~~ ../tcg/tcg.c:120:41: note: previously declared as an array 'const TCGArg[16]' {aka 'const unsigned int[16]'} const TCGArg args[TCG_MAX_OP_ARGS], ~~~~~~~~~~~~~~^~~~ Signed-off-by: Jose R. Ziviani Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210908185338.7927-1-jziviani@suse.de> Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 007ceee68e..e5b4f86841 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2715,7 +2715,8 @@ static const ARMInsn vec_cmp0_insn[16] = { static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGType type = vecl + TCG_TYPE_V64; unsigned q = vecl;