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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Ingo Molnar , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH 01/19] x86/cpufreatures: add AMD CPPC extension feature flag Date: Wed, 8 Sep 2021 22:59:43 +0800 Message-ID: <20210908150001.3702552-2-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210908150001.3702552-1-ray.huang@amd.com> References: <20210908150001.3702552-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f8407e99-1bb0-4470-3212-08d972d9749c X-MS-TrafficTypeDiagnostic: BL1PR12MB5143: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1079; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sYpfS/yh6Y0C13zxJKxTya3BBkte30C0phvrBlssQs3XK6y5+t+srMGiXsHxYsimEXnVRbHQfU5kpB0fmf3rAFoX/WfWuLezTypLQc59XDntKBreZN5tfPLP2MFzCNwQ0rGwz54AJyxgOyDEK+zLFeY5QSgJ6EKIeM0tQXAQk01hu0RwwDZTDI7SD9Sm0DeeMbwd9MV/8DUskJtyDm02sh0HcCy1drlhUS4vru4SFh4PcMDuV9o2QisKTD+Yo+J8v6PYi+I42gjrkQMCX821j386pqB3eQql2EgKgEJPlUMzk9fjP2bj/1ZovyFzt/gvL0Vr0dsBncyEPI8qUYZW7fx0RxOWEeEKSo3CSHNyZAyepldYy9N3XveuOJejadUDJxc1lUDCFgw1ntD1DCH9TIhrnUTnnM7nnGIZ1gMuzzzuc9qyOESHj1ZcSUj/8LR0n2uIiUUVj+nbpBzSjfszL0MxSUZUX9VukFgTDNQa05osVaeBAfHzBkF9N2X0m0s1Ur/OJJOt7DqeoNMQ5z4TWcj5TOMA/HGSuwpHz+WQt8M5VqJnM/6YYWFFeZJh46hO+RQcCYLQqPNhMQpe6m70dHBKEgPZ6X6X8lndFAFhy/imzjt+1q0lJjOfde3qJ5dMwNI1xPUDML0rwlsU58ZoBEM9FZEFsNG9u9/0BHca0lx63dLiQQ2H6WQnAIK/yC/3emm10UYT7JnzBFJLQyso/Vt23vOfPSF2zPRflKCVjAI= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(39860400002)(136003)(346002)(396003)(376002)(36840700001)(46966006)(2906002)(1076003)(54906003)(8936002)(110136005)(356005)(186003)(36756003)(86362001)(6666004)(26005)(316002)(16526019)(4326008)(81166007)(7696005)(4744005)(5660300002)(70206006)(2616005)(8676002)(82310400003)(47076005)(426003)(336012)(478600001)(36860700001)(82740400003)(70586007)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2021 15:00:53.7891 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f8407e99-1bb0-4470-3212-08d972d9749c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT011.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5143 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add Collaborative Processor Performance Control Extension feature flag for AMD processors. Signed-off-by: Huang Rui --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index d0ce5cfd3ac1..f7aea50e3371 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -313,6 +313,7 @@ #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ +#define X86_FEATURE_AMD_CPPC_EXT (13*32+27) /* Collaborative Processor Performance Control Extension */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ From patchwork Wed Sep 8 14:59:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 508159 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 620ECC433FE for ; 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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Ingo Molnar , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH 02/19] x86/msr: add AMD CPPC MSR definitions Date: Wed, 8 Sep 2021 22:59:44 +0800 Message-ID: <20210908150001.3702552-3-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210908150001.3702552-1-ray.huang@amd.com> References: <20210908150001.3702552-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 590a14db-34a9-4488-a22e-08d972d97caf X-MS-TrafficTypeDiagnostic: MWHPR12MB1504: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1107; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yA2JjAipvYTpw6Zzy3NIMWP+UxbMRXLKy0MF84nG9SN2NE0yM3xGZBERPp2TiIZCRqcGbO8kyKCK/1i5ZQIxJrC5/eiCRuwAGjyOJSUzBVNbK5y4nZbjG5SCBdhddO5XHQhZR+FgBxT/m9sZ9NgTiljpqKW/L0f1M0EoNVhsA/r52I2OOVtXj9ciHnTXoFCmFPAVReCyXG78b594e/7HXoIRHUv1tzhJO8VuIc+EJNi2FEhX6GFfVaI4MhD+L1YiUebzrkPd4WUCevUm2/UY3pe36wfJhVXXlJcFN50Zunyj1QM1IUCLX0ciExYeclvweobpo/e8SumxzHGY5K0quY0fzUbqUWw11clS7Wv3tinHrRPVucihgtvQWvudKloT+nekpkEeXyBdj0/UrjtU1ABVIeJQXQ6jFL/gQexv61yekzmieHXQnaug17/W0/X0xUxVCB5NYsimaK8omZmUG5Ane7ImOh+R7Tq5ttHNQnu/exupusci2iwcGMtdkCALnBEQmpxCF9k5Z0X6nqfzcpCVtlHVUItsG+MLmpY02pjh058eL0yrJjeZ9eDrA6Tl57XO1Bl+X2/wE/85a0rO3lCUEGDBA4QkqJbXMPFVYB/aV8JEYKJ0YsF2ISN6PvYg13Q+CtHqSkplm9ukxUKigub2sLVsNLC6oTpmtE63uq4VqGjdCWIsDEZv6RsolYKzN4Feg/rTgbjAI/y8phuw54nfxaPEW/kxGZx2//zUYTM= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(346002)(396003)(136003)(39860400002)(376002)(46966006)(36840700001)(47076005)(4326008)(16526019)(5660300002)(186003)(8676002)(7696005)(426003)(26005)(336012)(82740400003)(316002)(110136005)(70586007)(70206006)(54906003)(81166007)(2906002)(36756003)(36860700001)(1076003)(356005)(478600001)(82310400003)(6666004)(86362001)(8936002)(2616005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2021 15:01:07.3331 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 590a14db-34a9-4488-a22e-08d972d97caf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1504 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org AMD CPPC (Collaborative Processor Performance Control) function uses MSR registers to manage the performance hints. So add the MSR register macro here. Signed-off-by: Huang Rui --- arch/x86/include/asm/msr-index.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index a7c413432b33..ce42e15cf303 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -486,6 +486,23 @@ #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f +/* AMD Collaborative Processor Performance Control MSRs */ +#define MSR_AMD_CPPC_CAP1 0xc00102b0 +#define MSR_AMD_CPPC_ENABLE 0xc00102b1 +#define MSR_AMD_CPPC_CAP2 0xc00102b2 +#define MSR_AMD_CPPC_REQ 0xc00102b3 +#define MSR_AMD_CPPC_STATUS 0xc00102b4 + +#define CAP1_LOWEST_PERF(x) (((x) >> 0) & 0xff) +#define CAP1_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) +#define CAP1_NOMINAL_PERF(x) (((x) >> 16) & 0xff) +#define CAP1_HIGHEST_PERF(x) (((x) >> 24) & 0xff) + +#define REQ_MAX_PERF(x) (((x) & 0xff) << 0) +#define REQ_MIN_PERF(x) (((x) & 0xff) << 8) +#define REQ_DES_PERF(x) (((x) & 0xff) << 16) +#define REQ_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) + /* Fam 17h MSRs */ #define MSR_F17H_IRPERF 0xc00000e9 From patchwork Wed Sep 8 14:59:47 2021 Content-Type: text/plain; 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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Ingo Molnar , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH 05/19] cpufreq: amd: add fast switch function for amd-pstate module Date: Wed, 8 Sep 2021 22:59:47 +0800 Message-ID: <20210908150001.3702552-6-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210908150001.3702552-1-ray.huang@amd.com> References: <20210908150001.3702552-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9751629c-aa0a-4fae-86d9-08d972d97f38 X-MS-TrafficTypeDiagnostic: MWHPR1201MB0143: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2803; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9Nr+Ib6p6gSYR610owIZbVKm1+izZ6SfCGolmTGk7J3VSTHwFRBeRLzNJfbW6XBLEQAn46xABp4dv3Z+e1D3aCf7HeNZOTkoJVxvQ3e/+Esg2iYVd2czC0FJ3cuGJTVGjeRIlp0cYGqSAoUggGmUX0AwAdRw8j0YHwTjzrFrxmzcjLpjNHdGadTMqhhmaD8YqR2uB/pRHTlEbumMLezyBJmIRYktxAQBl/U96/dKRUaiXaex99En3m75t6iug5xA4r8bNlGxddvz4PEy4fphbzxunC7JW6AOciJ2zPRMkjXMhvT755rxwkvUJeqfkX0aEre9l+EdcvDd4LoFaG59YZ+ExuIZx2g7Ac9iRLwpoWKU2tj7fJWSGQ6lWd11bvo30zuohEqi02+YDsJHdgcjxT71ZW1AeyldnymP6FxFlGftF0ENVGJ3T3olqwJCW4CGTztiCkwJQoLEiCRZzzjtuFSMm7+1SSay7vE3AE2BNk1zJyPsutWSrYd+lTP8pO0krTr3vMBwOS/bZSret8DXJEanR34/p5mvb7IodDDBnHHZDKJ2SyvcqecgSNFJ9QCzZoDryX4svUxZ4YpF94CJxNQE4k6vIiJDNcMljBU8n3TbW+tvyFSbtkS15XwupX2AIbgmoSvr/RB5HPXIBAvIrPAcdrNCnGKzAOIieoDIZvdvVLBWp4uVN5j+VgZcjvnAnvVtsg4r/2ugNrHctmVWI+CBAUuPIh4sQdcLdPYlEGw= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(83380400001)(36860700001)(6666004)(70206006)(70586007)(2616005)(4326008)(81166007)(36756003)(82310400003)(47076005)(16526019)(2906002)(316002)(186003)(54906003)(110136005)(7696005)(8936002)(86362001)(5660300002)(26005)(508600001)(336012)(356005)(8676002)(1076003)(426003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2021 15:01:11.5847 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9751629c-aa0a-4fae-86d9-08d972d97f38 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB0143 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce the fast switch function for amd-pstate module on the AMD processors which support the full MSR register control. It's able to decrease the lattency on interrupt context. Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 64 ++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 4c9c9bf1d72b..32b4f6d79783 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -212,6 +212,66 @@ static int amd_pstate_target(struct cpufreq_policy *policy, return ret; } +static void amd_pstate_adjust_perf(unsigned int cpu, + unsigned long min_perf, + unsigned long target_perf, + unsigned long capacity) +{ + unsigned long amd_max_perf, amd_min_perf, amd_des_perf, + amd_cap_perf, lowest_nonlinear_perf; + struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); + struct amd_cpudata *cpudata = policy->driver_data; + + amd_cap_perf = READ_ONCE(cpudata->highest_perf); + lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); + + if (target_perf < capacity) + amd_des_perf = DIV_ROUND_UP(amd_cap_perf * target_perf, + capacity); + + amd_min_perf = READ_ONCE(cpudata->highest_perf); + if (min_perf < capacity) + amd_min_perf = DIV_ROUND_UP(amd_cap_perf * min_perf, capacity); + + if (amd_min_perf < lowest_nonlinear_perf) + amd_min_perf = lowest_nonlinear_perf; + + amd_max_perf = amd_cap_perf; + if (amd_max_perf < amd_min_perf) + amd_max_perf = amd_min_perf; + + amd_des_perf = clamp_t(unsigned long, amd_des_perf, + amd_min_perf, amd_max_perf); + + amd_pstate_update(cpudata, amd_min_perf, amd_des_perf, + amd_max_perf, true); +} + +static unsigned int amd_pstate_fast_switch(struct cpufreq_policy *policy, + unsigned int target_freq) +{ + u64 ratio; + struct amd_cpudata *cpudata = policy->driver_data; + unsigned long amd_max_perf, amd_min_perf, amd_des_perf, nominal_perf; + + if (!cpudata->max_freq) + return -ENODEV; + + amd_max_perf = READ_ONCE(cpudata->highest_perf); + amd_min_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); + + amd_des_perf = DIV_ROUND_UP(target_freq * amd_max_perf, + cpudata->max_freq); + + amd_pstate_update(cpudata, amd_min_perf, amd_des_perf, + amd_max_perf, true); + + nominal_perf = READ_ONCE(cpudata->nominal_perf); + ratio = div_u64(amd_des_perf << SCHED_CAPACITY_SHIFT, nominal_perf); + + return cpudata->nominal_freq * ratio >> SCHED_CAPACITY_SHIFT; +} + static int amd_get_min_freq(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; @@ -356,6 +416,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) /* It will be updated by governor */ policy->cur = policy->cpuinfo.min_freq; + policy->fast_switch_possible = true; + ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], FREQ_QOS_MIN, policy->cpuinfo.min_freq); if (ret < 0) { @@ -408,6 +470,8 @@ static struct cpufreq_driver amd_pstate_driver = { .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, .verify = amd_pstate_verify, .target = amd_pstate_target, + .fast_switch = amd_pstate_fast_switch, + .adjust_perf = amd_pstate_adjust_perf, .init = amd_pstate_cpu_init, .exit = amd_pstate_cpu_exit, .name = "amd-pstate", From patchwork Wed Sep 8 14:59:48 2021 Content-Type: text/plain; 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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Ingo Molnar , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH 06/19] cpufreq: amd: add acpi cppc function as the backend for legacy processors Date: Wed, 8 Sep 2021 22:59:48 +0800 Message-ID: <20210908150001.3702552-7-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210908150001.3702552-1-ray.huang@amd.com> References: <20210908150001.3702552-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 219fec5b-6fad-4734-3d6a-08d972d980ad X-MS-TrafficTypeDiagnostic: CH2PR12MB4860: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3383; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CDaNJZnvnMbm/XMsYvBAGMi3AXlNkUJlkKevn8MhAXdFf13xXFw2Qg4BBghTh2sD20RbkJy8dLRzWexKDgYRsztQ8MUvGI1a3iVILds6JJtd2I+zzJY2Hw//tkPscEwPJ0pMn/42tCdy/NWgQmmnh+88aTzyY2mUl7/g5XhVwSqjnzQo7ywEkmhXIXa9SDrH/68cHDQrxh40IoQKpBdcCA3I93qSH3CooBKaW6BRJYnUqL2KcRx9H9NdCc50aECkEBJzJUE3q6bUrLhgYhrmiJwvsVno3muoFGj4Ycm1of2AIs+hZ9ES+1oi6P1sG4eTLG7Df1CTl81ZsDg7IPaql+pwFEjx959XfvrZzhCOEAvUPx9ScmjfoSUzdNzm4aQiL0X79RG4YUrIM+K/fCchU76KqL5tMANERzDD2tCtl4CalLNMjs7bgkQ12w5iojNmrUILd/xMAM17lg8t5DtMgFMAAddqAgk4+PdI/jHsRw3EaEmEhcPEH/Nn9RC6oFm7SaVFKVulOYhmUK81Bo5LH9PemyBeJzf4lK3aPx/IM/U/hP9fKQro3j/22tDKeRFY2/UAvUt+RHttnQcVmrqCb5HZvgslmqNzSqzy+auF4UpoupzTkUjn2puSUDhS9ApgEiEeKeyJUS0iVs1IEZZZIKN/ZiFRViDEcbDHXT9XqXQa5WV04jBlgDWhh3InmIQ6vHppqx3ldo55+oXIKTSJXtny5PU8cHSL2Cidc/BTBu4= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(47076005)(70206006)(316002)(8676002)(7696005)(81166007)(54906003)(336012)(356005)(8936002)(426003)(110136005)(83380400001)(2616005)(4326008)(86362001)(508600001)(36756003)(186003)(5660300002)(1076003)(16526019)(26005)(2906002)(70586007)(82310400003)(6666004)(36860700001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2021 15:01:14.0303 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 219fec5b-6fad-4734-3d6a-08d972d980ad X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4860 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org In some old Zen based processors, they are using the shared memory that exposed from ACPI SBIOS. Signed-off-by: Jinzhou Su Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 63 ++++++++++++++++++++++++++++++++---- 1 file changed, 57 insertions(+), 6 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 32b4f6d79783..a46cd5dd9f7c 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -82,6 +82,19 @@ static inline int pstate_enable(bool enable) return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable ? 1 : 0); } +static int cppc_enable(bool enable) +{ + int cpu, ret = 0; + + for_each_online_cpu(cpu) { + ret = cppc_set_enable(cpu, enable ? 1 : 0); + if (ret) + return ret; + } + + return ret; +} + static int amd_pstate_enable(struct amd_pstate_perf_funcs *funcs, bool enable) { @@ -113,6 +126,24 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) return 0; } +static int cppc_init_perf(struct amd_cpudata *cpudata) +{ + struct cppc_perf_caps cppc_perf; + + int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); + if (ret) + return ret; + + WRITE_ONCE(cpudata->highest_perf, amd_get_highest_perf()); + + WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); + WRITE_ONCE(cpudata->lowest_nonlinear_perf, + cppc_perf.lowest_nonlinear_perf); + WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf); + + return 0; +} + static int amd_pstate_init_perf(struct amd_cpudata *cpudata) { struct amd_pstate_perf_funcs *funcs = cpufreq_get_driver_data(); @@ -134,6 +165,19 @@ static void pstate_update_perf(struct amd_cpudata *cpudata, READ_ONCE(cpudata->cppc_req_cached)); } +static void cppc_update_perf(struct amd_cpudata *cpudata, + u32 min_perf, u32 des_perf, + u32 max_perf, bool fast_switch) +{ + struct cppc_perf_ctrls perf_ctrls; + + perf_ctrls.max_perf = max_perf; + perf_ctrls.min_perf = min_perf; + perf_ctrls.desired_perf = des_perf; + + cppc_set_perf(cpudata->cpu, &perf_ctrls); +} + static int amd_pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch) @@ -370,6 +414,12 @@ static struct amd_pstate_perf_funcs pstate_funcs = { .update_perf = pstate_update_perf, }; +static struct amd_pstate_perf_funcs cppc_funcs = { + .enable = cppc_enable, + .init_perf = cppc_init_perf, + .update_perf = cppc_update_perf, +}; + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -416,7 +466,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) /* It will be updated by governor */ policy->cur = policy->cpuinfo.min_freq; - policy->fast_switch_possible = true; + if (boot_cpu_has(X86_FEATURE_AMD_CPPC_EXT)) + policy->fast_switch_possible = true; ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], FREQ_QOS_MIN, policy->cpuinfo.min_freq); @@ -471,7 +522,6 @@ static struct cpufreq_driver amd_pstate_driver = { .verify = amd_pstate_verify, .target = amd_pstate_target, .fast_switch = amd_pstate_fast_switch, - .adjust_perf = amd_pstate_adjust_perf, .init = amd_pstate_cpu_init, .exit = amd_pstate_cpu_exit, .name = "amd-pstate", @@ -496,14 +546,15 @@ static int __init amd_pstate_init(void) return -EEXIST; /* capability check */ - if (!boot_cpu_has(X86_FEATURE_AMD_CPPC_EXT)) { + if (boot_cpu_has(X86_FEATURE_AMD_CPPC_EXT)) { pr_debug("%s, AMD CPPC extension functionality is supported\n", __func__); - return -ENODEV; + funcs = &pstate_funcs; + amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf; + } else { + funcs = &cppc_funcs; } - funcs = &pstate_funcs; - /* enable amd pstate feature */ ret = amd_pstate_enable(funcs, true); if (ret) { From patchwork Wed Sep 8 14:59:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 508155 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AF68C4332F for ; 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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Ingo Molnar , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH 09/19] cpufreq: amd: add amd-pstate checking support check attribute Date: Wed, 8 Sep 2021 22:59:51 +0800 Message-ID: <20210908150001.3702552-10-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210908150001.3702552-1-ray.huang@amd.com> References: <20210908150001.3702552-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c2d8abba-6be8-4114-35ea-08d972d98b95 X-MS-TrafficTypeDiagnostic: MWHPR12MB1487: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:541; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: KCcM4NisxY06vO3FwcUSs9IGFV5pLduZVASogN40cP9LLS9LqlIw3gXBOBCO8SVIrbzO1ZJCRFVLHpP9tjDssHRi2m2c9p1mN6X/vslnKSFutE/Qz38XukZwViVXLCZ8wB5GYlKWN/ZW6sC89GSYmSAYAxX0IWiNfM7/vAIaHo2KPOtCeXx9BPJU4B6cCe9A8lYJ0ogb3P1MRnB1Ow8ZtL9a+e02G02NZ0G3QnCI2vc1LAr+R2qxgzz36Dc3l6BZQhCztUb/mj5CqFDH30uSHgPkimnHR4WD2xH+1+7XtbdIao4w6Zx/3uG9aBfkXEAXPmwpf6fYlCUstjPwEFVu7vgz0soKN5gHWixd/LE+BSzVoZ34QERXZNEl+5y2yHiDhbjxjj4p8Pqc3sMfXNqIF26BfUW3GoI9oWc+2n9kwixHwMltFrWjjusWLlpW5xyhIJhG3gEw2UEYNd1YA0x63HaqF7ZYvgOITaZjPK+lMuneVnXaLjtOWtS1Z+nWEs/DLVwKU/qswzJBYgLB6d7hjC6NrBMs1Zwa94re7wmNURot8tNJ/Z0EUIjsP/9ZFSU+XlYQJTAGeuqNBq1HVVClhBLmsSogIDurICC8LEBwEdredxuSupmHzOKqIS7ptW0GAXyFeUtaeISyQ5zbriUaTzQiGSkNtp5jv97sbLzSmS6FuWK9oHp3tqczAH1Or4rbwiIZXWZzT/s5NB9KfFZ45BVhSO57lfuqBxWJeFl/YE4= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(346002)(136003)(376002)(39860400002)(396003)(36840700001)(46966006)(16526019)(186003)(70586007)(86362001)(5660300002)(478600001)(82310400003)(8676002)(70206006)(36756003)(82740400003)(110136005)(8936002)(316002)(356005)(336012)(7696005)(1076003)(81166007)(47076005)(2906002)(54906003)(6666004)(26005)(83380400001)(426003)(36860700001)(2616005)(4326008)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2021 15:01:32.3368 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c2d8abba-6be8-4114-35ea-08d972d98b95 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT057.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1487 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The amd-pstate hardware support check will be needed by cpupower to know whether amd-pstate is enabled and supported. Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 67a9a117f524..48dedd5af101 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -577,6 +577,19 @@ static int amd_pstate_cpu_exit(struct cpufreq_policy *policy) return 0; } +static ssize_t show_is_amd_pstate_enabled(struct cpufreq_policy *policy, + char *buf) +{ + return sprintf(&buf[0], "%d\n", acpi_cpc_valid() ? 1 : 0); +} + +cpufreq_freq_attr_ro(is_amd_pstate_enabled); + +static struct freq_attr *amd_pstate_attr[] = { + &is_amd_pstate_enabled, + NULL, +}; + static struct cpufreq_driver amd_pstate_driver = { .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, .verify = amd_pstate_verify, @@ -586,6 +599,7 @@ static struct cpufreq_driver amd_pstate_driver = { .exit = amd_pstate_cpu_exit, .set_boost = amd_pstate_set_boost, .name = "amd-pstate", + .attr = amd_pstate_attr, }; static int __init amd_pstate_init(void) From patchwork Wed Sep 8 14:59:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 508156 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB116C433EF for ; Wed, 8 Sep 2021 15:01:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CF775611B0 for ; Wed, 8 Sep 2021 15:01:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352054AbhIHPCu (ORCPT ); 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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Ingo Molnar , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH 10/19] cpufreq: amd: add amd-pstate frequencies attributes Date: Wed, 8 Sep 2021 22:59:52 +0800 Message-ID: <20210908150001.3702552-11-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210908150001.3702552-1-ray.huang@amd.com> References: <20210908150001.3702552-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f9dabfd4-399a-4e9f-ff88-08d972d98bf2 X-MS-TrafficTypeDiagnostic: SJ0PR12MB5405: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:497; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8S+HLIRajyTSN1U6YMJa7dk9yJaq1l4aCdCXoRULHxnM+wNQPs3H1iG0bUz1U0o6UoRzLOpMoxab4FVjOGkxaEoDW7kVbElalLhnnges7vljzjsWIBhETrejgxB8TBCCIdIGBH/+QXURHtpVz1bPvh9GU9l/J3tJ5AJOEMdfNvScMDO9oe/V67h2Z/NJA99ifOODU311FblQeq5dqOrb5XSEwPRBvW/9KLqbmf0HDUlamMeBFz18+IPEttgD2IlhjMofe55iJUyK/fr9x5IZVPm+DHO7AQ1GJokulYN6cQ0R4OhjExFOVwQ151jrYeqnBfgQ5jVGmJGk2uef3HN055uIi+RkfsY/++DSQdNatIh/P/WZQEoCck5p+85/edm8iGWVHISXbXlfm5eDHUVt9uJXRlq6A+jZrBeSpFZRb0C9Ol/CH1TTmy7CppS6iTccqFyTq2/c04SPeMrO2X7BD+NqQF4BYzNvYDKF7JXuuujyBoEUerurXsKM53tLicDBphtUH4wj/GjI4bQNCE/j4li2RakUbW/M0FcrMdmUl5RAKlS1gNivR7J0zBrJOwBquB63RgTC5JI9dmpQxxaNvingrdqeJuBtxVIel5CPpadnQTitDjcNzaBWM0XTvsR2PxJ/gFDrZueozi8BCvrj0qMhSAihMEbOspkH6YFTNuunqs6BsO1Pl5BsslyXxW5nz1pwqtFMXWVlMisz28PIHzvS6CI/GWezPYjGrniIEsE= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(136003)(396003)(376002)(346002)(39860400002)(46966006)(36840700001)(26005)(36860700001)(47076005)(426003)(2616005)(1076003)(4326008)(82740400003)(70586007)(82310400003)(5660300002)(86362001)(186003)(83380400001)(336012)(81166007)(70206006)(478600001)(8936002)(6666004)(7696005)(8676002)(2906002)(110136005)(356005)(54906003)(36756003)(316002)(16526019)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2021 15:01:32.9524 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9dabfd4-399a-4e9f-ff88-08d972d98bf2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT057.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5405 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce sysfs attributes to get the different level processor frequencies. Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 80 +++++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 48dedd5af101..3c727a22cb69 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -577,16 +577,94 @@ static int amd_pstate_cpu_exit(struct cpufreq_policy *policy) return 0; } -static ssize_t show_is_amd_pstate_enabled(struct cpufreq_policy *policy, +/* Sysfs attributes */ + +static ssize_t show_amd_pstate_max_freq(struct cpufreq_policy *policy, char *buf) +{ + int ret = 0, max_freq; + struct amd_cpudata *cpudata; + + cpudata = policy->driver_data; + + max_freq = amd_get_max_freq(cpudata); + if (max_freq < 0) + return max_freq; + + ret += sprintf(&buf[ret], "%u\n", max_freq); + + return ret; +} + +static ssize_t show_amd_pstate_nominal_freq(struct cpufreq_policy *policy, + char *buf) +{ + int ret = 0, nominal_freq; + struct amd_cpudata *cpudata; + + cpudata = policy->driver_data; + + nominal_freq = amd_get_nominal_freq(cpudata); + if (nominal_freq < 0) + return nominal_freq; + + ret += sprintf(&buf[ret], "%u\n", nominal_freq); + + return ret; +} + +static ssize_t +show_amd_pstate_lowest_nonlinear_freq(struct cpufreq_policy *policy, char *buf) +{ + int ret = 0, freq; + struct amd_cpudata *cpudata; + + cpudata = policy->driver_data; + + freq = amd_get_lowest_nonlinear_freq(cpudata); + if (freq < 0) + return freq; + + ret += sprintf(&buf[ret], "%u\n", freq); + + return ret; +} + +static ssize_t show_amd_pstate_min_freq(struct cpufreq_policy *policy, char *buf) +{ + int ret = 0; + int freq; + struct amd_cpudata *cpudata; + + cpudata = policy->driver_data; + + freq = amd_get_min_freq(cpudata); + if (freq < 0) + return freq; + + ret += sprintf(&buf[ret], "%u\n", freq); + + return ret; +} + +static ssize_t show_is_amd_pstate_enabled(struct cpufreq_policy *policy, + char *buf) { return sprintf(&buf[0], "%d\n", acpi_cpc_valid() ? 1 : 0); } cpufreq_freq_attr_ro(is_amd_pstate_enabled); +cpufreq_freq_attr_ro(amd_pstate_max_freq); +cpufreq_freq_attr_ro(amd_pstate_nominal_freq); +cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); +cpufreq_freq_attr_ro(amd_pstate_min_freq); static struct freq_attr *amd_pstate_attr[] = { &is_amd_pstate_enabled, + &amd_pstate_max_freq, + &amd_pstate_nominal_freq, + &amd_pstate_lowest_nonlinear_freq, + &amd_pstate_min_freq, NULL, }; From patchwork Wed Sep 8 14:59:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 508154 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C344BC43219 for ; Wed, 8 Sep 2021 15:01:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 95AFF611ED for ; Wed, 8 Sep 2021 15:01:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352028AbhIHPCx (ORCPT ); Wed, 8 Sep 2021 11:02:53 -0400 Received: from mail-bn8nam11on2058.outbound.protection.outlook.com ([40.107.236.58]:57760 "EHLO NAM11-BN8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1351981AbhIHPCu (ORCPT ); Wed, 8 Sep 2021 11:02:50 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=OIqY9vFJvbScoEtyQocYD2SN6iRqUeSPZoHn+GEzJmoof/lwydleSSc/oTb/6ByMI1gYYKegx5kZynL9V0Icq1d+xDaA/dTwex/3gKxPN9pTi2eZGwUbneb1gNLk3ePPA0C8UeS3qi/68y8z7HI9wmGIM/nYZ6kbTM2vqkbzTdtDRzZQNSF9XE7tr1u0VNY9t7I1D3Y3SR+EAL524j+4wXIWGfNoYeTc2DLHzwT2fQIsiMVSv5uBUJRYOWL12dJ9MK88EvlI9MkLgbdbOLO8VSsHxMO4ubk1qKXOuIpkF+a+XzTlEdRVz206ocnkar1tT7SHJuOOkrpkTPuzkBBIkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=ccvgLGXMmqJ33bBs2A5cCQooNFOumTwff+lvc6oq7AU=; b=fFM39dwTAHUTq+0Y1AdwCNw8wQT5B+prUIJlYlm9mYe3B/PXWDS8REalcgke3LwmHv1tmxx6KyIkNEo06DdU0+/67RNpPavyw8O7kIf4b3yi22D0NAJCSnNIPglcbreV2ozlf9ECGb2FNtku/9Lzs2RnIvkIQCChRoXO9kID9JyumbJTm6pMaHtpzH1YLmLjUmxtNU0UYINfH3es0ewI37keAQy+J+rMaWgGB4btRavpx13j0FIzviprD+3BGDg66dTlD43d7N8e7F9zXCi9NNRVMi8PS4rTANfz2LY7zuoxvisr4I1U6G8oRaM40JngUSPoLYAIHDZiF5aeCZ75/w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ccvgLGXMmqJ33bBs2A5cCQooNFOumTwff+lvc6oq7AU=; b=4LHlLQKQMGkcH2KtT4PXHrelUFBS85OZUB/mpGU0Y803TS3nBiwHC24IMhgyTMKMVnpt+2nideR4Y03hvE4HlrV6NQZhH3wQGOpd+p6P1E+ZCODEcP+ZkH354V9yzp0Vp1GbVF77G1rcYt4jsh/ei/u/t9qX8Nk39cKmgPs4FOs= Received: from MWHPR10CA0005.namprd10.prod.outlook.com (2603:10b6:301::15) by BL1PR12MB5157.namprd12.prod.outlook.com (2603:10b6:208:308::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4478.21; Wed, 8 Sep 2021 15:01:41 +0000 Received: from CO1NAM11FT057.eop-nam11.prod.protection.outlook.com (2603:10b6:301:0:cafe::52) by MWHPR10CA0005.outlook.office365.com (2603:10b6:301::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4500.14 via Frontend Transport; Wed, 8 Sep 2021 15:01:40 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; intel.com; dkim=none (message not signed) header.d=none; intel.com; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT057.mail.protection.outlook.com (10.13.174.205) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4500.14 via Frontend Transport; Wed, 8 Sep 2021 15:01:40 +0000 Received: from hr-amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.8; Wed, 8 Sep 2021 10:01:35 -0500 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Ingo Molnar , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH 13/19] cpupower: add the function to check amd-pstate enabled Date: Wed, 8 Sep 2021 22:59:55 +0800 Message-ID: <20210908150001.3702552-14-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210908150001.3702552-1-ray.huang@amd.com> References: <20210908150001.3702552-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9de47605-7254-4efa-5d1f-08d972d99059 X-MS-TrafficTypeDiagnostic: BL1PR12MB5157: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:626; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zRa5wpkVX2HhFF3y7vmWOgs6gXdVJblk//GnuuuJ1pac1Q7fFysD4LN5J9rIZkGhrJLUYqViPjHeYykT61Q8iDih7v4Q+SKHP54uuwoKJKYeZPTKe/4EFkv3WvY4J8xlvGgESxKDrt+p/etiqRkrtq0bGBLHg3ZhuMUYrqGmIkD0b5eJo/voqmLxd4r3ivlrjipSJHgqb7GZb2xIRSv0yLTslMQYxVCXeHV1nH5mK/1kOAWhUNDNEU1N5XYXVCZ5GgchneeN8WxynLcaxdlLYs+WtWXaFKMym5DJH7KlVxP3SSW8v1+XJhF31Nc9DyDKQVIc/XdDMiP/hA1ahZR94tMx/A3m6Ra+bgKnWqB7DBaWNG6UVUsDNOuTdCOZNvl9/3Hc6WUeU+Y/D/j1wCzxghERV759XsCDESlixYQSBqYg96/vmwGCSkxGwWhgsgZqWFugQcZyS/Vbc3phHnvA15V13kylq/RCZIw1zkzTG31Zm4Kxlu2EtPOxpZ6HkPobPMh78gP9bkrON48gTUMuL1qlH0sBpCHwvZaw10+UaWozLxuzGr0eHQsptTVJU9BWGBuM051NA7B6NVpRc+BKfOzeFLhwB8dAhEGfjoAGZa8WCujnajAxcTJEa4+lWJspjphI8SFWOpKVruMgp+FdH0dvwOE6JB/2xL/SGYbQT9RMt/e1WRJrmczLYgg8wxxnlHgK3CeN4OztuCQDWYi5jPgNaiMVLL4V0RXn9Hyko5A= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(376002)(39860400002)(136003)(346002)(396003)(36840700001)(46966006)(82740400003)(356005)(81166007)(4326008)(186003)(426003)(1076003)(70586007)(36756003)(2616005)(36860700001)(86362001)(47076005)(6666004)(2906002)(5660300002)(26005)(478600001)(8676002)(8936002)(16526019)(7696005)(70206006)(110136005)(316002)(336012)(82310400003)(54906003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2021 15:01:40.3352 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9de47605-7254-4efa-5d1f-08d972d99059 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT057.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5157 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce the cpupower_amd_pstate_enabled() to check whether the kernel mode enables amd-pstate. Signed-off-by: Huang Rui --- tools/power/cpupower/utils/helpers/helpers.h | 5 +++++ tools/power/cpupower/utils/helpers/misc.c | 20 ++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/tools/power/cpupower/utils/helpers/helpers.h b/tools/power/cpupower/utils/helpers/helpers.h index b4813efdfb00..eb43c14d1728 100644 --- a/tools/power/cpupower/utils/helpers/helpers.h +++ b/tools/power/cpupower/utils/helpers/helpers.h @@ -136,6 +136,11 @@ extern int decode_pstates(unsigned int cpu, int boost_states, extern int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active, int * states); + +/* AMD PSTATE enabling **************************/ + +extern unsigned long cpupower_amd_pstate_enabled(unsigned int cpu); + /* * CPUID functions returning a single datum */ diff --git a/tools/power/cpupower/utils/helpers/misc.c b/tools/power/cpupower/utils/helpers/misc.c index fc6e34511721..07d80775fb68 100644 --- a/tools/power/cpupower/utils/helpers/misc.c +++ b/tools/power/cpupower/utils/helpers/misc.c @@ -83,6 +83,26 @@ int cpupower_intel_set_perf_bias(unsigned int cpu, unsigned int val) return 0; } +unsigned long cpupower_amd_pstate_enabled(unsigned int cpu) +{ + char linebuf[MAX_LINE_LEN]; + char path[SYSFS_PATH_MAX]; + unsigned long val; + char *endp; + + snprintf(path, sizeof(path), + PATH_TO_CPU "cpu%u/cpufreq/is_amd_pstate_enabled", cpu); + + if (cpupower_read_sysfs(path, linebuf, MAX_LINE_LEN) == 0) + return 0; + + val = strtoul(linebuf, &endp, 0); + if (endp == linebuf || errno == ERANGE) + return 0; + + return val; +} + #endif /* #if defined(__i386__) || defined(__x86_64__) */ /* get_cpustate From patchwork Wed Sep 8 14:59:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 508153 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3241C433EF for ; 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Signed-off-by: Huang Rui --- tools/power/cpupower/lib/cpufreq.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/tools/power/cpupower/lib/cpufreq.c b/tools/power/cpupower/lib/cpufreq.c index c3b56db8b921..3f92ddadaad2 100644 --- a/tools/power/cpupower/lib/cpufreq.c +++ b/tools/power/cpupower/lib/cpufreq.c @@ -69,6 +69,14 @@ enum cpufreq_value { SCALING_MIN_FREQ, SCALING_MAX_FREQ, STATS_NUM_TRANSITIONS, + AMD_PSTATE_HIGHEST_PERF, + AMD_PSTATE_NOMINAL_PERF, + AMD_PSTATE_LOWEST_NONLINEAR_PERF, + AMD_PSTATE_LOWEST_PERF, + AMD_PSTATE_MAX_FREQ, + AMD_PSTATE_NOMINAL_FREQ, + AMD_PSTATE_LOWEST_NONLINEAR_FREQ, + AMD_PSTATE_MIN_FREQ, MAX_CPUFREQ_VALUE_READ_FILES }; @@ -80,7 +88,15 @@ static const char *cpufreq_value_files[MAX_CPUFREQ_VALUE_READ_FILES] = { [SCALING_CUR_FREQ] = "scaling_cur_freq", [SCALING_MIN_FREQ] = "scaling_min_freq", [SCALING_MAX_FREQ] = "scaling_max_freq", - [STATS_NUM_TRANSITIONS] = "stats/total_trans" + [STATS_NUM_TRANSITIONS] = "stats/total_trans", + [AMD_PSTATE_HIGHEST_PERF] = "amd_pstate_highest_perf", + [AMD_PSTATE_NOMINAL_PERF] = "amd_pstate_nominal_perf", + [AMD_PSTATE_LOWEST_NONLINEAR_PERF] = "amd_pstate_lowest_nonlinear_perf", + [AMD_PSTATE_LOWEST_PERF] = "amd_pstate_lowest_perf", + [AMD_PSTATE_MAX_FREQ] = "amd_pstate_max_freq", + [AMD_PSTATE_NOMINAL_FREQ] = "amd_pstate_nominal_freq", + [AMD_PSTATE_LOWEST_NONLINEAR_FREQ] = "amd_pstate_lowest_nonlinear_freq", + [AMD_PSTATE_MIN_FREQ] = "amd_pstate_min_freq" }; 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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Ingo Molnar , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH 17/19] cpupower: add amd-pstate get data function to query the info Date: Wed, 8 Sep 2021 22:59:59 +0800 Message-ID: <20210908150001.3702552-18-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210908150001.3702552-1-ray.huang@amd.com> References: <20210908150001.3702552-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 47733560-7453-4dda-79d2-08d972d99de1 X-MS-TrafficTypeDiagnostic: BL0PR12MB4754: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:849; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: pRdqJaEks2HQ0O26Ttkads+ODJPmtNz/Xz4oATz6I6MniZTkg8d/YMI9qZM4PF9r5fSG16KRH8UBE05kNjjChkckLM8PmZ/062Jdn3mpb9a3LM4jwoKrbJF/7y24qZkXlGkHX8J34MU62X5tKVvHVIDIj8r2ln2s0heshkSSuG02+w4/IYP5oQhsCvm35gHEB/SWPIL/DQvmhfWB5tV0BdOkfvzbJY7ZdzLhT2fUm9RGx0JChvOGdrNdJ31hmTnf9lF4X5ArBES/M26ZgtQvFpE2L/LOsS7KS3VZySYbhKZptS98NEr4LX5OCwRqkDeRjLdNZ1wl6Mgu1NZpS8nUoonUxzlMHiS//3OOUOOG+urPup6iw6xqSYnkzrJgvgzDaC7d1Wx/2tK4f1jEQ+VjhQclwwmsYAJ5tPja/zUD2tDyQfzO1rL7c7hiT8fG5nOSdQ+zGjLliDC+af78+Aw0BQi38hGQXEKSGJAxgReKoDJ8yWJn7voN98YPNcDlSPM/5/ImMtiFUP+47OJYDknRU5EM4jMzB2o/8p65y276IZ3sy8QBBRIHvFCnkc6J678HqqwU9tXfTK4HV6JqAqeHaBw6kTAvNLBMPaX44mQt5vGut8AHRlsPuQdlQL1gkVcWQJWEX9oEUMU1I9pIFuwqPvZMWZ3QQVoiVgXenVu9h6rW6cg+ntGvfUZsbMZVPQAnAe/2QrzFr6dXbxqH1+iGXnP2mES/77yO4RtjpVbSKbY= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(136003)(396003)(376002)(39860400002)(346002)(46966006)(36840700001)(4326008)(110136005)(316002)(70206006)(86362001)(336012)(83380400001)(36756003)(47076005)(81166007)(82740400003)(356005)(70586007)(2906002)(54906003)(426003)(5660300002)(8936002)(186003)(26005)(36860700001)(82310400003)(2616005)(1076003)(478600001)(7696005)(16526019)(8676002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2021 15:02:03.0286 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 47733560-7453-4dda-79d2-08d972d99de1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4754 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Frequency-info needs an interface to query the current amd-pstate data. Signed-off-by: Huang Rui --- tools/power/cpupower/lib/cpufreq.c | 6 ++++++ tools/power/cpupower/lib/cpufreq.h | 13 +++++++++++++ 2 files changed, 19 insertions(+) diff --git a/tools/power/cpupower/lib/cpufreq.c b/tools/power/cpupower/lib/cpufreq.c index 37da87bdcfb1..1443080868da 100644 --- a/tools/power/cpupower/lib/cpufreq.c +++ b/tools/power/cpupower/lib/cpufreq.c @@ -810,3 +810,9 @@ int amd_pstate_boost_enabled(unsigned int cpu) return cpuinfo_max == amd_pstate_max ? 1 : 0; } + +unsigned amd_pstate_get_data(unsigned int cpu, enum amd_pstate_param param) +{ + return sysfs_cpufreq_get_one_value(cpu, + param + AMD_PSTATE_HIGHEST_PERF); +} diff --git a/tools/power/cpupower/lib/cpufreq.h b/tools/power/cpupower/lib/cpufreq.h index d54d02a7a4f4..954e72704fc0 100644 --- a/tools/power/cpupower/lib/cpufreq.h +++ b/tools/power/cpupower/lib/cpufreq.h @@ -206,6 +206,19 @@ int cpufreq_set_frequency(unsigned int cpu, int amd_pstate_boost_support(unsigned int cpu); int amd_pstate_boost_enabled(unsigned int cpu); +enum amd_pstate_param { + HIGHEST_PERF, + NOMINAL_PERF, + LOWEST_NONLINEAR_PERF, + LOWEST_PERF, + MAX_FREQ, + NOMINAL_FREQ, + LOWEST_NONLINEAR_FREQ, + MIN_FREQ, +}; + +unsigned amd_pstate_get_data(unsigned int cpu, enum amd_pstate_param param); + #ifdef __cplusplus } #endif From patchwork Wed Sep 8 15:00:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 508151 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6FA9C433F5 for ; Wed, 8 Sep 2021 15:02:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D2C69611BF for ; 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Wed, 8 Sep 2021 10:01:57 -0500 From: Huang Rui To: "Rafael J . Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Ingo Molnar , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH 19/19] Documentation: amd-pstate: add amd-pstate driver introduction Date: Wed, 8 Sep 2021 23:00:01 +0800 Message-ID: <20210908150001.3702552-20-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210908150001.3702552-1-ray.huang@amd.com> References: <20210908150001.3702552-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 39f39b53-84bc-46d7-cb8c-08d972d99fd2 X-MS-TrafficTypeDiagnostic: DM6PR12MB4516: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6Wuv09UsijfwBYZjpZq9C39IBUFP6gwWi6fuduTfrTUdSPpJiaVcUU1oTD72NBEo3wVhjDUWPxOznHntCOBY89Tw2A0zDA8OlIKX410qcNstYAVGqA21IocVHV/rQunG+/6gkxe7yPvq++poFVyxQjwpeWR1vsslHNnYTsmYAo7LQEj98UkZ5s8jwJH2TAKh1Y2oeQ7MAaM0OoU8krw3hM6ilbaE2g/2SwCFpEpv7BEg56Z9hZH9mLiiH+ZKdDH2Vtz0OhhdQQzq+TUX7BZ3Pfqol2a6nF1GP9zBrX8hFrWGmDi4/kVTqBsZnJKFCYu5WpWrX/4j/qPXcv9Tq4BylWZNdPuJcs3mTg5kfFyAyx/zv2GNIqLYj+Gno0l5BkLUcSe5XM0K/y2Dp57WnqPbYJjrUzJ+wHj4v+fNVwvZnn/Qs5nH+E7HoSGE/XAtvk4H6M+/nv/utm+wWn0+6oi2vI5FXjid1ca+pcEE0dz3BObN6RW6tamAokieubGOtfKi6Fn59Gj7iIdEt6OCK0ZxF+hFvxDXqP5xqWl66xHW2Be6kBVcpYTu+j8Ips2aKBzB3FmMiQmDT9ESCZ36P+pwc0+AECHreNaD5qimxuLQQcCOKV89jLweL63Np7lDWOID7mryd4Sh0JTHa5uEGtZ6qm3wlpdwv6I1vLghoHebJhhpoJuSDgq7kDrFud1aCwTU9KTMWm6iEfzilRqjPuj34LwUarTmKgbzP+TQldZ35YXq3tq/UAcfBOr9nfwPC7cZkVYo3WNhEs/OFLf/N7tzS2ibIbI0aaQGZ61Y4TOEjg7w+hcfwerDK8Xe+3vhnEdN7anjxa8ok4+io4MSIqF3KhoV5fTCq613PyEWfB7pOU4= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(346002)(39860400002)(376002)(136003)(396003)(46966006)(36840700001)(47076005)(30864003)(6666004)(5660300002)(7696005)(478600001)(186003)(16526019)(966005)(8936002)(110136005)(316002)(54906003)(82740400003)(8676002)(2906002)(336012)(36756003)(86362001)(2616005)(70586007)(70206006)(36860700001)(83380400001)(82310400003)(426003)(81166007)(26005)(356005)(4326008)(1076003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2021 15:02:06.2838 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39f39b53-84bc-46d7-cb8c-08d972d99fd2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4516 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce the amd-pstate driver design and implementation. Signed-off-by: Huang Rui --- Documentation/admin-guide/pm/amd_pstate.rst | 377 ++++++++++++++++++ .../admin-guide/pm/working-state.rst | 1 + 2 files changed, 378 insertions(+) create mode 100644 Documentation/admin-guide/pm/amd_pstate.rst diff --git a/Documentation/admin-guide/pm/amd_pstate.rst b/Documentation/admin-guide/pm/amd_pstate.rst new file mode 100644 index 000000000000..c3659dde0cee --- /dev/null +++ b/Documentation/admin-guide/pm/amd_pstate.rst @@ -0,0 +1,377 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. include:: + +=============================================== +``amd-pstate`` CPU Performance Scaling Driver +=============================================== + +:Copyright: |copy| 2021 Advanced Micro Devices, Inc. + +:Author: Huang Rui + + +Introduction +=================== + +``amd-pstate`` is the AMD CPU performance scaling driver that introduces a +new CPU frequency control mechanism on modern AMD APU and CPU series in +Linux kernel. The new mechanism is based on Collaborative Processor +Performance Control (CPPC) which provides finer grain frequency management +than legacy ACPI hardware P-States. Current AMD CPU/APU platforms are using +the ACPI P-states driver to manage CPU frequency and clocks with switching +only in 3 P-states. CPPC replaces the ACPI P-states controls, allows a +flexible, low-latency interface for the Linux kernel to directly +communicate the performance hints to hardware. + +``amd-pstate`` leverages the Linux kernel governors such as ``schedutil``, +``ondemand``, etc. to manage the performance hints which are provided by +CPPC hardware functionality that internally follows the hardware +specification (for details refer to AMD64 Architecture Programmer's Manual +Volume 2: System Programming [1]_). Currently ``amd-pstate`` supports basic +frequency control function according to kernel governors on some of the +Zen2 and Zen3 processors, and we will implement more AMD specific functions +in future after we verify them on the hardware and SBIOS. + + +AMD CPPC Overview +======================= + +Collaborative Processor Performance Control (CPPC) interface enumerates a +continuous, abstract, and unit-less performance value in a scale that is +not tied to a specific performance state / frequency. This is an ACPI +standard [2]_ which software can specify application performance goals and +hints as a relative target to the infrastructure limits. AMD processors +provides the low latency register model (MSR) instead of AML code +interpreter for performance adjustments. ``amd-pstate`` will initialize a +``struct cpufreq_driver`` instance ``amd_pstate_driver`` with the callbacks +to manage each performance update behavior. :: + + Highest Perf ------>+-----------------------+ +-----------------------+ + | | | | + | | | | + | | Max Perf ---->| | + | | | | + | | | | + Nominal Perf ------>+-----------------------+ +-----------------------+ + | | | | + | | | | + | | | | + | | | | + | | | | + | | | | + | | Desired Perf ---->| | + | | | | + | | | | + | | | | + | | | | + | | | | + | | | | + | | | | + | | | | + | | | | + Lowest non- | | | | + linear perf ------>+-----------------------+ +-----------------------+ + | | | | + | | Lowest perf ---->| | + | | | | + Lowest perf ------>+-----------------------+ +-----------------------+ + | | | | + | | | | + | | | | + 0 ------>+-----------------------+ +-----------------------+ + + AMD P-States Performance Scale + + +.. _perf_cap: + +AMD CPPC Performance Capability +-------------------------------- + +Highest Performance (RO) +......................... + +It is the absolute maximum performance an individual processor may reach, +assuming ideal conditions. This performance level may not be sustainable +for long durations and may only be achievable if other platform components +are in a specific state; for example, it may require other processors be in +an idle state. This would be equivalent to the highest frequencies +supported by the processor. + +Nominal (Guaranteed) Performance (RO) +...................................... + +It is the maximum sustained performance level of the processor, assuming +ideal operating conditions. In absence of an external constraint (power, +thermal, etc.) this is the performance level the processor is expected to +be able to maintain continuously. All cores/processors are expected to be +able to sustain their nominal performance state simultaneously. + +Lowest non-linear Performance (RO) +................................... + +It is the lowest performance level at which nonlinear power savings are +achieved, for example, due to the combined effects of voltage and frequency +scaling. Above this threshold, lower performance levels should be generally +more energy efficient than higher performance levels. This register +effectively conveys the most efficient performance level to ``amd-pstate``. + +Lowest Performance (RO) +........................ + +It is the absolute lowest performance level of the processor. Selecting a +performance level lower than the lowest nonlinear performance level may +cause an efficiency penalty but should reduce the instantaneous power +consumption of the processor. + +AMD CPPC Performance Control +------------------------------ + +``amd-pstate`` passes performance goals through these registers. The +register drives the behavior of the desired performance target. + +Minimum requested performance (RW) +................................... + +``amd-pstate`` specifies the minimum allowed performance level. + +Maximum requested performance (RW) +................................... + +``amd-pstate`` specifies a limit the maximum performance that is expected +to be supplied by the hardware. + +Desired performance target (RW) +................................... + +``amd-pstate`` specifies a desired target in the CPPC performance scale as +a relative number. This can be expressed as percentage of nominal +performance (infrastructure max). Below the nominal sustained performance +level, desired performance expresses the average performance level of the +processor subject to hardware. Above the nominal performance level, +processor must provide at least nominal performance requested and go higher +if current operating conditions allow. + +Energy Performance Preference (EPP) (RW) +......................................... + +Provides a hint to the hardware if software wants to bias toward performance +(0x0) or energy efficiency (0xff). + + +Key Governors Support +======================= + +``amd-pstate`` can be used with all the (generic) scaling governors listed +by the ``scaling_available_governors`` policy attribute in ``sysfs``. Then, +it is responsible for the configuration of policy objects corresponding to +CPUs and provides the ``CPUFreq`` core (and the scaling governors attached +to the policy objects) with accurate information on the maximum and minimum +operating frequencies supported by the hardware. Users can check the +``scaling_cur_freq`` information comes from the ``CPUFreq`` core. + +``amd-pstate`` mainly supports ``schedutil`` and ``ondemand`` for dynamic +frequency control. It is to fine tune the processor configuration on +``amd-pstate`` to the ``schedutil`` with CPU CFS scheduler. ``amd-pstate`` +registers adjust_perf callback to implement the CPPC similar performance +update behavior. It is initialized by ``sugov_start`` and then populate the +CPU's update_util_data pointer to assign ``sugov_update_single_perf`` as +the utilization update callback function in CPU scheduler. CPU scheduler +will call ``cpufreq_update_util`` and assign the target performance +according to the ``struct sugov_cpu`` that utilization update belongs to. +Then ``amd-pstate`` updates the desired performance according to the CPU +scheduler assigned. + + +Processor Support +======================= + +The ``amd-pstate`` initialization will fail if the _CPC in ACPI SBIOS is +not existed at the detected processor, and it uses ``acpi_cpc_valid`` to +check the _CPC existence. All Zen based processors support legacy ACPI +hardware P-States function, so while the ``amd-pstate`` fails to be +initialized, the kernel will fall back to initialize ``acpi-cpufreq`` +driver. + +There are two types of hardware implementations for ``amd-pstate``: one is +`Full MSR Support `_ and another is `Shared Memory Support +`_. It can use :c:macro:`X86_FEATURE_AMD_CPPC_EXT` feature flag +(for details refer to Processor Programming Reference (PPR) for AMD Family +19h Model 21h, Revision B0 Processors [3]_) to indicate the different +types. ``amd-pstate`` is to register different ``amd_pstate_perf_funcs`` +instances for different hardware implementations. + +Currently, some of Zen2 and Zen3 processors support ``amd-pstate``. In the +future, it will be supported on more and more AMD processors. + +Full MSR Support +----------------- + +Some new Zen3 processors such as Cezanne provide the MSR registers directly +while the :c:macro:`X86_FEATURE_AMD_CPPC_EXT` CPU feature flag is set. +``amd-pstate`` can handle the MSR register to implement the fast switch +function in ``CPUFreq`` that can shrink latency of frequency control on the +interrupt context. + +Shared Memory Support +---------------------- + +If :c:macro:`X86_FEATURE_AMD_CPPC_EXT` CPU feature flag is not set, that +means the processor supports shared memory solution. In this case, +``amd-pstate`` uses the ``cppc_acpi`` helper methods to implement the +callback functions of ``amd_pstate_perf_funcs``. + + +AMD P-States and ACPI hardware P-States always can be supported in one +processor. But AMD P-States has the higher priority and if it is enabled +with :c:macro:`MSR_AMD_CPPC_ENABLE` or ``cppc_set_enable``, it will respond +to the request from AMD P-States. + + +User Space Interface in ``sysfs`` +================================== + +``amd-pstate`` exposes several global attributes (files) in ``sysfs`` to +control its functionality at the system level. They located in the +``/sys/devices/system/cpu/cpufreq/policyX/`` directory and affect all CPUs. :: + + root@hr-test1:/home/ray# ls /sys/devices/system/cpu/cpufreq/policy0/*amd* + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_highest_perf + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_lowest_nonlinear_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_lowest_nonlinear_perf + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_lowest_perf + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_max_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_min_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_nominal_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_nominal_perf + /sys/devices/system/cpu/cpufreq/policy0/is_amd_pstate_enabled + + +``is_amd_pstate_enabled`` + +Query whether current kernel loads ``amd-pstate`` to enable the AMD +P-States functionality. +This attribute is read-only. + +``amd_pstate_highest_perf / amd_pstate_max_freq`` + +Maximum CPPC performance and CPU frequency that the driver is allowed to +set in percent of the maximum supported CPPC performance level (the highest +performance supported in `AMD CPPC Performance Capability `_). +This attribute is read-only. + +``amd_pstate_nominal_perf / amd_pstate_nominal_freq`` + +Nominal CPPC performance and CPU frequency that the driver is allowed to +set in percent of the maximum supported CPPC performance level (Please see +nominal performance in `AMD CPPC Performance Capability `_). +This attribute is read-only. + +``amd_pstate_lowest_nonlinear_perf / amd_pstate_lowest_nonlinear_freq`` + +The lowest non-linear CPPC performance and CPU frequency that the driver is +allowed to set in percent of the maximum supported CPPC performance level +(Please see the lowest non-linear performance in `AMD CPPC Performance +Capability `_). +This attribute is read-only. + +``amd_pstate_lowest_perf / amd_pstate_min_freq`` + +The lowest physical CPPC performance and CPU frequency. +This attribute is read-only. + + +``amd-pstate`` vs ``acpi-cpufreq`` +====================================== + +On majority of AMD platforms supported by ``acpi-cpufreq``, the ACPI tables +provided by the platform firmware used for CPU performance scaling, but +only provides 3 P-states on AMD processors. +However, on modern AMD APU and CPU series, it provides the collaborative +processor performance control according to ACPI protocol and customize this +for AMD platforms. That is fine-grain and continuous frequency range +instead of the legacy hardware P-states. ``amd-pstate`` is the kernel +module which supports the new AMD P-States mechanism on most of future AMD +platforms. The AMD P-States mechanism will be the more performance and energy +efficiency frequency management method on AMD processors. + +``cpupower`` tool support for ``amd-pstate`` +=============================================== + +``amd-pstate`` is supported on ``cpupower`` tool that can be used to dump the frequency +information. And it is in progress to support more and more operations for new +``amd-pstate`` module with this tool. :: + + root@hr-test1:/home/ray# cpupower frequency-info + analyzing CPU 0: + driver: amd-pstate + CPUs which run at the same hardware frequency: 0 + CPUs which need to have their frequency coordinated by software: 0 + maximum transition latency: 131 us + hardware limits: 400 MHz - 4.68 GHz + available cpufreq governors: ondemand conservative powersave userspace performance schedutil + current policy: frequency should be within 400 MHz and 4.68 GHz. + The governor "schedutil" may decide which speed to use + within this range. + current CPU frequency: Unable to call hardware + current CPU frequency: 4.02 GHz (asserted by call to kernel) + boost state support: + Supported: yes + Active: yes + AMD PSTATE Highest Performance: 166. Maximum Frequency: 4.68 GHz. + AMD PSTATE Nominal Performance: 117. Nominal Frequency: 3.30 GHz. + AMD PSTATE Lowest Non-linear Performance: 39. Lowest Non-linear Frequency: 1.10 GHz. + AMD PSTATE Lowest Performance: 15. Lowest Frequency: 400 MHz. + + +Diagnostics and Tuning +======================= + +Trace Events +-------------- + +There are two static trace events that can be used for ``amd-pstate`` +diagnostics. One of them is the cpu_frequency trace event generally used +by ``CPUFreq``, and the other one is the ``amd_pstate_perf`` trace event +specific to ``amd-pstate``. The following sequence of shell commands can +be used to enable them and see their output (if the kernel is generally +configured to support event tracing). :: + + root@hr-test1:/home/ray# cd /sys/kernel/tracing/ + root@hr-test1:/sys/kernel/tracing# echo 1 > events/amd_cpu/enable + root@hr-test1:/sys/kernel/tracing# cat trace + # tracer: nop + # + # entries-in-buffer/entries-written: 47827/42233061 #P:2 + # + # _-----=> irqs-off + # / _----=> need-resched + # | / _---=> hardirq/softirq + # || / _--=> preempt-depth + # ||| / delay + # TASK-PID CPU# |||| TIMESTAMP FUNCTION + # | | | |||| | | + -0 [000] d.s. 244057.464842: amd_pstate_perf: amd_min_perf=39 amd_des_perf=39 amd_max_perf=166 cpu_id=0 prev=0x2727a6 value=0x2727a6 + -0 [000] d.h. 244057.475436: amd_pstate_perf: amd_min_perf=39 amd_des_perf=39 amd_max_perf=166 cpu_id=0 prev=0x2727a6 value=0x2727a6 + -0 [000] d.h. 244057.476629: amd_pstate_perf: amd_min_perf=39 amd_des_perf=39 amd_max_perf=166 cpu_id=0 prev=0x2727a6 value=0x2727a6 + -0 [000] d.s. 244057.484847: amd_pstate_perf: amd_min_perf=39 amd_des_perf=39 amd_max_perf=166 cpu_id=0 prev=0x2727a6 value=0x2727a6 + -0 [000] d.h. 244057.499821: amd_pstate_perf: amd_min_perf=39 amd_des_perf=39 amd_max_perf=166 cpu_id=0 prev=0x2727a6 value=0x2727a6 + avahi-daemon-528 [000] d... 244057.513568: amd_pstate_perf: amd_min_perf=39 amd_des_perf=39 amd_max_perf=166 cpu_id=0 prev=0x2727a6 value=0x2727a6 + +The cpu_frequency trace event will be triggered either by the ``schedutil`` scaling +governor (for the policies it is attached to), or by the ``CPUFreq`` core (for the +policies with other scaling governors). + + +Reference +=========== + +.. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming, + https://www.amd.com/system/files/TechDocs/24593.pdf + +.. [2] Advanced Configuration and Power Interface Specification, + https://uefi.org/sites/default/files/resources/ACPI_Spec_6_4_Jan22.pdf + +.. [3] Processor Programming Reference (PPR) for AMD Family 19h Model 21h, Revision B0 Processors + https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip + diff --git a/Documentation/admin-guide/pm/working-state.rst b/Documentation/admin-guide/pm/working-state.rst index f40994c422dc..28db6156b55d 100644 --- a/Documentation/admin-guide/pm/working-state.rst +++ b/Documentation/admin-guide/pm/working-state.rst @@ -11,6 +11,7 @@ Working-State Power Management intel_idle cpufreq intel_pstate + amd_pstate cpufreq_drivers intel_epb intel-speed-select