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Tue, 7 Sep 2021 09:49:52 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v8 01/15] dt-bindings: media: amphion: add amphion video codec bindings Date: Tue, 7 Sep 2021 17:49:08 +0800 Message-Id: <40ecffa8bcb7197b7bf0212ccf04e0698345596f.1631002447.git.ming.qian@nxp.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: X-ClientProxiedBy: SG2PR02CA0097.apcprd02.prod.outlook.com (2603:1096:4:92::13) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by SG2PR02CA0097.apcprd02.prod.outlook.com (2603:1096:4:92::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4478.19 via Frontend Transport; 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Implement via mailbox on driver. + $ref: ../mailbox/fsl,mu.yaml# + + + "^vpu_core@[0-9a-f]+$": + description: + Each core correspond a decoder or encoder, need to configure them + separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC + has one decoder and one encoder. + type: object + + properties: + compatible: + oneOf: + - const: nxp,imx8q-vpu-decoder + - const: nxp,imx8q-vpu-encoder + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + mbox-names: + items: + - const: tx0 + - const: tx1 + - const: rx + + mboxes: + description: + List of phandle of 2 MU channels for tx, 1 MU channel for rx. + maxItems: 3 + + memory-region: + description: + Phandle to the reserved memory nodes to be associated with the + remoteproc device. The reserved memory nodes should be carveout nodes, + and should be defined as per the bindings in + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + items: + - description: region reserved for firmware image sections. + - description: region used for RPC shared memory between firmware and + driver. + + required: + - compatible + - reg + - power-domains + - mbox-names + - mboxes + - memory-region + + additionalProperties: false + +required: + - compatible + - reg + - power-domains + +additionalProperties: false + +examples: + # Device node example for i.MX8QM platform: + - | + #include + + vpu: vpu@2c000000 { + compatible = "nxp,imx8qm-vpu"; + ranges = <0x2c000000 0x2c000000 0x2000000>; + reg = <0x2c000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&pd IMX_SC_R_VPU>; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = <0 472 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = <0 473 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = <0 474 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + }; + + vpu_core0: vpu_core@2d080000 { + compatible = "nxp,imx8q-vpu-decoder"; + reg = <0x2d080000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0>, + <&mu_m0 0 1>, + <&mu_m0 1 0>; + memory-region = <&decoder_boot>, <&decoder_rpc>; + }; + + vpu_core1: vpu_core@2d090000 { + compatible = "nxp,imx8q-vpu-encoder"; + reg = <0x2d090000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu1_m0 0 0>, + <&mu1_m0 0 1>, + <&mu1_m0 1 0>; + memory-region = <&encoder1_boot>, <&encoder1_rpc>; + }; + + vpu_core2: vpu_core@2d0a0000 { + reg = <0x2d0a0000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu2_m0 0 0>, + <&mu2_m0 0 1>, + <&mu2_m0 1 0>; + memory-region = <&encoder2_boot>, <&encoder2_rpc>; + }; + }; + +... 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So we add a buf flag to tell this case. Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- Documentation/userspace-api/media/v4l/buffer.rst | 7 +++++++ include/uapi/linux/videodev2.h | 1 + 2 files changed, 8 insertions(+) diff --git a/Documentation/userspace-api/media/v4l/buffer.rst b/Documentation/userspace-api/media/v4l/buffer.rst index e991ba73d873..11013bcf8a41 100644 --- a/Documentation/userspace-api/media/v4l/buffer.rst +++ b/Documentation/userspace-api/media/v4l/buffer.rst @@ -607,6 +607,13 @@ Buffer Flags the format. Any subsequent call to the :ref:`VIDIOC_DQBUF ` ioctl will not block anymore, but return an ``EPIPE`` error code. + * .. _`V4L2-BUF-FLAG-CODECCONFIG`: + + - ``V4L2_BUF_FLAG_CODECCONFIG`` + - 0x00200000 + - The buffer only contains codec config data, eg. sps and pps. + Applications can set this bit when ``type`` refers to an output + stream, this flag is usually used by v4l2 decoder. * .. _`V4L2-BUF-FLAG-REQUEST-FD`: - ``V4L2_BUF_FLAG_REQUEST_FD`` diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 167c0e40ec06..5bb0682b4a23 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -1119,6 +1119,7 @@ static inline __u64 v4l2_timeval_to_ns(const struct timeval *tv) #define V4L2_BUF_FLAG_TSTAMP_SRC_SOE 0x00010000 /* mem2mem encoder/decoder */ #define V4L2_BUF_FLAG_LAST 0x00100000 +#define V4L2_BUF_FLAG_CODECCONFIG 0x00200000 /* request_fd is valid */ #define V4L2_BUF_FLAG_REQUEST_FD 0x00800000 From patchwork Tue Sep 7 09:49:12 2021 Content-Type: text/plain; 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Tue, 7 Sep 2021 09:50:08 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v8 05/15] media: amphion: add amphion vpu device driver Date: Tue, 7 Sep 2021 17:49:12 +0800 Message-Id: <194be3d46e21c8ef07d3a2da1e1416cc9c44b6c7.1631002447.git.ming.qian@nxp.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: X-ClientProxiedBy: SG2PR02CA0097.apcprd02.prod.outlook.com (2603:1096:4:92::13) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by SG2PR02CA0097.apcprd02.prod.outlook.com (2603:1096:4:92::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4478.19 via Frontend Transport; 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Windsor is the encoder, it supports to encode H.264. Malone is the decoder, it features a powerful video processing unit able to decode many foramts, such as H.264, HEVC, and other foramts. This Driver is for this IP that is based on the v4l2 mem2mem framework. Supported SoCs are: IMX8QXP, IMX8QM Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng Reported-by: kernel test robot --- drivers/media/platform/Kconfig | 19 + drivers/media/platform/Makefile | 2 + drivers/media/platform/amphion/Makefile | 23 ++ drivers/media/platform/amphion/vpu.h | 333 ++++++++++++++++++ drivers/media/platform/amphion/vpu_defs.h | 186 ++++++++++ .../media/platform/amphion/vpu_dev_imx8q.c | 72 ++++ drivers/media/platform/amphion/vpu_drv.c | 217 ++++++++++++ 7 files changed, 852 insertions(+) create mode 100644 drivers/media/platform/amphion/Makefile create mode 100644 drivers/media/platform/amphion/vpu.h create mode 100644 drivers/media/platform/amphion/vpu_defs.h create mode 100644 drivers/media/platform/amphion/vpu_dev_imx8q.c create mode 100644 drivers/media/platform/amphion/vpu_drv.c diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index 157c924686e4..5240111da884 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -200,6 +200,25 @@ config VIDEO_TI_CAL_MC endif # VIDEO_TI_CAL +config VIDEO_AMPHION_VPU + tristate "Amphion VPU(Video Processing Unit) Codec IP" + depends on ARCH_MXC + depends on MEDIA_SUPPORT + depends on VIDEO_DEV + depends on VIDEO_V4L2 + select V4L2_MEM2MEM_DEV + select VIDEOBUF2_DMA_CONTIG + select VIDEOBUF2_VMALLOC + default y + help + Amphion VPU Codec IP contains two parts: Windsor and Malone. + Windsor is encoder that supports H.264, and Malone is decoder + that supports H.264, HEVC, and other video formats. + This is a V4L2 driver for NXP MXC 8Q video accelerator hardware. + It accelerates encoding and decoding operations on + various NXP SoCs. + To compile this driver as a module choose m here. + endif # V4L_PLATFORM_DRIVERS menuconfig V4L_MEM2MEM_DRIVERS diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index 73ce083c2fc6..116797484ded 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -86,3 +86,5 @@ obj-$(CONFIG_VIDEO_QCOM_VENUS) += qcom/venus/ obj-y += sunxi/ obj-$(CONFIG_VIDEO_MESON_GE2D) += meson/ge2d/ + +obj-$(CONFIG_VIDEO_AMPHION_VPU) += amphion/ diff --git a/drivers/media/platform/amphion/Makefile b/drivers/media/platform/amphion/Makefile new file mode 100644 index 000000000000..315ba4b41157 --- /dev/null +++ b/drivers/media/platform/amphion/Makefile @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0 +# Makefile for NXP VPU driver + +amphion-vpu-dev-objs += vpu_drv.o \ + vpu_dev_imx8q.o + +amphion-vpu-core-objs += vpu_core.o \ + vpu_mbox.o \ + vpu_v4l2.o \ + vpu_helpers.o \ + vpu_cmds.o \ + vpu_msgs.o \ + vpu_rpc.o \ + vpu_imx8q.o \ + vpu_windsor.o \ + vpu_malone.o \ + vpu_color.o \ + vdec.o \ + venc.o \ + vpu_dbg.o + +obj-$(CONFIG_VIDEO_AMPHION_VPU) += amphion-vpu-dev.o +obj-$(CONFIG_VIDEO_AMPHION_VPU) += amphion-vpu-core.o diff --git a/drivers/media/platform/amphion/vpu.h b/drivers/media/platform/amphion/vpu.h new file mode 100644 index 000000000000..2530f3885758 --- /dev/null +++ b/drivers/media/platform/amphion/vpu.h @@ -0,0 +1,333 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2020-2021 NXP + */ + +#ifndef _AMPHION_VPU_H +#define _AMPHION_VPU_H + +#include +#include +#include +#include +#include +#include + +#define VPU_TIMEOUT msecs_to_jiffies(1000) +#define VPU_INST_NULL_ID (-1L) +#define VPU_MSG_BUFFER_SIZE (8192) + +enum imx_plat_type { + IMX8QXP = 0, + IMX8QM = 1, + IMX8DM, + IMX8DX, + PLAT_TYPE_RESERVED +}; + +enum vpu_core_type { + VPU_CORE_TYPE_ENC = 0, + VPU_CORE_TYPE_DEC = 0x10, +}; + +struct vpu_dev; +struct vpu_resources { + enum imx_plat_type plat_type; + u32 mreg_base; + int (*setup)(struct vpu_dev *vpu); + int (*setup_encoder)(struct vpu_dev *vpu); + int (*setup_decoder)(struct vpu_dev *vpu); + int (*reset)(struct vpu_dev *vpu); +}; + +struct vpu_buffer { + void *virt; + dma_addr_t phys; + u32 length; + u32 bytesused; + struct device *dev; +}; + +struct vpu_dev { + void __iomem *base; + struct platform_device *pdev; + struct device *dev; + struct mutex lock; + const struct vpu_resources *res; + struct list_head cores; + + struct v4l2_device v4l2_dev; + struct video_device *vdev_dec; + struct video_device *vdev_enc; + + struct delayed_work watchdog_work; + void (*get_vpu)(struct vpu_dev *vpu); + void (*put_vpu)(struct vpu_dev *vpu); + void (*get_enc)(struct vpu_dev *vpu); + void (*put_enc)(struct vpu_dev *vpu); + void (*get_dec)(struct vpu_dev *vpu); + void (*put_dec)(struct vpu_dev *vpu); + atomic_t ref_vpu; + atomic_t ref_enc; + atomic_t ref_dec; + + struct dentry *debugfs; +}; + +struct vpu_format { + u32 pixfmt; + unsigned int num_planes; + u32 type; + u32 flags; + u32 width; + u32 height; + u32 sizeimage[VIDEO_MAX_PLANES]; + u32 bytesperline[VIDEO_MAX_PLANES]; + u32 field; +}; + +struct vpu_core_resources { + enum vpu_core_type type; + const char *fwname; + u32 stride; + u32 max_width; + u32 min_width; + u32 step_width; + u32 max_height; + u32 min_height; + u32 step_height; + u32 rpc_size; + u32 fwlog_size; + u32 act_size; + bool standalone; +}; + +struct vpu_mbox { + char name[20]; + struct mbox_client cl; + struct mbox_chan *ch; + bool block; +}; + +enum vpu_core_state { + VPU_CORE_DEINIT = 0, + VPU_CORE_ACTIVE, + VPU_CORE_SNAPSHOT, + VPU_CORE_HANG +}; + +struct vpu_core { + void __iomem *base; + struct platform_device *pdev; + struct device *dev; + struct device *parent; + struct device *pd; + struct device_link *pd_link; + struct mutex lock; + struct mutex cmd_lock; + struct list_head list; + enum vpu_core_type type; + int id; + const struct vpu_core_resources *res; + unsigned long instance_mask; + u32 supported_instance_count; + unsigned long hang_mask; + u32 request_count; + struct list_head instances; + enum vpu_core_state state; + u32 fw_version; + + struct vpu_buffer fw; + struct vpu_buffer rpc; + struct vpu_buffer log; + struct vpu_buffer act; + + struct vpu_mbox tx_type; + struct vpu_mbox tx_data; + struct vpu_mbox rx; + unsigned long cmd_seq; + + wait_queue_head_t ack_wq; + struct completion cmp; + struct workqueue_struct *workqueue; + struct work_struct msg_work; + struct delayed_work msg_delayed_work; + struct kfifo msg_fifo; + void *msg_buffer; + unsigned int msg_buffer_size; + + struct vpu_dev *vpu; + void *iface; + + struct dentry *debugfs; + struct dentry *debugfs_fwlog; +}; + +enum vpu_codec_state { + VPU_CODEC_STATE_DEINIT = 1, + VPU_CODEC_STATE_CONFIGURED, + VPU_CODEC_STATE_START, + VPU_CODEC_STATE_STARTED, + VPU_CODEC_STATE_ACTIVE, + VPU_CODEC_STATE_SEEK, + VPU_CODEC_STATE_STOP, + VPU_CODEC_STATE_DRAIN, + VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE, +}; + +struct vpu_frame_info { + u32 type; + u32 id; + u32 sequence; + u32 luma; + u32 chroma_u; + u32 chroma_v; + u32 data_offset; + u32 flags; + u32 skipped; + s64 timestamp; +}; + +struct vpu_inst; +struct vpu_inst_ops { + int (*ctrl_init)(struct vpu_inst *inst); + int (*start)(struct vpu_inst *inst, u32 type); + int (*stop)(struct vpu_inst *inst, u32 type); + int (*abort)(struct vpu_inst *inst); + bool (*check_ready)(struct vpu_inst *inst, unsigned int type); + void (*buf_done)(struct vpu_inst *inst, struct vpu_frame_info *frame); + void (*event_notify)(struct vpu_inst *inst, u32 event, void *data); + void (*release)(struct vpu_inst *inst); + void (*cleanup)(struct vpu_inst *inst); + void (*mem_request)(struct vpu_inst *inst, + u32 enc_frame_size, + u32 enc_frame_num, + u32 ref_frame_size, + u32 ref_frame_num, + u32 act_frame_size, + u32 act_frame_num); + void (*input_done)(struct vpu_inst *inst); + void (*stop_done)(struct vpu_inst *inst); + int (*process_output)(struct vpu_inst *inst, struct vb2_buffer *vb); + int (*process_capture)(struct vpu_inst *inst, struct vb2_buffer *vb); + int (*get_one_frame)(struct vpu_inst *inst, void *info); + void (*on_queue_empty)(struct vpu_inst *inst, u32 type); + int (*get_debug_info)(struct vpu_inst *inst, char *str, u32 size, u32 i); + void (*wait_prepare)(struct vpu_inst *inst); + void (*wait_finish)(struct vpu_inst *inst); +}; + +struct vpu_inst { + struct list_head list; + struct mutex lock; + struct vpu_core *core; + int id; + + struct v4l2_fh fh; + struct v4l2_m2m_dev *m2m_dev; + struct v4l2_m2m_ctx *m2m_ctx; + struct v4l2_ctrl_handler ctrl_handler; + atomic_t ref_count; + int (*release)(struct vpu_inst *inst); + + enum vpu_codec_state state; + enum vpu_core_type type; + + struct workqueue_struct *workqueue; + struct work_struct msg_work; + struct kfifo msg_fifo; + u8 msg_buffer[VPU_MSG_BUFFER_SIZE]; + + struct vpu_buffer stream_buffer; + bool use_stream_buffer; + struct vpu_buffer act; + + struct list_head cmd_q; + void *pending; + + struct vpu_inst_ops *ops; + const struct vpu_format *formats; + struct vpu_format out_format; + struct vpu_format cap_format; + u32 min_buffer_cap; + u32 min_buffer_out; + + struct v4l2_rect crop; + u32 colorspace; + u8 ycbcr_enc; + u8 quantization; + u8 xfer_func; + u32 sequence; + u32 extra_size; + + u32 flows[16]; + u32 flow_idx; + + pid_t pid; + pid_t tgid; + struct dentry *debugfs; + + void *priv; +}; + +#define call_vop(inst, op, args...) \ + ((inst)->ops->op ? (inst)->ops->op(inst, ##args) : 0) \ + +enum { + VPU_BUF_STATE_IDLE = 0, + VPU_BUF_STATE_INUSE, + VPU_BUF_STATE_DECODED, + VPU_BUF_STATE_READY, + VPU_BUF_STATE_SKIP, + VPU_BUF_STATE_ERROR +}; + +struct vpu_vb2_buffer { + struct v4l2_m2m_buffer m2m_buf; + dma_addr_t luma; + dma_addr_t chroma_u; + dma_addr_t chroma_v; + unsigned int state; + u32 tag; +}; + +void vpu_writel(struct vpu_dev *vpu, u32 reg, u32 val); +u32 vpu_readl(struct vpu_dev *vpu, u32 reg); + +static inline struct vpu_vb2_buffer *to_vpu_vb2_buffer(struct vb2_v4l2_buffer *vbuf) +{ + struct v4l2_m2m_buffer *m2m_buf = container_of(vbuf, struct v4l2_m2m_buffer, vb); + + return container_of(m2m_buf, struct vpu_vb2_buffer, m2m_buf); +} + +static inline const char *vpu_core_type_desc(enum vpu_core_type type) +{ + return type == VPU_CORE_TYPE_ENC ? "encoder" : "decoder"; +} + +static inline struct vpu_inst *to_inst(struct file *filp) +{ + return container_of(filp->private_data, struct vpu_inst, fh); +} + +#define ctrl_to_inst(ctrl) \ + container_of((ctrl)->handler, struct vpu_inst, ctrl_handler) + +int venc_create_video_device(struct vpu_dev *vpu); +int vdec_create_video_device(struct vpu_dev *vpu); + +struct vpu_inst *vpu_inst_get(struct vpu_inst *inst); +void vpu_inst_put(struct vpu_inst *inst); +struct vpu_core *vpu_request_core(struct vpu_dev *vpu, enum vpu_core_type type); +void vpu_release_core(struct vpu_core *core); +int vpu_inst_register(struct vpu_inst *inst); +int vpu_inst_unregister(struct vpu_inst *inst); + +int vpu_inst_create_dbgfs_file(struct vpu_inst *inst); +int vpu_inst_remove_dbgfs_file(struct vpu_inst *inst); +int vpu_core_create_dbgfs_file(struct vpu_core *core); +int vpu_core_remove_dbgfs_file(struct vpu_core *core); +void vpu_inst_record_flow(struct vpu_inst *inst, u32 flow); + +#endif diff --git a/drivers/media/platform/amphion/vpu_defs.h b/drivers/media/platform/amphion/vpu_defs.h new file mode 100644 index 000000000000..7fd4380a21dd --- /dev/null +++ b/drivers/media/platform/amphion/vpu_defs.h @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2020-2021 NXP + */ + +#ifndef _AMPHION_VPU_DEFS_H +#define _AMPHION_VPU_DEFS_H + +enum MSG_TYPE { + INIT_DONE = 1, + PRC_BUF_OFFSET, + BOOT_ADDRESS, + COMMAND, + EVENT, +}; + +enum { + VPU_IRQ_CODE_BOOT_DONE = 0x55, + VPU_IRQ_CODE_SNAPSHOT_DONE = 0xa5, + VPU_IRQ_CODE_SYNC = 0xaa, +}; + +enum { + VPU_CMD_ID_NOOP = 0x0, + VPU_CMD_ID_CONFIGURE_CODEC, + VPU_CMD_ID_START, + VPU_CMD_ID_STOP, + VPU_CMD_ID_ABORT, + VPU_CMD_ID_RST_BUF, + VPU_CMD_ID_SNAPSHOT, + VPU_CMD_ID_FIRM_RESET, + VPU_CMD_ID_UPDATE_PARAMETER, + VPU_CMD_ID_FRAME_ENCODE, + VPU_CMD_ID_SKIP, + VPU_CMD_ID_PARSE_NEXT_SEQ, + VPU_CMD_ID_PARSE_NEXT_I, + VPU_CMD_ID_PARSE_NEXT_IP, + VPU_CMD_ID_PARSE_NEXT_ANY, + VPU_CMD_ID_DEC_PIC, + VPU_CMD_ID_FS_ALLOC, + VPU_CMD_ID_FS_RELEASE, + VPU_CMD_ID_TIMESTAMP, + VPU_CMD_ID_DEBUG +}; + +enum { + VPU_MSG_ID_NOOP = 0x100, + VPU_MSG_ID_RESET_DONE, + VPU_MSG_ID_START_DONE, + VPU_MSG_ID_STOP_DONE, + VPU_MSG_ID_ABORT_DONE, + VPU_MSG_ID_BUF_RST, + VPU_MSG_ID_MEM_REQUEST, + VPU_MSG_ID_PARAM_UPD_DONE, + VPU_MSG_ID_FRAME_INPUT_DONE, + VPU_MSG_ID_ENC_DONE, + VPU_MSG_ID_DEC_DONE, + VPU_MSG_ID_FRAME_REQ, + VPU_MSG_ID_FRAME_RELEASE, + VPU_MSG_ID_SEQ_HDR_FOUND, + VPU_MSG_ID_RES_CHANGE, + VPU_MSG_ID_PIC_HDR_FOUND, + VPU_MSG_ID_PIC_DECODED, + VPU_MSG_ID_PIC_EOS, + VPU_MSG_ID_FIFO_LOW, + VPU_MSG_ID_FIFO_HIGH, + VPU_MSG_ID_FIFO_EMPTY, + VPU_MSG_ID_FIFO_FULL, + VPU_MSG_ID_BS_ERROR, + VPU_MSG_ID_UNSUPPORTED, + VPU_MSG_ID_TIMESTAMP_INFO, + + VPU_MSG_ID_FIRMWARE_XCPT, +}; + +enum VPU_ENC_MEMORY_RESOURSE { + MEM_RES_ENC, + MEM_RES_REF, + MEM_RES_ACT +}; + +enum VPU_DEC_MEMORY_RESOURCE { + MEM_RES_FRAME, + MEM_RES_MBI, + MEM_RES_DCP +}; + +enum VPU_SCODE_TYPE { + SCODE_PADDING_EOS = 1, + SCODE_PADDING_BUFFLUSH = 2, + SCODE_PADDING_ABORT = 3, + SCODE_SEQUENCE = 0x31, + SCODE_PICTURE = 0x32, + SCODE_SLICE = 0x33 +}; + +struct vpu_pkt_mem_req_data { + u32 enc_frame_size; + u32 enc_frame_num; + u32 ref_frame_size; + u32 ref_frame_num; + u32 act_buf_size; + u32 act_buf_num; +}; + +struct vpu_enc_pic_info { + u32 frame_id; + u32 pic_type; + u32 skipped_frame; + u32 error_flag; + u32 psnr; + u32 frame_size; + u32 wptr; + u32 crc; + s64 timestamp; +}; + +struct vpu_dec_codec_info { + u32 pixfmt; + u32 num_ref_frms; + u32 num_dpb_frms; + u32 num_dfe_area; + u32 color_primaries; + u32 transfer_chars; + u32 matrix_coeffs; + u32 full_range; + u32 vui_present; + u32 progressive; + u32 width; + u32 height; + u32 decoded_width; + u32 decoded_height; + u32 frame_rate; + u32 dsp_asp_ratio; + u32 level_idc; + u32 bit_depth_luma; + u32 bit_depth_chroma; + u32 chroma_fmt; + u32 mvc_num_views; + u32 offset_x; + u32 offset_y; + u32 tag; + u32 sizeimage[VIDEO_MAX_PLANES]; + u32 bytesperline[VIDEO_MAX_PLANES]; + u32 mbi_size; + u32 dcp_size; + u32 stride; +}; + +struct vpu_dec_pic_info { + u32 id; + u32 luma; + u32 start; + u32 end; + u32 pic_size; + u32 stride; + u32 skipped; + s64 timestamp; + u32 consumed_count; +}; + +struct vpu_fs_info { + u32 id; + u32 type; + u32 tag; + u32 luma_addr; + u32 luma_size; + u32 chroma_addr; + u32 chromau_size; + u32 chromav_addr; + u32 chromav_size; + u32 bytesperline; + u32 not_displayed; +}; + +struct vpu_ts_info { + s64 timestamp; + u32 size; +}; + +#define BITRATE_STEP (1024) +#define BITRATE_MIN (16 * BITRATE_STEP) +#define BITRATE_MAX (240 * 1024 * BITRATE_STEP) +#define BITRATE_DEFAULT (2 * 1024 * BITRATE_STEP) + +#endif diff --git a/drivers/media/platform/amphion/vpu_dev_imx8q.c b/drivers/media/platform/amphion/vpu_dev_imx8q.c new file mode 100644 index 000000000000..cbeb6a4608e2 --- /dev/null +++ b/drivers/media/platform/amphion/vpu_dev_imx8q.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include "vpu.h" +#include "vpu_imx8q.h" + +int vpu_imx8q_setup_dec(struct vpu_dev *vpu) +{ + const off_t offset = DEC_MFD_XREG_SLV_BASE + MFD_BLK_CTRL; + + vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_SET, 0x1f); + vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_SET, 0xffffffff); + + return 0; +} + +int vpu_imx8q_setup_enc(struct vpu_dev *vpu) +{ + return 0; +} + +int vpu_imx8q_setup(struct vpu_dev *vpu) +{ + const off_t offset = SCB_XREG_SLV_BASE + SCB_SCB_BLK_CTRL; + + vpu_readl(vpu, offset + 0x108); + + vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0x1); + vpu_writel(vpu, offset + 0x190, 0xffffffff); + vpu_writel(vpu, offset + SCB_BLK_CTRL_XMEM_RESET_SET, 0xffffffff); + vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0xE); + vpu_writel(vpu, offset + SCB_BLK_CTRL_CACHE_RESET_SET, 0x7); + vpu_writel(vpu, XMEM_CONTROL, 0x102); + + vpu_readl(vpu, offset + 0x108); + + return 0; +} + +static int vpu_imx8q_reset_enc(struct vpu_dev *vpu) +{ + return 0; +} + +static int vpu_imx8q_reset_dec(struct vpu_dev *vpu) +{ + const off_t offset = DEC_MFD_XREG_SLV_BASE + MFD_BLK_CTRL; + + vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_CLR, 0xffffffff); + + return 0; +} + +int vpu_imx8q_reset(struct vpu_dev *vpu) +{ + const off_t offset = SCB_XREG_SLV_BASE + SCB_SCB_BLK_CTRL; + + vpu_writel(vpu, offset + SCB_BLK_CTRL_CACHE_RESET_CLR, 0x7); + vpu_imx8q_reset_enc(vpu); + vpu_imx8q_reset_dec(vpu); + + return 0; +} diff --git a/drivers/media/platform/amphion/vpu_drv.c b/drivers/media/platform/amphion/vpu_drv.c new file mode 100644 index 000000000000..df759ab04f0a --- /dev/null +++ b/drivers/media/platform/amphion/vpu_drv.c @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vpu.h" +#include "vpu_imx8q.h" + +void vpu_writel(struct vpu_dev *vpu, u32 reg, u32 val) +{ + writel(val, vpu->base + reg); +} + +u32 vpu_readl(struct vpu_dev *vpu, u32 reg) +{ + return readl(vpu->base + reg); +} + +static void vpu_dev_get(struct vpu_dev *vpu) +{ + if (atomic_inc_return(&vpu->ref_vpu) == 1 && vpu->res->setup) + vpu->res->setup(vpu); +} + +static void vpu_dev_put(struct vpu_dev *vpu) +{ + atomic_dec(&vpu->ref_vpu); +} + +static void vpu_enc_get(struct vpu_dev *vpu) +{ + if (atomic_inc_return(&vpu->ref_enc) == 1 && vpu->res->setup_encoder) + vpu->res->setup_encoder(vpu); +} + +static void vpu_enc_put(struct vpu_dev *vpu) +{ + atomic_dec(&vpu->ref_enc); +} + +static void vpu_dec_get(struct vpu_dev *vpu) +{ + if (atomic_inc_return(&vpu->ref_dec) == 1 && vpu->res->setup_decoder) + vpu->res->setup_decoder(vpu); +} + +static void vpu_dec_put(struct vpu_dev *vpu) +{ + atomic_dec(&vpu->ref_dec); +} + +static int vpu_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct vpu_dev *vpu; + struct resource *r; + int ret; + + pr_info("vpu probe %s\n", pdev->dev.of_node->name); + vpu = devm_kzalloc(dev, sizeof(*vpu), GFP_KERNEL); + if (!vpu) + return -ENOMEM; + + vpu->pdev = pdev; + vpu->dev = dev; + mutex_init(&vpu->lock); + INIT_LIST_HEAD(&vpu->cores); + platform_set_drvdata(pdev, vpu); + atomic_set(&vpu->ref_vpu, 0); + atomic_set(&vpu->ref_enc, 0); + atomic_set(&vpu->ref_dec, 0); + vpu->get_vpu = vpu_dev_get; + vpu->put_vpu = vpu_dev_put; + vpu->get_enc = vpu_enc_get; + vpu->put_enc = vpu_enc_put; + vpu->get_dec = vpu_dec_get; + vpu->put_dec = vpu_dec_put; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + vpu->base = devm_ioremap_resource(dev, r); + if (IS_ERR(vpu->base)) + return PTR_ERR(vpu->base); + + vpu->res = of_device_get_match_data(dev); + if (!vpu->res) + return -ENODEV; + + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret) + goto err_runtime_disable; + + pm_runtime_put_sync(dev); + + ret = v4l2_device_register(dev, &vpu->v4l2_dev); + if (ret) + goto err_vpu_deinit; + + vpu->debugfs = debugfs_create_dir("amphion_vpu", NULL); + + of_platform_populate(dev->of_node, NULL, NULL, dev); + + return 0; + +err_vpu_deinit: +err_runtime_disable: + pm_runtime_set_suspended(dev); + pm_runtime_disable(dev); + + return ret; +} + +static int vpu_remove(struct platform_device *pdev) +{ + struct vpu_dev *vpu = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + int ret; + + ret = pm_runtime_get_sync(dev); + WARN_ON(ret < 0); + + debugfs_remove_recursive(vpu->debugfs); + vpu->debugfs = NULL; + + pm_runtime_put_sync(dev); + pm_runtime_disable(dev); + + v4l2_device_unregister(&vpu->v4l2_dev); + mutex_destroy(&vpu->lock); + + return 0; +} + +static int __maybe_unused vpu_runtime_resume(struct device *dev) +{ + return 0; +} + +static int __maybe_unused vpu_runtime_suspend(struct device *dev) +{ + return 0; +} + +static int __maybe_unused vpu_resume(struct device *dev) +{ + return 0; +} + +static int __maybe_unused vpu_suspend(struct device *dev) +{ + return 0; +} + +static const struct dev_pm_ops vpu_pm_ops = { + SET_RUNTIME_PM_OPS(vpu_runtime_suspend, vpu_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(vpu_suspend, vpu_resume) +}; + +struct vpu_resources imx8qxp_res = { + .plat_type = IMX8QXP, + .mreg_base = 0x40000000, + .setup = vpu_imx8q_setup, + .setup_encoder = vpu_imx8q_setup_enc, + .setup_decoder = vpu_imx8q_setup_dec, + .reset = vpu_imx8q_reset +}; + +struct vpu_resources imx8qm_res = { + .plat_type = IMX8QM, + .mreg_base = 0x40000000, + .setup = vpu_imx8q_setup, + .setup_encoder = vpu_imx8q_setup_enc, + .setup_decoder = vpu_imx8q_setup_dec, + .reset = vpu_imx8q_reset +}; + +static const struct of_device_id vpu_dt_match[] = { + { .compatible = "nxp,imx8qxp-vpu", .data = &imx8qxp_res }, + { .compatible = "nxp,imx8qm-vpu", .data = &imx8qm_res }, + {} +}; +MODULE_DEVICE_TABLE(of, vpu_dt_match); + +static struct platform_driver amphion_vpu_driver = { + .probe = vpu_probe, + .remove = vpu_remove, + .driver = { + .name = "amphion-vpu", + .of_match_table = vpu_dt_match, + .pm = &vpu_pm_ops, + }, +}; +module_platform_driver(amphion_vpu_driver); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Linux VPU driver for Freescale i.MX8Q"); +MODULE_LICENSE("GPL v2"); From patchwork Tue Sep 7 09:49:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Qian X-Patchwork-Id: 507652 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A3CCC433F5 for ; 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dkim=none (message not signed) header.d=none; kernel.org; dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) by AS8PR04MB7767.eurprd04.prod.outlook.com (2603:10a6:20b:288::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4500.14; Tue, 7 Sep 2021 09:50:18 +0000 Received: from AM6PR04MB6341.eurprd04.prod.outlook.com ([fe80::998c:7f25:6d75:d5f4]) by AM6PR04MB6341.eurprd04.prod.outlook.com ([fe80::998c:7f25:6d75:d5f4%7]) with mapi id 15.20.4478.025; Tue, 7 Sep 2021 09:50:17 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v8 07/15] media: amphion: implement vpu core communication based on mailbox Date: Tue, 7 Sep 2021 17:49:14 +0800 Message-Id: <978f68de22b817107bd84488870073ec79ea0128.1631002447.git.ming.qian@nxp.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: X-ClientProxiedBy: SG2PR02CA0097.apcprd02.prod.outlook.com (2603:1096:4:92::13) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by SG2PR02CA0097.apcprd02.prod.outlook.com (2603:1096:4:92::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4478.19 via Frontend Transport; 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Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- drivers/media/platform/amphion/vpu_cmds.c | 435 ++++++++++++++++++++++ drivers/media/platform/amphion/vpu_cmds.h | 25 ++ drivers/media/platform/amphion/vpu_mbox.c | 126 +++++++ drivers/media/platform/amphion/vpu_mbox.h | 16 + drivers/media/platform/amphion/vpu_msgs.c | 413 ++++++++++++++++++++ drivers/media/platform/amphion/vpu_msgs.h | 14 + 6 files changed, 1029 insertions(+) create mode 100644 drivers/media/platform/amphion/vpu_cmds.c create mode 100644 drivers/media/platform/amphion/vpu_cmds.h create mode 100644 drivers/media/platform/amphion/vpu_mbox.c create mode 100644 drivers/media/platform/amphion/vpu_mbox.h create mode 100644 drivers/media/platform/amphion/vpu_msgs.c create mode 100644 drivers/media/platform/amphion/vpu_msgs.h diff --git a/drivers/media/platform/amphion/vpu_cmds.c b/drivers/media/platform/amphion/vpu_cmds.c new file mode 100644 index 000000000000..01a79ff9eec6 --- /dev/null +++ b/drivers/media/platform/amphion/vpu_cmds.c @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2021 NXP + */ + +#define TAG "CMD" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vpu.h" +#include "vpu_defs.h" +#include "vpu_cmds.h" +#include "vpu_rpc.h" +#include "vpu_mbox.h" +#include "vpu_log.h" + +struct vpu_cmd_request { + u32 request; + u32 response; + u32 handled; +}; + +struct vpu_cmd_t { + struct list_head list; + u32 id; + struct vpu_cmd_request *request; + struct vpu_rpc_event *pkt; + unsigned long key; +}; + +static struct vpu_cmd_request vpu_cmd_requests[] = { + { + .request = VPU_CMD_ID_CONFIGURE_CODEC, + .response = VPU_MSG_ID_MEM_REQUEST, + .handled = 1, + }, + { + .request = VPU_CMD_ID_START, + .response = VPU_MSG_ID_START_DONE, + .handled = 0, + }, + { + .request = VPU_CMD_ID_STOP, + .response = VPU_MSG_ID_STOP_DONE, + .handled = 0, + }, + { + .request = VPU_CMD_ID_ABORT, + .response = VPU_MSG_ID_ABORT_DONE, + .handled = 0, + }, + { + .request = VPU_CMD_ID_RST_BUF, + .response = VPU_MSG_ID_BUF_RST, + .handled = 1, + }, +}; + +static int vpu_cmd_send(struct vpu_core *core, struct vpu_rpc_event *pkt) +{ + int ret = 0; + + WARN_ON(!core || !pkt); + + ret = vpu_iface_send_cmd(core, pkt); + if (ret) + return ret; + + /*write cmd data to cmd buffer before trigger a cmd interrupt*/ + mb(); + vpu_mbox_send_type(core, COMMAND); + + return ret; +} + +static struct vpu_cmd_t *vpu_alloc_cmd(struct vpu_inst *inst, u32 id, void *data) +{ + struct vpu_cmd_t *cmd; + int i; + int ret; + + cmd = vzalloc(sizeof(*cmd)); + if (!cmd) + return NULL; + + cmd->pkt = vzalloc(sizeof(*cmd->pkt)); + if (!cmd->pkt) { + vfree(cmd); + return NULL; + } + + cmd->id = id; + ret = vpu_iface_pack_cmd(inst->core, cmd->pkt, inst->id, id, data); + if (ret) { + inst_err(inst, "iface pack cmd(%d) fail\n", id); + vfree(cmd->pkt); + vfree(cmd); + return NULL; + } + for (i = 0; i < ARRAY_SIZE(vpu_cmd_requests); i++) { + if (vpu_cmd_requests[i].request == id) { + cmd->request = &vpu_cmd_requests[i]; + break; + } + } + + return cmd; +} + +static void vpu_free_cmd(struct vpu_cmd_t *cmd) +{ + if (!cmd) + return; + if (cmd->pkt) + vfree(cmd->pkt); + vfree(cmd); +} + +static int vpu_session_process_cmd(struct vpu_inst *inst, struct vpu_cmd_t *cmd) +{ + int ret; + + if (!inst || !cmd || !cmd->pkt) + return -EINVAL; + + inst_dbg(inst, LVL_CMD, "send cmd(0x%x)\n", cmd->id); + vpu_iface_pre_send_cmd(inst); + ret = vpu_cmd_send(inst->core, cmd->pkt); + if (!ret) { + vpu_iface_post_send_cmd(inst); + vpu_inst_record_flow(inst, cmd->id); + } else { + inst_err(inst, "iface send cmd(0x%x) fail\n", cmd->id); + } + + return ret; +} + +static void vpu_process_cmd_request(struct vpu_inst *inst) +{ + struct vpu_cmd_t *cmd; + struct vpu_cmd_t *tmp; + + if (!inst || inst->pending) + return; + + list_for_each_entry_safe(cmd, tmp, &inst->cmd_q, list) { + list_del_init(&cmd->list); + if (vpu_session_process_cmd(inst, cmd)) + inst_err(inst, "process cmd(%d) fail\n", cmd->id); + if (cmd->request) { + inst->pending = (void *)cmd; + break; + } + vpu_free_cmd(cmd); + } +} + +static int vpu_request_cmd(struct vpu_inst *inst, u32 id, void *data, + unsigned long *key, int *sync) +{ + struct vpu_core *core; + struct vpu_cmd_t *cmd; + + if (!inst || !inst->core) + return -EINVAL; + + core = inst->core; + cmd = vpu_alloc_cmd(inst, id, data); + if (!cmd) + return -ENOMEM; + + mutex_lock(&core->cmd_lock); + cmd->key = core->cmd_seq++; + if (key) + *key = cmd->key; + if (sync) + *sync = cmd->request ? true : false; + list_add_tail(&cmd->list, &inst->cmd_q); + vpu_process_cmd_request(inst); + mutex_unlock(&core->cmd_lock); + + return 0; +} + +static void vpu_clear_pending(struct vpu_inst *inst) +{ + if (!inst || !inst->pending) + return; + + vpu_free_cmd(inst->pending); + wake_up_all(&inst->core->ack_wq); + inst->pending = NULL; +} + +static bool vpu_check_response(struct vpu_cmd_t *cmd, u32 response, u32 handled) +{ + struct vpu_cmd_request *request; + + if (!cmd || !cmd->request) + return false; + + request = cmd->request; + if (request->response != response) + return false; + if (request->handled != handled) + return false; + + return true; +} + +int vpu_response_cmd(struct vpu_inst *inst, u32 response, u32 handled) +{ + struct vpu_core *core; + + if (!inst || !inst->core) + return -EINVAL; + + core = inst->core; + mutex_lock(&core->cmd_lock); + if (vpu_check_response(inst->pending, response, handled)) + vpu_clear_pending(inst); + + vpu_process_cmd_request(inst); + mutex_unlock(&core->cmd_lock); + + return 0; +} + +void vpu_clear_request(struct vpu_inst *inst) +{ + struct vpu_cmd_t *cmd; + struct vpu_cmd_t *tmp; + + mutex_lock(&inst->core->cmd_lock); + if (inst->pending) + vpu_clear_pending(inst); + + list_for_each_entry_safe(cmd, tmp, &inst->cmd_q, list) { + list_del_init(&cmd->list); + vpu_free_cmd(cmd); + } + mutex_unlock(&inst->core->cmd_lock); +} + +static bool check_is_responsed(struct vpu_inst *inst, unsigned long key) +{ + struct vpu_core *core = inst->core; + struct vpu_cmd_t *cmd; + bool flag = true; + + mutex_lock(&core->cmd_lock); + cmd = inst->pending; + if (cmd && key == cmd->key) { + flag = false; + goto exit; + } + list_for_each_entry(cmd, &inst->cmd_q, list) { + if (key == cmd->key) { + flag = false; + break; + } + } +exit: + mutex_unlock(&core->cmd_lock); + + return flag; +} + +static int sync_session_response(struct vpu_inst *inst, unsigned long key) +{ + struct vpu_core *core; + + if (!inst || !inst->core) + return -EINVAL; + + core = inst->core; + + call_vop(inst, wait_prepare); + wait_event_timeout(core->ack_wq, + check_is_responsed(inst, key), + VPU_TIMEOUT); + call_vop(inst, wait_finish); + + if (!check_is_responsed(inst, key)) { + inst_err(inst, "sync session timeout\n"); + set_bit(inst->id, &core->hang_mask); + mutex_lock(&inst->core->cmd_lock); + vpu_clear_pending(inst); + mutex_unlock(&inst->core->cmd_lock); + return -EINVAL; + } + + return 0; +} + +static int vpu_session_send_cmd(struct vpu_inst *inst, u32 id, void *data) +{ + unsigned long key; + int sync = false; + int ret = -EINVAL; + + WARN_ON(!inst || !inst->core || inst->id < 0); + + ret = vpu_request_cmd(inst, id, data, &key, &sync); + if (!ret && sync) + ret = sync_session_response(inst, key); + + if (ret) + inst_err(inst, "send cmd(0x%x) fail\n", id); + + return ret; +} + +int vpu_session_configure_codec(struct vpu_inst *inst) +{ + return vpu_session_send_cmd(inst, VPU_CMD_ID_CONFIGURE_CODEC, NULL); +} + +int vpu_session_start(struct vpu_inst *inst) +{ + inst_dbg(inst, LVL_FLOW, "send start cmd\n"); + + return vpu_session_send_cmd(inst, VPU_CMD_ID_START, NULL); +} + +int vpu_session_stop(struct vpu_inst *inst) +{ + inst_dbg(inst, LVL_FLOW, "send stop cmd\n"); + + return vpu_session_send_cmd(inst, VPU_CMD_ID_STOP, NULL); +} + +int vpu_session_encode_frame(struct vpu_inst *inst, s64 timestamp) +{ + return vpu_session_send_cmd(inst, VPU_CMD_ID_FRAME_ENCODE, ×tamp); +} + +int vpu_session_alloc_fs(struct vpu_inst *inst, struct vpu_fs_info *fs) +{ + return vpu_session_send_cmd(inst, VPU_CMD_ID_FS_ALLOC, fs); +} + +int vpu_session_release_fs(struct vpu_inst *inst, struct vpu_fs_info *fs) +{ + return vpu_session_send_cmd(inst, VPU_CMD_ID_FS_RELEASE, fs); +} + +int vpu_session_abort(struct vpu_inst *inst) +{ + return vpu_session_send_cmd(inst, VPU_CMD_ID_ABORT, NULL); +} + +int vpu_session_rst_buf(struct vpu_inst *inst) +{ + return vpu_session_send_cmd(inst, VPU_CMD_ID_RST_BUF, NULL); +} + +int vpu_session_fill_timestamp(struct vpu_inst *inst, struct vpu_ts_info *info) +{ + return vpu_session_send_cmd(inst, VPU_CMD_ID_TIMESTAMP, info); +} + +int vpu_session_update_parameters(struct vpu_inst *inst, void *arg) +{ + if (inst->type & VPU_CORE_TYPE_DEC) + vpu_iface_set_decode_params(inst, arg, 1); + else + vpu_iface_set_encode_params(inst, arg, 1); + + return vpu_session_send_cmd(inst, VPU_CMD_ID_UPDATE_PARAMETER, arg); +} + +int vpu_session_debug(struct vpu_inst *inst) +{ + return vpu_session_send_cmd(inst, VPU_CMD_ID_DEBUG, NULL); +} + +int vpu_core_snapshot(struct vpu_core *core) +{ + struct vpu_inst *inst; + int ret; + + WARN_ON(!core || list_empty(&core->instances)); + + inst = list_first_entry(&core->instances, struct vpu_inst, list); + + reinit_completion(&core->cmp); + ret = vpu_session_send_cmd(inst, VPU_CMD_ID_SNAPSHOT, NULL); + if (ret) + return ret; + ret = wait_for_completion_timeout(&core->cmp, VPU_TIMEOUT); + if (!ret) { + vpu_err("core[%d] snapshot timeout\n", core->id); + return -EINVAL; + } + + return 0; +} + +int vpu_core_sw_reset(struct vpu_core *core) +{ + struct vpu_rpc_event pkt; + int ret; + + WARN_ON(!core); + + memset(&pkt, 0, sizeof(pkt)); + vpu_iface_pack_cmd(core, &pkt, 0, VPU_CMD_ID_FIRM_RESET, NULL); + + reinit_completion(&core->cmp); + mutex_lock(&core->cmd_lock); + ret = vpu_cmd_send(core, &pkt); + mutex_unlock(&core->cmd_lock); + if (ret) + return ret; + ret = wait_for_completion_timeout(&core->cmp, VPU_TIMEOUT); + if (!ret) { + vpu_err("core[%d] sw reset timeout\n", core->id); + return -EINVAL; + } + + return 0; +} diff --git a/drivers/media/platform/amphion/vpu_cmds.h b/drivers/media/platform/amphion/vpu_cmds.h new file mode 100644 index 000000000000..bc538d277bc9 --- /dev/null +++ b/drivers/media/platform/amphion/vpu_cmds.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2020-2021 NXP + */ + +#ifndef _AMPHION_VPU_CMDS_H +#define _AMPHION_VPU_CMDS_H + +int vpu_session_configure_codec(struct vpu_inst *inst); +int vpu_session_start(struct vpu_inst *inst); +int vpu_session_stop(struct vpu_inst *inst); +int vpu_session_abort(struct vpu_inst *inst); +int vpu_session_rst_buf(struct vpu_inst *inst); +int vpu_session_encode_frame(struct vpu_inst *inst, s64 timestamp); +int vpu_session_alloc_fs(struct vpu_inst *inst, struct vpu_fs_info *fs); +int vpu_session_release_fs(struct vpu_inst *inst, struct vpu_fs_info *fs); +int vpu_session_fill_timestamp(struct vpu_inst *inst, struct vpu_ts_info *info); +int vpu_session_update_parameters(struct vpu_inst *inst, void *arg); +int vpu_core_snapshot(struct vpu_core *core); +int vpu_core_sw_reset(struct vpu_core *core); +int vpu_response_cmd(struct vpu_inst *inst, u32 response, u32 handled); +void vpu_clear_request(struct vpu_inst *inst); +int vpu_session_debug(struct vpu_inst *inst); + +#endif diff --git a/drivers/media/platform/amphion/vpu_mbox.c b/drivers/media/platform/amphion/vpu_mbox.c new file mode 100644 index 000000000000..5f926837932f --- /dev/null +++ b/drivers/media/platform/amphion/vpu_mbox.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2021 NXP + */ + +#define TAG "MBOX" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vpu.h" +#include "vpu_mbox.h" +#include "vpu_msgs.h" +#include "vpu_log.h" + +static void vpu_mbox_rx_callback(struct mbox_client *cl, void *msg) +{ + struct vpu_mbox *rx = container_of(cl, struct vpu_mbox, cl); + struct vpu_core *core = container_of(rx, struct vpu_core, rx); + + vpu_isr(core, *(u32 *)msg); +} + +static int vpu_mbox_request_channel(struct device *dev, struct vpu_mbox *mbox) +{ + struct mbox_chan *ch; + struct mbox_client *cl; + + if (!dev || !mbox) + return -EINVAL; + if (mbox->ch) + return 0; + + cl = &mbox->cl; + cl->dev = dev; + if (mbox->block) { + cl->tx_block = true; + cl->tx_tout = 1000; + } else { + cl->tx_block = false; + } + cl->knows_txdone = false; + cl->rx_callback = vpu_mbox_rx_callback; + + ch = mbox_request_channel_byname(cl, mbox->name); + if (IS_ERR(ch)) { + vpu_err("Failed to request mbox chan %s, ret : %ld\n", + mbox->name, PTR_ERR(ch)); + return PTR_ERR(ch); + } + + mbox->ch = ch; + return 0; +} + +int vpu_mbox_init(struct vpu_core *core) +{ + WARN_ON(!core); + + scnprintf(core->tx_type.name, sizeof(core->tx_type.name) - 1, "tx0"); + core->tx_type.block = true; + + scnprintf(core->tx_data.name, sizeof(core->tx_data.name) - 1, "tx1"); + core->tx_data.block = false; + + scnprintf(core->rx.name, sizeof(core->rx.name) - 1, "rx"); + core->rx.block = true; + + return 0; +} + +int vpu_mbox_request(struct vpu_core *core) +{ + int ret; + + WARN_ON(!core); + + ret = vpu_mbox_request_channel(core->dev, &core->tx_type); + if (ret) + goto error; + ret = vpu_mbox_request_channel(core->dev, &core->tx_data); + if (ret) + goto error; + ret = vpu_mbox_request_channel(core->dev, &core->rx); + if (ret) + goto error; + + vpu_dbg(LVL_DEBUG, "mbox request\n"); + return 0; +error: + vpu_mbox_free(core); + return ret; +} + +void vpu_mbox_free(struct vpu_core *core) +{ + WARN_ON(!core); + + mbox_free_channel(core->tx_type.ch); + mbox_free_channel(core->tx_data.ch); + mbox_free_channel(core->rx.ch); + core->tx_type.ch = NULL; + core->tx_data.ch = NULL; + core->rx.ch = NULL; + vpu_dbg(LVL_DEBUG, "mbox free\n"); +} + +void vpu_mbox_send_type(struct vpu_core *core, u32 type) +{ + mbox_send_message(core->tx_type.ch, &type); +} + +void vpu_mbox_send_msg(struct vpu_core *core, u32 type, u32 data) +{ + mbox_send_message(core->tx_data.ch, &data); + mbox_send_message(core->tx_type.ch, &type); +} + +void vpu_mbox_enable_rx(struct vpu_dev *dev) +{ +} diff --git a/drivers/media/platform/amphion/vpu_mbox.h b/drivers/media/platform/amphion/vpu_mbox.h new file mode 100644 index 000000000000..79cfd874e92b --- /dev/null +++ b/drivers/media/platform/amphion/vpu_mbox.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2020-2021 NXP + */ + +#ifndef _AMPHION_VPU_MBOX_H +#define _AMPHION_VPU_MBOX_H + +int vpu_mbox_init(struct vpu_core *core); +int vpu_mbox_request(struct vpu_core *core); +void vpu_mbox_free(struct vpu_core *core); +void vpu_mbox_send_msg(struct vpu_core *core, u32 type, u32 data); +void vpu_mbox_send_type(struct vpu_core *core, u32 type); +void vpu_mbox_enable_rx(struct vpu_dev *dev); + +#endif diff --git a/drivers/media/platform/amphion/vpu_msgs.c b/drivers/media/platform/amphion/vpu_msgs.c new file mode 100644 index 000000000000..8938fd27a5eb --- /dev/null +++ b/drivers/media/platform/amphion/vpu_msgs.c @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2021 NXP + */ + +#define TAG "MSG" + +#include +#include +#include +#include +#include +#include +#include "vpu.h" +#include "vpu_core.h" +#include "vpu_rpc.h" +#include "vpu_mbox.h" +#include "vpu_defs.h" +#include "vpu_cmds.h" +#include "vpu_msgs.h" +#include "vpu_v4l2.h" +#include "vpu_log.h" + +#define VPU_PKT_HEADER_LENGTH 3 + +struct vpu_msg_handler { + u32 id; + void (*done)(struct vpu_inst *inst, struct vpu_rpc_event *pkt); +}; + +static void vpu_session_handle_start_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + WARN_ON(!inst || !inst->core); + + inst_dbg(inst, LVL_FLOW, "start done\n"); +} + +static void vpu_session_handle_mem_request(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + struct vpu_pkt_mem_req_data req_data; + + WARN_ON(!inst || !inst->core || !inst->ops); + + vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&req_data); + inst_dbg(inst, LVL_FLOW, "mem request event : %d:%d %d:%d %d:%d\n", + req_data.enc_frame_size, + req_data.enc_frame_num, + req_data.ref_frame_size, + req_data.ref_frame_num, + req_data.act_buf_size, + req_data.act_buf_num); + call_vop(inst, mem_request, + req_data.enc_frame_size, + req_data.enc_frame_num, + req_data.ref_frame_size, + req_data.ref_frame_num, + req_data.act_buf_size, + req_data.act_buf_num); +} + +static void vpu_session_handle_stop_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + WARN_ON(!inst || !inst->core); + + inst_dbg(inst, LVL_FLOW, "stop done\n"); + + call_vop(inst, stop_done); +} + +static void vpu_session_handle_seq_hdr(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + struct vpu_dec_codec_info info; + + WARN_ON(!inst || !inst->core); + + info.stride = inst->core->res->stride; + vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info); + call_vop(inst, event_notify, VPU_MSG_ID_SEQ_HDR_FOUND, &info); +} + +static void vpu_session_handle_resolution_change(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + WARN_ON(!inst || !inst->core); + + call_vop(inst, event_notify, VPU_MSG_ID_RES_CHANGE, NULL); +} + +static void vpu_session_handle_enc_frame_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + struct vpu_enc_pic_info info; + + WARN_ON(!inst || !inst->core); + + vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info); + inst_dbg(inst, LVL_DEBUG, "frame id = %d, wptr = 0x%x, size = %d\n", + info.frame_id, info.wptr, info.frame_size); + call_vop(inst, get_one_frame, &info); +} + +static void vpu_session_handle_frame_request(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + struct vpu_fs_info fs; + + vpu_iface_unpack_msg_data(inst->core, pkt, &fs); + call_vop(inst, event_notify, VPU_MSG_ID_FRAME_REQ, &fs); +} + +static void vpu_session_handle_frame_release(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + + WARN_ON(!inst || !inst->core); + + if (inst->core->type == VPU_CORE_TYPE_ENC) { + struct vpu_frame_info info; + + memset(&info, 0, sizeof(info)); + vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info.sequence); + inst_dbg(inst, LVL_DEBUG, "frame release:%d\n", info.sequence); + info.type = inst->out_format.type; + call_vop(inst, buf_done, &info); + } else if (inst->core->type == VPU_CORE_TYPE_DEC) { + struct vpu_fs_info fs; + + vpu_iface_unpack_msg_data(inst->core, pkt, &fs); + call_vop(inst, event_notify, VPU_MSG_ID_FRAME_RELEASE, &fs); + } +} + +static void vpu_session_handle_input_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + + WARN_ON(!inst || !inst->core); + + inst_dbg(inst, LVL_DEBUG, "frame input done\n"); + call_vop(inst, input_done); +} + +static void vpu_session_handle_pic_decoded(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + struct vpu_dec_pic_info info; + + WARN_ON(!inst || !inst->core); + + vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info); + call_vop(inst, get_one_frame, &info); +} + +static void vpu_session_handle_pic_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + struct vpu_dec_pic_info info; + struct vpu_frame_info frame; + + WARN_ON(!inst || !inst->core); + + memset(&frame, 0, sizeof(frame)); + vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info); + if (inst->core->type == VPU_CORE_TYPE_DEC) + frame.type = inst->cap_format.type; + frame.id = info.id; + frame.luma = info.luma; + frame.skipped = info.skipped; + frame.timestamp = info.timestamp; + + call_vop(inst, buf_done, &frame); +} + +static void vpu_session_handle_eos(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + call_vop(inst, event_notify, VPU_MSG_ID_PIC_EOS, NULL); +} + +static void vpu_session_handle_error(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + call_vop(inst, event_notify, VPU_MSG_ID_UNSUPPORTED, NULL); + vpu_notify_codec_error(inst); +} + +static void vpu_session_handle_firmware_xcpt(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + char *str = (char *)pkt->data; + + inst_err(inst, "%s firmware xcpt: %s\n", + vpu_core_type_desc(inst->core->type), str); + call_vop(inst, event_notify, VPU_MSG_ID_FIRMWARE_XCPT, NULL); + set_bit(inst->id, &inst->core->hang_mask); + vpu_notify_codec_error(inst); +} + +struct vpu_msg_handler handlers[] = { + {VPU_MSG_ID_START_DONE, vpu_session_handle_start_done}, + {VPU_MSG_ID_STOP_DONE, vpu_session_handle_stop_done}, + {VPU_MSG_ID_MEM_REQUEST, vpu_session_handle_mem_request}, + {VPU_MSG_ID_SEQ_HDR_FOUND, vpu_session_handle_seq_hdr}, + {VPU_MSG_ID_RES_CHANGE, vpu_session_handle_resolution_change}, + {VPU_MSG_ID_FRAME_INPUT_DONE, vpu_session_handle_input_done}, + {VPU_MSG_ID_FRAME_REQ, vpu_session_handle_frame_request}, + {VPU_MSG_ID_FRAME_RELEASE, vpu_session_handle_frame_release}, + {VPU_MSG_ID_ENC_DONE, vpu_session_handle_enc_frame_done}, + {VPU_MSG_ID_PIC_DECODED, vpu_session_handle_pic_decoded}, + {VPU_MSG_ID_DEC_DONE, vpu_session_handle_pic_done}, + {VPU_MSG_ID_PIC_EOS, vpu_session_handle_eos}, + {VPU_MSG_ID_UNSUPPORTED, vpu_session_handle_error}, + {VPU_MSG_ID_FIRMWARE_XCPT, vpu_session_handle_firmware_xcpt}, +}; + +static int vpu_session_handle_msg(struct vpu_inst *inst, struct vpu_rpc_event *msg) +{ + int ret; + u32 msg_id; + struct vpu_msg_handler *handler = NULL; + unsigned int i; + + ret = vpu_iface_convert_msg_id(inst->core, msg->hdr.id); + if (ret < 0) + return -EINVAL; + + msg_id = ret; + inst_dbg(inst, LVL_EVT, "receive event(0x%x)\n", msg_id); + + for (i = 0; i < ARRAY_SIZE(handlers); i++) { + if (handlers[i].id == msg_id) { + handler = &handlers[i]; + break; + } + } + + if (handler && handler->done) + handler->done(inst, msg); + + vpu_response_cmd(inst, msg_id, 1); + + return 0; +} + +static bool vpu_inst_receive_msg(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + u32 bytes = sizeof(struct vpu_rpc_event_header); + u32 ret; + + memset(pkt, 0, sizeof(*pkt)); + if (kfifo_len(&inst->msg_fifo) < bytes) + return false; + + ret = kfifo_out(&inst->msg_fifo, pkt, bytes); + if (ret != bytes) + return false; + + if (pkt->hdr.num > 0) { + bytes = pkt->hdr.num * sizeof(u32); + ret = kfifo_out(&inst->msg_fifo, pkt->data, bytes); + if (ret != bytes) + return false; + } + + return true; +} + +void vpu_inst_run_work(struct work_struct *work) +{ + struct vpu_inst *inst = container_of(work, struct vpu_inst, msg_work); + struct vpu_rpc_event pkt; + + while (vpu_inst_receive_msg(inst, &pkt)) + vpu_session_handle_msg(inst, &pkt); +} + +static void vpu_inst_handle_msg(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + u32 bytes; + u32 id = pkt->hdr.id; + int ret; + + if (!inst->workqueue) { + vpu_session_handle_msg(inst, pkt); + return; + } + + bytes = sizeof(pkt->hdr) + pkt->hdr.num * sizeof(u32); + ret = kfifo_in(&inst->msg_fifo, pkt, bytes); + if (ret != bytes) + vpu_err("[%d:%d]overflow: %d\n", inst->core->id, inst->id, id); + queue_work(inst->workqueue, &inst->msg_work); +} + +static int vpu_handle_msg(struct vpu_core *core) +{ + struct vpu_rpc_event pkt; + struct vpu_inst *inst; + int ret; + + memset(&pkt, 0, sizeof(pkt)); + while (!vpu_iface_receive_msg(core, &pkt)) { + vpu_dbg(LVL_DEBUG, "event index = %d, id = %d, num = %d\n", + pkt.hdr.index, pkt.hdr.id, pkt.hdr.num); + + ret = vpu_iface_convert_msg_id(core, pkt.hdr.id); + if (ret < 0) + continue; + + inst = vpu_core_find_instance(core, pkt.hdr.index); + if (inst) { + vpu_response_cmd(inst, ret, 0); + mutex_lock(&core->cmd_lock); + vpu_inst_record_flow(inst, ret); + mutex_unlock(&core->cmd_lock); + + vpu_inst_handle_msg(inst, &pkt); + vpu_inst_put(inst); + } + memset(&pkt, 0, sizeof(pkt)); + } + + return 0; +} + +static int vpu_isr_thread(struct vpu_core *core, u32 irq_code) +{ + WARN_ON(!core); + + vpu_dbg(LVL_DEBUG, "core[%d] irq code = 0x%x\n", core->id, irq_code); + switch (irq_code) { + case VPU_IRQ_CODE_SYNC: + vpu_mbox_send_msg(core, PRC_BUF_OFFSET, core->rpc.phys - core->fw.phys); + vpu_mbox_send_msg(core, BOOT_ADDRESS, core->fw.phys); + vpu_mbox_send_msg(core, INIT_DONE, 2); + break; + case VPU_IRQ_CODE_BOOT_DONE: + break; + case VPU_IRQ_CODE_SNAPSHOT_DONE: + break; + default: + vpu_handle_msg(core); + break; + } + + return 0; +} + +static void vpu_core_run_msg_work(struct vpu_core *core) +{ + const unsigned int SIZE = sizeof(u32); + + while (kfifo_len(&core->msg_fifo) >= SIZE) { + u32 data; + + if (kfifo_out(&core->msg_fifo, &data, SIZE) == SIZE) + vpu_isr_thread(core, data); + } +} + +void vpu_msg_run_work(struct work_struct *work) +{ + struct vpu_core *core = container_of(work, struct vpu_core, msg_work); + unsigned long delay = msecs_to_jiffies(10); + + vpu_core_run_msg_work(core); + queue_delayed_work(core->workqueue, &core->msg_delayed_work, delay); +} + +void vpu_msg_delayed_work(struct work_struct *work) +{ + struct vpu_core *core; + struct delayed_work *dwork; + u32 bytes = sizeof(bytes); + u32 i; + + if (!work) + return; + + dwork = to_delayed_work(work); + core = container_of(dwork, struct vpu_core, msg_delayed_work); + if (kfifo_len(&core->msg_fifo) >= bytes) + vpu_core_run_msg_work(core); + + bytes = sizeof(struct vpu_rpc_event_header); + for (i = 0; i < core->supported_instance_count; i++) { + struct vpu_inst *inst = vpu_core_find_instance(core, i); + + if (!inst) + continue; + + if (inst->workqueue && kfifo_len(&inst->msg_fifo) >= bytes) + queue_work(inst->workqueue, &inst->msg_work); + + vpu_inst_put(inst); + } +} + + +int vpu_isr(struct vpu_core *core, u32 irq) +{ + WARN_ON(!core); + + vpu_dbg(LVL_DEBUG, "core[%d] irq code = 0x%x\n", core->id, irq); + switch (irq) { + case VPU_IRQ_CODE_SYNC: + break; + case VPU_IRQ_CODE_BOOT_DONE: + complete(&core->cmp); + break; + case VPU_IRQ_CODE_SNAPSHOT_DONE: + complete(&core->cmp); + break; + default: + break; + } + + if (kfifo_in(&core->msg_fifo, &irq, sizeof(irq)) != sizeof(irq)) + vpu_err("[%d]overflow: %d\n", core->id, irq); + queue_work(core->workqueue, &core->msg_work); + + return 0; +} diff --git a/drivers/media/platform/amphion/vpu_msgs.h b/drivers/media/platform/amphion/vpu_msgs.h new file mode 100644 index 000000000000..c466b4f62aad --- /dev/null +++ b/drivers/media/platform/amphion/vpu_msgs.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2020-2021 NXP + */ + +#ifndef _AMPHION_VPU_MSGS_H +#define _AMPHION_VPU_MSGS_H + +int vpu_isr(struct vpu_core *core, u32 irq); +void vpu_inst_run_work(struct work_struct *work); +void vpu_msg_run_work(struct work_struct *work); +void vpu_msg_delayed_work(struct work_struct *work); + +#endif From patchwork Tue Sep 7 09:49:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Qian X-Patchwork-Id: 507651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87DF3C433FE for ; Tue, 7 Sep 2021 09:50:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6F1AA610FE for ; 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ITU-R BT.709-6*/ + 0, + 0, + V4L2_COLORSPACE_470_SYSTEM_M, /*Rec. ITU-R BT.470-6 System M*/ + V4L2_COLORSPACE_470_SYSTEM_BG,/*Rec. ITU-R BT.470-6 System B, G*/ + V4L2_COLORSPACE_SMPTE170M, /*SMPTE170M*/ + V4L2_COLORSPACE_SMPTE240M, /*SMPTE240M*/ + 0, /*Generic film*/ + V4L2_COLORSPACE_BT2020, /*Rec. ITU-R BT.2020-2*/ + 0, /*SMPTE ST 428-1*/ +}; + +static const u8 colortransfers[] = { + 0, + V4L2_XFER_FUNC_709, /*Rec. ITU-R BT.709-6*/ + 0, + 0, + 0, /*Rec. ITU-R BT.470-6 System M*/ + 0, /*Rec. ITU-R BT.470-6 System B, G*/ + V4L2_XFER_FUNC_709, /*SMPTE170M*/ + V4L2_XFER_FUNC_SMPTE240M,/*SMPTE240M*/ + V4L2_XFER_FUNC_NONE, /*Linear transfer characteristics*/ + 0, + 0, + 0, /*IEC 61966-2-4*/ + 0, /*Rec. ITU-R BT.1361-0 extended colour gamut*/ + V4L2_XFER_FUNC_SRGB, /*IEC 61966-2-1 sRGB or sYCC*/ + V4L2_XFER_FUNC_709, /*Rec. ITU-R BT.2020-2 (10 bit system)*/ + V4L2_XFER_FUNC_709, /*Rec. ITU-R BT.2020-2 (12 bit system)*/ + V4L2_XFER_FUNC_SMPTE2084,/*SMPTE ST 2084*/ + 0, /*SMPTE ST 428-1*/ + 0 /*Rec. ITU-R BT.2100-0 hybrid log-gamma (HLG)*/ +}; + +static const u8 colormatrixcoefs[] = { + 0, + V4L2_YCBCR_ENC_709, /*Rec. ITU-R BT.709-6*/ + 0, + 0, + 0, /*Title 47 Code of Federal Regulations*/ + V4L2_YCBCR_ENC_601, /*Rec. ITU-R BT.601-7 625*/ + V4L2_YCBCR_ENC_601, /*Rec. ITU-R BT.601-7 525*/ + V4L2_YCBCR_ENC_SMPTE240M, /*SMPTE240M*/ + 0, + V4L2_YCBCR_ENC_BT2020, /*Rec. ITU-R BT.2020-2*/ + V4L2_YCBCR_ENC_BT2020_CONST_LUM /*Rec. ITU-R BT.2020-2 constant*/ +}; + +u32 vpu_color_cvrt_primaries_v2i(u32 primaries) +{ + return VPU_ARRAY_FIND(colorprimaries, primaries); +} + +u32 vpu_color_cvrt_primaries_i2v(u32 primaries) +{ + return VPU_ARRAY_AT(colorprimaries, primaries); +} + +u32 vpu_color_cvrt_transfers_v2i(u32 transfers) +{ + return VPU_ARRAY_FIND(colortransfers, transfers); +} + +u32 vpu_color_cvrt_transfers_i2v(u32 transfers) +{ + return VPU_ARRAY_AT(colortransfers, transfers); +} + +u32 vpu_color_cvrt_matrix_v2i(u32 matrix) +{ + return VPU_ARRAY_FIND(colormatrixcoefs, matrix); +} + +u32 vpu_color_cvrt_matrix_i2v(u32 matrix) +{ + return VPU_ARRAY_AT(colormatrixcoefs, matrix); +} + +u32 vpu_color_cvrt_full_range_v2i(u32 full_range) +{ + return (full_range == V4L2_QUANTIZATION_FULL_RANGE); +} + +u32 vpu_color_cvrt_full_range_i2v(u32 full_range) +{ + if (full_range) + return V4L2_QUANTIZATION_FULL_RANGE; + + return V4L2_QUANTIZATION_LIM_RANGE; +} + +int vpu_color_check_primaries(u32 primaries) +{ + return vpu_color_cvrt_primaries_v2i(primaries) ? 0 : -EINVAL; +} + +int vpu_color_check_transfers(u32 transfers) +{ + return vpu_color_cvrt_transfers_v2i(transfers) ? 0 : -EINVAL; +} + +int vpu_color_check_matrix(u32 matrix) +{ + return vpu_color_cvrt_matrix_v2i(matrix) ? 0 : -EINVAL; +} + +int vpu_color_check_full_range(u32 full_range) +{ + int ret = -EINVAL; + + switch (full_range) { + case V4L2_QUANTIZATION_FULL_RANGE: + case V4L2_QUANTIZATION_LIM_RANGE: + ret = 0; + break; + default: + break; + + } + + return ret; +} + +int vpu_color_get_default(u32 primaries, + u32 *ptransfers, u32 *pmatrix, u32 *pfull_range) +{ + u32 transfers; + u32 matrix; + u32 full_range; + + switch (primaries) { + case V4L2_COLORSPACE_REC709: + transfers = V4L2_XFER_FUNC_709; + matrix = V4L2_YCBCR_ENC_709; + full_range = V4L2_QUANTIZATION_LIM_RANGE; + break; + case V4L2_COLORSPACE_470_SYSTEM_M: + case V4L2_COLORSPACE_470_SYSTEM_BG: + case V4L2_COLORSPACE_SMPTE170M: + transfers = V4L2_XFER_FUNC_709; + matrix = V4L2_YCBCR_ENC_601; + full_range = V4L2_QUANTIZATION_LIM_RANGE; + break; + case V4L2_COLORSPACE_SMPTE240M: + transfers = V4L2_XFER_FUNC_SMPTE240M; + matrix = V4L2_YCBCR_ENC_SMPTE240M; + full_range = V4L2_QUANTIZATION_LIM_RANGE; + break; + case V4L2_COLORSPACE_BT2020: + transfers = V4L2_XFER_FUNC_709; + matrix = V4L2_YCBCR_ENC_BT2020; + full_range = V4L2_QUANTIZATION_LIM_RANGE; + break; + default: + transfers = V4L2_XFER_FUNC_709; + matrix = V4L2_YCBCR_ENC_709; + full_range = V4L2_QUANTIZATION_LIM_RANGE; + break; + } + + if (ptransfers) + *ptransfers = transfers; + if (pmatrix) + *pmatrix = matrix; + if (pfull_range) + *pfull_range = full_range; + + + return 0; +} diff --git a/drivers/media/platform/amphion/vpu_helpers.c b/drivers/media/platform/amphion/vpu_helpers.c new file mode 100644 index 000000000000..484575d2975e --- /dev/null +++ b/drivers/media/platform/amphion/vpu_helpers.c @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2021 NXP + */ + +#define TAG "HELPER" +#include +#include +#include +#include +#include +#include +#include +#include "vpu.h" +#include "vpu_core.h" +#include "vpu_rpc.h" +#include "vpu_helpers.h" +#include "vpu_log.h" + +int vpu_helper_find_in_array_u8(const u8 *array, u32 size, u32 x) +{ + int i; + + for (i = 0; i < size; i++) { + if (array[i] == x) + return i; + } + + return 0; +} + +bool vpu_helper_check_type(struct vpu_inst *inst, u32 type) +{ + const struct vpu_format *pfmt; + + for (pfmt = inst->formats; pfmt->pixfmt; pfmt++) { + if (vpu_core_check_fmt(inst->core, pfmt->pixfmt)) + continue; + if (pfmt->type == type) + return true; + } + + return false; +} + +const struct vpu_format *vpu_helper_find_format(struct vpu_inst *inst, u32 type, u32 pixelfmt) +{ + const struct vpu_format *pfmt; + + if (!inst || !inst->formats) + return NULL; + + if (vpu_core_check_fmt(inst->core, pixelfmt)) + return NULL; + + for (pfmt = inst->formats; pfmt->pixfmt; pfmt++) { + if (vpu_core_check_fmt(inst->core, pfmt->pixfmt)) + continue; + + if (pfmt->pixfmt == pixelfmt && (!type || type == pfmt->type)) + return pfmt; + } + + return NULL; +} + +const struct vpu_format *vpu_helper_enum_format(struct vpu_inst *inst, u32 type, int index) +{ + const struct vpu_format *pfmt; + int i = 0; + + if (!inst || !inst->formats) + return NULL; + + for (pfmt = inst->formats; pfmt->pixfmt; pfmt++) { + if (vpu_core_check_fmt(inst->core, pfmt->pixfmt)) + continue; + + if (pfmt->type == type) { + if (index == i) + return pfmt; + i++; + } + } + + return NULL; +} + +u32 vpu_helper_valid_frame_width(struct vpu_inst *inst, u32 width) +{ + const struct vpu_core_resources *res; + + if (!inst || !inst->core || !inst->core->res) + return width; + + res = inst->core->res; + if (res->max_width) + width = clamp(width, res->min_width, res->max_width); + if (res->step_width) + width = ALIGN(width, res->step_width); + + return width; +} + +u32 vpu_helper_valid_frame_height(struct vpu_inst *inst, u32 height) +{ + const struct vpu_core_resources *res; + + if (!inst || !inst->core || !inst->core->res) + return height; + + res = inst->core->res; + if (res->max_height) + height = clamp(height, res->min_height, res->max_height); + if (res->step_height) + height = ALIGN(height, res->step_height); + + return height; +} + +u32 vpu_helper_get_frame_size(u32 fmt, u32 width, u32 height) +{ + switch (fmt) { + case V4L2_PIX_FMT_NV12: + return ((width * 3) >> 1) * height; + default: + return width * height; + } +} + +static u32 get_nv12_plane_size(u32 width, u32 height, int plane_no, + u32 stride, u32 interlaced, u32 *pbl) +{ + u32 bytesperline; + u32 size = 0; + + bytesperline = ALIGN(width, stride); + height = ALIGN(height, 2); + if (plane_no == 0) + size = bytesperline * height; + else + size = bytesperline * height >> 1; + + if (pbl) + *pbl = bytesperline; + + return size; +} + +static u32 get_tiled_8l128_plane_size(u32 fmt, u32 width, u32 height, int plane_no, + u32 stride, u32 interlaced, u32 *pbl) +{ + u32 ws = 3; + u32 hs = 7; + u32 bitdepth = 8; + u32 bytesperline; + u32 size = 0; + + if (interlaced) + hs++; + if (fmt == V4L2_PIX_FMT_NV12_10BE_8L128) + bitdepth = 10; + bytesperline = DIV_ROUND_UP(width * bitdepth, BITS_PER_BYTE); + bytesperline = ALIGN(bytesperline, 1 << ws); + bytesperline = ALIGN(bytesperline, stride); + height = ALIGN(height, 1 << hs); + if (plane_no == 0) + size = bytesperline * height; + else if (plane_no == 1) + size = (bytesperline * ALIGN(height, 1 << (hs + 1))) >> 1; + + if (pbl) + *pbl = bytesperline; + + return size; +} + +static u32 get_default_plane_size(u32 width, u32 height, int plane_no, + u32 stride, u32 interlaced, u32 *pbl) +{ + u32 bytesperline; + u32 size = 0; + + bytesperline = ALIGN(width, stride); + if (plane_no == 0) + size = bytesperline * height; + + if (pbl) + *pbl = bytesperline; + + return size; +} + +u32 vpu_helper_get_plane_size(u32 fmt, u32 w, u32 h, int plane_no, + u32 stride, u32 interlaced, u32 *pbl) +{ + switch (fmt) { + case V4L2_PIX_FMT_NV12: + return get_nv12_plane_size(w, h, plane_no, stride, interlaced, pbl); + case V4L2_PIX_FMT_NV12_8L128: + case V4L2_PIX_FMT_NV12_10BE_8L128: + return get_tiled_8l128_plane_size(fmt, w, h, plane_no, stride, interlaced, pbl); + default: + return get_default_plane_size(w, h, plane_no, stride, interlaced, pbl); + } +} + +u32 vpu_helper_copy_from_stream_buffer(struct vpu_buffer *stream_buffer, + u32 *rptr, u32 size, void *dst) +{ + u32 offset; + u32 start; + u32 end; + void *virt; + + if (!stream_buffer || !rptr || !dst) + return -EINVAL; + + if (!size) + return 0; + + offset = *rptr; + start = stream_buffer->phys; + end = start + stream_buffer->length; + virt = stream_buffer->virt; + + if (offset < start || offset > end) { + vpu_err("rptr 0x%x is out of range [0x%x, 0x%x]\n", + offset, start, end); + return -EINVAL; + } + + if (offset + size <= end) { + memcpy(dst, virt + (offset - start), size); + } else { + memcpy(dst, virt + (offset - start), end - offset); + memcpy(dst + end - offset, virt, size + offset - end); + } + + *rptr = vpu_helper_step_walk(stream_buffer, offset, size); + return size; +} + +u32 vpu_helper_copy_to_stream_buffer(struct vpu_buffer *stream_buffer, + u32 *wptr, u32 size, void *src) +{ + u32 offset; + u32 start; + u32 end; + void *virt; + + if (!stream_buffer || !wptr || !src) + return -EINVAL; + + if (!size) + return 0; + + offset = *wptr; + start = stream_buffer->phys; + end = start + stream_buffer->length; + virt = stream_buffer->virt; + if (offset < start || offset > end) { + vpu_err("wptr 0x%x is out of range [0x%x, 0x%x]\n", + offset, start, end); + return -EINVAL; + } + + if (offset + size <= end) { + memcpy(virt + (offset - start), src, size); + } else { + memcpy(virt + (offset - start), src, end - offset); + memcpy(virt, src + end - offset, size + offset - end); + } + + *wptr = vpu_helper_step_walk(stream_buffer, offset, size); + + return size; +} + +u32 vpu_helper_memset_stream_buffer(struct vpu_buffer *stream_buffer, + u32 *wptr, u8 val, u32 size) +{ + u32 offset; + u32 start; + u32 end; + void *virt; + + if (!stream_buffer || !wptr) + return -EINVAL; + + if (!size) + return 0; + + offset = *wptr; + start = stream_buffer->phys; + end = start + stream_buffer->length; + virt = stream_buffer->virt; + if (offset < start || offset > end) { + vpu_err("wptr 0x%x is out of range [0x%x, 0x%x]\n", + offset, start, end); + return -EINVAL; + } + + if (offset + size <= end) { + memset(virt + (offset - start), val, size); + } else { + memset(virt + (offset - start), val, end - offset); + memset(virt, val, size + offset - end); + } + + offset += size; + if (offset >= end) + offset -= stream_buffer->length; + + *wptr = offset; + + return size; +} + +u32 vpu_helper_get_free_space(struct vpu_inst *inst) +{ + struct vpu_rpc_buffer_desc desc; + + if (vpu_iface_get_stream_buffer_desc(inst, &desc)) + return 0; + + if (desc.rptr > desc.wptr) + return desc.rptr - desc.wptr; + else if (desc.rptr < desc.wptr) + return (desc.end - desc.start + desc.rptr - desc.wptr); + else + return desc.end - desc.start; +} + +u32 vpu_helper_get_used_space(struct vpu_inst *inst) +{ + struct vpu_rpc_buffer_desc desc; + + if (vpu_iface_get_stream_buffer_desc(inst, &desc)) + return 0; + + if (desc.wptr > desc.rptr) + return desc.wptr - desc.rptr; + else if (desc.wptr < desc.rptr) + return (desc.end - desc.start + desc.wptr - desc.rptr); + else + return 0; +} + +int vpu_helper_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct vpu_inst *inst = ctrl_to_inst(ctrl); + + switch (ctrl->id) { + case V4L2_CID_MIN_BUFFERS_FOR_CAPTURE: + ctrl->val = inst->min_buffer_cap; + break; + case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT: + ctrl->val = inst->min_buffer_out; + break; + default: + return -EINVAL; + } + + return 0; +} + +u32 vpu_helper_calc_coprime(u32 *a, u32 *b) +{ + int m = *a; + int n = *b; + + if (m == 0) + return n; + if (n == 0) + return m; + + while (n != 0) { + int tmp = m % n; + + m = n; + n = tmp; + } + *a = (*a) / m; + *b = (*b) / m; + + return m; +} + +#define READ_BYTE(buffer, pos) (*(u8 *)((buffer)->virt + ((pos) % buffer->length))) +int vpu_helper_find_startcode(struct vpu_buffer *stream_buffer, + u32 pixelformat, u32 offset, u32 bytesused) +{ + u32 start_code; + int start_code_size; + u32 val = 0; + int i; + int ret = -EINVAL; + + if (!stream_buffer || !stream_buffer->virt) + return -EINVAL; + + switch (pixelformat) { + case V4L2_PIX_FMT_H264: + start_code_size = 4; + start_code = 0x00000001; + break; + default: + return 0; + } + + for (i = 0; i < bytesused; i++) { + val = (val << 8) | READ_BYTE(stream_buffer, offset + i); + if (i < start_code_size - 1) + continue; + if (val == start_code) { + ret = i + 1 - start_code_size; + break; + } + } + + return ret; +} + +int vpu_find_dst_by_src(struct vpu_pair *pairs, u32 cnt, u32 src) +{ + u32 i; + + if (!pairs || !cnt) + return -EINVAL; + + for (i = 0; i < cnt; i++) { + if (pairs[i].src == src) + return pairs[i].dst; + } + + return -EINVAL; +} + +int vpu_find_src_by_dst(struct vpu_pair *pairs, u32 cnt, u32 dst) +{ + u32 i; + + if (!pairs || !cnt) + return -EINVAL; + + for (i = 0; i < cnt; i++) { + if (pairs[i].dst == dst) + return pairs[i].src; + } + + return -EINVAL; +} diff --git a/drivers/media/platform/amphion/vpu_helpers.h b/drivers/media/platform/amphion/vpu_helpers.h new file mode 100644 index 000000000000..22029eab7b56 --- /dev/null +++ b/drivers/media/platform/amphion/vpu_helpers.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2020-2021 NXP + */ + +#ifndef _AMPHION_VPU_HELPERS_H +#define _AMPHION_VPU_HELPERS_H + +struct vpu_pair { + u32 src; + u32 dst; +}; + +#define MAKE_TIMESTAMP(s, ns) (((s32)(s) * NSEC_PER_SEC) + (ns)) +#define VPU_INVALID_TIMESTAMP MAKE_TIMESTAMP(-1, 0) +#define VPU_ARRAY_AT(array, i) (((i) < ARRAY_SIZE(array)) ? array[i] : 0) +#define VPU_ARRAY_FIND(array, x) vpu_helper_find_in_array_u8(array, ARRAY_SIZE(array), x) + +int vpu_helper_find_in_array_u8(const u8 *array, u32 size, u32 x); +bool vpu_helper_check_type(struct vpu_inst *inst, u32 type); +const struct vpu_format *vpu_helper_find_format(struct vpu_inst *inst, u32 type, u32 pixelfmt); +const struct vpu_format *vpu_helper_enum_format(struct vpu_inst *inst, u32 type, int index); +u32 vpu_helper_valid_frame_width(struct vpu_inst *inst, u32 width); +u32 vpu_helper_valid_frame_height(struct vpu_inst *inst, u32 height); +u32 vpu_helper_get_frame_size(u32 fmt, u32 width, u32 height); +u32 vpu_helper_get_plane_size(u32 fmt, u32 width, u32 height, int plane_no, + u32 stride, u32 interlaced, u32 *pbl); +u32 vpu_helper_copy_from_stream_buffer(struct vpu_buffer *stream_buffer, + u32 *rptr, u32 size, void *dst); +u32 vpu_helper_copy_to_stream_buffer(struct vpu_buffer *stream_buffer, + u32 *wptr, u32 size, void *src); +u32 vpu_helper_memset_stream_buffer(struct vpu_buffer *stream_buffer, + u32 *wptr, u8 val, u32 size); +u32 vpu_helper_get_free_space(struct vpu_inst *inst); +u32 vpu_helper_get_used_space(struct vpu_inst *inst); +int vpu_helper_g_volatile_ctrl(struct v4l2_ctrl *ctrl); +u32 vpu_helper_calc_coprime(u32 *a, u32 *b); +void vpu_helper_get_kmp_next(const u8 *pattern, int *next, int size); +int vpu_helper_kmp_search(u8 *s, int s_len, const u8 *p, int p_len, int *next); +int vpu_helper_kmp_search_in_stream_buffer(struct vpu_buffer *stream_buffer, + u32 offset, int bytesused, + const u8 *p, int p_len, int *next); +int vpu_helper_find_startcode(struct vpu_buffer *stream_buffer, + u32 pixelformat, u32 offset, u32 bytesused); + +static inline u32 vpu_helper_step_walk(struct vpu_buffer *stream_buffer, u32 pos, u32 step) +{ + pos += step; + if (pos > stream_buffer->phys + stream_buffer->length) + pos -= stream_buffer->length; + + return pos; +} + +int vpu_color_check_primaries(u32 primaries); +int vpu_color_check_transfers(u32 transfers); +int vpu_color_check_matrix(u32 matrix); +int vpu_color_check_full_range(u32 full_range); +u32 vpu_color_cvrt_primaries_v2i(u32 primaries); +u32 vpu_color_cvrt_primaries_i2v(u32 primaries); +u32 vpu_color_cvrt_transfers_v2i(u32 transfers); +u32 vpu_color_cvrt_transfers_i2v(u32 transfers); +u32 vpu_color_cvrt_matrix_v2i(u32 matrix); +u32 vpu_color_cvrt_matrix_i2v(u32 matrix); +u32 vpu_color_cvrt_full_range_v2i(u32 full_range); +u32 vpu_color_cvrt_full_range_i2v(u32 full_range); +int vpu_color_get_default(u32 primaries, + u32 *ptransfers, u32 *pmatrix, u32 *pfull_range); + +int vpu_find_dst_by_src(struct vpu_pair *pairs, u32 cnt, u32 src); +int vpu_find_src_by_dst(struct vpu_pair *pairs, u32 cnt, u32 dst); +#endif diff --git a/drivers/media/platform/amphion/vpu_v4l2.c b/drivers/media/platform/amphion/vpu_v4l2.c new file mode 100644 index 000000000000..10116e72190b --- /dev/null +++ b/drivers/media/platform/amphion/vpu_v4l2.c @@ -0,0 +1,653 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2021 NXP + */ + +#define TAG "V4L2" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vpu.h" +#include "vpu_core.h" +#include "vpu_v4l2.h" +#include "vpu_msgs.h" +#include "vpu_helpers.h" +#include "vpu_log.h" + +void vpu_inst_lock(struct vpu_inst *inst) +{ + mutex_lock(&inst->lock); +} + +void vpu_inst_unlock(struct vpu_inst *inst) +{ + mutex_unlock(&inst->lock); +} + +dma_addr_t vpu_get_vb_phy_addr(struct vb2_buffer *vb, u32 plane_no) +{ + return vb2_dma_contig_plane_dma_addr(vb, plane_no) + + vb->planes[plane_no].data_offset; +} + +unsigned int vpu_get_vb_length(struct vb2_buffer *vb, u32 plane_no) +{ + if (plane_no >= vb->num_planes) + return 0; + return vb2_plane_size(vb, plane_no) - vb->planes[plane_no].data_offset; +} + +void vpu_v4l2_set_error(struct vpu_inst *inst) +{ + struct vb2_queue *src_q; + struct vb2_queue *dst_q; + + src_q = v4l2_m2m_get_src_vq(inst->m2m_ctx); + dst_q = v4l2_m2m_get_dst_vq(inst->m2m_ctx); + if (src_q) + src_q->error = 1; + if (dst_q) + dst_q->error = 1; +} + +int vpu_notify_eos(struct vpu_inst *inst) +{ + const struct v4l2_event ev = { + .id = 0, + .type = V4L2_EVENT_EOS + }; + + inst_dbg(inst, LVL_FLOW, "notify eos event\n"); + v4l2_event_queue_fh(&inst->fh, &ev); + + return 0; +} + +int vpu_notify_source_change(struct vpu_inst *inst) +{ + const struct v4l2_event ev = { + .id = 0, + .type = V4L2_EVENT_SOURCE_CHANGE, + .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION + }; + + inst_dbg(inst, LVL_FLOW, "notify source change event\n"); + v4l2_event_queue_fh(&inst->fh, &ev); + return 0; +} + +int vpu_notify_skip(struct vpu_inst *inst) +{ + const struct v4l2_event ev = { + .id = 0, + .type = V4L2_EVENT_SKIP, + .u.data[0] = 0xff, + }; + + inst_dbg(inst, LVL_FLOW, "notify skip event\n"); + v4l2_event_queue_fh(&inst->fh, &ev); + + return 0; +} + +int vpu_notify_codec_error(struct vpu_inst *inst) +{ + const struct v4l2_event ev = { + .id = 0, + .type = V4L2_EVENT_CODEC_ERROR, + }; + + inst_dbg(inst, LVL_FLOW, "notify error event\n"); + v4l2_event_queue_fh(&inst->fh, &ev); + vpu_v4l2_set_error(inst); + + return 0; +} + +const struct vpu_format *vpu_try_fmt_common(struct vpu_inst *inst, + struct v4l2_format *f) +{ + struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp; + u32 type = f->type; + u32 stride; + u32 bytesperline; + u32 sizeimage; + const struct vpu_format *fmt; + int i; + + fmt = vpu_helper_find_format(inst, type, pixmp->pixelformat); + if (!fmt) { + fmt = vpu_helper_enum_format(inst, type, 0); + if (!fmt) + return NULL; + pixmp->pixelformat = fmt->pixfmt; + } + + stride = inst->core->res->stride; + pixmp->width = vpu_helper_valid_frame_width(inst, pixmp->width); + pixmp->height = vpu_helper_valid_frame_height(inst, pixmp->height); + pixmp->flags = fmt->flags; + pixmp->num_planes = fmt->num_planes; + if (pixmp->field == V4L2_FIELD_ANY) + pixmp->field = V4L2_FIELD_NONE; + for (i = 0; i < pixmp->num_planes; i++) { + sizeimage = vpu_helper_get_plane_size(pixmp->pixelformat, + pixmp->width, pixmp->height, i, stride, + pixmp->field == V4L2_FIELD_INTERLACED ? 1 : 0, + &bytesperline); + if ((s32)(pixmp->plane_fmt[i].bytesperline) <= 0) + pixmp->plane_fmt[i].bytesperline = bytesperline; + if ((s32)(pixmp->plane_fmt[i].sizeimage) <= 0) + pixmp->plane_fmt[i].sizeimage = sizeimage; + if (pixmp->plane_fmt[i].bytesperline < bytesperline) + pixmp->plane_fmt[i].bytesperline = bytesperline; + if (pixmp->plane_fmt[i].sizeimage <= sizeimage) + pixmp->plane_fmt[i].sizeimage = sizeimage; + } + + return fmt; +} + +static bool vpu_check_ready(struct vpu_inst *inst, u32 type) +{ + if (!inst) + return false; + if (inst->state == VPU_CODEC_STATE_DEINIT || inst->id < 0) + return false; + if (!inst->ops->check_ready) + return true; + return call_vop(inst, check_ready, type); +} + +int vpu_process_output_buffer(struct vpu_inst *inst) +{ + struct v4l2_m2m_buffer *buf = NULL; + struct vpu_vb2_buffer *vpu_buf = NULL; + + if (!inst) + return -EINVAL; + + if (!vpu_check_ready(inst, inst->out_format.type)) + return -EINVAL; + + v4l2_m2m_for_each_src_buf(inst->m2m_ctx, buf) { + vpu_buf = container_of(buf, struct vpu_vb2_buffer, m2m_buf); + if (vpu_buf->state == VPU_BUF_STATE_IDLE) + break; + vpu_buf = NULL; + } + + if (!vpu_buf) + return -EINVAL; + + inst_dbg(inst, LVL_DEBUG, "frame id = %d / %d\n", + vpu_buf->m2m_buf.vb.sequence, inst->sequence); + return call_vop(inst, process_output, &vpu_buf->m2m_buf.vb.vb2_buf); +} + +int vpu_process_capture_buffer(struct vpu_inst *inst) +{ + struct v4l2_m2m_buffer *buf = NULL; + struct vpu_vb2_buffer *vpu_buf = NULL; + + if (!inst) + return -EINVAL; + + if (!vpu_check_ready(inst, inst->cap_format.type)) + return -EINVAL; + + v4l2_m2m_for_each_dst_buf(inst->m2m_ctx, buf) { + vpu_buf = container_of(buf, struct vpu_vb2_buffer, m2m_buf); + if (vpu_buf->state == VPU_BUF_STATE_IDLE) + break; + vpu_buf = NULL; + } + if (!vpu_buf) + return -EINVAL; + + return call_vop(inst, process_capture, &vpu_buf->m2m_buf.vb.vb2_buf); +} + +struct vb2_v4l2_buffer *vpu_find_buf_by_sequence(struct vpu_inst *inst, + u32 type, u32 sequence) +{ + struct v4l2_m2m_buffer *buf = NULL; + struct vb2_v4l2_buffer *vbuf = NULL; + + if (V4L2_TYPE_IS_OUTPUT(type)) { + v4l2_m2m_for_each_src_buf(inst->m2m_ctx, buf) { + vbuf = &buf->vb; + if (vbuf->sequence == sequence) + break; + vbuf = NULL; + } + } else { + v4l2_m2m_for_each_dst_buf(inst->m2m_ctx, buf) { + vbuf = &buf->vb; + if (vbuf->sequence == sequence) + break; + vbuf = NULL; + } + } + + return vbuf; +} + +struct vb2_v4l2_buffer *vpu_find_buf_by_idx(struct vpu_inst *inst, + u32 type, u32 idx) +{ + struct v4l2_m2m_buffer *buf = NULL; + struct vb2_v4l2_buffer *vbuf = NULL; + + if (V4L2_TYPE_IS_OUTPUT(type)) { + v4l2_m2m_for_each_src_buf(inst->m2m_ctx, buf) { + vbuf = &buf->vb; + if (vbuf->vb2_buf.index == idx) + break; + vbuf = NULL; + } + } else { + v4l2_m2m_for_each_dst_buf(inst->m2m_ctx, buf) { + vbuf = &buf->vb; + if (vbuf->vb2_buf.index == idx) + break; + vbuf = NULL; + } + } + + return vbuf; +} + +int vpu_get_num_buffers(struct vpu_inst *inst, u32 type) +{ + struct vb2_queue *q; + + if (!inst || !inst->m2m_ctx) + return -EINVAL; + if (V4L2_TYPE_IS_OUTPUT(type)) + q = v4l2_m2m_get_src_vq(inst->m2m_ctx); + else + q = v4l2_m2m_get_dst_vq(inst->m2m_ctx); + + return q->num_buffers; +} + +static void vpu_m2m_device_run(void *priv) +{ +} + +static void vpu_m2m_job_abort(void *priv) +{ + struct vpu_inst *inst = priv; + + v4l2_m2m_job_finish(inst->m2m_dev, inst->m2m_ctx); +} + +static const struct v4l2_m2m_ops vpu_m2m_ops = { + .device_run = vpu_m2m_device_run, + .job_abort = vpu_m2m_job_abort +}; + +static int vpu_vb2_queue_setup(struct vb2_queue *vq, + unsigned int *buf_count, + unsigned int *plane_count, + unsigned int psize[], + struct device *allocators[]) +{ + struct vpu_inst *inst = vb2_get_drv_priv(vq); + struct vpu_format *cur_fmt; + int i; + + cur_fmt = vpu_get_format(inst, vq->type); + + if (*plane_count) { + if (*plane_count != cur_fmt->num_planes) + return -EINVAL; + for (i = 0; i < cur_fmt->num_planes; i++) { + if (psize[i] < cur_fmt->sizeimage[i]) + return -EINVAL; + } + } + + *plane_count = cur_fmt->num_planes; + for (i = 0; i < cur_fmt->num_planes; i++) + psize[i] = cur_fmt->sizeimage[i]; + + inst_dbg(inst, LVL_FLOW, "%s queue setup : %u; %u, %u\n", + vpu_type_name(vq->type), + *buf_count, + psize[0], psize[1]); + + return 0; +} + +static int vpu_vb2_buf_init(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct vpu_vb2_buffer *vpu_buf = to_vpu_vb2_buffer(vbuf); + + vpu_buf->state = VPU_BUF_STATE_IDLE; + + return 0; +} + +static void vpu_vb2_buf_cleanup(struct vb2_buffer *vb) +{ +} + +static int vpu_vb2_buf_prepare(struct vb2_buffer *vb) +{ + struct vpu_inst *inst = vb2_get_drv_priv(vb->vb2_queue); + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct vpu_vb2_buffer *vpu_buf = to_vpu_vb2_buffer(vbuf); + struct vpu_format *cur_fmt; + u32 i; + + cur_fmt = vpu_get_format(inst, vb->type); + if (vb->num_planes != cur_fmt->num_planes) + return -EINVAL; + for (i = 0; i < cur_fmt->num_planes; i++) { + if (vpu_get_vb_length(vb, i) < cur_fmt->sizeimage[i]) { + inst_err(inst, "%s buf[%d] is invalid\n", + vpu_type_name(vb->type), + vb->index); + vpu_buf->state = VPU_BUF_STATE_ERROR; + } + } + + return 0; +} + +static void vpu_vb2_buf_finish(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct vpu_inst *inst = vb2_get_drv_priv(vb->vb2_queue); + struct vb2_queue *q = vb->vb2_queue; + + if (vbuf->flags & V4L2_BUF_FLAG_LAST) + vpu_notify_eos(inst); + + if (list_empty(&q->done_list)) + call_vop(inst, on_queue_empty, q->type); +} + +void vpu_vb2_buffers_return(struct vpu_inst *inst, + unsigned int type, enum vb2_buffer_state state) +{ + struct vb2_v4l2_buffer *buf; + + if (!inst || !inst->m2m_ctx) + return; + + if (V4L2_TYPE_IS_OUTPUT(type)) { + while ((buf = v4l2_m2m_src_buf_remove(inst->m2m_ctx))) + v4l2_m2m_buf_done(buf, state); + } else { + while ((buf = v4l2_m2m_dst_buf_remove(inst->m2m_ctx))) + v4l2_m2m_buf_done(buf, state); + } +} + +static int vpu_vb2_start_streaming(struct vb2_queue *q, unsigned int count) +{ + struct vpu_inst *inst = vb2_get_drv_priv(q); + int ret; + + vpu_inst_unlock(inst); + ret = vpu_inst_register(inst); + vpu_inst_lock(inst); + if (ret) + return ret; + + vpu_inst_get(inst); + inst_dbg(inst, LVL_FLOW, "%s start streaming : %d\n", + vpu_type_name(q->type), q->num_buffers); + call_vop(inst, start, q->type); + vb2_clear_last_buffer_dequeued(q); + + return 0; +} + +static void vpu_vb2_stop_streaming(struct vb2_queue *q) +{ + struct vpu_inst *inst = vb2_get_drv_priv(q); + + inst_dbg(inst, LVL_FLOW, "%s stop streaming\n", vpu_type_name(q->type)); + + call_vop(inst, stop, q->type); + vpu_vb2_buffers_return(inst, q->type, VB2_BUF_STATE_ERROR); + if (V4L2_TYPE_IS_OUTPUT(q->type)) + inst->sequence = 0; + + vpu_inst_put(inst); +} + +static void vpu_vb2_buf_queue(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct vpu_inst *inst = vb2_get_drv_priv(vb->vb2_queue); + + inst_dbg(inst, LVL_DEBUG, "%s buf queue\n", vpu_type_name(vb->type)); + + if (V4L2_TYPE_IS_OUTPUT(vb->type)) { + vbuf->sequence = inst->sequence++; + if ((s64)vb->timestamp < 0) + vb->timestamp = VPU_INVALID_TIMESTAMP; + } + + v4l2_m2m_buf_queue(inst->m2m_ctx, vbuf); + vpu_process_output_buffer(inst); + vpu_process_capture_buffer(inst); +} + +static struct vb2_ops vpu_vb2_ops = { + .queue_setup = vpu_vb2_queue_setup, + .buf_init = vpu_vb2_buf_init, + .buf_cleanup = vpu_vb2_buf_cleanup, + .buf_prepare = vpu_vb2_buf_prepare, + .buf_finish = vpu_vb2_buf_finish, + .start_streaming = vpu_vb2_start_streaming, + .stop_streaming = vpu_vb2_stop_streaming, + .buf_queue = vpu_vb2_buf_queue, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, +}; + +static int vpu_m2m_queue_init(void *priv, struct vb2_queue *src_vq, + struct vb2_queue *dst_vq) +{ + struct vpu_inst *inst = priv; + int ret; + + src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; + src_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->ops = &vpu_vb2_ops; + src_vq->mem_ops = &vb2_dma_contig_memops; + if (inst->type == VPU_CORE_TYPE_DEC && inst->use_stream_buffer) + src_vq->mem_ops = &vb2_vmalloc_memops; + src_vq->drv_priv = inst; + src_vq->buf_struct_size = sizeof(struct vpu_vb2_buffer); + src_vq->allow_zero_bytesused = 1; + src_vq->min_buffers_needed = 1; + src_vq->dev = inst->core->dev; + src_vq->lock = &inst->lock; + ret = vb2_queue_init(src_vq); + if (ret) + return ret; + + dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; + dst_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->ops = &vpu_vb2_ops; + dst_vq->mem_ops = &vb2_dma_contig_memops; + if (inst->type == VPU_CORE_TYPE_ENC && inst->use_stream_buffer) + dst_vq->mem_ops = &vb2_vmalloc_memops; + dst_vq->drv_priv = inst; + dst_vq->buf_struct_size = sizeof(struct vpu_vb2_buffer); + dst_vq->allow_zero_bytesused = 1; + dst_vq->min_buffers_needed = 1; + dst_vq->dev = inst->core->dev; + dst_vq->lock = &inst->lock; + ret = vb2_queue_init(dst_vq); + if (ret) { + vb2_queue_release(src_vq); + return ret; + } + + return 0; +} + +static int vpu_v4l2_release(struct vpu_inst *inst) +{ + struct vpu_core *core = inst->core; + + inst_dbg(inst, LVL_FLOW, "%s\n", __func__); + + vpu_release_core(core); + + if (inst->workqueue) { + cancel_work_sync(&inst->msg_work); + destroy_workqueue(inst->workqueue); + inst->workqueue = NULL; + } + if (inst->m2m_ctx) { + v4l2_m2m_ctx_release(inst->m2m_ctx); + inst->m2m_ctx = NULL; + } + if (inst->m2m_dev) { + v4l2_m2m_release(inst->m2m_dev); + inst->m2m_dev = NULL; + } + + v4l2_ctrl_handler_free(&inst->ctrl_handler); + mutex_destroy(&inst->lock); + v4l2_fh_del(&inst->fh); + v4l2_fh_exit(&inst->fh); + + call_vop(inst, cleanup); + + return 0; +} + +int vpu_v4l2_open(struct file *file, struct vpu_inst *inst) +{ + struct vpu_dev *vpu = video_drvdata(file); + struct video_device *vdev; + struct vpu_core *core = NULL; + int ret = 0; + + WARN_ON(!file || !inst || !inst->ops); + + if (inst->type == VPU_CORE_TYPE_ENC) + vdev = vpu->vdev_enc; + else + vdev = vpu->vdev_dec; + + mutex_init(&inst->lock); + INIT_LIST_HEAD(&inst->cmd_q); + + inst->id = VPU_INST_NULL_ID; + inst->release = vpu_v4l2_release; + inst->core = vpu_request_core(vpu, inst->type); + + core = inst->core; + if (!core) { + vpu_err("there is no core for %s\n", + vpu_core_type_desc(inst->type)); + return -EINVAL; + } + + inst->min_buffer_cap = 2; + inst->min_buffer_out = 2; + + ret = call_vop(inst, ctrl_init); + if (ret) + goto error; + + inst->m2m_dev = v4l2_m2m_init(&vpu_m2m_ops); + if (IS_ERR(inst->m2m_dev)) { + vpu_err("v4l2_m2m_init fail\n"); + ret = PTR_ERR(inst->m2m_dev); + goto error; + } + + inst->m2m_ctx = v4l2_m2m_ctx_init(inst->m2m_dev, + inst, vpu_m2m_queue_init); + if (IS_ERR(inst->m2m_ctx)) { + vpu_err("v4l2_m2m_ctx_init fail\n"); + ret = PTR_ERR(inst->m2m_dev); + goto error; + } + + v4l2_fh_init(&inst->fh, vdev); + v4l2_fh_add(&inst->fh); + inst->fh.ctrl_handler = &inst->ctrl_handler; + inst->fh.m2m_ctx = inst->m2m_ctx; + file->private_data = &inst->fh; + inst->state = VPU_CODEC_STATE_DEINIT; + inst->workqueue = alloc_workqueue("vpu_inst", WQ_UNBOUND | WQ_MEM_RECLAIM, 1); + if (inst->workqueue) { + INIT_WORK(&inst->msg_work, vpu_inst_run_work); + ret = kfifo_init(&inst->msg_fifo, + inst->msg_buffer, + roundup_pow_of_two(sizeof(inst->msg_buffer))); + if (ret) { + destroy_workqueue(inst->workqueue); + inst->workqueue = NULL; + } + } + atomic_set(&inst->ref_count, 0); + vpu_inst_get(inst); + vpu_dbg(LVL_FLOW, "open, tgid = %d, pid = %d\n", inst->tgid, inst->pid); + + return 0; +error: + if (inst->m2m_ctx) { + v4l2_m2m_ctx_release(inst->m2m_ctx); + inst->m2m_ctx = NULL; + } + if (inst->m2m_dev) { + v4l2_m2m_release(inst->m2m_dev); + inst->m2m_dev = NULL; + } + v4l2_ctrl_handler_free(&inst->ctrl_handler); + vpu_release_core(inst->core); + + return ret; +} + +int vpu_v4l2_close(struct file *file) +{ + struct vpu_inst *inst = to_inst(file); + struct vb2_queue *src_q; + struct vb2_queue *dst_q; + + inst_dbg(inst, LVL_FLOW, "close\n"); + src_q = v4l2_m2m_get_src_vq(inst->m2m_ctx); + dst_q = v4l2_m2m_get_dst_vq(inst->m2m_ctx); + vpu_inst_lock(inst); + if (vb2_is_streaming(src_q)) + v4l2_m2m_streamoff(file, inst->m2m_ctx, src_q->type); + if (vb2_is_streaming(dst_q)) + v4l2_m2m_streamoff(file, inst->m2m_ctx, dst_q->type); + vpu_inst_unlock(inst); + + call_vop(inst, release); + vpu_inst_unregister(inst); + vpu_inst_put(inst); + + return 0; +} diff --git a/drivers/media/platform/amphion/vpu_v4l2.h b/drivers/media/platform/amphion/vpu_v4l2.h new file mode 100644 index 000000000000..5a8d2f8bfb20 --- /dev/null +++ b/drivers/media/platform/amphion/vpu_v4l2.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2020-2021 NXP + */ + +#ifndef _AMPHION_VPU_V4L2_H +#define _AMPHION_VPU_V4L2_H + +void vpu_inst_lock(struct vpu_inst *inst); +void vpu_inst_unlock(struct vpu_inst *inst); + +int vpu_v4l2_open(struct file *file, struct vpu_inst *inst); +int vpu_v4l2_close(struct file *file); + +const struct vpu_format *vpu_try_fmt_common(struct vpu_inst *inst, struct v4l2_format *f); +int vpu_process_output_buffer(struct vpu_inst *inst); +int vpu_process_capture_buffer(struct vpu_inst *inst); +struct vb2_v4l2_buffer *vpu_find_buf_by_sequence(struct vpu_inst *inst, u32 type, u32 sequence); +struct vb2_v4l2_buffer *vpu_find_buf_by_idx(struct vpu_inst *inst, u32 type, u32 idx); +void vpu_v4l2_set_error(struct vpu_inst *inst); +int vpu_notify_eos(struct vpu_inst *inst); +int vpu_notify_source_change(struct vpu_inst *inst); +int vpu_notify_skip(struct vpu_inst *inst); +int vpu_notify_codec_error(struct vpu_inst *inst); +void vpu_vb2_buffers_return(struct vpu_inst *inst, + unsigned int type, enum vb2_buffer_state state); +int vpu_get_num_buffers(struct vpu_inst *inst, u32 type); + +dma_addr_t vpu_get_vb_phy_addr(struct vb2_buffer *vb, u32 plane_no); +unsigned int vpu_get_vb_length(struct vb2_buffer *vb, u32 plane_no); +static inline struct vpu_format *vpu_get_format(struct vpu_inst *inst, u32 type) +{ + if (V4L2_TYPE_IS_OUTPUT(type)) + return &inst->out_format; + else + return &inst->cap_format; +} + +static inline char *vpu_type_name(u32 type) +{ + return V4L2_TYPE_IS_OUTPUT(type) ? "output" : "capture"; +} + +#endif From patchwork Tue Sep 7 09:49:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Qian X-Patchwork-Id: 507650 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A50D4C433FE for ; Tue, 7 Sep 2021 09:51:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9013561102 for ; Tue, 7 Sep 2021 09:51:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244910AbhIGJwZ (ORCPT ); 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Tue, 7 Sep 2021 09:50:38 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v8 12/15] media: amphion: implement malone decoder rpc interface Date: Tue, 7 Sep 2021 17:49:19 +0800 Message-Id: X-Mailer: git-send-email 2.32.0 In-Reply-To: References: X-ClientProxiedBy: SG2PR02CA0097.apcprd02.prod.outlook.com (2603:1096:4:92::13) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by SG2PR02CA0097.apcprd02.prod.outlook.com (2603:1096:4:92::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4478.19 via Frontend Transport; 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Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- drivers/media/platform/amphion/vpu_malone.c | 1682 +++++++++++++++++++ drivers/media/platform/amphion/vpu_malone.h | 42 + 2 files changed, 1724 insertions(+) create mode 100644 drivers/media/platform/amphion/vpu_malone.c create mode 100644 drivers/media/platform/amphion/vpu_malone.h diff --git a/drivers/media/platform/amphion/vpu_malone.c b/drivers/media/platform/amphion/vpu_malone.c new file mode 100644 index 000000000000..ceae81c47202 --- /dev/null +++ b/drivers/media/platform/amphion/vpu_malone.c @@ -0,0 +1,1682 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2021 NXP + */ + +#define TAG "MALONE" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vpu.h" +#include "vpu_rpc.h" +#include "vpu_defs.h" +#include "vpu_helpers.h" +#include "vpu_cmds.h" +#include "vpu_log.h" +#include "vpu_imx8q.h" +#include "vpu_malone.h" + +#define CMD_SIZE 25600 +#define MSG_SIZE 25600 +#define CODEC_SIZE 0x1000 +#define JPEG_SIZE 0x1000 +#define SEQ_SIZE 0x1000 +#define GOP_SIZE 0x1000 +#define PIC_SIZE 0x1000 +#define QMETER_SIZE 0x1000 +#define DBGLOG_SIZE 0x10000 +#define DEBUG_SIZE 0x80000 +#define ENG_SIZE 0x1000 +#define MALONE_SKIPPED_FRAME_ID 0x555 + +#define MALONE_ALIGN_MBI 0x800 +#define MALONE_DCP_CHUNK_BIT 16 +#define MALONE_DCP_SIZE_MAX 0x3000000 +#define MALONE_DCP_SIZE_MIN 0x100000 +#define MALONE_DCP_FIXED_MB_ALLOC 250 + +#define CONFIG_SET(val, cfg, pos, mask) \ + (*(cfg) |= (((val) << (pos)) & (mask))) +//x means source data , y means destination data +#define STREAM_CONFIG_FORMAT_SET(x, y) CONFIG_SET(x, y, 0, 0x0000000F) +#define STREAM_CONFIG_STRBUFIDX_SET(x, y) CONFIG_SET(x, y, 8, 0x00000300) +#define STREAM_CONFIG_NOSEQ_SET(x, y) CONFIG_SET(x, y, 10, 0x00000400) +#define STREAM_CONFIG_DEBLOCK_SET(x, y) CONFIG_SET(x, y, 11, 0x00000800) +#define STREAM_CONFIG_DERING_SET(x, y) CONFIG_SET(x, y, 12, 0x00001000) +#define STREAM_CONFIG_IBWAIT_SET(x, y) CONFIG_SET(x, y, 13, 0x00002000) +#define STREAM_CONFIG_FBC_SET(x, y) CONFIG_SET(x, y, 14, 0x00004000) +#define STREAM_CONFIG_PLAY_MODE_SET(x, y) CONFIG_SET(x, y, 16, 0x00030000) +#define STREAM_CONFIG_ENABLE_DCP_SET(x, y) CONFIG_SET(x, y, 20, 0x00100000) +#define STREAM_CONFIG_NUM_STR_BUF_SET(x, y) CONFIG_SET(x, y, 21, 0x00600000) +#define STREAM_CONFIG_MALONE_USAGE_SET(x, y) CONFIG_SET(x, y, 23, 0x01800000) +#define STREAM_CONFIG_MULTI_VID_SET(x, y) CONFIG_SET(x, y, 25, 0x02000000) +#define STREAM_CONFIG_OBFUSC_EN_SET(x, y) CONFIG_SET(x, y, 26, 0x04000000) +#define STREAM_CONFIG_RC4_EN_SET(x, y) CONFIG_SET(x, y, 27, 0x08000000) +#define STREAM_CONFIG_MCX_SET(x, y) CONFIG_SET(x, y, 28, 0x10000000) +#define STREAM_CONFIG_PES_SET(x, y) CONFIG_SET(x, y, 29, 0x20000000) +#define STREAM_CONFIG_NUM_DBE_SET(x, y) CONFIG_SET(x, y, 30, 0x40000000) +#define STREAM_CONFIG_FS_CTRL_MODE_SET(x, y) CONFIG_SET(x, y, 31, 0x80000000) + +enum vpu_malone_stream_input_mode { + INVALID_MODE = 0, + FRAME_LVL, + NON_FRAME_LVL +}; + +enum vpu_malone_format { + MALONE_FMT_NULL = 0x0, + MALONE_FMT_AVC = 0x1, + MALONE_FMT_MP2 = 0x2, + MALONE_FMT_VC1 = 0x3, + MALONE_FMT_AVS = 0x4, + MALONE_FMT_ASP = 0x5, + MALONE_FMT_JPG = 0x6, + MALONE_FMT_RV = 0x7, + MALONE_FMT_VP6 = 0x8, + MALONE_FMT_SPK = 0x9, + MALONE_FMT_VP8 = 0xA, + MALONE_FMT_HEVC = 0xB, + MALONE_FMT_LAST = MALONE_FMT_HEVC +}; + +enum { + VID_API_CMD_NULL = 0x00, + VID_API_CMD_PARSE_NEXT_SEQ = 0x01, + VID_API_CMD_PARSE_NEXT_I = 0x02, + VID_API_CMD_PARSE_NEXT_IP = 0x03, + VID_API_CMD_PARSE_NEXT_ANY = 0x04, + VID_API_CMD_DEC_PIC = 0x05, + VID_API_CMD_UPDATE_ES_WR_PTR = 0x06, + VID_API_CMD_UPDATE_ES_RD_PTR = 0x07, + VID_API_CMD_UPDATE_UDATA = 0x08, + VID_API_CMD_GET_FSINFO = 0x09, + VID_API_CMD_SKIP_PIC = 0x0a, + VID_API_CMD_DEC_CHUNK = 0x0b, + VID_API_CMD_START = 0x10, + VID_API_CMD_STOP = 0x11, + VID_API_CMD_ABORT = 0x12, + VID_API_CMD_RST_BUF = 0x13, + VID_API_CMD_FS_RELEASE = 0x15, + VID_API_CMD_MEM_REGION_ATTACH = 0x16, + VID_API_CMD_MEM_REGION_DETACH = 0x17, + VID_API_CMD_MVC_VIEW_SELECT = 0x18, + VID_API_CMD_FS_ALLOC = 0x19, + VID_API_CMD_DBG_GET_STATUS = 0x1C, + VID_API_CMD_DBG_START_LOG = 0x1D, + VID_API_CMD_DBG_STOP_LOG = 0x1E, + VID_API_CMD_DBG_DUMP_LOG = 0x1F, + VID_API_CMD_YUV_READY = 0x20, + VID_API_CMD_TS = 0x21, + + VID_API_CMD_FIRM_RESET = 0x40, + + VID_API_CMD_SNAPSHOT = 0xAA, + VID_API_CMD_ROLL_SNAPSHOT = 0xAB, + VID_API_CMD_LOCK_SCHEDULER = 0xAC, + VID_API_CMD_UNLOCK_SCHEDULER = 0xAD, + VID_API_CMD_CQ_FIFO_DUMP = 0xAE, + VID_API_CMD_DBG_FIFO_DUMP = 0xAF, + VID_API_CMD_SVC_ILP = 0xBB, + VID_API_CMD_FW_STATUS = 0xF0, + VID_API_CMD_INVALID = 0xFF +}; + +enum { + VID_API_EVENT_NULL = 0x00, + VID_API_EVENT_RESET_DONE = 0x01, + VID_API_EVENT_SEQ_HDR_FOUND = 0x02, + VID_API_EVENT_PIC_HDR_FOUND = 0x03, + VID_API_EVENT_PIC_DECODED = 0x04, + VID_API_EVENT_FIFO_LOW = 0x05, + VID_API_EVENT_FIFO_HIGH = 0x06, + VID_API_EVENT_FIFO_EMPTY = 0x07, + VID_API_EVENT_FIFO_FULL = 0x08, + VID_API_EVENT_BS_ERROR = 0x09, + VID_API_EVENT_UDATA_FIFO_UPTD = 0x0A, + VID_API_EVENT_RES_CHANGE = 0x0B, + VID_API_EVENT_FIFO_OVF = 0x0C, + VID_API_EVENT_CHUNK_DECODED = 0x0D, + VID_API_EVENT_REQ_FRAME_BUFF = 0x10, + VID_API_EVENT_FRAME_BUFF_RDY = 0x11, + VID_API_EVENT_REL_FRAME_BUFF = 0x12, + VID_API_EVENT_STR_BUF_RST = 0x13, + VID_API_EVENT_RET_PING = 0x14, + VID_API_EVENT_QMETER = 0x15, + VID_API_EVENT_STR_FMT_CHANGE = 0x16, + VID_API_EVENT_FIRMWARE_XCPT = 0x17, + VID_API_EVENT_START_DONE = 0x18, + VID_API_EVENT_STOPPED = 0x19, + VID_API_EVENT_ABORT_DONE = 0x1A, + VID_API_EVENT_FINISHED = 0x1B, + VID_API_EVENT_DBG_STAT_UPDATE = 0x1C, + VID_API_EVENT_DBG_LOG_STARTED = 0x1D, + VID_API_EVENT_DBG_LOG_STOPPED = 0x1E, + VID_API_EVENT_DBG_LOG_UPDATED = 0x1F, + VID_API_EVENT_DBG_MSG_DEC = 0x20, + VID_API_EVENT_DEC_SC_ERR = 0x21, + VID_API_EVENT_CQ_FIFO_DUMP = 0x22, + VID_API_EVENT_DBG_FIFO_DUMP = 0x23, + VID_API_EVENT_DEC_CHECK_RES = 0x24, + VID_API_EVENT_DEC_CFG_INFO = 0x25, + VID_API_EVENT_UNSUPPORTED_STREAM = 0x26, + VID_API_EVENT_STR_SUSPENDED = 0x30, + VID_API_EVENT_SNAPSHOT_DONE = 0x40, + VID_API_EVENT_FW_STATUS = 0xF0, + VID_API_EVENT_INVALID = 0xFF +}; + +struct vpu_malone_buffer_desc { + struct vpu_rpc_buffer_desc buffer; + u32 low; + u32 high; +}; + +struct vpu_malone_str_buffer { + u32 wptr; + u32 rptr; + u32 start; + u32 end; + u32 lwm; +}; + +struct vpu_malone_picth_info { + u32 frame_pitch; +}; + +struct vpu_malone_table_desc { + u32 array_base; + u32 size; +}; + +struct vpu_malone_dbglog_desc { + u32 addr; + u32 size; + u32 level; + u32 reserved; +}; + +struct vpu_malone_frame_buffer { + u32 addr; + u32 size; +}; + +struct vpu_malone_udata { + u32 base; + u32 total_size; + u32 slot_size; +}; + +struct vpu_malone_buffer_info { + u32 stream_input_mode; + u32 stream_pic_input_count; + u32 stream_pic_parsed_count; + u32 stream_buffer_threshold; + u32 stream_pic_end_flag; +}; + +struct vpu_malone_encrypt_info { + u32 rec4key[8]; + u32 obfusc; +}; + +struct malone_iface { + u32 exec_base_addr; + u32 exec_area_size; + struct vpu_malone_buffer_desc cmd_buffer_desc; + struct vpu_malone_buffer_desc msg_buffer_desc; + u32 cmd_int_enable[VID_API_NUM_STREAMS]; + struct vpu_malone_picth_info stream_pitch_info[VID_API_NUM_STREAMS]; + u32 stream_config[VID_API_NUM_STREAMS]; + struct vpu_malone_table_desc codec_param_tab_desc; + struct vpu_malone_table_desc jpeg_param_tab_desc; + u32 stream_buffer_desc[VID_API_NUM_STREAMS][VID_API_MAX_BUF_PER_STR]; + struct vpu_malone_table_desc seq_info_tab_desc; + struct vpu_malone_table_desc pic_info_tab_desc; + struct vpu_malone_table_desc gop_info_tab_desc; + struct vpu_malone_table_desc qmeter_info_tab_desc; + u32 stream_error[VID_API_NUM_STREAMS]; + u32 fw_version; + u32 fw_offset; + u32 max_streams; + struct vpu_malone_dbglog_desc dbglog_desc; + struct vpu_rpc_buffer_desc api_cmd_buffer_desc[VID_API_NUM_STREAMS]; + struct vpu_malone_udata udata_buffer[VID_API_NUM_STREAMS]; + struct vpu_malone_buffer_desc debug_buffer_desc; + struct vpu_malone_buffer_desc eng_access_buff_desc[VID_API_NUM_STREAMS]; + u32 encrypt_info[VID_API_NUM_STREAMS]; + struct vpu_rpc_system_config system_cfg; + u32 api_version; + struct vpu_malone_buffer_info stream_buff_info[VID_API_NUM_STREAMS]; +}; + +struct malone_jpg_params { + u32 rotation_angle; + u32 horiz_scale_factor; + u32 vert_scale_factor; + u32 rotation_mode; + u32 rgb_mode; + u32 chunk_mode; /* 0 ~ 1 */ + u32 last_chunk; /* 0 ~ 1 */ + u32 chunk_rows; /* 0 ~ 255 */ + u32 num_bytes; + u32 jpg_crop_x; + u32 jpg_crop_y; + u32 jpg_crop_width; + u32 jpg_crop_height; + u32 jpg_mjpeg_mode; + u32 jpg_mjpeg_interlaced; +}; + +struct malone_codec_params { + u32 disp_imm; + u32 fourcc; + u32 codec_version; + u32 frame_rate; + u32 dbglog_enable; + u32 bsdma_lwm; + u32 bbd_coring; + u32 bbd_s_thr_row; + u32 bbd_p_thr_row; + u32 bbd_s_thr_logo_row; + u32 bbd_p_thr_logo_row; + u32 bbd_s_thr_col; + u32 bbd_p_thr_col; + u32 bbd_chr_thr_row; + u32 bbd_chr_thr_col; + u32 bbd_uv_mid_level; + u32 bbd_excl_win_mb_left; + u32 bbd_excl_win_mb_right; +}; + +struct malone_padding_scode { + u32 scode_type; + u32 pixelformat; + u32 data[2]; +}; + +struct malone_fmt_mapping { + u32 pixelformat; + enum vpu_malone_format malone_format; +}; + +struct malone_scode_t { + struct vpu_inst *inst; + struct vb2_buffer *vb; + u32 wptr; + u32 need_data; +}; + +struct malone_scode_handler { + u32 pixelformat; + int (*insert_scode_seq)(struct malone_scode_t *scode); + int (*insert_scode_pic)(struct malone_scode_t *scode); +}; + +struct vpu_dec_ctrl { + struct malone_codec_params *codec_param; + struct malone_jpg_params *jpg; + void *seq_mem; + void *pic_mem; + void *gop_mem; + void *qmeter_mem; + void *dbglog_mem; + struct vpu_malone_str_buffer *str_buf[VID_API_NUM_STREAMS]; + u32 buf_addr[VID_API_NUM_STREAMS]; +}; + +u32 vpu_malone_get_data_size(void) +{ + return sizeof(struct vpu_dec_ctrl); +} + +void vpu_malone_init_rpc(struct vpu_shared_addr *shared, + struct vpu_buffer *rpc, dma_addr_t boot_addr) +{ + struct malone_iface *iface; + struct vpu_dec_ctrl *hc; + unsigned long base_phy_addr; + unsigned long phy_addr; + unsigned long offset; + unsigned int i; + + WARN_ON(!shared || !shared->priv); + WARN_ON(!rpc || !rpc->phys || !rpc->length || rpc->phys < boot_addr); + + iface = rpc->virt; + base_phy_addr = rpc->phys - boot_addr; + hc = shared->priv; + + shared->iface = iface; + shared->boot_addr = boot_addr; + + iface->exec_base_addr = base_phy_addr; + iface->exec_area_size = rpc->length; + + offset = sizeof(struct malone_iface); + phy_addr = base_phy_addr + offset; + + shared->cmd_desc = &iface->cmd_buffer_desc.buffer; + shared->cmd_mem_vir = rpc->virt + offset; + iface->cmd_buffer_desc.buffer.start = + iface->cmd_buffer_desc.buffer.rptr = + iface->cmd_buffer_desc.buffer.wptr = phy_addr; + iface->cmd_buffer_desc.buffer.end = iface->cmd_buffer_desc.buffer.start + CMD_SIZE; + offset += CMD_SIZE; + phy_addr = base_phy_addr + offset; + + shared->msg_desc = &iface->msg_buffer_desc.buffer; + shared->msg_mem_vir = rpc->virt + offset; + iface->msg_buffer_desc.buffer.start = + iface->msg_buffer_desc.buffer.wptr = + iface->msg_buffer_desc.buffer.rptr = phy_addr; + iface->msg_buffer_desc.buffer.end = iface->msg_buffer_desc.buffer.start + MSG_SIZE; + offset += MSG_SIZE; + phy_addr = base_phy_addr + offset; + + iface->codec_param_tab_desc.array_base = phy_addr; + hc->codec_param = rpc->virt + offset; + offset += CODEC_SIZE; + phy_addr = base_phy_addr + offset; + + iface->jpeg_param_tab_desc.array_base = phy_addr; + hc->jpg = rpc->virt + offset; + offset += JPEG_SIZE; + phy_addr = base_phy_addr + offset; + + iface->seq_info_tab_desc.array_base = phy_addr; + hc->seq_mem = rpc->virt + offset; + offset += SEQ_SIZE; + phy_addr = base_phy_addr + offset; + + iface->pic_info_tab_desc.array_base = phy_addr; + hc->pic_mem = rpc->virt + offset; + offset += PIC_SIZE; + phy_addr = base_phy_addr + offset; + + iface->gop_info_tab_desc.array_base = phy_addr; + hc->gop_mem = rpc->virt + offset; + offset += GOP_SIZE; + phy_addr = base_phy_addr + offset; + + iface->qmeter_info_tab_desc.array_base = phy_addr; + hc->qmeter_mem = rpc->virt + offset; + offset += QMETER_SIZE; + phy_addr = base_phy_addr + offset; + + iface->dbglog_desc.addr = phy_addr; + iface->dbglog_desc.size = DBGLOG_SIZE; + hc->dbglog_mem = rpc->virt + offset; + offset += DBGLOG_SIZE; + phy_addr = base_phy_addr + offset; + + for (i = 0; i < VID_API_NUM_STREAMS; i++) { + iface->eng_access_buff_desc[i].buffer.start = + iface->eng_access_buff_desc[i].buffer.wptr = + iface->eng_access_buff_desc[i].buffer.rptr = phy_addr; + iface->eng_access_buff_desc[i].buffer.end = + iface->eng_access_buff_desc[i].buffer.start + ENG_SIZE; + offset += ENG_SIZE; + phy_addr = base_phy_addr + offset; + } + + for (i = 0; i < VID_API_NUM_STREAMS; i++) { + iface->encrypt_info[i] = phy_addr; + offset += sizeof(struct vpu_malone_encrypt_info); + phy_addr = base_phy_addr + offset; + } + + rpc->bytesused = offset; +} + +void vpu_malone_set_log_buf(struct vpu_shared_addr *shared, + struct vpu_buffer *log) +{ + struct malone_iface *iface; + + WARN_ON(!shared || !log || !log->phys); + vpu_dbg(LVL_DEBUG, "set log area <0x%llx, 0x%x> (0x%lx)\n", + log->phys, log->length, shared->boot_addr); + iface = shared->iface; + iface->debug_buffer_desc.buffer.start = + iface->debug_buffer_desc.buffer.wptr = + iface->debug_buffer_desc.buffer.rptr = log->phys - shared->boot_addr; + iface->debug_buffer_desc.buffer.end = iface->debug_buffer_desc.buffer.start + log->length; +} + +static u32 get_str_buffer_offset(u32 instance) +{ + return DEC_MFD_XREG_SLV_BASE + MFD_MCX + MFD_MCX_OFF * instance; +} + +void vpu_malone_set_system_cfg(struct vpu_shared_addr *shared, + u32 regs_base, void __iomem *regs, u32 core_id) +{ + struct malone_iface *iface; + struct vpu_rpc_system_config *config; + struct vpu_dec_ctrl *hc; + int i; + + WARN_ON(!shared || !shared->iface || !shared->core || !shared->priv); + + iface = shared->iface; + config = &iface->system_cfg; + hc = shared->priv; + + vpu_imx8q_set_system_cfg_common(config, regs_base, core_id); + for (i = 0; i < VID_API_NUM_STREAMS; i++) { + u32 offset = get_str_buffer_offset(i); + + hc->buf_addr[i] = regs_base + offset; + hc->str_buf[i] = regs + offset; + } +} + +u32 vpu_malone_get_version(struct vpu_shared_addr *shared) +{ + struct malone_iface *iface; + + WARN_ON(!shared || !shared->iface); + + iface = shared->iface; + return iface->fw_version; +} + +int vpu_malone_get_stream_buffer_size(struct vpu_shared_addr *shared) +{ + return 0xc00000; +} + +int vpu_malone_config_stream_buffer(struct vpu_shared_addr *shared, + u32 instance, + struct vpu_buffer *buf) +{ + struct malone_iface *iface; + struct vpu_dec_ctrl *hc; + struct vpu_malone_str_buffer *str_buf; + + WARN_ON(!shared || !shared->iface || !shared->core || !shared->priv); + + iface = shared->iface; + hc = shared->priv; + str_buf = hc->str_buf[instance]; + str_buf->wptr = str_buf->rptr = str_buf->start = buf->phys; + str_buf->end = buf->phys + buf->length; + str_buf->lwm = 0x1; + + iface->stream_buffer_desc[instance][0] = hc->buf_addr[instance]; + + return 0; +} + +int vpu_malone_get_stream_buffer_desc(struct vpu_shared_addr *shared, + u32 instance, struct vpu_rpc_buffer_desc *desc) +{ + struct vpu_dec_ctrl *hc; + struct vpu_malone_str_buffer *str_buf; + + WARN_ON(!shared || !shared->iface || !shared->core || !shared->priv); + + hc = shared->priv; + str_buf = hc->str_buf[instance]; + + if (desc) { + desc->wptr = str_buf->wptr; + desc->rptr = str_buf->rptr; + desc->start = str_buf->start; + desc->end = str_buf->end; + } + + return 0; +} + +static void vpu_malone_update_wptr(struct vpu_malone_str_buffer *str_buf, + u32 wptr) +{ + u32 size = str_buf->end - str_buf->start; + u32 space = (str_buf->rptr + size - str_buf->wptr) % size; + u32 step = (wptr + size - str_buf->wptr) % size; + + if (space && step > space) + vpu_err("update wptr from 0x%x to 0x%x, cross over rptr 0x%x\n", + str_buf->wptr, wptr, str_buf->rptr); + + /*update wptr after data is written*/ + mb(); + str_buf->wptr = wptr; +} + +static void vpu_malone_update_rptr(struct vpu_malone_str_buffer *str_buf, + u32 rptr) +{ + u32 size = str_buf->end - str_buf->start; + u32 space = (str_buf->wptr + size - str_buf->rptr) % size; + u32 step = (rptr + size - str_buf->rptr) % size; + + if (step > space) + vpu_err("update rptr from 0x%x to 0x%x, cross over wptr 0x%x\n", + str_buf->rptr, rptr, str_buf->wptr); + /*update rptr after data is read*/ + mb(); + str_buf->rptr = rptr; +} + +int vpu_malone_update_stream_buffer(struct vpu_shared_addr *shared, + u32 instance, u32 ptr, bool write) +{ + struct vpu_dec_ctrl *hc; + struct vpu_malone_str_buffer *str_buf; + + WARN_ON(!shared || !shared->iface || !shared->core || !shared->priv); + + hc = shared->priv; + str_buf = hc->str_buf[instance]; + + if (write) + vpu_malone_update_wptr(str_buf, ptr); + else + vpu_malone_update_rptr(str_buf, ptr); + + return 0; +} + +static struct malone_fmt_mapping fmt_mappings[] = { + {V4L2_PIX_FMT_H264, MALONE_FMT_AVC}, + {V4L2_PIX_FMT_H264_MVC, MALONE_FMT_AVC}, + {V4L2_PIX_FMT_HEVC, MALONE_FMT_HEVC}, + {V4L2_PIX_FMT_VC1_ANNEX_G, MALONE_FMT_VC1}, + {V4L2_PIX_FMT_VC1_ANNEX_L, MALONE_FMT_VC1}, + {V4L2_PIX_FMT_MPEG2, MALONE_FMT_MP2}, + {V4L2_PIX_FMT_MPEG4, MALONE_FMT_ASP}, + {V4L2_PIX_FMT_XVID, MALONE_FMT_ASP}, + {V4L2_PIX_FMT_H263, MALONE_FMT_ASP}, + {V4L2_PIX_FMT_JPEG, MALONE_FMT_JPG}, + {V4L2_PIX_FMT_VP8, MALONE_FMT_VP8}, +}; + +static enum vpu_malone_format vpu_malone_format_remap(u32 pixelformat) +{ + u32 i; + + for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) { + if (pixelformat == fmt_mappings[i].pixelformat) + return fmt_mappings[i].malone_format; + } + + return MALONE_FMT_NULL; +} + +static void vpu_malone_set_stream_cfg(struct vpu_shared_addr *shared, + u32 instance, enum vpu_malone_format malone_format) +{ + struct malone_iface *iface; + u32 *curr_str_cfg; + + iface = shared->iface; + curr_str_cfg = &iface->stream_config[instance]; + + *curr_str_cfg = 0; + STREAM_CONFIG_FORMAT_SET(malone_format, curr_str_cfg); + STREAM_CONFIG_STRBUFIDX_SET(0, curr_str_cfg); + STREAM_CONFIG_NOSEQ_SET(0, curr_str_cfg); + STREAM_CONFIG_DEBLOCK_SET(0, curr_str_cfg); + STREAM_CONFIG_DERING_SET(0, curr_str_cfg); + STREAM_CONFIG_PLAY_MODE_SET(0x3, curr_str_cfg); + STREAM_CONFIG_FS_CTRL_MODE_SET(0x1, curr_str_cfg); + STREAM_CONFIG_ENABLE_DCP_SET(1, curr_str_cfg); + STREAM_CONFIG_NUM_STR_BUF_SET(1, curr_str_cfg); + STREAM_CONFIG_MALONE_USAGE_SET(1, curr_str_cfg); + STREAM_CONFIG_MULTI_VID_SET(0, curr_str_cfg); + STREAM_CONFIG_OBFUSC_EN_SET(0, curr_str_cfg); + STREAM_CONFIG_RC4_EN_SET(0, curr_str_cfg); + STREAM_CONFIG_MCX_SET(1, curr_str_cfg); + STREAM_CONFIG_PES_SET(0, curr_str_cfg); + STREAM_CONFIG_NUM_DBE_SET(1, curr_str_cfg); +} + +static int vpu_malone_set_params(struct vpu_shared_addr *shared, + u32 instance, struct vpu_decode_params *params) +{ + struct malone_iface *iface; + struct vpu_dec_ctrl *hc; + enum vpu_malone_format malone_format; + + iface = shared->iface; + hc = shared->priv; + malone_format = vpu_malone_format_remap(params->codec_format); + iface->udata_buffer[instance].base = params->udata.base; + iface->udata_buffer[instance].slot_size = params->udata.size; + + vpu_malone_set_stream_cfg(shared, instance, malone_format); + + if (malone_format == MALONE_FMT_JPG) { + //1:JPGD_MJPEG_MODE_A; 2:JPGD_MJPEG_MODE_B + hc->jpg[instance].jpg_mjpeg_mode = 1; + //0: JPGD_MJPEG_PROGRESSIVE + hc->jpg[instance].jpg_mjpeg_interlaced = 0; + } + + hc->codec_param[instance].disp_imm = params->b_dis_reorder ? 1 : 0; + hc->codec_param[instance].dbglog_enable = 0; + iface->dbglog_desc.level = 0; + + if (params->b_non_frame) + iface->stream_buff_info[instance].stream_input_mode = NON_FRAME_LVL; + else + iface->stream_buff_info[instance].stream_input_mode = FRAME_LVL; + iface->stream_buff_info[instance].stream_buffer_threshold = 0; + iface->stream_buff_info[instance].stream_pic_input_count = 0; + + return 0; +} + +static bool vpu_malone_is_non_frame_mode(struct vpu_shared_addr *shared, + u32 instance) +{ + struct malone_iface *iface; + + iface = shared->iface; + if (iface->stream_buff_info[instance].stream_input_mode == NON_FRAME_LVL) + return true; + + return false; +} + +static int vpu_malone_update_params(struct vpu_shared_addr *shared, + u32 instance, struct vpu_decode_params *params) +{ + struct malone_iface *iface; + + iface = shared->iface; + + if (params->end_flag) + iface->stream_buff_info[instance].stream_pic_end_flag = params->end_flag; + params->end_flag = 0; + + return 0; +} + +int vpu_malone_set_decode_params(struct vpu_shared_addr *shared, + u32 instance, struct vpu_decode_params *params, u32 update) +{ + if (!params) + return -EINVAL; + + if (!update) + return vpu_malone_set_params(shared, instance, params); + else + return vpu_malone_update_params(shared, instance, params); +} + +static struct vpu_pair malone_cmds[] = { + {VPU_CMD_ID_START, VID_API_CMD_START}, + {VPU_CMD_ID_STOP, VID_API_CMD_STOP}, + {VPU_CMD_ID_ABORT, VID_API_CMD_ABORT}, + {VPU_CMD_ID_RST_BUF, VID_API_CMD_RST_BUF}, + {VPU_CMD_ID_SNAPSHOT, VID_API_CMD_SNAPSHOT}, + {VPU_CMD_ID_FIRM_RESET, VID_API_CMD_FIRM_RESET}, + {VPU_CMD_ID_FS_ALLOC, VID_API_CMD_FS_ALLOC}, + {VPU_CMD_ID_FS_RELEASE, VID_API_CMD_FS_RELEASE}, + {VPU_CMD_ID_TIMESTAMP, VID_API_CMD_TS}, + {VPU_CMD_ID_DEBUG, VID_API_CMD_FW_STATUS}, +}; + +static struct vpu_pair malone_msgs[] = { + {VPU_MSG_ID_RESET_DONE, VID_API_EVENT_RESET_DONE}, + {VPU_MSG_ID_START_DONE, VID_API_EVENT_START_DONE}, + {VPU_MSG_ID_STOP_DONE, VID_API_EVENT_STOPPED}, + {VPU_MSG_ID_ABORT_DONE, VID_API_EVENT_ABORT_DONE}, + {VPU_MSG_ID_BUF_RST, VID_API_EVENT_STR_BUF_RST}, + {VPU_MSG_ID_PIC_EOS, VID_API_EVENT_FINISHED}, + {VPU_MSG_ID_SEQ_HDR_FOUND, VID_API_EVENT_SEQ_HDR_FOUND}, + {VPU_MSG_ID_RES_CHANGE, VID_API_EVENT_RES_CHANGE}, + {VPU_MSG_ID_PIC_HDR_FOUND, VID_API_EVENT_PIC_HDR_FOUND}, + {VPU_MSG_ID_PIC_DECODED, VID_API_EVENT_PIC_DECODED}, + {VPU_MSG_ID_DEC_DONE, VID_API_EVENT_FRAME_BUFF_RDY}, + {VPU_MSG_ID_FRAME_REQ, VID_API_EVENT_REQ_FRAME_BUFF}, + {VPU_MSG_ID_FRAME_RELEASE, VID_API_EVENT_REL_FRAME_BUFF}, + {VPU_MSG_ID_FIFO_LOW, VID_API_EVENT_FIFO_LOW}, + {VPU_MSG_ID_BS_ERROR, VID_API_EVENT_BS_ERROR}, + {VPU_MSG_ID_UNSUPPORTED, VID_API_EVENT_UNSUPPORTED_STREAM}, + {VPU_MSG_ID_FIRMWARE_XCPT, VID_API_EVENT_FIRMWARE_XCPT}, +}; + +static void vpu_malone_pack_fs_alloc(struct vpu_rpc_event *pkt, + struct vpu_fs_info *fs) +{ + const u32 fs_type[] = { + [MEM_RES_FRAME] = 0, + [MEM_RES_MBI] = 1, + [MEM_RES_DCP] = 2, + }; + + pkt->hdr.num = 7; + pkt->data[0] = fs->id | (fs->tag << 24); + pkt->data[1] = fs->luma_addr; + if (fs->type == MEM_RES_FRAME) { + /* + * if luma_addr equal to chroma_addr, + * means luma(plane[0]) and chromau(plane[1]) used the + * same fd -- usage of NXP codec2. Need to manually + * offset chroma addr. + */ + if (fs->luma_addr == fs->chroma_addr) + fs->chroma_addr = fs->luma_addr + fs->luma_size; + pkt->data[2] = fs->luma_addr + fs->luma_size / 2; + pkt->data[3] = fs->chroma_addr; + pkt->data[4] = fs->chroma_addr + fs->chromau_size / 2; + pkt->data[5] = fs->bytesperline; + } else { + pkt->data[2] = fs->luma_size; + pkt->data[3] = 0; + pkt->data[4] = 0; + pkt->data[5] = 0; + } + pkt->data[6] = fs_type[fs->type]; +} + +static void vpu_malone_pack_fs_release(struct vpu_rpc_event *pkt, + struct vpu_fs_info *fs) +{ + pkt->hdr.num = 1; + pkt->data[0] = fs->id | (fs->tag << 24); +} + +static void vpu_malone_pack_timestamp(struct vpu_rpc_event *pkt, + struct vpu_ts_info *info) +{ + pkt->hdr.num = 3; + if (info->timestamp < 0) { + pkt->data[0] = (u32)-1; + pkt->data[1] = 0; + } else { + pkt->data[0] = info->timestamp / NSEC_PER_SEC; + pkt->data[1] = info->timestamp % NSEC_PER_SEC; + } + pkt->data[2] = info->size; +} + +int vpu_malone_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data) +{ + int ret; + + WARN_ON(!pkt); + + ret = vpu_find_dst_by_src(malone_cmds, ARRAY_SIZE(malone_cmds), id); + if (ret < 0) + return ret; + + pkt->hdr.id = ret; + pkt->hdr.num = 0; + pkt->hdr.index = index; + + switch (id) { + case VPU_CMD_ID_FS_ALLOC: + vpu_malone_pack_fs_alloc(pkt, data); + break; + case VPU_CMD_ID_FS_RELEASE: + vpu_malone_pack_fs_release(pkt, data); + break; + case VPU_CMD_ID_TIMESTAMP: + vpu_malone_pack_timestamp(pkt, data); + break; + } + + pkt->hdr.index = index; + return 0; +} + +int vpu_malone_convert_msg_id(u32 id) +{ + return vpu_find_src_by_dst(malone_msgs, ARRAY_SIZE(malone_msgs), id); +} + +static void vpu_malone_fill_planes(struct vpu_dec_codec_info *info) +{ + u32 interlaced = info->progressive ? 0 : 1; + + info->sizeimage[0] = vpu_helper_get_plane_size(info->pixfmt, + info->decoded_width, info->decoded_height, + 0, info->stride, interlaced, + &info->bytesperline[0]); + info->sizeimage[1] = vpu_helper_get_plane_size(info->pixfmt, + info->decoded_width, info->decoded_height, + 1, info->stride, interlaced, + &info->bytesperline[1]); +} + +static void vpu_malone_init_seq_hdr(struct vpu_dec_codec_info *info) +{ + u32 chunks = info->num_dfe_area >> MALONE_DCP_CHUNK_BIT; + + vpu_malone_fill_planes(info); + + info->mbi_size = (info->sizeimage[0] + info->sizeimage[1]) >> 2; + info->mbi_size = ALIGN(info->mbi_size, MALONE_ALIGN_MBI); + + info->dcp_size = MALONE_DCP_SIZE_MAX; + if (chunks) { + u32 mb_num; + u32 mb_w; + u32 mb_h; + + mb_w = DIV_ROUND_UP(info->decoded_width, 16); + mb_h = DIV_ROUND_UP(info->decoded_height, 16); + mb_num = mb_w * mb_h; + info->dcp_size = mb_num * MALONE_DCP_FIXED_MB_ALLOC * chunks; + info->dcp_size = clamp_t(u32, info->dcp_size, + MALONE_DCP_SIZE_MIN, MALONE_DCP_SIZE_MAX); + } +} + +static void vpu_malone_unpack_seq_hdr(struct vpu_rpc_event *pkt, + struct vpu_dec_codec_info *info) +{ + info->num_ref_frms = pkt->data[0]; + info->num_dpb_frms = pkt->data[1]; + info->num_dfe_area = pkt->data[2]; + info->progressive = pkt->data[3]; + info->width = pkt->data[5]; + info->height = pkt->data[4]; + info->decoded_width = pkt->data[12]; + info->decoded_height = pkt->data[11]; + info->frame_rate = pkt->data[8]; + info->dsp_asp_ratio = pkt->data[9]; + info->level_idc = pkt->data[10]; + info->bit_depth_luma = pkt->data[13]; + info->bit_depth_chroma = pkt->data[14]; + info->chroma_fmt = pkt->data[15]; + info->color_primaries = vpu_color_cvrt_primaries_i2v(pkt->data[16]); + info->transfer_chars = vpu_color_cvrt_transfers_i2v(pkt->data[17]); + info->matrix_coeffs = vpu_color_cvrt_matrix_i2v(pkt->data[18]); + info->full_range = vpu_color_cvrt_full_range_i2v(pkt->data[19]); + info->vui_present = pkt->data[20]; + info->mvc_num_views = pkt->data[21]; + info->offset_x = pkt->data[23]; + info->offset_y = pkt->data[25]; + info->tag = pkt->data[27]; + if (info->bit_depth_luma > 8) + info->pixfmt = V4L2_PIX_FMT_NV12_10BE_8L128; + else + info->pixfmt = V4L2_PIX_FMT_NV12_8L128; + vpu_malone_init_seq_hdr(info); +} + +static void vpu_malone_unpack_pic_info(struct vpu_rpc_event *pkt, + struct vpu_dec_pic_info *info) +{ + info->id = pkt->data[7]; + info->luma = pkt->data[0]; + info->start = pkt->data[10]; + info->end = pkt->data[12]; + info->pic_size = pkt->data[11]; + info->stride = pkt->data[5]; + info->consumed_count = pkt->data[13]; + if (info->id == MALONE_SKIPPED_FRAME_ID) + info->skipped = 1; + else + info->skipped = 0; +} + +static void vpu_malone_unpack_req_frame(struct vpu_rpc_event *pkt, + struct vpu_fs_info *info) +{ + info->type = pkt->data[1]; +} + +static void vpu_malone_unpack_rel_frame(struct vpu_rpc_event *pkt, + struct vpu_fs_info *info) +{ + info->id = pkt->data[0]; + info->type = pkt->data[1]; + info->not_displayed = pkt->data[2]; +} + +static void vpu_malone_unpack_buff_rdy(struct vpu_rpc_event *pkt, + struct vpu_dec_pic_info *info) +{ + info->id = pkt->data[0]; + info->luma = pkt->data[1]; + info->stride = pkt->data[3]; + if (info->id == MALONE_SKIPPED_FRAME_ID) + info->skipped = 1; + else + info->skipped = 0; + info->timestamp = MAKE_TIMESTAMP(pkt->data[9], pkt->data[10]); +} + +int vpu_malone_unpack_msg_data(struct vpu_rpc_event *pkt, void *data) +{ + if (!pkt || !data) + return -EINVAL; + + switch (pkt->hdr.id) { + case VID_API_EVENT_SEQ_HDR_FOUND: + vpu_malone_unpack_seq_hdr(pkt, data); + break; + case VID_API_EVENT_PIC_DECODED: + vpu_malone_unpack_pic_info(pkt, data); + break; + case VID_API_EVENT_REQ_FRAME_BUFF: + vpu_malone_unpack_req_frame(pkt, data); + break; + case VID_API_EVENT_REL_FRAME_BUFF: + vpu_malone_unpack_rel_frame(pkt, data); + break; + case VID_API_EVENT_FRAME_BUFF_RDY: + vpu_malone_unpack_buff_rdy(pkt, data); + break; + } + + return 0; +} + +static const struct malone_padding_scode padding_scodes[] = { + {SCODE_PADDING_EOS, V4L2_PIX_FMT_H264, {0x0B010000, 0}}, + {SCODE_PADDING_EOS, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}}, + {SCODE_PADDING_EOS, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}}, + {SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}}, + {SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}}, + {SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG2, {0xCC010000, 0x0}}, + {SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}}, + {SCODE_PADDING_EOS, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}}, + {SCODE_PADDING_EOS, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}}, + {SCODE_PADDING_EOS, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}}, + {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0xefff0000, 0x0}}, + {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264, {0x0B010000, 0}}, + {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}}, + {SCODE_PADDING_ABORT, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}}, + {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}}, + {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}}, + {SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG2, {0xb7010000, 0x0}}, + {SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}}, + {SCODE_PADDING_ABORT, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}}, + {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}}, + {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}}, + {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0x0, 0x0}}, + {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264, {0x15010000, 0x0}}, + {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264_MVC, {0x15010000, 0x0}}, +}; +static const struct malone_padding_scode padding_scode_dft = {0x0, 0x0}; + +static const struct malone_padding_scode *get_padding_scode(u32 type, u32 fmt) +{ + const struct malone_padding_scode *s; + int i; + + for (i = 0; i < ARRAY_SIZE(padding_scodes); i++) { + s = &padding_scodes[i]; + + if (s->scode_type == type && s->pixelformat == fmt) + return s; + } + + if (type != SCODE_PADDING_BUFFLUSH) + return &padding_scode_dft; + + return NULL; +} + +static int vpu_malone_add_padding_scode(struct vpu_buffer *stream_buffer, + struct vpu_malone_str_buffer *str_buf, + u32 pixelformat, u32 scode_type) +{ + u32 wptr; + u32 size; + u32 total_size = 0; + const struct malone_padding_scode *ps; + const u32 padding_size = 4096; + int ret; + + ps = get_padding_scode(scode_type, pixelformat); + if (!ps) + return -EINVAL; + + wptr = str_buf->wptr; + size = ALIGN(wptr, 4) - wptr; + if (size) + vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size); + total_size += size; + + size = sizeof(ps->data); + ret = vpu_helper_copy_to_stream_buffer(stream_buffer, &wptr, size, (void *)ps->data); + if (ret < size) + return -EINVAL; + total_size += size; + + size = padding_size - sizeof(ps->data); + vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size); + total_size += size; + + vpu_malone_update_wptr(str_buf, wptr); + return total_size; +} + +int vpu_malone_add_scode(struct vpu_shared_addr *shared, + u32 instance, + struct vpu_buffer *stream_buffer, + u32 pixelformat, + u32 scode_type) +{ + struct vpu_dec_ctrl *hc; + struct vpu_malone_str_buffer *str_buf; + int ret = -EINVAL; + + WARN_ON(!shared || !shared->iface || !shared->core || !shared->priv); + + hc = shared->priv; + str_buf = hc->str_buf[instance]; + + switch (scode_type) { + case SCODE_PADDING_EOS: + case SCODE_PADDING_ABORT: + case SCODE_PADDING_BUFFLUSH: + ret = vpu_malone_add_padding_scode(stream_buffer, + str_buf, pixelformat, scode_type); + break; + default: + break; + } + + return ret; +} + +#define MALONE_PAYLOAD_HEADER_SIZE 16 +#define MALONE_CODEC_VERSION_ID 0x1 +#define MALONE_CODEC_ID_VC1_SIMPLE 0x10 +#define MALONE_CODEC_ID_VC1_MAIN 0x11 +#define MALONE_CODEC_ID_ARV8 0x28 +#define MALONE_CODEC_ID_ARV9 0x29 +#define MALONE_CODEC_ID_VP6 0x36 +#define MALONE_CODEC_ID_VP8 0x36 +#define MALONE_CODEC_ID_DIVX3 0x38 +#define MALONE_CODEC_ID_SPK 0x39 + +#define MALONE_VP8_IVF_SEQ_HEADER_LEN 32 +#define MALONE_VP8_IVF_FRAME_HEADER_LEN 8 + +#define MALONE_VC1_RCV_CODEC_V1_VERSION 0x85 +#define MALONE_VC1_RCV_CODEC_V2_VERSION 0xC5 +#define MALONE_VC1_RCV_NUM_FRAMES 0xFF +#define MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE 4 +#define MALONE_VC1_RCV_SEQ_HEADER_LEN 20 +#define MALONE_VC1_RCV_PIC_HEADER_LEN 4 +#define MALONE_VC1_NAL_HEADER_LEN 4 +#define MALONE_VC1_CONTAIN_NAL(data) ((data & 0x00FFFFFF) == 0x00010000) + + +static void set_payload_hdr(u8 *dst, u32 scd_type, u32 codec_id, + u32 buffer_size, u32 width, u32 height) +{ + unsigned int payload_size; + /* payload_size = buffer_size + itself_size(16) - start_code(4) */ + payload_size = buffer_size + 12; + + dst[0] = 0x00; + dst[1] = 0x00; + dst[2] = 0x01; + dst[3] = scd_type; + + /* length */ + dst[4] = ((payload_size>>16)&0xff); + dst[5] = ((payload_size>>8)&0xff); + dst[6] = 0x4e; + dst[7] = ((payload_size>>0)&0xff); + + /* Codec ID and Version */ + dst[8] = codec_id; + dst[9] = MALONE_CODEC_VERSION_ID; + + /* width */ + dst[10] = ((width>>8)&0xff); + dst[11] = ((width>>0)&0xff); + dst[12] = 0x58; + + /* height */ + dst[13] = ((height>>8)&0xff); + dst[14] = ((height>>0)&0xff); + dst[15] = 0x50; +} + +static void set_vp8_ivf_seqhdr(u8 *dst, u32 width, u32 height) +{ + /* 0-3byte signature "DKIF" */ + dst[0] = 0x44; + dst[1] = 0x4b; + dst[2] = 0x49; + dst[3] = 0x46; + /* 4-5byte version: should be 0*/ + dst[4] = 0x00; + dst[5] = 0x00; + /* 6-7 length of Header */ + dst[6] = MALONE_VP8_IVF_SEQ_HEADER_LEN; + dst[7] = MALONE_VP8_IVF_SEQ_HEADER_LEN >> 8; + /* 8-11 VP8 fourcc */ + dst[8] = 0x56; + dst[9] = 0x50; + dst[10] = 0x38; + dst[11] = 0x30; + /* 12-13 width in pixels */ + dst[12] = width; + dst[13] = width >> 8; + /* 14-15 height in pixels */ + dst[14] = height; + dst[15] = height >> 8; + /* 16-19 frame rate */ + dst[16] = 0xe8; + dst[17] = 0x03; + dst[18] = 0x00; + dst[19] = 0x00; + /* 20-23 time scale */ + dst[20] = 0x01; + dst[21] = 0x00; + dst[22] = 0x00; + dst[23] = 0x00; + /* 24-27 number frames */ + dst[24] = 0xdf; + dst[25] = 0xf9; + dst[26] = 0x09; + dst[27] = 0x00; + /* 28-31 reserved */ +} + +static void set_vp8_ivf_pichdr(u8 *dst, u32 frame_size) +{ + /* + * firmware just parse 64-bit timestamp(8 bytes). + * As not transfer timestamp to firmware, use default value(ZERO). + * No need to do anything here + */ +} + +static void set_vc1_rcv_seqhdr(u8 *dst, u8 *src, u32 width, u32 height) +{ + u32 frames = MALONE_VC1_RCV_NUM_FRAMES; + u32 ext_data_size = MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE; + + /* 0-2 Number of frames, used default value 0xFF */ + dst[0] = frames; + dst[1] = frames >> 8; + dst[2] = frames >> 16; + + /* 3 RCV version, used V1 */ + dst[3] = MALONE_VC1_RCV_CODEC_V1_VERSION; + + /* 4-7 extension data size */ + dst[4] = ext_data_size; + dst[5] = ext_data_size >> 8; + dst[6] = ext_data_size >> 16; + dst[7] = ext_data_size >> 24; + /* 8-11 extension data */ + dst[8] = src[0]; + dst[9] = src[1]; + dst[10] = src[2]; + dst[11] = src[3]; + + /* height */ + dst[12] = height; + dst[13] = (height >> 8) & 0xff; + dst[14] = (height >> 16) & 0xff; + dst[15] = (height >> 24) & 0xff; + /* width */ + dst[16] = width; + dst[17] = (width >> 8) & 0xff; + dst[18] = (width >> 16) & 0xff; + dst[19] = (width >> 24) & 0xff; +} + +static void set_vc1_rcv_pichdr(u8 *dst, u32 buffer_size) +{ + dst[0] = buffer_size; + dst[1] = buffer_size >> 8; + dst[2] = buffer_size >> 16; + dst[3] = buffer_size >> 24; +} + +static void create_vc1_nal_pichdr(u8 *dst) +{ + /* need insert nal header: special ID */ + dst[0] = 0x0; + dst[1] = 0x0; + dst[2] = 0x01; + dst[3] = 0x0D; +} + +static int vpu_malone_insert_scode_seq(struct malone_scode_t *scode, u32 codec_id, u32 ext_size) +{ + u8 hdr[MALONE_PAYLOAD_HEADER_SIZE]; + int ret; + + set_payload_hdr(hdr, + SCODE_SEQUENCE, + codec_id, + ext_size, + scode->inst->out_format.width, + scode->inst->out_format.height); + ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, + &scode->wptr, + sizeof(hdr), + hdr); + return ret; +} + +static int vpu_malone_insert_scode_pic(struct malone_scode_t *scode, u32 codec_id, u32 ext_size) +{ + u8 hdr[MALONE_PAYLOAD_HEADER_SIZE]; + + set_payload_hdr(hdr, + SCODE_PICTURE, + codec_id, + ext_size + vb2_get_plane_payload(scode->vb, 0), + scode->inst->out_format.width, + scode->inst->out_format.height); + return vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, + &scode->wptr, + sizeof(hdr), + hdr); +} + +static int vpu_malone_insert_scode_vc1_g_pic(struct malone_scode_t *scode) +{ + struct vb2_v4l2_buffer *vbuf; + u8 nal_hdr[MALONE_VC1_NAL_HEADER_LEN]; + u32 *data = NULL; + + vbuf = to_vb2_v4l2_buffer(scode->vb); + data = vb2_plane_vaddr(scode->vb, 0); + + if (vbuf->sequence == 0 || (vbuf->flags & V4L2_BUF_FLAG_CODECCONFIG)) + return 0; + if (MALONE_VC1_CONTAIN_NAL(*data)) + return 0; + + create_vc1_nal_pichdr(nal_hdr); + return vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, + &scode->wptr, + sizeof(nal_hdr), + nal_hdr); +} + +static int vpu_malone_insert_scode_vc1_l_seq(struct malone_scode_t *scode) +{ + int ret; + int size = 0; + u8 rcv_seqhdr[MALONE_VC1_RCV_SEQ_HEADER_LEN]; + + scode->need_data = 0; + + ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VC1_SIMPLE, + sizeof(rcv_seqhdr)); + if (ret < 0) + return ret; + size = ret; + + set_vc1_rcv_seqhdr(rcv_seqhdr, + vb2_plane_vaddr(scode->vb, 0), + scode->inst->out_format.width, + scode->inst->out_format.height); + ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, + &scode->wptr, + sizeof(rcv_seqhdr), + rcv_seqhdr); + + if (ret < 0) + return ret; + size += ret; + return size; +} + +static int vpu_malone_insert_scode_vc1_l_pic(struct malone_scode_t *scode) +{ + int ret; + int size = 0; + u8 rcv_pichdr[MALONE_VC1_RCV_PIC_HEADER_LEN]; + + ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VC1_SIMPLE, + sizeof(rcv_pichdr)); + if (ret < 0) + return ret; + size = ret; + + set_vc1_rcv_pichdr(rcv_pichdr, vb2_get_plane_payload(scode->vb, 0)); + ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, + &scode->wptr, + sizeof(rcv_pichdr), + rcv_pichdr); + if (ret < 0) + return ret; + size += ret; + return size; +} + +static int vpu_malone_insert_scode_vp8_seq(struct malone_scode_t *scode) +{ + int ret; + int size = 0; + u8 ivf_hdr[MALONE_VP8_IVF_SEQ_HEADER_LEN]; + + ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr)); + if (ret < 0) + return ret; + size = ret; + + set_vp8_ivf_seqhdr(ivf_hdr, + scode->inst->out_format.width, + scode->inst->out_format.height); + ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, + &scode->wptr, + sizeof(ivf_hdr), + ivf_hdr); + if (ret < 0) + return ret; + size += ret; + + return size; +} + +static int vpu_malone_insert_scode_vp8_pic(struct malone_scode_t *scode) +{ + int ret; + int size = 0; + u8 ivf_hdr[MALONE_VP8_IVF_FRAME_HEADER_LEN] = {0}; + + ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr)); + if (ret < 0) + return ret; + size = ret; + + set_vp8_ivf_pichdr(ivf_hdr, vb2_get_plane_payload(scode->vb, 0)); + ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, + &scode->wptr, + sizeof(ivf_hdr), + ivf_hdr); + if (ret < 0) + return ret; + size += ret; + + return size; +} + +static const struct malone_scode_handler scode_handlers[] = { + { + /* fix me, need to swap return operation after gstreamer swap */ + .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_L, + .insert_scode_seq = vpu_malone_insert_scode_vc1_l_seq, + .insert_scode_pic = vpu_malone_insert_scode_vc1_l_pic, + }, + { + .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_G, + .insert_scode_pic = vpu_malone_insert_scode_vc1_g_pic, + }, + { + .pixelformat = V4L2_PIX_FMT_VP8, + .insert_scode_seq = vpu_malone_insert_scode_vp8_seq, + .insert_scode_pic = vpu_malone_insert_scode_vp8_pic, + }, +}; + +static const struct malone_scode_handler *get_scode_handler(u32 pixelformat) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(scode_handlers); i++) { + if (scode_handlers[i].pixelformat == pixelformat) + return &scode_handlers[i]; + } + + return NULL; +} + +static int vpu_malone_insert_scode(struct malone_scode_t *scode, u32 type) +{ + const struct malone_scode_handler *handler; + int ret = 0; + + if (!scode || !scode->inst || !scode->vb) + return 0; + + scode->need_data = 1; + handler = get_scode_handler(scode->inst->out_format.pixfmt); + if (!handler) + return 0; + + switch (type) { + case SCODE_SEQUENCE: + if (handler->insert_scode_seq) + ret = handler->insert_scode_seq(scode); + break; + case SCODE_PICTURE: + if (handler->insert_scode_pic) + ret = handler->insert_scode_pic(scode); + break; + default: + break; + } + + return ret; +} + +static int vpu_malone_input_frame_data(struct vpu_malone_str_buffer *str_buf, + struct vpu_inst *inst, struct vb2_buffer *vb, + u32 disp_imm) +{ + struct malone_scode_t scode; + struct vb2_v4l2_buffer *vbuf; + u32 wptr; + int size = 0; + int ret = 0; + + wptr = str_buf->wptr; + + /*add scode: SCODE_SEQUENCE, SCODE_PICTURE, SCODE_SLICE*/ + vbuf = to_vb2_v4l2_buffer(vb); + scode.inst = inst; + scode.vb = vb; + scode.wptr = wptr; + scode.need_data = 1; + if (vbuf->sequence == 0 || (vbuf->flags & V4L2_BUF_FLAG_CODECCONFIG)) + ret = vpu_malone_insert_scode(&scode, SCODE_SEQUENCE); + + if (ret < 0) + return -ENOMEM; + size += ret; + wptr = scode.wptr; + if (!scode.need_data) { + vpu_malone_update_wptr(str_buf, wptr); + return size; + } + + ret = vpu_malone_insert_scode(&scode, SCODE_PICTURE); + if (ret < 0) + return -ENOMEM; + size += ret; + wptr = scode.wptr; + + ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer, + &wptr, + vb2_get_plane_payload(vb, 0), + vb2_plane_vaddr(vb, 0)); + if (ret < vb2_get_plane_payload(vb, 0)) + return -ENOMEM; + size += ret; + + vpu_malone_update_wptr(str_buf, wptr); + + if (disp_imm && !(vbuf->flags & V4L2_BUF_FLAG_CODECCONFIG)) { + ret = vpu_malone_add_scode(inst->core->iface, + inst->id, + &inst->stream_buffer, + inst->out_format.pixfmt, + SCODE_PADDING_BUFFLUSH); + if (ret < 0) + return ret; + size += ret; + } + + return size; +} + +static int vpu_malone_input_stream_data(struct vpu_malone_str_buffer *str_buf, + struct vpu_inst *inst, struct vb2_buffer *vb) +{ + u32 wptr; + int ret = 0; + + wptr = str_buf->wptr; + ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer, + &wptr, + vb2_get_plane_payload(vb, 0), + vb2_plane_vaddr(vb, 0)); + if (ret < vb2_get_plane_payload(vb, 0)) + return -ENOMEM; + + vpu_malone_update_wptr(str_buf, wptr); + + return ret; +} + +static int vpu_malone_input_ts(struct vpu_inst *inst, s64 timestamp, u32 size) +{ + struct vpu_ts_info info; + + memset(&info, 0, sizeof(info)); + info.timestamp = timestamp; + info.size = size; + + return vpu_session_fill_timestamp(inst, &info); +} + +int vpu_malone_input_frame(struct vpu_shared_addr *shared, + struct vpu_inst *inst, struct vb2_buffer *vb) +{ + struct vpu_dec_ctrl *hc; + struct vb2_v4l2_buffer *vbuf; + struct vpu_malone_str_buffer *str_buf; + u32 disp_imm = 0; + u32 size; + int ret; + + WARN_ON(!shared || !shared->iface || !shared->core || !shared->priv); + hc = shared->priv; + str_buf = hc->str_buf[inst->id]; + disp_imm = hc->codec_param[inst->id].disp_imm; + + if (vpu_malone_is_non_frame_mode(shared, inst->id)) + ret = vpu_malone_input_stream_data(str_buf, inst, vb); + else + ret = vpu_malone_input_frame_data(str_buf, inst, vb, disp_imm); + if (ret < 0) + return ret; + size = ret; + + /* + * if buffer only contain codec data, and the timestamp is invalid, + * don't put the invalid timestamp to resync + * merge the data to next frame + */ + vbuf = to_vb2_v4l2_buffer(vb); + if ((vbuf->flags & V4L2_BUF_FLAG_CODECCONFIG) && (s64)vb->timestamp < 0) { + inst->extra_size += size; + return 0; + } + if (inst->extra_size) { + size += inst->extra_size; + inst->extra_size = 0; + } + + ret = vpu_malone_input_ts(inst, vb->timestamp, size); + if (ret) + return ret; + + return 0; +} + +static bool vpu_malone_check_ready(struct vpu_shared_addr *shared, u32 instance) +{ + struct malone_iface *iface; + struct vpu_rpc_buffer_desc *desc; + u32 size; + u32 rptr; + u32 wptr; + u32 used; + + iface = shared->iface; + desc = &iface->api_cmd_buffer_desc[instance]; + size = desc->end - desc->start; + rptr = desc->rptr; + wptr = desc->wptr; + used = (wptr + size - rptr) % size; + if (!size || used < size / 2) + return true; + + vpu_dbg(LVL_DEBUG, "[%d]api cmd used = %d/%d\n", instance, used, size); + + return false; +} + +bool vpu_malone_is_ready(struct vpu_shared_addr *shared, u32 instance) +{ + u32 cnt = 0; + + while (!vpu_malone_check_ready(shared, instance)) { + if (cnt > 30) + return false; + mdelay(1); + cnt++; + } + return true; +} + +int vpu_malone_pre_cmd(struct vpu_shared_addr *shared, u32 instance) +{ + if (!vpu_malone_is_ready(shared, instance)) { + vpu_err("[%d] is not ready\n", instance); + return -EINVAL; + } + + return 0; +} + +int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance) +{ + struct malone_iface *iface; + struct vpu_rpc_buffer_desc *desc; + + iface = shared->iface; + desc = &iface->api_cmd_buffer_desc[instance]; + desc->wptr++; + if (desc->wptr == desc->end) + desc->wptr = desc->start; + + return 0; +} + +int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance) +{ + struct malone_iface *iface; + struct vpu_rpc_buffer_desc *desc; + + iface = shared->iface; + desc = &iface->api_cmd_buffer_desc[instance]; + desc->wptr = desc->rptr; + if (desc->wptr == desc->end) + desc->wptr = desc->start; + + return 0; +} + +u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared) +{ + struct malone_iface *iface = shared->iface; + + return iface->max_streams; +} diff --git a/drivers/media/platform/amphion/vpu_malone.h b/drivers/media/platform/amphion/vpu_malone.h new file mode 100644 index 000000000000..4699252fc73c --- /dev/null +++ b/drivers/media/platform/amphion/vpu_malone.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2020-2021 NXP + */ + +#ifndef _AMPHION_VPU_MALONE_H +#define _AMPHION_VPU_MALONE_H + +u32 vpu_malone_get_data_size(void); +void vpu_malone_init_rpc(struct vpu_shared_addr *shared, + struct vpu_buffer *rpc, dma_addr_t boot_addr); +void vpu_malone_set_log_buf(struct vpu_shared_addr *shared, + struct vpu_buffer *log); +void vpu_malone_set_system_cfg(struct vpu_shared_addr *shared, + u32 regs_base, void __iomem *regs, u32 core_id); +u32 vpu_malone_get_version(struct vpu_shared_addr *shared); +int vpu_malone_get_stream_buffer_size(struct vpu_shared_addr *shared); +int vpu_malone_config_stream_buffer(struct vpu_shared_addr *shared, + u32 instance, struct vpu_buffer *buf); +int vpu_malone_get_stream_buffer_desc(struct vpu_shared_addr *shared, + u32 instance, struct vpu_rpc_buffer_desc *desc); +int vpu_malone_update_stream_buffer(struct vpu_shared_addr *shared, + u32 instance, u32 ptr, bool write); +int vpu_malone_set_decode_params(struct vpu_shared_addr *shared, + u32 instance, struct vpu_decode_params *params, u32 update); +int vpu_malone_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data); +int vpu_malone_convert_msg_id(u32 msg_id); +int vpu_malone_unpack_msg_data(struct vpu_rpc_event *pkt, void *data); +int vpu_malone_add_scode(struct vpu_shared_addr *shared, + u32 instance, + struct vpu_buffer *stream_buffer, + u32 pixelformat, + u32 scode_type); +int vpu_malone_input_frame(struct vpu_shared_addr *shared, + struct vpu_inst *inst, struct vb2_buffer *vb); +bool vpu_malone_is_ready(struct vpu_shared_addr *shared, u32 instance); +int vpu_malone_pre_cmd(struct vpu_shared_addr *shared, u32 instance); +int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance); +int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance); +u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared); + +#endif From patchwork Tue Sep 7 09:49:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Qian X-Patchwork-Id: 507649 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF464C433FE for ; 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Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- .../arm64/boot/dts/freescale/imx8-ss-vpu.dtsi | 72 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 17 +++++ arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 24 +++++++ 3 files changed, 113 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi new file mode 100644 index 000000000000..f2dde6d14ca3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + * Dong Aisheng + */ + +vpu: vpu@2c000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x2c000000 0x0 0x2c000000 0x2000000>; + reg = <0 0x2c000000 0 0x1000000>; + power-domains = <&pd IMX_SC_R_VPU>; + status = "disabled"; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + status = "okay"; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + status = "okay"; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + status = "disabled"; + }; + + vpu_core0: vpu_core@2d080000 { + reg = <0x2d080000 0x10000>; + compatible = "nxp,imx8q-vpu-decoder"; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0>, + <&mu_m0 0 1>, + <&mu_m0 1 0>; + status = "disabled"; + }; + vpu_core1: vpu_core@2d090000 { + reg = <0x2d090000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu1_m0 0 0>, + <&mu1_m0 0 1>, + <&mu1_m0 1 0>; + status = "disabled"; + }; + vpu_core2: vpu_core@2d0a0000 { + reg = <0x2d0a0000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu2_m0 0 0>, + <&mu2_m0 0 1>, + <&mu2_m0 1 0>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 863232a47004..05495b60beb8 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -196,6 +196,23 @@ &usdhc2 { status = "okay"; }; +&vpu { + compatible = "nxp,imx8qxp-vpu"; + status = "okay"; +}; + +&vpu_core0 { + reg = <0x2d040000 0x10000>; + memory-region = <&decoder_boot>, <&decoder_rpc>; + status = "okay"; +}; + +&vpu_core1 { + reg = <0x2d050000 0x10000>; + memory-region = <&encoder_boot>, <&encoder_rpc>; + status = "okay"; +}; + &iomuxc { pinctrl_fec1: fec1grp { fsl,pins = < diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 1e6b4995091e..6b421cfa5534 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -46,6 +46,9 @@ aliases { serial1 = &lpuart1; serial2 = &lpuart2; serial3 = &lpuart3; + vpu_core0 = &vpu_core0; + vpu_core1 = &vpu_core1; + vpu_core2 = &vpu_core2; }; cpus { @@ -134,10 +137,30 @@ reserved-memory { #size-cells = <2>; ranges; + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@0x92000000 { + reg = <0 0x92000000 0 0x100000>; + no-map; + }; + dsp_reserved: dsp@92400000 { reg = <0 0x92400000 0 0x2000000>; no-map; }; + + encoder_rpc: encoder-rpc@0x94400000 { + reg = <0 0x94400000 0 0x700000>; + no-map; + }; }; pmu { @@ -258,6 +281,7 @@ map0 { }; /* sorted in register address */ + #include "imx8-ss-vpu.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi" From patchwork Tue Sep 7 09:49:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Qian X-Patchwork-Id: 507648 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C0A5C433FE for ; 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